2006.160.07:04:40.73;Log Opened: Mark IV Field System Version 9.7.7 2006.160.07:04:40.73;location,TSUKUB32,-140.09,36.10,61.0 2006.160.07:04:40.73;horizon1,0.,5.,360. 2006.160.07:04:40.73;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.160.07:04:40.73;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.160.07:04:40.73;drivev11,330,270,no 2006.160.07:04:40.73;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.160.07:04:40.73;drivev13,15.000,268,10.000,10.000,10.000 2006.160.07:04:40.73;drivev21,330,270,no 2006.160.07:04:40.73;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.160.07:04:40.73;drivev23,15.000,268,10.000,10.000,10.000 2006.160.07:04:40.73;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.160.07:04:40.73;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.160.07:04:40.73;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.160.07:04:40.73;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.160.07:04:40.73;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.160.07:04:40.73;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.160.07:04:40.73;time,-0.364,101.533,rate 2006.160.07:04:40.73;flagr,200 2006.160.07:04:40.73:" K06161 2006 TSUKUB32 T Ts 2006.160.07:04:40.73:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.160.07:04:40.73:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.160.07:04:40.73:" 108 TSUKUB32 14 17400 2006.160.07:04:40.73:" drudg version 050216 compiled under FS 9.7.07 2006.160.07:04:40.73:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.160.07:04:40.73:exper_initi 2006.160.07:04:40.73&exper_initi/proc_library 2006.160.07:04:40.73&exper_initi/sched_initi 2006.160.07:04:40.73:!2006.161.07:19:50 2006.160.07:04:40.73&proc_library/" k06161 tsukub32 ts 2006.160.07:04:40.73&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.160.07:04:40.73&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.160.07:04:40.73&sched_initi/startcheck 2006.160.07:04:40.73&startcheck/sy=check_fsrun.pl & 2006.160.07:04:40.73&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.160.07:04:53.34;cable 2006.160.07:04:53.44/cable/+6.5393E-03 2006.160.07:05:37.13;cablelong 2006.160.07:05:37.21/cablelong/+7.0831E-03 2006.160.07:05:41.42;cablediff 2006.160.07:05:41.42/cablediff/543.8e-6,+ 2006.160.07:06:18.25;cable 2006.160.07:06:18.36/cable/+6.5393E-03 2006.160.07:06:34.38;wx 2006.160.07:06:34.38/wx/18.67,989.0,100 2006.160.07:06:47.33;"Sky is rainy. 2006.160.07:06:52.76;xfe 2006.160.07:06:52.85/xfe/off,on,14.7 2006.160.07:06:58.63;clockoff 2006.160.07:06:58.63&clockoff/"gps-fmout=1p 2006.160.07:06:58.63&clockoff/fmout-gps=1p 2006.160.07:06:59.07/fmout-gps/S +4.53E-07 2006.161.07:19:50.00:unstow 2006.161.07:19:50.00&unstow/antenna=e 2006.161.07:19:50.00&unstow/!+10s 2006.161.07:19:50.00&unstow/antenna=m2 2006.161.07:20:02.01:scan_name=161-0730,k06161,60 2006.161.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.161.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.161.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.161.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.161.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.161.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.161.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.161.07:20:03.14:ready_k5 2006.161.07:20:03.14&ready_k5/obsinfo=st 2006.161.07:20:03.14&ready_k5/autoobs=1 2006.161.07:20:03.14&ready_k5/autoobs=2 2006.161.07:20:03.14&ready_k5/autoobs=3 2006.161.07:20:03.14&ready_k5/autoobs=4 2006.161.07:20:03.14&ready_k5/obsinfo 2006.161.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.161.07:20:03.14#flagr#flagr/antenna,new-source 2006.161.07:20:06.78/autoobs//k5ts1/ autoobs started! 2006.161.07:20:10.47/autoobs//k5ts2/ autoobs started! 2006.161.07:20:14.15/autoobs//k5ts3/ autoobs started! 2006.161.07:20:17.98/autoobs//k5ts4/ autoobs started! 2006.161.07:20:18.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:20:18.01:4f8m12a=1 2006.161.07:20:18.01&4f8m12a/xlog=on 2006.161.07:20:18.01&4f8m12a/echo=on 2006.161.07:20:18.01&4f8m12a/pcalon 2006.161.07:20:18.01&4f8m12a/"tpicd=stop 2006.161.07:20:18.01&4f8m12a/vc4f8 2006.161.07:20:18.01&4f8m12a/ifd4f 2006.161.07:20:18.01&4f8m12a/"form=m,16.000,1:2 2006.161.07:20:18.01&4f8m12a/"tpicd 2006.161.07:20:18.01&4f8m12a/echo=off 2006.161.07:20:18.01&4f8m12a/xlog=off 2006.161.07:20:18.01$4f8m12a/echo=on 2006.161.07:20:18.01$4f8m12a/pcalon 2006.161.07:20:18.01&pcalon/"no phase cal control is implemented here 2006.161.07:20:18.01$pcalon/"no phase cal control is implemented here 2006.161.07:20:18.01$4f8m12a/"tpicd=stop 2006.161.07:20:18.01$4f8m12a/vc4f8 2006.161.07:20:18.01&vc4f8/valo=1,532.99 2006.161.07:20:18.01&vc4f8/va=1,8 2006.161.07:20:18.01&vc4f8/valo=2,572.99 2006.161.07:20:18.01&vc4f8/va=2,7 2006.161.07:20:18.01&vc4f8/valo=3,672.99 2006.161.07:20:18.01&vc4f8/va=3,6 2006.161.07:20:18.01&vc4f8/valo=4,832.99 2006.161.07:20:18.01&vc4f8/va=4,7 2006.161.07:20:18.01&vc4f8/valo=5,652.99 2006.161.07:20:18.01&vc4f8/va=5,7 2006.161.07:20:18.01&vc4f8/valo=6,772.99 2006.161.07:20:18.01&vc4f8/va=6,6 2006.161.07:20:18.01&vc4f8/valo=7,832.99 2006.161.07:20:18.01&vc4f8/va=7,6 2006.161.07:20:18.01&vc4f8/valo=8,852.99 2006.161.07:20:18.01&vc4f8/va=8,7 2006.161.07:20:18.01&vc4f8/vblo=1,632.99 2006.161.07:20:18.01&vc4f8/vb=1,4 2006.161.07:20:18.01&vc4f8/vblo=2,640.99 2006.161.07:20:18.01&vc4f8/vb=2,4 2006.161.07:20:18.01&vc4f8/vblo=3,656.99 2006.161.07:20:18.01&vc4f8/vb=3,4 2006.161.07:20:18.01&vc4f8/vblo=4,712.99 2006.161.07:20:18.01&vc4f8/vb=4,4 2006.161.07:20:18.01&vc4f8/vblo=5,744.99 2006.161.07:20:18.01&vc4f8/vb=5,4 2006.161.07:20:18.01&vc4f8/vblo=6,752.99 2006.161.07:20:18.01&vc4f8/vb=6,4 2006.161.07:20:18.01&vc4f8/vabw=wide 2006.161.07:20:18.01&vc4f8/vbbw=wide 2006.161.07:20:18.01$vc4f8/valo=1,532.99 2006.161.07:20:18.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:20:18.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:20:18.02#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:18.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:18.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:18.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:18.02#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:20:18.02#ibcon#first serial, iclass 40, count 0 2006.161.07:20:18.02#ibcon#enter sib2, iclass 40, count 0 2006.161.07:20:18.02#ibcon#flushed, iclass 40, count 0 2006.161.07:20:18.02#ibcon#about to write, iclass 40, count 0 2006.161.07:20:18.02#ibcon#wrote, iclass 40, count 0 2006.161.07:20:18.02#ibcon#about to read 3, iclass 40, count 0 2006.161.07:20:18.06#ibcon#read 3, iclass 40, count 0 2006.161.07:20:18.06#ibcon#about to read 4, iclass 40, count 0 2006.161.07:20:18.06#ibcon#read 4, iclass 40, count 0 2006.161.07:20:18.06#ibcon#about to read 5, iclass 40, count 0 2006.161.07:20:18.06#ibcon#read 5, iclass 40, count 0 2006.161.07:20:18.06#ibcon#about to read 6, iclass 40, count 0 2006.161.07:20:18.06#ibcon#read 6, iclass 40, count 0 2006.161.07:20:18.06#ibcon#end of sib2, iclass 40, count 0 2006.161.07:20:18.06#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:20:18.06#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:20:18.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:20:18.06#ibcon#*before write, iclass 40, count 0 2006.161.07:20:18.06#ibcon#enter sib2, iclass 40, count 0 2006.161.07:20:18.06#ibcon#flushed, iclass 40, count 0 2006.161.07:20:18.06#ibcon#about to write, iclass 40, count 0 2006.161.07:20:18.06#ibcon#wrote, iclass 40, count 0 2006.161.07:20:18.06#ibcon#about to read 3, iclass 40, count 0 2006.161.07:20:18.12#ibcon#read 3, iclass 40, count 0 2006.161.07:20:18.12#ibcon#about to read 4, iclass 40, count 0 2006.161.07:20:18.12#ibcon#read 4, iclass 40, count 0 2006.161.07:20:18.12#ibcon#about to read 5, iclass 40, count 0 2006.161.07:20:18.12#ibcon#read 5, iclass 40, count 0 2006.161.07:20:18.12#ibcon#about to read 6, iclass 40, count 0 2006.161.07:20:18.12#ibcon#read 6, iclass 40, count 0 2006.161.07:20:18.12#ibcon#end of sib2, iclass 40, count 0 2006.161.07:20:18.12#ibcon#*after write, iclass 40, count 0 2006.161.07:20:18.12#ibcon#*before return 0, iclass 40, count 0 2006.161.07:20:18.12#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:18.12#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:18.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:20:18.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:20:18.12$vc4f8/va=1,8 2006.161.07:20:18.12#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:20:18.12#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:20:18.12#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:18.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:18.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:18.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:18.12#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:20:18.12#ibcon#first serial, iclass 4, count 2 2006.161.07:20:18.12#ibcon#enter sib2, iclass 4, count 2 2006.161.07:20:18.12#ibcon#flushed, iclass 4, count 2 2006.161.07:20:18.12#ibcon#about to write, iclass 4, count 2 2006.161.07:20:18.12#ibcon#wrote, iclass 4, count 2 2006.161.07:20:18.12#ibcon#about to read 3, iclass 4, count 2 2006.161.07:20:18.14#ibcon#read 3, iclass 4, count 2 2006.161.07:20:18.14#ibcon#about to read 4, iclass 4, count 2 2006.161.07:20:18.14#ibcon#read 4, iclass 4, count 2 2006.161.07:20:18.14#ibcon#about to read 5, iclass 4, count 2 2006.161.07:20:18.14#ibcon#read 5, iclass 4, count 2 2006.161.07:20:18.14#ibcon#about to read 6, iclass 4, count 2 2006.161.07:20:18.14#ibcon#read 6, iclass 4, count 2 2006.161.07:20:18.14#ibcon#end of sib2, iclass 4, count 2 2006.161.07:20:18.14#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:20:18.14#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:20:18.14#ibcon#[25=AT01-08\r\n] 2006.161.07:20:18.14#ibcon#*before write, iclass 4, count 2 2006.161.07:20:18.14#ibcon#enter sib2, iclass 4, count 2 2006.161.07:20:18.14#ibcon#flushed, iclass 4, count 2 2006.161.07:20:18.14#ibcon#about to write, iclass 4, count 2 2006.161.07:20:18.14#ibcon#wrote, iclass 4, count 2 2006.161.07:20:18.14#ibcon#about to read 3, iclass 4, count 2 2006.161.07:20:18.18#ibcon#read 3, iclass 4, count 2 2006.161.07:20:18.18#ibcon#about to read 4, iclass 4, count 2 2006.161.07:20:18.18#ibcon#read 4, iclass 4, count 2 2006.161.07:20:18.18#ibcon#about to read 5, iclass 4, count 2 2006.161.07:20:18.18#ibcon#read 5, iclass 4, count 2 2006.161.07:20:18.18#ibcon#about to read 6, iclass 4, count 2 2006.161.07:20:18.18#ibcon#read 6, iclass 4, count 2 2006.161.07:20:18.18#ibcon#end of sib2, iclass 4, count 2 2006.161.07:20:18.18#ibcon#*after write, iclass 4, count 2 2006.161.07:20:18.18#ibcon#*before return 0, iclass 4, count 2 2006.161.07:20:18.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:18.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:18.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:20:18.18#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:18.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:18.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:18.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:18.30#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:20:18.30#ibcon#first serial, iclass 4, count 0 2006.161.07:20:18.30#ibcon#enter sib2, iclass 4, count 0 2006.161.07:20:18.30#ibcon#flushed, iclass 4, count 0 2006.161.07:20:18.30#ibcon#about to write, iclass 4, count 0 2006.161.07:20:18.30#ibcon#wrote, iclass 4, count 0 2006.161.07:20:18.30#ibcon#about to read 3, iclass 4, count 0 2006.161.07:20:18.32#ibcon#read 3, iclass 4, count 0 2006.161.07:20:18.32#ibcon#about to read 4, iclass 4, count 0 2006.161.07:20:18.32#ibcon#read 4, iclass 4, count 0 2006.161.07:20:18.32#ibcon#about to read 5, iclass 4, count 0 2006.161.07:20:18.32#ibcon#read 5, iclass 4, count 0 2006.161.07:20:18.32#ibcon#about to read 6, iclass 4, count 0 2006.161.07:20:18.32#ibcon#read 6, iclass 4, count 0 2006.161.07:20:18.32#ibcon#end of sib2, iclass 4, count 0 2006.161.07:20:18.32#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:20:18.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:20:18.32#ibcon#[25=USB\r\n] 2006.161.07:20:18.32#ibcon#*before write, iclass 4, count 0 2006.161.07:20:18.32#ibcon#enter sib2, iclass 4, count 0 2006.161.07:20:18.32#ibcon#flushed, iclass 4, count 0 2006.161.07:20:18.32#ibcon#about to write, iclass 4, count 0 2006.161.07:20:18.32#ibcon#wrote, iclass 4, count 0 2006.161.07:20:18.32#ibcon#about to read 3, iclass 4, count 0 2006.161.07:20:18.35#ibcon#read 3, iclass 4, count 0 2006.161.07:20:18.35#ibcon#about to read 4, iclass 4, count 0 2006.161.07:20:18.35#ibcon#read 4, iclass 4, count 0 2006.161.07:20:18.35#ibcon#about to read 5, iclass 4, count 0 2006.161.07:20:18.35#ibcon#read 5, iclass 4, count 0 2006.161.07:20:18.35#ibcon#about to read 6, iclass 4, count 0 2006.161.07:20:18.35#ibcon#read 6, iclass 4, count 0 2006.161.07:20:18.35#ibcon#end of sib2, iclass 4, count 0 2006.161.07:20:18.35#ibcon#*after write, iclass 4, count 0 2006.161.07:20:18.35#ibcon#*before return 0, iclass 4, count 0 2006.161.07:20:18.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:18.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:18.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:20:18.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:20:18.35$vc4f8/valo=2,572.99 2006.161.07:20:18.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:20:18.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:20:18.35#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:18.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:18.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:18.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:18.35#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:20:18.35#ibcon#first serial, iclass 6, count 0 2006.161.07:20:18.35#ibcon#enter sib2, iclass 6, count 0 2006.161.07:20:18.35#ibcon#flushed, iclass 6, count 0 2006.161.07:20:18.35#ibcon#about to write, iclass 6, count 0 2006.161.07:20:18.35#ibcon#wrote, iclass 6, count 0 2006.161.07:20:18.35#ibcon#about to read 3, iclass 6, count 0 2006.161.07:20:18.37#ibcon#read 3, iclass 6, count 0 2006.161.07:20:18.37#ibcon#about to read 4, iclass 6, count 0 2006.161.07:20:18.37#ibcon#read 4, iclass 6, count 0 2006.161.07:20:18.37#ibcon#about to read 5, iclass 6, count 0 2006.161.07:20:18.37#ibcon#read 5, iclass 6, count 0 2006.161.07:20:18.37#ibcon#about to read 6, iclass 6, count 0 2006.161.07:20:18.37#ibcon#read 6, iclass 6, count 0 2006.161.07:20:18.37#ibcon#end of sib2, iclass 6, count 0 2006.161.07:20:18.37#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:20:18.37#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:20:18.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:20:18.37#ibcon#*before write, iclass 6, count 0 2006.161.07:20:18.37#ibcon#enter sib2, iclass 6, count 0 2006.161.07:20:18.37#ibcon#flushed, iclass 6, count 0 2006.161.07:20:18.37#ibcon#about to write, iclass 6, count 0 2006.161.07:20:18.37#ibcon#wrote, iclass 6, count 0 2006.161.07:20:18.37#ibcon#about to read 3, iclass 6, count 0 2006.161.07:20:18.42#ibcon#read 3, iclass 6, count 0 2006.161.07:20:18.42#ibcon#about to read 4, iclass 6, count 0 2006.161.07:20:18.42#ibcon#read 4, iclass 6, count 0 2006.161.07:20:18.42#ibcon#about to read 5, iclass 6, count 0 2006.161.07:20:18.42#ibcon#read 5, iclass 6, count 0 2006.161.07:20:18.42#ibcon#about to read 6, iclass 6, count 0 2006.161.07:20:18.42#ibcon#read 6, iclass 6, count 0 2006.161.07:20:18.42#ibcon#end of sib2, iclass 6, count 0 2006.161.07:20:18.42#ibcon#*after write, iclass 6, count 0 2006.161.07:20:18.42#ibcon#*before return 0, iclass 6, count 0 2006.161.07:20:18.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:18.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:18.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:20:18.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:20:18.42$vc4f8/va=2,7 2006.161.07:20:18.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:20:18.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:20:18.42#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:18.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:18.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:18.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:18.47#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:20:18.47#ibcon#first serial, iclass 10, count 2 2006.161.07:20:18.47#ibcon#enter sib2, iclass 10, count 2 2006.161.07:20:18.47#ibcon#flushed, iclass 10, count 2 2006.161.07:20:18.47#ibcon#about to write, iclass 10, count 2 2006.161.07:20:18.47#ibcon#wrote, iclass 10, count 2 2006.161.07:20:18.47#ibcon#about to read 3, iclass 10, count 2 2006.161.07:20:18.49#ibcon#read 3, iclass 10, count 2 2006.161.07:20:18.49#ibcon#about to read 4, iclass 10, count 2 2006.161.07:20:18.49#ibcon#read 4, iclass 10, count 2 2006.161.07:20:18.49#ibcon#about to read 5, iclass 10, count 2 2006.161.07:20:18.49#ibcon#read 5, iclass 10, count 2 2006.161.07:20:18.49#ibcon#about to read 6, iclass 10, count 2 2006.161.07:20:18.49#ibcon#read 6, iclass 10, count 2 2006.161.07:20:18.49#ibcon#end of sib2, iclass 10, count 2 2006.161.07:20:18.49#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:20:18.49#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:20:18.49#ibcon#[25=AT02-07\r\n] 2006.161.07:20:18.49#ibcon#*before write, iclass 10, count 2 2006.161.07:20:18.49#ibcon#enter sib2, iclass 10, count 2 2006.161.07:20:18.49#ibcon#flushed, iclass 10, count 2 2006.161.07:20:18.49#ibcon#about to write, iclass 10, count 2 2006.161.07:20:18.49#ibcon#wrote, iclass 10, count 2 2006.161.07:20:18.49#ibcon#about to read 3, iclass 10, count 2 2006.161.07:20:18.53#ibcon#read 3, iclass 10, count 2 2006.161.07:20:18.53#ibcon#about to read 4, iclass 10, count 2 2006.161.07:20:18.53#ibcon#read 4, iclass 10, count 2 2006.161.07:20:18.53#ibcon#about to read 5, iclass 10, count 2 2006.161.07:20:18.53#ibcon#read 5, iclass 10, count 2 2006.161.07:20:18.53#ibcon#about to read 6, iclass 10, count 2 2006.161.07:20:18.53#ibcon#read 6, iclass 10, count 2 2006.161.07:20:18.53#ibcon#end of sib2, iclass 10, count 2 2006.161.07:20:18.53#ibcon#*after write, iclass 10, count 2 2006.161.07:20:18.53#ibcon#*before return 0, iclass 10, count 2 2006.161.07:20:18.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:18.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:18.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:20:18.53#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:18.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:18.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:18.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:18.65#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:20:18.65#ibcon#first serial, iclass 10, count 0 2006.161.07:20:18.65#ibcon#enter sib2, iclass 10, count 0 2006.161.07:20:18.65#ibcon#flushed, iclass 10, count 0 2006.161.07:20:18.65#ibcon#about to write, iclass 10, count 0 2006.161.07:20:18.65#ibcon#wrote, iclass 10, count 0 2006.161.07:20:18.65#ibcon#about to read 3, iclass 10, count 0 2006.161.07:20:18.67#ibcon#read 3, iclass 10, count 0 2006.161.07:20:18.67#ibcon#about to read 4, iclass 10, count 0 2006.161.07:20:18.67#ibcon#read 4, iclass 10, count 0 2006.161.07:20:18.67#ibcon#about to read 5, iclass 10, count 0 2006.161.07:20:18.67#ibcon#read 5, iclass 10, count 0 2006.161.07:20:18.67#ibcon#about to read 6, iclass 10, count 0 2006.161.07:20:18.67#ibcon#read 6, iclass 10, count 0 2006.161.07:20:18.67#ibcon#end of sib2, iclass 10, count 0 2006.161.07:20:18.67#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:20:18.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:20:18.67#ibcon#[25=USB\r\n] 2006.161.07:20:18.67#ibcon#*before write, iclass 10, count 0 2006.161.07:20:18.67#ibcon#enter sib2, iclass 10, count 0 2006.161.07:20:18.67#ibcon#flushed, iclass 10, count 0 2006.161.07:20:18.67#ibcon#about to write, iclass 10, count 0 2006.161.07:20:18.67#ibcon#wrote, iclass 10, count 0 2006.161.07:20:18.67#ibcon#about to read 3, iclass 10, count 0 2006.161.07:20:18.70#ibcon#read 3, iclass 10, count 0 2006.161.07:20:18.70#ibcon#about to read 4, iclass 10, count 0 2006.161.07:20:18.70#ibcon#read 4, iclass 10, count 0 2006.161.07:20:18.70#ibcon#about to read 5, iclass 10, count 0 2006.161.07:20:18.70#ibcon#read 5, iclass 10, count 0 2006.161.07:20:18.70#ibcon#about to read 6, iclass 10, count 0 2006.161.07:20:18.70#ibcon#read 6, iclass 10, count 0 2006.161.07:20:18.70#ibcon#end of sib2, iclass 10, count 0 2006.161.07:20:18.70#ibcon#*after write, iclass 10, count 0 2006.161.07:20:18.70#ibcon#*before return 0, iclass 10, count 0 2006.161.07:20:18.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:18.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:18.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:20:18.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:20:18.70$vc4f8/valo=3,672.99 2006.161.07:20:18.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:20:18.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:20:18.70#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:18.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:18.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:18.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:18.70#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:20:18.70#ibcon#first serial, iclass 12, count 0 2006.161.07:20:18.70#ibcon#enter sib2, iclass 12, count 0 2006.161.07:20:18.70#ibcon#flushed, iclass 12, count 0 2006.161.07:20:18.70#ibcon#about to write, iclass 12, count 0 2006.161.07:20:18.70#ibcon#wrote, iclass 12, count 0 2006.161.07:20:18.70#ibcon#about to read 3, iclass 12, count 0 2006.161.07:20:18.72#ibcon#read 3, iclass 12, count 0 2006.161.07:20:18.72#ibcon#about to read 4, iclass 12, count 0 2006.161.07:20:18.72#ibcon#read 4, iclass 12, count 0 2006.161.07:20:18.72#ibcon#about to read 5, iclass 12, count 0 2006.161.07:20:18.72#ibcon#read 5, iclass 12, count 0 2006.161.07:20:18.72#ibcon#about to read 6, iclass 12, count 0 2006.161.07:20:18.72#ibcon#read 6, iclass 12, count 0 2006.161.07:20:18.72#ibcon#end of sib2, iclass 12, count 0 2006.161.07:20:18.72#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:20:18.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:20:18.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:20:18.72#ibcon#*before write, iclass 12, count 0 2006.161.07:20:18.72#ibcon#enter sib2, iclass 12, count 0 2006.161.07:20:18.72#ibcon#flushed, iclass 12, count 0 2006.161.07:20:18.72#ibcon#about to write, iclass 12, count 0 2006.161.07:20:18.72#ibcon#wrote, iclass 12, count 0 2006.161.07:20:18.72#ibcon#about to read 3, iclass 12, count 0 2006.161.07:20:18.77#ibcon#read 3, iclass 12, count 0 2006.161.07:20:18.77#ibcon#about to read 4, iclass 12, count 0 2006.161.07:20:18.77#ibcon#read 4, iclass 12, count 0 2006.161.07:20:18.77#ibcon#about to read 5, iclass 12, count 0 2006.161.07:20:18.77#ibcon#read 5, iclass 12, count 0 2006.161.07:20:18.77#ibcon#about to read 6, iclass 12, count 0 2006.161.07:20:18.77#ibcon#read 6, iclass 12, count 0 2006.161.07:20:18.77#ibcon#end of sib2, iclass 12, count 0 2006.161.07:20:18.77#ibcon#*after write, iclass 12, count 0 2006.161.07:20:18.77#ibcon#*before return 0, iclass 12, count 0 2006.161.07:20:18.77#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:18.77#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:18.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:20:18.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:20:18.77$vc4f8/va=3,6 2006.161.07:20:18.77#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:20:18.77#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:20:18.77#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:18.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:18.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:18.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:18.82#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:20:18.82#ibcon#first serial, iclass 14, count 2 2006.161.07:20:18.82#ibcon#enter sib2, iclass 14, count 2 2006.161.07:20:18.82#ibcon#flushed, iclass 14, count 2 2006.161.07:20:18.82#ibcon#about to write, iclass 14, count 2 2006.161.07:20:18.82#ibcon#wrote, iclass 14, count 2 2006.161.07:20:18.82#ibcon#about to read 3, iclass 14, count 2 2006.161.07:20:18.84#ibcon#read 3, iclass 14, count 2 2006.161.07:20:18.84#ibcon#about to read 4, iclass 14, count 2 2006.161.07:20:18.84#ibcon#read 4, iclass 14, count 2 2006.161.07:20:18.84#ibcon#about to read 5, iclass 14, count 2 2006.161.07:20:18.84#ibcon#read 5, iclass 14, count 2 2006.161.07:20:18.84#ibcon#about to read 6, iclass 14, count 2 2006.161.07:20:18.84#ibcon#read 6, iclass 14, count 2 2006.161.07:20:18.84#ibcon#end of sib2, iclass 14, count 2 2006.161.07:20:18.84#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:20:18.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:20:18.84#ibcon#[25=AT03-06\r\n] 2006.161.07:20:18.84#ibcon#*before write, iclass 14, count 2 2006.161.07:20:18.84#ibcon#enter sib2, iclass 14, count 2 2006.161.07:20:18.84#ibcon#flushed, iclass 14, count 2 2006.161.07:20:18.84#ibcon#about to write, iclass 14, count 2 2006.161.07:20:18.84#ibcon#wrote, iclass 14, count 2 2006.161.07:20:18.84#ibcon#about to read 3, iclass 14, count 2 2006.161.07:20:18.88#ibcon#read 3, iclass 14, count 2 2006.161.07:20:18.88#ibcon#about to read 4, iclass 14, count 2 2006.161.07:20:18.88#ibcon#read 4, iclass 14, count 2 2006.161.07:20:18.88#ibcon#about to read 5, iclass 14, count 2 2006.161.07:20:18.88#ibcon#read 5, iclass 14, count 2 2006.161.07:20:18.88#ibcon#about to read 6, iclass 14, count 2 2006.161.07:20:18.88#ibcon#read 6, iclass 14, count 2 2006.161.07:20:18.88#ibcon#end of sib2, iclass 14, count 2 2006.161.07:20:18.88#ibcon#*after write, iclass 14, count 2 2006.161.07:20:18.88#ibcon#*before return 0, iclass 14, count 2 2006.161.07:20:18.88#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:18.88#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:18.88#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:20:18.88#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:18.88#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:19.00#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:19.00#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:19.00#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:20:19.00#ibcon#first serial, iclass 14, count 0 2006.161.07:20:19.00#ibcon#enter sib2, iclass 14, count 0 2006.161.07:20:19.00#ibcon#flushed, iclass 14, count 0 2006.161.07:20:19.00#ibcon#about to write, iclass 14, count 0 2006.161.07:20:19.00#ibcon#wrote, iclass 14, count 0 2006.161.07:20:19.00#ibcon#about to read 3, iclass 14, count 0 2006.161.07:20:19.02#ibcon#read 3, iclass 14, count 0 2006.161.07:20:19.02#ibcon#about to read 4, iclass 14, count 0 2006.161.07:20:19.02#ibcon#read 4, iclass 14, count 0 2006.161.07:20:19.02#ibcon#about to read 5, iclass 14, count 0 2006.161.07:20:19.02#ibcon#read 5, iclass 14, count 0 2006.161.07:20:19.02#ibcon#about to read 6, iclass 14, count 0 2006.161.07:20:19.02#ibcon#read 6, iclass 14, count 0 2006.161.07:20:19.02#ibcon#end of sib2, iclass 14, count 0 2006.161.07:20:19.02#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:20:19.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:20:19.02#ibcon#[25=USB\r\n] 2006.161.07:20:19.02#ibcon#*before write, iclass 14, count 0 2006.161.07:20:19.02#ibcon#enter sib2, iclass 14, count 0 2006.161.07:20:19.02#ibcon#flushed, iclass 14, count 0 2006.161.07:20:19.02#ibcon#about to write, iclass 14, count 0 2006.161.07:20:19.02#ibcon#wrote, iclass 14, count 0 2006.161.07:20:19.02#ibcon#about to read 3, iclass 14, count 0 2006.161.07:20:19.05#ibcon#read 3, iclass 14, count 0 2006.161.07:20:19.05#ibcon#about to read 4, iclass 14, count 0 2006.161.07:20:19.05#ibcon#read 4, iclass 14, count 0 2006.161.07:20:19.05#ibcon#about to read 5, iclass 14, count 0 2006.161.07:20:19.05#ibcon#read 5, iclass 14, count 0 2006.161.07:20:19.05#ibcon#about to read 6, iclass 14, count 0 2006.161.07:20:19.05#ibcon#read 6, iclass 14, count 0 2006.161.07:20:19.05#ibcon#end of sib2, iclass 14, count 0 2006.161.07:20:19.05#ibcon#*after write, iclass 14, count 0 2006.161.07:20:19.05#ibcon#*before return 0, iclass 14, count 0 2006.161.07:20:19.05#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:19.05#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:19.05#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:20:19.05#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:20:19.05$vc4f8/valo=4,832.99 2006.161.07:20:19.05#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:20:19.05#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:20:19.05#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:19.05#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:19.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:19.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:19.05#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:20:19.05#ibcon#first serial, iclass 16, count 0 2006.161.07:20:19.05#ibcon#enter sib2, iclass 16, count 0 2006.161.07:20:19.05#ibcon#flushed, iclass 16, count 0 2006.161.07:20:19.05#ibcon#about to write, iclass 16, count 0 2006.161.07:20:19.05#ibcon#wrote, iclass 16, count 0 2006.161.07:20:19.05#ibcon#about to read 3, iclass 16, count 0 2006.161.07:20:19.07#ibcon#read 3, iclass 16, count 0 2006.161.07:20:19.07#ibcon#about to read 4, iclass 16, count 0 2006.161.07:20:19.07#ibcon#read 4, iclass 16, count 0 2006.161.07:20:19.07#ibcon#about to read 5, iclass 16, count 0 2006.161.07:20:19.07#ibcon#read 5, iclass 16, count 0 2006.161.07:20:19.07#ibcon#about to read 6, iclass 16, count 0 2006.161.07:20:19.07#ibcon#read 6, iclass 16, count 0 2006.161.07:20:19.07#ibcon#end of sib2, iclass 16, count 0 2006.161.07:20:19.07#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:20:19.07#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:20:19.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:20:19.07#ibcon#*before write, iclass 16, count 0 2006.161.07:20:19.07#ibcon#enter sib2, iclass 16, count 0 2006.161.07:20:19.07#ibcon#flushed, iclass 16, count 0 2006.161.07:20:19.07#ibcon#about to write, iclass 16, count 0 2006.161.07:20:19.07#ibcon#wrote, iclass 16, count 0 2006.161.07:20:19.07#ibcon#about to read 3, iclass 16, count 0 2006.161.07:20:19.11#ibcon#read 3, iclass 16, count 0 2006.161.07:20:19.11#ibcon#about to read 4, iclass 16, count 0 2006.161.07:20:19.11#ibcon#read 4, iclass 16, count 0 2006.161.07:20:19.11#ibcon#about to read 5, iclass 16, count 0 2006.161.07:20:19.11#ibcon#read 5, iclass 16, count 0 2006.161.07:20:19.11#ibcon#about to read 6, iclass 16, count 0 2006.161.07:20:19.11#ibcon#read 6, iclass 16, count 0 2006.161.07:20:19.11#ibcon#end of sib2, iclass 16, count 0 2006.161.07:20:19.11#ibcon#*after write, iclass 16, count 0 2006.161.07:20:19.11#ibcon#*before return 0, iclass 16, count 0 2006.161.07:20:19.11#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:19.11#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:19.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:20:19.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:20:19.11$vc4f8/va=4,7 2006.161.07:20:19.11#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:20:19.11#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:20:19.11#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:19.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:19.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:19.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:19.17#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:20:19.17#ibcon#first serial, iclass 18, count 2 2006.161.07:20:19.17#ibcon#enter sib2, iclass 18, count 2 2006.161.07:20:19.17#ibcon#flushed, iclass 18, count 2 2006.161.07:20:19.17#ibcon#about to write, iclass 18, count 2 2006.161.07:20:19.17#ibcon#wrote, iclass 18, count 2 2006.161.07:20:19.17#ibcon#about to read 3, iclass 18, count 2 2006.161.07:20:19.19#ibcon#read 3, iclass 18, count 2 2006.161.07:20:19.19#ibcon#about to read 4, iclass 18, count 2 2006.161.07:20:19.19#ibcon#read 4, iclass 18, count 2 2006.161.07:20:19.19#ibcon#about to read 5, iclass 18, count 2 2006.161.07:20:19.19#ibcon#read 5, iclass 18, count 2 2006.161.07:20:19.19#ibcon#about to read 6, iclass 18, count 2 2006.161.07:20:19.19#ibcon#read 6, iclass 18, count 2 2006.161.07:20:19.19#ibcon#end of sib2, iclass 18, count 2 2006.161.07:20:19.19#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:20:19.19#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:20:19.19#ibcon#[25=AT04-07\r\n] 2006.161.07:20:19.19#ibcon#*before write, iclass 18, count 2 2006.161.07:20:19.19#ibcon#enter sib2, iclass 18, count 2 2006.161.07:20:19.19#ibcon#flushed, iclass 18, count 2 2006.161.07:20:19.19#ibcon#about to write, iclass 18, count 2 2006.161.07:20:19.19#ibcon#wrote, iclass 18, count 2 2006.161.07:20:19.19#ibcon#about to read 3, iclass 18, count 2 2006.161.07:20:19.22#ibcon#read 3, iclass 18, count 2 2006.161.07:20:19.22#ibcon#about to read 4, iclass 18, count 2 2006.161.07:20:19.22#ibcon#read 4, iclass 18, count 2 2006.161.07:20:19.22#ibcon#about to read 5, iclass 18, count 2 2006.161.07:20:19.22#ibcon#read 5, iclass 18, count 2 2006.161.07:20:19.22#ibcon#about to read 6, iclass 18, count 2 2006.161.07:20:19.22#ibcon#read 6, iclass 18, count 2 2006.161.07:20:19.22#ibcon#end of sib2, iclass 18, count 2 2006.161.07:20:19.22#ibcon#*after write, iclass 18, count 2 2006.161.07:20:19.22#ibcon#*before return 0, iclass 18, count 2 2006.161.07:20:19.22#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:19.22#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:19.22#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:20:19.22#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:19.22#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:19.34#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:19.34#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:19.34#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:20:19.34#ibcon#first serial, iclass 18, count 0 2006.161.07:20:19.34#ibcon#enter sib2, iclass 18, count 0 2006.161.07:20:19.34#ibcon#flushed, iclass 18, count 0 2006.161.07:20:19.34#ibcon#about to write, iclass 18, count 0 2006.161.07:20:19.34#ibcon#wrote, iclass 18, count 0 2006.161.07:20:19.34#ibcon#about to read 3, iclass 18, count 0 2006.161.07:20:19.36#ibcon#read 3, iclass 18, count 0 2006.161.07:20:19.36#ibcon#about to read 4, iclass 18, count 0 2006.161.07:20:19.36#ibcon#read 4, iclass 18, count 0 2006.161.07:20:19.36#ibcon#about to read 5, iclass 18, count 0 2006.161.07:20:19.36#ibcon#read 5, iclass 18, count 0 2006.161.07:20:19.36#ibcon#about to read 6, iclass 18, count 0 2006.161.07:20:19.36#ibcon#read 6, iclass 18, count 0 2006.161.07:20:19.36#ibcon#end of sib2, iclass 18, count 0 2006.161.07:20:19.36#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:20:19.36#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:20:19.36#ibcon#[25=USB\r\n] 2006.161.07:20:19.36#ibcon#*before write, iclass 18, count 0 2006.161.07:20:19.36#ibcon#enter sib2, iclass 18, count 0 2006.161.07:20:19.36#ibcon#flushed, iclass 18, count 0 2006.161.07:20:19.36#ibcon#about to write, iclass 18, count 0 2006.161.07:20:19.36#ibcon#wrote, iclass 18, count 0 2006.161.07:20:19.36#ibcon#about to read 3, iclass 18, count 0 2006.161.07:20:19.39#ibcon#read 3, iclass 18, count 0 2006.161.07:20:19.39#ibcon#about to read 4, iclass 18, count 0 2006.161.07:20:19.39#ibcon#read 4, iclass 18, count 0 2006.161.07:20:19.39#ibcon#about to read 5, iclass 18, count 0 2006.161.07:20:19.39#ibcon#read 5, iclass 18, count 0 2006.161.07:20:19.39#ibcon#about to read 6, iclass 18, count 0 2006.161.07:20:19.39#ibcon#read 6, iclass 18, count 0 2006.161.07:20:19.39#ibcon#end of sib2, iclass 18, count 0 2006.161.07:20:19.39#ibcon#*after write, iclass 18, count 0 2006.161.07:20:19.39#ibcon#*before return 0, iclass 18, count 0 2006.161.07:20:19.39#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:19.39#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:19.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:20:19.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:20:19.39$vc4f8/valo=5,652.99 2006.161.07:20:19.39#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:20:19.39#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:20:19.39#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:19.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:19.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:19.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:19.39#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:20:19.39#ibcon#first serial, iclass 20, count 0 2006.161.07:20:19.39#ibcon#enter sib2, iclass 20, count 0 2006.161.07:20:19.39#ibcon#flushed, iclass 20, count 0 2006.161.07:20:19.39#ibcon#about to write, iclass 20, count 0 2006.161.07:20:19.39#ibcon#wrote, iclass 20, count 0 2006.161.07:20:19.39#ibcon#about to read 3, iclass 20, count 0 2006.161.07:20:19.41#ibcon#read 3, iclass 20, count 0 2006.161.07:20:19.41#ibcon#about to read 4, iclass 20, count 0 2006.161.07:20:19.41#ibcon#read 4, iclass 20, count 0 2006.161.07:20:19.41#ibcon#about to read 5, iclass 20, count 0 2006.161.07:20:19.41#ibcon#read 5, iclass 20, count 0 2006.161.07:20:19.41#ibcon#about to read 6, iclass 20, count 0 2006.161.07:20:19.41#ibcon#read 6, iclass 20, count 0 2006.161.07:20:19.41#ibcon#end of sib2, iclass 20, count 0 2006.161.07:20:19.41#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:20:19.41#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:20:19.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:20:19.41#ibcon#*before write, iclass 20, count 0 2006.161.07:20:19.41#ibcon#enter sib2, iclass 20, count 0 2006.161.07:20:19.41#ibcon#flushed, iclass 20, count 0 2006.161.07:20:19.41#ibcon#about to write, iclass 20, count 0 2006.161.07:20:19.41#ibcon#wrote, iclass 20, count 0 2006.161.07:20:19.41#ibcon#about to read 3, iclass 20, count 0 2006.161.07:20:19.45#ibcon#read 3, iclass 20, count 0 2006.161.07:20:19.45#ibcon#about to read 4, iclass 20, count 0 2006.161.07:20:19.45#ibcon#read 4, iclass 20, count 0 2006.161.07:20:19.45#ibcon#about to read 5, iclass 20, count 0 2006.161.07:20:19.45#ibcon#read 5, iclass 20, count 0 2006.161.07:20:19.45#ibcon#about to read 6, iclass 20, count 0 2006.161.07:20:19.45#ibcon#read 6, iclass 20, count 0 2006.161.07:20:19.45#ibcon#end of sib2, iclass 20, count 0 2006.161.07:20:19.45#ibcon#*after write, iclass 20, count 0 2006.161.07:20:19.45#ibcon#*before return 0, iclass 20, count 0 2006.161.07:20:19.45#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:19.45#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:19.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:20:19.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:20:19.45$vc4f8/va=5,7 2006.161.07:20:19.45#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:20:19.45#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:20:19.45#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:19.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:19.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:19.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:19.51#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:20:19.51#ibcon#first serial, iclass 22, count 2 2006.161.07:20:19.51#ibcon#enter sib2, iclass 22, count 2 2006.161.07:20:19.51#ibcon#flushed, iclass 22, count 2 2006.161.07:20:19.51#ibcon#about to write, iclass 22, count 2 2006.161.07:20:19.51#ibcon#wrote, iclass 22, count 2 2006.161.07:20:19.51#ibcon#about to read 3, iclass 22, count 2 2006.161.07:20:19.53#ibcon#read 3, iclass 22, count 2 2006.161.07:20:19.53#ibcon#about to read 4, iclass 22, count 2 2006.161.07:20:19.53#ibcon#read 4, iclass 22, count 2 2006.161.07:20:19.53#ibcon#about to read 5, iclass 22, count 2 2006.161.07:20:19.53#ibcon#read 5, iclass 22, count 2 2006.161.07:20:19.53#ibcon#about to read 6, iclass 22, count 2 2006.161.07:20:19.53#ibcon#read 6, iclass 22, count 2 2006.161.07:20:19.53#ibcon#end of sib2, iclass 22, count 2 2006.161.07:20:19.53#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:20:19.53#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:20:19.53#ibcon#[25=AT05-07\r\n] 2006.161.07:20:19.53#ibcon#*before write, iclass 22, count 2 2006.161.07:20:19.53#ibcon#enter sib2, iclass 22, count 2 2006.161.07:20:19.53#ibcon#flushed, iclass 22, count 2 2006.161.07:20:19.53#ibcon#about to write, iclass 22, count 2 2006.161.07:20:19.53#ibcon#wrote, iclass 22, count 2 2006.161.07:20:19.53#ibcon#about to read 3, iclass 22, count 2 2006.161.07:20:19.57#ibcon#read 3, iclass 22, count 2 2006.161.07:20:19.57#ibcon#about to read 4, iclass 22, count 2 2006.161.07:20:19.57#ibcon#read 4, iclass 22, count 2 2006.161.07:20:19.57#ibcon#about to read 5, iclass 22, count 2 2006.161.07:20:19.57#ibcon#read 5, iclass 22, count 2 2006.161.07:20:19.57#ibcon#about to read 6, iclass 22, count 2 2006.161.07:20:19.57#ibcon#read 6, iclass 22, count 2 2006.161.07:20:19.57#ibcon#end of sib2, iclass 22, count 2 2006.161.07:20:19.57#ibcon#*after write, iclass 22, count 2 2006.161.07:20:19.57#ibcon#*before return 0, iclass 22, count 2 2006.161.07:20:19.57#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:19.57#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:19.57#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:20:19.57#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:19.57#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:19.69#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:19.69#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:19.69#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:20:19.69#ibcon#first serial, iclass 22, count 0 2006.161.07:20:19.69#ibcon#enter sib2, iclass 22, count 0 2006.161.07:20:19.69#ibcon#flushed, iclass 22, count 0 2006.161.07:20:19.69#ibcon#about to write, iclass 22, count 0 2006.161.07:20:19.69#ibcon#wrote, iclass 22, count 0 2006.161.07:20:19.69#ibcon#about to read 3, iclass 22, count 0 2006.161.07:20:19.71#ibcon#read 3, iclass 22, count 0 2006.161.07:20:19.71#ibcon#about to read 4, iclass 22, count 0 2006.161.07:20:19.71#ibcon#read 4, iclass 22, count 0 2006.161.07:20:19.71#ibcon#about to read 5, iclass 22, count 0 2006.161.07:20:19.71#ibcon#read 5, iclass 22, count 0 2006.161.07:20:19.71#ibcon#about to read 6, iclass 22, count 0 2006.161.07:20:19.71#ibcon#read 6, iclass 22, count 0 2006.161.07:20:19.71#ibcon#end of sib2, iclass 22, count 0 2006.161.07:20:19.71#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:20:19.71#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:20:19.71#ibcon#[25=USB\r\n] 2006.161.07:20:19.71#ibcon#*before write, iclass 22, count 0 2006.161.07:20:19.71#ibcon#enter sib2, iclass 22, count 0 2006.161.07:20:19.71#ibcon#flushed, iclass 22, count 0 2006.161.07:20:19.71#ibcon#about to write, iclass 22, count 0 2006.161.07:20:19.71#ibcon#wrote, iclass 22, count 0 2006.161.07:20:19.71#ibcon#about to read 3, iclass 22, count 0 2006.161.07:20:19.74#ibcon#read 3, iclass 22, count 0 2006.161.07:20:19.74#ibcon#about to read 4, iclass 22, count 0 2006.161.07:20:19.74#ibcon#read 4, iclass 22, count 0 2006.161.07:20:19.74#ibcon#about to read 5, iclass 22, count 0 2006.161.07:20:19.74#ibcon#read 5, iclass 22, count 0 2006.161.07:20:19.74#ibcon#about to read 6, iclass 22, count 0 2006.161.07:20:19.74#ibcon#read 6, iclass 22, count 0 2006.161.07:20:19.74#ibcon#end of sib2, iclass 22, count 0 2006.161.07:20:19.74#ibcon#*after write, iclass 22, count 0 2006.161.07:20:19.74#ibcon#*before return 0, iclass 22, count 0 2006.161.07:20:19.74#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:19.74#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:19.74#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:20:19.74#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:20:19.74$vc4f8/valo=6,772.99 2006.161.07:20:19.74#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:20:19.74#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:20:19.74#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:19.74#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:19.74#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:19.74#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:19.74#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:20:19.74#ibcon#first serial, iclass 24, count 0 2006.161.07:20:19.74#ibcon#enter sib2, iclass 24, count 0 2006.161.07:20:19.74#ibcon#flushed, iclass 24, count 0 2006.161.07:20:19.74#ibcon#about to write, iclass 24, count 0 2006.161.07:20:19.74#ibcon#wrote, iclass 24, count 0 2006.161.07:20:19.74#ibcon#about to read 3, iclass 24, count 0 2006.161.07:20:19.76#ibcon#read 3, iclass 24, count 0 2006.161.07:20:19.76#ibcon#about to read 4, iclass 24, count 0 2006.161.07:20:19.76#ibcon#read 4, iclass 24, count 0 2006.161.07:20:19.76#ibcon#about to read 5, iclass 24, count 0 2006.161.07:20:19.76#ibcon#read 5, iclass 24, count 0 2006.161.07:20:19.76#ibcon#about to read 6, iclass 24, count 0 2006.161.07:20:19.76#ibcon#read 6, iclass 24, count 0 2006.161.07:20:19.76#ibcon#end of sib2, iclass 24, count 0 2006.161.07:20:19.76#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:20:19.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:20:19.76#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:20:19.76#ibcon#*before write, iclass 24, count 0 2006.161.07:20:19.76#ibcon#enter sib2, iclass 24, count 0 2006.161.07:20:19.76#ibcon#flushed, iclass 24, count 0 2006.161.07:20:19.76#ibcon#about to write, iclass 24, count 0 2006.161.07:20:19.76#ibcon#wrote, iclass 24, count 0 2006.161.07:20:19.76#ibcon#about to read 3, iclass 24, count 0 2006.161.07:20:19.80#ibcon#read 3, iclass 24, count 0 2006.161.07:20:19.80#ibcon#about to read 4, iclass 24, count 0 2006.161.07:20:19.80#ibcon#read 4, iclass 24, count 0 2006.161.07:20:19.80#ibcon#about to read 5, iclass 24, count 0 2006.161.07:20:19.80#ibcon#read 5, iclass 24, count 0 2006.161.07:20:19.80#ibcon#about to read 6, iclass 24, count 0 2006.161.07:20:19.80#ibcon#read 6, iclass 24, count 0 2006.161.07:20:19.80#ibcon#end of sib2, iclass 24, count 0 2006.161.07:20:19.80#ibcon#*after write, iclass 24, count 0 2006.161.07:20:19.80#ibcon#*before return 0, iclass 24, count 0 2006.161.07:20:19.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:19.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:19.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:20:19.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:20:19.80$vc4f8/va=6,6 2006.161.07:20:19.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:20:19.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:20:19.80#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:19.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:19.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:19.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:19.86#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:20:19.86#ibcon#first serial, iclass 26, count 2 2006.161.07:20:19.86#ibcon#enter sib2, iclass 26, count 2 2006.161.07:20:19.86#ibcon#flushed, iclass 26, count 2 2006.161.07:20:19.86#ibcon#about to write, iclass 26, count 2 2006.161.07:20:19.86#ibcon#wrote, iclass 26, count 2 2006.161.07:20:19.86#ibcon#about to read 3, iclass 26, count 2 2006.161.07:20:19.88#ibcon#read 3, iclass 26, count 2 2006.161.07:20:19.88#ibcon#about to read 4, iclass 26, count 2 2006.161.07:20:19.88#ibcon#read 4, iclass 26, count 2 2006.161.07:20:19.88#ibcon#about to read 5, iclass 26, count 2 2006.161.07:20:19.88#ibcon#read 5, iclass 26, count 2 2006.161.07:20:19.88#ibcon#about to read 6, iclass 26, count 2 2006.161.07:20:19.88#ibcon#read 6, iclass 26, count 2 2006.161.07:20:19.88#ibcon#end of sib2, iclass 26, count 2 2006.161.07:20:19.88#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:20:19.88#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:20:19.88#ibcon#[25=AT06-06\r\n] 2006.161.07:20:19.88#ibcon#*before write, iclass 26, count 2 2006.161.07:20:19.88#ibcon#enter sib2, iclass 26, count 2 2006.161.07:20:19.88#ibcon#flushed, iclass 26, count 2 2006.161.07:20:19.88#ibcon#about to write, iclass 26, count 2 2006.161.07:20:19.88#ibcon#wrote, iclass 26, count 2 2006.161.07:20:19.88#ibcon#about to read 3, iclass 26, count 2 2006.161.07:20:19.91#ibcon#read 3, iclass 26, count 2 2006.161.07:20:19.91#ibcon#about to read 4, iclass 26, count 2 2006.161.07:20:19.91#ibcon#read 4, iclass 26, count 2 2006.161.07:20:19.91#ibcon#about to read 5, iclass 26, count 2 2006.161.07:20:19.91#ibcon#read 5, iclass 26, count 2 2006.161.07:20:19.91#ibcon#about to read 6, iclass 26, count 2 2006.161.07:20:19.91#ibcon#read 6, iclass 26, count 2 2006.161.07:20:19.91#ibcon#end of sib2, iclass 26, count 2 2006.161.07:20:19.91#ibcon#*after write, iclass 26, count 2 2006.161.07:20:19.91#ibcon#*before return 0, iclass 26, count 2 2006.161.07:20:19.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:19.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:19.91#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:20:19.91#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:19.91#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:20:20.03#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:20:20.03#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:20:20.03#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:20:20.03#ibcon#first serial, iclass 26, count 0 2006.161.07:20:20.03#ibcon#enter sib2, iclass 26, count 0 2006.161.07:20:20.03#ibcon#flushed, iclass 26, count 0 2006.161.07:20:20.03#ibcon#about to write, iclass 26, count 0 2006.161.07:20:20.03#ibcon#wrote, iclass 26, count 0 2006.161.07:20:20.03#ibcon#about to read 3, iclass 26, count 0 2006.161.07:20:20.05#ibcon#read 3, iclass 26, count 0 2006.161.07:20:20.05#ibcon#about to read 4, iclass 26, count 0 2006.161.07:20:20.05#ibcon#read 4, iclass 26, count 0 2006.161.07:20:20.05#ibcon#about to read 5, iclass 26, count 0 2006.161.07:20:20.05#ibcon#read 5, iclass 26, count 0 2006.161.07:20:20.05#ibcon#about to read 6, iclass 26, count 0 2006.161.07:20:20.05#ibcon#read 6, iclass 26, count 0 2006.161.07:20:20.05#ibcon#end of sib2, iclass 26, count 0 2006.161.07:20:20.05#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:20:20.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:20:20.05#ibcon#[25=USB\r\n] 2006.161.07:20:20.05#ibcon#*before write, iclass 26, count 0 2006.161.07:20:20.05#ibcon#enter sib2, iclass 26, count 0 2006.161.07:20:20.05#ibcon#flushed, iclass 26, count 0 2006.161.07:20:20.05#ibcon#about to write, iclass 26, count 0 2006.161.07:20:20.05#ibcon#wrote, iclass 26, count 0 2006.161.07:20:20.05#ibcon#about to read 3, iclass 26, count 0 2006.161.07:20:20.08#ibcon#read 3, iclass 26, count 0 2006.161.07:20:20.08#ibcon#about to read 4, iclass 26, count 0 2006.161.07:20:20.08#ibcon#read 4, iclass 26, count 0 2006.161.07:20:20.08#ibcon#about to read 5, iclass 26, count 0 2006.161.07:20:20.08#ibcon#read 5, iclass 26, count 0 2006.161.07:20:20.08#ibcon#about to read 6, iclass 26, count 0 2006.161.07:20:20.08#ibcon#read 6, iclass 26, count 0 2006.161.07:20:20.08#ibcon#end of sib2, iclass 26, count 0 2006.161.07:20:20.08#ibcon#*after write, iclass 26, count 0 2006.161.07:20:20.08#ibcon#*before return 0, iclass 26, count 0 2006.161.07:20:20.08#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:20:20.08#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:20:20.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:20:20.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:20:20.08$vc4f8/valo=7,832.99 2006.161.07:20:20.08#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:20:20.08#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:20.08#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:20:20.08#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:20:20.08#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:20:20.08#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:20:20.08#ibcon#first serial, iclass 28, count 0 2006.161.07:20:20.08#ibcon#enter sib2, iclass 28, count 0 2006.161.07:20:20.08#ibcon#flushed, iclass 28, count 0 2006.161.07:20:20.08#ibcon#about to write, iclass 28, count 0 2006.161.07:20:20.08#ibcon#wrote, iclass 28, count 0 2006.161.07:20:20.08#ibcon#about to read 3, iclass 28, count 0 2006.161.07:20:20.10#ibcon#read 3, iclass 28, count 0 2006.161.07:20:20.10#ibcon#about to read 4, iclass 28, count 0 2006.161.07:20:20.10#ibcon#read 4, iclass 28, count 0 2006.161.07:20:20.10#ibcon#about to read 5, iclass 28, count 0 2006.161.07:20:20.10#ibcon#read 5, iclass 28, count 0 2006.161.07:20:20.10#ibcon#about to read 6, iclass 28, count 0 2006.161.07:20:20.10#ibcon#read 6, iclass 28, count 0 2006.161.07:20:20.10#ibcon#end of sib2, iclass 28, count 0 2006.161.07:20:20.10#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:20:20.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:20:20.10#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:20:20.10#ibcon#*before write, iclass 28, count 0 2006.161.07:20:20.10#ibcon#enter sib2, iclass 28, count 0 2006.161.07:20:20.10#ibcon#flushed, iclass 28, count 0 2006.161.07:20:20.10#ibcon#about to write, iclass 28, count 0 2006.161.07:20:20.10#ibcon#wrote, iclass 28, count 0 2006.161.07:20:20.10#ibcon#about to read 3, iclass 28, count 0 2006.161.07:20:20.14#ibcon#read 3, iclass 28, count 0 2006.161.07:20:20.14#ibcon#about to read 4, iclass 28, count 0 2006.161.07:20:20.14#ibcon#read 4, iclass 28, count 0 2006.161.07:20:20.14#ibcon#about to read 5, iclass 28, count 0 2006.161.07:20:20.14#ibcon#read 5, iclass 28, count 0 2006.161.07:20:20.14#ibcon#about to read 6, iclass 28, count 0 2006.161.07:20:20.14#ibcon#read 6, iclass 28, count 0 2006.161.07:20:20.14#ibcon#end of sib2, iclass 28, count 0 2006.161.07:20:20.14#ibcon#*after write, iclass 28, count 0 2006.161.07:20:20.14#ibcon#*before return 0, iclass 28, count 0 2006.161.07:20:20.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:20:20.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:20:20.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:20:20.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:20:20.14$vc4f8/va=7,6 2006.161.07:20:20.14#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.07:20:20.14#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.07:20:20.14#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:20.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:20:20.20#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:20:20.20#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:20:20.20#ibcon#enter wrdev, iclass 30, count 2 2006.161.07:20:20.20#ibcon#first serial, iclass 30, count 2 2006.161.07:20:20.20#ibcon#enter sib2, iclass 30, count 2 2006.161.07:20:20.20#ibcon#flushed, iclass 30, count 2 2006.161.07:20:20.20#ibcon#about to write, iclass 30, count 2 2006.161.07:20:20.20#ibcon#wrote, iclass 30, count 2 2006.161.07:20:20.20#ibcon#about to read 3, iclass 30, count 2 2006.161.07:20:20.22#ibcon#read 3, iclass 30, count 2 2006.161.07:20:20.22#ibcon#about to read 4, iclass 30, count 2 2006.161.07:20:20.22#ibcon#read 4, iclass 30, count 2 2006.161.07:20:20.22#ibcon#about to read 5, iclass 30, count 2 2006.161.07:20:20.22#ibcon#read 5, iclass 30, count 2 2006.161.07:20:20.22#ibcon#about to read 6, iclass 30, count 2 2006.161.07:20:20.22#ibcon#read 6, iclass 30, count 2 2006.161.07:20:20.22#ibcon#end of sib2, iclass 30, count 2 2006.161.07:20:20.22#ibcon#*mode == 0, iclass 30, count 2 2006.161.07:20:20.22#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.07:20:20.22#ibcon#[25=AT07-06\r\n] 2006.161.07:20:20.22#ibcon#*before write, iclass 30, count 2 2006.161.07:20:20.22#ibcon#enter sib2, iclass 30, count 2 2006.161.07:20:20.22#ibcon#flushed, iclass 30, count 2 2006.161.07:20:20.22#ibcon#about to write, iclass 30, count 2 2006.161.07:20:20.22#ibcon#wrote, iclass 30, count 2 2006.161.07:20:20.22#ibcon#about to read 3, iclass 30, count 2 2006.161.07:20:20.25#ibcon#read 3, iclass 30, count 2 2006.161.07:20:20.25#ibcon#about to read 4, iclass 30, count 2 2006.161.07:20:20.25#ibcon#read 4, iclass 30, count 2 2006.161.07:20:20.25#ibcon#about to read 5, iclass 30, count 2 2006.161.07:20:20.25#ibcon#read 5, iclass 30, count 2 2006.161.07:20:20.25#ibcon#about to read 6, iclass 30, count 2 2006.161.07:20:20.25#ibcon#read 6, iclass 30, count 2 2006.161.07:20:20.25#ibcon#end of sib2, iclass 30, count 2 2006.161.07:20:20.25#ibcon#*after write, iclass 30, count 2 2006.161.07:20:20.25#ibcon#*before return 0, iclass 30, count 2 2006.161.07:20:20.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:20:20.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:20:20.25#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.07:20:20.25#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:20.25#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:20:20.37#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:20:20.37#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:20:20.37#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:20:20.37#ibcon#first serial, iclass 30, count 0 2006.161.07:20:20.37#ibcon#enter sib2, iclass 30, count 0 2006.161.07:20:20.37#ibcon#flushed, iclass 30, count 0 2006.161.07:20:20.37#ibcon#about to write, iclass 30, count 0 2006.161.07:20:20.37#ibcon#wrote, iclass 30, count 0 2006.161.07:20:20.37#ibcon#about to read 3, iclass 30, count 0 2006.161.07:20:20.39#ibcon#read 3, iclass 30, count 0 2006.161.07:20:20.39#ibcon#about to read 4, iclass 30, count 0 2006.161.07:20:20.39#ibcon#read 4, iclass 30, count 0 2006.161.07:20:20.39#ibcon#about to read 5, iclass 30, count 0 2006.161.07:20:20.39#ibcon#read 5, iclass 30, count 0 2006.161.07:20:20.39#ibcon#about to read 6, iclass 30, count 0 2006.161.07:20:20.39#ibcon#read 6, iclass 30, count 0 2006.161.07:20:20.39#ibcon#end of sib2, iclass 30, count 0 2006.161.07:20:20.39#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:20:20.39#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:20:20.39#ibcon#[25=USB\r\n] 2006.161.07:20:20.39#ibcon#*before write, iclass 30, count 0 2006.161.07:20:20.39#ibcon#enter sib2, iclass 30, count 0 2006.161.07:20:20.39#ibcon#flushed, iclass 30, count 0 2006.161.07:20:20.39#ibcon#about to write, iclass 30, count 0 2006.161.07:20:20.39#ibcon#wrote, iclass 30, count 0 2006.161.07:20:20.39#ibcon#about to read 3, iclass 30, count 0 2006.161.07:20:20.42#ibcon#read 3, iclass 30, count 0 2006.161.07:20:20.42#ibcon#about to read 4, iclass 30, count 0 2006.161.07:20:20.42#ibcon#read 4, iclass 30, count 0 2006.161.07:20:20.42#ibcon#about to read 5, iclass 30, count 0 2006.161.07:20:20.42#ibcon#read 5, iclass 30, count 0 2006.161.07:20:20.42#ibcon#about to read 6, iclass 30, count 0 2006.161.07:20:20.42#ibcon#read 6, iclass 30, count 0 2006.161.07:20:20.42#ibcon#end of sib2, iclass 30, count 0 2006.161.07:20:20.42#ibcon#*after write, iclass 30, count 0 2006.161.07:20:20.42#ibcon#*before return 0, iclass 30, count 0 2006.161.07:20:20.42#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:20:20.42#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:20:20.42#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:20:20.42#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:20:20.42$vc4f8/valo=8,852.99 2006.161.07:20:20.42#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.07:20:20.42#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.07:20:20.42#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:20.42#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:20:20.42#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:20:20.42#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:20:20.42#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:20:20.42#ibcon#first serial, iclass 32, count 0 2006.161.07:20:20.42#ibcon#enter sib2, iclass 32, count 0 2006.161.07:20:20.42#ibcon#flushed, iclass 32, count 0 2006.161.07:20:20.42#ibcon#about to write, iclass 32, count 0 2006.161.07:20:20.42#ibcon#wrote, iclass 32, count 0 2006.161.07:20:20.42#ibcon#about to read 3, iclass 32, count 0 2006.161.07:20:20.44#ibcon#read 3, iclass 32, count 0 2006.161.07:20:20.44#ibcon#about to read 4, iclass 32, count 0 2006.161.07:20:20.44#ibcon#read 4, iclass 32, count 0 2006.161.07:20:20.44#ibcon#about to read 5, iclass 32, count 0 2006.161.07:20:20.44#ibcon#read 5, iclass 32, count 0 2006.161.07:20:20.44#ibcon#about to read 6, iclass 32, count 0 2006.161.07:20:20.44#ibcon#read 6, iclass 32, count 0 2006.161.07:20:20.44#ibcon#end of sib2, iclass 32, count 0 2006.161.07:20:20.44#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:20:20.44#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:20:20.44#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:20:20.44#ibcon#*before write, iclass 32, count 0 2006.161.07:20:20.44#ibcon#enter sib2, iclass 32, count 0 2006.161.07:20:20.44#ibcon#flushed, iclass 32, count 0 2006.161.07:20:20.44#ibcon#about to write, iclass 32, count 0 2006.161.07:20:20.44#ibcon#wrote, iclass 32, count 0 2006.161.07:20:20.44#ibcon#about to read 3, iclass 32, count 0 2006.161.07:20:20.48#ibcon#read 3, iclass 32, count 0 2006.161.07:20:20.48#ibcon#about to read 4, iclass 32, count 0 2006.161.07:20:20.48#ibcon#read 4, iclass 32, count 0 2006.161.07:20:20.48#ibcon#about to read 5, iclass 32, count 0 2006.161.07:20:20.48#ibcon#read 5, iclass 32, count 0 2006.161.07:20:20.48#ibcon#about to read 6, iclass 32, count 0 2006.161.07:20:20.48#ibcon#read 6, iclass 32, count 0 2006.161.07:20:20.48#ibcon#end of sib2, iclass 32, count 0 2006.161.07:20:20.48#ibcon#*after write, iclass 32, count 0 2006.161.07:20:20.48#ibcon#*before return 0, iclass 32, count 0 2006.161.07:20:20.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:20:20.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:20:20.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:20:20.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:20:20.48$vc4f8/va=8,7 2006.161.07:20:20.48#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.07:20:20.48#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.07:20:20.48#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:20.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:20:20.54#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:20:20.54#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:20:20.54#ibcon#enter wrdev, iclass 34, count 2 2006.161.07:20:20.54#ibcon#first serial, iclass 34, count 2 2006.161.07:20:20.54#ibcon#enter sib2, iclass 34, count 2 2006.161.07:20:20.54#ibcon#flushed, iclass 34, count 2 2006.161.07:20:20.54#ibcon#about to write, iclass 34, count 2 2006.161.07:20:20.54#ibcon#wrote, iclass 34, count 2 2006.161.07:20:20.54#ibcon#about to read 3, iclass 34, count 2 2006.161.07:20:20.56#ibcon#read 3, iclass 34, count 2 2006.161.07:20:20.56#ibcon#about to read 4, iclass 34, count 2 2006.161.07:20:20.56#ibcon#read 4, iclass 34, count 2 2006.161.07:20:20.56#ibcon#about to read 5, iclass 34, count 2 2006.161.07:20:20.56#ibcon#read 5, iclass 34, count 2 2006.161.07:20:20.56#ibcon#about to read 6, iclass 34, count 2 2006.161.07:20:20.56#ibcon#read 6, iclass 34, count 2 2006.161.07:20:20.56#ibcon#end of sib2, iclass 34, count 2 2006.161.07:20:20.56#ibcon#*mode == 0, iclass 34, count 2 2006.161.07:20:20.56#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.07:20:20.56#ibcon#[25=AT08-07\r\n] 2006.161.07:20:20.56#ibcon#*before write, iclass 34, count 2 2006.161.07:20:20.56#ibcon#enter sib2, iclass 34, count 2 2006.161.07:20:20.56#ibcon#flushed, iclass 34, count 2 2006.161.07:20:20.56#ibcon#about to write, iclass 34, count 2 2006.161.07:20:20.56#ibcon#wrote, iclass 34, count 2 2006.161.07:20:20.56#ibcon#about to read 3, iclass 34, count 2 2006.161.07:20:20.59#ibcon#read 3, iclass 34, count 2 2006.161.07:20:20.59#ibcon#about to read 4, iclass 34, count 2 2006.161.07:20:20.59#ibcon#read 4, iclass 34, count 2 2006.161.07:20:20.59#ibcon#about to read 5, iclass 34, count 2 2006.161.07:20:20.59#ibcon#read 5, iclass 34, count 2 2006.161.07:20:20.59#ibcon#about to read 6, iclass 34, count 2 2006.161.07:20:20.59#ibcon#read 6, iclass 34, count 2 2006.161.07:20:20.59#ibcon#end of sib2, iclass 34, count 2 2006.161.07:20:20.59#ibcon#*after write, iclass 34, count 2 2006.161.07:20:20.59#ibcon#*before return 0, iclass 34, count 2 2006.161.07:20:20.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:20:20.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:20:20.59#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.07:20:20.59#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:20.59#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:20:20.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:20:20.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:20:20.71#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:20:20.71#ibcon#first serial, iclass 34, count 0 2006.161.07:20:20.71#ibcon#enter sib2, iclass 34, count 0 2006.161.07:20:20.71#ibcon#flushed, iclass 34, count 0 2006.161.07:20:20.71#ibcon#about to write, iclass 34, count 0 2006.161.07:20:20.71#ibcon#wrote, iclass 34, count 0 2006.161.07:20:20.71#ibcon#about to read 3, iclass 34, count 0 2006.161.07:20:20.73#ibcon#read 3, iclass 34, count 0 2006.161.07:20:20.73#ibcon#about to read 4, iclass 34, count 0 2006.161.07:20:20.73#ibcon#read 4, iclass 34, count 0 2006.161.07:20:20.73#ibcon#about to read 5, iclass 34, count 0 2006.161.07:20:20.73#ibcon#read 5, iclass 34, count 0 2006.161.07:20:20.73#ibcon#about to read 6, iclass 34, count 0 2006.161.07:20:20.73#ibcon#read 6, iclass 34, count 0 2006.161.07:20:20.73#ibcon#end of sib2, iclass 34, count 0 2006.161.07:20:20.73#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:20:20.73#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:20:20.73#ibcon#[25=USB\r\n] 2006.161.07:20:20.73#ibcon#*before write, iclass 34, count 0 2006.161.07:20:20.73#ibcon#enter sib2, iclass 34, count 0 2006.161.07:20:20.73#ibcon#flushed, iclass 34, count 0 2006.161.07:20:20.73#ibcon#about to write, iclass 34, count 0 2006.161.07:20:20.73#ibcon#wrote, iclass 34, count 0 2006.161.07:20:20.73#ibcon#about to read 3, iclass 34, count 0 2006.161.07:20:20.76#ibcon#read 3, iclass 34, count 0 2006.161.07:20:20.76#ibcon#about to read 4, iclass 34, count 0 2006.161.07:20:20.76#ibcon#read 4, iclass 34, count 0 2006.161.07:20:20.76#ibcon#about to read 5, iclass 34, count 0 2006.161.07:20:20.76#ibcon#read 5, iclass 34, count 0 2006.161.07:20:20.76#ibcon#about to read 6, iclass 34, count 0 2006.161.07:20:20.76#ibcon#read 6, iclass 34, count 0 2006.161.07:20:20.76#ibcon#end of sib2, iclass 34, count 0 2006.161.07:20:20.76#ibcon#*after write, iclass 34, count 0 2006.161.07:20:20.76#ibcon#*before return 0, iclass 34, count 0 2006.161.07:20:20.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:20:20.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:20:20.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:20:20.76#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:20:20.76$vc4f8/vblo=1,632.99 2006.161.07:20:20.76#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.07:20:20.76#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.07:20:20.76#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:20.76#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:20:20.76#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:20:20.76#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:20:20.76#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:20:20.76#ibcon#first serial, iclass 36, count 0 2006.161.07:20:20.76#ibcon#enter sib2, iclass 36, count 0 2006.161.07:20:20.76#ibcon#flushed, iclass 36, count 0 2006.161.07:20:20.76#ibcon#about to write, iclass 36, count 0 2006.161.07:20:20.76#ibcon#wrote, iclass 36, count 0 2006.161.07:20:20.76#ibcon#about to read 3, iclass 36, count 0 2006.161.07:20:20.78#ibcon#read 3, iclass 36, count 0 2006.161.07:20:20.78#ibcon#about to read 4, iclass 36, count 0 2006.161.07:20:20.78#ibcon#read 4, iclass 36, count 0 2006.161.07:20:20.78#ibcon#about to read 5, iclass 36, count 0 2006.161.07:20:20.78#ibcon#read 5, iclass 36, count 0 2006.161.07:20:20.78#ibcon#about to read 6, iclass 36, count 0 2006.161.07:20:20.78#ibcon#read 6, iclass 36, count 0 2006.161.07:20:20.78#ibcon#end of sib2, iclass 36, count 0 2006.161.07:20:20.78#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:20:20.78#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:20:20.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:20:20.78#ibcon#*before write, iclass 36, count 0 2006.161.07:20:20.78#ibcon#enter sib2, iclass 36, count 0 2006.161.07:20:20.78#ibcon#flushed, iclass 36, count 0 2006.161.07:20:20.78#ibcon#about to write, iclass 36, count 0 2006.161.07:20:20.78#ibcon#wrote, iclass 36, count 0 2006.161.07:20:20.78#ibcon#about to read 3, iclass 36, count 0 2006.161.07:20:20.84#ibcon#read 3, iclass 36, count 0 2006.161.07:20:20.84#ibcon#about to read 4, iclass 36, count 0 2006.161.07:20:20.84#ibcon#read 4, iclass 36, count 0 2006.161.07:20:20.84#ibcon#about to read 5, iclass 36, count 0 2006.161.07:20:20.84#ibcon#read 5, iclass 36, count 0 2006.161.07:20:20.84#ibcon#about to read 6, iclass 36, count 0 2006.161.07:20:20.84#ibcon#read 6, iclass 36, count 0 2006.161.07:20:20.84#ibcon#end of sib2, iclass 36, count 0 2006.161.07:20:20.84#ibcon#*after write, iclass 36, count 0 2006.161.07:20:20.84#ibcon#*before return 0, iclass 36, count 0 2006.161.07:20:20.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:20:20.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:20:20.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:20:20.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:20:20.84$vc4f8/vb=1,4 2006.161.07:20:20.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.07:20:20.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.07:20:20.84#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:20.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:20:20.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:20:20.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:20:20.84#ibcon#enter wrdev, iclass 38, count 2 2006.161.07:20:20.84#ibcon#first serial, iclass 38, count 2 2006.161.07:20:20.84#ibcon#enter sib2, iclass 38, count 2 2006.161.07:20:20.84#ibcon#flushed, iclass 38, count 2 2006.161.07:20:20.84#ibcon#about to write, iclass 38, count 2 2006.161.07:20:20.84#ibcon#wrote, iclass 38, count 2 2006.161.07:20:20.84#ibcon#about to read 3, iclass 38, count 2 2006.161.07:20:20.86#ibcon#read 3, iclass 38, count 2 2006.161.07:20:20.86#ibcon#about to read 4, iclass 38, count 2 2006.161.07:20:20.86#ibcon#read 4, iclass 38, count 2 2006.161.07:20:20.86#ibcon#about to read 5, iclass 38, count 2 2006.161.07:20:20.86#ibcon#read 5, iclass 38, count 2 2006.161.07:20:20.86#ibcon#about to read 6, iclass 38, count 2 2006.161.07:20:20.86#ibcon#read 6, iclass 38, count 2 2006.161.07:20:20.86#ibcon#end of sib2, iclass 38, count 2 2006.161.07:20:20.86#ibcon#*mode == 0, iclass 38, count 2 2006.161.07:20:20.86#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.07:20:20.86#ibcon#[27=AT01-04\r\n] 2006.161.07:20:20.86#ibcon#*before write, iclass 38, count 2 2006.161.07:20:20.86#ibcon#enter sib2, iclass 38, count 2 2006.161.07:20:20.86#ibcon#flushed, iclass 38, count 2 2006.161.07:20:20.86#ibcon#about to write, iclass 38, count 2 2006.161.07:20:20.86#ibcon#wrote, iclass 38, count 2 2006.161.07:20:20.86#ibcon#about to read 3, iclass 38, count 2 2006.161.07:20:20.90#ibcon#read 3, iclass 38, count 2 2006.161.07:20:20.90#ibcon#about to read 4, iclass 38, count 2 2006.161.07:20:20.90#ibcon#read 4, iclass 38, count 2 2006.161.07:20:20.90#ibcon#about to read 5, iclass 38, count 2 2006.161.07:20:20.90#ibcon#read 5, iclass 38, count 2 2006.161.07:20:20.90#ibcon#about to read 6, iclass 38, count 2 2006.161.07:20:20.90#ibcon#read 6, iclass 38, count 2 2006.161.07:20:20.90#ibcon#end of sib2, iclass 38, count 2 2006.161.07:20:20.90#ibcon#*after write, iclass 38, count 2 2006.161.07:20:20.90#ibcon#*before return 0, iclass 38, count 2 2006.161.07:20:20.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:20:20.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:20:20.90#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.07:20:20.90#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:20.90#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:20:21.02#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:20:21.02#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:20:21.02#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:20:21.02#ibcon#first serial, iclass 38, count 0 2006.161.07:20:21.02#ibcon#enter sib2, iclass 38, count 0 2006.161.07:20:21.02#ibcon#flushed, iclass 38, count 0 2006.161.07:20:21.02#ibcon#about to write, iclass 38, count 0 2006.161.07:20:21.02#ibcon#wrote, iclass 38, count 0 2006.161.07:20:21.02#ibcon#about to read 3, iclass 38, count 0 2006.161.07:20:21.04#ibcon#read 3, iclass 38, count 0 2006.161.07:20:21.04#ibcon#about to read 4, iclass 38, count 0 2006.161.07:20:21.04#ibcon#read 4, iclass 38, count 0 2006.161.07:20:21.04#ibcon#about to read 5, iclass 38, count 0 2006.161.07:20:21.04#ibcon#read 5, iclass 38, count 0 2006.161.07:20:21.04#ibcon#about to read 6, iclass 38, count 0 2006.161.07:20:21.04#ibcon#read 6, iclass 38, count 0 2006.161.07:20:21.04#ibcon#end of sib2, iclass 38, count 0 2006.161.07:20:21.04#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:20:21.04#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:20:21.04#ibcon#[27=USB\r\n] 2006.161.07:20:21.04#ibcon#*before write, iclass 38, count 0 2006.161.07:20:21.04#ibcon#enter sib2, iclass 38, count 0 2006.161.07:20:21.04#ibcon#flushed, iclass 38, count 0 2006.161.07:20:21.04#ibcon#about to write, iclass 38, count 0 2006.161.07:20:21.04#ibcon#wrote, iclass 38, count 0 2006.161.07:20:21.04#ibcon#about to read 3, iclass 38, count 0 2006.161.07:20:21.07#ibcon#read 3, iclass 38, count 0 2006.161.07:20:21.07#ibcon#about to read 4, iclass 38, count 0 2006.161.07:20:21.07#ibcon#read 4, iclass 38, count 0 2006.161.07:20:21.07#ibcon#about to read 5, iclass 38, count 0 2006.161.07:20:21.07#ibcon#read 5, iclass 38, count 0 2006.161.07:20:21.07#ibcon#about to read 6, iclass 38, count 0 2006.161.07:20:21.07#ibcon#read 6, iclass 38, count 0 2006.161.07:20:21.07#ibcon#end of sib2, iclass 38, count 0 2006.161.07:20:21.07#ibcon#*after write, iclass 38, count 0 2006.161.07:20:21.07#ibcon#*before return 0, iclass 38, count 0 2006.161.07:20:21.07#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:20:21.07#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:20:21.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:20:21.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:20:21.07$vc4f8/vblo=2,640.99 2006.161.07:20:21.07#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:20:21.07#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:20:21.07#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:21.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:21.07#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:21.07#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:21.07#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:20:21.07#ibcon#first serial, iclass 40, count 0 2006.161.07:20:21.07#ibcon#enter sib2, iclass 40, count 0 2006.161.07:20:21.07#ibcon#flushed, iclass 40, count 0 2006.161.07:20:21.07#ibcon#about to write, iclass 40, count 0 2006.161.07:20:21.07#ibcon#wrote, iclass 40, count 0 2006.161.07:20:21.07#ibcon#about to read 3, iclass 40, count 0 2006.161.07:20:21.09#ibcon#read 3, iclass 40, count 0 2006.161.07:20:21.09#ibcon#about to read 4, iclass 40, count 0 2006.161.07:20:21.09#ibcon#read 4, iclass 40, count 0 2006.161.07:20:21.09#ibcon#about to read 5, iclass 40, count 0 2006.161.07:20:21.09#ibcon#read 5, iclass 40, count 0 2006.161.07:20:21.09#ibcon#about to read 6, iclass 40, count 0 2006.161.07:20:21.09#ibcon#read 6, iclass 40, count 0 2006.161.07:20:21.09#ibcon#end of sib2, iclass 40, count 0 2006.161.07:20:21.09#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:20:21.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:20:21.09#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:20:21.09#ibcon#*before write, iclass 40, count 0 2006.161.07:20:21.09#ibcon#enter sib2, iclass 40, count 0 2006.161.07:20:21.09#ibcon#flushed, iclass 40, count 0 2006.161.07:20:21.09#ibcon#about to write, iclass 40, count 0 2006.161.07:20:21.09#ibcon#wrote, iclass 40, count 0 2006.161.07:20:21.09#ibcon#about to read 3, iclass 40, count 0 2006.161.07:20:21.13#ibcon#read 3, iclass 40, count 0 2006.161.07:20:21.13#ibcon#about to read 4, iclass 40, count 0 2006.161.07:20:21.13#ibcon#read 4, iclass 40, count 0 2006.161.07:20:21.13#ibcon#about to read 5, iclass 40, count 0 2006.161.07:20:21.13#ibcon#read 5, iclass 40, count 0 2006.161.07:20:21.13#ibcon#about to read 6, iclass 40, count 0 2006.161.07:20:21.13#ibcon#read 6, iclass 40, count 0 2006.161.07:20:21.13#ibcon#end of sib2, iclass 40, count 0 2006.161.07:20:21.13#ibcon#*after write, iclass 40, count 0 2006.161.07:20:21.13#ibcon#*before return 0, iclass 40, count 0 2006.161.07:20:21.13#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:21.13#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:20:21.13#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:20:21.13#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:20:21.13$vc4f8/vb=2,4 2006.161.07:20:21.13#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:20:21.13#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:20:21.13#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:21.13#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:21.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:21.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:21.19#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:20:21.19#ibcon#first serial, iclass 4, count 2 2006.161.07:20:21.19#ibcon#enter sib2, iclass 4, count 2 2006.161.07:20:21.19#ibcon#flushed, iclass 4, count 2 2006.161.07:20:21.19#ibcon#about to write, iclass 4, count 2 2006.161.07:20:21.19#ibcon#wrote, iclass 4, count 2 2006.161.07:20:21.19#ibcon#about to read 3, iclass 4, count 2 2006.161.07:20:21.21#ibcon#read 3, iclass 4, count 2 2006.161.07:20:21.21#ibcon#about to read 4, iclass 4, count 2 2006.161.07:20:21.21#ibcon#read 4, iclass 4, count 2 2006.161.07:20:21.21#ibcon#about to read 5, iclass 4, count 2 2006.161.07:20:21.21#ibcon#read 5, iclass 4, count 2 2006.161.07:20:21.21#ibcon#about to read 6, iclass 4, count 2 2006.161.07:20:21.21#ibcon#read 6, iclass 4, count 2 2006.161.07:20:21.21#ibcon#end of sib2, iclass 4, count 2 2006.161.07:20:21.21#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:20:21.21#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:20:21.21#ibcon#[27=AT02-04\r\n] 2006.161.07:20:21.21#ibcon#*before write, iclass 4, count 2 2006.161.07:20:21.21#ibcon#enter sib2, iclass 4, count 2 2006.161.07:20:21.21#ibcon#flushed, iclass 4, count 2 2006.161.07:20:21.21#ibcon#about to write, iclass 4, count 2 2006.161.07:20:21.21#ibcon#wrote, iclass 4, count 2 2006.161.07:20:21.21#ibcon#about to read 3, iclass 4, count 2 2006.161.07:20:21.24#ibcon#read 3, iclass 4, count 2 2006.161.07:20:21.24#ibcon#about to read 4, iclass 4, count 2 2006.161.07:20:21.24#ibcon#read 4, iclass 4, count 2 2006.161.07:20:21.24#ibcon#about to read 5, iclass 4, count 2 2006.161.07:20:21.24#ibcon#read 5, iclass 4, count 2 2006.161.07:20:21.24#ibcon#about to read 6, iclass 4, count 2 2006.161.07:20:21.24#ibcon#read 6, iclass 4, count 2 2006.161.07:20:21.24#ibcon#end of sib2, iclass 4, count 2 2006.161.07:20:21.24#ibcon#*after write, iclass 4, count 2 2006.161.07:20:21.24#ibcon#*before return 0, iclass 4, count 2 2006.161.07:20:21.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:21.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:20:21.24#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:20:21.24#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:21.24#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:21.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:21.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:21.36#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:20:21.36#ibcon#first serial, iclass 4, count 0 2006.161.07:20:21.36#ibcon#enter sib2, iclass 4, count 0 2006.161.07:20:21.36#ibcon#flushed, iclass 4, count 0 2006.161.07:20:21.36#ibcon#about to write, iclass 4, count 0 2006.161.07:20:21.36#ibcon#wrote, iclass 4, count 0 2006.161.07:20:21.36#ibcon#about to read 3, iclass 4, count 0 2006.161.07:20:21.38#ibcon#read 3, iclass 4, count 0 2006.161.07:20:21.38#ibcon#about to read 4, iclass 4, count 0 2006.161.07:20:21.38#ibcon#read 4, iclass 4, count 0 2006.161.07:20:21.38#ibcon#about to read 5, iclass 4, count 0 2006.161.07:20:21.38#ibcon#read 5, iclass 4, count 0 2006.161.07:20:21.38#ibcon#about to read 6, iclass 4, count 0 2006.161.07:20:21.38#ibcon#read 6, iclass 4, count 0 2006.161.07:20:21.38#ibcon#end of sib2, iclass 4, count 0 2006.161.07:20:21.38#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:20:21.38#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:20:21.38#ibcon#[27=USB\r\n] 2006.161.07:20:21.38#ibcon#*before write, iclass 4, count 0 2006.161.07:20:21.38#ibcon#enter sib2, iclass 4, count 0 2006.161.07:20:21.38#ibcon#flushed, iclass 4, count 0 2006.161.07:20:21.38#ibcon#about to write, iclass 4, count 0 2006.161.07:20:21.38#ibcon#wrote, iclass 4, count 0 2006.161.07:20:21.38#ibcon#about to read 3, iclass 4, count 0 2006.161.07:20:21.41#ibcon#read 3, iclass 4, count 0 2006.161.07:20:21.41#ibcon#about to read 4, iclass 4, count 0 2006.161.07:20:21.41#ibcon#read 4, iclass 4, count 0 2006.161.07:20:21.41#ibcon#about to read 5, iclass 4, count 0 2006.161.07:20:21.41#ibcon#read 5, iclass 4, count 0 2006.161.07:20:21.41#ibcon#about to read 6, iclass 4, count 0 2006.161.07:20:21.41#ibcon#read 6, iclass 4, count 0 2006.161.07:20:21.41#ibcon#end of sib2, iclass 4, count 0 2006.161.07:20:21.41#ibcon#*after write, iclass 4, count 0 2006.161.07:20:21.41#ibcon#*before return 0, iclass 4, count 0 2006.161.07:20:21.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:21.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:20:21.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:20:21.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:20:21.41$vc4f8/vblo=3,656.99 2006.161.07:20:21.41#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:20:21.41#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:20:21.41#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:21.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:21.41#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:21.41#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:21.41#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:20:21.41#ibcon#first serial, iclass 6, count 0 2006.161.07:20:21.41#ibcon#enter sib2, iclass 6, count 0 2006.161.07:20:21.41#ibcon#flushed, iclass 6, count 0 2006.161.07:20:21.41#ibcon#about to write, iclass 6, count 0 2006.161.07:20:21.41#ibcon#wrote, iclass 6, count 0 2006.161.07:20:21.41#ibcon#about to read 3, iclass 6, count 0 2006.161.07:20:21.43#ibcon#read 3, iclass 6, count 0 2006.161.07:20:21.43#ibcon#about to read 4, iclass 6, count 0 2006.161.07:20:21.43#ibcon#read 4, iclass 6, count 0 2006.161.07:20:21.43#ibcon#about to read 5, iclass 6, count 0 2006.161.07:20:21.43#ibcon#read 5, iclass 6, count 0 2006.161.07:20:21.43#ibcon#about to read 6, iclass 6, count 0 2006.161.07:20:21.43#ibcon#read 6, iclass 6, count 0 2006.161.07:20:21.43#ibcon#end of sib2, iclass 6, count 0 2006.161.07:20:21.43#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:20:21.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:20:21.43#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:20:21.43#ibcon#*before write, iclass 6, count 0 2006.161.07:20:21.43#ibcon#enter sib2, iclass 6, count 0 2006.161.07:20:21.43#ibcon#flushed, iclass 6, count 0 2006.161.07:20:21.43#ibcon#about to write, iclass 6, count 0 2006.161.07:20:21.43#ibcon#wrote, iclass 6, count 0 2006.161.07:20:21.43#ibcon#about to read 3, iclass 6, count 0 2006.161.07:20:21.47#ibcon#read 3, iclass 6, count 0 2006.161.07:20:21.47#ibcon#about to read 4, iclass 6, count 0 2006.161.07:20:21.47#ibcon#read 4, iclass 6, count 0 2006.161.07:20:21.47#ibcon#about to read 5, iclass 6, count 0 2006.161.07:20:21.47#ibcon#read 5, iclass 6, count 0 2006.161.07:20:21.47#ibcon#about to read 6, iclass 6, count 0 2006.161.07:20:21.47#ibcon#read 6, iclass 6, count 0 2006.161.07:20:21.47#ibcon#end of sib2, iclass 6, count 0 2006.161.07:20:21.47#ibcon#*after write, iclass 6, count 0 2006.161.07:20:21.47#ibcon#*before return 0, iclass 6, count 0 2006.161.07:20:21.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:21.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:20:21.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:20:21.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:20:21.47$vc4f8/vb=3,4 2006.161.07:20:21.47#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:20:21.47#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:20:21.47#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:21.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:21.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:21.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:21.53#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:20:21.53#ibcon#first serial, iclass 10, count 2 2006.161.07:20:21.53#ibcon#enter sib2, iclass 10, count 2 2006.161.07:20:21.53#ibcon#flushed, iclass 10, count 2 2006.161.07:20:21.53#ibcon#about to write, iclass 10, count 2 2006.161.07:20:21.53#ibcon#wrote, iclass 10, count 2 2006.161.07:20:21.53#ibcon#about to read 3, iclass 10, count 2 2006.161.07:20:21.55#ibcon#read 3, iclass 10, count 2 2006.161.07:20:21.55#ibcon#about to read 4, iclass 10, count 2 2006.161.07:20:21.55#ibcon#read 4, iclass 10, count 2 2006.161.07:20:21.55#ibcon#about to read 5, iclass 10, count 2 2006.161.07:20:21.55#ibcon#read 5, iclass 10, count 2 2006.161.07:20:21.55#ibcon#about to read 6, iclass 10, count 2 2006.161.07:20:21.55#ibcon#read 6, iclass 10, count 2 2006.161.07:20:21.55#ibcon#end of sib2, iclass 10, count 2 2006.161.07:20:21.55#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:20:21.55#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:20:21.55#ibcon#[27=AT03-04\r\n] 2006.161.07:20:21.55#ibcon#*before write, iclass 10, count 2 2006.161.07:20:21.55#ibcon#enter sib2, iclass 10, count 2 2006.161.07:20:21.55#ibcon#flushed, iclass 10, count 2 2006.161.07:20:21.55#ibcon#about to write, iclass 10, count 2 2006.161.07:20:21.55#ibcon#wrote, iclass 10, count 2 2006.161.07:20:21.55#ibcon#about to read 3, iclass 10, count 2 2006.161.07:20:21.58#ibcon#read 3, iclass 10, count 2 2006.161.07:20:21.58#ibcon#about to read 4, iclass 10, count 2 2006.161.07:20:21.58#ibcon#read 4, iclass 10, count 2 2006.161.07:20:21.58#ibcon#about to read 5, iclass 10, count 2 2006.161.07:20:21.58#ibcon#read 5, iclass 10, count 2 2006.161.07:20:21.58#ibcon#about to read 6, iclass 10, count 2 2006.161.07:20:21.58#ibcon#read 6, iclass 10, count 2 2006.161.07:20:21.58#ibcon#end of sib2, iclass 10, count 2 2006.161.07:20:21.58#ibcon#*after write, iclass 10, count 2 2006.161.07:20:21.58#ibcon#*before return 0, iclass 10, count 2 2006.161.07:20:21.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:21.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:20:21.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:20:21.58#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:21.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:21.70#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:21.70#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:21.70#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:20:21.70#ibcon#first serial, iclass 10, count 0 2006.161.07:20:21.70#ibcon#enter sib2, iclass 10, count 0 2006.161.07:20:21.70#ibcon#flushed, iclass 10, count 0 2006.161.07:20:21.70#ibcon#about to write, iclass 10, count 0 2006.161.07:20:21.70#ibcon#wrote, iclass 10, count 0 2006.161.07:20:21.70#ibcon#about to read 3, iclass 10, count 0 2006.161.07:20:21.72#ibcon#read 3, iclass 10, count 0 2006.161.07:20:21.72#ibcon#about to read 4, iclass 10, count 0 2006.161.07:20:21.72#ibcon#read 4, iclass 10, count 0 2006.161.07:20:21.72#ibcon#about to read 5, iclass 10, count 0 2006.161.07:20:21.72#ibcon#read 5, iclass 10, count 0 2006.161.07:20:21.72#ibcon#about to read 6, iclass 10, count 0 2006.161.07:20:21.72#ibcon#read 6, iclass 10, count 0 2006.161.07:20:21.72#ibcon#end of sib2, iclass 10, count 0 2006.161.07:20:21.72#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:20:21.72#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:20:21.72#ibcon#[27=USB\r\n] 2006.161.07:20:21.72#ibcon#*before write, iclass 10, count 0 2006.161.07:20:21.72#ibcon#enter sib2, iclass 10, count 0 2006.161.07:20:21.72#ibcon#flushed, iclass 10, count 0 2006.161.07:20:21.72#ibcon#about to write, iclass 10, count 0 2006.161.07:20:21.72#ibcon#wrote, iclass 10, count 0 2006.161.07:20:21.72#ibcon#about to read 3, iclass 10, count 0 2006.161.07:20:21.75#ibcon#read 3, iclass 10, count 0 2006.161.07:20:21.75#ibcon#about to read 4, iclass 10, count 0 2006.161.07:20:21.75#ibcon#read 4, iclass 10, count 0 2006.161.07:20:21.75#ibcon#about to read 5, iclass 10, count 0 2006.161.07:20:21.75#ibcon#read 5, iclass 10, count 0 2006.161.07:20:21.75#ibcon#about to read 6, iclass 10, count 0 2006.161.07:20:21.75#ibcon#read 6, iclass 10, count 0 2006.161.07:20:21.75#ibcon#end of sib2, iclass 10, count 0 2006.161.07:20:21.75#ibcon#*after write, iclass 10, count 0 2006.161.07:20:21.75#ibcon#*before return 0, iclass 10, count 0 2006.161.07:20:21.75#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:21.75#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:20:21.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:20:21.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:20:21.75$vc4f8/vblo=4,712.99 2006.161.07:20:21.75#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:20:21.75#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:20:21.75#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:21.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:21.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:21.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:21.75#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:20:21.75#ibcon#first serial, iclass 12, count 0 2006.161.07:20:21.75#ibcon#enter sib2, iclass 12, count 0 2006.161.07:20:21.75#ibcon#flushed, iclass 12, count 0 2006.161.07:20:21.75#ibcon#about to write, iclass 12, count 0 2006.161.07:20:21.75#ibcon#wrote, iclass 12, count 0 2006.161.07:20:21.75#ibcon#about to read 3, iclass 12, count 0 2006.161.07:20:21.77#ibcon#read 3, iclass 12, count 0 2006.161.07:20:21.77#ibcon#about to read 4, iclass 12, count 0 2006.161.07:20:21.77#ibcon#read 4, iclass 12, count 0 2006.161.07:20:21.77#ibcon#about to read 5, iclass 12, count 0 2006.161.07:20:21.77#ibcon#read 5, iclass 12, count 0 2006.161.07:20:21.77#ibcon#about to read 6, iclass 12, count 0 2006.161.07:20:21.77#ibcon#read 6, iclass 12, count 0 2006.161.07:20:21.77#ibcon#end of sib2, iclass 12, count 0 2006.161.07:20:21.77#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:20:21.77#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:20:21.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:20:21.77#ibcon#*before write, iclass 12, count 0 2006.161.07:20:21.77#ibcon#enter sib2, iclass 12, count 0 2006.161.07:20:21.77#ibcon#flushed, iclass 12, count 0 2006.161.07:20:21.77#ibcon#about to write, iclass 12, count 0 2006.161.07:20:21.77#ibcon#wrote, iclass 12, count 0 2006.161.07:20:21.77#ibcon#about to read 3, iclass 12, count 0 2006.161.07:20:21.81#ibcon#read 3, iclass 12, count 0 2006.161.07:20:21.81#ibcon#about to read 4, iclass 12, count 0 2006.161.07:20:21.81#ibcon#read 4, iclass 12, count 0 2006.161.07:20:21.81#ibcon#about to read 5, iclass 12, count 0 2006.161.07:20:21.81#ibcon#read 5, iclass 12, count 0 2006.161.07:20:21.81#ibcon#about to read 6, iclass 12, count 0 2006.161.07:20:21.81#ibcon#read 6, iclass 12, count 0 2006.161.07:20:21.81#ibcon#end of sib2, iclass 12, count 0 2006.161.07:20:21.81#ibcon#*after write, iclass 12, count 0 2006.161.07:20:21.81#ibcon#*before return 0, iclass 12, count 0 2006.161.07:20:21.81#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:21.81#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:20:21.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:20:21.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:20:21.81$vc4f8/vb=4,4 2006.161.07:20:21.81#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:20:21.81#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:20:21.81#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:21.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:21.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:21.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:21.87#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:20:21.87#ibcon#first serial, iclass 14, count 2 2006.161.07:20:21.87#ibcon#enter sib2, iclass 14, count 2 2006.161.07:20:21.87#ibcon#flushed, iclass 14, count 2 2006.161.07:20:21.87#ibcon#about to write, iclass 14, count 2 2006.161.07:20:21.87#ibcon#wrote, iclass 14, count 2 2006.161.07:20:21.87#ibcon#about to read 3, iclass 14, count 2 2006.161.07:20:21.89#ibcon#read 3, iclass 14, count 2 2006.161.07:20:21.89#ibcon#about to read 4, iclass 14, count 2 2006.161.07:20:21.89#ibcon#read 4, iclass 14, count 2 2006.161.07:20:21.89#ibcon#about to read 5, iclass 14, count 2 2006.161.07:20:21.89#ibcon#read 5, iclass 14, count 2 2006.161.07:20:21.89#ibcon#about to read 6, iclass 14, count 2 2006.161.07:20:21.89#ibcon#read 6, iclass 14, count 2 2006.161.07:20:21.89#ibcon#end of sib2, iclass 14, count 2 2006.161.07:20:21.89#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:20:21.89#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:20:21.89#ibcon#[27=AT04-04\r\n] 2006.161.07:20:21.89#ibcon#*before write, iclass 14, count 2 2006.161.07:20:21.89#ibcon#enter sib2, iclass 14, count 2 2006.161.07:20:21.89#ibcon#flushed, iclass 14, count 2 2006.161.07:20:21.89#ibcon#about to write, iclass 14, count 2 2006.161.07:20:21.89#ibcon#wrote, iclass 14, count 2 2006.161.07:20:21.89#ibcon#about to read 3, iclass 14, count 2 2006.161.07:20:21.92#ibcon#read 3, iclass 14, count 2 2006.161.07:20:21.92#ibcon#about to read 4, iclass 14, count 2 2006.161.07:20:21.92#ibcon#read 4, iclass 14, count 2 2006.161.07:20:21.92#ibcon#about to read 5, iclass 14, count 2 2006.161.07:20:21.92#ibcon#read 5, iclass 14, count 2 2006.161.07:20:21.92#ibcon#about to read 6, iclass 14, count 2 2006.161.07:20:21.92#ibcon#read 6, iclass 14, count 2 2006.161.07:20:21.92#ibcon#end of sib2, iclass 14, count 2 2006.161.07:20:21.92#ibcon#*after write, iclass 14, count 2 2006.161.07:20:21.92#ibcon#*before return 0, iclass 14, count 2 2006.161.07:20:21.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:21.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:20:21.92#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:20:21.92#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:21.92#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:22.04#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:22.04#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:22.04#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:20:22.04#ibcon#first serial, iclass 14, count 0 2006.161.07:20:22.04#ibcon#enter sib2, iclass 14, count 0 2006.161.07:20:22.04#ibcon#flushed, iclass 14, count 0 2006.161.07:20:22.04#ibcon#about to write, iclass 14, count 0 2006.161.07:20:22.04#ibcon#wrote, iclass 14, count 0 2006.161.07:20:22.04#ibcon#about to read 3, iclass 14, count 0 2006.161.07:20:22.06#ibcon#read 3, iclass 14, count 0 2006.161.07:20:22.06#ibcon#about to read 4, iclass 14, count 0 2006.161.07:20:22.06#ibcon#read 4, iclass 14, count 0 2006.161.07:20:22.06#ibcon#about to read 5, iclass 14, count 0 2006.161.07:20:22.06#ibcon#read 5, iclass 14, count 0 2006.161.07:20:22.06#ibcon#about to read 6, iclass 14, count 0 2006.161.07:20:22.06#ibcon#read 6, iclass 14, count 0 2006.161.07:20:22.06#ibcon#end of sib2, iclass 14, count 0 2006.161.07:20:22.06#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:20:22.06#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:20:22.06#ibcon#[27=USB\r\n] 2006.161.07:20:22.06#ibcon#*before write, iclass 14, count 0 2006.161.07:20:22.06#ibcon#enter sib2, iclass 14, count 0 2006.161.07:20:22.06#ibcon#flushed, iclass 14, count 0 2006.161.07:20:22.06#ibcon#about to write, iclass 14, count 0 2006.161.07:20:22.06#ibcon#wrote, iclass 14, count 0 2006.161.07:20:22.06#ibcon#about to read 3, iclass 14, count 0 2006.161.07:20:22.09#ibcon#read 3, iclass 14, count 0 2006.161.07:20:22.09#ibcon#about to read 4, iclass 14, count 0 2006.161.07:20:22.09#ibcon#read 4, iclass 14, count 0 2006.161.07:20:22.09#ibcon#about to read 5, iclass 14, count 0 2006.161.07:20:22.09#ibcon#read 5, iclass 14, count 0 2006.161.07:20:22.09#ibcon#about to read 6, iclass 14, count 0 2006.161.07:20:22.09#ibcon#read 6, iclass 14, count 0 2006.161.07:20:22.09#ibcon#end of sib2, iclass 14, count 0 2006.161.07:20:22.09#ibcon#*after write, iclass 14, count 0 2006.161.07:20:22.09#ibcon#*before return 0, iclass 14, count 0 2006.161.07:20:22.09#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:22.09#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:20:22.09#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:20:22.09#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:20:22.09$vc4f8/vblo=5,744.99 2006.161.07:20:22.09#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:20:22.09#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:20:22.09#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:22.09#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:22.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:22.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:22.09#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:20:22.09#ibcon#first serial, iclass 16, count 0 2006.161.07:20:22.09#ibcon#enter sib2, iclass 16, count 0 2006.161.07:20:22.09#ibcon#flushed, iclass 16, count 0 2006.161.07:20:22.09#ibcon#about to write, iclass 16, count 0 2006.161.07:20:22.09#ibcon#wrote, iclass 16, count 0 2006.161.07:20:22.09#ibcon#about to read 3, iclass 16, count 0 2006.161.07:20:22.11#ibcon#read 3, iclass 16, count 0 2006.161.07:20:22.11#ibcon#about to read 4, iclass 16, count 0 2006.161.07:20:22.11#ibcon#read 4, iclass 16, count 0 2006.161.07:20:22.11#ibcon#about to read 5, iclass 16, count 0 2006.161.07:20:22.11#ibcon#read 5, iclass 16, count 0 2006.161.07:20:22.11#ibcon#about to read 6, iclass 16, count 0 2006.161.07:20:22.11#ibcon#read 6, iclass 16, count 0 2006.161.07:20:22.11#ibcon#end of sib2, iclass 16, count 0 2006.161.07:20:22.11#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:20:22.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:20:22.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:20:22.11#ibcon#*before write, iclass 16, count 0 2006.161.07:20:22.11#ibcon#enter sib2, iclass 16, count 0 2006.161.07:20:22.11#ibcon#flushed, iclass 16, count 0 2006.161.07:20:22.11#ibcon#about to write, iclass 16, count 0 2006.161.07:20:22.11#ibcon#wrote, iclass 16, count 0 2006.161.07:20:22.11#ibcon#about to read 3, iclass 16, count 0 2006.161.07:20:22.15#ibcon#read 3, iclass 16, count 0 2006.161.07:20:22.15#ibcon#about to read 4, iclass 16, count 0 2006.161.07:20:22.15#ibcon#read 4, iclass 16, count 0 2006.161.07:20:22.15#ibcon#about to read 5, iclass 16, count 0 2006.161.07:20:22.15#ibcon#read 5, iclass 16, count 0 2006.161.07:20:22.15#ibcon#about to read 6, iclass 16, count 0 2006.161.07:20:22.15#ibcon#read 6, iclass 16, count 0 2006.161.07:20:22.15#ibcon#end of sib2, iclass 16, count 0 2006.161.07:20:22.15#ibcon#*after write, iclass 16, count 0 2006.161.07:20:22.15#ibcon#*before return 0, iclass 16, count 0 2006.161.07:20:22.15#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:22.15#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:20:22.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:20:22.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:20:22.15$vc4f8/vb=5,4 2006.161.07:20:22.15#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:20:22.15#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:20:22.15#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:22.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:22.21#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:22.21#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:22.21#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:20:22.21#ibcon#first serial, iclass 18, count 2 2006.161.07:20:22.21#ibcon#enter sib2, iclass 18, count 2 2006.161.07:20:22.21#ibcon#flushed, iclass 18, count 2 2006.161.07:20:22.21#ibcon#about to write, iclass 18, count 2 2006.161.07:20:22.21#ibcon#wrote, iclass 18, count 2 2006.161.07:20:22.21#ibcon#about to read 3, iclass 18, count 2 2006.161.07:20:22.23#ibcon#read 3, iclass 18, count 2 2006.161.07:20:22.23#ibcon#about to read 4, iclass 18, count 2 2006.161.07:20:22.23#ibcon#read 4, iclass 18, count 2 2006.161.07:20:22.23#ibcon#about to read 5, iclass 18, count 2 2006.161.07:20:22.23#ibcon#read 5, iclass 18, count 2 2006.161.07:20:22.23#ibcon#about to read 6, iclass 18, count 2 2006.161.07:20:22.23#ibcon#read 6, iclass 18, count 2 2006.161.07:20:22.23#ibcon#end of sib2, iclass 18, count 2 2006.161.07:20:22.23#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:20:22.23#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:20:22.23#ibcon#[27=AT05-04\r\n] 2006.161.07:20:22.23#ibcon#*before write, iclass 18, count 2 2006.161.07:20:22.23#ibcon#enter sib2, iclass 18, count 2 2006.161.07:20:22.23#ibcon#flushed, iclass 18, count 2 2006.161.07:20:22.23#ibcon#about to write, iclass 18, count 2 2006.161.07:20:22.23#ibcon#wrote, iclass 18, count 2 2006.161.07:20:22.23#ibcon#about to read 3, iclass 18, count 2 2006.161.07:20:22.26#ibcon#read 3, iclass 18, count 2 2006.161.07:20:22.26#ibcon#about to read 4, iclass 18, count 2 2006.161.07:20:22.26#ibcon#read 4, iclass 18, count 2 2006.161.07:20:22.26#ibcon#about to read 5, iclass 18, count 2 2006.161.07:20:22.26#ibcon#read 5, iclass 18, count 2 2006.161.07:20:22.26#ibcon#about to read 6, iclass 18, count 2 2006.161.07:20:22.26#ibcon#read 6, iclass 18, count 2 2006.161.07:20:22.26#ibcon#end of sib2, iclass 18, count 2 2006.161.07:20:22.26#ibcon#*after write, iclass 18, count 2 2006.161.07:20:22.26#ibcon#*before return 0, iclass 18, count 2 2006.161.07:20:22.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:22.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:20:22.26#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:20:22.26#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:22.26#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:22.38#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:22.38#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:22.38#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:20:22.38#ibcon#first serial, iclass 18, count 0 2006.161.07:20:22.38#ibcon#enter sib2, iclass 18, count 0 2006.161.07:20:22.38#ibcon#flushed, iclass 18, count 0 2006.161.07:20:22.38#ibcon#about to write, iclass 18, count 0 2006.161.07:20:22.38#ibcon#wrote, iclass 18, count 0 2006.161.07:20:22.38#ibcon#about to read 3, iclass 18, count 0 2006.161.07:20:22.40#ibcon#read 3, iclass 18, count 0 2006.161.07:20:22.40#ibcon#about to read 4, iclass 18, count 0 2006.161.07:20:22.40#ibcon#read 4, iclass 18, count 0 2006.161.07:20:22.40#ibcon#about to read 5, iclass 18, count 0 2006.161.07:20:22.40#ibcon#read 5, iclass 18, count 0 2006.161.07:20:22.40#ibcon#about to read 6, iclass 18, count 0 2006.161.07:20:22.40#ibcon#read 6, iclass 18, count 0 2006.161.07:20:22.40#ibcon#end of sib2, iclass 18, count 0 2006.161.07:20:22.40#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:20:22.40#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:20:22.40#ibcon#[27=USB\r\n] 2006.161.07:20:22.40#ibcon#*before write, iclass 18, count 0 2006.161.07:20:22.40#ibcon#enter sib2, iclass 18, count 0 2006.161.07:20:22.40#ibcon#flushed, iclass 18, count 0 2006.161.07:20:22.40#ibcon#about to write, iclass 18, count 0 2006.161.07:20:22.40#ibcon#wrote, iclass 18, count 0 2006.161.07:20:22.40#ibcon#about to read 3, iclass 18, count 0 2006.161.07:20:22.43#ibcon#read 3, iclass 18, count 0 2006.161.07:20:22.43#ibcon#about to read 4, iclass 18, count 0 2006.161.07:20:22.43#ibcon#read 4, iclass 18, count 0 2006.161.07:20:22.43#ibcon#about to read 5, iclass 18, count 0 2006.161.07:20:22.43#ibcon#read 5, iclass 18, count 0 2006.161.07:20:22.43#ibcon#about to read 6, iclass 18, count 0 2006.161.07:20:22.43#ibcon#read 6, iclass 18, count 0 2006.161.07:20:22.43#ibcon#end of sib2, iclass 18, count 0 2006.161.07:20:22.43#ibcon#*after write, iclass 18, count 0 2006.161.07:20:22.43#ibcon#*before return 0, iclass 18, count 0 2006.161.07:20:22.43#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:22.43#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:20:22.43#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:20:22.43#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:20:22.43$vc4f8/vblo=6,752.99 2006.161.07:20:22.43#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:20:22.43#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:20:22.43#ibcon#ireg 17 cls_cnt 0 2006.161.07:20:22.43#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:22.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:22.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:22.43#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:20:22.43#ibcon#first serial, iclass 20, count 0 2006.161.07:20:22.43#ibcon#enter sib2, iclass 20, count 0 2006.161.07:20:22.43#ibcon#flushed, iclass 20, count 0 2006.161.07:20:22.43#ibcon#about to write, iclass 20, count 0 2006.161.07:20:22.43#ibcon#wrote, iclass 20, count 0 2006.161.07:20:22.43#ibcon#about to read 3, iclass 20, count 0 2006.161.07:20:22.45#ibcon#read 3, iclass 20, count 0 2006.161.07:20:22.45#ibcon#about to read 4, iclass 20, count 0 2006.161.07:20:22.45#ibcon#read 4, iclass 20, count 0 2006.161.07:20:22.45#ibcon#about to read 5, iclass 20, count 0 2006.161.07:20:22.45#ibcon#read 5, iclass 20, count 0 2006.161.07:20:22.45#ibcon#about to read 6, iclass 20, count 0 2006.161.07:20:22.45#ibcon#read 6, iclass 20, count 0 2006.161.07:20:22.45#ibcon#end of sib2, iclass 20, count 0 2006.161.07:20:22.45#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:20:22.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:20:22.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:20:22.45#ibcon#*before write, iclass 20, count 0 2006.161.07:20:22.45#ibcon#enter sib2, iclass 20, count 0 2006.161.07:20:22.45#ibcon#flushed, iclass 20, count 0 2006.161.07:20:22.45#ibcon#about to write, iclass 20, count 0 2006.161.07:20:22.45#ibcon#wrote, iclass 20, count 0 2006.161.07:20:22.45#ibcon#about to read 3, iclass 20, count 0 2006.161.07:20:22.49#ibcon#read 3, iclass 20, count 0 2006.161.07:20:22.49#ibcon#about to read 4, iclass 20, count 0 2006.161.07:20:22.49#ibcon#read 4, iclass 20, count 0 2006.161.07:20:22.49#ibcon#about to read 5, iclass 20, count 0 2006.161.07:20:22.49#ibcon#read 5, iclass 20, count 0 2006.161.07:20:22.49#ibcon#about to read 6, iclass 20, count 0 2006.161.07:20:22.49#ibcon#read 6, iclass 20, count 0 2006.161.07:20:22.49#ibcon#end of sib2, iclass 20, count 0 2006.161.07:20:22.49#ibcon#*after write, iclass 20, count 0 2006.161.07:20:22.49#ibcon#*before return 0, iclass 20, count 0 2006.161.07:20:22.49#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:22.49#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:20:22.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:20:22.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:20:22.49$vc4f8/vb=6,4 2006.161.07:20:22.49#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:20:22.49#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:20:22.49#ibcon#ireg 11 cls_cnt 2 2006.161.07:20:22.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:22.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:22.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:22.55#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:20:22.55#ibcon#first serial, iclass 22, count 2 2006.161.07:20:22.55#ibcon#enter sib2, iclass 22, count 2 2006.161.07:20:22.55#ibcon#flushed, iclass 22, count 2 2006.161.07:20:22.55#ibcon#about to write, iclass 22, count 2 2006.161.07:20:22.55#ibcon#wrote, iclass 22, count 2 2006.161.07:20:22.55#ibcon#about to read 3, iclass 22, count 2 2006.161.07:20:22.57#ibcon#read 3, iclass 22, count 2 2006.161.07:20:22.57#ibcon#about to read 4, iclass 22, count 2 2006.161.07:20:22.57#ibcon#read 4, iclass 22, count 2 2006.161.07:20:22.57#ibcon#about to read 5, iclass 22, count 2 2006.161.07:20:22.57#ibcon#read 5, iclass 22, count 2 2006.161.07:20:22.57#ibcon#about to read 6, iclass 22, count 2 2006.161.07:20:22.57#ibcon#read 6, iclass 22, count 2 2006.161.07:20:22.57#ibcon#end of sib2, iclass 22, count 2 2006.161.07:20:22.57#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:20:22.57#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:20:22.57#ibcon#[27=AT06-04\r\n] 2006.161.07:20:22.57#ibcon#*before write, iclass 22, count 2 2006.161.07:20:22.57#ibcon#enter sib2, iclass 22, count 2 2006.161.07:20:22.57#ibcon#flushed, iclass 22, count 2 2006.161.07:20:22.57#ibcon#about to write, iclass 22, count 2 2006.161.07:20:22.57#ibcon#wrote, iclass 22, count 2 2006.161.07:20:22.57#ibcon#about to read 3, iclass 22, count 2 2006.161.07:20:22.60#ibcon#read 3, iclass 22, count 2 2006.161.07:20:22.60#ibcon#about to read 4, iclass 22, count 2 2006.161.07:20:22.60#ibcon#read 4, iclass 22, count 2 2006.161.07:20:22.60#ibcon#about to read 5, iclass 22, count 2 2006.161.07:20:22.60#ibcon#read 5, iclass 22, count 2 2006.161.07:20:22.60#ibcon#about to read 6, iclass 22, count 2 2006.161.07:20:22.60#ibcon#read 6, iclass 22, count 2 2006.161.07:20:22.60#ibcon#end of sib2, iclass 22, count 2 2006.161.07:20:22.60#ibcon#*after write, iclass 22, count 2 2006.161.07:20:22.60#ibcon#*before return 0, iclass 22, count 2 2006.161.07:20:22.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:22.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:20:22.60#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:20:22.60#ibcon#ireg 7 cls_cnt 0 2006.161.07:20:22.60#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:22.72#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:22.72#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:22.72#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:20:22.72#ibcon#first serial, iclass 22, count 0 2006.161.07:20:22.72#ibcon#enter sib2, iclass 22, count 0 2006.161.07:20:22.72#ibcon#flushed, iclass 22, count 0 2006.161.07:20:22.72#ibcon#about to write, iclass 22, count 0 2006.161.07:20:22.72#ibcon#wrote, iclass 22, count 0 2006.161.07:20:22.72#ibcon#about to read 3, iclass 22, count 0 2006.161.07:20:22.74#ibcon#read 3, iclass 22, count 0 2006.161.07:20:22.74#ibcon#about to read 4, iclass 22, count 0 2006.161.07:20:22.74#ibcon#read 4, iclass 22, count 0 2006.161.07:20:22.74#ibcon#about to read 5, iclass 22, count 0 2006.161.07:20:22.74#ibcon#read 5, iclass 22, count 0 2006.161.07:20:22.74#ibcon#about to read 6, iclass 22, count 0 2006.161.07:20:22.74#ibcon#read 6, iclass 22, count 0 2006.161.07:20:22.74#ibcon#end of sib2, iclass 22, count 0 2006.161.07:20:22.74#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:20:22.74#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:20:22.74#ibcon#[27=USB\r\n] 2006.161.07:20:22.74#ibcon#*before write, iclass 22, count 0 2006.161.07:20:22.74#ibcon#enter sib2, iclass 22, count 0 2006.161.07:20:22.74#ibcon#flushed, iclass 22, count 0 2006.161.07:20:22.74#ibcon#about to write, iclass 22, count 0 2006.161.07:20:22.74#ibcon#wrote, iclass 22, count 0 2006.161.07:20:22.74#ibcon#about to read 3, iclass 22, count 0 2006.161.07:20:22.77#ibcon#read 3, iclass 22, count 0 2006.161.07:20:22.77#ibcon#about to read 4, iclass 22, count 0 2006.161.07:20:22.77#ibcon#read 4, iclass 22, count 0 2006.161.07:20:22.77#ibcon#about to read 5, iclass 22, count 0 2006.161.07:20:22.77#ibcon#read 5, iclass 22, count 0 2006.161.07:20:22.77#ibcon#about to read 6, iclass 22, count 0 2006.161.07:20:22.77#ibcon#read 6, iclass 22, count 0 2006.161.07:20:22.77#ibcon#end of sib2, iclass 22, count 0 2006.161.07:20:22.77#ibcon#*after write, iclass 22, count 0 2006.161.07:20:22.77#ibcon#*before return 0, iclass 22, count 0 2006.161.07:20:22.77#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:22.77#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:20:22.77#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:20:22.77#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:20:22.77$vc4f8/vabw=wide 2006.161.07:20:22.77#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:20:22.77#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:20:22.77#ibcon#ireg 8 cls_cnt 0 2006.161.07:20:22.77#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:22.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:22.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:22.77#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:20:22.77#ibcon#first serial, iclass 24, count 0 2006.161.07:20:22.77#ibcon#enter sib2, iclass 24, count 0 2006.161.07:20:22.77#ibcon#flushed, iclass 24, count 0 2006.161.07:20:22.77#ibcon#about to write, iclass 24, count 0 2006.161.07:20:22.77#ibcon#wrote, iclass 24, count 0 2006.161.07:20:22.77#ibcon#about to read 3, iclass 24, count 0 2006.161.07:20:22.79#ibcon#read 3, iclass 24, count 0 2006.161.07:20:22.79#ibcon#about to read 4, iclass 24, count 0 2006.161.07:20:22.79#ibcon#read 4, iclass 24, count 0 2006.161.07:20:22.79#ibcon#about to read 5, iclass 24, count 0 2006.161.07:20:22.79#ibcon#read 5, iclass 24, count 0 2006.161.07:20:22.79#ibcon#about to read 6, iclass 24, count 0 2006.161.07:20:22.79#ibcon#read 6, iclass 24, count 0 2006.161.07:20:22.79#ibcon#end of sib2, iclass 24, count 0 2006.161.07:20:22.79#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:20:22.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:20:22.79#ibcon#[25=BW32\r\n] 2006.161.07:20:22.79#ibcon#*before write, iclass 24, count 0 2006.161.07:20:22.79#ibcon#enter sib2, iclass 24, count 0 2006.161.07:20:22.79#ibcon#flushed, iclass 24, count 0 2006.161.07:20:22.79#ibcon#about to write, iclass 24, count 0 2006.161.07:20:22.79#ibcon#wrote, iclass 24, count 0 2006.161.07:20:22.79#ibcon#about to read 3, iclass 24, count 0 2006.161.07:20:22.82#ibcon#read 3, iclass 24, count 0 2006.161.07:20:22.82#ibcon#about to read 4, iclass 24, count 0 2006.161.07:20:22.82#ibcon#read 4, iclass 24, count 0 2006.161.07:20:22.82#ibcon#about to read 5, iclass 24, count 0 2006.161.07:20:22.82#ibcon#read 5, iclass 24, count 0 2006.161.07:20:22.82#ibcon#about to read 6, iclass 24, count 0 2006.161.07:20:22.82#ibcon#read 6, iclass 24, count 0 2006.161.07:20:22.82#ibcon#end of sib2, iclass 24, count 0 2006.161.07:20:22.82#ibcon#*after write, iclass 24, count 0 2006.161.07:20:22.82#ibcon#*before return 0, iclass 24, count 0 2006.161.07:20:22.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:22.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:20:22.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:20:22.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:20:22.82$vc4f8/vbbw=wide 2006.161.07:20:22.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:20:22.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:20:22.82#ibcon#ireg 8 cls_cnt 0 2006.161.07:20:22.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:20:22.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:20:22.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:20:22.89#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:20:22.89#ibcon#first serial, iclass 26, count 0 2006.161.07:20:22.89#ibcon#enter sib2, iclass 26, count 0 2006.161.07:20:22.89#ibcon#flushed, iclass 26, count 0 2006.161.07:20:22.89#ibcon#about to write, iclass 26, count 0 2006.161.07:20:22.89#ibcon#wrote, iclass 26, count 0 2006.161.07:20:22.89#ibcon#about to read 3, iclass 26, count 0 2006.161.07:20:22.91#ibcon#read 3, iclass 26, count 0 2006.161.07:20:22.91#ibcon#about to read 4, iclass 26, count 0 2006.161.07:20:22.91#ibcon#read 4, iclass 26, count 0 2006.161.07:20:22.91#ibcon#about to read 5, iclass 26, count 0 2006.161.07:20:22.91#ibcon#read 5, iclass 26, count 0 2006.161.07:20:22.91#ibcon#about to read 6, iclass 26, count 0 2006.161.07:20:22.91#ibcon#read 6, iclass 26, count 0 2006.161.07:20:22.91#ibcon#end of sib2, iclass 26, count 0 2006.161.07:20:22.91#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:20:22.91#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:20:22.91#ibcon#[27=BW32\r\n] 2006.161.07:20:22.91#ibcon#*before write, iclass 26, count 0 2006.161.07:20:22.91#ibcon#enter sib2, iclass 26, count 0 2006.161.07:20:22.91#ibcon#flushed, iclass 26, count 0 2006.161.07:20:22.91#ibcon#about to write, iclass 26, count 0 2006.161.07:20:22.91#ibcon#wrote, iclass 26, count 0 2006.161.07:20:22.91#ibcon#about to read 3, iclass 26, count 0 2006.161.07:20:22.94#ibcon#read 3, iclass 26, count 0 2006.161.07:20:22.94#ibcon#about to read 4, iclass 26, count 0 2006.161.07:20:22.94#ibcon#read 4, iclass 26, count 0 2006.161.07:20:22.94#ibcon#about to read 5, iclass 26, count 0 2006.161.07:20:22.94#ibcon#read 5, iclass 26, count 0 2006.161.07:20:22.94#ibcon#about to read 6, iclass 26, count 0 2006.161.07:20:22.94#ibcon#read 6, iclass 26, count 0 2006.161.07:20:22.94#ibcon#end of sib2, iclass 26, count 0 2006.161.07:20:22.94#ibcon#*after write, iclass 26, count 0 2006.161.07:20:22.94#ibcon#*before return 0, iclass 26, count 0 2006.161.07:20:22.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:20:22.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:20:22.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:20:22.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:20:22.94$4f8m12a/ifd4f 2006.161.07:20:22.94&ifd4f/lo= 2006.161.07:20:22.94&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:20:22.94&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:20:22.94&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:20:22.94&ifd4f/patch= 2006.161.07:20:22.94&ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:20:22.94&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:20:22.94&ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:20:22.94$ifd4f/lo= 2006.161.07:20:22.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:20:22.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:20:22.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:20:22.94$ifd4f/patch= 2006.161.07:20:22.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:20:22.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:20:22.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:20:22.94$4f8m12a/"form=m,16.000,1:2 2006.161.07:20:22.94$4f8m12a/"tpicd 2006.161.07:20:22.94$4f8m12a/echo=off 2006.161.07:20:22.94$4f8m12a/xlog=off 2006.161.07:20:22.94:!2006.161.07:29:50 2006.161.07:20:38.14#trakl#Source acquired 2006.161.07:20:38.14#flagr#flagr/antenna,acquired 2006.161.07:29:50.00:preob 2006.161.07:29:50.00&preob/onsource 2006.161.07:29:51.14/onsource/TRACKING 2006.161.07:29:51.14:!2006.161.07:30:00 2006.161.07:30:00.00:data_valid=on 2006.161.07:30:00.00:midob 2006.161.07:30:00.00&midob/onsource 2006.161.07:30:00.00&midob/wx 2006.161.07:30:00.00&midob/cable 2006.161.07:30:00.00&midob/va 2006.161.07:30:00.00&midob/valo 2006.161.07:30:00.00&midob/vb 2006.161.07:30:00.00&midob/vblo 2006.161.07:30:00.00&midob/vabw 2006.161.07:30:00.00&midob/vbbw 2006.161.07:30:00.00&midob/"form 2006.161.07:30:00.00&midob/xfe 2006.161.07:30:00.00&midob/ifatt 2006.161.07:30:00.00&midob/clockoff 2006.161.07:30:00.00&midob/sy=logmail 2006.161.07:30:00.00&midob/"sy=run setcl adapt & 2006.161.07:30:00.14/onsource/TRACKING 2006.161.07:30:00.14/wx/24.24,1001.9,84 2006.161.07:30:00.29/cable/+6.4975E-03 2006.161.07:30:01.38/va/01,08,usb,yes,30,32 2006.161.07:30:01.38/va/02,07,usb,yes,30,31 2006.161.07:30:01.38/va/03,06,usb,yes,32,32 2006.161.07:30:01.38/va/04,07,usb,yes,31,33 2006.161.07:30:01.38/va/05,07,usb,yes,31,33 2006.161.07:30:01.38/va/06,06,usb,yes,30,30 2006.161.07:30:01.38/va/07,06,usb,yes,30,30 2006.161.07:30:01.38/va/08,07,usb,yes,29,28 2006.161.07:30:01.61/valo/01,532.99,yes,locked 2006.161.07:30:01.61/valo/02,572.99,yes,locked 2006.161.07:30:01.61/valo/03,672.99,yes,locked 2006.161.07:30:01.61/valo/04,832.99,yes,locked 2006.161.07:30:01.61/valo/05,652.99,yes,locked 2006.161.07:30:01.61/valo/06,772.99,yes,locked 2006.161.07:30:01.61/valo/07,832.99,yes,locked 2006.161.07:30:01.61/valo/08,852.99,yes,locked 2006.161.07:30:02.70/vb/01,04,usb,yes,30,28 2006.161.07:30:02.70/vb/02,04,usb,yes,31,33 2006.161.07:30:02.70/vb/03,04,usb,yes,28,32 2006.161.07:30:02.70/vb/04,04,usb,yes,29,29 2006.161.07:30:02.70/vb/05,04,usb,yes,27,31 2006.161.07:30:02.70/vb/06,04,usb,yes,28,31 2006.161.07:30:02.70/vb/07,04,usb,yes,30,30 2006.161.07:30:02.70/vb/08,04,usb,yes,28,31 2006.161.07:30:02.93/vblo/01,632.99,yes,locked 2006.161.07:30:02.93/vblo/02,640.99,yes,locked 2006.161.07:30:02.93/vblo/03,656.99,yes,locked 2006.161.07:30:02.93/vblo/04,712.99,yes,locked 2006.161.07:30:02.93/vblo/05,744.99,yes,locked 2006.161.07:30:02.93/vblo/06,752.99,yes,locked 2006.161.07:30:02.93/vblo/07,734.99,yes,locked 2006.161.07:30:02.93/vblo/08,744.99,yes,locked 2006.161.07:30:03.08/vabw/8 2006.161.07:30:03.23/vbbw/8 2006.161.07:30:03.32/xfe/off,on,15.0 2006.161.07:30:03.70/ifatt/23,28,28,28 2006.161.07:30:04.07/fmout-gps/S +4.47E-07 2006.161.07:30:04.16:!2006.161.07:31:00 2006.161.07:31:00.01:data_valid=off 2006.161.07:31:00.02:postob 2006.161.07:31:00.02&postob/cable 2006.161.07:31:00.03&postob/wx 2006.161.07:31:00.03&postob/clockoff 2006.161.07:31:00.14/cable/+6.4986E-03 2006.161.07:31:00.15/wx/24.22,1001.9,84 2006.161.07:31:00.21/fmout-gps/S +4.46E-07 2006.161.07:31:00.22:scan_name=161-0733,k06161,60 2006.161.07:31:00.22:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.161.07:31:01.13#flagr#flagr/antenna,new-source 2006.161.07:31:01.14:checkk5 2006.161.07:31:01.14&checkk5/chk_autoobs=1 2006.161.07:31:01.15&checkk5/chk_autoobs=2 2006.161.07:31:01.15&checkk5/chk_autoobs=3 2006.161.07:31:01.15&checkk5/chk_autoobs=4 2006.161.07:31:01.16&checkk5/chk_obsdata=1 2006.161.07:31:01.16&checkk5/chk_obsdata=2 2006.161.07:31:01.16&checkk5/chk_obsdata=3 2006.161.07:31:01.16&checkk5/chk_obsdata=4 2006.161.07:31:01.16&checkk5/k5log=1 2006.161.07:31:01.16&checkk5/k5log=2 2006.161.07:31:01.16&checkk5/k5log=3 2006.161.07:31:01.16&checkk5/k5log=4 2006.161.07:31:01.16&checkk5/obsinfo 2006.161.07:31:01.62/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:31:02.02/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:31:02.46/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:31:02.96/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:31:03.39/chk_obsdata//k5ts1/T1610730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:31:03.79/chk_obsdata//k5ts2/T1610730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:31:04.18/chk_obsdata//k5ts3/T1610730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:31:04.60/chk_obsdata//k5ts4/T1610730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:31:05.71/k5log//k5ts1_log_newline 2006.161.07:31:06.51/k5log//k5ts2_log_newline 2006.161.07:31:07.73/k5log//k5ts3_log_newline 2006.161.07:31:08.53/k5log//k5ts4_log_newline 2006.161.07:31:08.55/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:31:08.55:4f8m12a=1 2006.161.07:31:08.55$4f8m12a/echo=on 2006.161.07:31:08.55$4f8m12a/pcalon 2006.161.07:31:08.55$pcalon/"no phase cal control is implemented here 2006.161.07:31:08.55$4f8m12a/"tpicd=stop 2006.161.07:31:08.55$4f8m12a/vc4f8 2006.161.07:31:08.55$vc4f8/valo=1,532.99 2006.161.07:31:08.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:31:08.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:31:08.55#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:08.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:08.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:08.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:08.55#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:31:08.55#ibcon#first serial, iclass 33, count 0 2006.161.07:31:08.55#ibcon#enter sib2, iclass 33, count 0 2006.161.07:31:08.55#ibcon#flushed, iclass 33, count 0 2006.161.07:31:08.56#ibcon#about to write, iclass 33, count 0 2006.161.07:31:08.56#ibcon#wrote, iclass 33, count 0 2006.161.07:31:08.56#ibcon#about to read 3, iclass 33, count 0 2006.161.07:31:08.60#ibcon#read 3, iclass 33, count 0 2006.161.07:31:08.60#ibcon#about to read 4, iclass 33, count 0 2006.161.07:31:08.60#ibcon#read 4, iclass 33, count 0 2006.161.07:31:08.60#ibcon#about to read 5, iclass 33, count 0 2006.161.07:31:08.60#ibcon#read 5, iclass 33, count 0 2006.161.07:31:08.60#ibcon#about to read 6, iclass 33, count 0 2006.161.07:31:08.60#ibcon#read 6, iclass 33, count 0 2006.161.07:31:08.60#ibcon#end of sib2, iclass 33, count 0 2006.161.07:31:08.60#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:31:08.60#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:31:08.60#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:31:08.60#ibcon#*before write, iclass 33, count 0 2006.161.07:31:08.60#ibcon#enter sib2, iclass 33, count 0 2006.161.07:31:08.60#ibcon#flushed, iclass 33, count 0 2006.161.07:31:08.60#ibcon#about to write, iclass 33, count 0 2006.161.07:31:08.60#ibcon#wrote, iclass 33, count 0 2006.161.07:31:08.60#ibcon#about to read 3, iclass 33, count 0 2006.161.07:31:08.64#ibcon#read 3, iclass 33, count 0 2006.161.07:31:08.64#ibcon#about to read 4, iclass 33, count 0 2006.161.07:31:08.64#ibcon#read 4, iclass 33, count 0 2006.161.07:31:08.64#ibcon#about to read 5, iclass 33, count 0 2006.161.07:31:08.64#ibcon#read 5, iclass 33, count 0 2006.161.07:31:08.64#ibcon#about to read 6, iclass 33, count 0 2006.161.07:31:08.64#ibcon#read 6, iclass 33, count 0 2006.161.07:31:08.64#ibcon#end of sib2, iclass 33, count 0 2006.161.07:31:08.64#ibcon#*after write, iclass 33, count 0 2006.161.07:31:08.64#ibcon#*before return 0, iclass 33, count 0 2006.161.07:31:08.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:08.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:08.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:31:08.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:31:08.64$vc4f8/va=1,8 2006.161.07:31:08.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.07:31:08.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.07:31:08.64#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:08.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:08.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:08.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:08.64#ibcon#enter wrdev, iclass 35, count 2 2006.161.07:31:08.64#ibcon#first serial, iclass 35, count 2 2006.161.07:31:08.64#ibcon#enter sib2, iclass 35, count 2 2006.161.07:31:08.64#ibcon#flushed, iclass 35, count 2 2006.161.07:31:08.64#ibcon#about to write, iclass 35, count 2 2006.161.07:31:08.64#ibcon#wrote, iclass 35, count 2 2006.161.07:31:08.64#ibcon#about to read 3, iclass 35, count 2 2006.161.07:31:08.67#ibcon#read 3, iclass 35, count 2 2006.161.07:31:08.67#ibcon#about to read 4, iclass 35, count 2 2006.161.07:31:08.67#ibcon#read 4, iclass 35, count 2 2006.161.07:31:08.67#ibcon#about to read 5, iclass 35, count 2 2006.161.07:31:08.67#ibcon#read 5, iclass 35, count 2 2006.161.07:31:08.67#ibcon#about to read 6, iclass 35, count 2 2006.161.07:31:08.67#ibcon#read 6, iclass 35, count 2 2006.161.07:31:08.67#ibcon#end of sib2, iclass 35, count 2 2006.161.07:31:08.67#ibcon#*mode == 0, iclass 35, count 2 2006.161.07:31:08.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.07:31:08.67#ibcon#[25=AT01-08\r\n] 2006.161.07:31:08.67#ibcon#*before write, iclass 35, count 2 2006.161.07:31:08.67#ibcon#enter sib2, iclass 35, count 2 2006.161.07:31:08.67#ibcon#flushed, iclass 35, count 2 2006.161.07:31:08.67#ibcon#about to write, iclass 35, count 2 2006.161.07:31:08.67#ibcon#wrote, iclass 35, count 2 2006.161.07:31:08.67#ibcon#about to read 3, iclass 35, count 2 2006.161.07:31:08.70#ibcon#read 3, iclass 35, count 2 2006.161.07:31:08.70#ibcon#about to read 4, iclass 35, count 2 2006.161.07:31:08.70#ibcon#read 4, iclass 35, count 2 2006.161.07:31:08.70#ibcon#about to read 5, iclass 35, count 2 2006.161.07:31:08.70#ibcon#read 5, iclass 35, count 2 2006.161.07:31:08.70#ibcon#about to read 6, iclass 35, count 2 2006.161.07:31:08.70#ibcon#read 6, iclass 35, count 2 2006.161.07:31:08.70#ibcon#end of sib2, iclass 35, count 2 2006.161.07:31:08.70#ibcon#*after write, iclass 35, count 2 2006.161.07:31:08.70#ibcon#*before return 0, iclass 35, count 2 2006.161.07:31:08.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:08.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:08.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.07:31:08.70#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:08.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:08.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:08.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:08.81#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:31:08.81#ibcon#first serial, iclass 35, count 0 2006.161.07:31:08.81#ibcon#enter sib2, iclass 35, count 0 2006.161.07:31:08.81#ibcon#flushed, iclass 35, count 0 2006.161.07:31:08.81#ibcon#about to write, iclass 35, count 0 2006.161.07:31:08.81#ibcon#wrote, iclass 35, count 0 2006.161.07:31:08.81#ibcon#about to read 3, iclass 35, count 0 2006.161.07:31:08.83#ibcon#read 3, iclass 35, count 0 2006.161.07:31:08.83#ibcon#about to read 4, iclass 35, count 0 2006.161.07:31:08.83#ibcon#read 4, iclass 35, count 0 2006.161.07:31:08.83#ibcon#about to read 5, iclass 35, count 0 2006.161.07:31:08.83#ibcon#read 5, iclass 35, count 0 2006.161.07:31:08.83#ibcon#about to read 6, iclass 35, count 0 2006.161.07:31:08.83#ibcon#read 6, iclass 35, count 0 2006.161.07:31:08.83#ibcon#end of sib2, iclass 35, count 0 2006.161.07:31:08.83#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:31:08.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:31:08.83#ibcon#[25=USB\r\n] 2006.161.07:31:08.83#ibcon#*before write, iclass 35, count 0 2006.161.07:31:08.83#ibcon#enter sib2, iclass 35, count 0 2006.161.07:31:08.83#ibcon#flushed, iclass 35, count 0 2006.161.07:31:08.83#ibcon#about to write, iclass 35, count 0 2006.161.07:31:08.83#ibcon#wrote, iclass 35, count 0 2006.161.07:31:08.83#ibcon#about to read 3, iclass 35, count 0 2006.161.07:31:08.86#ibcon#read 3, iclass 35, count 0 2006.161.07:31:08.86#ibcon#about to read 4, iclass 35, count 0 2006.161.07:31:08.86#ibcon#read 4, iclass 35, count 0 2006.161.07:31:08.86#ibcon#about to read 5, iclass 35, count 0 2006.161.07:31:08.86#ibcon#read 5, iclass 35, count 0 2006.161.07:31:08.86#ibcon#about to read 6, iclass 35, count 0 2006.161.07:31:08.86#ibcon#read 6, iclass 35, count 0 2006.161.07:31:08.86#ibcon#end of sib2, iclass 35, count 0 2006.161.07:31:08.86#ibcon#*after write, iclass 35, count 0 2006.161.07:31:08.86#ibcon#*before return 0, iclass 35, count 0 2006.161.07:31:08.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:08.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:08.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:31:08.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:31:08.86$vc4f8/valo=2,572.99 2006.161.07:31:08.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:31:08.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:31:08.86#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:08.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:08.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:08.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:08.86#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:31:08.86#ibcon#first serial, iclass 37, count 0 2006.161.07:31:08.86#ibcon#enter sib2, iclass 37, count 0 2006.161.07:31:08.86#ibcon#flushed, iclass 37, count 0 2006.161.07:31:08.86#ibcon#about to write, iclass 37, count 0 2006.161.07:31:08.86#ibcon#wrote, iclass 37, count 0 2006.161.07:31:08.86#ibcon#about to read 3, iclass 37, count 0 2006.161.07:31:08.88#ibcon#read 3, iclass 37, count 0 2006.161.07:31:08.88#ibcon#about to read 4, iclass 37, count 0 2006.161.07:31:08.88#ibcon#read 4, iclass 37, count 0 2006.161.07:31:08.88#ibcon#about to read 5, iclass 37, count 0 2006.161.07:31:08.88#ibcon#read 5, iclass 37, count 0 2006.161.07:31:08.88#ibcon#about to read 6, iclass 37, count 0 2006.161.07:31:08.88#ibcon#read 6, iclass 37, count 0 2006.161.07:31:08.88#ibcon#end of sib2, iclass 37, count 0 2006.161.07:31:08.88#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:31:08.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:31:08.88#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:31:08.88#ibcon#*before write, iclass 37, count 0 2006.161.07:31:08.88#ibcon#enter sib2, iclass 37, count 0 2006.161.07:31:08.88#ibcon#flushed, iclass 37, count 0 2006.161.07:31:08.88#ibcon#about to write, iclass 37, count 0 2006.161.07:31:08.88#ibcon#wrote, iclass 37, count 0 2006.161.07:31:08.88#ibcon#about to read 3, iclass 37, count 0 2006.161.07:31:08.92#ibcon#read 3, iclass 37, count 0 2006.161.07:31:08.92#ibcon#about to read 4, iclass 37, count 0 2006.161.07:31:08.92#ibcon#read 4, iclass 37, count 0 2006.161.07:31:08.92#ibcon#about to read 5, iclass 37, count 0 2006.161.07:31:08.92#ibcon#read 5, iclass 37, count 0 2006.161.07:31:08.92#ibcon#about to read 6, iclass 37, count 0 2006.161.07:31:08.92#ibcon#read 6, iclass 37, count 0 2006.161.07:31:08.92#ibcon#end of sib2, iclass 37, count 0 2006.161.07:31:08.92#ibcon#*after write, iclass 37, count 0 2006.161.07:31:08.92#ibcon#*before return 0, iclass 37, count 0 2006.161.07:31:08.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:08.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:08.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:31:08.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:31:08.92$vc4f8/va=2,7 2006.161.07:31:08.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.07:31:08.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.07:31:08.92#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:08.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:08.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:08.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:08.98#ibcon#enter wrdev, iclass 39, count 2 2006.161.07:31:08.98#ibcon#first serial, iclass 39, count 2 2006.161.07:31:08.98#ibcon#enter sib2, iclass 39, count 2 2006.161.07:31:08.98#ibcon#flushed, iclass 39, count 2 2006.161.07:31:08.98#ibcon#about to write, iclass 39, count 2 2006.161.07:31:08.98#ibcon#wrote, iclass 39, count 2 2006.161.07:31:08.98#ibcon#about to read 3, iclass 39, count 2 2006.161.07:31:09.01#ibcon#read 3, iclass 39, count 2 2006.161.07:31:09.01#ibcon#about to read 4, iclass 39, count 2 2006.161.07:31:09.01#ibcon#read 4, iclass 39, count 2 2006.161.07:31:09.01#ibcon#about to read 5, iclass 39, count 2 2006.161.07:31:09.01#ibcon#read 5, iclass 39, count 2 2006.161.07:31:09.01#ibcon#about to read 6, iclass 39, count 2 2006.161.07:31:09.01#ibcon#read 6, iclass 39, count 2 2006.161.07:31:09.01#ibcon#end of sib2, iclass 39, count 2 2006.161.07:31:09.01#ibcon#*mode == 0, iclass 39, count 2 2006.161.07:31:09.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.07:31:09.01#ibcon#[25=AT02-07\r\n] 2006.161.07:31:09.01#ibcon#*before write, iclass 39, count 2 2006.161.07:31:09.01#ibcon#enter sib2, iclass 39, count 2 2006.161.07:31:09.01#ibcon#flushed, iclass 39, count 2 2006.161.07:31:09.01#ibcon#about to write, iclass 39, count 2 2006.161.07:31:09.01#ibcon#wrote, iclass 39, count 2 2006.161.07:31:09.01#ibcon#about to read 3, iclass 39, count 2 2006.161.07:31:09.04#ibcon#read 3, iclass 39, count 2 2006.161.07:31:09.04#ibcon#about to read 4, iclass 39, count 2 2006.161.07:31:09.04#ibcon#read 4, iclass 39, count 2 2006.161.07:31:09.04#ibcon#about to read 5, iclass 39, count 2 2006.161.07:31:09.04#ibcon#read 5, iclass 39, count 2 2006.161.07:31:09.04#ibcon#about to read 6, iclass 39, count 2 2006.161.07:31:09.04#ibcon#read 6, iclass 39, count 2 2006.161.07:31:09.04#ibcon#end of sib2, iclass 39, count 2 2006.161.07:31:09.04#ibcon#*after write, iclass 39, count 2 2006.161.07:31:09.04#ibcon#*before return 0, iclass 39, count 2 2006.161.07:31:09.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:09.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:09.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.07:31:09.04#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:09.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:09.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:09.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:09.16#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:31:09.16#ibcon#first serial, iclass 39, count 0 2006.161.07:31:09.16#ibcon#enter sib2, iclass 39, count 0 2006.161.07:31:09.16#ibcon#flushed, iclass 39, count 0 2006.161.07:31:09.16#ibcon#about to write, iclass 39, count 0 2006.161.07:31:09.16#ibcon#wrote, iclass 39, count 0 2006.161.07:31:09.16#ibcon#about to read 3, iclass 39, count 0 2006.161.07:31:09.20#ibcon#read 3, iclass 39, count 0 2006.161.07:31:09.20#ibcon#about to read 4, iclass 39, count 0 2006.161.07:31:09.20#ibcon#read 4, iclass 39, count 0 2006.161.07:31:09.20#ibcon#about to read 5, iclass 39, count 0 2006.161.07:31:09.20#ibcon#read 5, iclass 39, count 0 2006.161.07:31:09.20#ibcon#about to read 6, iclass 39, count 0 2006.161.07:31:09.20#ibcon#read 6, iclass 39, count 0 2006.161.07:31:09.20#ibcon#end of sib2, iclass 39, count 0 2006.161.07:31:09.20#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:31:09.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:31:09.20#ibcon#[25=USB\r\n] 2006.161.07:31:09.20#ibcon#*before write, iclass 39, count 0 2006.161.07:31:09.20#ibcon#enter sib2, iclass 39, count 0 2006.161.07:31:09.20#ibcon#flushed, iclass 39, count 0 2006.161.07:31:09.20#ibcon#about to write, iclass 39, count 0 2006.161.07:31:09.20#ibcon#wrote, iclass 39, count 0 2006.161.07:31:09.20#ibcon#about to read 3, iclass 39, count 0 2006.161.07:31:09.23#ibcon#read 3, iclass 39, count 0 2006.161.07:31:09.23#ibcon#about to read 4, iclass 39, count 0 2006.161.07:31:09.23#ibcon#read 4, iclass 39, count 0 2006.161.07:31:09.23#ibcon#about to read 5, iclass 39, count 0 2006.161.07:31:09.23#ibcon#read 5, iclass 39, count 0 2006.161.07:31:09.23#ibcon#about to read 6, iclass 39, count 0 2006.161.07:31:09.23#ibcon#read 6, iclass 39, count 0 2006.161.07:31:09.23#ibcon#end of sib2, iclass 39, count 0 2006.161.07:31:09.23#ibcon#*after write, iclass 39, count 0 2006.161.07:31:09.23#ibcon#*before return 0, iclass 39, count 0 2006.161.07:31:09.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:09.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:09.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:31:09.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:31:09.23$vc4f8/valo=3,672.99 2006.161.07:31:09.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.07:31:09.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.07:31:09.23#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:09.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:09.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:09.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:09.23#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:31:09.23#ibcon#first serial, iclass 3, count 0 2006.161.07:31:09.23#ibcon#enter sib2, iclass 3, count 0 2006.161.07:31:09.23#ibcon#flushed, iclass 3, count 0 2006.161.07:31:09.23#ibcon#about to write, iclass 3, count 0 2006.161.07:31:09.23#ibcon#wrote, iclass 3, count 0 2006.161.07:31:09.23#ibcon#about to read 3, iclass 3, count 0 2006.161.07:31:09.25#ibcon#read 3, iclass 3, count 0 2006.161.07:31:09.25#ibcon#about to read 4, iclass 3, count 0 2006.161.07:31:09.25#ibcon#read 4, iclass 3, count 0 2006.161.07:31:09.25#ibcon#about to read 5, iclass 3, count 0 2006.161.07:31:09.25#ibcon#read 5, iclass 3, count 0 2006.161.07:31:09.25#ibcon#about to read 6, iclass 3, count 0 2006.161.07:31:09.25#ibcon#read 6, iclass 3, count 0 2006.161.07:31:09.25#ibcon#end of sib2, iclass 3, count 0 2006.161.07:31:09.25#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:31:09.25#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:31:09.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:31:09.25#ibcon#*before write, iclass 3, count 0 2006.161.07:31:09.25#ibcon#enter sib2, iclass 3, count 0 2006.161.07:31:09.25#ibcon#flushed, iclass 3, count 0 2006.161.07:31:09.25#ibcon#about to write, iclass 3, count 0 2006.161.07:31:09.25#ibcon#wrote, iclass 3, count 0 2006.161.07:31:09.25#ibcon#about to read 3, iclass 3, count 0 2006.161.07:31:09.30#ibcon#read 3, iclass 3, count 0 2006.161.07:31:09.30#ibcon#about to read 4, iclass 3, count 0 2006.161.07:31:09.30#ibcon#read 4, iclass 3, count 0 2006.161.07:31:09.30#ibcon#about to read 5, iclass 3, count 0 2006.161.07:31:09.30#ibcon#read 5, iclass 3, count 0 2006.161.07:31:09.30#ibcon#about to read 6, iclass 3, count 0 2006.161.07:31:09.30#ibcon#read 6, iclass 3, count 0 2006.161.07:31:09.30#ibcon#end of sib2, iclass 3, count 0 2006.161.07:31:09.30#ibcon#*after write, iclass 3, count 0 2006.161.07:31:09.30#ibcon#*before return 0, iclass 3, count 0 2006.161.07:31:09.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:09.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:09.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:31:09.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:31:09.30$vc4f8/va=3,6 2006.161.07:31:09.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.07:31:09.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.07:31:09.30#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:09.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:09.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:09.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:09.34#ibcon#enter wrdev, iclass 5, count 2 2006.161.07:31:09.34#ibcon#first serial, iclass 5, count 2 2006.161.07:31:09.34#ibcon#enter sib2, iclass 5, count 2 2006.161.07:31:09.34#ibcon#flushed, iclass 5, count 2 2006.161.07:31:09.34#ibcon#about to write, iclass 5, count 2 2006.161.07:31:09.34#ibcon#wrote, iclass 5, count 2 2006.161.07:31:09.34#ibcon#about to read 3, iclass 5, count 2 2006.161.07:31:09.36#ibcon#read 3, iclass 5, count 2 2006.161.07:31:09.36#ibcon#about to read 4, iclass 5, count 2 2006.161.07:31:09.36#ibcon#read 4, iclass 5, count 2 2006.161.07:31:09.36#ibcon#about to read 5, iclass 5, count 2 2006.161.07:31:09.36#ibcon#read 5, iclass 5, count 2 2006.161.07:31:09.36#ibcon#about to read 6, iclass 5, count 2 2006.161.07:31:09.36#ibcon#read 6, iclass 5, count 2 2006.161.07:31:09.36#ibcon#end of sib2, iclass 5, count 2 2006.161.07:31:09.36#ibcon#*mode == 0, iclass 5, count 2 2006.161.07:31:09.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.07:31:09.36#ibcon#[25=AT03-06\r\n] 2006.161.07:31:09.36#ibcon#*before write, iclass 5, count 2 2006.161.07:31:09.36#ibcon#enter sib2, iclass 5, count 2 2006.161.07:31:09.36#ibcon#flushed, iclass 5, count 2 2006.161.07:31:09.36#ibcon#about to write, iclass 5, count 2 2006.161.07:31:09.36#ibcon#wrote, iclass 5, count 2 2006.161.07:31:09.36#ibcon#about to read 3, iclass 5, count 2 2006.161.07:31:09.39#ibcon#read 3, iclass 5, count 2 2006.161.07:31:09.39#ibcon#about to read 4, iclass 5, count 2 2006.161.07:31:09.39#ibcon#read 4, iclass 5, count 2 2006.161.07:31:09.39#ibcon#about to read 5, iclass 5, count 2 2006.161.07:31:09.39#ibcon#read 5, iclass 5, count 2 2006.161.07:31:09.39#ibcon#about to read 6, iclass 5, count 2 2006.161.07:31:09.39#ibcon#read 6, iclass 5, count 2 2006.161.07:31:09.39#ibcon#end of sib2, iclass 5, count 2 2006.161.07:31:09.39#ibcon#*after write, iclass 5, count 2 2006.161.07:31:09.39#ibcon#*before return 0, iclass 5, count 2 2006.161.07:31:09.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:09.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:09.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.07:31:09.39#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:09.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:09.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:09.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:09.51#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:31:09.51#ibcon#first serial, iclass 5, count 0 2006.161.07:31:09.51#ibcon#enter sib2, iclass 5, count 0 2006.161.07:31:09.51#ibcon#flushed, iclass 5, count 0 2006.161.07:31:09.51#ibcon#about to write, iclass 5, count 0 2006.161.07:31:09.51#ibcon#wrote, iclass 5, count 0 2006.161.07:31:09.51#ibcon#about to read 3, iclass 5, count 0 2006.161.07:31:09.53#ibcon#read 3, iclass 5, count 0 2006.161.07:31:09.53#ibcon#about to read 4, iclass 5, count 0 2006.161.07:31:09.53#ibcon#read 4, iclass 5, count 0 2006.161.07:31:09.53#ibcon#about to read 5, iclass 5, count 0 2006.161.07:31:09.53#ibcon#read 5, iclass 5, count 0 2006.161.07:31:09.53#ibcon#about to read 6, iclass 5, count 0 2006.161.07:31:09.53#ibcon#read 6, iclass 5, count 0 2006.161.07:31:09.53#ibcon#end of sib2, iclass 5, count 0 2006.161.07:31:09.53#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:31:09.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:31:09.53#ibcon#[25=USB\r\n] 2006.161.07:31:09.53#ibcon#*before write, iclass 5, count 0 2006.161.07:31:09.53#ibcon#enter sib2, iclass 5, count 0 2006.161.07:31:09.53#ibcon#flushed, iclass 5, count 0 2006.161.07:31:09.53#ibcon#about to write, iclass 5, count 0 2006.161.07:31:09.53#ibcon#wrote, iclass 5, count 0 2006.161.07:31:09.53#ibcon#about to read 3, iclass 5, count 0 2006.161.07:31:09.56#ibcon#read 3, iclass 5, count 0 2006.161.07:31:09.56#ibcon#about to read 4, iclass 5, count 0 2006.161.07:31:09.56#ibcon#read 4, iclass 5, count 0 2006.161.07:31:09.56#ibcon#about to read 5, iclass 5, count 0 2006.161.07:31:09.56#ibcon#read 5, iclass 5, count 0 2006.161.07:31:09.56#ibcon#about to read 6, iclass 5, count 0 2006.161.07:31:09.56#ibcon#read 6, iclass 5, count 0 2006.161.07:31:09.56#ibcon#end of sib2, iclass 5, count 0 2006.161.07:31:09.56#ibcon#*after write, iclass 5, count 0 2006.161.07:31:09.56#ibcon#*before return 0, iclass 5, count 0 2006.161.07:31:09.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:09.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:09.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:31:09.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:31:09.56$vc4f8/valo=4,832.99 2006.161.07:31:09.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:31:09.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:31:09.56#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:09.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:09.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:09.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:09.56#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:31:09.56#ibcon#first serial, iclass 7, count 0 2006.161.07:31:09.56#ibcon#enter sib2, iclass 7, count 0 2006.161.07:31:09.56#ibcon#flushed, iclass 7, count 0 2006.161.07:31:09.56#ibcon#about to write, iclass 7, count 0 2006.161.07:31:09.56#ibcon#wrote, iclass 7, count 0 2006.161.07:31:09.56#ibcon#about to read 3, iclass 7, count 0 2006.161.07:31:09.58#ibcon#read 3, iclass 7, count 0 2006.161.07:31:09.58#ibcon#about to read 4, iclass 7, count 0 2006.161.07:31:09.58#ibcon#read 4, iclass 7, count 0 2006.161.07:31:09.58#ibcon#about to read 5, iclass 7, count 0 2006.161.07:31:09.58#ibcon#read 5, iclass 7, count 0 2006.161.07:31:09.58#ibcon#about to read 6, iclass 7, count 0 2006.161.07:31:09.58#ibcon#read 6, iclass 7, count 0 2006.161.07:31:09.58#ibcon#end of sib2, iclass 7, count 0 2006.161.07:31:09.58#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:31:09.58#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:31:09.58#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:31:09.58#ibcon#*before write, iclass 7, count 0 2006.161.07:31:09.58#ibcon#enter sib2, iclass 7, count 0 2006.161.07:31:09.58#ibcon#flushed, iclass 7, count 0 2006.161.07:31:09.58#ibcon#about to write, iclass 7, count 0 2006.161.07:31:09.58#ibcon#wrote, iclass 7, count 0 2006.161.07:31:09.58#ibcon#about to read 3, iclass 7, count 0 2006.161.07:31:09.62#ibcon#read 3, iclass 7, count 0 2006.161.07:31:09.62#ibcon#about to read 4, iclass 7, count 0 2006.161.07:31:09.62#ibcon#read 4, iclass 7, count 0 2006.161.07:31:09.62#ibcon#about to read 5, iclass 7, count 0 2006.161.07:31:09.62#ibcon#read 5, iclass 7, count 0 2006.161.07:31:09.62#ibcon#about to read 6, iclass 7, count 0 2006.161.07:31:09.62#ibcon#read 6, iclass 7, count 0 2006.161.07:31:09.62#ibcon#end of sib2, iclass 7, count 0 2006.161.07:31:09.62#ibcon#*after write, iclass 7, count 0 2006.161.07:31:09.62#ibcon#*before return 0, iclass 7, count 0 2006.161.07:31:09.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:09.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:09.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:31:09.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:31:09.62$vc4f8/va=4,7 2006.161.07:31:09.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:31:09.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:31:09.62#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:09.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:09.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:09.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:09.68#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:31:09.68#ibcon#first serial, iclass 11, count 2 2006.161.07:31:09.68#ibcon#enter sib2, iclass 11, count 2 2006.161.07:31:09.68#ibcon#flushed, iclass 11, count 2 2006.161.07:31:09.68#ibcon#about to write, iclass 11, count 2 2006.161.07:31:09.68#ibcon#wrote, iclass 11, count 2 2006.161.07:31:09.68#ibcon#about to read 3, iclass 11, count 2 2006.161.07:31:09.70#ibcon#read 3, iclass 11, count 2 2006.161.07:31:09.70#ibcon#about to read 4, iclass 11, count 2 2006.161.07:31:09.70#ibcon#read 4, iclass 11, count 2 2006.161.07:31:09.70#ibcon#about to read 5, iclass 11, count 2 2006.161.07:31:09.70#ibcon#read 5, iclass 11, count 2 2006.161.07:31:09.70#ibcon#about to read 6, iclass 11, count 2 2006.161.07:31:09.70#ibcon#read 6, iclass 11, count 2 2006.161.07:31:09.70#ibcon#end of sib2, iclass 11, count 2 2006.161.07:31:09.70#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:31:09.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:31:09.70#ibcon#[25=AT04-07\r\n] 2006.161.07:31:09.70#ibcon#*before write, iclass 11, count 2 2006.161.07:31:09.70#ibcon#enter sib2, iclass 11, count 2 2006.161.07:31:09.70#ibcon#flushed, iclass 11, count 2 2006.161.07:31:09.70#ibcon#about to write, iclass 11, count 2 2006.161.07:31:09.70#ibcon#wrote, iclass 11, count 2 2006.161.07:31:09.70#ibcon#about to read 3, iclass 11, count 2 2006.161.07:31:09.73#ibcon#read 3, iclass 11, count 2 2006.161.07:31:09.73#ibcon#about to read 4, iclass 11, count 2 2006.161.07:31:09.73#ibcon#read 4, iclass 11, count 2 2006.161.07:31:09.73#ibcon#about to read 5, iclass 11, count 2 2006.161.07:31:09.73#ibcon#read 5, iclass 11, count 2 2006.161.07:31:09.73#ibcon#about to read 6, iclass 11, count 2 2006.161.07:31:09.73#ibcon#read 6, iclass 11, count 2 2006.161.07:31:09.73#ibcon#end of sib2, iclass 11, count 2 2006.161.07:31:09.73#ibcon#*after write, iclass 11, count 2 2006.161.07:31:09.73#ibcon#*before return 0, iclass 11, count 2 2006.161.07:31:09.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:09.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:09.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:31:09.73#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:09.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:09.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:09.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:09.85#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:31:09.85#ibcon#first serial, iclass 11, count 0 2006.161.07:31:09.85#ibcon#enter sib2, iclass 11, count 0 2006.161.07:31:09.85#ibcon#flushed, iclass 11, count 0 2006.161.07:31:09.85#ibcon#about to write, iclass 11, count 0 2006.161.07:31:09.85#ibcon#wrote, iclass 11, count 0 2006.161.07:31:09.85#ibcon#about to read 3, iclass 11, count 0 2006.161.07:31:09.87#ibcon#read 3, iclass 11, count 0 2006.161.07:31:09.87#ibcon#about to read 4, iclass 11, count 0 2006.161.07:31:09.87#ibcon#read 4, iclass 11, count 0 2006.161.07:31:09.87#ibcon#about to read 5, iclass 11, count 0 2006.161.07:31:09.87#ibcon#read 5, iclass 11, count 0 2006.161.07:31:09.87#ibcon#about to read 6, iclass 11, count 0 2006.161.07:31:09.87#ibcon#read 6, iclass 11, count 0 2006.161.07:31:09.87#ibcon#end of sib2, iclass 11, count 0 2006.161.07:31:09.87#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:31:09.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:31:09.87#ibcon#[25=USB\r\n] 2006.161.07:31:09.87#ibcon#*before write, iclass 11, count 0 2006.161.07:31:09.87#ibcon#enter sib2, iclass 11, count 0 2006.161.07:31:09.87#ibcon#flushed, iclass 11, count 0 2006.161.07:31:09.87#ibcon#about to write, iclass 11, count 0 2006.161.07:31:09.87#ibcon#wrote, iclass 11, count 0 2006.161.07:31:09.87#ibcon#about to read 3, iclass 11, count 0 2006.161.07:31:09.90#ibcon#read 3, iclass 11, count 0 2006.161.07:31:09.90#ibcon#about to read 4, iclass 11, count 0 2006.161.07:31:09.90#ibcon#read 4, iclass 11, count 0 2006.161.07:31:09.90#ibcon#about to read 5, iclass 11, count 0 2006.161.07:31:09.90#ibcon#read 5, iclass 11, count 0 2006.161.07:31:09.90#ibcon#about to read 6, iclass 11, count 0 2006.161.07:31:09.90#ibcon#read 6, iclass 11, count 0 2006.161.07:31:09.90#ibcon#end of sib2, iclass 11, count 0 2006.161.07:31:09.90#ibcon#*after write, iclass 11, count 0 2006.161.07:31:09.90#ibcon#*before return 0, iclass 11, count 0 2006.161.07:31:09.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:09.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:09.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:31:09.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:31:09.90$vc4f8/valo=5,652.99 2006.161.07:31:09.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:31:09.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:31:09.90#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:09.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:09.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:09.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:09.90#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:31:09.90#ibcon#first serial, iclass 13, count 0 2006.161.07:31:09.90#ibcon#enter sib2, iclass 13, count 0 2006.161.07:31:09.90#ibcon#flushed, iclass 13, count 0 2006.161.07:31:09.90#ibcon#about to write, iclass 13, count 0 2006.161.07:31:09.90#ibcon#wrote, iclass 13, count 0 2006.161.07:31:09.90#ibcon#about to read 3, iclass 13, count 0 2006.161.07:31:09.92#ibcon#read 3, iclass 13, count 0 2006.161.07:31:09.92#ibcon#about to read 4, iclass 13, count 0 2006.161.07:31:09.92#ibcon#read 4, iclass 13, count 0 2006.161.07:31:09.92#ibcon#about to read 5, iclass 13, count 0 2006.161.07:31:09.92#ibcon#read 5, iclass 13, count 0 2006.161.07:31:09.92#ibcon#about to read 6, iclass 13, count 0 2006.161.07:31:09.92#ibcon#read 6, iclass 13, count 0 2006.161.07:31:09.92#ibcon#end of sib2, iclass 13, count 0 2006.161.07:31:09.92#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:31:09.92#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:31:09.92#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:31:09.92#ibcon#*before write, iclass 13, count 0 2006.161.07:31:09.92#ibcon#enter sib2, iclass 13, count 0 2006.161.07:31:09.92#ibcon#flushed, iclass 13, count 0 2006.161.07:31:09.92#ibcon#about to write, iclass 13, count 0 2006.161.07:31:09.92#ibcon#wrote, iclass 13, count 0 2006.161.07:31:09.92#ibcon#about to read 3, iclass 13, count 0 2006.161.07:31:09.96#ibcon#read 3, iclass 13, count 0 2006.161.07:31:09.96#ibcon#about to read 4, iclass 13, count 0 2006.161.07:31:09.96#ibcon#read 4, iclass 13, count 0 2006.161.07:31:09.96#ibcon#about to read 5, iclass 13, count 0 2006.161.07:31:09.96#ibcon#read 5, iclass 13, count 0 2006.161.07:31:09.96#ibcon#about to read 6, iclass 13, count 0 2006.161.07:31:09.96#ibcon#read 6, iclass 13, count 0 2006.161.07:31:09.96#ibcon#end of sib2, iclass 13, count 0 2006.161.07:31:09.96#ibcon#*after write, iclass 13, count 0 2006.161.07:31:09.96#ibcon#*before return 0, iclass 13, count 0 2006.161.07:31:09.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:09.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:09.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:31:09.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:31:09.96$vc4f8/va=5,7 2006.161.07:31:09.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:31:09.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:31:09.96#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:09.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:10.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:10.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:10.02#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:31:10.02#ibcon#first serial, iclass 15, count 2 2006.161.07:31:10.02#ibcon#enter sib2, iclass 15, count 2 2006.161.07:31:10.02#ibcon#flushed, iclass 15, count 2 2006.161.07:31:10.02#ibcon#about to write, iclass 15, count 2 2006.161.07:31:10.02#ibcon#wrote, iclass 15, count 2 2006.161.07:31:10.02#ibcon#about to read 3, iclass 15, count 2 2006.161.07:31:10.04#ibcon#read 3, iclass 15, count 2 2006.161.07:31:10.04#ibcon#about to read 4, iclass 15, count 2 2006.161.07:31:10.04#ibcon#read 4, iclass 15, count 2 2006.161.07:31:10.04#ibcon#about to read 5, iclass 15, count 2 2006.161.07:31:10.04#ibcon#read 5, iclass 15, count 2 2006.161.07:31:10.04#ibcon#about to read 6, iclass 15, count 2 2006.161.07:31:10.04#ibcon#read 6, iclass 15, count 2 2006.161.07:31:10.04#ibcon#end of sib2, iclass 15, count 2 2006.161.07:31:10.04#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:31:10.04#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:31:10.04#ibcon#[25=AT05-07\r\n] 2006.161.07:31:10.04#ibcon#*before write, iclass 15, count 2 2006.161.07:31:10.04#ibcon#enter sib2, iclass 15, count 2 2006.161.07:31:10.04#ibcon#flushed, iclass 15, count 2 2006.161.07:31:10.04#ibcon#about to write, iclass 15, count 2 2006.161.07:31:10.04#ibcon#wrote, iclass 15, count 2 2006.161.07:31:10.04#ibcon#about to read 3, iclass 15, count 2 2006.161.07:31:10.07#ibcon#read 3, iclass 15, count 2 2006.161.07:31:10.07#ibcon#about to read 4, iclass 15, count 2 2006.161.07:31:10.07#ibcon#read 4, iclass 15, count 2 2006.161.07:31:10.07#ibcon#about to read 5, iclass 15, count 2 2006.161.07:31:10.07#ibcon#read 5, iclass 15, count 2 2006.161.07:31:10.07#ibcon#about to read 6, iclass 15, count 2 2006.161.07:31:10.07#ibcon#read 6, iclass 15, count 2 2006.161.07:31:10.07#ibcon#end of sib2, iclass 15, count 2 2006.161.07:31:10.07#ibcon#*after write, iclass 15, count 2 2006.161.07:31:10.07#ibcon#*before return 0, iclass 15, count 2 2006.161.07:31:10.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:10.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:10.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:31:10.07#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:10.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:10.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:10.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:10.19#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:31:10.19#ibcon#first serial, iclass 15, count 0 2006.161.07:31:10.19#ibcon#enter sib2, iclass 15, count 0 2006.161.07:31:10.19#ibcon#flushed, iclass 15, count 0 2006.161.07:31:10.19#ibcon#about to write, iclass 15, count 0 2006.161.07:31:10.19#ibcon#wrote, iclass 15, count 0 2006.161.07:31:10.19#ibcon#about to read 3, iclass 15, count 0 2006.161.07:31:10.21#ibcon#read 3, iclass 15, count 0 2006.161.07:31:10.21#ibcon#about to read 4, iclass 15, count 0 2006.161.07:31:10.21#ibcon#read 4, iclass 15, count 0 2006.161.07:31:10.21#ibcon#about to read 5, iclass 15, count 0 2006.161.07:31:10.21#ibcon#read 5, iclass 15, count 0 2006.161.07:31:10.21#ibcon#about to read 6, iclass 15, count 0 2006.161.07:31:10.21#ibcon#read 6, iclass 15, count 0 2006.161.07:31:10.21#ibcon#end of sib2, iclass 15, count 0 2006.161.07:31:10.21#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:31:10.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:31:10.21#ibcon#[25=USB\r\n] 2006.161.07:31:10.21#ibcon#*before write, iclass 15, count 0 2006.161.07:31:10.21#ibcon#enter sib2, iclass 15, count 0 2006.161.07:31:10.21#ibcon#flushed, iclass 15, count 0 2006.161.07:31:10.21#ibcon#about to write, iclass 15, count 0 2006.161.07:31:10.21#ibcon#wrote, iclass 15, count 0 2006.161.07:31:10.21#ibcon#about to read 3, iclass 15, count 0 2006.161.07:31:10.24#ibcon#read 3, iclass 15, count 0 2006.161.07:31:10.24#ibcon#about to read 4, iclass 15, count 0 2006.161.07:31:10.24#ibcon#read 4, iclass 15, count 0 2006.161.07:31:10.24#ibcon#about to read 5, iclass 15, count 0 2006.161.07:31:10.24#ibcon#read 5, iclass 15, count 0 2006.161.07:31:10.24#ibcon#about to read 6, iclass 15, count 0 2006.161.07:31:10.24#ibcon#read 6, iclass 15, count 0 2006.161.07:31:10.24#ibcon#end of sib2, iclass 15, count 0 2006.161.07:31:10.24#ibcon#*after write, iclass 15, count 0 2006.161.07:31:10.24#ibcon#*before return 0, iclass 15, count 0 2006.161.07:31:10.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:10.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:10.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:31:10.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:31:10.24$vc4f8/valo=6,772.99 2006.161.07:31:10.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:31:10.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:31:10.24#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:10.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:10.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:10.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:10.24#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:31:10.24#ibcon#first serial, iclass 17, count 0 2006.161.07:31:10.24#ibcon#enter sib2, iclass 17, count 0 2006.161.07:31:10.24#ibcon#flushed, iclass 17, count 0 2006.161.07:31:10.24#ibcon#about to write, iclass 17, count 0 2006.161.07:31:10.24#ibcon#wrote, iclass 17, count 0 2006.161.07:31:10.24#ibcon#about to read 3, iclass 17, count 0 2006.161.07:31:10.26#ibcon#read 3, iclass 17, count 0 2006.161.07:31:10.26#ibcon#about to read 4, iclass 17, count 0 2006.161.07:31:10.26#ibcon#read 4, iclass 17, count 0 2006.161.07:31:10.26#ibcon#about to read 5, iclass 17, count 0 2006.161.07:31:10.26#ibcon#read 5, iclass 17, count 0 2006.161.07:31:10.26#ibcon#about to read 6, iclass 17, count 0 2006.161.07:31:10.26#ibcon#read 6, iclass 17, count 0 2006.161.07:31:10.26#ibcon#end of sib2, iclass 17, count 0 2006.161.07:31:10.26#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:31:10.26#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:31:10.26#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:31:10.26#ibcon#*before write, iclass 17, count 0 2006.161.07:31:10.26#ibcon#enter sib2, iclass 17, count 0 2006.161.07:31:10.26#ibcon#flushed, iclass 17, count 0 2006.161.07:31:10.26#ibcon#about to write, iclass 17, count 0 2006.161.07:31:10.26#ibcon#wrote, iclass 17, count 0 2006.161.07:31:10.26#ibcon#about to read 3, iclass 17, count 0 2006.161.07:31:10.30#ibcon#read 3, iclass 17, count 0 2006.161.07:31:10.30#ibcon#about to read 4, iclass 17, count 0 2006.161.07:31:10.30#ibcon#read 4, iclass 17, count 0 2006.161.07:31:10.30#ibcon#about to read 5, iclass 17, count 0 2006.161.07:31:10.30#ibcon#read 5, iclass 17, count 0 2006.161.07:31:10.30#ibcon#about to read 6, iclass 17, count 0 2006.161.07:31:10.30#ibcon#read 6, iclass 17, count 0 2006.161.07:31:10.30#ibcon#end of sib2, iclass 17, count 0 2006.161.07:31:10.30#ibcon#*after write, iclass 17, count 0 2006.161.07:31:10.30#ibcon#*before return 0, iclass 17, count 0 2006.161.07:31:10.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:10.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:10.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:31:10.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:31:10.30$vc4f8/va=6,6 2006.161.07:31:10.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.07:31:10.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.07:31:10.30#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:10.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:10.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:10.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:10.36#ibcon#enter wrdev, iclass 19, count 2 2006.161.07:31:10.36#ibcon#first serial, iclass 19, count 2 2006.161.07:31:10.36#ibcon#enter sib2, iclass 19, count 2 2006.161.07:31:10.36#ibcon#flushed, iclass 19, count 2 2006.161.07:31:10.36#ibcon#about to write, iclass 19, count 2 2006.161.07:31:10.36#ibcon#wrote, iclass 19, count 2 2006.161.07:31:10.36#ibcon#about to read 3, iclass 19, count 2 2006.161.07:31:10.38#ibcon#read 3, iclass 19, count 2 2006.161.07:31:10.38#ibcon#about to read 4, iclass 19, count 2 2006.161.07:31:10.38#ibcon#read 4, iclass 19, count 2 2006.161.07:31:10.38#ibcon#about to read 5, iclass 19, count 2 2006.161.07:31:10.38#ibcon#read 5, iclass 19, count 2 2006.161.07:31:10.38#ibcon#about to read 6, iclass 19, count 2 2006.161.07:31:10.38#ibcon#read 6, iclass 19, count 2 2006.161.07:31:10.38#ibcon#end of sib2, iclass 19, count 2 2006.161.07:31:10.38#ibcon#*mode == 0, iclass 19, count 2 2006.161.07:31:10.38#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.07:31:10.38#ibcon#[25=AT06-06\r\n] 2006.161.07:31:10.38#ibcon#*before write, iclass 19, count 2 2006.161.07:31:10.38#ibcon#enter sib2, iclass 19, count 2 2006.161.07:31:10.38#ibcon#flushed, iclass 19, count 2 2006.161.07:31:10.38#ibcon#about to write, iclass 19, count 2 2006.161.07:31:10.38#ibcon#wrote, iclass 19, count 2 2006.161.07:31:10.38#ibcon#about to read 3, iclass 19, count 2 2006.161.07:31:10.41#ibcon#read 3, iclass 19, count 2 2006.161.07:31:10.41#ibcon#about to read 4, iclass 19, count 2 2006.161.07:31:10.41#ibcon#read 4, iclass 19, count 2 2006.161.07:31:10.41#ibcon#about to read 5, iclass 19, count 2 2006.161.07:31:10.41#ibcon#read 5, iclass 19, count 2 2006.161.07:31:10.41#ibcon#about to read 6, iclass 19, count 2 2006.161.07:31:10.41#ibcon#read 6, iclass 19, count 2 2006.161.07:31:10.41#ibcon#end of sib2, iclass 19, count 2 2006.161.07:31:10.41#ibcon#*after write, iclass 19, count 2 2006.161.07:31:10.41#ibcon#*before return 0, iclass 19, count 2 2006.161.07:31:10.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:10.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:10.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.07:31:10.41#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:10.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:31:10.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:31:10.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:31:10.53#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:31:10.53#ibcon#first serial, iclass 19, count 0 2006.161.07:31:10.53#ibcon#enter sib2, iclass 19, count 0 2006.161.07:31:10.53#ibcon#flushed, iclass 19, count 0 2006.161.07:31:10.53#ibcon#about to write, iclass 19, count 0 2006.161.07:31:10.53#ibcon#wrote, iclass 19, count 0 2006.161.07:31:10.53#ibcon#about to read 3, iclass 19, count 0 2006.161.07:31:10.55#ibcon#read 3, iclass 19, count 0 2006.161.07:31:10.55#ibcon#about to read 4, iclass 19, count 0 2006.161.07:31:10.55#ibcon#read 4, iclass 19, count 0 2006.161.07:31:10.55#ibcon#about to read 5, iclass 19, count 0 2006.161.07:31:10.55#ibcon#read 5, iclass 19, count 0 2006.161.07:31:10.55#ibcon#about to read 6, iclass 19, count 0 2006.161.07:31:10.55#ibcon#read 6, iclass 19, count 0 2006.161.07:31:10.55#ibcon#end of sib2, iclass 19, count 0 2006.161.07:31:10.55#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:31:10.55#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:31:10.55#ibcon#[25=USB\r\n] 2006.161.07:31:10.55#ibcon#*before write, iclass 19, count 0 2006.161.07:31:10.55#ibcon#enter sib2, iclass 19, count 0 2006.161.07:31:10.55#ibcon#flushed, iclass 19, count 0 2006.161.07:31:10.55#ibcon#about to write, iclass 19, count 0 2006.161.07:31:10.55#ibcon#wrote, iclass 19, count 0 2006.161.07:31:10.55#ibcon#about to read 3, iclass 19, count 0 2006.161.07:31:10.58#ibcon#read 3, iclass 19, count 0 2006.161.07:31:10.58#ibcon#about to read 4, iclass 19, count 0 2006.161.07:31:10.58#ibcon#read 4, iclass 19, count 0 2006.161.07:31:10.58#ibcon#about to read 5, iclass 19, count 0 2006.161.07:31:10.58#ibcon#read 5, iclass 19, count 0 2006.161.07:31:10.58#ibcon#about to read 6, iclass 19, count 0 2006.161.07:31:10.58#ibcon#read 6, iclass 19, count 0 2006.161.07:31:10.58#ibcon#end of sib2, iclass 19, count 0 2006.161.07:31:10.58#ibcon#*after write, iclass 19, count 0 2006.161.07:31:10.58#ibcon#*before return 0, iclass 19, count 0 2006.161.07:31:10.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:31:10.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:31:10.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:31:10.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:31:10.58$vc4f8/valo=7,832.99 2006.161.07:31:10.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.07:31:10.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.07:31:10.58#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:10.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:31:10.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:31:10.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:31:10.58#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:31:10.58#ibcon#first serial, iclass 21, count 0 2006.161.07:31:10.58#ibcon#enter sib2, iclass 21, count 0 2006.161.07:31:10.58#ibcon#flushed, iclass 21, count 0 2006.161.07:31:10.58#ibcon#about to write, iclass 21, count 0 2006.161.07:31:10.58#ibcon#wrote, iclass 21, count 0 2006.161.07:31:10.58#ibcon#about to read 3, iclass 21, count 0 2006.161.07:31:10.60#ibcon#read 3, iclass 21, count 0 2006.161.07:31:10.60#ibcon#about to read 4, iclass 21, count 0 2006.161.07:31:10.60#ibcon#read 4, iclass 21, count 0 2006.161.07:31:10.60#ibcon#about to read 5, iclass 21, count 0 2006.161.07:31:10.60#ibcon#read 5, iclass 21, count 0 2006.161.07:31:10.60#ibcon#about to read 6, iclass 21, count 0 2006.161.07:31:10.60#ibcon#read 6, iclass 21, count 0 2006.161.07:31:10.60#ibcon#end of sib2, iclass 21, count 0 2006.161.07:31:10.60#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:31:10.60#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:31:10.60#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:31:10.60#ibcon#*before write, iclass 21, count 0 2006.161.07:31:10.60#ibcon#enter sib2, iclass 21, count 0 2006.161.07:31:10.60#ibcon#flushed, iclass 21, count 0 2006.161.07:31:10.60#ibcon#about to write, iclass 21, count 0 2006.161.07:31:10.60#ibcon#wrote, iclass 21, count 0 2006.161.07:31:10.60#ibcon#about to read 3, iclass 21, count 0 2006.161.07:31:10.64#ibcon#read 3, iclass 21, count 0 2006.161.07:31:10.64#ibcon#about to read 4, iclass 21, count 0 2006.161.07:31:10.64#ibcon#read 4, iclass 21, count 0 2006.161.07:31:10.64#ibcon#about to read 5, iclass 21, count 0 2006.161.07:31:10.64#ibcon#read 5, iclass 21, count 0 2006.161.07:31:10.64#ibcon#about to read 6, iclass 21, count 0 2006.161.07:31:10.64#ibcon#read 6, iclass 21, count 0 2006.161.07:31:10.64#ibcon#end of sib2, iclass 21, count 0 2006.161.07:31:10.64#ibcon#*after write, iclass 21, count 0 2006.161.07:31:10.64#ibcon#*before return 0, iclass 21, count 0 2006.161.07:31:10.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:31:10.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:31:10.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:31:10.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:31:10.64$vc4f8/va=7,6 2006.161.07:31:10.64#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.07:31:10.64#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.07:31:10.64#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:10.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:31:10.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:31:10.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:31:10.70#ibcon#enter wrdev, iclass 23, count 2 2006.161.07:31:10.70#ibcon#first serial, iclass 23, count 2 2006.161.07:31:10.70#ibcon#enter sib2, iclass 23, count 2 2006.161.07:31:10.70#ibcon#flushed, iclass 23, count 2 2006.161.07:31:10.70#ibcon#about to write, iclass 23, count 2 2006.161.07:31:10.70#ibcon#wrote, iclass 23, count 2 2006.161.07:31:10.70#ibcon#about to read 3, iclass 23, count 2 2006.161.07:31:10.72#ibcon#read 3, iclass 23, count 2 2006.161.07:31:10.72#ibcon#about to read 4, iclass 23, count 2 2006.161.07:31:10.72#ibcon#read 4, iclass 23, count 2 2006.161.07:31:10.72#ibcon#about to read 5, iclass 23, count 2 2006.161.07:31:10.72#ibcon#read 5, iclass 23, count 2 2006.161.07:31:10.72#ibcon#about to read 6, iclass 23, count 2 2006.161.07:31:10.72#ibcon#read 6, iclass 23, count 2 2006.161.07:31:10.72#ibcon#end of sib2, iclass 23, count 2 2006.161.07:31:10.72#ibcon#*mode == 0, iclass 23, count 2 2006.161.07:31:10.72#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.07:31:10.72#ibcon#[25=AT07-06\r\n] 2006.161.07:31:10.72#ibcon#*before write, iclass 23, count 2 2006.161.07:31:10.72#ibcon#enter sib2, iclass 23, count 2 2006.161.07:31:10.72#ibcon#flushed, iclass 23, count 2 2006.161.07:31:10.72#ibcon#about to write, iclass 23, count 2 2006.161.07:31:10.72#ibcon#wrote, iclass 23, count 2 2006.161.07:31:10.72#ibcon#about to read 3, iclass 23, count 2 2006.161.07:31:10.75#ibcon#read 3, iclass 23, count 2 2006.161.07:31:10.75#ibcon#about to read 4, iclass 23, count 2 2006.161.07:31:10.75#ibcon#read 4, iclass 23, count 2 2006.161.07:31:10.75#ibcon#about to read 5, iclass 23, count 2 2006.161.07:31:10.75#ibcon#read 5, iclass 23, count 2 2006.161.07:31:10.75#ibcon#about to read 6, iclass 23, count 2 2006.161.07:31:10.75#ibcon#read 6, iclass 23, count 2 2006.161.07:31:10.75#ibcon#end of sib2, iclass 23, count 2 2006.161.07:31:10.75#ibcon#*after write, iclass 23, count 2 2006.161.07:31:10.75#ibcon#*before return 0, iclass 23, count 2 2006.161.07:31:10.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:31:10.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:31:10.75#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.07:31:10.75#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:10.75#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:31:10.87#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:31:10.87#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:31:10.87#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:31:10.87#ibcon#first serial, iclass 23, count 0 2006.161.07:31:10.87#ibcon#enter sib2, iclass 23, count 0 2006.161.07:31:10.87#ibcon#flushed, iclass 23, count 0 2006.161.07:31:10.87#ibcon#about to write, iclass 23, count 0 2006.161.07:31:10.87#ibcon#wrote, iclass 23, count 0 2006.161.07:31:10.87#ibcon#about to read 3, iclass 23, count 0 2006.161.07:31:10.89#ibcon#read 3, iclass 23, count 0 2006.161.07:31:10.89#ibcon#about to read 4, iclass 23, count 0 2006.161.07:31:10.89#ibcon#read 4, iclass 23, count 0 2006.161.07:31:10.89#ibcon#about to read 5, iclass 23, count 0 2006.161.07:31:10.89#ibcon#read 5, iclass 23, count 0 2006.161.07:31:10.89#ibcon#about to read 6, iclass 23, count 0 2006.161.07:31:10.89#ibcon#read 6, iclass 23, count 0 2006.161.07:31:10.89#ibcon#end of sib2, iclass 23, count 0 2006.161.07:31:10.89#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:31:10.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:31:10.89#ibcon#[25=USB\r\n] 2006.161.07:31:10.89#ibcon#*before write, iclass 23, count 0 2006.161.07:31:10.89#ibcon#enter sib2, iclass 23, count 0 2006.161.07:31:10.89#ibcon#flushed, iclass 23, count 0 2006.161.07:31:10.89#ibcon#about to write, iclass 23, count 0 2006.161.07:31:10.89#ibcon#wrote, iclass 23, count 0 2006.161.07:31:10.89#ibcon#about to read 3, iclass 23, count 0 2006.161.07:31:10.92#ibcon#read 3, iclass 23, count 0 2006.161.07:31:10.92#ibcon#about to read 4, iclass 23, count 0 2006.161.07:31:10.92#ibcon#read 4, iclass 23, count 0 2006.161.07:31:10.92#ibcon#about to read 5, iclass 23, count 0 2006.161.07:31:10.92#ibcon#read 5, iclass 23, count 0 2006.161.07:31:10.92#ibcon#about to read 6, iclass 23, count 0 2006.161.07:31:10.92#ibcon#read 6, iclass 23, count 0 2006.161.07:31:10.92#ibcon#end of sib2, iclass 23, count 0 2006.161.07:31:10.92#ibcon#*after write, iclass 23, count 0 2006.161.07:31:10.92#ibcon#*before return 0, iclass 23, count 0 2006.161.07:31:10.92#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:31:10.92#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:31:10.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:31:10.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:31:10.92$vc4f8/valo=8,852.99 2006.161.07:31:10.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.07:31:10.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.07:31:10.92#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:10.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:31:10.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:31:10.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:31:10.92#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:31:10.92#ibcon#first serial, iclass 25, count 0 2006.161.07:31:10.92#ibcon#enter sib2, iclass 25, count 0 2006.161.07:31:10.92#ibcon#flushed, iclass 25, count 0 2006.161.07:31:10.92#ibcon#about to write, iclass 25, count 0 2006.161.07:31:10.92#ibcon#wrote, iclass 25, count 0 2006.161.07:31:10.92#ibcon#about to read 3, iclass 25, count 0 2006.161.07:31:10.94#ibcon#read 3, iclass 25, count 0 2006.161.07:31:10.94#ibcon#about to read 4, iclass 25, count 0 2006.161.07:31:10.94#ibcon#read 4, iclass 25, count 0 2006.161.07:31:10.94#ibcon#about to read 5, iclass 25, count 0 2006.161.07:31:10.94#ibcon#read 5, iclass 25, count 0 2006.161.07:31:10.94#ibcon#about to read 6, iclass 25, count 0 2006.161.07:31:10.94#ibcon#read 6, iclass 25, count 0 2006.161.07:31:10.94#ibcon#end of sib2, iclass 25, count 0 2006.161.07:31:10.94#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:31:10.94#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:31:10.94#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:31:10.94#ibcon#*before write, iclass 25, count 0 2006.161.07:31:10.94#ibcon#enter sib2, iclass 25, count 0 2006.161.07:31:10.94#ibcon#flushed, iclass 25, count 0 2006.161.07:31:10.94#ibcon#about to write, iclass 25, count 0 2006.161.07:31:10.94#ibcon#wrote, iclass 25, count 0 2006.161.07:31:10.94#ibcon#about to read 3, iclass 25, count 0 2006.161.07:31:10.98#ibcon#read 3, iclass 25, count 0 2006.161.07:31:10.98#ibcon#about to read 4, iclass 25, count 0 2006.161.07:31:10.98#ibcon#read 4, iclass 25, count 0 2006.161.07:31:10.98#ibcon#about to read 5, iclass 25, count 0 2006.161.07:31:10.98#ibcon#read 5, iclass 25, count 0 2006.161.07:31:10.98#ibcon#about to read 6, iclass 25, count 0 2006.161.07:31:10.98#ibcon#read 6, iclass 25, count 0 2006.161.07:31:10.98#ibcon#end of sib2, iclass 25, count 0 2006.161.07:31:10.98#ibcon#*after write, iclass 25, count 0 2006.161.07:31:10.98#ibcon#*before return 0, iclass 25, count 0 2006.161.07:31:10.98#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:31:10.98#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:31:10.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:31:10.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:31:10.98$vc4f8/va=8,7 2006.161.07:31:10.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.07:31:10.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.07:31:10.98#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:10.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:31:11.04#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:31:11.04#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:31:11.04#ibcon#enter wrdev, iclass 27, count 2 2006.161.07:31:11.04#ibcon#first serial, iclass 27, count 2 2006.161.07:31:11.04#ibcon#enter sib2, iclass 27, count 2 2006.161.07:31:11.04#ibcon#flushed, iclass 27, count 2 2006.161.07:31:11.04#ibcon#about to write, iclass 27, count 2 2006.161.07:31:11.04#ibcon#wrote, iclass 27, count 2 2006.161.07:31:11.04#ibcon#about to read 3, iclass 27, count 2 2006.161.07:31:11.06#ibcon#read 3, iclass 27, count 2 2006.161.07:31:11.06#ibcon#about to read 4, iclass 27, count 2 2006.161.07:31:11.06#ibcon#read 4, iclass 27, count 2 2006.161.07:31:11.06#ibcon#about to read 5, iclass 27, count 2 2006.161.07:31:11.06#ibcon#read 5, iclass 27, count 2 2006.161.07:31:11.06#ibcon#about to read 6, iclass 27, count 2 2006.161.07:31:11.06#ibcon#read 6, iclass 27, count 2 2006.161.07:31:11.06#ibcon#end of sib2, iclass 27, count 2 2006.161.07:31:11.06#ibcon#*mode == 0, iclass 27, count 2 2006.161.07:31:11.06#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.07:31:11.06#ibcon#[25=AT08-07\r\n] 2006.161.07:31:11.06#ibcon#*before write, iclass 27, count 2 2006.161.07:31:11.06#ibcon#enter sib2, iclass 27, count 2 2006.161.07:31:11.06#ibcon#flushed, iclass 27, count 2 2006.161.07:31:11.06#ibcon#about to write, iclass 27, count 2 2006.161.07:31:11.06#ibcon#wrote, iclass 27, count 2 2006.161.07:31:11.06#ibcon#about to read 3, iclass 27, count 2 2006.161.07:31:11.09#ibcon#read 3, iclass 27, count 2 2006.161.07:31:11.09#ibcon#about to read 4, iclass 27, count 2 2006.161.07:31:11.09#ibcon#read 4, iclass 27, count 2 2006.161.07:31:11.09#ibcon#about to read 5, iclass 27, count 2 2006.161.07:31:11.09#ibcon#read 5, iclass 27, count 2 2006.161.07:31:11.09#ibcon#about to read 6, iclass 27, count 2 2006.161.07:31:11.09#ibcon#read 6, iclass 27, count 2 2006.161.07:31:11.09#ibcon#end of sib2, iclass 27, count 2 2006.161.07:31:11.09#ibcon#*after write, iclass 27, count 2 2006.161.07:31:11.09#ibcon#*before return 0, iclass 27, count 2 2006.161.07:31:11.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:31:11.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:31:11.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.07:31:11.09#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:11.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:31:11.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:31:11.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:31:11.21#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:31:11.21#ibcon#first serial, iclass 27, count 0 2006.161.07:31:11.21#ibcon#enter sib2, iclass 27, count 0 2006.161.07:31:11.21#ibcon#flushed, iclass 27, count 0 2006.161.07:31:11.21#ibcon#about to write, iclass 27, count 0 2006.161.07:31:11.21#ibcon#wrote, iclass 27, count 0 2006.161.07:31:11.21#ibcon#about to read 3, iclass 27, count 0 2006.161.07:31:11.23#ibcon#read 3, iclass 27, count 0 2006.161.07:31:11.23#ibcon#about to read 4, iclass 27, count 0 2006.161.07:31:11.23#ibcon#read 4, iclass 27, count 0 2006.161.07:31:11.23#ibcon#about to read 5, iclass 27, count 0 2006.161.07:31:11.23#ibcon#read 5, iclass 27, count 0 2006.161.07:31:11.23#ibcon#about to read 6, iclass 27, count 0 2006.161.07:31:11.23#ibcon#read 6, iclass 27, count 0 2006.161.07:31:11.23#ibcon#end of sib2, iclass 27, count 0 2006.161.07:31:11.23#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:31:11.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:31:11.23#ibcon#[25=USB\r\n] 2006.161.07:31:11.23#ibcon#*before write, iclass 27, count 0 2006.161.07:31:11.23#ibcon#enter sib2, iclass 27, count 0 2006.161.07:31:11.23#ibcon#flushed, iclass 27, count 0 2006.161.07:31:11.23#ibcon#about to write, iclass 27, count 0 2006.161.07:31:11.23#ibcon#wrote, iclass 27, count 0 2006.161.07:31:11.23#ibcon#about to read 3, iclass 27, count 0 2006.161.07:31:11.26#ibcon#read 3, iclass 27, count 0 2006.161.07:31:11.26#ibcon#about to read 4, iclass 27, count 0 2006.161.07:31:11.26#ibcon#read 4, iclass 27, count 0 2006.161.07:31:11.26#ibcon#about to read 5, iclass 27, count 0 2006.161.07:31:11.26#ibcon#read 5, iclass 27, count 0 2006.161.07:31:11.26#ibcon#about to read 6, iclass 27, count 0 2006.161.07:31:11.26#ibcon#read 6, iclass 27, count 0 2006.161.07:31:11.26#ibcon#end of sib2, iclass 27, count 0 2006.161.07:31:11.26#ibcon#*after write, iclass 27, count 0 2006.161.07:31:11.26#ibcon#*before return 0, iclass 27, count 0 2006.161.07:31:11.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:31:11.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:31:11.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:31:11.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:31:11.26$vc4f8/vblo=1,632.99 2006.161.07:31:11.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.07:31:11.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.07:31:11.26#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:11.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:31:11.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:31:11.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:31:11.26#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:31:11.26#ibcon#first serial, iclass 29, count 0 2006.161.07:31:11.26#ibcon#enter sib2, iclass 29, count 0 2006.161.07:31:11.26#ibcon#flushed, iclass 29, count 0 2006.161.07:31:11.26#ibcon#about to write, iclass 29, count 0 2006.161.07:31:11.26#ibcon#wrote, iclass 29, count 0 2006.161.07:31:11.26#ibcon#about to read 3, iclass 29, count 0 2006.161.07:31:11.28#ibcon#read 3, iclass 29, count 0 2006.161.07:31:11.28#ibcon#about to read 4, iclass 29, count 0 2006.161.07:31:11.28#ibcon#read 4, iclass 29, count 0 2006.161.07:31:11.28#ibcon#about to read 5, iclass 29, count 0 2006.161.07:31:11.28#ibcon#read 5, iclass 29, count 0 2006.161.07:31:11.28#ibcon#about to read 6, iclass 29, count 0 2006.161.07:31:11.28#ibcon#read 6, iclass 29, count 0 2006.161.07:31:11.28#ibcon#end of sib2, iclass 29, count 0 2006.161.07:31:11.28#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:31:11.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:31:11.28#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:31:11.28#ibcon#*before write, iclass 29, count 0 2006.161.07:31:11.28#ibcon#enter sib2, iclass 29, count 0 2006.161.07:31:11.28#ibcon#flushed, iclass 29, count 0 2006.161.07:31:11.28#ibcon#about to write, iclass 29, count 0 2006.161.07:31:11.28#ibcon#wrote, iclass 29, count 0 2006.161.07:31:11.28#ibcon#about to read 3, iclass 29, count 0 2006.161.07:31:11.32#ibcon#read 3, iclass 29, count 0 2006.161.07:31:11.32#ibcon#about to read 4, iclass 29, count 0 2006.161.07:31:11.32#ibcon#read 4, iclass 29, count 0 2006.161.07:31:11.32#ibcon#about to read 5, iclass 29, count 0 2006.161.07:31:11.32#ibcon#read 5, iclass 29, count 0 2006.161.07:31:11.32#ibcon#about to read 6, iclass 29, count 0 2006.161.07:31:11.32#ibcon#read 6, iclass 29, count 0 2006.161.07:31:11.32#ibcon#end of sib2, iclass 29, count 0 2006.161.07:31:11.32#ibcon#*after write, iclass 29, count 0 2006.161.07:31:11.32#ibcon#*before return 0, iclass 29, count 0 2006.161.07:31:11.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:31:11.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:31:11.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:31:11.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:31:11.32$vc4f8/vb=1,4 2006.161.07:31:11.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.07:31:11.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.07:31:11.32#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:11.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:31:11.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:31:11.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:31:11.32#ibcon#enter wrdev, iclass 31, count 2 2006.161.07:31:11.32#ibcon#first serial, iclass 31, count 2 2006.161.07:31:11.32#ibcon#enter sib2, iclass 31, count 2 2006.161.07:31:11.32#ibcon#flushed, iclass 31, count 2 2006.161.07:31:11.32#ibcon#about to write, iclass 31, count 2 2006.161.07:31:11.32#ibcon#wrote, iclass 31, count 2 2006.161.07:31:11.32#ibcon#about to read 3, iclass 31, count 2 2006.161.07:31:11.34#ibcon#read 3, iclass 31, count 2 2006.161.07:31:11.34#ibcon#about to read 4, iclass 31, count 2 2006.161.07:31:11.34#ibcon#read 4, iclass 31, count 2 2006.161.07:31:11.34#ibcon#about to read 5, iclass 31, count 2 2006.161.07:31:11.34#ibcon#read 5, iclass 31, count 2 2006.161.07:31:11.34#ibcon#about to read 6, iclass 31, count 2 2006.161.07:31:11.34#ibcon#read 6, iclass 31, count 2 2006.161.07:31:11.34#ibcon#end of sib2, iclass 31, count 2 2006.161.07:31:11.34#ibcon#*mode == 0, iclass 31, count 2 2006.161.07:31:11.34#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.07:31:11.34#ibcon#[27=AT01-04\r\n] 2006.161.07:31:11.34#ibcon#*before write, iclass 31, count 2 2006.161.07:31:11.34#ibcon#enter sib2, iclass 31, count 2 2006.161.07:31:11.34#ibcon#flushed, iclass 31, count 2 2006.161.07:31:11.34#ibcon#about to write, iclass 31, count 2 2006.161.07:31:11.34#ibcon#wrote, iclass 31, count 2 2006.161.07:31:11.34#ibcon#about to read 3, iclass 31, count 2 2006.161.07:31:11.37#ibcon#read 3, iclass 31, count 2 2006.161.07:31:11.37#ibcon#about to read 4, iclass 31, count 2 2006.161.07:31:11.37#ibcon#read 4, iclass 31, count 2 2006.161.07:31:11.37#ibcon#about to read 5, iclass 31, count 2 2006.161.07:31:11.37#ibcon#read 5, iclass 31, count 2 2006.161.07:31:11.37#ibcon#about to read 6, iclass 31, count 2 2006.161.07:31:11.37#ibcon#read 6, iclass 31, count 2 2006.161.07:31:11.37#ibcon#end of sib2, iclass 31, count 2 2006.161.07:31:11.37#ibcon#*after write, iclass 31, count 2 2006.161.07:31:11.37#ibcon#*before return 0, iclass 31, count 2 2006.161.07:31:11.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:31:11.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:31:11.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.07:31:11.37#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:11.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:31:11.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:31:11.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:31:11.49#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:31:11.49#ibcon#first serial, iclass 31, count 0 2006.161.07:31:11.49#ibcon#enter sib2, iclass 31, count 0 2006.161.07:31:11.49#ibcon#flushed, iclass 31, count 0 2006.161.07:31:11.49#ibcon#about to write, iclass 31, count 0 2006.161.07:31:11.49#ibcon#wrote, iclass 31, count 0 2006.161.07:31:11.49#ibcon#about to read 3, iclass 31, count 0 2006.161.07:31:11.51#ibcon#read 3, iclass 31, count 0 2006.161.07:31:11.51#ibcon#about to read 4, iclass 31, count 0 2006.161.07:31:11.51#ibcon#read 4, iclass 31, count 0 2006.161.07:31:11.51#ibcon#about to read 5, iclass 31, count 0 2006.161.07:31:11.51#ibcon#read 5, iclass 31, count 0 2006.161.07:31:11.51#ibcon#about to read 6, iclass 31, count 0 2006.161.07:31:11.51#ibcon#read 6, iclass 31, count 0 2006.161.07:31:11.51#ibcon#end of sib2, iclass 31, count 0 2006.161.07:31:11.51#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:31:11.51#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:31:11.51#ibcon#[27=USB\r\n] 2006.161.07:31:11.51#ibcon#*before write, iclass 31, count 0 2006.161.07:31:11.51#ibcon#enter sib2, iclass 31, count 0 2006.161.07:31:11.51#ibcon#flushed, iclass 31, count 0 2006.161.07:31:11.51#ibcon#about to write, iclass 31, count 0 2006.161.07:31:11.51#ibcon#wrote, iclass 31, count 0 2006.161.07:31:11.51#ibcon#about to read 3, iclass 31, count 0 2006.161.07:31:11.54#ibcon#read 3, iclass 31, count 0 2006.161.07:31:11.54#ibcon#about to read 4, iclass 31, count 0 2006.161.07:31:11.54#ibcon#read 4, iclass 31, count 0 2006.161.07:31:11.54#ibcon#about to read 5, iclass 31, count 0 2006.161.07:31:11.54#ibcon#read 5, iclass 31, count 0 2006.161.07:31:11.54#ibcon#about to read 6, iclass 31, count 0 2006.161.07:31:11.54#ibcon#read 6, iclass 31, count 0 2006.161.07:31:11.54#ibcon#end of sib2, iclass 31, count 0 2006.161.07:31:11.54#ibcon#*after write, iclass 31, count 0 2006.161.07:31:11.54#ibcon#*before return 0, iclass 31, count 0 2006.161.07:31:11.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:31:11.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:31:11.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:31:11.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:31:11.54$vc4f8/vblo=2,640.99 2006.161.07:31:11.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:31:11.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:31:11.54#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:11.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:11.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:11.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:11.54#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:31:11.54#ibcon#first serial, iclass 33, count 0 2006.161.07:31:11.54#ibcon#enter sib2, iclass 33, count 0 2006.161.07:31:11.54#ibcon#flushed, iclass 33, count 0 2006.161.07:31:11.54#ibcon#about to write, iclass 33, count 0 2006.161.07:31:11.54#ibcon#wrote, iclass 33, count 0 2006.161.07:31:11.54#ibcon#about to read 3, iclass 33, count 0 2006.161.07:31:11.56#ibcon#read 3, iclass 33, count 0 2006.161.07:31:11.56#ibcon#about to read 4, iclass 33, count 0 2006.161.07:31:11.56#ibcon#read 4, iclass 33, count 0 2006.161.07:31:11.56#ibcon#about to read 5, iclass 33, count 0 2006.161.07:31:11.56#ibcon#read 5, iclass 33, count 0 2006.161.07:31:11.56#ibcon#about to read 6, iclass 33, count 0 2006.161.07:31:11.56#ibcon#read 6, iclass 33, count 0 2006.161.07:31:11.56#ibcon#end of sib2, iclass 33, count 0 2006.161.07:31:11.56#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:31:11.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:31:11.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:31:11.56#ibcon#*before write, iclass 33, count 0 2006.161.07:31:11.56#ibcon#enter sib2, iclass 33, count 0 2006.161.07:31:11.56#ibcon#flushed, iclass 33, count 0 2006.161.07:31:11.56#ibcon#about to write, iclass 33, count 0 2006.161.07:31:11.56#ibcon#wrote, iclass 33, count 0 2006.161.07:31:11.56#ibcon#about to read 3, iclass 33, count 0 2006.161.07:31:11.61#ibcon#read 3, iclass 33, count 0 2006.161.07:31:11.61#ibcon#about to read 4, iclass 33, count 0 2006.161.07:31:11.61#ibcon#read 4, iclass 33, count 0 2006.161.07:31:11.61#ibcon#about to read 5, iclass 33, count 0 2006.161.07:31:11.61#ibcon#read 5, iclass 33, count 0 2006.161.07:31:11.61#ibcon#about to read 6, iclass 33, count 0 2006.161.07:31:11.61#ibcon#read 6, iclass 33, count 0 2006.161.07:31:11.61#ibcon#end of sib2, iclass 33, count 0 2006.161.07:31:11.61#ibcon#*after write, iclass 33, count 0 2006.161.07:31:11.61#ibcon#*before return 0, iclass 33, count 0 2006.161.07:31:11.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:11.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:31:11.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:31:11.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:31:11.61$vc4f8/vb=2,4 2006.161.07:31:11.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.07:31:11.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.07:31:11.61#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:11.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:11.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:11.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:11.65#ibcon#enter wrdev, iclass 35, count 2 2006.161.07:31:11.65#ibcon#first serial, iclass 35, count 2 2006.161.07:31:11.65#ibcon#enter sib2, iclass 35, count 2 2006.161.07:31:11.65#ibcon#flushed, iclass 35, count 2 2006.161.07:31:11.65#ibcon#about to write, iclass 35, count 2 2006.161.07:31:11.65#ibcon#wrote, iclass 35, count 2 2006.161.07:31:11.65#ibcon#about to read 3, iclass 35, count 2 2006.161.07:31:11.67#ibcon#read 3, iclass 35, count 2 2006.161.07:31:11.67#ibcon#about to read 4, iclass 35, count 2 2006.161.07:31:11.67#ibcon#read 4, iclass 35, count 2 2006.161.07:31:11.67#ibcon#about to read 5, iclass 35, count 2 2006.161.07:31:11.67#ibcon#read 5, iclass 35, count 2 2006.161.07:31:11.67#ibcon#about to read 6, iclass 35, count 2 2006.161.07:31:11.67#ibcon#read 6, iclass 35, count 2 2006.161.07:31:11.67#ibcon#end of sib2, iclass 35, count 2 2006.161.07:31:11.67#ibcon#*mode == 0, iclass 35, count 2 2006.161.07:31:11.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.07:31:11.67#ibcon#[27=AT02-04\r\n] 2006.161.07:31:11.67#ibcon#*before write, iclass 35, count 2 2006.161.07:31:11.67#ibcon#enter sib2, iclass 35, count 2 2006.161.07:31:11.67#ibcon#flushed, iclass 35, count 2 2006.161.07:31:11.67#ibcon#about to write, iclass 35, count 2 2006.161.07:31:11.67#ibcon#wrote, iclass 35, count 2 2006.161.07:31:11.67#ibcon#about to read 3, iclass 35, count 2 2006.161.07:31:11.70#ibcon#read 3, iclass 35, count 2 2006.161.07:31:11.70#ibcon#about to read 4, iclass 35, count 2 2006.161.07:31:11.70#ibcon#read 4, iclass 35, count 2 2006.161.07:31:11.70#ibcon#about to read 5, iclass 35, count 2 2006.161.07:31:11.70#ibcon#read 5, iclass 35, count 2 2006.161.07:31:11.70#ibcon#about to read 6, iclass 35, count 2 2006.161.07:31:11.70#ibcon#read 6, iclass 35, count 2 2006.161.07:31:11.70#ibcon#end of sib2, iclass 35, count 2 2006.161.07:31:11.70#ibcon#*after write, iclass 35, count 2 2006.161.07:31:11.70#ibcon#*before return 0, iclass 35, count 2 2006.161.07:31:11.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:11.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:31:11.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.07:31:11.70#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:11.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:11.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:11.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:11.82#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:31:11.82#ibcon#first serial, iclass 35, count 0 2006.161.07:31:11.82#ibcon#enter sib2, iclass 35, count 0 2006.161.07:31:11.82#ibcon#flushed, iclass 35, count 0 2006.161.07:31:11.82#ibcon#about to write, iclass 35, count 0 2006.161.07:31:11.82#ibcon#wrote, iclass 35, count 0 2006.161.07:31:11.82#ibcon#about to read 3, iclass 35, count 0 2006.161.07:31:11.84#ibcon#read 3, iclass 35, count 0 2006.161.07:31:11.84#ibcon#about to read 4, iclass 35, count 0 2006.161.07:31:11.84#ibcon#read 4, iclass 35, count 0 2006.161.07:31:11.84#ibcon#about to read 5, iclass 35, count 0 2006.161.07:31:11.84#ibcon#read 5, iclass 35, count 0 2006.161.07:31:11.84#ibcon#about to read 6, iclass 35, count 0 2006.161.07:31:11.84#ibcon#read 6, iclass 35, count 0 2006.161.07:31:11.84#ibcon#end of sib2, iclass 35, count 0 2006.161.07:31:11.84#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:31:11.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:31:11.84#ibcon#[27=USB\r\n] 2006.161.07:31:11.84#ibcon#*before write, iclass 35, count 0 2006.161.07:31:11.84#ibcon#enter sib2, iclass 35, count 0 2006.161.07:31:11.84#ibcon#flushed, iclass 35, count 0 2006.161.07:31:11.84#ibcon#about to write, iclass 35, count 0 2006.161.07:31:11.84#ibcon#wrote, iclass 35, count 0 2006.161.07:31:11.84#ibcon#about to read 3, iclass 35, count 0 2006.161.07:31:11.87#ibcon#read 3, iclass 35, count 0 2006.161.07:31:11.87#ibcon#about to read 4, iclass 35, count 0 2006.161.07:31:11.87#ibcon#read 4, iclass 35, count 0 2006.161.07:31:11.87#ibcon#about to read 5, iclass 35, count 0 2006.161.07:31:11.87#ibcon#read 5, iclass 35, count 0 2006.161.07:31:11.87#ibcon#about to read 6, iclass 35, count 0 2006.161.07:31:11.87#ibcon#read 6, iclass 35, count 0 2006.161.07:31:11.87#ibcon#end of sib2, iclass 35, count 0 2006.161.07:31:11.87#ibcon#*after write, iclass 35, count 0 2006.161.07:31:11.87#ibcon#*before return 0, iclass 35, count 0 2006.161.07:31:11.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:11.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:31:11.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:31:11.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:31:11.87$vc4f8/vblo=3,656.99 2006.161.07:31:11.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:31:11.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:31:11.87#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:11.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:11.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:11.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:11.87#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:31:11.87#ibcon#first serial, iclass 37, count 0 2006.161.07:31:11.87#ibcon#enter sib2, iclass 37, count 0 2006.161.07:31:11.87#ibcon#flushed, iclass 37, count 0 2006.161.07:31:11.87#ibcon#about to write, iclass 37, count 0 2006.161.07:31:11.87#ibcon#wrote, iclass 37, count 0 2006.161.07:31:11.87#ibcon#about to read 3, iclass 37, count 0 2006.161.07:31:11.89#ibcon#read 3, iclass 37, count 0 2006.161.07:31:11.89#ibcon#about to read 4, iclass 37, count 0 2006.161.07:31:11.89#ibcon#read 4, iclass 37, count 0 2006.161.07:31:11.89#ibcon#about to read 5, iclass 37, count 0 2006.161.07:31:11.89#ibcon#read 5, iclass 37, count 0 2006.161.07:31:11.89#ibcon#about to read 6, iclass 37, count 0 2006.161.07:31:11.89#ibcon#read 6, iclass 37, count 0 2006.161.07:31:11.89#ibcon#end of sib2, iclass 37, count 0 2006.161.07:31:11.89#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:31:11.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:31:11.89#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:31:11.89#ibcon#*before write, iclass 37, count 0 2006.161.07:31:11.89#ibcon#enter sib2, iclass 37, count 0 2006.161.07:31:11.89#ibcon#flushed, iclass 37, count 0 2006.161.07:31:11.89#ibcon#about to write, iclass 37, count 0 2006.161.07:31:11.89#ibcon#wrote, iclass 37, count 0 2006.161.07:31:11.89#ibcon#about to read 3, iclass 37, count 0 2006.161.07:31:11.93#ibcon#read 3, iclass 37, count 0 2006.161.07:31:11.93#ibcon#about to read 4, iclass 37, count 0 2006.161.07:31:11.93#ibcon#read 4, iclass 37, count 0 2006.161.07:31:11.93#ibcon#about to read 5, iclass 37, count 0 2006.161.07:31:11.93#ibcon#read 5, iclass 37, count 0 2006.161.07:31:11.93#ibcon#about to read 6, iclass 37, count 0 2006.161.07:31:11.93#ibcon#read 6, iclass 37, count 0 2006.161.07:31:11.93#ibcon#end of sib2, iclass 37, count 0 2006.161.07:31:11.93#ibcon#*after write, iclass 37, count 0 2006.161.07:31:11.93#ibcon#*before return 0, iclass 37, count 0 2006.161.07:31:11.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:11.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:31:11.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:31:11.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:31:11.93$vc4f8/vb=3,4 2006.161.07:31:11.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.07:31:11.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.07:31:11.93#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:11.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:11.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:11.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:11.99#ibcon#enter wrdev, iclass 39, count 2 2006.161.07:31:11.99#ibcon#first serial, iclass 39, count 2 2006.161.07:31:11.99#ibcon#enter sib2, iclass 39, count 2 2006.161.07:31:11.99#ibcon#flushed, iclass 39, count 2 2006.161.07:31:11.99#ibcon#about to write, iclass 39, count 2 2006.161.07:31:11.99#ibcon#wrote, iclass 39, count 2 2006.161.07:31:11.99#ibcon#about to read 3, iclass 39, count 2 2006.161.07:31:12.01#ibcon#read 3, iclass 39, count 2 2006.161.07:31:12.01#ibcon#about to read 4, iclass 39, count 2 2006.161.07:31:12.01#ibcon#read 4, iclass 39, count 2 2006.161.07:31:12.01#ibcon#about to read 5, iclass 39, count 2 2006.161.07:31:12.01#ibcon#read 5, iclass 39, count 2 2006.161.07:31:12.01#ibcon#about to read 6, iclass 39, count 2 2006.161.07:31:12.01#ibcon#read 6, iclass 39, count 2 2006.161.07:31:12.01#ibcon#end of sib2, iclass 39, count 2 2006.161.07:31:12.01#ibcon#*mode == 0, iclass 39, count 2 2006.161.07:31:12.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.07:31:12.01#ibcon#[27=AT03-04\r\n] 2006.161.07:31:12.01#ibcon#*before write, iclass 39, count 2 2006.161.07:31:12.01#ibcon#enter sib2, iclass 39, count 2 2006.161.07:31:12.01#ibcon#flushed, iclass 39, count 2 2006.161.07:31:12.01#ibcon#about to write, iclass 39, count 2 2006.161.07:31:12.01#ibcon#wrote, iclass 39, count 2 2006.161.07:31:12.01#ibcon#about to read 3, iclass 39, count 2 2006.161.07:31:12.04#ibcon#read 3, iclass 39, count 2 2006.161.07:31:12.04#ibcon#about to read 4, iclass 39, count 2 2006.161.07:31:12.04#ibcon#read 4, iclass 39, count 2 2006.161.07:31:12.04#ibcon#about to read 5, iclass 39, count 2 2006.161.07:31:12.04#ibcon#read 5, iclass 39, count 2 2006.161.07:31:12.04#ibcon#about to read 6, iclass 39, count 2 2006.161.07:31:12.04#ibcon#read 6, iclass 39, count 2 2006.161.07:31:12.04#ibcon#end of sib2, iclass 39, count 2 2006.161.07:31:12.04#ibcon#*after write, iclass 39, count 2 2006.161.07:31:12.04#ibcon#*before return 0, iclass 39, count 2 2006.161.07:31:12.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:12.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:31:12.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.07:31:12.04#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:12.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:12.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:12.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:12.16#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:31:12.16#ibcon#first serial, iclass 39, count 0 2006.161.07:31:12.16#ibcon#enter sib2, iclass 39, count 0 2006.161.07:31:12.16#ibcon#flushed, iclass 39, count 0 2006.161.07:31:12.16#ibcon#about to write, iclass 39, count 0 2006.161.07:31:12.16#ibcon#wrote, iclass 39, count 0 2006.161.07:31:12.16#ibcon#about to read 3, iclass 39, count 0 2006.161.07:31:12.18#ibcon#read 3, iclass 39, count 0 2006.161.07:31:12.18#ibcon#about to read 4, iclass 39, count 0 2006.161.07:31:12.18#ibcon#read 4, iclass 39, count 0 2006.161.07:31:12.18#ibcon#about to read 5, iclass 39, count 0 2006.161.07:31:12.18#ibcon#read 5, iclass 39, count 0 2006.161.07:31:12.18#ibcon#about to read 6, iclass 39, count 0 2006.161.07:31:12.18#ibcon#read 6, iclass 39, count 0 2006.161.07:31:12.18#ibcon#end of sib2, iclass 39, count 0 2006.161.07:31:12.18#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:31:12.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:31:12.18#ibcon#[27=USB\r\n] 2006.161.07:31:12.18#ibcon#*before write, iclass 39, count 0 2006.161.07:31:12.18#ibcon#enter sib2, iclass 39, count 0 2006.161.07:31:12.18#ibcon#flushed, iclass 39, count 0 2006.161.07:31:12.18#ibcon#about to write, iclass 39, count 0 2006.161.07:31:12.18#ibcon#wrote, iclass 39, count 0 2006.161.07:31:12.18#ibcon#about to read 3, iclass 39, count 0 2006.161.07:31:12.21#ibcon#read 3, iclass 39, count 0 2006.161.07:31:12.21#ibcon#about to read 4, iclass 39, count 0 2006.161.07:31:12.21#ibcon#read 4, iclass 39, count 0 2006.161.07:31:12.21#ibcon#about to read 5, iclass 39, count 0 2006.161.07:31:12.21#ibcon#read 5, iclass 39, count 0 2006.161.07:31:12.21#ibcon#about to read 6, iclass 39, count 0 2006.161.07:31:12.21#ibcon#read 6, iclass 39, count 0 2006.161.07:31:12.21#ibcon#end of sib2, iclass 39, count 0 2006.161.07:31:12.21#ibcon#*after write, iclass 39, count 0 2006.161.07:31:12.21#ibcon#*before return 0, iclass 39, count 0 2006.161.07:31:12.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:12.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:31:12.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:31:12.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:31:12.21$vc4f8/vblo=4,712.99 2006.161.07:31:12.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.07:31:12.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.07:31:12.21#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:12.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:12.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:12.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:12.21#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:31:12.21#ibcon#first serial, iclass 3, count 0 2006.161.07:31:12.21#ibcon#enter sib2, iclass 3, count 0 2006.161.07:31:12.21#ibcon#flushed, iclass 3, count 0 2006.161.07:31:12.21#ibcon#about to write, iclass 3, count 0 2006.161.07:31:12.21#ibcon#wrote, iclass 3, count 0 2006.161.07:31:12.21#ibcon#about to read 3, iclass 3, count 0 2006.161.07:31:12.23#ibcon#read 3, iclass 3, count 0 2006.161.07:31:12.23#ibcon#about to read 4, iclass 3, count 0 2006.161.07:31:12.23#ibcon#read 4, iclass 3, count 0 2006.161.07:31:12.23#ibcon#about to read 5, iclass 3, count 0 2006.161.07:31:12.23#ibcon#read 5, iclass 3, count 0 2006.161.07:31:12.23#ibcon#about to read 6, iclass 3, count 0 2006.161.07:31:12.23#ibcon#read 6, iclass 3, count 0 2006.161.07:31:12.23#ibcon#end of sib2, iclass 3, count 0 2006.161.07:31:12.23#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:31:12.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:31:12.23#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:31:12.23#ibcon#*before write, iclass 3, count 0 2006.161.07:31:12.23#ibcon#enter sib2, iclass 3, count 0 2006.161.07:31:12.23#ibcon#flushed, iclass 3, count 0 2006.161.07:31:12.23#ibcon#about to write, iclass 3, count 0 2006.161.07:31:12.23#ibcon#wrote, iclass 3, count 0 2006.161.07:31:12.23#ibcon#about to read 3, iclass 3, count 0 2006.161.07:31:12.27#ibcon#read 3, iclass 3, count 0 2006.161.07:31:12.27#ibcon#about to read 4, iclass 3, count 0 2006.161.07:31:12.27#ibcon#read 4, iclass 3, count 0 2006.161.07:31:12.27#ibcon#about to read 5, iclass 3, count 0 2006.161.07:31:12.27#ibcon#read 5, iclass 3, count 0 2006.161.07:31:12.27#ibcon#about to read 6, iclass 3, count 0 2006.161.07:31:12.27#ibcon#read 6, iclass 3, count 0 2006.161.07:31:12.27#ibcon#end of sib2, iclass 3, count 0 2006.161.07:31:12.27#ibcon#*after write, iclass 3, count 0 2006.161.07:31:12.27#ibcon#*before return 0, iclass 3, count 0 2006.161.07:31:12.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:12.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:31:12.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:31:12.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:31:12.27$vc4f8/vb=4,4 2006.161.07:31:12.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.07:31:12.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.07:31:12.27#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:12.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:12.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:12.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:12.33#ibcon#enter wrdev, iclass 5, count 2 2006.161.07:31:12.33#ibcon#first serial, iclass 5, count 2 2006.161.07:31:12.33#ibcon#enter sib2, iclass 5, count 2 2006.161.07:31:12.33#ibcon#flushed, iclass 5, count 2 2006.161.07:31:12.33#ibcon#about to write, iclass 5, count 2 2006.161.07:31:12.33#ibcon#wrote, iclass 5, count 2 2006.161.07:31:12.33#ibcon#about to read 3, iclass 5, count 2 2006.161.07:31:12.35#ibcon#read 3, iclass 5, count 2 2006.161.07:31:12.35#ibcon#about to read 4, iclass 5, count 2 2006.161.07:31:12.35#ibcon#read 4, iclass 5, count 2 2006.161.07:31:12.35#ibcon#about to read 5, iclass 5, count 2 2006.161.07:31:12.35#ibcon#read 5, iclass 5, count 2 2006.161.07:31:12.35#ibcon#about to read 6, iclass 5, count 2 2006.161.07:31:12.35#ibcon#read 6, iclass 5, count 2 2006.161.07:31:12.35#ibcon#end of sib2, iclass 5, count 2 2006.161.07:31:12.35#ibcon#*mode == 0, iclass 5, count 2 2006.161.07:31:12.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.07:31:12.35#ibcon#[27=AT04-04\r\n] 2006.161.07:31:12.35#ibcon#*before write, iclass 5, count 2 2006.161.07:31:12.35#ibcon#enter sib2, iclass 5, count 2 2006.161.07:31:12.35#ibcon#flushed, iclass 5, count 2 2006.161.07:31:12.35#ibcon#about to write, iclass 5, count 2 2006.161.07:31:12.35#ibcon#wrote, iclass 5, count 2 2006.161.07:31:12.35#ibcon#about to read 3, iclass 5, count 2 2006.161.07:31:12.38#ibcon#read 3, iclass 5, count 2 2006.161.07:31:12.38#ibcon#about to read 4, iclass 5, count 2 2006.161.07:31:12.38#ibcon#read 4, iclass 5, count 2 2006.161.07:31:12.38#ibcon#about to read 5, iclass 5, count 2 2006.161.07:31:12.38#ibcon#read 5, iclass 5, count 2 2006.161.07:31:12.38#ibcon#about to read 6, iclass 5, count 2 2006.161.07:31:12.38#ibcon#read 6, iclass 5, count 2 2006.161.07:31:12.38#ibcon#end of sib2, iclass 5, count 2 2006.161.07:31:12.38#ibcon#*after write, iclass 5, count 2 2006.161.07:31:12.38#ibcon#*before return 0, iclass 5, count 2 2006.161.07:31:12.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:12.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:31:12.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.07:31:12.38#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:12.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:12.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:12.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:12.50#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:31:12.50#ibcon#first serial, iclass 5, count 0 2006.161.07:31:12.50#ibcon#enter sib2, iclass 5, count 0 2006.161.07:31:12.50#ibcon#flushed, iclass 5, count 0 2006.161.07:31:12.50#ibcon#about to write, iclass 5, count 0 2006.161.07:31:12.50#ibcon#wrote, iclass 5, count 0 2006.161.07:31:12.50#ibcon#about to read 3, iclass 5, count 0 2006.161.07:31:12.52#ibcon#read 3, iclass 5, count 0 2006.161.07:31:12.52#ibcon#about to read 4, iclass 5, count 0 2006.161.07:31:12.52#ibcon#read 4, iclass 5, count 0 2006.161.07:31:12.52#ibcon#about to read 5, iclass 5, count 0 2006.161.07:31:12.52#ibcon#read 5, iclass 5, count 0 2006.161.07:31:12.52#ibcon#about to read 6, iclass 5, count 0 2006.161.07:31:12.52#ibcon#read 6, iclass 5, count 0 2006.161.07:31:12.52#ibcon#end of sib2, iclass 5, count 0 2006.161.07:31:12.52#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:31:12.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:31:12.52#ibcon#[27=USB\r\n] 2006.161.07:31:12.52#ibcon#*before write, iclass 5, count 0 2006.161.07:31:12.52#ibcon#enter sib2, iclass 5, count 0 2006.161.07:31:12.52#ibcon#flushed, iclass 5, count 0 2006.161.07:31:12.52#ibcon#about to write, iclass 5, count 0 2006.161.07:31:12.52#ibcon#wrote, iclass 5, count 0 2006.161.07:31:12.52#ibcon#about to read 3, iclass 5, count 0 2006.161.07:31:12.55#ibcon#read 3, iclass 5, count 0 2006.161.07:31:12.55#ibcon#about to read 4, iclass 5, count 0 2006.161.07:31:12.55#ibcon#read 4, iclass 5, count 0 2006.161.07:31:12.55#ibcon#about to read 5, iclass 5, count 0 2006.161.07:31:12.55#ibcon#read 5, iclass 5, count 0 2006.161.07:31:12.55#ibcon#about to read 6, iclass 5, count 0 2006.161.07:31:12.55#ibcon#read 6, iclass 5, count 0 2006.161.07:31:12.55#ibcon#end of sib2, iclass 5, count 0 2006.161.07:31:12.55#ibcon#*after write, iclass 5, count 0 2006.161.07:31:12.55#ibcon#*before return 0, iclass 5, count 0 2006.161.07:31:12.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:12.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:31:12.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:31:12.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:31:12.55$vc4f8/vblo=5,744.99 2006.161.07:31:12.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:31:12.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:31:12.55#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:12.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:12.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:12.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:12.55#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:31:12.55#ibcon#first serial, iclass 7, count 0 2006.161.07:31:12.55#ibcon#enter sib2, iclass 7, count 0 2006.161.07:31:12.55#ibcon#flushed, iclass 7, count 0 2006.161.07:31:12.55#ibcon#about to write, iclass 7, count 0 2006.161.07:31:12.55#ibcon#wrote, iclass 7, count 0 2006.161.07:31:12.55#ibcon#about to read 3, iclass 7, count 0 2006.161.07:31:12.57#ibcon#read 3, iclass 7, count 0 2006.161.07:31:12.57#ibcon#about to read 4, iclass 7, count 0 2006.161.07:31:12.57#ibcon#read 4, iclass 7, count 0 2006.161.07:31:12.57#ibcon#about to read 5, iclass 7, count 0 2006.161.07:31:12.57#ibcon#read 5, iclass 7, count 0 2006.161.07:31:12.57#ibcon#about to read 6, iclass 7, count 0 2006.161.07:31:12.57#ibcon#read 6, iclass 7, count 0 2006.161.07:31:12.57#ibcon#end of sib2, iclass 7, count 0 2006.161.07:31:12.57#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:31:12.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:31:12.57#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:31:12.57#ibcon#*before write, iclass 7, count 0 2006.161.07:31:12.57#ibcon#enter sib2, iclass 7, count 0 2006.161.07:31:12.57#ibcon#flushed, iclass 7, count 0 2006.161.07:31:12.57#ibcon#about to write, iclass 7, count 0 2006.161.07:31:12.57#ibcon#wrote, iclass 7, count 0 2006.161.07:31:12.57#ibcon#about to read 3, iclass 7, count 0 2006.161.07:31:12.61#ibcon#read 3, iclass 7, count 0 2006.161.07:31:12.61#ibcon#about to read 4, iclass 7, count 0 2006.161.07:31:12.61#ibcon#read 4, iclass 7, count 0 2006.161.07:31:12.61#ibcon#about to read 5, iclass 7, count 0 2006.161.07:31:12.61#ibcon#read 5, iclass 7, count 0 2006.161.07:31:12.61#ibcon#about to read 6, iclass 7, count 0 2006.161.07:31:12.61#ibcon#read 6, iclass 7, count 0 2006.161.07:31:12.61#ibcon#end of sib2, iclass 7, count 0 2006.161.07:31:12.61#ibcon#*after write, iclass 7, count 0 2006.161.07:31:12.61#ibcon#*before return 0, iclass 7, count 0 2006.161.07:31:12.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:12.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:31:12.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:31:12.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:31:12.61$vc4f8/vb=5,4 2006.161.07:31:12.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:31:12.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:31:12.61#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:12.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:12.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:12.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:12.67#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:31:12.67#ibcon#first serial, iclass 11, count 2 2006.161.07:31:12.67#ibcon#enter sib2, iclass 11, count 2 2006.161.07:31:12.67#ibcon#flushed, iclass 11, count 2 2006.161.07:31:12.67#ibcon#about to write, iclass 11, count 2 2006.161.07:31:12.67#ibcon#wrote, iclass 11, count 2 2006.161.07:31:12.67#ibcon#about to read 3, iclass 11, count 2 2006.161.07:31:12.69#ibcon#read 3, iclass 11, count 2 2006.161.07:31:12.69#ibcon#about to read 4, iclass 11, count 2 2006.161.07:31:12.69#ibcon#read 4, iclass 11, count 2 2006.161.07:31:12.69#ibcon#about to read 5, iclass 11, count 2 2006.161.07:31:12.69#ibcon#read 5, iclass 11, count 2 2006.161.07:31:12.69#ibcon#about to read 6, iclass 11, count 2 2006.161.07:31:12.69#ibcon#read 6, iclass 11, count 2 2006.161.07:31:12.69#ibcon#end of sib2, iclass 11, count 2 2006.161.07:31:12.69#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:31:12.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:31:12.69#ibcon#[27=AT05-04\r\n] 2006.161.07:31:12.69#ibcon#*before write, iclass 11, count 2 2006.161.07:31:12.69#ibcon#enter sib2, iclass 11, count 2 2006.161.07:31:12.69#ibcon#flushed, iclass 11, count 2 2006.161.07:31:12.69#ibcon#about to write, iclass 11, count 2 2006.161.07:31:12.69#ibcon#wrote, iclass 11, count 2 2006.161.07:31:12.69#ibcon#about to read 3, iclass 11, count 2 2006.161.07:31:12.72#ibcon#read 3, iclass 11, count 2 2006.161.07:31:12.72#ibcon#about to read 4, iclass 11, count 2 2006.161.07:31:12.72#ibcon#read 4, iclass 11, count 2 2006.161.07:31:12.72#ibcon#about to read 5, iclass 11, count 2 2006.161.07:31:12.72#ibcon#read 5, iclass 11, count 2 2006.161.07:31:12.72#ibcon#about to read 6, iclass 11, count 2 2006.161.07:31:12.72#ibcon#read 6, iclass 11, count 2 2006.161.07:31:12.72#ibcon#end of sib2, iclass 11, count 2 2006.161.07:31:12.72#ibcon#*after write, iclass 11, count 2 2006.161.07:31:12.72#ibcon#*before return 0, iclass 11, count 2 2006.161.07:31:12.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:12.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:31:12.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:31:12.72#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:12.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:12.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:12.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:12.84#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:31:12.84#ibcon#first serial, iclass 11, count 0 2006.161.07:31:12.84#ibcon#enter sib2, iclass 11, count 0 2006.161.07:31:12.84#ibcon#flushed, iclass 11, count 0 2006.161.07:31:12.84#ibcon#about to write, iclass 11, count 0 2006.161.07:31:12.84#ibcon#wrote, iclass 11, count 0 2006.161.07:31:12.84#ibcon#about to read 3, iclass 11, count 0 2006.161.07:31:12.86#ibcon#read 3, iclass 11, count 0 2006.161.07:31:12.86#ibcon#about to read 4, iclass 11, count 0 2006.161.07:31:12.86#ibcon#read 4, iclass 11, count 0 2006.161.07:31:12.86#ibcon#about to read 5, iclass 11, count 0 2006.161.07:31:12.86#ibcon#read 5, iclass 11, count 0 2006.161.07:31:12.86#ibcon#about to read 6, iclass 11, count 0 2006.161.07:31:12.86#ibcon#read 6, iclass 11, count 0 2006.161.07:31:12.86#ibcon#end of sib2, iclass 11, count 0 2006.161.07:31:12.86#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:31:12.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:31:12.86#ibcon#[27=USB\r\n] 2006.161.07:31:12.86#ibcon#*before write, iclass 11, count 0 2006.161.07:31:12.86#ibcon#enter sib2, iclass 11, count 0 2006.161.07:31:12.86#ibcon#flushed, iclass 11, count 0 2006.161.07:31:12.86#ibcon#about to write, iclass 11, count 0 2006.161.07:31:12.86#ibcon#wrote, iclass 11, count 0 2006.161.07:31:12.86#ibcon#about to read 3, iclass 11, count 0 2006.161.07:31:12.89#ibcon#read 3, iclass 11, count 0 2006.161.07:31:12.89#ibcon#about to read 4, iclass 11, count 0 2006.161.07:31:12.89#ibcon#read 4, iclass 11, count 0 2006.161.07:31:12.89#ibcon#about to read 5, iclass 11, count 0 2006.161.07:31:12.89#ibcon#read 5, iclass 11, count 0 2006.161.07:31:12.89#ibcon#about to read 6, iclass 11, count 0 2006.161.07:31:12.89#ibcon#read 6, iclass 11, count 0 2006.161.07:31:12.89#ibcon#end of sib2, iclass 11, count 0 2006.161.07:31:12.89#ibcon#*after write, iclass 11, count 0 2006.161.07:31:12.89#ibcon#*before return 0, iclass 11, count 0 2006.161.07:31:12.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:12.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:31:12.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:31:12.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:31:12.89$vc4f8/vblo=6,752.99 2006.161.07:31:12.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:31:12.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:31:12.89#ibcon#ireg 17 cls_cnt 0 2006.161.07:31:12.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:12.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:12.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:12.89#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:31:12.89#ibcon#first serial, iclass 13, count 0 2006.161.07:31:12.89#ibcon#enter sib2, iclass 13, count 0 2006.161.07:31:12.89#ibcon#flushed, iclass 13, count 0 2006.161.07:31:12.89#ibcon#about to write, iclass 13, count 0 2006.161.07:31:12.89#ibcon#wrote, iclass 13, count 0 2006.161.07:31:12.89#ibcon#about to read 3, iclass 13, count 0 2006.161.07:31:12.91#ibcon#read 3, iclass 13, count 0 2006.161.07:31:12.91#ibcon#about to read 4, iclass 13, count 0 2006.161.07:31:12.91#ibcon#read 4, iclass 13, count 0 2006.161.07:31:12.91#ibcon#about to read 5, iclass 13, count 0 2006.161.07:31:12.91#ibcon#read 5, iclass 13, count 0 2006.161.07:31:12.91#ibcon#about to read 6, iclass 13, count 0 2006.161.07:31:12.91#ibcon#read 6, iclass 13, count 0 2006.161.07:31:12.91#ibcon#end of sib2, iclass 13, count 0 2006.161.07:31:12.91#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:31:12.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:31:12.91#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:31:12.91#ibcon#*before write, iclass 13, count 0 2006.161.07:31:12.91#ibcon#enter sib2, iclass 13, count 0 2006.161.07:31:12.91#ibcon#flushed, iclass 13, count 0 2006.161.07:31:12.91#ibcon#about to write, iclass 13, count 0 2006.161.07:31:12.91#ibcon#wrote, iclass 13, count 0 2006.161.07:31:12.91#ibcon#about to read 3, iclass 13, count 0 2006.161.07:31:12.95#ibcon#read 3, iclass 13, count 0 2006.161.07:31:12.95#ibcon#about to read 4, iclass 13, count 0 2006.161.07:31:12.95#ibcon#read 4, iclass 13, count 0 2006.161.07:31:12.95#ibcon#about to read 5, iclass 13, count 0 2006.161.07:31:12.95#ibcon#read 5, iclass 13, count 0 2006.161.07:31:12.95#ibcon#about to read 6, iclass 13, count 0 2006.161.07:31:12.95#ibcon#read 6, iclass 13, count 0 2006.161.07:31:12.95#ibcon#end of sib2, iclass 13, count 0 2006.161.07:31:12.95#ibcon#*after write, iclass 13, count 0 2006.161.07:31:12.95#ibcon#*before return 0, iclass 13, count 0 2006.161.07:31:12.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:12.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:31:12.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:31:12.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:31:12.95$vc4f8/vb=6,4 2006.161.07:31:12.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:31:12.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:31:12.95#ibcon#ireg 11 cls_cnt 2 2006.161.07:31:12.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:13.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:13.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:13.01#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:31:13.01#ibcon#first serial, iclass 15, count 2 2006.161.07:31:13.01#ibcon#enter sib2, iclass 15, count 2 2006.161.07:31:13.01#ibcon#flushed, iclass 15, count 2 2006.161.07:31:13.01#ibcon#about to write, iclass 15, count 2 2006.161.07:31:13.01#ibcon#wrote, iclass 15, count 2 2006.161.07:31:13.01#ibcon#about to read 3, iclass 15, count 2 2006.161.07:31:13.03#ibcon#read 3, iclass 15, count 2 2006.161.07:31:13.03#ibcon#about to read 4, iclass 15, count 2 2006.161.07:31:13.03#ibcon#read 4, iclass 15, count 2 2006.161.07:31:13.03#ibcon#about to read 5, iclass 15, count 2 2006.161.07:31:13.03#ibcon#read 5, iclass 15, count 2 2006.161.07:31:13.03#ibcon#about to read 6, iclass 15, count 2 2006.161.07:31:13.03#ibcon#read 6, iclass 15, count 2 2006.161.07:31:13.03#ibcon#end of sib2, iclass 15, count 2 2006.161.07:31:13.03#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:31:13.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:31:13.03#ibcon#[27=AT06-04\r\n] 2006.161.07:31:13.03#ibcon#*before write, iclass 15, count 2 2006.161.07:31:13.03#ibcon#enter sib2, iclass 15, count 2 2006.161.07:31:13.03#ibcon#flushed, iclass 15, count 2 2006.161.07:31:13.03#ibcon#about to write, iclass 15, count 2 2006.161.07:31:13.03#ibcon#wrote, iclass 15, count 2 2006.161.07:31:13.03#ibcon#about to read 3, iclass 15, count 2 2006.161.07:31:13.06#ibcon#read 3, iclass 15, count 2 2006.161.07:31:13.06#ibcon#about to read 4, iclass 15, count 2 2006.161.07:31:13.06#ibcon#read 4, iclass 15, count 2 2006.161.07:31:13.06#ibcon#about to read 5, iclass 15, count 2 2006.161.07:31:13.06#ibcon#read 5, iclass 15, count 2 2006.161.07:31:13.06#ibcon#about to read 6, iclass 15, count 2 2006.161.07:31:13.06#ibcon#read 6, iclass 15, count 2 2006.161.07:31:13.06#ibcon#end of sib2, iclass 15, count 2 2006.161.07:31:13.06#ibcon#*after write, iclass 15, count 2 2006.161.07:31:13.06#ibcon#*before return 0, iclass 15, count 2 2006.161.07:31:13.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:13.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:31:13.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:31:13.06#ibcon#ireg 7 cls_cnt 0 2006.161.07:31:13.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:13.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:13.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:13.18#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:31:13.18#ibcon#first serial, iclass 15, count 0 2006.161.07:31:13.18#ibcon#enter sib2, iclass 15, count 0 2006.161.07:31:13.18#ibcon#flushed, iclass 15, count 0 2006.161.07:31:13.18#ibcon#about to write, iclass 15, count 0 2006.161.07:31:13.18#ibcon#wrote, iclass 15, count 0 2006.161.07:31:13.18#ibcon#about to read 3, iclass 15, count 0 2006.161.07:31:13.20#ibcon#read 3, iclass 15, count 0 2006.161.07:31:13.20#ibcon#about to read 4, iclass 15, count 0 2006.161.07:31:13.20#ibcon#read 4, iclass 15, count 0 2006.161.07:31:13.20#ibcon#about to read 5, iclass 15, count 0 2006.161.07:31:13.20#ibcon#read 5, iclass 15, count 0 2006.161.07:31:13.20#ibcon#about to read 6, iclass 15, count 0 2006.161.07:31:13.20#ibcon#read 6, iclass 15, count 0 2006.161.07:31:13.20#ibcon#end of sib2, iclass 15, count 0 2006.161.07:31:13.20#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:31:13.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:31:13.20#ibcon#[27=USB\r\n] 2006.161.07:31:13.20#ibcon#*before write, iclass 15, count 0 2006.161.07:31:13.20#ibcon#enter sib2, iclass 15, count 0 2006.161.07:31:13.20#ibcon#flushed, iclass 15, count 0 2006.161.07:31:13.20#ibcon#about to write, iclass 15, count 0 2006.161.07:31:13.20#ibcon#wrote, iclass 15, count 0 2006.161.07:31:13.20#ibcon#about to read 3, iclass 15, count 0 2006.161.07:31:13.23#ibcon#read 3, iclass 15, count 0 2006.161.07:31:13.23#ibcon#about to read 4, iclass 15, count 0 2006.161.07:31:13.23#ibcon#read 4, iclass 15, count 0 2006.161.07:31:13.23#ibcon#about to read 5, iclass 15, count 0 2006.161.07:31:13.23#ibcon#read 5, iclass 15, count 0 2006.161.07:31:13.23#ibcon#about to read 6, iclass 15, count 0 2006.161.07:31:13.23#ibcon#read 6, iclass 15, count 0 2006.161.07:31:13.23#ibcon#end of sib2, iclass 15, count 0 2006.161.07:31:13.23#ibcon#*after write, iclass 15, count 0 2006.161.07:31:13.23#ibcon#*before return 0, iclass 15, count 0 2006.161.07:31:13.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:13.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:31:13.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:31:13.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:31:13.23$vc4f8/vabw=wide 2006.161.07:31:13.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:31:13.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:31:13.23#ibcon#ireg 8 cls_cnt 0 2006.161.07:31:13.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:13.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:13.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:13.23#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:31:13.23#ibcon#first serial, iclass 17, count 0 2006.161.07:31:13.23#ibcon#enter sib2, iclass 17, count 0 2006.161.07:31:13.23#ibcon#flushed, iclass 17, count 0 2006.161.07:31:13.23#ibcon#about to write, iclass 17, count 0 2006.161.07:31:13.23#ibcon#wrote, iclass 17, count 0 2006.161.07:31:13.23#ibcon#about to read 3, iclass 17, count 0 2006.161.07:31:13.25#ibcon#read 3, iclass 17, count 0 2006.161.07:31:13.25#ibcon#about to read 4, iclass 17, count 0 2006.161.07:31:13.25#ibcon#read 4, iclass 17, count 0 2006.161.07:31:13.25#ibcon#about to read 5, iclass 17, count 0 2006.161.07:31:13.25#ibcon#read 5, iclass 17, count 0 2006.161.07:31:13.25#ibcon#about to read 6, iclass 17, count 0 2006.161.07:31:13.25#ibcon#read 6, iclass 17, count 0 2006.161.07:31:13.25#ibcon#end of sib2, iclass 17, count 0 2006.161.07:31:13.25#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:31:13.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:31:13.25#ibcon#[25=BW32\r\n] 2006.161.07:31:13.25#ibcon#*before write, iclass 17, count 0 2006.161.07:31:13.25#ibcon#enter sib2, iclass 17, count 0 2006.161.07:31:13.25#ibcon#flushed, iclass 17, count 0 2006.161.07:31:13.25#ibcon#about to write, iclass 17, count 0 2006.161.07:31:13.25#ibcon#wrote, iclass 17, count 0 2006.161.07:31:13.25#ibcon#about to read 3, iclass 17, count 0 2006.161.07:31:13.28#ibcon#read 3, iclass 17, count 0 2006.161.07:31:13.28#ibcon#about to read 4, iclass 17, count 0 2006.161.07:31:13.28#ibcon#read 4, iclass 17, count 0 2006.161.07:31:13.28#ibcon#about to read 5, iclass 17, count 0 2006.161.07:31:13.28#ibcon#read 5, iclass 17, count 0 2006.161.07:31:13.28#ibcon#about to read 6, iclass 17, count 0 2006.161.07:31:13.28#ibcon#read 6, iclass 17, count 0 2006.161.07:31:13.28#ibcon#end of sib2, iclass 17, count 0 2006.161.07:31:13.28#ibcon#*after write, iclass 17, count 0 2006.161.07:31:13.28#ibcon#*before return 0, iclass 17, count 0 2006.161.07:31:13.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:13.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:31:13.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:31:13.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:31:13.28$vc4f8/vbbw=wide 2006.161.07:31:13.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:31:13.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:31:13.28#ibcon#ireg 8 cls_cnt 0 2006.161.07:31:13.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:31:13.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:31:13.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:31:13.35#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:31:13.35#ibcon#first serial, iclass 19, count 0 2006.161.07:31:13.35#ibcon#enter sib2, iclass 19, count 0 2006.161.07:31:13.35#ibcon#flushed, iclass 19, count 0 2006.161.07:31:13.35#ibcon#about to write, iclass 19, count 0 2006.161.07:31:13.35#ibcon#wrote, iclass 19, count 0 2006.161.07:31:13.35#ibcon#about to read 3, iclass 19, count 0 2006.161.07:31:13.37#ibcon#read 3, iclass 19, count 0 2006.161.07:31:13.37#ibcon#about to read 4, iclass 19, count 0 2006.161.07:31:13.37#ibcon#read 4, iclass 19, count 0 2006.161.07:31:13.37#ibcon#about to read 5, iclass 19, count 0 2006.161.07:31:13.37#ibcon#read 5, iclass 19, count 0 2006.161.07:31:13.37#ibcon#about to read 6, iclass 19, count 0 2006.161.07:31:13.37#ibcon#read 6, iclass 19, count 0 2006.161.07:31:13.37#ibcon#end of sib2, iclass 19, count 0 2006.161.07:31:13.37#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:31:13.37#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:31:13.37#ibcon#[27=BW32\r\n] 2006.161.07:31:13.37#ibcon#*before write, iclass 19, count 0 2006.161.07:31:13.37#ibcon#enter sib2, iclass 19, count 0 2006.161.07:31:13.37#ibcon#flushed, iclass 19, count 0 2006.161.07:31:13.37#ibcon#about to write, iclass 19, count 0 2006.161.07:31:13.37#ibcon#wrote, iclass 19, count 0 2006.161.07:31:13.37#ibcon#about to read 3, iclass 19, count 0 2006.161.07:31:13.40#ibcon#read 3, iclass 19, count 0 2006.161.07:31:13.40#ibcon#about to read 4, iclass 19, count 0 2006.161.07:31:13.40#ibcon#read 4, iclass 19, count 0 2006.161.07:31:13.40#ibcon#about to read 5, iclass 19, count 0 2006.161.07:31:13.40#ibcon#read 5, iclass 19, count 0 2006.161.07:31:13.40#ibcon#about to read 6, iclass 19, count 0 2006.161.07:31:13.40#ibcon#read 6, iclass 19, count 0 2006.161.07:31:13.40#ibcon#end of sib2, iclass 19, count 0 2006.161.07:31:13.40#ibcon#*after write, iclass 19, count 0 2006.161.07:31:13.40#ibcon#*before return 0, iclass 19, count 0 2006.161.07:31:13.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:31:13.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:31:13.40#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:31:13.40#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:31:13.40$4f8m12a/ifd4f 2006.161.07:31:13.40$ifd4f/lo= 2006.161.07:31:13.40$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:31:13.40$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:31:13.40$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:31:13.40$ifd4f/patch= 2006.161.07:31:13.40$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:31:13.40$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:31:13.41$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:31:13.41$4f8m12a/"form=m,16.000,1:2 2006.161.07:31:13.41$4f8m12a/"tpicd 2006.161.07:31:13.41$4f8m12a/echo=off 2006.161.07:31:13.41$4f8m12a/xlog=off 2006.161.07:31:13.41:!2006.161.07:33:20 2006.161.07:31:47.13#trakl#Source acquired 2006.161.07:31:48.13#flagr#flagr/antenna,acquired 2006.161.07:33:20.01:preob 2006.161.07:33:21.14/onsource/TRACKING 2006.161.07:33:21.14:!2006.161.07:33:30 2006.161.07:33:30.00:data_valid=on 2006.161.07:33:30.00:midob 2006.161.07:33:30.14/onsource/TRACKING 2006.161.07:33:30.14/wx/24.19,1001.9,84 2006.161.07:33:30.20/cable/+6.4962E-03 2006.161.07:33:31.30/va/01,08,usb,yes,28,30 2006.161.07:33:31.30/va/02,07,usb,yes,28,30 2006.161.07:33:31.30/va/03,06,usb,yes,30,30 2006.161.07:33:31.30/va/04,07,usb,yes,29,31 2006.161.07:33:31.30/va/05,07,usb,yes,29,30 2006.161.07:33:31.30/va/06,06,usb,yes,28,28 2006.161.07:33:31.30/va/07,06,usb,yes,28,28 2006.161.07:33:31.30/va/08,07,usb,yes,27,26 2006.161.07:33:31.53/valo/01,532.99,yes,locked 2006.161.07:33:31.53/valo/02,572.99,yes,locked 2006.161.07:33:31.53/valo/03,672.99,yes,locked 2006.161.07:33:31.53/valo/04,832.99,yes,locked 2006.161.07:33:31.53/valo/05,652.99,yes,locked 2006.161.07:33:31.53/valo/06,772.99,yes,locked 2006.161.07:33:31.53/valo/07,832.99,yes,locked 2006.161.07:33:31.53/valo/08,852.99,yes,locked 2006.161.07:33:32.62/vb/01,04,usb,yes,28,27 2006.161.07:33:32.62/vb/02,04,usb,yes,30,32 2006.161.07:33:32.62/vb/03,04,usb,yes,27,30 2006.161.07:33:32.62/vb/04,04,usb,yes,28,28 2006.161.07:33:32.62/vb/05,04,usb,yes,26,30 2006.161.07:33:32.62/vb/06,04,usb,yes,27,30 2006.161.07:33:32.62/vb/07,04,usb,yes,29,29 2006.161.07:33:32.62/vb/08,04,usb,yes,27,30 2006.161.07:33:32.85/vblo/01,632.99,yes,locked 2006.161.07:33:32.85/vblo/02,640.99,yes,locked 2006.161.07:33:32.85/vblo/03,656.99,yes,locked 2006.161.07:33:32.85/vblo/04,712.99,yes,locked 2006.161.07:33:32.85/vblo/05,744.99,yes,locked 2006.161.07:33:32.85/vblo/06,752.99,yes,locked 2006.161.07:33:32.85/vblo/07,734.99,yes,locked 2006.161.07:33:32.85/vblo/08,744.99,yes,locked 2006.161.07:33:33.00/vabw/8 2006.161.07:33:33.15/vbbw/8 2006.161.07:33:33.24/xfe/off,on,14.2 2006.161.07:33:33.62/ifatt/23,28,28,28 2006.161.07:33:34.07/fmout-gps/S +4.47E-07 2006.161.07:33:34.11:!2006.161.07:34:30 2006.161.07:34:30.01:data_valid=off 2006.161.07:34:30.02:postob 2006.161.07:34:30.21/cable/+6.4992E-03 2006.161.07:34:30.22/wx/24.17,1002.0,84 2006.161.07:34:31.07/fmout-gps/S +4.48E-07 2006.161.07:34:31.08:scan_name=161-0735,k06161,100 2006.161.07:34:31.08:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.161.07:34:32.14#flagr#flagr/antenna,new-source 2006.161.07:34:32.15:checkk5 2006.161.07:34:32.63/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:34:33.11/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:34:33.70/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:34:34.32/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:34:34.69/chk_obsdata//k5ts1/T1610733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:34:35.12/chk_obsdata//k5ts2/T1610733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:34:35.55/chk_obsdata//k5ts3/T1610733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:34:35.99/chk_obsdata//k5ts4/T1610733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:34:36.90/k5log//k5ts1_log_newline 2006.161.07:34:37.69/k5log//k5ts2_log_newline 2006.161.07:34:38.48/k5log//k5ts3_log_newline 2006.161.07:34:39.60/k5log//k5ts4_log_newline 2006.161.07:34:39.62/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:34:39.62:4f8m12a=1 2006.161.07:34:39.62$4f8m12a/echo=on 2006.161.07:34:39.62$4f8m12a/pcalon 2006.161.07:34:39.62$pcalon/"no phase cal control is implemented here 2006.161.07:34:39.62$4f8m12a/"tpicd=stop 2006.161.07:34:39.62$4f8m12a/vc4f8 2006.161.07:34:39.62$vc4f8/valo=1,532.99 2006.161.07:34:39.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:34:39.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:34:39.63#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:39.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:39.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:39.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:39.63#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:34:39.63#ibcon#first serial, iclass 30, count 0 2006.161.07:34:39.63#ibcon#enter sib2, iclass 30, count 0 2006.161.07:34:39.63#ibcon#flushed, iclass 30, count 0 2006.161.07:34:39.63#ibcon#about to write, iclass 30, count 0 2006.161.07:34:39.63#ibcon#wrote, iclass 30, count 0 2006.161.07:34:39.63#ibcon#about to read 3, iclass 30, count 0 2006.161.07:34:39.67#ibcon#read 3, iclass 30, count 0 2006.161.07:34:39.67#ibcon#about to read 4, iclass 30, count 0 2006.161.07:34:39.67#ibcon#read 4, iclass 30, count 0 2006.161.07:34:39.67#ibcon#about to read 5, iclass 30, count 0 2006.161.07:34:39.67#ibcon#read 5, iclass 30, count 0 2006.161.07:34:39.67#ibcon#about to read 6, iclass 30, count 0 2006.161.07:34:39.67#ibcon#read 6, iclass 30, count 0 2006.161.07:34:39.67#ibcon#end of sib2, iclass 30, count 0 2006.161.07:34:39.67#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:34:39.67#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:34:39.67#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:34:39.67#ibcon#*before write, iclass 30, count 0 2006.161.07:34:39.67#ibcon#enter sib2, iclass 30, count 0 2006.161.07:34:39.67#ibcon#flushed, iclass 30, count 0 2006.161.07:34:39.67#ibcon#about to write, iclass 30, count 0 2006.161.07:34:39.67#ibcon#wrote, iclass 30, count 0 2006.161.07:34:39.67#ibcon#about to read 3, iclass 30, count 0 2006.161.07:34:39.71#ibcon#read 3, iclass 30, count 0 2006.161.07:34:39.71#ibcon#about to read 4, iclass 30, count 0 2006.161.07:34:39.71#ibcon#read 4, iclass 30, count 0 2006.161.07:34:39.71#ibcon#about to read 5, iclass 30, count 0 2006.161.07:34:39.71#ibcon#read 5, iclass 30, count 0 2006.161.07:34:39.71#ibcon#about to read 6, iclass 30, count 0 2006.161.07:34:39.71#ibcon#read 6, iclass 30, count 0 2006.161.07:34:39.71#ibcon#end of sib2, iclass 30, count 0 2006.161.07:34:39.71#ibcon#*after write, iclass 30, count 0 2006.161.07:34:39.71#ibcon#*before return 0, iclass 30, count 0 2006.161.07:34:39.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:39.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:39.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:34:39.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:34:39.71$vc4f8/va=1,8 2006.161.07:34:39.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:34:39.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:34:39.71#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:39.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:39.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:39.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:39.71#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:34:39.71#ibcon#first serial, iclass 32, count 2 2006.161.07:34:39.71#ibcon#enter sib2, iclass 32, count 2 2006.161.07:34:39.71#ibcon#flushed, iclass 32, count 2 2006.161.07:34:39.71#ibcon#about to write, iclass 32, count 2 2006.161.07:34:39.71#ibcon#wrote, iclass 32, count 2 2006.161.07:34:39.71#ibcon#about to read 3, iclass 32, count 2 2006.161.07:34:39.74#ibcon#read 3, iclass 32, count 2 2006.161.07:34:39.74#ibcon#about to read 4, iclass 32, count 2 2006.161.07:34:39.74#ibcon#read 4, iclass 32, count 2 2006.161.07:34:39.74#ibcon#about to read 5, iclass 32, count 2 2006.161.07:34:39.74#ibcon#read 5, iclass 32, count 2 2006.161.07:34:39.74#ibcon#about to read 6, iclass 32, count 2 2006.161.07:34:39.74#ibcon#read 6, iclass 32, count 2 2006.161.07:34:39.74#ibcon#end of sib2, iclass 32, count 2 2006.161.07:34:39.74#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:34:39.74#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:34:39.74#ibcon#[25=AT01-08\r\n] 2006.161.07:34:39.74#ibcon#*before write, iclass 32, count 2 2006.161.07:34:39.74#ibcon#enter sib2, iclass 32, count 2 2006.161.07:34:39.74#ibcon#flushed, iclass 32, count 2 2006.161.07:34:39.74#ibcon#about to write, iclass 32, count 2 2006.161.07:34:39.74#ibcon#wrote, iclass 32, count 2 2006.161.07:34:39.74#ibcon#about to read 3, iclass 32, count 2 2006.161.07:34:39.76#ibcon#read 3, iclass 32, count 2 2006.161.07:34:39.76#ibcon#about to read 4, iclass 32, count 2 2006.161.07:34:39.76#ibcon#read 4, iclass 32, count 2 2006.161.07:34:39.77#ibcon#about to read 5, iclass 32, count 2 2006.161.07:34:39.77#ibcon#read 5, iclass 32, count 2 2006.161.07:34:39.77#ibcon#about to read 6, iclass 32, count 2 2006.161.07:34:39.77#ibcon#read 6, iclass 32, count 2 2006.161.07:34:39.77#ibcon#end of sib2, iclass 32, count 2 2006.161.07:34:39.77#ibcon#*after write, iclass 32, count 2 2006.161.07:34:39.77#ibcon#*before return 0, iclass 32, count 2 2006.161.07:34:39.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:39.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:39.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:34:39.77#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:39.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:39.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:39.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:39.88#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:34:39.88#ibcon#first serial, iclass 32, count 0 2006.161.07:34:39.88#ibcon#enter sib2, iclass 32, count 0 2006.161.07:34:39.88#ibcon#flushed, iclass 32, count 0 2006.161.07:34:39.88#ibcon#about to write, iclass 32, count 0 2006.161.07:34:39.88#ibcon#wrote, iclass 32, count 0 2006.161.07:34:39.88#ibcon#about to read 3, iclass 32, count 0 2006.161.07:34:39.90#ibcon#read 3, iclass 32, count 0 2006.161.07:34:39.90#ibcon#about to read 4, iclass 32, count 0 2006.161.07:34:39.90#ibcon#read 4, iclass 32, count 0 2006.161.07:34:39.90#ibcon#about to read 5, iclass 32, count 0 2006.161.07:34:39.90#ibcon#read 5, iclass 32, count 0 2006.161.07:34:39.90#ibcon#about to read 6, iclass 32, count 0 2006.161.07:34:39.90#ibcon#read 6, iclass 32, count 0 2006.161.07:34:39.90#ibcon#end of sib2, iclass 32, count 0 2006.161.07:34:39.90#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:34:39.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:34:39.90#ibcon#[25=USB\r\n] 2006.161.07:34:39.90#ibcon#*before write, iclass 32, count 0 2006.161.07:34:39.90#ibcon#enter sib2, iclass 32, count 0 2006.161.07:34:39.90#ibcon#flushed, iclass 32, count 0 2006.161.07:34:39.90#ibcon#about to write, iclass 32, count 0 2006.161.07:34:39.90#ibcon#wrote, iclass 32, count 0 2006.161.07:34:39.90#ibcon#about to read 3, iclass 32, count 0 2006.161.07:34:39.93#ibcon#read 3, iclass 32, count 0 2006.161.07:34:39.93#ibcon#about to read 4, iclass 32, count 0 2006.161.07:34:39.93#ibcon#read 4, iclass 32, count 0 2006.161.07:34:39.93#ibcon#about to read 5, iclass 32, count 0 2006.161.07:34:39.93#ibcon#read 5, iclass 32, count 0 2006.161.07:34:39.93#ibcon#about to read 6, iclass 32, count 0 2006.161.07:34:39.93#ibcon#read 6, iclass 32, count 0 2006.161.07:34:39.93#ibcon#end of sib2, iclass 32, count 0 2006.161.07:34:39.93#ibcon#*after write, iclass 32, count 0 2006.161.07:34:39.93#ibcon#*before return 0, iclass 32, count 0 2006.161.07:34:39.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:39.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:39.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:34:39.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:34:39.93$vc4f8/valo=2,572.99 2006.161.07:34:39.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.07:34:39.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.07:34:39.93#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:39.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:39.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:39.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:39.93#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:34:39.93#ibcon#first serial, iclass 34, count 0 2006.161.07:34:39.93#ibcon#enter sib2, iclass 34, count 0 2006.161.07:34:39.93#ibcon#flushed, iclass 34, count 0 2006.161.07:34:39.93#ibcon#about to write, iclass 34, count 0 2006.161.07:34:39.93#ibcon#wrote, iclass 34, count 0 2006.161.07:34:39.93#ibcon#about to read 3, iclass 34, count 0 2006.161.07:34:39.96#ibcon#read 3, iclass 34, count 0 2006.161.07:34:39.96#ibcon#about to read 4, iclass 34, count 0 2006.161.07:34:39.96#ibcon#read 4, iclass 34, count 0 2006.161.07:34:39.96#ibcon#about to read 5, iclass 34, count 0 2006.161.07:34:39.96#ibcon#read 5, iclass 34, count 0 2006.161.07:34:39.96#ibcon#about to read 6, iclass 34, count 0 2006.161.07:34:39.96#ibcon#read 6, iclass 34, count 0 2006.161.07:34:39.96#ibcon#end of sib2, iclass 34, count 0 2006.161.07:34:39.96#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:34:39.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:34:39.96#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:34:39.96#ibcon#*before write, iclass 34, count 0 2006.161.07:34:39.96#ibcon#enter sib2, iclass 34, count 0 2006.161.07:34:39.96#ibcon#flushed, iclass 34, count 0 2006.161.07:34:39.96#ibcon#about to write, iclass 34, count 0 2006.161.07:34:39.96#ibcon#wrote, iclass 34, count 0 2006.161.07:34:39.96#ibcon#about to read 3, iclass 34, count 0 2006.161.07:34:40.00#ibcon#read 3, iclass 34, count 0 2006.161.07:34:40.00#ibcon#about to read 4, iclass 34, count 0 2006.161.07:34:40.00#ibcon#read 4, iclass 34, count 0 2006.161.07:34:40.00#ibcon#about to read 5, iclass 34, count 0 2006.161.07:34:40.00#ibcon#read 5, iclass 34, count 0 2006.161.07:34:40.00#ibcon#about to read 6, iclass 34, count 0 2006.161.07:34:40.00#ibcon#read 6, iclass 34, count 0 2006.161.07:34:40.00#ibcon#end of sib2, iclass 34, count 0 2006.161.07:34:40.00#ibcon#*after write, iclass 34, count 0 2006.161.07:34:40.00#ibcon#*before return 0, iclass 34, count 0 2006.161.07:34:40.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:40.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:40.00#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:34:40.00#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:34:40.00$vc4f8/va=2,7 2006.161.07:34:40.00#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.07:34:40.00#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.07:34:40.00#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:40.00#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:40.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:40.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:40.05#ibcon#enter wrdev, iclass 36, count 2 2006.161.07:34:40.05#ibcon#first serial, iclass 36, count 2 2006.161.07:34:40.05#ibcon#enter sib2, iclass 36, count 2 2006.161.07:34:40.05#ibcon#flushed, iclass 36, count 2 2006.161.07:34:40.05#ibcon#about to write, iclass 36, count 2 2006.161.07:34:40.05#ibcon#wrote, iclass 36, count 2 2006.161.07:34:40.05#ibcon#about to read 3, iclass 36, count 2 2006.161.07:34:40.08#ibcon#read 3, iclass 36, count 2 2006.161.07:34:40.08#ibcon#about to read 4, iclass 36, count 2 2006.161.07:34:40.08#ibcon#read 4, iclass 36, count 2 2006.161.07:34:40.08#ibcon#about to read 5, iclass 36, count 2 2006.161.07:34:40.08#ibcon#read 5, iclass 36, count 2 2006.161.07:34:40.08#ibcon#about to read 6, iclass 36, count 2 2006.161.07:34:40.08#ibcon#read 6, iclass 36, count 2 2006.161.07:34:40.08#ibcon#end of sib2, iclass 36, count 2 2006.161.07:34:40.08#ibcon#*mode == 0, iclass 36, count 2 2006.161.07:34:40.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.07:34:40.08#ibcon#[25=AT02-07\r\n] 2006.161.07:34:40.08#ibcon#*before write, iclass 36, count 2 2006.161.07:34:40.08#ibcon#enter sib2, iclass 36, count 2 2006.161.07:34:40.08#ibcon#flushed, iclass 36, count 2 2006.161.07:34:40.08#ibcon#about to write, iclass 36, count 2 2006.161.07:34:40.08#ibcon#wrote, iclass 36, count 2 2006.161.07:34:40.08#ibcon#about to read 3, iclass 36, count 2 2006.161.07:34:40.11#ibcon#read 3, iclass 36, count 2 2006.161.07:34:40.11#ibcon#about to read 4, iclass 36, count 2 2006.161.07:34:40.11#ibcon#read 4, iclass 36, count 2 2006.161.07:34:40.11#ibcon#about to read 5, iclass 36, count 2 2006.161.07:34:40.11#ibcon#read 5, iclass 36, count 2 2006.161.07:34:40.11#ibcon#about to read 6, iclass 36, count 2 2006.161.07:34:40.11#ibcon#read 6, iclass 36, count 2 2006.161.07:34:40.11#ibcon#end of sib2, iclass 36, count 2 2006.161.07:34:40.11#ibcon#*after write, iclass 36, count 2 2006.161.07:34:40.11#ibcon#*before return 0, iclass 36, count 2 2006.161.07:34:40.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:40.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:40.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.07:34:40.11#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:40.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:40.12#abcon#<5=/04 2.8 5.2 24.17 841002.0\r\n> 2006.161.07:34:40.14#abcon#{5=INTERFACE CLEAR} 2006.161.07:34:40.20#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:34:40.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:40.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:40.23#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:34:40.23#ibcon#first serial, iclass 36, count 0 2006.161.07:34:40.23#ibcon#enter sib2, iclass 36, count 0 2006.161.07:34:40.23#ibcon#flushed, iclass 36, count 0 2006.161.07:34:40.23#ibcon#about to write, iclass 36, count 0 2006.161.07:34:40.23#ibcon#wrote, iclass 36, count 0 2006.161.07:34:40.23#ibcon#about to read 3, iclass 36, count 0 2006.161.07:34:40.25#ibcon#read 3, iclass 36, count 0 2006.161.07:34:40.25#ibcon#about to read 4, iclass 36, count 0 2006.161.07:34:40.25#ibcon#read 4, iclass 36, count 0 2006.161.07:34:40.25#ibcon#about to read 5, iclass 36, count 0 2006.161.07:34:40.25#ibcon#read 5, iclass 36, count 0 2006.161.07:34:40.25#ibcon#about to read 6, iclass 36, count 0 2006.161.07:34:40.25#ibcon#read 6, iclass 36, count 0 2006.161.07:34:40.25#ibcon#end of sib2, iclass 36, count 0 2006.161.07:34:40.25#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:34:40.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:34:40.25#ibcon#[25=USB\r\n] 2006.161.07:34:40.25#ibcon#*before write, iclass 36, count 0 2006.161.07:34:40.25#ibcon#enter sib2, iclass 36, count 0 2006.161.07:34:40.25#ibcon#flushed, iclass 36, count 0 2006.161.07:34:40.25#ibcon#about to write, iclass 36, count 0 2006.161.07:34:40.25#ibcon#wrote, iclass 36, count 0 2006.161.07:34:40.25#ibcon#about to read 3, iclass 36, count 0 2006.161.07:34:40.28#ibcon#read 3, iclass 36, count 0 2006.161.07:34:40.28#ibcon#about to read 4, iclass 36, count 0 2006.161.07:34:40.28#ibcon#read 4, iclass 36, count 0 2006.161.07:34:40.28#ibcon#about to read 5, iclass 36, count 0 2006.161.07:34:40.28#ibcon#read 5, iclass 36, count 0 2006.161.07:34:40.28#ibcon#about to read 6, iclass 36, count 0 2006.161.07:34:40.28#ibcon#read 6, iclass 36, count 0 2006.161.07:34:40.28#ibcon#end of sib2, iclass 36, count 0 2006.161.07:34:40.28#ibcon#*after write, iclass 36, count 0 2006.161.07:34:40.28#ibcon#*before return 0, iclass 36, count 0 2006.161.07:34:40.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:40.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:40.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:34:40.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:34:40.28$vc4f8/valo=3,672.99 2006.161.07:34:40.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.07:34:40.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.07:34:40.28#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:40.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:40.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:40.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:40.28#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:34:40.28#ibcon#first serial, iclass 4, count 0 2006.161.07:34:40.28#ibcon#enter sib2, iclass 4, count 0 2006.161.07:34:40.28#ibcon#flushed, iclass 4, count 0 2006.161.07:34:40.28#ibcon#about to write, iclass 4, count 0 2006.161.07:34:40.28#ibcon#wrote, iclass 4, count 0 2006.161.07:34:40.28#ibcon#about to read 3, iclass 4, count 0 2006.161.07:34:40.30#ibcon#read 3, iclass 4, count 0 2006.161.07:34:40.30#ibcon#about to read 4, iclass 4, count 0 2006.161.07:34:40.30#ibcon#read 4, iclass 4, count 0 2006.161.07:34:40.30#ibcon#about to read 5, iclass 4, count 0 2006.161.07:34:40.30#ibcon#read 5, iclass 4, count 0 2006.161.07:34:40.30#ibcon#about to read 6, iclass 4, count 0 2006.161.07:34:40.30#ibcon#read 6, iclass 4, count 0 2006.161.07:34:40.30#ibcon#end of sib2, iclass 4, count 0 2006.161.07:34:40.30#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:34:40.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:34:40.30#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:34:40.30#ibcon#*before write, iclass 4, count 0 2006.161.07:34:40.30#ibcon#enter sib2, iclass 4, count 0 2006.161.07:34:40.30#ibcon#flushed, iclass 4, count 0 2006.161.07:34:40.30#ibcon#about to write, iclass 4, count 0 2006.161.07:34:40.30#ibcon#wrote, iclass 4, count 0 2006.161.07:34:40.30#ibcon#about to read 3, iclass 4, count 0 2006.161.07:34:40.34#ibcon#read 3, iclass 4, count 0 2006.161.07:34:40.34#ibcon#about to read 4, iclass 4, count 0 2006.161.07:34:40.34#ibcon#read 4, iclass 4, count 0 2006.161.07:34:40.34#ibcon#about to read 5, iclass 4, count 0 2006.161.07:34:40.34#ibcon#read 5, iclass 4, count 0 2006.161.07:34:40.34#ibcon#about to read 6, iclass 4, count 0 2006.161.07:34:40.34#ibcon#read 6, iclass 4, count 0 2006.161.07:34:40.34#ibcon#end of sib2, iclass 4, count 0 2006.161.07:34:40.34#ibcon#*after write, iclass 4, count 0 2006.161.07:34:40.34#ibcon#*before return 0, iclass 4, count 0 2006.161.07:34:40.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:40.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:40.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:34:40.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:34:40.34$vc4f8/va=3,6 2006.161.07:34:40.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.07:34:40.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.07:34:40.34#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:40.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:40.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:40.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:40.40#ibcon#enter wrdev, iclass 6, count 2 2006.161.07:34:40.40#ibcon#first serial, iclass 6, count 2 2006.161.07:34:40.40#ibcon#enter sib2, iclass 6, count 2 2006.161.07:34:40.40#ibcon#flushed, iclass 6, count 2 2006.161.07:34:40.40#ibcon#about to write, iclass 6, count 2 2006.161.07:34:40.40#ibcon#wrote, iclass 6, count 2 2006.161.07:34:40.40#ibcon#about to read 3, iclass 6, count 2 2006.161.07:34:40.42#ibcon#read 3, iclass 6, count 2 2006.161.07:34:40.42#ibcon#about to read 4, iclass 6, count 2 2006.161.07:34:40.42#ibcon#read 4, iclass 6, count 2 2006.161.07:34:40.42#ibcon#about to read 5, iclass 6, count 2 2006.161.07:34:40.42#ibcon#read 5, iclass 6, count 2 2006.161.07:34:40.42#ibcon#about to read 6, iclass 6, count 2 2006.161.07:34:40.42#ibcon#read 6, iclass 6, count 2 2006.161.07:34:40.42#ibcon#end of sib2, iclass 6, count 2 2006.161.07:34:40.42#ibcon#*mode == 0, iclass 6, count 2 2006.161.07:34:40.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.07:34:40.42#ibcon#[25=AT03-06\r\n] 2006.161.07:34:40.42#ibcon#*before write, iclass 6, count 2 2006.161.07:34:40.42#ibcon#enter sib2, iclass 6, count 2 2006.161.07:34:40.42#ibcon#flushed, iclass 6, count 2 2006.161.07:34:40.42#ibcon#about to write, iclass 6, count 2 2006.161.07:34:40.42#ibcon#wrote, iclass 6, count 2 2006.161.07:34:40.42#ibcon#about to read 3, iclass 6, count 2 2006.161.07:34:40.45#ibcon#read 3, iclass 6, count 2 2006.161.07:34:40.45#ibcon#about to read 4, iclass 6, count 2 2006.161.07:34:40.45#ibcon#read 4, iclass 6, count 2 2006.161.07:34:40.45#ibcon#about to read 5, iclass 6, count 2 2006.161.07:34:40.45#ibcon#read 5, iclass 6, count 2 2006.161.07:34:40.45#ibcon#about to read 6, iclass 6, count 2 2006.161.07:34:40.45#ibcon#read 6, iclass 6, count 2 2006.161.07:34:40.45#ibcon#end of sib2, iclass 6, count 2 2006.161.07:34:40.45#ibcon#*after write, iclass 6, count 2 2006.161.07:34:40.45#ibcon#*before return 0, iclass 6, count 2 2006.161.07:34:40.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:40.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:40.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.07:34:40.45#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:40.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:40.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:40.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:40.57#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:34:40.57#ibcon#first serial, iclass 6, count 0 2006.161.07:34:40.57#ibcon#enter sib2, iclass 6, count 0 2006.161.07:34:40.57#ibcon#flushed, iclass 6, count 0 2006.161.07:34:40.57#ibcon#about to write, iclass 6, count 0 2006.161.07:34:40.57#ibcon#wrote, iclass 6, count 0 2006.161.07:34:40.57#ibcon#about to read 3, iclass 6, count 0 2006.161.07:34:40.59#ibcon#read 3, iclass 6, count 0 2006.161.07:34:40.59#ibcon#about to read 4, iclass 6, count 0 2006.161.07:34:40.59#ibcon#read 4, iclass 6, count 0 2006.161.07:34:40.59#ibcon#about to read 5, iclass 6, count 0 2006.161.07:34:40.59#ibcon#read 5, iclass 6, count 0 2006.161.07:34:40.59#ibcon#about to read 6, iclass 6, count 0 2006.161.07:34:40.59#ibcon#read 6, iclass 6, count 0 2006.161.07:34:40.59#ibcon#end of sib2, iclass 6, count 0 2006.161.07:34:40.59#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:34:40.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:34:40.59#ibcon#[25=USB\r\n] 2006.161.07:34:40.59#ibcon#*before write, iclass 6, count 0 2006.161.07:34:40.59#ibcon#enter sib2, iclass 6, count 0 2006.161.07:34:40.59#ibcon#flushed, iclass 6, count 0 2006.161.07:34:40.59#ibcon#about to write, iclass 6, count 0 2006.161.07:34:40.59#ibcon#wrote, iclass 6, count 0 2006.161.07:34:40.59#ibcon#about to read 3, iclass 6, count 0 2006.161.07:34:40.62#ibcon#read 3, iclass 6, count 0 2006.161.07:34:40.62#ibcon#about to read 4, iclass 6, count 0 2006.161.07:34:40.62#ibcon#read 4, iclass 6, count 0 2006.161.07:34:40.62#ibcon#about to read 5, iclass 6, count 0 2006.161.07:34:40.62#ibcon#read 5, iclass 6, count 0 2006.161.07:34:40.62#ibcon#about to read 6, iclass 6, count 0 2006.161.07:34:40.62#ibcon#read 6, iclass 6, count 0 2006.161.07:34:40.62#ibcon#end of sib2, iclass 6, count 0 2006.161.07:34:40.62#ibcon#*after write, iclass 6, count 0 2006.161.07:34:40.62#ibcon#*before return 0, iclass 6, count 0 2006.161.07:34:40.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:40.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:40.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:34:40.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:34:40.62$vc4f8/valo=4,832.99 2006.161.07:34:40.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:34:40.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:34:40.62#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:40.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:40.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:40.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:40.62#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:34:40.62#ibcon#first serial, iclass 10, count 0 2006.161.07:34:40.62#ibcon#enter sib2, iclass 10, count 0 2006.161.07:34:40.62#ibcon#flushed, iclass 10, count 0 2006.161.07:34:40.62#ibcon#about to write, iclass 10, count 0 2006.161.07:34:40.62#ibcon#wrote, iclass 10, count 0 2006.161.07:34:40.62#ibcon#about to read 3, iclass 10, count 0 2006.161.07:34:40.64#ibcon#read 3, iclass 10, count 0 2006.161.07:34:40.64#ibcon#about to read 4, iclass 10, count 0 2006.161.07:34:40.64#ibcon#read 4, iclass 10, count 0 2006.161.07:34:40.64#ibcon#about to read 5, iclass 10, count 0 2006.161.07:34:40.64#ibcon#read 5, iclass 10, count 0 2006.161.07:34:40.64#ibcon#about to read 6, iclass 10, count 0 2006.161.07:34:40.64#ibcon#read 6, iclass 10, count 0 2006.161.07:34:40.64#ibcon#end of sib2, iclass 10, count 0 2006.161.07:34:40.64#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:34:40.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:34:40.64#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:34:40.64#ibcon#*before write, iclass 10, count 0 2006.161.07:34:40.64#ibcon#enter sib2, iclass 10, count 0 2006.161.07:34:40.64#ibcon#flushed, iclass 10, count 0 2006.161.07:34:40.64#ibcon#about to write, iclass 10, count 0 2006.161.07:34:40.64#ibcon#wrote, iclass 10, count 0 2006.161.07:34:40.64#ibcon#about to read 3, iclass 10, count 0 2006.161.07:34:40.68#ibcon#read 3, iclass 10, count 0 2006.161.07:34:40.68#ibcon#about to read 4, iclass 10, count 0 2006.161.07:34:40.68#ibcon#read 4, iclass 10, count 0 2006.161.07:34:40.68#ibcon#about to read 5, iclass 10, count 0 2006.161.07:34:40.68#ibcon#read 5, iclass 10, count 0 2006.161.07:34:40.68#ibcon#about to read 6, iclass 10, count 0 2006.161.07:34:40.68#ibcon#read 6, iclass 10, count 0 2006.161.07:34:40.68#ibcon#end of sib2, iclass 10, count 0 2006.161.07:34:40.68#ibcon#*after write, iclass 10, count 0 2006.161.07:34:40.68#ibcon#*before return 0, iclass 10, count 0 2006.161.07:34:40.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:40.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:40.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:34:40.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:34:40.68$vc4f8/va=4,7 2006.161.07:34:40.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.07:34:40.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.07:34:40.68#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:40.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:40.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:40.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:40.74#ibcon#enter wrdev, iclass 12, count 2 2006.161.07:34:40.74#ibcon#first serial, iclass 12, count 2 2006.161.07:34:40.74#ibcon#enter sib2, iclass 12, count 2 2006.161.07:34:40.74#ibcon#flushed, iclass 12, count 2 2006.161.07:34:40.74#ibcon#about to write, iclass 12, count 2 2006.161.07:34:40.74#ibcon#wrote, iclass 12, count 2 2006.161.07:34:40.74#ibcon#about to read 3, iclass 12, count 2 2006.161.07:34:40.76#ibcon#read 3, iclass 12, count 2 2006.161.07:34:40.76#ibcon#about to read 4, iclass 12, count 2 2006.161.07:34:40.76#ibcon#read 4, iclass 12, count 2 2006.161.07:34:40.76#ibcon#about to read 5, iclass 12, count 2 2006.161.07:34:40.76#ibcon#read 5, iclass 12, count 2 2006.161.07:34:40.76#ibcon#about to read 6, iclass 12, count 2 2006.161.07:34:40.76#ibcon#read 6, iclass 12, count 2 2006.161.07:34:40.76#ibcon#end of sib2, iclass 12, count 2 2006.161.07:34:40.76#ibcon#*mode == 0, iclass 12, count 2 2006.161.07:34:40.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.07:34:40.76#ibcon#[25=AT04-07\r\n] 2006.161.07:34:40.76#ibcon#*before write, iclass 12, count 2 2006.161.07:34:40.76#ibcon#enter sib2, iclass 12, count 2 2006.161.07:34:40.76#ibcon#flushed, iclass 12, count 2 2006.161.07:34:40.76#ibcon#about to write, iclass 12, count 2 2006.161.07:34:40.76#ibcon#wrote, iclass 12, count 2 2006.161.07:34:40.76#ibcon#about to read 3, iclass 12, count 2 2006.161.07:34:40.79#ibcon#read 3, iclass 12, count 2 2006.161.07:34:40.79#ibcon#about to read 4, iclass 12, count 2 2006.161.07:34:40.79#ibcon#read 4, iclass 12, count 2 2006.161.07:34:40.79#ibcon#about to read 5, iclass 12, count 2 2006.161.07:34:40.79#ibcon#read 5, iclass 12, count 2 2006.161.07:34:40.79#ibcon#about to read 6, iclass 12, count 2 2006.161.07:34:40.79#ibcon#read 6, iclass 12, count 2 2006.161.07:34:40.79#ibcon#end of sib2, iclass 12, count 2 2006.161.07:34:40.79#ibcon#*after write, iclass 12, count 2 2006.161.07:34:40.79#ibcon#*before return 0, iclass 12, count 2 2006.161.07:34:40.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:40.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:40.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.07:34:40.79#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:40.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:40.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:40.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:40.91#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:34:40.91#ibcon#first serial, iclass 12, count 0 2006.161.07:34:40.91#ibcon#enter sib2, iclass 12, count 0 2006.161.07:34:40.91#ibcon#flushed, iclass 12, count 0 2006.161.07:34:40.91#ibcon#about to write, iclass 12, count 0 2006.161.07:34:40.91#ibcon#wrote, iclass 12, count 0 2006.161.07:34:40.91#ibcon#about to read 3, iclass 12, count 0 2006.161.07:34:40.93#ibcon#read 3, iclass 12, count 0 2006.161.07:34:40.93#ibcon#about to read 4, iclass 12, count 0 2006.161.07:34:40.93#ibcon#read 4, iclass 12, count 0 2006.161.07:34:40.93#ibcon#about to read 5, iclass 12, count 0 2006.161.07:34:40.93#ibcon#read 5, iclass 12, count 0 2006.161.07:34:40.93#ibcon#about to read 6, iclass 12, count 0 2006.161.07:34:40.93#ibcon#read 6, iclass 12, count 0 2006.161.07:34:40.93#ibcon#end of sib2, iclass 12, count 0 2006.161.07:34:40.93#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:34:40.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:34:40.93#ibcon#[25=USB\r\n] 2006.161.07:34:40.93#ibcon#*before write, iclass 12, count 0 2006.161.07:34:40.93#ibcon#enter sib2, iclass 12, count 0 2006.161.07:34:40.93#ibcon#flushed, iclass 12, count 0 2006.161.07:34:40.93#ibcon#about to write, iclass 12, count 0 2006.161.07:34:40.93#ibcon#wrote, iclass 12, count 0 2006.161.07:34:40.93#ibcon#about to read 3, iclass 12, count 0 2006.161.07:34:40.96#ibcon#read 3, iclass 12, count 0 2006.161.07:34:40.96#ibcon#about to read 4, iclass 12, count 0 2006.161.07:34:40.96#ibcon#read 4, iclass 12, count 0 2006.161.07:34:40.96#ibcon#about to read 5, iclass 12, count 0 2006.161.07:34:40.96#ibcon#read 5, iclass 12, count 0 2006.161.07:34:40.96#ibcon#about to read 6, iclass 12, count 0 2006.161.07:34:40.96#ibcon#read 6, iclass 12, count 0 2006.161.07:34:40.96#ibcon#end of sib2, iclass 12, count 0 2006.161.07:34:40.96#ibcon#*after write, iclass 12, count 0 2006.161.07:34:40.96#ibcon#*before return 0, iclass 12, count 0 2006.161.07:34:40.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:40.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:40.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:34:40.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:34:40.96$vc4f8/valo=5,652.99 2006.161.07:34:40.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.07:34:40.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.07:34:40.96#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:40.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:40.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:40.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:40.96#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:34:40.96#ibcon#first serial, iclass 14, count 0 2006.161.07:34:40.96#ibcon#enter sib2, iclass 14, count 0 2006.161.07:34:40.96#ibcon#flushed, iclass 14, count 0 2006.161.07:34:40.96#ibcon#about to write, iclass 14, count 0 2006.161.07:34:40.96#ibcon#wrote, iclass 14, count 0 2006.161.07:34:40.96#ibcon#about to read 3, iclass 14, count 0 2006.161.07:34:40.98#ibcon#read 3, iclass 14, count 0 2006.161.07:34:40.98#ibcon#about to read 4, iclass 14, count 0 2006.161.07:34:40.98#ibcon#read 4, iclass 14, count 0 2006.161.07:34:40.98#ibcon#about to read 5, iclass 14, count 0 2006.161.07:34:40.98#ibcon#read 5, iclass 14, count 0 2006.161.07:34:40.98#ibcon#about to read 6, iclass 14, count 0 2006.161.07:34:40.98#ibcon#read 6, iclass 14, count 0 2006.161.07:34:40.98#ibcon#end of sib2, iclass 14, count 0 2006.161.07:34:40.98#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:34:40.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:34:40.98#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:34:40.98#ibcon#*before write, iclass 14, count 0 2006.161.07:34:40.98#ibcon#enter sib2, iclass 14, count 0 2006.161.07:34:40.98#ibcon#flushed, iclass 14, count 0 2006.161.07:34:40.98#ibcon#about to write, iclass 14, count 0 2006.161.07:34:40.98#ibcon#wrote, iclass 14, count 0 2006.161.07:34:40.98#ibcon#about to read 3, iclass 14, count 0 2006.161.07:34:41.02#ibcon#read 3, iclass 14, count 0 2006.161.07:34:41.02#ibcon#about to read 4, iclass 14, count 0 2006.161.07:34:41.02#ibcon#read 4, iclass 14, count 0 2006.161.07:34:41.02#ibcon#about to read 5, iclass 14, count 0 2006.161.07:34:41.02#ibcon#read 5, iclass 14, count 0 2006.161.07:34:41.02#ibcon#about to read 6, iclass 14, count 0 2006.161.07:34:41.02#ibcon#read 6, iclass 14, count 0 2006.161.07:34:41.02#ibcon#end of sib2, iclass 14, count 0 2006.161.07:34:41.02#ibcon#*after write, iclass 14, count 0 2006.161.07:34:41.02#ibcon#*before return 0, iclass 14, count 0 2006.161.07:34:41.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:41.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:41.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:34:41.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:34:41.02$vc4f8/va=5,7 2006.161.07:34:41.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.07:34:41.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.07:34:41.02#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:41.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:41.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:41.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:41.08#ibcon#enter wrdev, iclass 16, count 2 2006.161.07:34:41.08#ibcon#first serial, iclass 16, count 2 2006.161.07:34:41.08#ibcon#enter sib2, iclass 16, count 2 2006.161.07:34:41.08#ibcon#flushed, iclass 16, count 2 2006.161.07:34:41.08#ibcon#about to write, iclass 16, count 2 2006.161.07:34:41.08#ibcon#wrote, iclass 16, count 2 2006.161.07:34:41.08#ibcon#about to read 3, iclass 16, count 2 2006.161.07:34:41.10#ibcon#read 3, iclass 16, count 2 2006.161.07:34:41.10#ibcon#about to read 4, iclass 16, count 2 2006.161.07:34:41.10#ibcon#read 4, iclass 16, count 2 2006.161.07:34:41.10#ibcon#about to read 5, iclass 16, count 2 2006.161.07:34:41.10#ibcon#read 5, iclass 16, count 2 2006.161.07:34:41.10#ibcon#about to read 6, iclass 16, count 2 2006.161.07:34:41.10#ibcon#read 6, iclass 16, count 2 2006.161.07:34:41.10#ibcon#end of sib2, iclass 16, count 2 2006.161.07:34:41.10#ibcon#*mode == 0, iclass 16, count 2 2006.161.07:34:41.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.07:34:41.10#ibcon#[25=AT05-07\r\n] 2006.161.07:34:41.10#ibcon#*before write, iclass 16, count 2 2006.161.07:34:41.10#ibcon#enter sib2, iclass 16, count 2 2006.161.07:34:41.10#ibcon#flushed, iclass 16, count 2 2006.161.07:34:41.10#ibcon#about to write, iclass 16, count 2 2006.161.07:34:41.10#ibcon#wrote, iclass 16, count 2 2006.161.07:34:41.10#ibcon#about to read 3, iclass 16, count 2 2006.161.07:34:41.13#ibcon#read 3, iclass 16, count 2 2006.161.07:34:41.13#ibcon#about to read 4, iclass 16, count 2 2006.161.07:34:41.13#ibcon#read 4, iclass 16, count 2 2006.161.07:34:41.13#ibcon#about to read 5, iclass 16, count 2 2006.161.07:34:41.13#ibcon#read 5, iclass 16, count 2 2006.161.07:34:41.13#ibcon#about to read 6, iclass 16, count 2 2006.161.07:34:41.13#ibcon#read 6, iclass 16, count 2 2006.161.07:34:41.13#ibcon#end of sib2, iclass 16, count 2 2006.161.07:34:41.13#ibcon#*after write, iclass 16, count 2 2006.161.07:34:41.13#ibcon#*before return 0, iclass 16, count 2 2006.161.07:34:41.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:41.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:41.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.07:34:41.13#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:41.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:41.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:41.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:41.25#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:34:41.25#ibcon#first serial, iclass 16, count 0 2006.161.07:34:41.25#ibcon#enter sib2, iclass 16, count 0 2006.161.07:34:41.25#ibcon#flushed, iclass 16, count 0 2006.161.07:34:41.25#ibcon#about to write, iclass 16, count 0 2006.161.07:34:41.25#ibcon#wrote, iclass 16, count 0 2006.161.07:34:41.25#ibcon#about to read 3, iclass 16, count 0 2006.161.07:34:41.27#ibcon#read 3, iclass 16, count 0 2006.161.07:34:41.27#ibcon#about to read 4, iclass 16, count 0 2006.161.07:34:41.27#ibcon#read 4, iclass 16, count 0 2006.161.07:34:41.27#ibcon#about to read 5, iclass 16, count 0 2006.161.07:34:41.27#ibcon#read 5, iclass 16, count 0 2006.161.07:34:41.27#ibcon#about to read 6, iclass 16, count 0 2006.161.07:34:41.27#ibcon#read 6, iclass 16, count 0 2006.161.07:34:41.27#ibcon#end of sib2, iclass 16, count 0 2006.161.07:34:41.27#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:34:41.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:34:41.27#ibcon#[25=USB\r\n] 2006.161.07:34:41.27#ibcon#*before write, iclass 16, count 0 2006.161.07:34:41.27#ibcon#enter sib2, iclass 16, count 0 2006.161.07:34:41.27#ibcon#flushed, iclass 16, count 0 2006.161.07:34:41.27#ibcon#about to write, iclass 16, count 0 2006.161.07:34:41.27#ibcon#wrote, iclass 16, count 0 2006.161.07:34:41.27#ibcon#about to read 3, iclass 16, count 0 2006.161.07:34:41.30#ibcon#read 3, iclass 16, count 0 2006.161.07:34:41.30#ibcon#about to read 4, iclass 16, count 0 2006.161.07:34:41.30#ibcon#read 4, iclass 16, count 0 2006.161.07:34:41.30#ibcon#about to read 5, iclass 16, count 0 2006.161.07:34:41.30#ibcon#read 5, iclass 16, count 0 2006.161.07:34:41.30#ibcon#about to read 6, iclass 16, count 0 2006.161.07:34:41.30#ibcon#read 6, iclass 16, count 0 2006.161.07:34:41.30#ibcon#end of sib2, iclass 16, count 0 2006.161.07:34:41.30#ibcon#*after write, iclass 16, count 0 2006.161.07:34:41.30#ibcon#*before return 0, iclass 16, count 0 2006.161.07:34:41.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:41.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:41.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:34:41.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:34:41.30$vc4f8/valo=6,772.99 2006.161.07:34:41.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.07:34:41.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.07:34:41.30#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:41.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:41.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:41.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:41.30#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:34:41.30#ibcon#first serial, iclass 18, count 0 2006.161.07:34:41.30#ibcon#enter sib2, iclass 18, count 0 2006.161.07:34:41.30#ibcon#flushed, iclass 18, count 0 2006.161.07:34:41.30#ibcon#about to write, iclass 18, count 0 2006.161.07:34:41.30#ibcon#wrote, iclass 18, count 0 2006.161.07:34:41.30#ibcon#about to read 3, iclass 18, count 0 2006.161.07:34:41.32#ibcon#read 3, iclass 18, count 0 2006.161.07:34:41.32#ibcon#about to read 4, iclass 18, count 0 2006.161.07:34:41.32#ibcon#read 4, iclass 18, count 0 2006.161.07:34:41.32#ibcon#about to read 5, iclass 18, count 0 2006.161.07:34:41.32#ibcon#read 5, iclass 18, count 0 2006.161.07:34:41.32#ibcon#about to read 6, iclass 18, count 0 2006.161.07:34:41.32#ibcon#read 6, iclass 18, count 0 2006.161.07:34:41.32#ibcon#end of sib2, iclass 18, count 0 2006.161.07:34:41.32#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:34:41.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:34:41.32#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:34:41.32#ibcon#*before write, iclass 18, count 0 2006.161.07:34:41.32#ibcon#enter sib2, iclass 18, count 0 2006.161.07:34:41.32#ibcon#flushed, iclass 18, count 0 2006.161.07:34:41.32#ibcon#about to write, iclass 18, count 0 2006.161.07:34:41.32#ibcon#wrote, iclass 18, count 0 2006.161.07:34:41.32#ibcon#about to read 3, iclass 18, count 0 2006.161.07:34:41.36#ibcon#read 3, iclass 18, count 0 2006.161.07:34:41.36#ibcon#about to read 4, iclass 18, count 0 2006.161.07:34:41.36#ibcon#read 4, iclass 18, count 0 2006.161.07:34:41.36#ibcon#about to read 5, iclass 18, count 0 2006.161.07:34:41.36#ibcon#read 5, iclass 18, count 0 2006.161.07:34:41.36#ibcon#about to read 6, iclass 18, count 0 2006.161.07:34:41.36#ibcon#read 6, iclass 18, count 0 2006.161.07:34:41.36#ibcon#end of sib2, iclass 18, count 0 2006.161.07:34:41.36#ibcon#*after write, iclass 18, count 0 2006.161.07:34:41.36#ibcon#*before return 0, iclass 18, count 0 2006.161.07:34:41.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:41.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:41.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:34:41.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:34:41.36$vc4f8/va=6,6 2006.161.07:34:41.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.07:34:41.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.07:34:41.36#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:41.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:41.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:41.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:41.42#ibcon#enter wrdev, iclass 20, count 2 2006.161.07:34:41.42#ibcon#first serial, iclass 20, count 2 2006.161.07:34:41.42#ibcon#enter sib2, iclass 20, count 2 2006.161.07:34:41.42#ibcon#flushed, iclass 20, count 2 2006.161.07:34:41.42#ibcon#about to write, iclass 20, count 2 2006.161.07:34:41.42#ibcon#wrote, iclass 20, count 2 2006.161.07:34:41.42#ibcon#about to read 3, iclass 20, count 2 2006.161.07:34:41.44#ibcon#read 3, iclass 20, count 2 2006.161.07:34:41.44#ibcon#about to read 4, iclass 20, count 2 2006.161.07:34:41.44#ibcon#read 4, iclass 20, count 2 2006.161.07:34:41.44#ibcon#about to read 5, iclass 20, count 2 2006.161.07:34:41.44#ibcon#read 5, iclass 20, count 2 2006.161.07:34:41.44#ibcon#about to read 6, iclass 20, count 2 2006.161.07:34:41.44#ibcon#read 6, iclass 20, count 2 2006.161.07:34:41.44#ibcon#end of sib2, iclass 20, count 2 2006.161.07:34:41.44#ibcon#*mode == 0, iclass 20, count 2 2006.161.07:34:41.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.07:34:41.44#ibcon#[25=AT06-06\r\n] 2006.161.07:34:41.44#ibcon#*before write, iclass 20, count 2 2006.161.07:34:41.44#ibcon#enter sib2, iclass 20, count 2 2006.161.07:34:41.44#ibcon#flushed, iclass 20, count 2 2006.161.07:34:41.44#ibcon#about to write, iclass 20, count 2 2006.161.07:34:41.44#ibcon#wrote, iclass 20, count 2 2006.161.07:34:41.44#ibcon#about to read 3, iclass 20, count 2 2006.161.07:34:41.47#ibcon#read 3, iclass 20, count 2 2006.161.07:34:41.47#ibcon#about to read 4, iclass 20, count 2 2006.161.07:34:41.47#ibcon#read 4, iclass 20, count 2 2006.161.07:34:41.47#ibcon#about to read 5, iclass 20, count 2 2006.161.07:34:41.47#ibcon#read 5, iclass 20, count 2 2006.161.07:34:41.47#ibcon#about to read 6, iclass 20, count 2 2006.161.07:34:41.47#ibcon#read 6, iclass 20, count 2 2006.161.07:34:41.47#ibcon#end of sib2, iclass 20, count 2 2006.161.07:34:41.47#ibcon#*after write, iclass 20, count 2 2006.161.07:34:41.47#ibcon#*before return 0, iclass 20, count 2 2006.161.07:34:41.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:41.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:41.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.07:34:41.47#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:41.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:34:41.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:34:41.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:34:41.59#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:34:41.59#ibcon#first serial, iclass 20, count 0 2006.161.07:34:41.59#ibcon#enter sib2, iclass 20, count 0 2006.161.07:34:41.59#ibcon#flushed, iclass 20, count 0 2006.161.07:34:41.59#ibcon#about to write, iclass 20, count 0 2006.161.07:34:41.59#ibcon#wrote, iclass 20, count 0 2006.161.07:34:41.59#ibcon#about to read 3, iclass 20, count 0 2006.161.07:34:41.61#ibcon#read 3, iclass 20, count 0 2006.161.07:34:41.61#ibcon#about to read 4, iclass 20, count 0 2006.161.07:34:41.61#ibcon#read 4, iclass 20, count 0 2006.161.07:34:41.61#ibcon#about to read 5, iclass 20, count 0 2006.161.07:34:41.61#ibcon#read 5, iclass 20, count 0 2006.161.07:34:41.61#ibcon#about to read 6, iclass 20, count 0 2006.161.07:34:41.61#ibcon#read 6, iclass 20, count 0 2006.161.07:34:41.61#ibcon#end of sib2, iclass 20, count 0 2006.161.07:34:41.61#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:34:41.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:34:41.61#ibcon#[25=USB\r\n] 2006.161.07:34:41.61#ibcon#*before write, iclass 20, count 0 2006.161.07:34:41.61#ibcon#enter sib2, iclass 20, count 0 2006.161.07:34:41.61#ibcon#flushed, iclass 20, count 0 2006.161.07:34:41.61#ibcon#about to write, iclass 20, count 0 2006.161.07:34:41.61#ibcon#wrote, iclass 20, count 0 2006.161.07:34:41.61#ibcon#about to read 3, iclass 20, count 0 2006.161.07:34:41.64#ibcon#read 3, iclass 20, count 0 2006.161.07:34:41.64#ibcon#about to read 4, iclass 20, count 0 2006.161.07:34:41.64#ibcon#read 4, iclass 20, count 0 2006.161.07:34:41.64#ibcon#about to read 5, iclass 20, count 0 2006.161.07:34:41.64#ibcon#read 5, iclass 20, count 0 2006.161.07:34:41.64#ibcon#about to read 6, iclass 20, count 0 2006.161.07:34:41.64#ibcon#read 6, iclass 20, count 0 2006.161.07:34:41.64#ibcon#end of sib2, iclass 20, count 0 2006.161.07:34:41.64#ibcon#*after write, iclass 20, count 0 2006.161.07:34:41.64#ibcon#*before return 0, iclass 20, count 0 2006.161.07:34:41.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:34:41.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:34:41.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:34:41.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:34:41.64$vc4f8/valo=7,832.99 2006.161.07:34:41.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.07:34:41.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.07:34:41.64#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:41.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:34:41.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:34:41.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:34:41.64#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:34:41.64#ibcon#first serial, iclass 22, count 0 2006.161.07:34:41.64#ibcon#enter sib2, iclass 22, count 0 2006.161.07:34:41.64#ibcon#flushed, iclass 22, count 0 2006.161.07:34:41.64#ibcon#about to write, iclass 22, count 0 2006.161.07:34:41.64#ibcon#wrote, iclass 22, count 0 2006.161.07:34:41.64#ibcon#about to read 3, iclass 22, count 0 2006.161.07:34:41.66#ibcon#read 3, iclass 22, count 0 2006.161.07:34:41.66#ibcon#about to read 4, iclass 22, count 0 2006.161.07:34:41.66#ibcon#read 4, iclass 22, count 0 2006.161.07:34:41.66#ibcon#about to read 5, iclass 22, count 0 2006.161.07:34:41.66#ibcon#read 5, iclass 22, count 0 2006.161.07:34:41.66#ibcon#about to read 6, iclass 22, count 0 2006.161.07:34:41.66#ibcon#read 6, iclass 22, count 0 2006.161.07:34:41.66#ibcon#end of sib2, iclass 22, count 0 2006.161.07:34:41.66#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:34:41.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:34:41.66#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:34:41.66#ibcon#*before write, iclass 22, count 0 2006.161.07:34:41.66#ibcon#enter sib2, iclass 22, count 0 2006.161.07:34:41.66#ibcon#flushed, iclass 22, count 0 2006.161.07:34:41.66#ibcon#about to write, iclass 22, count 0 2006.161.07:34:41.66#ibcon#wrote, iclass 22, count 0 2006.161.07:34:41.66#ibcon#about to read 3, iclass 22, count 0 2006.161.07:34:41.70#ibcon#read 3, iclass 22, count 0 2006.161.07:34:41.70#ibcon#about to read 4, iclass 22, count 0 2006.161.07:34:41.70#ibcon#read 4, iclass 22, count 0 2006.161.07:34:41.70#ibcon#about to read 5, iclass 22, count 0 2006.161.07:34:41.70#ibcon#read 5, iclass 22, count 0 2006.161.07:34:41.70#ibcon#about to read 6, iclass 22, count 0 2006.161.07:34:41.70#ibcon#read 6, iclass 22, count 0 2006.161.07:34:41.70#ibcon#end of sib2, iclass 22, count 0 2006.161.07:34:41.70#ibcon#*after write, iclass 22, count 0 2006.161.07:34:41.70#ibcon#*before return 0, iclass 22, count 0 2006.161.07:34:41.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:34:41.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:34:41.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:34:41.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:34:41.70$vc4f8/va=7,6 2006.161.07:34:41.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.07:34:41.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.07:34:41.70#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:41.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:34:41.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:34:41.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:34:41.76#ibcon#enter wrdev, iclass 24, count 2 2006.161.07:34:41.76#ibcon#first serial, iclass 24, count 2 2006.161.07:34:41.76#ibcon#enter sib2, iclass 24, count 2 2006.161.07:34:41.76#ibcon#flushed, iclass 24, count 2 2006.161.07:34:41.76#ibcon#about to write, iclass 24, count 2 2006.161.07:34:41.76#ibcon#wrote, iclass 24, count 2 2006.161.07:34:41.76#ibcon#about to read 3, iclass 24, count 2 2006.161.07:34:41.78#ibcon#read 3, iclass 24, count 2 2006.161.07:34:41.78#ibcon#about to read 4, iclass 24, count 2 2006.161.07:34:41.78#ibcon#read 4, iclass 24, count 2 2006.161.07:34:41.78#ibcon#about to read 5, iclass 24, count 2 2006.161.07:34:41.78#ibcon#read 5, iclass 24, count 2 2006.161.07:34:41.78#ibcon#about to read 6, iclass 24, count 2 2006.161.07:34:41.78#ibcon#read 6, iclass 24, count 2 2006.161.07:34:41.78#ibcon#end of sib2, iclass 24, count 2 2006.161.07:34:41.78#ibcon#*mode == 0, iclass 24, count 2 2006.161.07:34:41.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.07:34:41.78#ibcon#[25=AT07-06\r\n] 2006.161.07:34:41.78#ibcon#*before write, iclass 24, count 2 2006.161.07:34:41.78#ibcon#enter sib2, iclass 24, count 2 2006.161.07:34:41.78#ibcon#flushed, iclass 24, count 2 2006.161.07:34:41.78#ibcon#about to write, iclass 24, count 2 2006.161.07:34:41.78#ibcon#wrote, iclass 24, count 2 2006.161.07:34:41.78#ibcon#about to read 3, iclass 24, count 2 2006.161.07:34:41.81#ibcon#read 3, iclass 24, count 2 2006.161.07:34:41.81#ibcon#about to read 4, iclass 24, count 2 2006.161.07:34:41.81#ibcon#read 4, iclass 24, count 2 2006.161.07:34:41.81#ibcon#about to read 5, iclass 24, count 2 2006.161.07:34:41.81#ibcon#read 5, iclass 24, count 2 2006.161.07:34:41.81#ibcon#about to read 6, iclass 24, count 2 2006.161.07:34:41.81#ibcon#read 6, iclass 24, count 2 2006.161.07:34:41.81#ibcon#end of sib2, iclass 24, count 2 2006.161.07:34:41.81#ibcon#*after write, iclass 24, count 2 2006.161.07:34:41.81#ibcon#*before return 0, iclass 24, count 2 2006.161.07:34:41.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:34:41.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:34:41.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.07:34:41.81#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:41.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:34:41.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:34:41.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:34:41.93#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:34:41.93#ibcon#first serial, iclass 24, count 0 2006.161.07:34:41.93#ibcon#enter sib2, iclass 24, count 0 2006.161.07:34:41.93#ibcon#flushed, iclass 24, count 0 2006.161.07:34:41.93#ibcon#about to write, iclass 24, count 0 2006.161.07:34:41.93#ibcon#wrote, iclass 24, count 0 2006.161.07:34:41.93#ibcon#about to read 3, iclass 24, count 0 2006.161.07:34:41.95#ibcon#read 3, iclass 24, count 0 2006.161.07:34:41.95#ibcon#about to read 4, iclass 24, count 0 2006.161.07:34:41.95#ibcon#read 4, iclass 24, count 0 2006.161.07:34:41.95#ibcon#about to read 5, iclass 24, count 0 2006.161.07:34:41.95#ibcon#read 5, iclass 24, count 0 2006.161.07:34:41.95#ibcon#about to read 6, iclass 24, count 0 2006.161.07:34:41.95#ibcon#read 6, iclass 24, count 0 2006.161.07:34:41.95#ibcon#end of sib2, iclass 24, count 0 2006.161.07:34:41.95#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:34:41.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:34:41.95#ibcon#[25=USB\r\n] 2006.161.07:34:41.95#ibcon#*before write, iclass 24, count 0 2006.161.07:34:41.95#ibcon#enter sib2, iclass 24, count 0 2006.161.07:34:41.95#ibcon#flushed, iclass 24, count 0 2006.161.07:34:41.95#ibcon#about to write, iclass 24, count 0 2006.161.07:34:41.95#ibcon#wrote, iclass 24, count 0 2006.161.07:34:41.95#ibcon#about to read 3, iclass 24, count 0 2006.161.07:34:41.98#ibcon#read 3, iclass 24, count 0 2006.161.07:34:41.98#ibcon#about to read 4, iclass 24, count 0 2006.161.07:34:41.98#ibcon#read 4, iclass 24, count 0 2006.161.07:34:41.98#ibcon#about to read 5, iclass 24, count 0 2006.161.07:34:41.98#ibcon#read 5, iclass 24, count 0 2006.161.07:34:41.98#ibcon#about to read 6, iclass 24, count 0 2006.161.07:34:41.98#ibcon#read 6, iclass 24, count 0 2006.161.07:34:41.98#ibcon#end of sib2, iclass 24, count 0 2006.161.07:34:41.98#ibcon#*after write, iclass 24, count 0 2006.161.07:34:41.98#ibcon#*before return 0, iclass 24, count 0 2006.161.07:34:41.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:34:41.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:34:41.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:34:41.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:34:41.98$vc4f8/valo=8,852.99 2006.161.07:34:41.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:34:41.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:34:41.98#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:41.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:34:41.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:34:41.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:34:41.98#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:34:41.98#ibcon#first serial, iclass 26, count 0 2006.161.07:34:41.98#ibcon#enter sib2, iclass 26, count 0 2006.161.07:34:41.98#ibcon#flushed, iclass 26, count 0 2006.161.07:34:41.98#ibcon#about to write, iclass 26, count 0 2006.161.07:34:41.98#ibcon#wrote, iclass 26, count 0 2006.161.07:34:41.98#ibcon#about to read 3, iclass 26, count 0 2006.161.07:34:42.01#ibcon#read 3, iclass 26, count 0 2006.161.07:34:42.01#ibcon#about to read 4, iclass 26, count 0 2006.161.07:34:42.01#ibcon#read 4, iclass 26, count 0 2006.161.07:34:42.01#ibcon#about to read 5, iclass 26, count 0 2006.161.07:34:42.01#ibcon#read 5, iclass 26, count 0 2006.161.07:34:42.01#ibcon#about to read 6, iclass 26, count 0 2006.161.07:34:42.01#ibcon#read 6, iclass 26, count 0 2006.161.07:34:42.01#ibcon#end of sib2, iclass 26, count 0 2006.161.07:34:42.01#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:34:42.01#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:34:42.01#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:34:42.01#ibcon#*before write, iclass 26, count 0 2006.161.07:34:42.01#ibcon#enter sib2, iclass 26, count 0 2006.161.07:34:42.01#ibcon#flushed, iclass 26, count 0 2006.161.07:34:42.01#ibcon#about to write, iclass 26, count 0 2006.161.07:34:42.01#ibcon#wrote, iclass 26, count 0 2006.161.07:34:42.01#ibcon#about to read 3, iclass 26, count 0 2006.161.07:34:42.05#ibcon#read 3, iclass 26, count 0 2006.161.07:34:42.05#ibcon#about to read 4, iclass 26, count 0 2006.161.07:34:42.05#ibcon#read 4, iclass 26, count 0 2006.161.07:34:42.05#ibcon#about to read 5, iclass 26, count 0 2006.161.07:34:42.05#ibcon#read 5, iclass 26, count 0 2006.161.07:34:42.05#ibcon#about to read 6, iclass 26, count 0 2006.161.07:34:42.05#ibcon#read 6, iclass 26, count 0 2006.161.07:34:42.05#ibcon#end of sib2, iclass 26, count 0 2006.161.07:34:42.05#ibcon#*after write, iclass 26, count 0 2006.161.07:34:42.05#ibcon#*before return 0, iclass 26, count 0 2006.161.07:34:42.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:34:42.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:34:42.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:34:42.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:34:42.05$vc4f8/va=8,7 2006.161.07:34:42.05#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.07:34:42.05#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.07:34:42.05#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:42.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:34:42.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:34:42.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:34:42.10#ibcon#enter wrdev, iclass 28, count 2 2006.161.07:34:42.10#ibcon#first serial, iclass 28, count 2 2006.161.07:34:42.10#ibcon#enter sib2, iclass 28, count 2 2006.161.07:34:42.10#ibcon#flushed, iclass 28, count 2 2006.161.07:34:42.10#ibcon#about to write, iclass 28, count 2 2006.161.07:34:42.10#ibcon#wrote, iclass 28, count 2 2006.161.07:34:42.10#ibcon#about to read 3, iclass 28, count 2 2006.161.07:34:42.12#ibcon#read 3, iclass 28, count 2 2006.161.07:34:42.12#ibcon#about to read 4, iclass 28, count 2 2006.161.07:34:42.12#ibcon#read 4, iclass 28, count 2 2006.161.07:34:42.12#ibcon#about to read 5, iclass 28, count 2 2006.161.07:34:42.12#ibcon#read 5, iclass 28, count 2 2006.161.07:34:42.12#ibcon#about to read 6, iclass 28, count 2 2006.161.07:34:42.12#ibcon#read 6, iclass 28, count 2 2006.161.07:34:42.12#ibcon#end of sib2, iclass 28, count 2 2006.161.07:34:42.12#ibcon#*mode == 0, iclass 28, count 2 2006.161.07:34:42.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.07:34:42.12#ibcon#[25=AT08-07\r\n] 2006.161.07:34:42.12#ibcon#*before write, iclass 28, count 2 2006.161.07:34:42.12#ibcon#enter sib2, iclass 28, count 2 2006.161.07:34:42.12#ibcon#flushed, iclass 28, count 2 2006.161.07:34:42.12#ibcon#about to write, iclass 28, count 2 2006.161.07:34:42.12#ibcon#wrote, iclass 28, count 2 2006.161.07:34:42.12#ibcon#about to read 3, iclass 28, count 2 2006.161.07:34:42.15#ibcon#read 3, iclass 28, count 2 2006.161.07:34:42.15#ibcon#about to read 4, iclass 28, count 2 2006.161.07:34:42.15#ibcon#read 4, iclass 28, count 2 2006.161.07:34:42.15#ibcon#about to read 5, iclass 28, count 2 2006.161.07:34:42.15#ibcon#read 5, iclass 28, count 2 2006.161.07:34:42.15#ibcon#about to read 6, iclass 28, count 2 2006.161.07:34:42.15#ibcon#read 6, iclass 28, count 2 2006.161.07:34:42.15#ibcon#end of sib2, iclass 28, count 2 2006.161.07:34:42.15#ibcon#*after write, iclass 28, count 2 2006.161.07:34:42.15#ibcon#*before return 0, iclass 28, count 2 2006.161.07:34:42.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:34:42.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:34:42.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.07:34:42.15#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:42.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:34:42.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:34:42.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:34:42.27#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:34:42.27#ibcon#first serial, iclass 28, count 0 2006.161.07:34:42.27#ibcon#enter sib2, iclass 28, count 0 2006.161.07:34:42.27#ibcon#flushed, iclass 28, count 0 2006.161.07:34:42.27#ibcon#about to write, iclass 28, count 0 2006.161.07:34:42.27#ibcon#wrote, iclass 28, count 0 2006.161.07:34:42.27#ibcon#about to read 3, iclass 28, count 0 2006.161.07:34:42.29#ibcon#read 3, iclass 28, count 0 2006.161.07:34:42.29#ibcon#about to read 4, iclass 28, count 0 2006.161.07:34:42.29#ibcon#read 4, iclass 28, count 0 2006.161.07:34:42.29#ibcon#about to read 5, iclass 28, count 0 2006.161.07:34:42.29#ibcon#read 5, iclass 28, count 0 2006.161.07:34:42.29#ibcon#about to read 6, iclass 28, count 0 2006.161.07:34:42.29#ibcon#read 6, iclass 28, count 0 2006.161.07:34:42.29#ibcon#end of sib2, iclass 28, count 0 2006.161.07:34:42.29#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:34:42.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:34:42.29#ibcon#[25=USB\r\n] 2006.161.07:34:42.29#ibcon#*before write, iclass 28, count 0 2006.161.07:34:42.29#ibcon#enter sib2, iclass 28, count 0 2006.161.07:34:42.29#ibcon#flushed, iclass 28, count 0 2006.161.07:34:42.29#ibcon#about to write, iclass 28, count 0 2006.161.07:34:42.29#ibcon#wrote, iclass 28, count 0 2006.161.07:34:42.29#ibcon#about to read 3, iclass 28, count 0 2006.161.07:34:42.32#ibcon#read 3, iclass 28, count 0 2006.161.07:34:42.32#ibcon#about to read 4, iclass 28, count 0 2006.161.07:34:42.32#ibcon#read 4, iclass 28, count 0 2006.161.07:34:42.32#ibcon#about to read 5, iclass 28, count 0 2006.161.07:34:42.32#ibcon#read 5, iclass 28, count 0 2006.161.07:34:42.32#ibcon#about to read 6, iclass 28, count 0 2006.161.07:34:42.32#ibcon#read 6, iclass 28, count 0 2006.161.07:34:42.32#ibcon#end of sib2, iclass 28, count 0 2006.161.07:34:42.32#ibcon#*after write, iclass 28, count 0 2006.161.07:34:42.32#ibcon#*before return 0, iclass 28, count 0 2006.161.07:34:42.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:34:42.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:34:42.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:34:42.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:34:42.32$vc4f8/vblo=1,632.99 2006.161.07:34:42.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:34:42.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:34:42.32#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:42.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:42.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:42.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:42.32#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:34:42.32#ibcon#first serial, iclass 30, count 0 2006.161.07:34:42.32#ibcon#enter sib2, iclass 30, count 0 2006.161.07:34:42.32#ibcon#flushed, iclass 30, count 0 2006.161.07:34:42.32#ibcon#about to write, iclass 30, count 0 2006.161.07:34:42.32#ibcon#wrote, iclass 30, count 0 2006.161.07:34:42.32#ibcon#about to read 3, iclass 30, count 0 2006.161.07:34:42.34#ibcon#read 3, iclass 30, count 0 2006.161.07:34:42.34#ibcon#about to read 4, iclass 30, count 0 2006.161.07:34:42.34#ibcon#read 4, iclass 30, count 0 2006.161.07:34:42.34#ibcon#about to read 5, iclass 30, count 0 2006.161.07:34:42.34#ibcon#read 5, iclass 30, count 0 2006.161.07:34:42.34#ibcon#about to read 6, iclass 30, count 0 2006.161.07:34:42.34#ibcon#read 6, iclass 30, count 0 2006.161.07:34:42.34#ibcon#end of sib2, iclass 30, count 0 2006.161.07:34:42.34#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:34:42.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:34:42.34#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:34:42.34#ibcon#*before write, iclass 30, count 0 2006.161.07:34:42.34#ibcon#enter sib2, iclass 30, count 0 2006.161.07:34:42.34#ibcon#flushed, iclass 30, count 0 2006.161.07:34:42.34#ibcon#about to write, iclass 30, count 0 2006.161.07:34:42.34#ibcon#wrote, iclass 30, count 0 2006.161.07:34:42.34#ibcon#about to read 3, iclass 30, count 0 2006.161.07:34:42.38#ibcon#read 3, iclass 30, count 0 2006.161.07:34:42.38#ibcon#about to read 4, iclass 30, count 0 2006.161.07:34:42.38#ibcon#read 4, iclass 30, count 0 2006.161.07:34:42.38#ibcon#about to read 5, iclass 30, count 0 2006.161.07:34:42.38#ibcon#read 5, iclass 30, count 0 2006.161.07:34:42.38#ibcon#about to read 6, iclass 30, count 0 2006.161.07:34:42.38#ibcon#read 6, iclass 30, count 0 2006.161.07:34:42.38#ibcon#end of sib2, iclass 30, count 0 2006.161.07:34:42.38#ibcon#*after write, iclass 30, count 0 2006.161.07:34:42.38#ibcon#*before return 0, iclass 30, count 0 2006.161.07:34:42.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:42.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:34:42.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:34:42.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:34:42.38$vc4f8/vb=1,4 2006.161.07:34:42.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:34:42.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:34:42.38#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:42.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:42.38#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:42.38#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:42.38#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:34:42.38#ibcon#first serial, iclass 32, count 2 2006.161.07:34:42.38#ibcon#enter sib2, iclass 32, count 2 2006.161.07:34:42.38#ibcon#flushed, iclass 32, count 2 2006.161.07:34:42.38#ibcon#about to write, iclass 32, count 2 2006.161.07:34:42.38#ibcon#wrote, iclass 32, count 2 2006.161.07:34:42.38#ibcon#about to read 3, iclass 32, count 2 2006.161.07:34:42.40#ibcon#read 3, iclass 32, count 2 2006.161.07:34:42.40#ibcon#about to read 4, iclass 32, count 2 2006.161.07:34:42.40#ibcon#read 4, iclass 32, count 2 2006.161.07:34:42.40#ibcon#about to read 5, iclass 32, count 2 2006.161.07:34:42.40#ibcon#read 5, iclass 32, count 2 2006.161.07:34:42.40#ibcon#about to read 6, iclass 32, count 2 2006.161.07:34:42.40#ibcon#read 6, iclass 32, count 2 2006.161.07:34:42.40#ibcon#end of sib2, iclass 32, count 2 2006.161.07:34:42.40#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:34:42.40#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:34:42.40#ibcon#[27=AT01-04\r\n] 2006.161.07:34:42.40#ibcon#*before write, iclass 32, count 2 2006.161.07:34:42.40#ibcon#enter sib2, iclass 32, count 2 2006.161.07:34:42.40#ibcon#flushed, iclass 32, count 2 2006.161.07:34:42.40#ibcon#about to write, iclass 32, count 2 2006.161.07:34:42.40#ibcon#wrote, iclass 32, count 2 2006.161.07:34:42.40#ibcon#about to read 3, iclass 32, count 2 2006.161.07:34:42.43#ibcon#read 3, iclass 32, count 2 2006.161.07:34:42.43#ibcon#about to read 4, iclass 32, count 2 2006.161.07:34:42.43#ibcon#read 4, iclass 32, count 2 2006.161.07:34:42.43#ibcon#about to read 5, iclass 32, count 2 2006.161.07:34:42.43#ibcon#read 5, iclass 32, count 2 2006.161.07:34:42.43#ibcon#about to read 6, iclass 32, count 2 2006.161.07:34:42.43#ibcon#read 6, iclass 32, count 2 2006.161.07:34:42.43#ibcon#end of sib2, iclass 32, count 2 2006.161.07:34:42.43#ibcon#*after write, iclass 32, count 2 2006.161.07:34:42.43#ibcon#*before return 0, iclass 32, count 2 2006.161.07:34:42.43#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:42.43#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:34:42.43#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:34:42.43#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:42.43#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:42.55#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:42.55#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:42.55#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:34:42.55#ibcon#first serial, iclass 32, count 0 2006.161.07:34:42.55#ibcon#enter sib2, iclass 32, count 0 2006.161.07:34:42.55#ibcon#flushed, iclass 32, count 0 2006.161.07:34:42.55#ibcon#about to write, iclass 32, count 0 2006.161.07:34:42.55#ibcon#wrote, iclass 32, count 0 2006.161.07:34:42.55#ibcon#about to read 3, iclass 32, count 0 2006.161.07:34:42.57#ibcon#read 3, iclass 32, count 0 2006.161.07:34:42.57#ibcon#about to read 4, iclass 32, count 0 2006.161.07:34:42.57#ibcon#read 4, iclass 32, count 0 2006.161.07:34:42.57#ibcon#about to read 5, iclass 32, count 0 2006.161.07:34:42.57#ibcon#read 5, iclass 32, count 0 2006.161.07:34:42.57#ibcon#about to read 6, iclass 32, count 0 2006.161.07:34:42.57#ibcon#read 6, iclass 32, count 0 2006.161.07:34:42.57#ibcon#end of sib2, iclass 32, count 0 2006.161.07:34:42.57#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:34:42.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:34:42.57#ibcon#[27=USB\r\n] 2006.161.07:34:42.57#ibcon#*before write, iclass 32, count 0 2006.161.07:34:42.57#ibcon#enter sib2, iclass 32, count 0 2006.161.07:34:42.57#ibcon#flushed, iclass 32, count 0 2006.161.07:34:42.57#ibcon#about to write, iclass 32, count 0 2006.161.07:34:42.57#ibcon#wrote, iclass 32, count 0 2006.161.07:34:42.57#ibcon#about to read 3, iclass 32, count 0 2006.161.07:34:42.60#ibcon#read 3, iclass 32, count 0 2006.161.07:34:42.60#ibcon#about to read 4, iclass 32, count 0 2006.161.07:34:42.60#ibcon#read 4, iclass 32, count 0 2006.161.07:34:42.60#ibcon#about to read 5, iclass 32, count 0 2006.161.07:34:42.60#ibcon#read 5, iclass 32, count 0 2006.161.07:34:42.60#ibcon#about to read 6, iclass 32, count 0 2006.161.07:34:42.60#ibcon#read 6, iclass 32, count 0 2006.161.07:34:42.60#ibcon#end of sib2, iclass 32, count 0 2006.161.07:34:42.60#ibcon#*after write, iclass 32, count 0 2006.161.07:34:42.60#ibcon#*before return 0, iclass 32, count 0 2006.161.07:34:42.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:42.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:34:42.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:34:42.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:34:42.60$vc4f8/vblo=2,640.99 2006.161.07:34:42.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.07:34:42.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.07:34:42.60#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:42.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:42.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:42.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:42.60#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:34:42.60#ibcon#first serial, iclass 34, count 0 2006.161.07:34:42.60#ibcon#enter sib2, iclass 34, count 0 2006.161.07:34:42.60#ibcon#flushed, iclass 34, count 0 2006.161.07:34:42.60#ibcon#about to write, iclass 34, count 0 2006.161.07:34:42.60#ibcon#wrote, iclass 34, count 0 2006.161.07:34:42.60#ibcon#about to read 3, iclass 34, count 0 2006.161.07:34:42.62#ibcon#read 3, iclass 34, count 0 2006.161.07:34:42.62#ibcon#about to read 4, iclass 34, count 0 2006.161.07:34:42.62#ibcon#read 4, iclass 34, count 0 2006.161.07:34:42.62#ibcon#about to read 5, iclass 34, count 0 2006.161.07:34:42.62#ibcon#read 5, iclass 34, count 0 2006.161.07:34:42.62#ibcon#about to read 6, iclass 34, count 0 2006.161.07:34:42.62#ibcon#read 6, iclass 34, count 0 2006.161.07:34:42.62#ibcon#end of sib2, iclass 34, count 0 2006.161.07:34:42.62#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:34:42.62#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:34:42.62#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:34:42.62#ibcon#*before write, iclass 34, count 0 2006.161.07:34:42.62#ibcon#enter sib2, iclass 34, count 0 2006.161.07:34:42.62#ibcon#flushed, iclass 34, count 0 2006.161.07:34:42.62#ibcon#about to write, iclass 34, count 0 2006.161.07:34:42.62#ibcon#wrote, iclass 34, count 0 2006.161.07:34:42.62#ibcon#about to read 3, iclass 34, count 0 2006.161.07:34:42.66#ibcon#read 3, iclass 34, count 0 2006.161.07:34:42.66#ibcon#about to read 4, iclass 34, count 0 2006.161.07:34:42.66#ibcon#read 4, iclass 34, count 0 2006.161.07:34:42.66#ibcon#about to read 5, iclass 34, count 0 2006.161.07:34:42.66#ibcon#read 5, iclass 34, count 0 2006.161.07:34:42.66#ibcon#about to read 6, iclass 34, count 0 2006.161.07:34:42.66#ibcon#read 6, iclass 34, count 0 2006.161.07:34:42.66#ibcon#end of sib2, iclass 34, count 0 2006.161.07:34:42.66#ibcon#*after write, iclass 34, count 0 2006.161.07:34:42.66#ibcon#*before return 0, iclass 34, count 0 2006.161.07:34:42.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:42.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:34:42.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:34:42.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:34:42.66$vc4f8/vb=2,4 2006.161.07:34:42.66#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.07:34:42.66#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.07:34:42.66#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:42.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:42.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:42.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:42.72#ibcon#enter wrdev, iclass 36, count 2 2006.161.07:34:42.72#ibcon#first serial, iclass 36, count 2 2006.161.07:34:42.72#ibcon#enter sib2, iclass 36, count 2 2006.161.07:34:42.72#ibcon#flushed, iclass 36, count 2 2006.161.07:34:42.72#ibcon#about to write, iclass 36, count 2 2006.161.07:34:42.72#ibcon#wrote, iclass 36, count 2 2006.161.07:34:42.72#ibcon#about to read 3, iclass 36, count 2 2006.161.07:34:42.74#ibcon#read 3, iclass 36, count 2 2006.161.07:34:42.74#ibcon#about to read 4, iclass 36, count 2 2006.161.07:34:42.74#ibcon#read 4, iclass 36, count 2 2006.161.07:34:42.74#ibcon#about to read 5, iclass 36, count 2 2006.161.07:34:42.74#ibcon#read 5, iclass 36, count 2 2006.161.07:34:42.74#ibcon#about to read 6, iclass 36, count 2 2006.161.07:34:42.74#ibcon#read 6, iclass 36, count 2 2006.161.07:34:42.74#ibcon#end of sib2, iclass 36, count 2 2006.161.07:34:42.74#ibcon#*mode == 0, iclass 36, count 2 2006.161.07:34:42.74#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.07:34:42.74#ibcon#[27=AT02-04\r\n] 2006.161.07:34:42.74#ibcon#*before write, iclass 36, count 2 2006.161.07:34:42.74#ibcon#enter sib2, iclass 36, count 2 2006.161.07:34:42.74#ibcon#flushed, iclass 36, count 2 2006.161.07:34:42.74#ibcon#about to write, iclass 36, count 2 2006.161.07:34:42.74#ibcon#wrote, iclass 36, count 2 2006.161.07:34:42.74#ibcon#about to read 3, iclass 36, count 2 2006.161.07:34:42.77#ibcon#read 3, iclass 36, count 2 2006.161.07:34:42.77#ibcon#about to read 4, iclass 36, count 2 2006.161.07:34:42.77#ibcon#read 4, iclass 36, count 2 2006.161.07:34:42.77#ibcon#about to read 5, iclass 36, count 2 2006.161.07:34:42.77#ibcon#read 5, iclass 36, count 2 2006.161.07:34:42.77#ibcon#about to read 6, iclass 36, count 2 2006.161.07:34:42.77#ibcon#read 6, iclass 36, count 2 2006.161.07:34:42.77#ibcon#end of sib2, iclass 36, count 2 2006.161.07:34:42.77#ibcon#*after write, iclass 36, count 2 2006.161.07:34:42.77#ibcon#*before return 0, iclass 36, count 2 2006.161.07:34:42.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:42.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:34:42.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.07:34:42.77#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:42.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:42.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:42.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:42.89#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:34:42.89#ibcon#first serial, iclass 36, count 0 2006.161.07:34:42.89#ibcon#enter sib2, iclass 36, count 0 2006.161.07:34:42.89#ibcon#flushed, iclass 36, count 0 2006.161.07:34:42.89#ibcon#about to write, iclass 36, count 0 2006.161.07:34:42.89#ibcon#wrote, iclass 36, count 0 2006.161.07:34:42.89#ibcon#about to read 3, iclass 36, count 0 2006.161.07:34:42.91#ibcon#read 3, iclass 36, count 0 2006.161.07:34:42.91#ibcon#about to read 4, iclass 36, count 0 2006.161.07:34:42.91#ibcon#read 4, iclass 36, count 0 2006.161.07:34:42.91#ibcon#about to read 5, iclass 36, count 0 2006.161.07:34:42.91#ibcon#read 5, iclass 36, count 0 2006.161.07:34:42.91#ibcon#about to read 6, iclass 36, count 0 2006.161.07:34:42.91#ibcon#read 6, iclass 36, count 0 2006.161.07:34:42.91#ibcon#end of sib2, iclass 36, count 0 2006.161.07:34:42.91#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:34:42.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:34:42.91#ibcon#[27=USB\r\n] 2006.161.07:34:42.91#ibcon#*before write, iclass 36, count 0 2006.161.07:34:42.91#ibcon#enter sib2, iclass 36, count 0 2006.161.07:34:42.91#ibcon#flushed, iclass 36, count 0 2006.161.07:34:42.91#ibcon#about to write, iclass 36, count 0 2006.161.07:34:42.91#ibcon#wrote, iclass 36, count 0 2006.161.07:34:42.91#ibcon#about to read 3, iclass 36, count 0 2006.161.07:34:42.94#ibcon#read 3, iclass 36, count 0 2006.161.07:34:42.94#ibcon#about to read 4, iclass 36, count 0 2006.161.07:34:42.94#ibcon#read 4, iclass 36, count 0 2006.161.07:34:42.94#ibcon#about to read 5, iclass 36, count 0 2006.161.07:34:42.94#ibcon#read 5, iclass 36, count 0 2006.161.07:34:42.94#ibcon#about to read 6, iclass 36, count 0 2006.161.07:34:42.94#ibcon#read 6, iclass 36, count 0 2006.161.07:34:42.94#ibcon#end of sib2, iclass 36, count 0 2006.161.07:34:42.94#ibcon#*after write, iclass 36, count 0 2006.161.07:34:42.94#ibcon#*before return 0, iclass 36, count 0 2006.161.07:34:42.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:42.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:34:42.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:34:42.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:34:42.94$vc4f8/vblo=3,656.99 2006.161.07:34:42.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.07:34:42.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.07:34:42.94#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:42.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:34:42.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:34:42.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:34:42.94#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:34:42.94#ibcon#first serial, iclass 38, count 0 2006.161.07:34:42.94#ibcon#enter sib2, iclass 38, count 0 2006.161.07:34:42.94#ibcon#flushed, iclass 38, count 0 2006.161.07:34:42.94#ibcon#about to write, iclass 38, count 0 2006.161.07:34:42.94#ibcon#wrote, iclass 38, count 0 2006.161.07:34:42.94#ibcon#about to read 3, iclass 38, count 0 2006.161.07:34:42.96#ibcon#read 3, iclass 38, count 0 2006.161.07:34:42.96#ibcon#about to read 4, iclass 38, count 0 2006.161.07:34:42.96#ibcon#read 4, iclass 38, count 0 2006.161.07:34:42.96#ibcon#about to read 5, iclass 38, count 0 2006.161.07:34:42.96#ibcon#read 5, iclass 38, count 0 2006.161.07:34:42.96#ibcon#about to read 6, iclass 38, count 0 2006.161.07:34:42.96#ibcon#read 6, iclass 38, count 0 2006.161.07:34:42.96#ibcon#end of sib2, iclass 38, count 0 2006.161.07:34:42.96#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:34:42.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:34:42.96#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:34:42.96#ibcon#*before write, iclass 38, count 0 2006.161.07:34:42.96#ibcon#enter sib2, iclass 38, count 0 2006.161.07:34:42.96#ibcon#flushed, iclass 38, count 0 2006.161.07:34:42.96#ibcon#about to write, iclass 38, count 0 2006.161.07:34:42.96#ibcon#wrote, iclass 38, count 0 2006.161.07:34:42.96#ibcon#about to read 3, iclass 38, count 0 2006.161.07:34:43.00#ibcon#read 3, iclass 38, count 0 2006.161.07:34:43.00#ibcon#about to read 4, iclass 38, count 0 2006.161.07:34:43.00#ibcon#read 4, iclass 38, count 0 2006.161.07:34:43.00#ibcon#about to read 5, iclass 38, count 0 2006.161.07:34:43.00#ibcon#read 5, iclass 38, count 0 2006.161.07:34:43.00#ibcon#about to read 6, iclass 38, count 0 2006.161.07:34:43.00#ibcon#read 6, iclass 38, count 0 2006.161.07:34:43.00#ibcon#end of sib2, iclass 38, count 0 2006.161.07:34:43.00#ibcon#*after write, iclass 38, count 0 2006.161.07:34:43.00#ibcon#*before return 0, iclass 38, count 0 2006.161.07:34:43.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:34:43.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:34:43.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:34:43.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:34:43.00$vc4f8/vb=3,4 2006.161.07:34:43.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.07:34:43.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.07:34:43.00#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:43.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:34:43.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:34:43.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:34:43.06#ibcon#enter wrdev, iclass 40, count 2 2006.161.07:34:43.06#ibcon#first serial, iclass 40, count 2 2006.161.07:34:43.06#ibcon#enter sib2, iclass 40, count 2 2006.161.07:34:43.06#ibcon#flushed, iclass 40, count 2 2006.161.07:34:43.06#ibcon#about to write, iclass 40, count 2 2006.161.07:34:43.06#ibcon#wrote, iclass 40, count 2 2006.161.07:34:43.06#ibcon#about to read 3, iclass 40, count 2 2006.161.07:34:43.08#ibcon#read 3, iclass 40, count 2 2006.161.07:34:43.08#ibcon#about to read 4, iclass 40, count 2 2006.161.07:34:43.08#ibcon#read 4, iclass 40, count 2 2006.161.07:34:43.08#ibcon#about to read 5, iclass 40, count 2 2006.161.07:34:43.08#ibcon#read 5, iclass 40, count 2 2006.161.07:34:43.08#ibcon#about to read 6, iclass 40, count 2 2006.161.07:34:43.08#ibcon#read 6, iclass 40, count 2 2006.161.07:34:43.08#ibcon#end of sib2, iclass 40, count 2 2006.161.07:34:43.08#ibcon#*mode == 0, iclass 40, count 2 2006.161.07:34:43.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.07:34:43.08#ibcon#[27=AT03-04\r\n] 2006.161.07:34:43.08#ibcon#*before write, iclass 40, count 2 2006.161.07:34:43.08#ibcon#enter sib2, iclass 40, count 2 2006.161.07:34:43.08#ibcon#flushed, iclass 40, count 2 2006.161.07:34:43.08#ibcon#about to write, iclass 40, count 2 2006.161.07:34:43.08#ibcon#wrote, iclass 40, count 2 2006.161.07:34:43.08#ibcon#about to read 3, iclass 40, count 2 2006.161.07:34:43.11#ibcon#read 3, iclass 40, count 2 2006.161.07:34:43.11#ibcon#about to read 4, iclass 40, count 2 2006.161.07:34:43.11#ibcon#read 4, iclass 40, count 2 2006.161.07:34:43.11#ibcon#about to read 5, iclass 40, count 2 2006.161.07:34:43.11#ibcon#read 5, iclass 40, count 2 2006.161.07:34:43.11#ibcon#about to read 6, iclass 40, count 2 2006.161.07:34:43.11#ibcon#read 6, iclass 40, count 2 2006.161.07:34:43.11#ibcon#end of sib2, iclass 40, count 2 2006.161.07:34:43.11#ibcon#*after write, iclass 40, count 2 2006.161.07:34:43.11#ibcon#*before return 0, iclass 40, count 2 2006.161.07:34:43.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:34:43.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:34:43.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.07:34:43.11#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:43.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:34:43.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:34:43.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:34:43.23#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:34:43.23#ibcon#first serial, iclass 40, count 0 2006.161.07:34:43.23#ibcon#enter sib2, iclass 40, count 0 2006.161.07:34:43.23#ibcon#flushed, iclass 40, count 0 2006.161.07:34:43.23#ibcon#about to write, iclass 40, count 0 2006.161.07:34:43.23#ibcon#wrote, iclass 40, count 0 2006.161.07:34:43.23#ibcon#about to read 3, iclass 40, count 0 2006.161.07:34:43.25#ibcon#read 3, iclass 40, count 0 2006.161.07:34:43.25#ibcon#about to read 4, iclass 40, count 0 2006.161.07:34:43.25#ibcon#read 4, iclass 40, count 0 2006.161.07:34:43.25#ibcon#about to read 5, iclass 40, count 0 2006.161.07:34:43.25#ibcon#read 5, iclass 40, count 0 2006.161.07:34:43.25#ibcon#about to read 6, iclass 40, count 0 2006.161.07:34:43.25#ibcon#read 6, iclass 40, count 0 2006.161.07:34:43.25#ibcon#end of sib2, iclass 40, count 0 2006.161.07:34:43.25#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:34:43.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:34:43.25#ibcon#[27=USB\r\n] 2006.161.07:34:43.25#ibcon#*before write, iclass 40, count 0 2006.161.07:34:43.25#ibcon#enter sib2, iclass 40, count 0 2006.161.07:34:43.25#ibcon#flushed, iclass 40, count 0 2006.161.07:34:43.25#ibcon#about to write, iclass 40, count 0 2006.161.07:34:43.25#ibcon#wrote, iclass 40, count 0 2006.161.07:34:43.25#ibcon#about to read 3, iclass 40, count 0 2006.161.07:34:43.28#ibcon#read 3, iclass 40, count 0 2006.161.07:34:43.28#ibcon#about to read 4, iclass 40, count 0 2006.161.07:34:43.28#ibcon#read 4, iclass 40, count 0 2006.161.07:34:43.28#ibcon#about to read 5, iclass 40, count 0 2006.161.07:34:43.28#ibcon#read 5, iclass 40, count 0 2006.161.07:34:43.28#ibcon#about to read 6, iclass 40, count 0 2006.161.07:34:43.28#ibcon#read 6, iclass 40, count 0 2006.161.07:34:43.28#ibcon#end of sib2, iclass 40, count 0 2006.161.07:34:43.28#ibcon#*after write, iclass 40, count 0 2006.161.07:34:43.28#ibcon#*before return 0, iclass 40, count 0 2006.161.07:34:43.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:34:43.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:34:43.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:34:43.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:34:43.28$vc4f8/vblo=4,712.99 2006.161.07:34:43.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.07:34:43.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.07:34:43.28#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:43.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:43.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:43.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:43.28#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:34:43.28#ibcon#first serial, iclass 4, count 0 2006.161.07:34:43.28#ibcon#enter sib2, iclass 4, count 0 2006.161.07:34:43.28#ibcon#flushed, iclass 4, count 0 2006.161.07:34:43.28#ibcon#about to write, iclass 4, count 0 2006.161.07:34:43.28#ibcon#wrote, iclass 4, count 0 2006.161.07:34:43.28#ibcon#about to read 3, iclass 4, count 0 2006.161.07:34:43.30#ibcon#read 3, iclass 4, count 0 2006.161.07:34:43.30#ibcon#about to read 4, iclass 4, count 0 2006.161.07:34:43.30#ibcon#read 4, iclass 4, count 0 2006.161.07:34:43.30#ibcon#about to read 5, iclass 4, count 0 2006.161.07:34:43.30#ibcon#read 5, iclass 4, count 0 2006.161.07:34:43.30#ibcon#about to read 6, iclass 4, count 0 2006.161.07:34:43.30#ibcon#read 6, iclass 4, count 0 2006.161.07:34:43.30#ibcon#end of sib2, iclass 4, count 0 2006.161.07:34:43.30#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:34:43.30#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:34:43.30#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:34:43.30#ibcon#*before write, iclass 4, count 0 2006.161.07:34:43.30#ibcon#enter sib2, iclass 4, count 0 2006.161.07:34:43.30#ibcon#flushed, iclass 4, count 0 2006.161.07:34:43.30#ibcon#about to write, iclass 4, count 0 2006.161.07:34:43.30#ibcon#wrote, iclass 4, count 0 2006.161.07:34:43.30#ibcon#about to read 3, iclass 4, count 0 2006.161.07:34:43.34#ibcon#read 3, iclass 4, count 0 2006.161.07:34:43.34#ibcon#about to read 4, iclass 4, count 0 2006.161.07:34:43.34#ibcon#read 4, iclass 4, count 0 2006.161.07:34:43.34#ibcon#about to read 5, iclass 4, count 0 2006.161.07:34:43.34#ibcon#read 5, iclass 4, count 0 2006.161.07:34:43.34#ibcon#about to read 6, iclass 4, count 0 2006.161.07:34:43.34#ibcon#read 6, iclass 4, count 0 2006.161.07:34:43.34#ibcon#end of sib2, iclass 4, count 0 2006.161.07:34:43.34#ibcon#*after write, iclass 4, count 0 2006.161.07:34:43.34#ibcon#*before return 0, iclass 4, count 0 2006.161.07:34:43.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:43.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:34:43.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:34:43.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:34:43.34$vc4f8/vb=4,4 2006.161.07:34:43.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.07:34:43.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.07:34:43.34#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:43.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:43.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:43.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:43.40#ibcon#enter wrdev, iclass 6, count 2 2006.161.07:34:43.40#ibcon#first serial, iclass 6, count 2 2006.161.07:34:43.40#ibcon#enter sib2, iclass 6, count 2 2006.161.07:34:43.40#ibcon#flushed, iclass 6, count 2 2006.161.07:34:43.40#ibcon#about to write, iclass 6, count 2 2006.161.07:34:43.40#ibcon#wrote, iclass 6, count 2 2006.161.07:34:43.40#ibcon#about to read 3, iclass 6, count 2 2006.161.07:34:43.42#ibcon#read 3, iclass 6, count 2 2006.161.07:34:43.42#ibcon#about to read 4, iclass 6, count 2 2006.161.07:34:43.42#ibcon#read 4, iclass 6, count 2 2006.161.07:34:43.42#ibcon#about to read 5, iclass 6, count 2 2006.161.07:34:43.42#ibcon#read 5, iclass 6, count 2 2006.161.07:34:43.42#ibcon#about to read 6, iclass 6, count 2 2006.161.07:34:43.42#ibcon#read 6, iclass 6, count 2 2006.161.07:34:43.42#ibcon#end of sib2, iclass 6, count 2 2006.161.07:34:43.42#ibcon#*mode == 0, iclass 6, count 2 2006.161.07:34:43.42#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.07:34:43.42#ibcon#[27=AT04-04\r\n] 2006.161.07:34:43.42#ibcon#*before write, iclass 6, count 2 2006.161.07:34:43.42#ibcon#enter sib2, iclass 6, count 2 2006.161.07:34:43.42#ibcon#flushed, iclass 6, count 2 2006.161.07:34:43.42#ibcon#about to write, iclass 6, count 2 2006.161.07:34:43.42#ibcon#wrote, iclass 6, count 2 2006.161.07:34:43.42#ibcon#about to read 3, iclass 6, count 2 2006.161.07:34:43.45#ibcon#read 3, iclass 6, count 2 2006.161.07:34:43.45#ibcon#about to read 4, iclass 6, count 2 2006.161.07:34:43.45#ibcon#read 4, iclass 6, count 2 2006.161.07:34:43.45#ibcon#about to read 5, iclass 6, count 2 2006.161.07:34:43.45#ibcon#read 5, iclass 6, count 2 2006.161.07:34:43.45#ibcon#about to read 6, iclass 6, count 2 2006.161.07:34:43.45#ibcon#read 6, iclass 6, count 2 2006.161.07:34:43.45#ibcon#end of sib2, iclass 6, count 2 2006.161.07:34:43.45#ibcon#*after write, iclass 6, count 2 2006.161.07:34:43.45#ibcon#*before return 0, iclass 6, count 2 2006.161.07:34:43.45#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:43.45#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:34:43.45#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.07:34:43.45#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:43.45#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:43.57#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:43.57#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:43.57#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:34:43.57#ibcon#first serial, iclass 6, count 0 2006.161.07:34:43.57#ibcon#enter sib2, iclass 6, count 0 2006.161.07:34:43.57#ibcon#flushed, iclass 6, count 0 2006.161.07:34:43.57#ibcon#about to write, iclass 6, count 0 2006.161.07:34:43.57#ibcon#wrote, iclass 6, count 0 2006.161.07:34:43.57#ibcon#about to read 3, iclass 6, count 0 2006.161.07:34:43.59#ibcon#read 3, iclass 6, count 0 2006.161.07:34:43.59#ibcon#about to read 4, iclass 6, count 0 2006.161.07:34:43.59#ibcon#read 4, iclass 6, count 0 2006.161.07:34:43.59#ibcon#about to read 5, iclass 6, count 0 2006.161.07:34:43.59#ibcon#read 5, iclass 6, count 0 2006.161.07:34:43.59#ibcon#about to read 6, iclass 6, count 0 2006.161.07:34:43.59#ibcon#read 6, iclass 6, count 0 2006.161.07:34:43.59#ibcon#end of sib2, iclass 6, count 0 2006.161.07:34:43.59#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:34:43.59#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:34:43.59#ibcon#[27=USB\r\n] 2006.161.07:34:43.59#ibcon#*before write, iclass 6, count 0 2006.161.07:34:43.59#ibcon#enter sib2, iclass 6, count 0 2006.161.07:34:43.59#ibcon#flushed, iclass 6, count 0 2006.161.07:34:43.59#ibcon#about to write, iclass 6, count 0 2006.161.07:34:43.59#ibcon#wrote, iclass 6, count 0 2006.161.07:34:43.59#ibcon#about to read 3, iclass 6, count 0 2006.161.07:34:43.62#ibcon#read 3, iclass 6, count 0 2006.161.07:34:43.62#ibcon#about to read 4, iclass 6, count 0 2006.161.07:34:43.62#ibcon#read 4, iclass 6, count 0 2006.161.07:34:43.62#ibcon#about to read 5, iclass 6, count 0 2006.161.07:34:43.62#ibcon#read 5, iclass 6, count 0 2006.161.07:34:43.62#ibcon#about to read 6, iclass 6, count 0 2006.161.07:34:43.62#ibcon#read 6, iclass 6, count 0 2006.161.07:34:43.62#ibcon#end of sib2, iclass 6, count 0 2006.161.07:34:43.62#ibcon#*after write, iclass 6, count 0 2006.161.07:34:43.62#ibcon#*before return 0, iclass 6, count 0 2006.161.07:34:43.62#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:43.62#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:34:43.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:34:43.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:34:43.62$vc4f8/vblo=5,744.99 2006.161.07:34:43.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:34:43.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:34:43.62#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:43.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:43.62#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:43.62#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:43.62#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:34:43.62#ibcon#first serial, iclass 10, count 0 2006.161.07:34:43.62#ibcon#enter sib2, iclass 10, count 0 2006.161.07:34:43.62#ibcon#flushed, iclass 10, count 0 2006.161.07:34:43.62#ibcon#about to write, iclass 10, count 0 2006.161.07:34:43.62#ibcon#wrote, iclass 10, count 0 2006.161.07:34:43.62#ibcon#about to read 3, iclass 10, count 0 2006.161.07:34:43.64#ibcon#read 3, iclass 10, count 0 2006.161.07:34:43.64#ibcon#about to read 4, iclass 10, count 0 2006.161.07:34:43.64#ibcon#read 4, iclass 10, count 0 2006.161.07:34:43.64#ibcon#about to read 5, iclass 10, count 0 2006.161.07:34:43.64#ibcon#read 5, iclass 10, count 0 2006.161.07:34:43.64#ibcon#about to read 6, iclass 10, count 0 2006.161.07:34:43.64#ibcon#read 6, iclass 10, count 0 2006.161.07:34:43.64#ibcon#end of sib2, iclass 10, count 0 2006.161.07:34:43.64#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:34:43.64#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:34:43.64#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:34:43.64#ibcon#*before write, iclass 10, count 0 2006.161.07:34:43.64#ibcon#enter sib2, iclass 10, count 0 2006.161.07:34:43.64#ibcon#flushed, iclass 10, count 0 2006.161.07:34:43.64#ibcon#about to write, iclass 10, count 0 2006.161.07:34:43.64#ibcon#wrote, iclass 10, count 0 2006.161.07:34:43.64#ibcon#about to read 3, iclass 10, count 0 2006.161.07:34:43.68#ibcon#read 3, iclass 10, count 0 2006.161.07:34:43.68#ibcon#about to read 4, iclass 10, count 0 2006.161.07:34:43.68#ibcon#read 4, iclass 10, count 0 2006.161.07:34:43.68#ibcon#about to read 5, iclass 10, count 0 2006.161.07:34:43.68#ibcon#read 5, iclass 10, count 0 2006.161.07:34:43.68#ibcon#about to read 6, iclass 10, count 0 2006.161.07:34:43.68#ibcon#read 6, iclass 10, count 0 2006.161.07:34:43.68#ibcon#end of sib2, iclass 10, count 0 2006.161.07:34:43.68#ibcon#*after write, iclass 10, count 0 2006.161.07:34:43.68#ibcon#*before return 0, iclass 10, count 0 2006.161.07:34:43.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:43.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:34:43.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:34:43.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:34:43.68$vc4f8/vb=5,4 2006.161.07:34:43.68#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.07:34:43.68#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.07:34:43.68#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:43.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:43.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:43.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:43.74#ibcon#enter wrdev, iclass 12, count 2 2006.161.07:34:43.74#ibcon#first serial, iclass 12, count 2 2006.161.07:34:43.74#ibcon#enter sib2, iclass 12, count 2 2006.161.07:34:43.74#ibcon#flushed, iclass 12, count 2 2006.161.07:34:43.74#ibcon#about to write, iclass 12, count 2 2006.161.07:34:43.74#ibcon#wrote, iclass 12, count 2 2006.161.07:34:43.74#ibcon#about to read 3, iclass 12, count 2 2006.161.07:34:43.76#ibcon#read 3, iclass 12, count 2 2006.161.07:34:43.76#ibcon#about to read 4, iclass 12, count 2 2006.161.07:34:43.76#ibcon#read 4, iclass 12, count 2 2006.161.07:34:43.76#ibcon#about to read 5, iclass 12, count 2 2006.161.07:34:43.76#ibcon#read 5, iclass 12, count 2 2006.161.07:34:43.76#ibcon#about to read 6, iclass 12, count 2 2006.161.07:34:43.76#ibcon#read 6, iclass 12, count 2 2006.161.07:34:43.76#ibcon#end of sib2, iclass 12, count 2 2006.161.07:34:43.76#ibcon#*mode == 0, iclass 12, count 2 2006.161.07:34:43.76#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.07:34:43.76#ibcon#[27=AT05-04\r\n] 2006.161.07:34:43.76#ibcon#*before write, iclass 12, count 2 2006.161.07:34:43.76#ibcon#enter sib2, iclass 12, count 2 2006.161.07:34:43.76#ibcon#flushed, iclass 12, count 2 2006.161.07:34:43.76#ibcon#about to write, iclass 12, count 2 2006.161.07:34:43.76#ibcon#wrote, iclass 12, count 2 2006.161.07:34:43.76#ibcon#about to read 3, iclass 12, count 2 2006.161.07:34:43.79#ibcon#read 3, iclass 12, count 2 2006.161.07:34:43.79#ibcon#about to read 4, iclass 12, count 2 2006.161.07:34:43.79#ibcon#read 4, iclass 12, count 2 2006.161.07:34:43.79#ibcon#about to read 5, iclass 12, count 2 2006.161.07:34:43.79#ibcon#read 5, iclass 12, count 2 2006.161.07:34:43.79#ibcon#about to read 6, iclass 12, count 2 2006.161.07:34:43.79#ibcon#read 6, iclass 12, count 2 2006.161.07:34:43.79#ibcon#end of sib2, iclass 12, count 2 2006.161.07:34:43.79#ibcon#*after write, iclass 12, count 2 2006.161.07:34:43.79#ibcon#*before return 0, iclass 12, count 2 2006.161.07:34:43.79#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:43.79#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:34:43.79#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.07:34:43.79#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:43.79#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:43.91#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:43.91#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:43.91#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:34:43.91#ibcon#first serial, iclass 12, count 0 2006.161.07:34:43.91#ibcon#enter sib2, iclass 12, count 0 2006.161.07:34:43.91#ibcon#flushed, iclass 12, count 0 2006.161.07:34:43.91#ibcon#about to write, iclass 12, count 0 2006.161.07:34:43.91#ibcon#wrote, iclass 12, count 0 2006.161.07:34:43.91#ibcon#about to read 3, iclass 12, count 0 2006.161.07:34:43.93#ibcon#read 3, iclass 12, count 0 2006.161.07:34:43.93#ibcon#about to read 4, iclass 12, count 0 2006.161.07:34:43.93#ibcon#read 4, iclass 12, count 0 2006.161.07:34:43.93#ibcon#about to read 5, iclass 12, count 0 2006.161.07:34:43.93#ibcon#read 5, iclass 12, count 0 2006.161.07:34:43.93#ibcon#about to read 6, iclass 12, count 0 2006.161.07:34:43.93#ibcon#read 6, iclass 12, count 0 2006.161.07:34:43.93#ibcon#end of sib2, iclass 12, count 0 2006.161.07:34:43.93#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:34:43.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:34:43.93#ibcon#[27=USB\r\n] 2006.161.07:34:43.93#ibcon#*before write, iclass 12, count 0 2006.161.07:34:43.93#ibcon#enter sib2, iclass 12, count 0 2006.161.07:34:43.93#ibcon#flushed, iclass 12, count 0 2006.161.07:34:43.93#ibcon#about to write, iclass 12, count 0 2006.161.07:34:43.93#ibcon#wrote, iclass 12, count 0 2006.161.07:34:43.93#ibcon#about to read 3, iclass 12, count 0 2006.161.07:34:43.96#ibcon#read 3, iclass 12, count 0 2006.161.07:34:43.96#ibcon#about to read 4, iclass 12, count 0 2006.161.07:34:43.96#ibcon#read 4, iclass 12, count 0 2006.161.07:34:43.96#ibcon#about to read 5, iclass 12, count 0 2006.161.07:34:43.96#ibcon#read 5, iclass 12, count 0 2006.161.07:34:43.96#ibcon#about to read 6, iclass 12, count 0 2006.161.07:34:43.96#ibcon#read 6, iclass 12, count 0 2006.161.07:34:43.96#ibcon#end of sib2, iclass 12, count 0 2006.161.07:34:43.96#ibcon#*after write, iclass 12, count 0 2006.161.07:34:43.96#ibcon#*before return 0, iclass 12, count 0 2006.161.07:34:43.96#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:43.96#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:34:43.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:34:43.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:34:43.96$vc4f8/vblo=6,752.99 2006.161.07:34:43.96#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.07:34:43.96#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.07:34:43.96#ibcon#ireg 17 cls_cnt 0 2006.161.07:34:43.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:43.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:43.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:43.96#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:34:43.96#ibcon#first serial, iclass 14, count 0 2006.161.07:34:43.96#ibcon#enter sib2, iclass 14, count 0 2006.161.07:34:43.96#ibcon#flushed, iclass 14, count 0 2006.161.07:34:43.96#ibcon#about to write, iclass 14, count 0 2006.161.07:34:43.96#ibcon#wrote, iclass 14, count 0 2006.161.07:34:43.96#ibcon#about to read 3, iclass 14, count 0 2006.161.07:34:43.98#ibcon#read 3, iclass 14, count 0 2006.161.07:34:43.98#ibcon#about to read 4, iclass 14, count 0 2006.161.07:34:43.98#ibcon#read 4, iclass 14, count 0 2006.161.07:34:43.98#ibcon#about to read 5, iclass 14, count 0 2006.161.07:34:43.98#ibcon#read 5, iclass 14, count 0 2006.161.07:34:43.98#ibcon#about to read 6, iclass 14, count 0 2006.161.07:34:43.98#ibcon#read 6, iclass 14, count 0 2006.161.07:34:43.98#ibcon#end of sib2, iclass 14, count 0 2006.161.07:34:43.98#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:34:43.98#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:34:43.98#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:34:43.98#ibcon#*before write, iclass 14, count 0 2006.161.07:34:43.98#ibcon#enter sib2, iclass 14, count 0 2006.161.07:34:43.98#ibcon#flushed, iclass 14, count 0 2006.161.07:34:43.98#ibcon#about to write, iclass 14, count 0 2006.161.07:34:43.98#ibcon#wrote, iclass 14, count 0 2006.161.07:34:43.98#ibcon#about to read 3, iclass 14, count 0 2006.161.07:34:44.02#ibcon#read 3, iclass 14, count 0 2006.161.07:34:44.02#ibcon#about to read 4, iclass 14, count 0 2006.161.07:34:44.02#ibcon#read 4, iclass 14, count 0 2006.161.07:34:44.02#ibcon#about to read 5, iclass 14, count 0 2006.161.07:34:44.02#ibcon#read 5, iclass 14, count 0 2006.161.07:34:44.02#ibcon#about to read 6, iclass 14, count 0 2006.161.07:34:44.02#ibcon#read 6, iclass 14, count 0 2006.161.07:34:44.02#ibcon#end of sib2, iclass 14, count 0 2006.161.07:34:44.02#ibcon#*after write, iclass 14, count 0 2006.161.07:34:44.02#ibcon#*before return 0, iclass 14, count 0 2006.161.07:34:44.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:44.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:34:44.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:34:44.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:34:44.02$vc4f8/vb=6,4 2006.161.07:34:44.02#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.07:34:44.02#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.07:34:44.02#ibcon#ireg 11 cls_cnt 2 2006.161.07:34:44.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:44.08#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:44.08#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:44.08#ibcon#enter wrdev, iclass 16, count 2 2006.161.07:34:44.08#ibcon#first serial, iclass 16, count 2 2006.161.07:34:44.08#ibcon#enter sib2, iclass 16, count 2 2006.161.07:34:44.08#ibcon#flushed, iclass 16, count 2 2006.161.07:34:44.08#ibcon#about to write, iclass 16, count 2 2006.161.07:34:44.08#ibcon#wrote, iclass 16, count 2 2006.161.07:34:44.08#ibcon#about to read 3, iclass 16, count 2 2006.161.07:34:44.10#ibcon#read 3, iclass 16, count 2 2006.161.07:34:44.10#ibcon#about to read 4, iclass 16, count 2 2006.161.07:34:44.10#ibcon#read 4, iclass 16, count 2 2006.161.07:34:44.10#ibcon#about to read 5, iclass 16, count 2 2006.161.07:34:44.10#ibcon#read 5, iclass 16, count 2 2006.161.07:34:44.10#ibcon#about to read 6, iclass 16, count 2 2006.161.07:34:44.10#ibcon#read 6, iclass 16, count 2 2006.161.07:34:44.10#ibcon#end of sib2, iclass 16, count 2 2006.161.07:34:44.10#ibcon#*mode == 0, iclass 16, count 2 2006.161.07:34:44.10#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.07:34:44.10#ibcon#[27=AT06-04\r\n] 2006.161.07:34:44.10#ibcon#*before write, iclass 16, count 2 2006.161.07:34:44.10#ibcon#enter sib2, iclass 16, count 2 2006.161.07:34:44.10#ibcon#flushed, iclass 16, count 2 2006.161.07:34:44.10#ibcon#about to write, iclass 16, count 2 2006.161.07:34:44.10#ibcon#wrote, iclass 16, count 2 2006.161.07:34:44.10#ibcon#about to read 3, iclass 16, count 2 2006.161.07:34:44.13#ibcon#read 3, iclass 16, count 2 2006.161.07:34:44.13#ibcon#about to read 4, iclass 16, count 2 2006.161.07:34:44.13#ibcon#read 4, iclass 16, count 2 2006.161.07:34:44.13#ibcon#about to read 5, iclass 16, count 2 2006.161.07:34:44.13#ibcon#read 5, iclass 16, count 2 2006.161.07:34:44.13#ibcon#about to read 6, iclass 16, count 2 2006.161.07:34:44.13#ibcon#read 6, iclass 16, count 2 2006.161.07:34:44.13#ibcon#end of sib2, iclass 16, count 2 2006.161.07:34:44.13#ibcon#*after write, iclass 16, count 2 2006.161.07:34:44.13#ibcon#*before return 0, iclass 16, count 2 2006.161.07:34:44.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:44.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:34:44.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.07:34:44.13#ibcon#ireg 7 cls_cnt 0 2006.161.07:34:44.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:44.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:44.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:44.25#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:34:44.25#ibcon#first serial, iclass 16, count 0 2006.161.07:34:44.25#ibcon#enter sib2, iclass 16, count 0 2006.161.07:34:44.25#ibcon#flushed, iclass 16, count 0 2006.161.07:34:44.25#ibcon#about to write, iclass 16, count 0 2006.161.07:34:44.25#ibcon#wrote, iclass 16, count 0 2006.161.07:34:44.25#ibcon#about to read 3, iclass 16, count 0 2006.161.07:34:44.27#ibcon#read 3, iclass 16, count 0 2006.161.07:34:44.27#ibcon#about to read 4, iclass 16, count 0 2006.161.07:34:44.27#ibcon#read 4, iclass 16, count 0 2006.161.07:34:44.27#ibcon#about to read 5, iclass 16, count 0 2006.161.07:34:44.27#ibcon#read 5, iclass 16, count 0 2006.161.07:34:44.27#ibcon#about to read 6, iclass 16, count 0 2006.161.07:34:44.27#ibcon#read 6, iclass 16, count 0 2006.161.07:34:44.27#ibcon#end of sib2, iclass 16, count 0 2006.161.07:34:44.27#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:34:44.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:34:44.27#ibcon#[27=USB\r\n] 2006.161.07:34:44.27#ibcon#*before write, iclass 16, count 0 2006.161.07:34:44.27#ibcon#enter sib2, iclass 16, count 0 2006.161.07:34:44.27#ibcon#flushed, iclass 16, count 0 2006.161.07:34:44.27#ibcon#about to write, iclass 16, count 0 2006.161.07:34:44.27#ibcon#wrote, iclass 16, count 0 2006.161.07:34:44.27#ibcon#about to read 3, iclass 16, count 0 2006.161.07:34:44.30#ibcon#read 3, iclass 16, count 0 2006.161.07:34:44.30#ibcon#about to read 4, iclass 16, count 0 2006.161.07:34:44.30#ibcon#read 4, iclass 16, count 0 2006.161.07:34:44.30#ibcon#about to read 5, iclass 16, count 0 2006.161.07:34:44.30#ibcon#read 5, iclass 16, count 0 2006.161.07:34:44.30#ibcon#about to read 6, iclass 16, count 0 2006.161.07:34:44.30#ibcon#read 6, iclass 16, count 0 2006.161.07:34:44.30#ibcon#end of sib2, iclass 16, count 0 2006.161.07:34:44.30#ibcon#*after write, iclass 16, count 0 2006.161.07:34:44.30#ibcon#*before return 0, iclass 16, count 0 2006.161.07:34:44.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:44.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:34:44.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:34:44.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:34:44.30$vc4f8/vabw=wide 2006.161.07:34:44.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.07:34:44.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.07:34:44.30#ibcon#ireg 8 cls_cnt 0 2006.161.07:34:44.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:44.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:44.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:44.30#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:34:44.30#ibcon#first serial, iclass 18, count 0 2006.161.07:34:44.30#ibcon#enter sib2, iclass 18, count 0 2006.161.07:34:44.30#ibcon#flushed, iclass 18, count 0 2006.161.07:34:44.30#ibcon#about to write, iclass 18, count 0 2006.161.07:34:44.30#ibcon#wrote, iclass 18, count 0 2006.161.07:34:44.30#ibcon#about to read 3, iclass 18, count 0 2006.161.07:34:44.32#ibcon#read 3, iclass 18, count 0 2006.161.07:34:44.32#ibcon#about to read 4, iclass 18, count 0 2006.161.07:34:44.32#ibcon#read 4, iclass 18, count 0 2006.161.07:34:44.32#ibcon#about to read 5, iclass 18, count 0 2006.161.07:34:44.32#ibcon#read 5, iclass 18, count 0 2006.161.07:34:44.32#ibcon#about to read 6, iclass 18, count 0 2006.161.07:34:44.32#ibcon#read 6, iclass 18, count 0 2006.161.07:34:44.32#ibcon#end of sib2, iclass 18, count 0 2006.161.07:34:44.32#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:34:44.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:34:44.32#ibcon#[25=BW32\r\n] 2006.161.07:34:44.32#ibcon#*before write, iclass 18, count 0 2006.161.07:34:44.32#ibcon#enter sib2, iclass 18, count 0 2006.161.07:34:44.32#ibcon#flushed, iclass 18, count 0 2006.161.07:34:44.32#ibcon#about to write, iclass 18, count 0 2006.161.07:34:44.32#ibcon#wrote, iclass 18, count 0 2006.161.07:34:44.32#ibcon#about to read 3, iclass 18, count 0 2006.161.07:34:44.35#ibcon#read 3, iclass 18, count 0 2006.161.07:34:44.35#ibcon#about to read 4, iclass 18, count 0 2006.161.07:34:44.35#ibcon#read 4, iclass 18, count 0 2006.161.07:34:44.35#ibcon#about to read 5, iclass 18, count 0 2006.161.07:34:44.35#ibcon#read 5, iclass 18, count 0 2006.161.07:34:44.35#ibcon#about to read 6, iclass 18, count 0 2006.161.07:34:44.35#ibcon#read 6, iclass 18, count 0 2006.161.07:34:44.35#ibcon#end of sib2, iclass 18, count 0 2006.161.07:34:44.35#ibcon#*after write, iclass 18, count 0 2006.161.07:34:44.35#ibcon#*before return 0, iclass 18, count 0 2006.161.07:34:44.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:44.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:34:44.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:34:44.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:34:44.35$vc4f8/vbbw=wide 2006.161.07:34:44.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:34:44.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:34:44.35#ibcon#ireg 8 cls_cnt 0 2006.161.07:34:44.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:34:44.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:34:44.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:34:44.42#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:34:44.42#ibcon#first serial, iclass 20, count 0 2006.161.07:34:44.42#ibcon#enter sib2, iclass 20, count 0 2006.161.07:34:44.42#ibcon#flushed, iclass 20, count 0 2006.161.07:34:44.42#ibcon#about to write, iclass 20, count 0 2006.161.07:34:44.42#ibcon#wrote, iclass 20, count 0 2006.161.07:34:44.42#ibcon#about to read 3, iclass 20, count 0 2006.161.07:34:44.44#ibcon#read 3, iclass 20, count 0 2006.161.07:34:44.44#ibcon#about to read 4, iclass 20, count 0 2006.161.07:34:44.44#ibcon#read 4, iclass 20, count 0 2006.161.07:34:44.44#ibcon#about to read 5, iclass 20, count 0 2006.161.07:34:44.44#ibcon#read 5, iclass 20, count 0 2006.161.07:34:44.44#ibcon#about to read 6, iclass 20, count 0 2006.161.07:34:44.44#ibcon#read 6, iclass 20, count 0 2006.161.07:34:44.44#ibcon#end of sib2, iclass 20, count 0 2006.161.07:34:44.44#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:34:44.44#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:34:44.44#ibcon#[27=BW32\r\n] 2006.161.07:34:44.44#ibcon#*before write, iclass 20, count 0 2006.161.07:34:44.44#ibcon#enter sib2, iclass 20, count 0 2006.161.07:34:44.44#ibcon#flushed, iclass 20, count 0 2006.161.07:34:44.44#ibcon#about to write, iclass 20, count 0 2006.161.07:34:44.44#ibcon#wrote, iclass 20, count 0 2006.161.07:34:44.44#ibcon#about to read 3, iclass 20, count 0 2006.161.07:34:44.47#ibcon#read 3, iclass 20, count 0 2006.161.07:34:44.47#ibcon#about to read 4, iclass 20, count 0 2006.161.07:34:44.47#ibcon#read 4, iclass 20, count 0 2006.161.07:34:44.47#ibcon#about to read 5, iclass 20, count 0 2006.161.07:34:44.47#ibcon#read 5, iclass 20, count 0 2006.161.07:34:44.47#ibcon#about to read 6, iclass 20, count 0 2006.161.07:34:44.47#ibcon#read 6, iclass 20, count 0 2006.161.07:34:44.47#ibcon#end of sib2, iclass 20, count 0 2006.161.07:34:44.47#ibcon#*after write, iclass 20, count 0 2006.161.07:34:44.47#ibcon#*before return 0, iclass 20, count 0 2006.161.07:34:44.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:34:44.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:34:44.47#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:34:44.47#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:34:44.47$4f8m12a/ifd4f 2006.161.07:34:44.47$ifd4f/lo= 2006.161.07:34:44.47$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:34:44.47$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:34:44.47$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:34:44.47$ifd4f/patch= 2006.161.07:34:44.47$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:34:44.47$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:34:44.47$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:34:44.47$4f8m12a/"form=m,16.000,1:2 2006.161.07:34:44.47$4f8m12a/"tpicd 2006.161.07:34:44.47$4f8m12a/echo=off 2006.161.07:34:44.47$4f8m12a/xlog=off 2006.161.07:34:44.47:!2006.161.07:35:20 2006.161.07:35:00.14#trakl#Source acquired 2006.161.07:35:00.14#flagr#flagr/antenna,acquired 2006.161.07:35:20.00:preob 2006.161.07:35:20.14/onsource/TRACKING 2006.161.07:35:20.14:!2006.161.07:35:30 2006.161.07:35:30.00:data_valid=on 2006.161.07:35:30.00:midob 2006.161.07:35:30.14/onsource/TRACKING 2006.161.07:35:30.14/wx/24.16,1002.0,84 2006.161.07:35:30.24/cable/+6.4979E-03 2006.161.07:35:31.33/va/01,08,usb,yes,35,37 2006.161.07:35:31.33/va/02,07,usb,yes,36,37 2006.161.07:35:31.33/va/03,06,usb,yes,37,38 2006.161.07:35:31.33/va/04,07,usb,yes,36,39 2006.161.07:35:31.33/va/05,07,usb,yes,36,39 2006.161.07:35:31.33/va/06,06,usb,yes,36,35 2006.161.07:35:31.33/va/07,06,usb,yes,36,36 2006.161.07:35:31.33/va/08,07,usb,yes,34,34 2006.161.07:35:31.56/valo/01,532.99,yes,locked 2006.161.07:35:31.56/valo/02,572.99,yes,locked 2006.161.07:35:31.56/valo/03,672.99,yes,locked 2006.161.07:35:31.56/valo/04,832.99,yes,locked 2006.161.07:35:31.56/valo/05,652.99,yes,locked 2006.161.07:35:31.56/valo/06,772.99,yes,locked 2006.161.07:35:31.56/valo/07,832.99,yes,locked 2006.161.07:35:31.56/valo/08,852.99,yes,locked 2006.161.07:35:32.65/vb/01,04,usb,yes,30,29 2006.161.07:35:32.65/vb/02,04,usb,yes,32,34 2006.161.07:35:32.65/vb/03,04,usb,yes,28,32 2006.161.07:35:32.65/vb/04,04,usb,yes,29,29 2006.161.07:35:32.65/vb/05,04,usb,yes,28,32 2006.161.07:35:32.65/vb/06,04,usb,yes,29,31 2006.161.07:35:32.65/vb/07,04,usb,yes,31,30 2006.161.07:35:32.65/vb/08,04,usb,yes,28,31 2006.161.07:35:32.89/vblo/01,632.99,yes,locked 2006.161.07:35:32.89/vblo/02,640.99,yes,locked 2006.161.07:35:32.89/vblo/03,656.99,yes,locked 2006.161.07:35:32.89/vblo/04,712.99,yes,locked 2006.161.07:35:32.89/vblo/05,744.99,yes,locked 2006.161.07:35:32.89/vblo/06,752.99,yes,locked 2006.161.07:35:32.89/vblo/07,734.99,yes,locked 2006.161.07:35:32.89/vblo/08,744.99,yes,locked 2006.161.07:35:33.04/vabw/8 2006.161.07:35:33.19/vbbw/8 2006.161.07:35:33.28/xfe/off,on,14.5 2006.161.07:35:33.67/ifatt/23,28,28,28 2006.161.07:35:34.08/fmout-gps/S +4.47E-07 2006.161.07:35:34.12:!2006.161.07:37:10 2006.161.07:37:10.01:data_valid=off 2006.161.07:37:10.02:postob 2006.161.07:37:10.13/cable/+6.4999E-03 2006.161.07:37:10.14/wx/24.15,1001.9,85 2006.161.07:37:11.08/fmout-gps/S +4.47E-07 2006.161.07:37:11.09:scan_name=161-0738,k06161,60 2006.161.07:37:11.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.161.07:37:12.14#flagr#flagr/antenna,new-source 2006.161.07:37:12.15:checkk5 2006.161.07:37:12.57/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:37:12.96/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:37:13.41/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:37:13.79/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:37:14.17/chk_obsdata//k5ts1/T1610735??a.dat file size is correct (nominal:800MB, actual:792MB). 2006.161.07:37:14.59/chk_obsdata//k5ts2/T1610735??b.dat file size is correct (nominal:800MB, actual:792MB). 2006.161.07:37:15.02/chk_obsdata//k5ts3/T1610735??c.dat file size is correct (nominal:800MB, actual:792MB). 2006.161.07:37:15.44/chk_obsdata//k5ts4/T1610735??d.dat file size is correct (nominal:800MB, actual:792MB). 2006.161.07:37:16.23/k5log//k5ts1_log_newline 2006.161.07:37:17.04/k5log//k5ts2_log_newline 2006.161.07:37:17.81/k5log//k5ts3_log_newline 2006.161.07:37:18.56/k5log//k5ts4_log_newline 2006.161.07:37:18.58/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:37:18.58:4f8m12a=1 2006.161.07:37:18.58$4f8m12a/echo=on 2006.161.07:37:18.58$4f8m12a/pcalon 2006.161.07:37:18.58$pcalon/"no phase cal control is implemented here 2006.161.07:37:18.58$4f8m12a/"tpicd=stop 2006.161.07:37:18.58$4f8m12a/vc4f8 2006.161.07:37:18.58$vc4f8/valo=1,532.99 2006.161.07:37:18.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:37:18.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:37:18.58#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:18.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:18.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:18.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:18.58#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:37:18.59#ibcon#first serial, iclass 11, count 0 2006.161.07:37:18.59#ibcon#enter sib2, iclass 11, count 0 2006.161.07:37:18.59#ibcon#flushed, iclass 11, count 0 2006.161.07:37:18.59#ibcon#about to write, iclass 11, count 0 2006.161.07:37:18.59#ibcon#wrote, iclass 11, count 0 2006.161.07:37:18.59#ibcon#about to read 3, iclass 11, count 0 2006.161.07:37:18.63#ibcon#read 3, iclass 11, count 0 2006.161.07:37:18.63#ibcon#about to read 4, iclass 11, count 0 2006.161.07:37:18.63#ibcon#read 4, iclass 11, count 0 2006.161.07:37:18.63#ibcon#about to read 5, iclass 11, count 0 2006.161.07:37:18.63#ibcon#read 5, iclass 11, count 0 2006.161.07:37:18.63#ibcon#about to read 6, iclass 11, count 0 2006.161.07:37:18.63#ibcon#read 6, iclass 11, count 0 2006.161.07:37:18.63#ibcon#end of sib2, iclass 11, count 0 2006.161.07:37:18.63#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:37:18.63#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:37:18.63#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:37:18.63#ibcon#*before write, iclass 11, count 0 2006.161.07:37:18.63#ibcon#enter sib2, iclass 11, count 0 2006.161.07:37:18.63#ibcon#flushed, iclass 11, count 0 2006.161.07:37:18.63#ibcon#about to write, iclass 11, count 0 2006.161.07:37:18.63#ibcon#wrote, iclass 11, count 0 2006.161.07:37:18.63#ibcon#about to read 3, iclass 11, count 0 2006.161.07:37:18.67#ibcon#read 3, iclass 11, count 0 2006.161.07:37:18.67#ibcon#about to read 4, iclass 11, count 0 2006.161.07:37:18.67#ibcon#read 4, iclass 11, count 0 2006.161.07:37:18.67#ibcon#about to read 5, iclass 11, count 0 2006.161.07:37:18.67#ibcon#read 5, iclass 11, count 0 2006.161.07:37:18.67#ibcon#about to read 6, iclass 11, count 0 2006.161.07:37:18.67#ibcon#read 6, iclass 11, count 0 2006.161.07:37:18.67#ibcon#end of sib2, iclass 11, count 0 2006.161.07:37:18.67#ibcon#*after write, iclass 11, count 0 2006.161.07:37:18.67#ibcon#*before return 0, iclass 11, count 0 2006.161.07:37:18.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:18.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:18.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:37:18.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:37:18.67$vc4f8/va=1,8 2006.161.07:37:18.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:37:18.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:37:18.67#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:18.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:18.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:18.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:18.67#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:37:18.67#ibcon#first serial, iclass 13, count 2 2006.161.07:37:18.67#ibcon#enter sib2, iclass 13, count 2 2006.161.07:37:18.67#ibcon#flushed, iclass 13, count 2 2006.161.07:37:18.67#ibcon#about to write, iclass 13, count 2 2006.161.07:37:18.67#ibcon#wrote, iclass 13, count 2 2006.161.07:37:18.67#ibcon#about to read 3, iclass 13, count 2 2006.161.07:37:18.69#ibcon#read 3, iclass 13, count 2 2006.161.07:37:18.69#ibcon#about to read 4, iclass 13, count 2 2006.161.07:37:18.69#ibcon#read 4, iclass 13, count 2 2006.161.07:37:18.69#ibcon#about to read 5, iclass 13, count 2 2006.161.07:37:18.69#ibcon#read 5, iclass 13, count 2 2006.161.07:37:18.69#ibcon#about to read 6, iclass 13, count 2 2006.161.07:37:18.69#ibcon#read 6, iclass 13, count 2 2006.161.07:37:18.69#ibcon#end of sib2, iclass 13, count 2 2006.161.07:37:18.69#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:37:18.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:37:18.69#ibcon#[25=AT01-08\r\n] 2006.161.07:37:18.69#ibcon#*before write, iclass 13, count 2 2006.161.07:37:18.69#ibcon#enter sib2, iclass 13, count 2 2006.161.07:37:18.69#ibcon#flushed, iclass 13, count 2 2006.161.07:37:18.69#ibcon#about to write, iclass 13, count 2 2006.161.07:37:18.69#ibcon#wrote, iclass 13, count 2 2006.161.07:37:18.69#ibcon#about to read 3, iclass 13, count 2 2006.161.07:37:18.72#ibcon#read 3, iclass 13, count 2 2006.161.07:37:18.72#ibcon#about to read 4, iclass 13, count 2 2006.161.07:37:18.72#ibcon#read 4, iclass 13, count 2 2006.161.07:37:18.72#ibcon#about to read 5, iclass 13, count 2 2006.161.07:37:18.72#ibcon#read 5, iclass 13, count 2 2006.161.07:37:18.72#ibcon#about to read 6, iclass 13, count 2 2006.161.07:37:18.72#ibcon#read 6, iclass 13, count 2 2006.161.07:37:18.72#ibcon#end of sib2, iclass 13, count 2 2006.161.07:37:18.72#ibcon#*after write, iclass 13, count 2 2006.161.07:37:18.72#ibcon#*before return 0, iclass 13, count 2 2006.161.07:37:18.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:18.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:18.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:37:18.72#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:18.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:18.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:18.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:18.84#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:37:18.84#ibcon#first serial, iclass 13, count 0 2006.161.07:37:18.84#ibcon#enter sib2, iclass 13, count 0 2006.161.07:37:18.84#ibcon#flushed, iclass 13, count 0 2006.161.07:37:18.84#ibcon#about to write, iclass 13, count 0 2006.161.07:37:18.84#ibcon#wrote, iclass 13, count 0 2006.161.07:37:18.84#ibcon#about to read 3, iclass 13, count 0 2006.161.07:37:18.86#ibcon#read 3, iclass 13, count 0 2006.161.07:37:18.86#ibcon#about to read 4, iclass 13, count 0 2006.161.07:37:18.86#ibcon#read 4, iclass 13, count 0 2006.161.07:37:18.86#ibcon#about to read 5, iclass 13, count 0 2006.161.07:37:18.86#ibcon#read 5, iclass 13, count 0 2006.161.07:37:18.86#ibcon#about to read 6, iclass 13, count 0 2006.161.07:37:18.86#ibcon#read 6, iclass 13, count 0 2006.161.07:37:18.86#ibcon#end of sib2, iclass 13, count 0 2006.161.07:37:18.86#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:37:18.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:37:18.86#ibcon#[25=USB\r\n] 2006.161.07:37:18.86#ibcon#*before write, iclass 13, count 0 2006.161.07:37:18.86#ibcon#enter sib2, iclass 13, count 0 2006.161.07:37:18.86#ibcon#flushed, iclass 13, count 0 2006.161.07:37:18.86#ibcon#about to write, iclass 13, count 0 2006.161.07:37:18.86#ibcon#wrote, iclass 13, count 0 2006.161.07:37:18.86#ibcon#about to read 3, iclass 13, count 0 2006.161.07:37:18.89#ibcon#read 3, iclass 13, count 0 2006.161.07:37:18.89#ibcon#about to read 4, iclass 13, count 0 2006.161.07:37:18.89#ibcon#read 4, iclass 13, count 0 2006.161.07:37:18.89#ibcon#about to read 5, iclass 13, count 0 2006.161.07:37:18.89#ibcon#read 5, iclass 13, count 0 2006.161.07:37:18.89#ibcon#about to read 6, iclass 13, count 0 2006.161.07:37:18.89#ibcon#read 6, iclass 13, count 0 2006.161.07:37:18.89#ibcon#end of sib2, iclass 13, count 0 2006.161.07:37:18.89#ibcon#*after write, iclass 13, count 0 2006.161.07:37:18.89#ibcon#*before return 0, iclass 13, count 0 2006.161.07:37:18.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:18.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:18.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:37:18.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:37:18.89$vc4f8/valo=2,572.99 2006.161.07:37:18.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.07:37:18.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.07:37:18.89#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:18.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:18.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:18.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:18.89#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:37:18.89#ibcon#first serial, iclass 15, count 0 2006.161.07:37:18.89#ibcon#enter sib2, iclass 15, count 0 2006.161.07:37:18.89#ibcon#flushed, iclass 15, count 0 2006.161.07:37:18.89#ibcon#about to write, iclass 15, count 0 2006.161.07:37:18.89#ibcon#wrote, iclass 15, count 0 2006.161.07:37:18.89#ibcon#about to read 3, iclass 15, count 0 2006.161.07:37:18.91#ibcon#read 3, iclass 15, count 0 2006.161.07:37:18.91#ibcon#about to read 4, iclass 15, count 0 2006.161.07:37:18.91#ibcon#read 4, iclass 15, count 0 2006.161.07:37:18.91#ibcon#about to read 5, iclass 15, count 0 2006.161.07:37:18.91#ibcon#read 5, iclass 15, count 0 2006.161.07:37:18.91#ibcon#about to read 6, iclass 15, count 0 2006.161.07:37:18.91#ibcon#read 6, iclass 15, count 0 2006.161.07:37:18.91#ibcon#end of sib2, iclass 15, count 0 2006.161.07:37:18.91#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:37:18.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:37:18.91#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:37:18.91#ibcon#*before write, iclass 15, count 0 2006.161.07:37:18.91#ibcon#enter sib2, iclass 15, count 0 2006.161.07:37:18.91#ibcon#flushed, iclass 15, count 0 2006.161.07:37:18.91#ibcon#about to write, iclass 15, count 0 2006.161.07:37:18.91#ibcon#wrote, iclass 15, count 0 2006.161.07:37:18.91#ibcon#about to read 3, iclass 15, count 0 2006.161.07:37:18.95#ibcon#read 3, iclass 15, count 0 2006.161.07:37:18.95#ibcon#about to read 4, iclass 15, count 0 2006.161.07:37:18.95#ibcon#read 4, iclass 15, count 0 2006.161.07:37:18.95#ibcon#about to read 5, iclass 15, count 0 2006.161.07:37:18.95#ibcon#read 5, iclass 15, count 0 2006.161.07:37:18.95#ibcon#about to read 6, iclass 15, count 0 2006.161.07:37:18.95#ibcon#read 6, iclass 15, count 0 2006.161.07:37:18.95#ibcon#end of sib2, iclass 15, count 0 2006.161.07:37:18.95#ibcon#*after write, iclass 15, count 0 2006.161.07:37:18.95#ibcon#*before return 0, iclass 15, count 0 2006.161.07:37:18.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:18.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:18.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:37:18.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:37:18.95$vc4f8/va=2,7 2006.161.07:37:18.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.07:37:18.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.07:37:18.95#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:18.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:19.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:19.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:19.01#ibcon#enter wrdev, iclass 17, count 2 2006.161.07:37:19.01#ibcon#first serial, iclass 17, count 2 2006.161.07:37:19.01#ibcon#enter sib2, iclass 17, count 2 2006.161.07:37:19.01#ibcon#flushed, iclass 17, count 2 2006.161.07:37:19.01#ibcon#about to write, iclass 17, count 2 2006.161.07:37:19.01#ibcon#wrote, iclass 17, count 2 2006.161.07:37:19.01#ibcon#about to read 3, iclass 17, count 2 2006.161.07:37:19.03#ibcon#read 3, iclass 17, count 2 2006.161.07:37:19.03#ibcon#about to read 4, iclass 17, count 2 2006.161.07:37:19.03#ibcon#read 4, iclass 17, count 2 2006.161.07:37:19.03#ibcon#about to read 5, iclass 17, count 2 2006.161.07:37:19.03#ibcon#read 5, iclass 17, count 2 2006.161.07:37:19.03#ibcon#about to read 6, iclass 17, count 2 2006.161.07:37:19.03#ibcon#read 6, iclass 17, count 2 2006.161.07:37:19.03#ibcon#end of sib2, iclass 17, count 2 2006.161.07:37:19.03#ibcon#*mode == 0, iclass 17, count 2 2006.161.07:37:19.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.07:37:19.03#ibcon#[25=AT02-07\r\n] 2006.161.07:37:19.03#ibcon#*before write, iclass 17, count 2 2006.161.07:37:19.03#ibcon#enter sib2, iclass 17, count 2 2006.161.07:37:19.03#ibcon#flushed, iclass 17, count 2 2006.161.07:37:19.03#ibcon#about to write, iclass 17, count 2 2006.161.07:37:19.03#ibcon#wrote, iclass 17, count 2 2006.161.07:37:19.03#ibcon#about to read 3, iclass 17, count 2 2006.161.07:37:19.06#ibcon#read 3, iclass 17, count 2 2006.161.07:37:19.06#ibcon#about to read 4, iclass 17, count 2 2006.161.07:37:19.06#ibcon#read 4, iclass 17, count 2 2006.161.07:37:19.06#ibcon#about to read 5, iclass 17, count 2 2006.161.07:37:19.06#ibcon#read 5, iclass 17, count 2 2006.161.07:37:19.06#ibcon#about to read 6, iclass 17, count 2 2006.161.07:37:19.06#ibcon#read 6, iclass 17, count 2 2006.161.07:37:19.06#ibcon#end of sib2, iclass 17, count 2 2006.161.07:37:19.06#ibcon#*after write, iclass 17, count 2 2006.161.07:37:19.06#ibcon#*before return 0, iclass 17, count 2 2006.161.07:37:19.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:19.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:19.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.07:37:19.06#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:19.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:19.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:19.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:19.18#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:37:19.18#ibcon#first serial, iclass 17, count 0 2006.161.07:37:19.18#ibcon#enter sib2, iclass 17, count 0 2006.161.07:37:19.18#ibcon#flushed, iclass 17, count 0 2006.161.07:37:19.18#ibcon#about to write, iclass 17, count 0 2006.161.07:37:19.18#ibcon#wrote, iclass 17, count 0 2006.161.07:37:19.18#ibcon#about to read 3, iclass 17, count 0 2006.161.07:37:19.20#ibcon#read 3, iclass 17, count 0 2006.161.07:37:19.20#ibcon#about to read 4, iclass 17, count 0 2006.161.07:37:19.20#ibcon#read 4, iclass 17, count 0 2006.161.07:37:19.20#ibcon#about to read 5, iclass 17, count 0 2006.161.07:37:19.20#ibcon#read 5, iclass 17, count 0 2006.161.07:37:19.20#ibcon#about to read 6, iclass 17, count 0 2006.161.07:37:19.20#ibcon#read 6, iclass 17, count 0 2006.161.07:37:19.20#ibcon#end of sib2, iclass 17, count 0 2006.161.07:37:19.20#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:37:19.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:37:19.20#ibcon#[25=USB\r\n] 2006.161.07:37:19.20#ibcon#*before write, iclass 17, count 0 2006.161.07:37:19.20#ibcon#enter sib2, iclass 17, count 0 2006.161.07:37:19.20#ibcon#flushed, iclass 17, count 0 2006.161.07:37:19.20#ibcon#about to write, iclass 17, count 0 2006.161.07:37:19.20#ibcon#wrote, iclass 17, count 0 2006.161.07:37:19.20#ibcon#about to read 3, iclass 17, count 0 2006.161.07:37:19.23#ibcon#read 3, iclass 17, count 0 2006.161.07:37:19.23#ibcon#about to read 4, iclass 17, count 0 2006.161.07:37:19.23#ibcon#read 4, iclass 17, count 0 2006.161.07:37:19.23#ibcon#about to read 5, iclass 17, count 0 2006.161.07:37:19.23#ibcon#read 5, iclass 17, count 0 2006.161.07:37:19.23#ibcon#about to read 6, iclass 17, count 0 2006.161.07:37:19.23#ibcon#read 6, iclass 17, count 0 2006.161.07:37:19.23#ibcon#end of sib2, iclass 17, count 0 2006.161.07:37:19.23#ibcon#*after write, iclass 17, count 0 2006.161.07:37:19.23#ibcon#*before return 0, iclass 17, count 0 2006.161.07:37:19.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:19.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:19.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:37:19.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:37:19.23$vc4f8/valo=3,672.99 2006.161.07:37:19.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:37:19.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:37:19.23#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:19.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:19.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:19.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:19.23#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:37:19.23#ibcon#first serial, iclass 19, count 0 2006.161.07:37:19.23#ibcon#enter sib2, iclass 19, count 0 2006.161.07:37:19.23#ibcon#flushed, iclass 19, count 0 2006.161.07:37:19.23#ibcon#about to write, iclass 19, count 0 2006.161.07:37:19.23#ibcon#wrote, iclass 19, count 0 2006.161.07:37:19.23#ibcon#about to read 3, iclass 19, count 0 2006.161.07:37:19.25#ibcon#read 3, iclass 19, count 0 2006.161.07:37:19.25#ibcon#about to read 4, iclass 19, count 0 2006.161.07:37:19.25#ibcon#read 4, iclass 19, count 0 2006.161.07:37:19.25#ibcon#about to read 5, iclass 19, count 0 2006.161.07:37:19.25#ibcon#read 5, iclass 19, count 0 2006.161.07:37:19.25#ibcon#about to read 6, iclass 19, count 0 2006.161.07:37:19.25#ibcon#read 6, iclass 19, count 0 2006.161.07:37:19.25#ibcon#end of sib2, iclass 19, count 0 2006.161.07:37:19.25#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:37:19.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:37:19.25#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:37:19.25#ibcon#*before write, iclass 19, count 0 2006.161.07:37:19.25#ibcon#enter sib2, iclass 19, count 0 2006.161.07:37:19.25#ibcon#flushed, iclass 19, count 0 2006.161.07:37:19.25#ibcon#about to write, iclass 19, count 0 2006.161.07:37:19.25#ibcon#wrote, iclass 19, count 0 2006.161.07:37:19.25#ibcon#about to read 3, iclass 19, count 0 2006.161.07:37:19.29#ibcon#read 3, iclass 19, count 0 2006.161.07:37:19.29#ibcon#about to read 4, iclass 19, count 0 2006.161.07:37:19.29#ibcon#read 4, iclass 19, count 0 2006.161.07:37:19.29#ibcon#about to read 5, iclass 19, count 0 2006.161.07:37:19.29#ibcon#read 5, iclass 19, count 0 2006.161.07:37:19.29#ibcon#about to read 6, iclass 19, count 0 2006.161.07:37:19.29#ibcon#read 6, iclass 19, count 0 2006.161.07:37:19.29#ibcon#end of sib2, iclass 19, count 0 2006.161.07:37:19.29#ibcon#*after write, iclass 19, count 0 2006.161.07:37:19.29#ibcon#*before return 0, iclass 19, count 0 2006.161.07:37:19.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:19.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:19.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:37:19.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:37:19.29$vc4f8/va=3,6 2006.161.07:37:19.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:37:19.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:37:19.29#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:19.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:19.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:19.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:19.35#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:37:19.35#ibcon#first serial, iclass 21, count 2 2006.161.07:37:19.35#ibcon#enter sib2, iclass 21, count 2 2006.161.07:37:19.35#ibcon#flushed, iclass 21, count 2 2006.161.07:37:19.35#ibcon#about to write, iclass 21, count 2 2006.161.07:37:19.35#ibcon#wrote, iclass 21, count 2 2006.161.07:37:19.35#ibcon#about to read 3, iclass 21, count 2 2006.161.07:37:19.37#ibcon#read 3, iclass 21, count 2 2006.161.07:37:19.37#ibcon#about to read 4, iclass 21, count 2 2006.161.07:37:19.37#ibcon#read 4, iclass 21, count 2 2006.161.07:37:19.37#ibcon#about to read 5, iclass 21, count 2 2006.161.07:37:19.37#ibcon#read 5, iclass 21, count 2 2006.161.07:37:19.37#ibcon#about to read 6, iclass 21, count 2 2006.161.07:37:19.37#ibcon#read 6, iclass 21, count 2 2006.161.07:37:19.37#ibcon#end of sib2, iclass 21, count 2 2006.161.07:37:19.37#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:37:19.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:37:19.37#ibcon#[25=AT03-06\r\n] 2006.161.07:37:19.37#ibcon#*before write, iclass 21, count 2 2006.161.07:37:19.37#ibcon#enter sib2, iclass 21, count 2 2006.161.07:37:19.37#ibcon#flushed, iclass 21, count 2 2006.161.07:37:19.37#ibcon#about to write, iclass 21, count 2 2006.161.07:37:19.37#ibcon#wrote, iclass 21, count 2 2006.161.07:37:19.37#ibcon#about to read 3, iclass 21, count 2 2006.161.07:37:19.40#ibcon#read 3, iclass 21, count 2 2006.161.07:37:19.40#ibcon#about to read 4, iclass 21, count 2 2006.161.07:37:19.40#ibcon#read 4, iclass 21, count 2 2006.161.07:37:19.40#ibcon#about to read 5, iclass 21, count 2 2006.161.07:37:19.40#ibcon#read 5, iclass 21, count 2 2006.161.07:37:19.40#ibcon#about to read 6, iclass 21, count 2 2006.161.07:37:19.40#ibcon#read 6, iclass 21, count 2 2006.161.07:37:19.40#ibcon#end of sib2, iclass 21, count 2 2006.161.07:37:19.40#ibcon#*after write, iclass 21, count 2 2006.161.07:37:19.40#ibcon#*before return 0, iclass 21, count 2 2006.161.07:37:19.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:19.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:19.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:37:19.40#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:19.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:19.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:19.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:19.52#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:37:19.52#ibcon#first serial, iclass 21, count 0 2006.161.07:37:19.52#ibcon#enter sib2, iclass 21, count 0 2006.161.07:37:19.52#ibcon#flushed, iclass 21, count 0 2006.161.07:37:19.52#ibcon#about to write, iclass 21, count 0 2006.161.07:37:19.52#ibcon#wrote, iclass 21, count 0 2006.161.07:37:19.52#ibcon#about to read 3, iclass 21, count 0 2006.161.07:37:19.54#ibcon#read 3, iclass 21, count 0 2006.161.07:37:19.54#ibcon#about to read 4, iclass 21, count 0 2006.161.07:37:19.54#ibcon#read 4, iclass 21, count 0 2006.161.07:37:19.54#ibcon#about to read 5, iclass 21, count 0 2006.161.07:37:19.54#ibcon#read 5, iclass 21, count 0 2006.161.07:37:19.54#ibcon#about to read 6, iclass 21, count 0 2006.161.07:37:19.54#ibcon#read 6, iclass 21, count 0 2006.161.07:37:19.54#ibcon#end of sib2, iclass 21, count 0 2006.161.07:37:19.54#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:37:19.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:37:19.54#ibcon#[25=USB\r\n] 2006.161.07:37:19.54#ibcon#*before write, iclass 21, count 0 2006.161.07:37:19.54#ibcon#enter sib2, iclass 21, count 0 2006.161.07:37:19.54#ibcon#flushed, iclass 21, count 0 2006.161.07:37:19.54#ibcon#about to write, iclass 21, count 0 2006.161.07:37:19.54#ibcon#wrote, iclass 21, count 0 2006.161.07:37:19.54#ibcon#about to read 3, iclass 21, count 0 2006.161.07:37:19.57#ibcon#read 3, iclass 21, count 0 2006.161.07:37:19.57#ibcon#about to read 4, iclass 21, count 0 2006.161.07:37:19.57#ibcon#read 4, iclass 21, count 0 2006.161.07:37:19.57#ibcon#about to read 5, iclass 21, count 0 2006.161.07:37:19.57#ibcon#read 5, iclass 21, count 0 2006.161.07:37:19.57#ibcon#about to read 6, iclass 21, count 0 2006.161.07:37:19.57#ibcon#read 6, iclass 21, count 0 2006.161.07:37:19.57#ibcon#end of sib2, iclass 21, count 0 2006.161.07:37:19.57#ibcon#*after write, iclass 21, count 0 2006.161.07:37:19.57#ibcon#*before return 0, iclass 21, count 0 2006.161.07:37:19.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:19.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:19.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:37:19.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:37:19.57$vc4f8/valo=4,832.99 2006.161.07:37:19.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:37:19.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:37:19.57#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:19.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:19.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:19.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:19.57#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:37:19.57#ibcon#first serial, iclass 23, count 0 2006.161.07:37:19.57#ibcon#enter sib2, iclass 23, count 0 2006.161.07:37:19.57#ibcon#flushed, iclass 23, count 0 2006.161.07:37:19.57#ibcon#about to write, iclass 23, count 0 2006.161.07:37:19.57#ibcon#wrote, iclass 23, count 0 2006.161.07:37:19.57#ibcon#about to read 3, iclass 23, count 0 2006.161.07:37:19.59#ibcon#read 3, iclass 23, count 0 2006.161.07:37:19.59#ibcon#about to read 4, iclass 23, count 0 2006.161.07:37:19.59#ibcon#read 4, iclass 23, count 0 2006.161.07:37:19.59#ibcon#about to read 5, iclass 23, count 0 2006.161.07:37:19.59#ibcon#read 5, iclass 23, count 0 2006.161.07:37:19.59#ibcon#about to read 6, iclass 23, count 0 2006.161.07:37:19.59#ibcon#read 6, iclass 23, count 0 2006.161.07:37:19.59#ibcon#end of sib2, iclass 23, count 0 2006.161.07:37:19.59#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:37:19.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:37:19.59#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:37:19.59#ibcon#*before write, iclass 23, count 0 2006.161.07:37:19.59#ibcon#enter sib2, iclass 23, count 0 2006.161.07:37:19.59#ibcon#flushed, iclass 23, count 0 2006.161.07:37:19.59#ibcon#about to write, iclass 23, count 0 2006.161.07:37:19.59#ibcon#wrote, iclass 23, count 0 2006.161.07:37:19.59#ibcon#about to read 3, iclass 23, count 0 2006.161.07:37:19.63#ibcon#read 3, iclass 23, count 0 2006.161.07:37:19.63#ibcon#about to read 4, iclass 23, count 0 2006.161.07:37:19.63#ibcon#read 4, iclass 23, count 0 2006.161.07:37:19.63#ibcon#about to read 5, iclass 23, count 0 2006.161.07:37:19.63#ibcon#read 5, iclass 23, count 0 2006.161.07:37:19.63#ibcon#about to read 6, iclass 23, count 0 2006.161.07:37:19.63#ibcon#read 6, iclass 23, count 0 2006.161.07:37:19.63#ibcon#end of sib2, iclass 23, count 0 2006.161.07:37:19.63#ibcon#*after write, iclass 23, count 0 2006.161.07:37:19.63#ibcon#*before return 0, iclass 23, count 0 2006.161.07:37:19.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:19.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:19.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:37:19.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:37:19.63$vc4f8/va=4,7 2006.161.07:37:19.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:37:19.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:37:19.63#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:19.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:19.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:19.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:19.69#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:37:19.69#ibcon#first serial, iclass 25, count 2 2006.161.07:37:19.69#ibcon#enter sib2, iclass 25, count 2 2006.161.07:37:19.69#ibcon#flushed, iclass 25, count 2 2006.161.07:37:19.69#ibcon#about to write, iclass 25, count 2 2006.161.07:37:19.69#ibcon#wrote, iclass 25, count 2 2006.161.07:37:19.69#ibcon#about to read 3, iclass 25, count 2 2006.161.07:37:19.71#ibcon#read 3, iclass 25, count 2 2006.161.07:37:19.71#ibcon#about to read 4, iclass 25, count 2 2006.161.07:37:19.71#ibcon#read 4, iclass 25, count 2 2006.161.07:37:19.71#ibcon#about to read 5, iclass 25, count 2 2006.161.07:37:19.71#ibcon#read 5, iclass 25, count 2 2006.161.07:37:19.71#ibcon#about to read 6, iclass 25, count 2 2006.161.07:37:19.71#ibcon#read 6, iclass 25, count 2 2006.161.07:37:19.71#ibcon#end of sib2, iclass 25, count 2 2006.161.07:37:19.71#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:37:19.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:37:19.71#ibcon#[25=AT04-07\r\n] 2006.161.07:37:19.71#ibcon#*before write, iclass 25, count 2 2006.161.07:37:19.71#ibcon#enter sib2, iclass 25, count 2 2006.161.07:37:19.71#ibcon#flushed, iclass 25, count 2 2006.161.07:37:19.71#ibcon#about to write, iclass 25, count 2 2006.161.07:37:19.71#ibcon#wrote, iclass 25, count 2 2006.161.07:37:19.71#ibcon#about to read 3, iclass 25, count 2 2006.161.07:37:19.74#ibcon#read 3, iclass 25, count 2 2006.161.07:37:19.74#ibcon#about to read 4, iclass 25, count 2 2006.161.07:37:19.74#ibcon#read 4, iclass 25, count 2 2006.161.07:37:19.74#ibcon#about to read 5, iclass 25, count 2 2006.161.07:37:19.74#ibcon#read 5, iclass 25, count 2 2006.161.07:37:19.74#ibcon#about to read 6, iclass 25, count 2 2006.161.07:37:19.74#ibcon#read 6, iclass 25, count 2 2006.161.07:37:19.74#ibcon#end of sib2, iclass 25, count 2 2006.161.07:37:19.74#ibcon#*after write, iclass 25, count 2 2006.161.07:37:19.74#ibcon#*before return 0, iclass 25, count 2 2006.161.07:37:19.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:19.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:19.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:37:19.74#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:19.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:19.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:19.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:19.86#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:37:19.86#ibcon#first serial, iclass 25, count 0 2006.161.07:37:19.86#ibcon#enter sib2, iclass 25, count 0 2006.161.07:37:19.86#ibcon#flushed, iclass 25, count 0 2006.161.07:37:19.86#ibcon#about to write, iclass 25, count 0 2006.161.07:37:19.86#ibcon#wrote, iclass 25, count 0 2006.161.07:37:19.86#ibcon#about to read 3, iclass 25, count 0 2006.161.07:37:19.88#ibcon#read 3, iclass 25, count 0 2006.161.07:37:19.88#ibcon#about to read 4, iclass 25, count 0 2006.161.07:37:19.88#ibcon#read 4, iclass 25, count 0 2006.161.07:37:19.88#ibcon#about to read 5, iclass 25, count 0 2006.161.07:37:19.88#ibcon#read 5, iclass 25, count 0 2006.161.07:37:19.88#ibcon#about to read 6, iclass 25, count 0 2006.161.07:37:19.88#ibcon#read 6, iclass 25, count 0 2006.161.07:37:19.88#ibcon#end of sib2, iclass 25, count 0 2006.161.07:37:19.88#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:37:19.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:37:19.88#ibcon#[25=USB\r\n] 2006.161.07:37:19.88#ibcon#*before write, iclass 25, count 0 2006.161.07:37:19.88#ibcon#enter sib2, iclass 25, count 0 2006.161.07:37:19.88#ibcon#flushed, iclass 25, count 0 2006.161.07:37:19.88#ibcon#about to write, iclass 25, count 0 2006.161.07:37:19.88#ibcon#wrote, iclass 25, count 0 2006.161.07:37:19.88#ibcon#about to read 3, iclass 25, count 0 2006.161.07:37:19.91#ibcon#read 3, iclass 25, count 0 2006.161.07:37:19.91#ibcon#about to read 4, iclass 25, count 0 2006.161.07:37:19.91#ibcon#read 4, iclass 25, count 0 2006.161.07:37:19.91#ibcon#about to read 5, iclass 25, count 0 2006.161.07:37:19.91#ibcon#read 5, iclass 25, count 0 2006.161.07:37:19.91#ibcon#about to read 6, iclass 25, count 0 2006.161.07:37:19.91#ibcon#read 6, iclass 25, count 0 2006.161.07:37:19.91#ibcon#end of sib2, iclass 25, count 0 2006.161.07:37:19.91#ibcon#*after write, iclass 25, count 0 2006.161.07:37:19.91#ibcon#*before return 0, iclass 25, count 0 2006.161.07:37:19.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:19.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:19.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:37:19.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:37:19.91$vc4f8/valo=5,652.99 2006.161.07:37:19.91#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.07:37:19.91#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.07:37:19.91#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:19.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:37:19.91#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:37:19.91#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:37:19.91#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:37:19.91#ibcon#first serial, iclass 27, count 0 2006.161.07:37:19.91#ibcon#enter sib2, iclass 27, count 0 2006.161.07:37:19.91#ibcon#flushed, iclass 27, count 0 2006.161.07:37:19.91#ibcon#about to write, iclass 27, count 0 2006.161.07:37:19.91#ibcon#wrote, iclass 27, count 0 2006.161.07:37:19.91#ibcon#about to read 3, iclass 27, count 0 2006.161.07:37:19.93#ibcon#read 3, iclass 27, count 0 2006.161.07:37:19.93#ibcon#about to read 4, iclass 27, count 0 2006.161.07:37:19.93#ibcon#read 4, iclass 27, count 0 2006.161.07:37:19.93#ibcon#about to read 5, iclass 27, count 0 2006.161.07:37:19.93#ibcon#read 5, iclass 27, count 0 2006.161.07:37:19.93#ibcon#about to read 6, iclass 27, count 0 2006.161.07:37:19.93#ibcon#read 6, iclass 27, count 0 2006.161.07:37:19.93#ibcon#end of sib2, iclass 27, count 0 2006.161.07:37:19.93#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:37:19.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:37:19.93#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:37:19.93#ibcon#*before write, iclass 27, count 0 2006.161.07:37:19.93#ibcon#enter sib2, iclass 27, count 0 2006.161.07:37:19.93#ibcon#flushed, iclass 27, count 0 2006.161.07:37:19.93#ibcon#about to write, iclass 27, count 0 2006.161.07:37:19.93#ibcon#wrote, iclass 27, count 0 2006.161.07:37:19.93#ibcon#about to read 3, iclass 27, count 0 2006.161.07:37:19.97#ibcon#read 3, iclass 27, count 0 2006.161.07:37:19.97#ibcon#about to read 4, iclass 27, count 0 2006.161.07:37:19.97#ibcon#read 4, iclass 27, count 0 2006.161.07:37:19.97#ibcon#about to read 5, iclass 27, count 0 2006.161.07:37:19.97#ibcon#read 5, iclass 27, count 0 2006.161.07:37:19.97#ibcon#about to read 6, iclass 27, count 0 2006.161.07:37:19.97#ibcon#read 6, iclass 27, count 0 2006.161.07:37:19.97#ibcon#end of sib2, iclass 27, count 0 2006.161.07:37:19.97#ibcon#*after write, iclass 27, count 0 2006.161.07:37:19.97#ibcon#*before return 0, iclass 27, count 0 2006.161.07:37:19.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:37:19.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:37:19.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:37:19.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:37:19.97$vc4f8/va=5,7 2006.161.07:37:19.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.07:37:19.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.07:37:19.97#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:19.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:37:20.03#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:37:20.03#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:37:20.03#ibcon#enter wrdev, iclass 29, count 2 2006.161.07:37:20.03#ibcon#first serial, iclass 29, count 2 2006.161.07:37:20.03#ibcon#enter sib2, iclass 29, count 2 2006.161.07:37:20.03#ibcon#flushed, iclass 29, count 2 2006.161.07:37:20.03#ibcon#about to write, iclass 29, count 2 2006.161.07:37:20.03#ibcon#wrote, iclass 29, count 2 2006.161.07:37:20.03#ibcon#about to read 3, iclass 29, count 2 2006.161.07:37:20.05#ibcon#read 3, iclass 29, count 2 2006.161.07:37:20.05#ibcon#about to read 4, iclass 29, count 2 2006.161.07:37:20.05#ibcon#read 4, iclass 29, count 2 2006.161.07:37:20.05#ibcon#about to read 5, iclass 29, count 2 2006.161.07:37:20.05#ibcon#read 5, iclass 29, count 2 2006.161.07:37:20.05#ibcon#about to read 6, iclass 29, count 2 2006.161.07:37:20.05#ibcon#read 6, iclass 29, count 2 2006.161.07:37:20.05#ibcon#end of sib2, iclass 29, count 2 2006.161.07:37:20.05#ibcon#*mode == 0, iclass 29, count 2 2006.161.07:37:20.05#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.07:37:20.05#ibcon#[25=AT05-07\r\n] 2006.161.07:37:20.05#ibcon#*before write, iclass 29, count 2 2006.161.07:37:20.05#ibcon#enter sib2, iclass 29, count 2 2006.161.07:37:20.05#ibcon#flushed, iclass 29, count 2 2006.161.07:37:20.05#ibcon#about to write, iclass 29, count 2 2006.161.07:37:20.05#ibcon#wrote, iclass 29, count 2 2006.161.07:37:20.05#ibcon#about to read 3, iclass 29, count 2 2006.161.07:37:20.08#ibcon#read 3, iclass 29, count 2 2006.161.07:37:20.08#ibcon#about to read 4, iclass 29, count 2 2006.161.07:37:20.08#ibcon#read 4, iclass 29, count 2 2006.161.07:37:20.08#ibcon#about to read 5, iclass 29, count 2 2006.161.07:37:20.08#ibcon#read 5, iclass 29, count 2 2006.161.07:37:20.08#ibcon#about to read 6, iclass 29, count 2 2006.161.07:37:20.08#ibcon#read 6, iclass 29, count 2 2006.161.07:37:20.08#ibcon#end of sib2, iclass 29, count 2 2006.161.07:37:20.08#ibcon#*after write, iclass 29, count 2 2006.161.07:37:20.08#ibcon#*before return 0, iclass 29, count 2 2006.161.07:37:20.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:37:20.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:37:20.08#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.07:37:20.08#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:20.08#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:37:20.20#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:37:20.20#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:37:20.20#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:37:20.20#ibcon#first serial, iclass 29, count 0 2006.161.07:37:20.20#ibcon#enter sib2, iclass 29, count 0 2006.161.07:37:20.20#ibcon#flushed, iclass 29, count 0 2006.161.07:37:20.20#ibcon#about to write, iclass 29, count 0 2006.161.07:37:20.20#ibcon#wrote, iclass 29, count 0 2006.161.07:37:20.20#ibcon#about to read 3, iclass 29, count 0 2006.161.07:37:20.22#ibcon#read 3, iclass 29, count 0 2006.161.07:37:20.22#ibcon#about to read 4, iclass 29, count 0 2006.161.07:37:20.22#ibcon#read 4, iclass 29, count 0 2006.161.07:37:20.22#ibcon#about to read 5, iclass 29, count 0 2006.161.07:37:20.22#ibcon#read 5, iclass 29, count 0 2006.161.07:37:20.22#ibcon#about to read 6, iclass 29, count 0 2006.161.07:37:20.22#ibcon#read 6, iclass 29, count 0 2006.161.07:37:20.22#ibcon#end of sib2, iclass 29, count 0 2006.161.07:37:20.22#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:37:20.22#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:37:20.22#ibcon#[25=USB\r\n] 2006.161.07:37:20.22#ibcon#*before write, iclass 29, count 0 2006.161.07:37:20.22#ibcon#enter sib2, iclass 29, count 0 2006.161.07:37:20.22#ibcon#flushed, iclass 29, count 0 2006.161.07:37:20.22#ibcon#about to write, iclass 29, count 0 2006.161.07:37:20.22#ibcon#wrote, iclass 29, count 0 2006.161.07:37:20.22#ibcon#about to read 3, iclass 29, count 0 2006.161.07:37:20.25#ibcon#read 3, iclass 29, count 0 2006.161.07:37:20.25#ibcon#about to read 4, iclass 29, count 0 2006.161.07:37:20.25#ibcon#read 4, iclass 29, count 0 2006.161.07:37:20.25#ibcon#about to read 5, iclass 29, count 0 2006.161.07:37:20.25#ibcon#read 5, iclass 29, count 0 2006.161.07:37:20.25#ibcon#about to read 6, iclass 29, count 0 2006.161.07:37:20.25#ibcon#read 6, iclass 29, count 0 2006.161.07:37:20.25#ibcon#end of sib2, iclass 29, count 0 2006.161.07:37:20.25#ibcon#*after write, iclass 29, count 0 2006.161.07:37:20.25#ibcon#*before return 0, iclass 29, count 0 2006.161.07:37:20.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:37:20.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:37:20.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:37:20.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:37:20.25$vc4f8/valo=6,772.99 2006.161.07:37:20.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.07:37:20.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.07:37:20.25#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:20.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:37:20.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:37:20.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:37:20.25#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:37:20.25#ibcon#first serial, iclass 31, count 0 2006.161.07:37:20.25#ibcon#enter sib2, iclass 31, count 0 2006.161.07:37:20.25#ibcon#flushed, iclass 31, count 0 2006.161.07:37:20.25#ibcon#about to write, iclass 31, count 0 2006.161.07:37:20.25#ibcon#wrote, iclass 31, count 0 2006.161.07:37:20.25#ibcon#about to read 3, iclass 31, count 0 2006.161.07:37:20.27#ibcon#read 3, iclass 31, count 0 2006.161.07:37:20.27#ibcon#about to read 4, iclass 31, count 0 2006.161.07:37:20.27#ibcon#read 4, iclass 31, count 0 2006.161.07:37:20.27#ibcon#about to read 5, iclass 31, count 0 2006.161.07:37:20.27#ibcon#read 5, iclass 31, count 0 2006.161.07:37:20.27#ibcon#about to read 6, iclass 31, count 0 2006.161.07:37:20.27#ibcon#read 6, iclass 31, count 0 2006.161.07:37:20.27#ibcon#end of sib2, iclass 31, count 0 2006.161.07:37:20.27#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:37:20.27#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:37:20.27#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:37:20.27#ibcon#*before write, iclass 31, count 0 2006.161.07:37:20.27#ibcon#enter sib2, iclass 31, count 0 2006.161.07:37:20.27#ibcon#flushed, iclass 31, count 0 2006.161.07:37:20.27#ibcon#about to write, iclass 31, count 0 2006.161.07:37:20.27#ibcon#wrote, iclass 31, count 0 2006.161.07:37:20.27#ibcon#about to read 3, iclass 31, count 0 2006.161.07:37:20.31#ibcon#read 3, iclass 31, count 0 2006.161.07:37:20.31#ibcon#about to read 4, iclass 31, count 0 2006.161.07:37:20.31#ibcon#read 4, iclass 31, count 0 2006.161.07:37:20.31#ibcon#about to read 5, iclass 31, count 0 2006.161.07:37:20.31#ibcon#read 5, iclass 31, count 0 2006.161.07:37:20.31#ibcon#about to read 6, iclass 31, count 0 2006.161.07:37:20.31#ibcon#read 6, iclass 31, count 0 2006.161.07:37:20.31#ibcon#end of sib2, iclass 31, count 0 2006.161.07:37:20.31#ibcon#*after write, iclass 31, count 0 2006.161.07:37:20.31#ibcon#*before return 0, iclass 31, count 0 2006.161.07:37:20.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:37:20.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:37:20.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:37:20.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:37:20.31$vc4f8/va=6,6 2006.161.07:37:20.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.07:37:20.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.07:37:20.31#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:20.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:37:20.37#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:37:20.37#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:37:20.37#ibcon#enter wrdev, iclass 33, count 2 2006.161.07:37:20.37#ibcon#first serial, iclass 33, count 2 2006.161.07:37:20.37#ibcon#enter sib2, iclass 33, count 2 2006.161.07:37:20.37#ibcon#flushed, iclass 33, count 2 2006.161.07:37:20.37#ibcon#about to write, iclass 33, count 2 2006.161.07:37:20.37#ibcon#wrote, iclass 33, count 2 2006.161.07:37:20.37#ibcon#about to read 3, iclass 33, count 2 2006.161.07:37:20.39#ibcon#read 3, iclass 33, count 2 2006.161.07:37:20.39#ibcon#about to read 4, iclass 33, count 2 2006.161.07:37:20.39#ibcon#read 4, iclass 33, count 2 2006.161.07:37:20.39#ibcon#about to read 5, iclass 33, count 2 2006.161.07:37:20.39#ibcon#read 5, iclass 33, count 2 2006.161.07:37:20.39#ibcon#about to read 6, iclass 33, count 2 2006.161.07:37:20.39#ibcon#read 6, iclass 33, count 2 2006.161.07:37:20.39#ibcon#end of sib2, iclass 33, count 2 2006.161.07:37:20.39#ibcon#*mode == 0, iclass 33, count 2 2006.161.07:37:20.39#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.07:37:20.39#ibcon#[25=AT06-06\r\n] 2006.161.07:37:20.39#ibcon#*before write, iclass 33, count 2 2006.161.07:37:20.39#ibcon#enter sib2, iclass 33, count 2 2006.161.07:37:20.39#ibcon#flushed, iclass 33, count 2 2006.161.07:37:20.39#ibcon#about to write, iclass 33, count 2 2006.161.07:37:20.39#ibcon#wrote, iclass 33, count 2 2006.161.07:37:20.39#ibcon#about to read 3, iclass 33, count 2 2006.161.07:37:20.42#ibcon#read 3, iclass 33, count 2 2006.161.07:37:20.42#ibcon#about to read 4, iclass 33, count 2 2006.161.07:37:20.42#ibcon#read 4, iclass 33, count 2 2006.161.07:37:20.42#ibcon#about to read 5, iclass 33, count 2 2006.161.07:37:20.42#ibcon#read 5, iclass 33, count 2 2006.161.07:37:20.42#ibcon#about to read 6, iclass 33, count 2 2006.161.07:37:20.42#ibcon#read 6, iclass 33, count 2 2006.161.07:37:20.42#ibcon#end of sib2, iclass 33, count 2 2006.161.07:37:20.42#ibcon#*after write, iclass 33, count 2 2006.161.07:37:20.42#ibcon#*before return 0, iclass 33, count 2 2006.161.07:37:20.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:37:20.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:37:20.42#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.07:37:20.42#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:20.42#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:37:20.54#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:37:20.54#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:37:20.54#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:37:20.54#ibcon#first serial, iclass 33, count 0 2006.161.07:37:20.54#ibcon#enter sib2, iclass 33, count 0 2006.161.07:37:20.54#ibcon#flushed, iclass 33, count 0 2006.161.07:37:20.54#ibcon#about to write, iclass 33, count 0 2006.161.07:37:20.54#ibcon#wrote, iclass 33, count 0 2006.161.07:37:20.54#ibcon#about to read 3, iclass 33, count 0 2006.161.07:37:20.56#ibcon#read 3, iclass 33, count 0 2006.161.07:37:20.56#ibcon#about to read 4, iclass 33, count 0 2006.161.07:37:20.56#ibcon#read 4, iclass 33, count 0 2006.161.07:37:20.56#ibcon#about to read 5, iclass 33, count 0 2006.161.07:37:20.56#ibcon#read 5, iclass 33, count 0 2006.161.07:37:20.56#ibcon#about to read 6, iclass 33, count 0 2006.161.07:37:20.56#ibcon#read 6, iclass 33, count 0 2006.161.07:37:20.56#ibcon#end of sib2, iclass 33, count 0 2006.161.07:37:20.56#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:37:20.56#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:37:20.56#ibcon#[25=USB\r\n] 2006.161.07:37:20.56#ibcon#*before write, iclass 33, count 0 2006.161.07:37:20.56#ibcon#enter sib2, iclass 33, count 0 2006.161.07:37:20.56#ibcon#flushed, iclass 33, count 0 2006.161.07:37:20.56#ibcon#about to write, iclass 33, count 0 2006.161.07:37:20.56#ibcon#wrote, iclass 33, count 0 2006.161.07:37:20.56#ibcon#about to read 3, iclass 33, count 0 2006.161.07:37:20.59#ibcon#read 3, iclass 33, count 0 2006.161.07:37:20.59#ibcon#about to read 4, iclass 33, count 0 2006.161.07:37:20.59#ibcon#read 4, iclass 33, count 0 2006.161.07:37:20.59#ibcon#about to read 5, iclass 33, count 0 2006.161.07:37:20.59#ibcon#read 5, iclass 33, count 0 2006.161.07:37:20.59#ibcon#about to read 6, iclass 33, count 0 2006.161.07:37:20.59#ibcon#read 6, iclass 33, count 0 2006.161.07:37:20.59#ibcon#end of sib2, iclass 33, count 0 2006.161.07:37:20.59#ibcon#*after write, iclass 33, count 0 2006.161.07:37:20.59#ibcon#*before return 0, iclass 33, count 0 2006.161.07:37:20.59#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:37:20.59#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:37:20.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:37:20.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:37:20.59$vc4f8/valo=7,832.99 2006.161.07:37:20.59#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.07:37:20.59#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.07:37:20.59#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:20.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:20.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:20.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:20.59#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:37:20.59#ibcon#first serial, iclass 35, count 0 2006.161.07:37:20.59#ibcon#enter sib2, iclass 35, count 0 2006.161.07:37:20.59#ibcon#flushed, iclass 35, count 0 2006.161.07:37:20.59#ibcon#about to write, iclass 35, count 0 2006.161.07:37:20.59#ibcon#wrote, iclass 35, count 0 2006.161.07:37:20.59#ibcon#about to read 3, iclass 35, count 0 2006.161.07:37:20.61#ibcon#read 3, iclass 35, count 0 2006.161.07:37:20.61#ibcon#about to read 4, iclass 35, count 0 2006.161.07:37:20.61#ibcon#read 4, iclass 35, count 0 2006.161.07:37:20.61#ibcon#about to read 5, iclass 35, count 0 2006.161.07:37:20.61#ibcon#read 5, iclass 35, count 0 2006.161.07:37:20.61#ibcon#about to read 6, iclass 35, count 0 2006.161.07:37:20.61#ibcon#read 6, iclass 35, count 0 2006.161.07:37:20.61#ibcon#end of sib2, iclass 35, count 0 2006.161.07:37:20.61#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:37:20.61#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:37:20.61#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:37:20.61#ibcon#*before write, iclass 35, count 0 2006.161.07:37:20.61#ibcon#enter sib2, iclass 35, count 0 2006.161.07:37:20.61#ibcon#flushed, iclass 35, count 0 2006.161.07:37:20.61#ibcon#about to write, iclass 35, count 0 2006.161.07:37:20.61#ibcon#wrote, iclass 35, count 0 2006.161.07:37:20.61#ibcon#about to read 3, iclass 35, count 0 2006.161.07:37:20.65#ibcon#read 3, iclass 35, count 0 2006.161.07:37:20.65#ibcon#about to read 4, iclass 35, count 0 2006.161.07:37:20.65#ibcon#read 4, iclass 35, count 0 2006.161.07:37:20.65#ibcon#about to read 5, iclass 35, count 0 2006.161.07:37:20.65#ibcon#read 5, iclass 35, count 0 2006.161.07:37:20.65#ibcon#about to read 6, iclass 35, count 0 2006.161.07:37:20.65#ibcon#read 6, iclass 35, count 0 2006.161.07:37:20.65#ibcon#end of sib2, iclass 35, count 0 2006.161.07:37:20.65#ibcon#*after write, iclass 35, count 0 2006.161.07:37:20.65#ibcon#*before return 0, iclass 35, count 0 2006.161.07:37:20.65#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:20.65#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:20.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:37:20.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:37:20.65$vc4f8/va=7,6 2006.161.07:37:20.65#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.07:37:20.65#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.07:37:20.65#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:20.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:20.71#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:20.71#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:20.71#ibcon#enter wrdev, iclass 37, count 2 2006.161.07:37:20.71#ibcon#first serial, iclass 37, count 2 2006.161.07:37:20.71#ibcon#enter sib2, iclass 37, count 2 2006.161.07:37:20.71#ibcon#flushed, iclass 37, count 2 2006.161.07:37:20.71#ibcon#about to write, iclass 37, count 2 2006.161.07:37:20.71#ibcon#wrote, iclass 37, count 2 2006.161.07:37:20.71#ibcon#about to read 3, iclass 37, count 2 2006.161.07:37:20.73#ibcon#read 3, iclass 37, count 2 2006.161.07:37:20.73#ibcon#about to read 4, iclass 37, count 2 2006.161.07:37:20.73#ibcon#read 4, iclass 37, count 2 2006.161.07:37:20.73#ibcon#about to read 5, iclass 37, count 2 2006.161.07:37:20.73#ibcon#read 5, iclass 37, count 2 2006.161.07:37:20.73#ibcon#about to read 6, iclass 37, count 2 2006.161.07:37:20.73#ibcon#read 6, iclass 37, count 2 2006.161.07:37:20.73#ibcon#end of sib2, iclass 37, count 2 2006.161.07:37:20.73#ibcon#*mode == 0, iclass 37, count 2 2006.161.07:37:20.73#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.07:37:20.73#ibcon#[25=AT07-06\r\n] 2006.161.07:37:20.73#ibcon#*before write, iclass 37, count 2 2006.161.07:37:20.73#ibcon#enter sib2, iclass 37, count 2 2006.161.07:37:20.73#ibcon#flushed, iclass 37, count 2 2006.161.07:37:20.73#ibcon#about to write, iclass 37, count 2 2006.161.07:37:20.73#ibcon#wrote, iclass 37, count 2 2006.161.07:37:20.73#ibcon#about to read 3, iclass 37, count 2 2006.161.07:37:20.76#ibcon#read 3, iclass 37, count 2 2006.161.07:37:20.76#ibcon#about to read 4, iclass 37, count 2 2006.161.07:37:20.76#ibcon#read 4, iclass 37, count 2 2006.161.07:37:20.76#ibcon#about to read 5, iclass 37, count 2 2006.161.07:37:20.76#ibcon#read 5, iclass 37, count 2 2006.161.07:37:20.76#ibcon#about to read 6, iclass 37, count 2 2006.161.07:37:20.76#ibcon#read 6, iclass 37, count 2 2006.161.07:37:20.76#ibcon#end of sib2, iclass 37, count 2 2006.161.07:37:20.76#ibcon#*after write, iclass 37, count 2 2006.161.07:37:20.76#ibcon#*before return 0, iclass 37, count 2 2006.161.07:37:20.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:20.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:20.76#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.07:37:20.76#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:20.76#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:37:20.88#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:37:20.88#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:37:20.88#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:37:20.88#ibcon#first serial, iclass 37, count 0 2006.161.07:37:20.88#ibcon#enter sib2, iclass 37, count 0 2006.161.07:37:20.88#ibcon#flushed, iclass 37, count 0 2006.161.07:37:20.88#ibcon#about to write, iclass 37, count 0 2006.161.07:37:20.88#ibcon#wrote, iclass 37, count 0 2006.161.07:37:20.88#ibcon#about to read 3, iclass 37, count 0 2006.161.07:37:20.90#ibcon#read 3, iclass 37, count 0 2006.161.07:37:20.90#ibcon#about to read 4, iclass 37, count 0 2006.161.07:37:20.90#ibcon#read 4, iclass 37, count 0 2006.161.07:37:20.90#ibcon#about to read 5, iclass 37, count 0 2006.161.07:37:20.90#ibcon#read 5, iclass 37, count 0 2006.161.07:37:20.90#ibcon#about to read 6, iclass 37, count 0 2006.161.07:37:20.90#ibcon#read 6, iclass 37, count 0 2006.161.07:37:20.90#ibcon#end of sib2, iclass 37, count 0 2006.161.07:37:20.90#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:37:20.90#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:37:20.90#ibcon#[25=USB\r\n] 2006.161.07:37:20.90#ibcon#*before write, iclass 37, count 0 2006.161.07:37:20.90#ibcon#enter sib2, iclass 37, count 0 2006.161.07:37:20.90#ibcon#flushed, iclass 37, count 0 2006.161.07:37:20.90#ibcon#about to write, iclass 37, count 0 2006.161.07:37:20.90#ibcon#wrote, iclass 37, count 0 2006.161.07:37:20.90#ibcon#about to read 3, iclass 37, count 0 2006.161.07:37:20.93#ibcon#read 3, iclass 37, count 0 2006.161.07:37:20.93#ibcon#about to read 4, iclass 37, count 0 2006.161.07:37:20.93#ibcon#read 4, iclass 37, count 0 2006.161.07:37:20.93#ibcon#about to read 5, iclass 37, count 0 2006.161.07:37:20.93#ibcon#read 5, iclass 37, count 0 2006.161.07:37:20.93#ibcon#about to read 6, iclass 37, count 0 2006.161.07:37:20.93#ibcon#read 6, iclass 37, count 0 2006.161.07:37:20.93#ibcon#end of sib2, iclass 37, count 0 2006.161.07:37:20.93#ibcon#*after write, iclass 37, count 0 2006.161.07:37:20.93#ibcon#*before return 0, iclass 37, count 0 2006.161.07:37:20.93#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:37:20.93#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:37:20.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:37:20.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:37:20.93$vc4f8/valo=8,852.99 2006.161.07:37:20.93#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.07:37:20.93#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.07:37:20.93#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:20.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:37:20.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:37:20.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:37:20.93#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:37:20.93#ibcon#first serial, iclass 39, count 0 2006.161.07:37:20.93#ibcon#enter sib2, iclass 39, count 0 2006.161.07:37:20.93#ibcon#flushed, iclass 39, count 0 2006.161.07:37:20.93#ibcon#about to write, iclass 39, count 0 2006.161.07:37:20.93#ibcon#wrote, iclass 39, count 0 2006.161.07:37:20.93#ibcon#about to read 3, iclass 39, count 0 2006.161.07:37:20.95#ibcon#read 3, iclass 39, count 0 2006.161.07:37:20.95#ibcon#about to read 4, iclass 39, count 0 2006.161.07:37:20.95#ibcon#read 4, iclass 39, count 0 2006.161.07:37:20.95#ibcon#about to read 5, iclass 39, count 0 2006.161.07:37:20.95#ibcon#read 5, iclass 39, count 0 2006.161.07:37:20.95#ibcon#about to read 6, iclass 39, count 0 2006.161.07:37:20.95#ibcon#read 6, iclass 39, count 0 2006.161.07:37:20.95#ibcon#end of sib2, iclass 39, count 0 2006.161.07:37:20.95#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:37:20.95#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:37:20.95#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:37:20.95#ibcon#*before write, iclass 39, count 0 2006.161.07:37:20.95#ibcon#enter sib2, iclass 39, count 0 2006.161.07:37:20.95#ibcon#flushed, iclass 39, count 0 2006.161.07:37:20.95#ibcon#about to write, iclass 39, count 0 2006.161.07:37:20.95#ibcon#wrote, iclass 39, count 0 2006.161.07:37:20.95#ibcon#about to read 3, iclass 39, count 0 2006.161.07:37:20.99#ibcon#read 3, iclass 39, count 0 2006.161.07:37:20.99#ibcon#about to read 4, iclass 39, count 0 2006.161.07:37:20.99#ibcon#read 4, iclass 39, count 0 2006.161.07:37:20.99#ibcon#about to read 5, iclass 39, count 0 2006.161.07:37:20.99#ibcon#read 5, iclass 39, count 0 2006.161.07:37:20.99#ibcon#about to read 6, iclass 39, count 0 2006.161.07:37:20.99#ibcon#read 6, iclass 39, count 0 2006.161.07:37:20.99#ibcon#end of sib2, iclass 39, count 0 2006.161.07:37:20.99#ibcon#*after write, iclass 39, count 0 2006.161.07:37:20.99#ibcon#*before return 0, iclass 39, count 0 2006.161.07:37:20.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:37:20.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:37:20.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:37:20.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:37:20.99$vc4f8/va=8,7 2006.161.07:37:20.99#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.07:37:20.99#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.07:37:20.99#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:20.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:37:21.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:37:21.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:37:21.05#ibcon#enter wrdev, iclass 3, count 2 2006.161.07:37:21.05#ibcon#first serial, iclass 3, count 2 2006.161.07:37:21.05#ibcon#enter sib2, iclass 3, count 2 2006.161.07:37:21.05#ibcon#flushed, iclass 3, count 2 2006.161.07:37:21.05#ibcon#about to write, iclass 3, count 2 2006.161.07:37:21.05#ibcon#wrote, iclass 3, count 2 2006.161.07:37:21.05#ibcon#about to read 3, iclass 3, count 2 2006.161.07:37:21.07#ibcon#read 3, iclass 3, count 2 2006.161.07:37:21.07#ibcon#about to read 4, iclass 3, count 2 2006.161.07:37:21.07#ibcon#read 4, iclass 3, count 2 2006.161.07:37:21.07#ibcon#about to read 5, iclass 3, count 2 2006.161.07:37:21.07#ibcon#read 5, iclass 3, count 2 2006.161.07:37:21.07#ibcon#about to read 6, iclass 3, count 2 2006.161.07:37:21.07#ibcon#read 6, iclass 3, count 2 2006.161.07:37:21.07#ibcon#end of sib2, iclass 3, count 2 2006.161.07:37:21.07#ibcon#*mode == 0, iclass 3, count 2 2006.161.07:37:21.07#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.07:37:21.07#ibcon#[25=AT08-07\r\n] 2006.161.07:37:21.07#ibcon#*before write, iclass 3, count 2 2006.161.07:37:21.07#ibcon#enter sib2, iclass 3, count 2 2006.161.07:37:21.07#ibcon#flushed, iclass 3, count 2 2006.161.07:37:21.07#ibcon#about to write, iclass 3, count 2 2006.161.07:37:21.07#ibcon#wrote, iclass 3, count 2 2006.161.07:37:21.07#ibcon#about to read 3, iclass 3, count 2 2006.161.07:37:21.10#ibcon#read 3, iclass 3, count 2 2006.161.07:37:21.10#ibcon#about to read 4, iclass 3, count 2 2006.161.07:37:21.10#ibcon#read 4, iclass 3, count 2 2006.161.07:37:21.10#ibcon#about to read 5, iclass 3, count 2 2006.161.07:37:21.10#ibcon#read 5, iclass 3, count 2 2006.161.07:37:21.10#ibcon#about to read 6, iclass 3, count 2 2006.161.07:37:21.10#ibcon#read 6, iclass 3, count 2 2006.161.07:37:21.10#ibcon#end of sib2, iclass 3, count 2 2006.161.07:37:21.10#ibcon#*after write, iclass 3, count 2 2006.161.07:37:21.10#ibcon#*before return 0, iclass 3, count 2 2006.161.07:37:21.10#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:37:21.10#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:37:21.10#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.07:37:21.10#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:21.10#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:37:21.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:37:21.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:37:21.22#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:37:21.22#ibcon#first serial, iclass 3, count 0 2006.161.07:37:21.22#ibcon#enter sib2, iclass 3, count 0 2006.161.07:37:21.22#ibcon#flushed, iclass 3, count 0 2006.161.07:37:21.22#ibcon#about to write, iclass 3, count 0 2006.161.07:37:21.22#ibcon#wrote, iclass 3, count 0 2006.161.07:37:21.22#ibcon#about to read 3, iclass 3, count 0 2006.161.07:37:21.24#ibcon#read 3, iclass 3, count 0 2006.161.07:37:21.24#ibcon#about to read 4, iclass 3, count 0 2006.161.07:37:21.24#ibcon#read 4, iclass 3, count 0 2006.161.07:37:21.24#ibcon#about to read 5, iclass 3, count 0 2006.161.07:37:21.24#ibcon#read 5, iclass 3, count 0 2006.161.07:37:21.24#ibcon#about to read 6, iclass 3, count 0 2006.161.07:37:21.24#ibcon#read 6, iclass 3, count 0 2006.161.07:37:21.24#ibcon#end of sib2, iclass 3, count 0 2006.161.07:37:21.24#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:37:21.24#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:37:21.24#ibcon#[25=USB\r\n] 2006.161.07:37:21.24#ibcon#*before write, iclass 3, count 0 2006.161.07:37:21.24#ibcon#enter sib2, iclass 3, count 0 2006.161.07:37:21.24#ibcon#flushed, iclass 3, count 0 2006.161.07:37:21.24#ibcon#about to write, iclass 3, count 0 2006.161.07:37:21.24#ibcon#wrote, iclass 3, count 0 2006.161.07:37:21.24#ibcon#about to read 3, iclass 3, count 0 2006.161.07:37:21.27#ibcon#read 3, iclass 3, count 0 2006.161.07:37:21.27#ibcon#about to read 4, iclass 3, count 0 2006.161.07:37:21.27#ibcon#read 4, iclass 3, count 0 2006.161.07:37:21.27#ibcon#about to read 5, iclass 3, count 0 2006.161.07:37:21.27#ibcon#read 5, iclass 3, count 0 2006.161.07:37:21.27#ibcon#about to read 6, iclass 3, count 0 2006.161.07:37:21.27#ibcon#read 6, iclass 3, count 0 2006.161.07:37:21.27#ibcon#end of sib2, iclass 3, count 0 2006.161.07:37:21.27#ibcon#*after write, iclass 3, count 0 2006.161.07:37:21.27#ibcon#*before return 0, iclass 3, count 0 2006.161.07:37:21.27#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:37:21.27#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:37:21.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:37:21.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:37:21.27$vc4f8/vblo=1,632.99 2006.161.07:37:21.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.07:37:21.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.07:37:21.27#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:21.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:37:21.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:37:21.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:37:21.27#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:37:21.27#ibcon#first serial, iclass 5, count 0 2006.161.07:37:21.27#ibcon#enter sib2, iclass 5, count 0 2006.161.07:37:21.27#ibcon#flushed, iclass 5, count 0 2006.161.07:37:21.27#ibcon#about to write, iclass 5, count 0 2006.161.07:37:21.27#ibcon#wrote, iclass 5, count 0 2006.161.07:37:21.27#ibcon#about to read 3, iclass 5, count 0 2006.161.07:37:21.29#ibcon#read 3, iclass 5, count 0 2006.161.07:37:21.29#ibcon#about to read 4, iclass 5, count 0 2006.161.07:37:21.29#ibcon#read 4, iclass 5, count 0 2006.161.07:37:21.29#ibcon#about to read 5, iclass 5, count 0 2006.161.07:37:21.29#ibcon#read 5, iclass 5, count 0 2006.161.07:37:21.29#ibcon#about to read 6, iclass 5, count 0 2006.161.07:37:21.29#ibcon#read 6, iclass 5, count 0 2006.161.07:37:21.29#ibcon#end of sib2, iclass 5, count 0 2006.161.07:37:21.29#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:37:21.29#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:37:21.29#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:37:21.29#ibcon#*before write, iclass 5, count 0 2006.161.07:37:21.29#ibcon#enter sib2, iclass 5, count 0 2006.161.07:37:21.29#ibcon#flushed, iclass 5, count 0 2006.161.07:37:21.29#ibcon#about to write, iclass 5, count 0 2006.161.07:37:21.29#ibcon#wrote, iclass 5, count 0 2006.161.07:37:21.29#ibcon#about to read 3, iclass 5, count 0 2006.161.07:37:21.33#ibcon#read 3, iclass 5, count 0 2006.161.07:37:21.33#ibcon#about to read 4, iclass 5, count 0 2006.161.07:37:21.33#ibcon#read 4, iclass 5, count 0 2006.161.07:37:21.33#ibcon#about to read 5, iclass 5, count 0 2006.161.07:37:21.33#ibcon#read 5, iclass 5, count 0 2006.161.07:37:21.33#ibcon#about to read 6, iclass 5, count 0 2006.161.07:37:21.33#ibcon#read 6, iclass 5, count 0 2006.161.07:37:21.33#ibcon#end of sib2, iclass 5, count 0 2006.161.07:37:21.33#ibcon#*after write, iclass 5, count 0 2006.161.07:37:21.33#ibcon#*before return 0, iclass 5, count 0 2006.161.07:37:21.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:37:21.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:37:21.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:37:21.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:37:21.33$vc4f8/vb=1,4 2006.161.07:37:21.33#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.07:37:21.33#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.07:37:21.33#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:21.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:37:21.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:37:21.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:37:21.33#ibcon#enter wrdev, iclass 7, count 2 2006.161.07:37:21.33#ibcon#first serial, iclass 7, count 2 2006.161.07:37:21.33#ibcon#enter sib2, iclass 7, count 2 2006.161.07:37:21.33#ibcon#flushed, iclass 7, count 2 2006.161.07:37:21.33#ibcon#about to write, iclass 7, count 2 2006.161.07:37:21.33#ibcon#wrote, iclass 7, count 2 2006.161.07:37:21.33#ibcon#about to read 3, iclass 7, count 2 2006.161.07:37:21.35#ibcon#read 3, iclass 7, count 2 2006.161.07:37:21.35#ibcon#about to read 4, iclass 7, count 2 2006.161.07:37:21.35#ibcon#read 4, iclass 7, count 2 2006.161.07:37:21.35#ibcon#about to read 5, iclass 7, count 2 2006.161.07:37:21.35#ibcon#read 5, iclass 7, count 2 2006.161.07:37:21.35#ibcon#about to read 6, iclass 7, count 2 2006.161.07:37:21.35#ibcon#read 6, iclass 7, count 2 2006.161.07:37:21.35#ibcon#end of sib2, iclass 7, count 2 2006.161.07:37:21.35#ibcon#*mode == 0, iclass 7, count 2 2006.161.07:37:21.35#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.07:37:21.35#ibcon#[27=AT01-04\r\n] 2006.161.07:37:21.35#ibcon#*before write, iclass 7, count 2 2006.161.07:37:21.35#ibcon#enter sib2, iclass 7, count 2 2006.161.07:37:21.35#ibcon#flushed, iclass 7, count 2 2006.161.07:37:21.35#ibcon#about to write, iclass 7, count 2 2006.161.07:37:21.35#ibcon#wrote, iclass 7, count 2 2006.161.07:37:21.35#ibcon#about to read 3, iclass 7, count 2 2006.161.07:37:21.38#ibcon#read 3, iclass 7, count 2 2006.161.07:37:21.38#ibcon#about to read 4, iclass 7, count 2 2006.161.07:37:21.38#ibcon#read 4, iclass 7, count 2 2006.161.07:37:21.38#ibcon#about to read 5, iclass 7, count 2 2006.161.07:37:21.38#ibcon#read 5, iclass 7, count 2 2006.161.07:37:21.38#ibcon#about to read 6, iclass 7, count 2 2006.161.07:37:21.38#ibcon#read 6, iclass 7, count 2 2006.161.07:37:21.38#ibcon#end of sib2, iclass 7, count 2 2006.161.07:37:21.38#ibcon#*after write, iclass 7, count 2 2006.161.07:37:21.38#ibcon#*before return 0, iclass 7, count 2 2006.161.07:37:21.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:37:21.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:37:21.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.07:37:21.38#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:21.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:37:21.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:37:21.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:37:21.50#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:37:21.50#ibcon#first serial, iclass 7, count 0 2006.161.07:37:21.50#ibcon#enter sib2, iclass 7, count 0 2006.161.07:37:21.50#ibcon#flushed, iclass 7, count 0 2006.161.07:37:21.50#ibcon#about to write, iclass 7, count 0 2006.161.07:37:21.50#ibcon#wrote, iclass 7, count 0 2006.161.07:37:21.50#ibcon#about to read 3, iclass 7, count 0 2006.161.07:37:21.52#ibcon#read 3, iclass 7, count 0 2006.161.07:37:21.52#ibcon#about to read 4, iclass 7, count 0 2006.161.07:37:21.52#ibcon#read 4, iclass 7, count 0 2006.161.07:37:21.52#ibcon#about to read 5, iclass 7, count 0 2006.161.07:37:21.52#ibcon#read 5, iclass 7, count 0 2006.161.07:37:21.52#ibcon#about to read 6, iclass 7, count 0 2006.161.07:37:21.52#ibcon#read 6, iclass 7, count 0 2006.161.07:37:21.52#ibcon#end of sib2, iclass 7, count 0 2006.161.07:37:21.52#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:37:21.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:37:21.52#ibcon#[27=USB\r\n] 2006.161.07:37:21.52#ibcon#*before write, iclass 7, count 0 2006.161.07:37:21.52#ibcon#enter sib2, iclass 7, count 0 2006.161.07:37:21.52#ibcon#flushed, iclass 7, count 0 2006.161.07:37:21.52#ibcon#about to write, iclass 7, count 0 2006.161.07:37:21.52#ibcon#wrote, iclass 7, count 0 2006.161.07:37:21.52#ibcon#about to read 3, iclass 7, count 0 2006.161.07:37:21.55#ibcon#read 3, iclass 7, count 0 2006.161.07:37:21.55#ibcon#about to read 4, iclass 7, count 0 2006.161.07:37:21.55#ibcon#read 4, iclass 7, count 0 2006.161.07:37:21.55#ibcon#about to read 5, iclass 7, count 0 2006.161.07:37:21.55#ibcon#read 5, iclass 7, count 0 2006.161.07:37:21.55#ibcon#about to read 6, iclass 7, count 0 2006.161.07:37:21.55#ibcon#read 6, iclass 7, count 0 2006.161.07:37:21.55#ibcon#end of sib2, iclass 7, count 0 2006.161.07:37:21.55#ibcon#*after write, iclass 7, count 0 2006.161.07:37:21.55#ibcon#*before return 0, iclass 7, count 0 2006.161.07:37:21.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:37:21.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:37:21.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:37:21.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:37:21.55$vc4f8/vblo=2,640.99 2006.161.07:37:21.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:37:21.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:37:21.55#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:21.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:21.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:21.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:21.55#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:37:21.55#ibcon#first serial, iclass 11, count 0 2006.161.07:37:21.55#ibcon#enter sib2, iclass 11, count 0 2006.161.07:37:21.55#ibcon#flushed, iclass 11, count 0 2006.161.07:37:21.55#ibcon#about to write, iclass 11, count 0 2006.161.07:37:21.55#ibcon#wrote, iclass 11, count 0 2006.161.07:37:21.55#ibcon#about to read 3, iclass 11, count 0 2006.161.07:37:21.57#ibcon#read 3, iclass 11, count 0 2006.161.07:37:21.57#ibcon#about to read 4, iclass 11, count 0 2006.161.07:37:21.57#ibcon#read 4, iclass 11, count 0 2006.161.07:37:21.57#ibcon#about to read 5, iclass 11, count 0 2006.161.07:37:21.57#ibcon#read 5, iclass 11, count 0 2006.161.07:37:21.57#ibcon#about to read 6, iclass 11, count 0 2006.161.07:37:21.57#ibcon#read 6, iclass 11, count 0 2006.161.07:37:21.57#ibcon#end of sib2, iclass 11, count 0 2006.161.07:37:21.57#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:37:21.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:37:21.57#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:37:21.57#ibcon#*before write, iclass 11, count 0 2006.161.07:37:21.57#ibcon#enter sib2, iclass 11, count 0 2006.161.07:37:21.57#ibcon#flushed, iclass 11, count 0 2006.161.07:37:21.57#ibcon#about to write, iclass 11, count 0 2006.161.07:37:21.57#ibcon#wrote, iclass 11, count 0 2006.161.07:37:21.57#ibcon#about to read 3, iclass 11, count 0 2006.161.07:37:21.61#ibcon#read 3, iclass 11, count 0 2006.161.07:37:21.61#ibcon#about to read 4, iclass 11, count 0 2006.161.07:37:21.61#ibcon#read 4, iclass 11, count 0 2006.161.07:37:21.61#ibcon#about to read 5, iclass 11, count 0 2006.161.07:37:21.61#ibcon#read 5, iclass 11, count 0 2006.161.07:37:21.61#ibcon#about to read 6, iclass 11, count 0 2006.161.07:37:21.61#ibcon#read 6, iclass 11, count 0 2006.161.07:37:21.61#ibcon#end of sib2, iclass 11, count 0 2006.161.07:37:21.61#ibcon#*after write, iclass 11, count 0 2006.161.07:37:21.61#ibcon#*before return 0, iclass 11, count 0 2006.161.07:37:21.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:21.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:37:21.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:37:21.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:37:21.61$vc4f8/vb=2,4 2006.161.07:37:21.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:37:21.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:37:21.61#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:21.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:21.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:21.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:21.67#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:37:21.67#ibcon#first serial, iclass 13, count 2 2006.161.07:37:21.67#ibcon#enter sib2, iclass 13, count 2 2006.161.07:37:21.67#ibcon#flushed, iclass 13, count 2 2006.161.07:37:21.67#ibcon#about to write, iclass 13, count 2 2006.161.07:37:21.67#ibcon#wrote, iclass 13, count 2 2006.161.07:37:21.67#ibcon#about to read 3, iclass 13, count 2 2006.161.07:37:21.69#ibcon#read 3, iclass 13, count 2 2006.161.07:37:21.69#ibcon#about to read 4, iclass 13, count 2 2006.161.07:37:21.69#ibcon#read 4, iclass 13, count 2 2006.161.07:37:21.69#ibcon#about to read 5, iclass 13, count 2 2006.161.07:37:21.69#ibcon#read 5, iclass 13, count 2 2006.161.07:37:21.69#ibcon#about to read 6, iclass 13, count 2 2006.161.07:37:21.69#ibcon#read 6, iclass 13, count 2 2006.161.07:37:21.69#ibcon#end of sib2, iclass 13, count 2 2006.161.07:37:21.69#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:37:21.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:37:21.69#ibcon#[27=AT02-04\r\n] 2006.161.07:37:21.69#ibcon#*before write, iclass 13, count 2 2006.161.07:37:21.69#ibcon#enter sib2, iclass 13, count 2 2006.161.07:37:21.69#ibcon#flushed, iclass 13, count 2 2006.161.07:37:21.69#ibcon#about to write, iclass 13, count 2 2006.161.07:37:21.69#ibcon#wrote, iclass 13, count 2 2006.161.07:37:21.69#ibcon#about to read 3, iclass 13, count 2 2006.161.07:37:21.72#ibcon#read 3, iclass 13, count 2 2006.161.07:37:21.72#ibcon#about to read 4, iclass 13, count 2 2006.161.07:37:21.72#ibcon#read 4, iclass 13, count 2 2006.161.07:37:21.72#ibcon#about to read 5, iclass 13, count 2 2006.161.07:37:21.72#ibcon#read 5, iclass 13, count 2 2006.161.07:37:21.72#ibcon#about to read 6, iclass 13, count 2 2006.161.07:37:21.72#ibcon#read 6, iclass 13, count 2 2006.161.07:37:21.72#ibcon#end of sib2, iclass 13, count 2 2006.161.07:37:21.72#ibcon#*after write, iclass 13, count 2 2006.161.07:37:21.72#ibcon#*before return 0, iclass 13, count 2 2006.161.07:37:21.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:21.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:37:21.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:37:21.72#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:21.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:21.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:21.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:21.84#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:37:21.84#ibcon#first serial, iclass 13, count 0 2006.161.07:37:21.84#ibcon#enter sib2, iclass 13, count 0 2006.161.07:37:21.84#ibcon#flushed, iclass 13, count 0 2006.161.07:37:21.84#ibcon#about to write, iclass 13, count 0 2006.161.07:37:21.84#ibcon#wrote, iclass 13, count 0 2006.161.07:37:21.84#ibcon#about to read 3, iclass 13, count 0 2006.161.07:37:21.86#ibcon#read 3, iclass 13, count 0 2006.161.07:37:21.86#ibcon#about to read 4, iclass 13, count 0 2006.161.07:37:21.86#ibcon#read 4, iclass 13, count 0 2006.161.07:37:21.86#ibcon#about to read 5, iclass 13, count 0 2006.161.07:37:21.86#ibcon#read 5, iclass 13, count 0 2006.161.07:37:21.86#ibcon#about to read 6, iclass 13, count 0 2006.161.07:37:21.86#ibcon#read 6, iclass 13, count 0 2006.161.07:37:21.86#ibcon#end of sib2, iclass 13, count 0 2006.161.07:37:21.86#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:37:21.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:37:21.86#ibcon#[27=USB\r\n] 2006.161.07:37:21.86#ibcon#*before write, iclass 13, count 0 2006.161.07:37:21.86#ibcon#enter sib2, iclass 13, count 0 2006.161.07:37:21.86#ibcon#flushed, iclass 13, count 0 2006.161.07:37:21.86#ibcon#about to write, iclass 13, count 0 2006.161.07:37:21.86#ibcon#wrote, iclass 13, count 0 2006.161.07:37:21.86#ibcon#about to read 3, iclass 13, count 0 2006.161.07:37:21.89#ibcon#read 3, iclass 13, count 0 2006.161.07:37:21.89#ibcon#about to read 4, iclass 13, count 0 2006.161.07:37:21.89#ibcon#read 4, iclass 13, count 0 2006.161.07:37:21.89#ibcon#about to read 5, iclass 13, count 0 2006.161.07:37:21.89#ibcon#read 5, iclass 13, count 0 2006.161.07:37:21.89#ibcon#about to read 6, iclass 13, count 0 2006.161.07:37:21.89#ibcon#read 6, iclass 13, count 0 2006.161.07:37:21.89#ibcon#end of sib2, iclass 13, count 0 2006.161.07:37:21.89#ibcon#*after write, iclass 13, count 0 2006.161.07:37:21.89#ibcon#*before return 0, iclass 13, count 0 2006.161.07:37:21.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:21.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:37:21.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:37:21.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:37:21.89$vc4f8/vblo=3,656.99 2006.161.07:37:21.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.07:37:21.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.07:37:21.89#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:21.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:21.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:21.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:21.89#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:37:21.89#ibcon#first serial, iclass 15, count 0 2006.161.07:37:21.89#ibcon#enter sib2, iclass 15, count 0 2006.161.07:37:21.89#ibcon#flushed, iclass 15, count 0 2006.161.07:37:21.89#ibcon#about to write, iclass 15, count 0 2006.161.07:37:21.89#ibcon#wrote, iclass 15, count 0 2006.161.07:37:21.89#ibcon#about to read 3, iclass 15, count 0 2006.161.07:37:21.91#ibcon#read 3, iclass 15, count 0 2006.161.07:37:21.91#ibcon#about to read 4, iclass 15, count 0 2006.161.07:37:21.91#ibcon#read 4, iclass 15, count 0 2006.161.07:37:21.91#ibcon#about to read 5, iclass 15, count 0 2006.161.07:37:21.91#ibcon#read 5, iclass 15, count 0 2006.161.07:37:21.91#ibcon#about to read 6, iclass 15, count 0 2006.161.07:37:21.91#ibcon#read 6, iclass 15, count 0 2006.161.07:37:21.91#ibcon#end of sib2, iclass 15, count 0 2006.161.07:37:21.91#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:37:21.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:37:21.91#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:37:21.91#ibcon#*before write, iclass 15, count 0 2006.161.07:37:21.91#ibcon#enter sib2, iclass 15, count 0 2006.161.07:37:21.91#ibcon#flushed, iclass 15, count 0 2006.161.07:37:21.91#ibcon#about to write, iclass 15, count 0 2006.161.07:37:21.91#ibcon#wrote, iclass 15, count 0 2006.161.07:37:21.91#ibcon#about to read 3, iclass 15, count 0 2006.161.07:37:21.95#ibcon#read 3, iclass 15, count 0 2006.161.07:37:21.95#ibcon#about to read 4, iclass 15, count 0 2006.161.07:37:21.95#ibcon#read 4, iclass 15, count 0 2006.161.07:37:21.95#ibcon#about to read 5, iclass 15, count 0 2006.161.07:37:21.95#ibcon#read 5, iclass 15, count 0 2006.161.07:37:21.95#ibcon#about to read 6, iclass 15, count 0 2006.161.07:37:21.95#ibcon#read 6, iclass 15, count 0 2006.161.07:37:21.95#ibcon#end of sib2, iclass 15, count 0 2006.161.07:37:21.95#ibcon#*after write, iclass 15, count 0 2006.161.07:37:21.95#ibcon#*before return 0, iclass 15, count 0 2006.161.07:37:21.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:21.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:37:21.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:37:21.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:37:21.95$vc4f8/vb=3,4 2006.161.07:37:21.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.07:37:21.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.07:37:21.95#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:21.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:22.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:22.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:22.01#ibcon#enter wrdev, iclass 17, count 2 2006.161.07:37:22.01#ibcon#first serial, iclass 17, count 2 2006.161.07:37:22.01#ibcon#enter sib2, iclass 17, count 2 2006.161.07:37:22.01#ibcon#flushed, iclass 17, count 2 2006.161.07:37:22.01#ibcon#about to write, iclass 17, count 2 2006.161.07:37:22.01#ibcon#wrote, iclass 17, count 2 2006.161.07:37:22.01#ibcon#about to read 3, iclass 17, count 2 2006.161.07:37:22.03#ibcon#read 3, iclass 17, count 2 2006.161.07:37:22.03#ibcon#about to read 4, iclass 17, count 2 2006.161.07:37:22.03#ibcon#read 4, iclass 17, count 2 2006.161.07:37:22.03#ibcon#about to read 5, iclass 17, count 2 2006.161.07:37:22.03#ibcon#read 5, iclass 17, count 2 2006.161.07:37:22.03#ibcon#about to read 6, iclass 17, count 2 2006.161.07:37:22.03#ibcon#read 6, iclass 17, count 2 2006.161.07:37:22.03#ibcon#end of sib2, iclass 17, count 2 2006.161.07:37:22.03#ibcon#*mode == 0, iclass 17, count 2 2006.161.07:37:22.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.07:37:22.03#ibcon#[27=AT03-04\r\n] 2006.161.07:37:22.03#ibcon#*before write, iclass 17, count 2 2006.161.07:37:22.03#ibcon#enter sib2, iclass 17, count 2 2006.161.07:37:22.03#ibcon#flushed, iclass 17, count 2 2006.161.07:37:22.03#ibcon#about to write, iclass 17, count 2 2006.161.07:37:22.03#ibcon#wrote, iclass 17, count 2 2006.161.07:37:22.03#ibcon#about to read 3, iclass 17, count 2 2006.161.07:37:22.06#ibcon#read 3, iclass 17, count 2 2006.161.07:37:22.06#ibcon#about to read 4, iclass 17, count 2 2006.161.07:37:22.06#ibcon#read 4, iclass 17, count 2 2006.161.07:37:22.06#ibcon#about to read 5, iclass 17, count 2 2006.161.07:37:22.06#ibcon#read 5, iclass 17, count 2 2006.161.07:37:22.06#ibcon#about to read 6, iclass 17, count 2 2006.161.07:37:22.06#ibcon#read 6, iclass 17, count 2 2006.161.07:37:22.06#ibcon#end of sib2, iclass 17, count 2 2006.161.07:37:22.06#ibcon#*after write, iclass 17, count 2 2006.161.07:37:22.06#ibcon#*before return 0, iclass 17, count 2 2006.161.07:37:22.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:22.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:37:22.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.07:37:22.06#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:22.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:22.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:22.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:22.18#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:37:22.18#ibcon#first serial, iclass 17, count 0 2006.161.07:37:22.18#ibcon#enter sib2, iclass 17, count 0 2006.161.07:37:22.18#ibcon#flushed, iclass 17, count 0 2006.161.07:37:22.18#ibcon#about to write, iclass 17, count 0 2006.161.07:37:22.18#ibcon#wrote, iclass 17, count 0 2006.161.07:37:22.18#ibcon#about to read 3, iclass 17, count 0 2006.161.07:37:22.20#ibcon#read 3, iclass 17, count 0 2006.161.07:37:22.20#ibcon#about to read 4, iclass 17, count 0 2006.161.07:37:22.20#ibcon#read 4, iclass 17, count 0 2006.161.07:37:22.20#ibcon#about to read 5, iclass 17, count 0 2006.161.07:37:22.20#ibcon#read 5, iclass 17, count 0 2006.161.07:37:22.20#ibcon#about to read 6, iclass 17, count 0 2006.161.07:37:22.20#ibcon#read 6, iclass 17, count 0 2006.161.07:37:22.20#ibcon#end of sib2, iclass 17, count 0 2006.161.07:37:22.20#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:37:22.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:37:22.20#ibcon#[27=USB\r\n] 2006.161.07:37:22.20#ibcon#*before write, iclass 17, count 0 2006.161.07:37:22.20#ibcon#enter sib2, iclass 17, count 0 2006.161.07:37:22.20#ibcon#flushed, iclass 17, count 0 2006.161.07:37:22.20#ibcon#about to write, iclass 17, count 0 2006.161.07:37:22.20#ibcon#wrote, iclass 17, count 0 2006.161.07:37:22.20#ibcon#about to read 3, iclass 17, count 0 2006.161.07:37:22.23#ibcon#read 3, iclass 17, count 0 2006.161.07:37:22.23#ibcon#about to read 4, iclass 17, count 0 2006.161.07:37:22.23#ibcon#read 4, iclass 17, count 0 2006.161.07:37:22.23#ibcon#about to read 5, iclass 17, count 0 2006.161.07:37:22.23#ibcon#read 5, iclass 17, count 0 2006.161.07:37:22.23#ibcon#about to read 6, iclass 17, count 0 2006.161.07:37:22.23#ibcon#read 6, iclass 17, count 0 2006.161.07:37:22.23#ibcon#end of sib2, iclass 17, count 0 2006.161.07:37:22.23#ibcon#*after write, iclass 17, count 0 2006.161.07:37:22.23#ibcon#*before return 0, iclass 17, count 0 2006.161.07:37:22.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:22.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:37:22.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:37:22.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:37:22.23$vc4f8/vblo=4,712.99 2006.161.07:37:22.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:37:22.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:37:22.23#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:22.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:22.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:22.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:22.23#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:37:22.23#ibcon#first serial, iclass 19, count 0 2006.161.07:37:22.23#ibcon#enter sib2, iclass 19, count 0 2006.161.07:37:22.23#ibcon#flushed, iclass 19, count 0 2006.161.07:37:22.23#ibcon#about to write, iclass 19, count 0 2006.161.07:37:22.23#ibcon#wrote, iclass 19, count 0 2006.161.07:37:22.23#ibcon#about to read 3, iclass 19, count 0 2006.161.07:37:22.25#ibcon#read 3, iclass 19, count 0 2006.161.07:37:22.25#ibcon#about to read 4, iclass 19, count 0 2006.161.07:37:22.25#ibcon#read 4, iclass 19, count 0 2006.161.07:37:22.25#ibcon#about to read 5, iclass 19, count 0 2006.161.07:37:22.25#ibcon#read 5, iclass 19, count 0 2006.161.07:37:22.25#ibcon#about to read 6, iclass 19, count 0 2006.161.07:37:22.25#ibcon#read 6, iclass 19, count 0 2006.161.07:37:22.25#ibcon#end of sib2, iclass 19, count 0 2006.161.07:37:22.25#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:37:22.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:37:22.25#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:37:22.25#ibcon#*before write, iclass 19, count 0 2006.161.07:37:22.25#ibcon#enter sib2, iclass 19, count 0 2006.161.07:37:22.25#ibcon#flushed, iclass 19, count 0 2006.161.07:37:22.25#ibcon#about to write, iclass 19, count 0 2006.161.07:37:22.25#ibcon#wrote, iclass 19, count 0 2006.161.07:37:22.25#ibcon#about to read 3, iclass 19, count 0 2006.161.07:37:22.29#ibcon#read 3, iclass 19, count 0 2006.161.07:37:22.29#ibcon#about to read 4, iclass 19, count 0 2006.161.07:37:22.29#ibcon#read 4, iclass 19, count 0 2006.161.07:37:22.29#ibcon#about to read 5, iclass 19, count 0 2006.161.07:37:22.29#ibcon#read 5, iclass 19, count 0 2006.161.07:37:22.29#ibcon#about to read 6, iclass 19, count 0 2006.161.07:37:22.29#ibcon#read 6, iclass 19, count 0 2006.161.07:37:22.29#ibcon#end of sib2, iclass 19, count 0 2006.161.07:37:22.29#ibcon#*after write, iclass 19, count 0 2006.161.07:37:22.29#ibcon#*before return 0, iclass 19, count 0 2006.161.07:37:22.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:22.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:37:22.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:37:22.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:37:22.29$vc4f8/vb=4,4 2006.161.07:37:22.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:37:22.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:37:22.29#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:22.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:22.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:22.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:22.35#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:37:22.35#ibcon#first serial, iclass 21, count 2 2006.161.07:37:22.35#ibcon#enter sib2, iclass 21, count 2 2006.161.07:37:22.35#ibcon#flushed, iclass 21, count 2 2006.161.07:37:22.35#ibcon#about to write, iclass 21, count 2 2006.161.07:37:22.35#ibcon#wrote, iclass 21, count 2 2006.161.07:37:22.35#ibcon#about to read 3, iclass 21, count 2 2006.161.07:37:22.37#ibcon#read 3, iclass 21, count 2 2006.161.07:37:22.37#ibcon#about to read 4, iclass 21, count 2 2006.161.07:37:22.37#ibcon#read 4, iclass 21, count 2 2006.161.07:37:22.37#ibcon#about to read 5, iclass 21, count 2 2006.161.07:37:22.37#ibcon#read 5, iclass 21, count 2 2006.161.07:37:22.37#ibcon#about to read 6, iclass 21, count 2 2006.161.07:37:22.37#ibcon#read 6, iclass 21, count 2 2006.161.07:37:22.37#ibcon#end of sib2, iclass 21, count 2 2006.161.07:37:22.37#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:37:22.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:37:22.37#ibcon#[27=AT04-04\r\n] 2006.161.07:37:22.37#ibcon#*before write, iclass 21, count 2 2006.161.07:37:22.37#ibcon#enter sib2, iclass 21, count 2 2006.161.07:37:22.37#ibcon#flushed, iclass 21, count 2 2006.161.07:37:22.37#ibcon#about to write, iclass 21, count 2 2006.161.07:37:22.37#ibcon#wrote, iclass 21, count 2 2006.161.07:37:22.37#ibcon#about to read 3, iclass 21, count 2 2006.161.07:37:22.40#ibcon#read 3, iclass 21, count 2 2006.161.07:37:22.40#ibcon#about to read 4, iclass 21, count 2 2006.161.07:37:22.40#ibcon#read 4, iclass 21, count 2 2006.161.07:37:22.40#ibcon#about to read 5, iclass 21, count 2 2006.161.07:37:22.40#ibcon#read 5, iclass 21, count 2 2006.161.07:37:22.40#ibcon#about to read 6, iclass 21, count 2 2006.161.07:37:22.40#ibcon#read 6, iclass 21, count 2 2006.161.07:37:22.40#ibcon#end of sib2, iclass 21, count 2 2006.161.07:37:22.40#ibcon#*after write, iclass 21, count 2 2006.161.07:37:22.40#ibcon#*before return 0, iclass 21, count 2 2006.161.07:37:22.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:22.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:37:22.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:37:22.40#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:22.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:22.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:22.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:22.52#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:37:22.52#ibcon#first serial, iclass 21, count 0 2006.161.07:37:22.52#ibcon#enter sib2, iclass 21, count 0 2006.161.07:37:22.52#ibcon#flushed, iclass 21, count 0 2006.161.07:37:22.52#ibcon#about to write, iclass 21, count 0 2006.161.07:37:22.52#ibcon#wrote, iclass 21, count 0 2006.161.07:37:22.52#ibcon#about to read 3, iclass 21, count 0 2006.161.07:37:22.54#ibcon#read 3, iclass 21, count 0 2006.161.07:37:22.54#ibcon#about to read 4, iclass 21, count 0 2006.161.07:37:22.54#ibcon#read 4, iclass 21, count 0 2006.161.07:37:22.54#ibcon#about to read 5, iclass 21, count 0 2006.161.07:37:22.54#ibcon#read 5, iclass 21, count 0 2006.161.07:37:22.54#ibcon#about to read 6, iclass 21, count 0 2006.161.07:37:22.54#ibcon#read 6, iclass 21, count 0 2006.161.07:37:22.54#ibcon#end of sib2, iclass 21, count 0 2006.161.07:37:22.54#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:37:22.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:37:22.54#ibcon#[27=USB\r\n] 2006.161.07:37:22.54#ibcon#*before write, iclass 21, count 0 2006.161.07:37:22.54#ibcon#enter sib2, iclass 21, count 0 2006.161.07:37:22.54#ibcon#flushed, iclass 21, count 0 2006.161.07:37:22.54#ibcon#about to write, iclass 21, count 0 2006.161.07:37:22.54#ibcon#wrote, iclass 21, count 0 2006.161.07:37:22.54#ibcon#about to read 3, iclass 21, count 0 2006.161.07:37:22.57#ibcon#read 3, iclass 21, count 0 2006.161.07:37:22.57#ibcon#about to read 4, iclass 21, count 0 2006.161.07:37:22.57#ibcon#read 4, iclass 21, count 0 2006.161.07:37:22.57#ibcon#about to read 5, iclass 21, count 0 2006.161.07:37:22.57#ibcon#read 5, iclass 21, count 0 2006.161.07:37:22.57#ibcon#about to read 6, iclass 21, count 0 2006.161.07:37:22.57#ibcon#read 6, iclass 21, count 0 2006.161.07:37:22.57#ibcon#end of sib2, iclass 21, count 0 2006.161.07:37:22.57#ibcon#*after write, iclass 21, count 0 2006.161.07:37:22.57#ibcon#*before return 0, iclass 21, count 0 2006.161.07:37:22.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:22.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:37:22.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:37:22.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:37:22.57$vc4f8/vblo=5,744.99 2006.161.07:37:22.57#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:37:22.57#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:37:22.57#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:22.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:22.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:22.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:22.57#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:37:22.57#ibcon#first serial, iclass 23, count 0 2006.161.07:37:22.57#ibcon#enter sib2, iclass 23, count 0 2006.161.07:37:22.57#ibcon#flushed, iclass 23, count 0 2006.161.07:37:22.57#ibcon#about to write, iclass 23, count 0 2006.161.07:37:22.57#ibcon#wrote, iclass 23, count 0 2006.161.07:37:22.57#ibcon#about to read 3, iclass 23, count 0 2006.161.07:37:22.59#ibcon#read 3, iclass 23, count 0 2006.161.07:37:22.59#ibcon#about to read 4, iclass 23, count 0 2006.161.07:37:22.59#ibcon#read 4, iclass 23, count 0 2006.161.07:37:22.59#ibcon#about to read 5, iclass 23, count 0 2006.161.07:37:22.59#ibcon#read 5, iclass 23, count 0 2006.161.07:37:22.59#ibcon#about to read 6, iclass 23, count 0 2006.161.07:37:22.59#ibcon#read 6, iclass 23, count 0 2006.161.07:37:22.59#ibcon#end of sib2, iclass 23, count 0 2006.161.07:37:22.59#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:37:22.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:37:22.59#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:37:22.59#ibcon#*before write, iclass 23, count 0 2006.161.07:37:22.59#ibcon#enter sib2, iclass 23, count 0 2006.161.07:37:22.59#ibcon#flushed, iclass 23, count 0 2006.161.07:37:22.59#ibcon#about to write, iclass 23, count 0 2006.161.07:37:22.59#ibcon#wrote, iclass 23, count 0 2006.161.07:37:22.59#ibcon#about to read 3, iclass 23, count 0 2006.161.07:37:22.63#ibcon#read 3, iclass 23, count 0 2006.161.07:37:22.63#ibcon#about to read 4, iclass 23, count 0 2006.161.07:37:22.63#ibcon#read 4, iclass 23, count 0 2006.161.07:37:22.63#ibcon#about to read 5, iclass 23, count 0 2006.161.07:37:22.63#ibcon#read 5, iclass 23, count 0 2006.161.07:37:22.63#ibcon#about to read 6, iclass 23, count 0 2006.161.07:37:22.63#ibcon#read 6, iclass 23, count 0 2006.161.07:37:22.63#ibcon#end of sib2, iclass 23, count 0 2006.161.07:37:22.63#ibcon#*after write, iclass 23, count 0 2006.161.07:37:22.63#ibcon#*before return 0, iclass 23, count 0 2006.161.07:37:22.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:22.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:37:22.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:37:22.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:37:22.63$vc4f8/vb=5,4 2006.161.07:37:22.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:37:22.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:37:22.63#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:22.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:22.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:22.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:22.69#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:37:22.69#ibcon#first serial, iclass 25, count 2 2006.161.07:37:22.69#ibcon#enter sib2, iclass 25, count 2 2006.161.07:37:22.69#ibcon#flushed, iclass 25, count 2 2006.161.07:37:22.69#ibcon#about to write, iclass 25, count 2 2006.161.07:37:22.69#ibcon#wrote, iclass 25, count 2 2006.161.07:37:22.69#ibcon#about to read 3, iclass 25, count 2 2006.161.07:37:22.71#ibcon#read 3, iclass 25, count 2 2006.161.07:37:22.71#ibcon#about to read 4, iclass 25, count 2 2006.161.07:37:22.71#ibcon#read 4, iclass 25, count 2 2006.161.07:37:22.71#ibcon#about to read 5, iclass 25, count 2 2006.161.07:37:22.71#ibcon#read 5, iclass 25, count 2 2006.161.07:37:22.71#ibcon#about to read 6, iclass 25, count 2 2006.161.07:37:22.71#ibcon#read 6, iclass 25, count 2 2006.161.07:37:22.71#ibcon#end of sib2, iclass 25, count 2 2006.161.07:37:22.71#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:37:22.71#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:37:22.71#ibcon#[27=AT05-04\r\n] 2006.161.07:37:22.71#ibcon#*before write, iclass 25, count 2 2006.161.07:37:22.71#ibcon#enter sib2, iclass 25, count 2 2006.161.07:37:22.71#ibcon#flushed, iclass 25, count 2 2006.161.07:37:22.71#ibcon#about to write, iclass 25, count 2 2006.161.07:37:22.71#ibcon#wrote, iclass 25, count 2 2006.161.07:37:22.71#ibcon#about to read 3, iclass 25, count 2 2006.161.07:37:22.74#ibcon#read 3, iclass 25, count 2 2006.161.07:37:22.74#ibcon#about to read 4, iclass 25, count 2 2006.161.07:37:22.74#ibcon#read 4, iclass 25, count 2 2006.161.07:37:22.74#ibcon#about to read 5, iclass 25, count 2 2006.161.07:37:22.74#ibcon#read 5, iclass 25, count 2 2006.161.07:37:22.74#ibcon#about to read 6, iclass 25, count 2 2006.161.07:37:22.74#ibcon#read 6, iclass 25, count 2 2006.161.07:37:22.74#ibcon#end of sib2, iclass 25, count 2 2006.161.07:37:22.74#ibcon#*after write, iclass 25, count 2 2006.161.07:37:22.74#ibcon#*before return 0, iclass 25, count 2 2006.161.07:37:22.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:22.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:37:22.74#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:37:22.74#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:22.74#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:22.86#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:22.86#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:22.86#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:37:22.86#ibcon#first serial, iclass 25, count 0 2006.161.07:37:22.86#ibcon#enter sib2, iclass 25, count 0 2006.161.07:37:22.86#ibcon#flushed, iclass 25, count 0 2006.161.07:37:22.86#ibcon#about to write, iclass 25, count 0 2006.161.07:37:22.86#ibcon#wrote, iclass 25, count 0 2006.161.07:37:22.86#ibcon#about to read 3, iclass 25, count 0 2006.161.07:37:22.88#ibcon#read 3, iclass 25, count 0 2006.161.07:37:22.88#ibcon#about to read 4, iclass 25, count 0 2006.161.07:37:22.88#ibcon#read 4, iclass 25, count 0 2006.161.07:37:22.88#ibcon#about to read 5, iclass 25, count 0 2006.161.07:37:22.88#ibcon#read 5, iclass 25, count 0 2006.161.07:37:22.88#ibcon#about to read 6, iclass 25, count 0 2006.161.07:37:22.88#ibcon#read 6, iclass 25, count 0 2006.161.07:37:22.88#ibcon#end of sib2, iclass 25, count 0 2006.161.07:37:22.88#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:37:22.88#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:37:22.88#ibcon#[27=USB\r\n] 2006.161.07:37:22.88#ibcon#*before write, iclass 25, count 0 2006.161.07:37:22.88#ibcon#enter sib2, iclass 25, count 0 2006.161.07:37:22.88#ibcon#flushed, iclass 25, count 0 2006.161.07:37:22.88#ibcon#about to write, iclass 25, count 0 2006.161.07:37:22.88#ibcon#wrote, iclass 25, count 0 2006.161.07:37:22.88#ibcon#about to read 3, iclass 25, count 0 2006.161.07:37:22.91#ibcon#read 3, iclass 25, count 0 2006.161.07:37:22.91#ibcon#about to read 4, iclass 25, count 0 2006.161.07:37:22.91#ibcon#read 4, iclass 25, count 0 2006.161.07:37:22.91#ibcon#about to read 5, iclass 25, count 0 2006.161.07:37:22.91#ibcon#read 5, iclass 25, count 0 2006.161.07:37:22.91#ibcon#about to read 6, iclass 25, count 0 2006.161.07:37:22.91#ibcon#read 6, iclass 25, count 0 2006.161.07:37:22.91#ibcon#end of sib2, iclass 25, count 0 2006.161.07:37:22.91#ibcon#*after write, iclass 25, count 0 2006.161.07:37:22.91#ibcon#*before return 0, iclass 25, count 0 2006.161.07:37:22.91#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:22.91#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:37:22.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:37:22.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:37:22.91$vc4f8/vblo=6,752.99 2006.161.07:37:22.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:37:22.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:37:22.91#ibcon#ireg 17 cls_cnt 0 2006.161.07:37:22.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:37:22.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:37:22.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:37:22.91#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:37:22.91#ibcon#first serial, iclass 28, count 0 2006.161.07:37:22.91#ibcon#enter sib2, iclass 28, count 0 2006.161.07:37:22.91#ibcon#flushed, iclass 28, count 0 2006.161.07:37:22.91#ibcon#about to write, iclass 28, count 0 2006.161.07:37:22.91#ibcon#wrote, iclass 28, count 0 2006.161.07:37:22.91#ibcon#about to read 3, iclass 28, count 0 2006.161.07:37:22.93#ibcon#read 3, iclass 28, count 0 2006.161.07:37:22.93#ibcon#about to read 4, iclass 28, count 0 2006.161.07:37:22.93#ibcon#read 4, iclass 28, count 0 2006.161.07:37:22.93#ibcon#about to read 5, iclass 28, count 0 2006.161.07:37:22.93#ibcon#read 5, iclass 28, count 0 2006.161.07:37:22.93#ibcon#about to read 6, iclass 28, count 0 2006.161.07:37:22.93#ibcon#read 6, iclass 28, count 0 2006.161.07:37:22.93#ibcon#end of sib2, iclass 28, count 0 2006.161.07:37:22.93#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:37:22.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:37:22.93#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:37:22.93#ibcon#*before write, iclass 28, count 0 2006.161.07:37:22.93#ibcon#enter sib2, iclass 28, count 0 2006.161.07:37:22.93#ibcon#flushed, iclass 28, count 0 2006.161.07:37:22.93#ibcon#about to write, iclass 28, count 0 2006.161.07:37:22.93#ibcon#wrote, iclass 28, count 0 2006.161.07:37:22.93#ibcon#about to read 3, iclass 28, count 0 2006.161.07:37:22.93#abcon#<5=/04 2.6 5.2 24.15 841001.9\r\n> 2006.161.07:37:22.95#abcon#{5=INTERFACE CLEAR} 2006.161.07:37:22.97#ibcon#read 3, iclass 28, count 0 2006.161.07:37:22.97#ibcon#about to read 4, iclass 28, count 0 2006.161.07:37:22.97#ibcon#read 4, iclass 28, count 0 2006.161.07:37:22.97#ibcon#about to read 5, iclass 28, count 0 2006.161.07:37:22.97#ibcon#read 5, iclass 28, count 0 2006.161.07:37:22.97#ibcon#about to read 6, iclass 28, count 0 2006.161.07:37:22.97#ibcon#read 6, iclass 28, count 0 2006.161.07:37:22.97#ibcon#end of sib2, iclass 28, count 0 2006.161.07:37:22.97#ibcon#*after write, iclass 28, count 0 2006.161.07:37:22.97#ibcon#*before return 0, iclass 28, count 0 2006.161.07:37:22.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:37:22.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:37:22.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:37:22.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:37:22.97$vc4f8/vb=6,4 2006.161.07:37:22.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:37:22.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:37:22.97#ibcon#ireg 11 cls_cnt 2 2006.161.07:37:22.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:37:23.01#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:37:23.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:37:23.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:37:23.04#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:37:23.04#ibcon#first serial, iclass 32, count 2 2006.161.07:37:23.04#ibcon#enter sib2, iclass 32, count 2 2006.161.07:37:23.04#ibcon#flushed, iclass 32, count 2 2006.161.07:37:23.04#ibcon#about to write, iclass 32, count 2 2006.161.07:37:23.04#ibcon#wrote, iclass 32, count 2 2006.161.07:37:23.04#ibcon#about to read 3, iclass 32, count 2 2006.161.07:37:23.06#ibcon#read 3, iclass 32, count 2 2006.161.07:37:23.06#ibcon#about to read 4, iclass 32, count 2 2006.161.07:37:23.06#ibcon#read 4, iclass 32, count 2 2006.161.07:37:23.06#ibcon#about to read 5, iclass 32, count 2 2006.161.07:37:23.06#ibcon#read 5, iclass 32, count 2 2006.161.07:37:23.06#ibcon#about to read 6, iclass 32, count 2 2006.161.07:37:23.06#ibcon#read 6, iclass 32, count 2 2006.161.07:37:23.06#ibcon#end of sib2, iclass 32, count 2 2006.161.07:37:23.06#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:37:23.06#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:37:23.06#ibcon#[27=AT06-04\r\n] 2006.161.07:37:23.06#ibcon#*before write, iclass 32, count 2 2006.161.07:37:23.06#ibcon#enter sib2, iclass 32, count 2 2006.161.07:37:23.06#ibcon#flushed, iclass 32, count 2 2006.161.07:37:23.06#ibcon#about to write, iclass 32, count 2 2006.161.07:37:23.06#ibcon#wrote, iclass 32, count 2 2006.161.07:37:23.06#ibcon#about to read 3, iclass 32, count 2 2006.161.07:37:23.08#ibcon#read 3, iclass 32, count 2 2006.161.07:37:23.08#ibcon#about to read 4, iclass 32, count 2 2006.161.07:37:23.08#ibcon#read 4, iclass 32, count 2 2006.161.07:37:23.08#ibcon#about to read 5, iclass 32, count 2 2006.161.07:37:23.08#ibcon#read 5, iclass 32, count 2 2006.161.07:37:23.08#ibcon#about to read 6, iclass 32, count 2 2006.161.07:37:23.08#ibcon#read 6, iclass 32, count 2 2006.161.07:37:23.08#ibcon#end of sib2, iclass 32, count 2 2006.161.07:37:23.08#ibcon#*after write, iclass 32, count 2 2006.161.07:37:23.08#ibcon#*before return 0, iclass 32, count 2 2006.161.07:37:23.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:37:23.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:37:23.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:37:23.08#ibcon#ireg 7 cls_cnt 0 2006.161.07:37:23.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:37:23.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:37:23.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:37:23.20#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:37:23.20#ibcon#first serial, iclass 32, count 0 2006.161.07:37:23.20#ibcon#enter sib2, iclass 32, count 0 2006.161.07:37:23.20#ibcon#flushed, iclass 32, count 0 2006.161.07:37:23.20#ibcon#about to write, iclass 32, count 0 2006.161.07:37:23.20#ibcon#wrote, iclass 32, count 0 2006.161.07:37:23.20#ibcon#about to read 3, iclass 32, count 0 2006.161.07:37:23.24#ibcon#read 3, iclass 32, count 0 2006.161.07:37:23.24#ibcon#about to read 4, iclass 32, count 0 2006.161.07:37:23.24#ibcon#read 4, iclass 32, count 0 2006.161.07:37:23.24#ibcon#about to read 5, iclass 32, count 0 2006.161.07:37:23.24#ibcon#read 5, iclass 32, count 0 2006.161.07:37:23.24#ibcon#about to read 6, iclass 32, count 0 2006.161.07:37:23.24#ibcon#read 6, iclass 32, count 0 2006.161.07:37:23.24#ibcon#end of sib2, iclass 32, count 0 2006.161.07:37:23.24#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:37:23.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:37:23.24#ibcon#[27=USB\r\n] 2006.161.07:37:23.24#ibcon#*before write, iclass 32, count 0 2006.161.07:37:23.24#ibcon#enter sib2, iclass 32, count 0 2006.161.07:37:23.24#ibcon#flushed, iclass 32, count 0 2006.161.07:37:23.24#ibcon#about to write, iclass 32, count 0 2006.161.07:37:23.24#ibcon#wrote, iclass 32, count 0 2006.161.07:37:23.24#ibcon#about to read 3, iclass 32, count 0 2006.161.07:37:23.27#ibcon#read 3, iclass 32, count 0 2006.161.07:37:23.27#ibcon#about to read 4, iclass 32, count 0 2006.161.07:37:23.27#ibcon#read 4, iclass 32, count 0 2006.161.07:37:23.27#ibcon#about to read 5, iclass 32, count 0 2006.161.07:37:23.27#ibcon#read 5, iclass 32, count 0 2006.161.07:37:23.27#ibcon#about to read 6, iclass 32, count 0 2006.161.07:37:23.27#ibcon#read 6, iclass 32, count 0 2006.161.07:37:23.27#ibcon#end of sib2, iclass 32, count 0 2006.161.07:37:23.27#ibcon#*after write, iclass 32, count 0 2006.161.07:37:23.27#ibcon#*before return 0, iclass 32, count 0 2006.161.07:37:23.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:37:23.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:37:23.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:37:23.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:37:23.27$vc4f8/vabw=wide 2006.161.07:37:23.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.07:37:23.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.07:37:23.27#ibcon#ireg 8 cls_cnt 0 2006.161.07:37:23.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:23.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:23.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:23.27#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:37:23.27#ibcon#first serial, iclass 35, count 0 2006.161.07:37:23.27#ibcon#enter sib2, iclass 35, count 0 2006.161.07:37:23.27#ibcon#flushed, iclass 35, count 0 2006.161.07:37:23.27#ibcon#about to write, iclass 35, count 0 2006.161.07:37:23.27#ibcon#wrote, iclass 35, count 0 2006.161.07:37:23.27#ibcon#about to read 3, iclass 35, count 0 2006.161.07:37:23.29#ibcon#read 3, iclass 35, count 0 2006.161.07:37:23.29#ibcon#about to read 4, iclass 35, count 0 2006.161.07:37:23.29#ibcon#read 4, iclass 35, count 0 2006.161.07:37:23.29#ibcon#about to read 5, iclass 35, count 0 2006.161.07:37:23.29#ibcon#read 5, iclass 35, count 0 2006.161.07:37:23.29#ibcon#about to read 6, iclass 35, count 0 2006.161.07:37:23.29#ibcon#read 6, iclass 35, count 0 2006.161.07:37:23.29#ibcon#end of sib2, iclass 35, count 0 2006.161.07:37:23.29#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:37:23.29#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:37:23.29#ibcon#[25=BW32\r\n] 2006.161.07:37:23.29#ibcon#*before write, iclass 35, count 0 2006.161.07:37:23.29#ibcon#enter sib2, iclass 35, count 0 2006.161.07:37:23.29#ibcon#flushed, iclass 35, count 0 2006.161.07:37:23.29#ibcon#about to write, iclass 35, count 0 2006.161.07:37:23.29#ibcon#wrote, iclass 35, count 0 2006.161.07:37:23.29#ibcon#about to read 3, iclass 35, count 0 2006.161.07:37:23.32#ibcon#read 3, iclass 35, count 0 2006.161.07:37:23.32#ibcon#about to read 4, iclass 35, count 0 2006.161.07:37:23.32#ibcon#read 4, iclass 35, count 0 2006.161.07:37:23.32#ibcon#about to read 5, iclass 35, count 0 2006.161.07:37:23.32#ibcon#read 5, iclass 35, count 0 2006.161.07:37:23.32#ibcon#about to read 6, iclass 35, count 0 2006.161.07:37:23.32#ibcon#read 6, iclass 35, count 0 2006.161.07:37:23.32#ibcon#end of sib2, iclass 35, count 0 2006.161.07:37:23.32#ibcon#*after write, iclass 35, count 0 2006.161.07:37:23.32#ibcon#*before return 0, iclass 35, count 0 2006.161.07:37:23.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:23.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:37:23.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:37:23.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:37:23.32$vc4f8/vbbw=wide 2006.161.07:37:23.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:37:23.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:37:23.32#ibcon#ireg 8 cls_cnt 0 2006.161.07:37:23.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:37:23.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:37:23.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:37:23.39#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:37:23.39#ibcon#first serial, iclass 37, count 0 2006.161.07:37:23.39#ibcon#enter sib2, iclass 37, count 0 2006.161.07:37:23.39#ibcon#flushed, iclass 37, count 0 2006.161.07:37:23.39#ibcon#about to write, iclass 37, count 0 2006.161.07:37:23.39#ibcon#wrote, iclass 37, count 0 2006.161.07:37:23.39#ibcon#about to read 3, iclass 37, count 0 2006.161.07:37:23.41#ibcon#read 3, iclass 37, count 0 2006.161.07:37:23.41#ibcon#about to read 4, iclass 37, count 0 2006.161.07:37:23.41#ibcon#read 4, iclass 37, count 0 2006.161.07:37:23.41#ibcon#about to read 5, iclass 37, count 0 2006.161.07:37:23.41#ibcon#read 5, iclass 37, count 0 2006.161.07:37:23.41#ibcon#about to read 6, iclass 37, count 0 2006.161.07:37:23.41#ibcon#read 6, iclass 37, count 0 2006.161.07:37:23.41#ibcon#end of sib2, iclass 37, count 0 2006.161.07:37:23.41#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:37:23.41#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:37:23.41#ibcon#[27=BW32\r\n] 2006.161.07:37:23.41#ibcon#*before write, iclass 37, count 0 2006.161.07:37:23.41#ibcon#enter sib2, iclass 37, count 0 2006.161.07:37:23.41#ibcon#flushed, iclass 37, count 0 2006.161.07:37:23.41#ibcon#about to write, iclass 37, count 0 2006.161.07:37:23.41#ibcon#wrote, iclass 37, count 0 2006.161.07:37:23.41#ibcon#about to read 3, iclass 37, count 0 2006.161.07:37:23.44#ibcon#read 3, iclass 37, count 0 2006.161.07:37:23.44#ibcon#about to read 4, iclass 37, count 0 2006.161.07:37:23.44#ibcon#read 4, iclass 37, count 0 2006.161.07:37:23.44#ibcon#about to read 5, iclass 37, count 0 2006.161.07:37:23.44#ibcon#read 5, iclass 37, count 0 2006.161.07:37:23.44#ibcon#about to read 6, iclass 37, count 0 2006.161.07:37:23.44#ibcon#read 6, iclass 37, count 0 2006.161.07:37:23.44#ibcon#end of sib2, iclass 37, count 0 2006.161.07:37:23.44#ibcon#*after write, iclass 37, count 0 2006.161.07:37:23.44#ibcon#*before return 0, iclass 37, count 0 2006.161.07:37:23.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:37:23.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:37:23.44#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:37:23.44#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:37:23.44$4f8m12a/ifd4f 2006.161.07:37:23.44$ifd4f/lo= 2006.161.07:37:23.44$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:37:23.44$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:37:23.44$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:37:23.44$ifd4f/patch= 2006.161.07:37:23.44$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:37:23.44$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:37:23.44$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:37:23.44$4f8m12a/"form=m,16.000,1:2 2006.161.07:37:23.44$4f8m12a/"tpicd 2006.161.07:37:23.44$4f8m12a/echo=off 2006.161.07:37:23.44$4f8m12a/xlog=off 2006.161.07:37:23.44:!2006.161.07:38:00 2006.161.07:37:44.14#trakl#Source acquired 2006.161.07:37:46.14#flagr#flagr/antenna,acquired 2006.161.07:38:00.00:preob 2006.161.07:38:00.14/onsource/TRACKING 2006.161.07:38:00.14:!2006.161.07:38:10 2006.161.07:38:10.00:data_valid=on 2006.161.07:38:10.00:midob 2006.161.07:38:10.14/onsource/TRACKING 2006.161.07:38:10.14/wx/24.14,1001.9,85 2006.161.07:38:10.33/cable/+6.4959E-03 2006.161.07:38:11.42/va/01,08,usb,yes,29,30 2006.161.07:38:11.42/va/02,07,usb,yes,29,30 2006.161.07:38:11.42/va/03,06,usb,yes,30,31 2006.161.07:38:11.42/va/04,07,usb,yes,30,32 2006.161.07:38:11.42/va/05,07,usb,yes,29,31 2006.161.07:38:11.42/va/06,06,usb,yes,29,28 2006.161.07:38:11.42/va/07,06,usb,yes,29,29 2006.161.07:38:11.42/va/08,07,usb,yes,27,27 2006.161.07:38:11.65/valo/01,532.99,yes,locked 2006.161.07:38:11.65/valo/02,572.99,yes,locked 2006.161.07:38:11.65/valo/03,672.99,yes,locked 2006.161.07:38:11.65/valo/04,832.99,yes,locked 2006.161.07:38:11.65/valo/05,652.99,yes,locked 2006.161.07:38:11.65/valo/06,772.99,yes,locked 2006.161.07:38:11.65/valo/07,832.99,yes,locked 2006.161.07:38:11.65/valo/08,852.99,yes,locked 2006.161.07:38:12.74/vb/01,04,usb,yes,29,28 2006.161.07:38:12.74/vb/02,04,usb,yes,31,32 2006.161.07:38:12.74/vb/03,04,usb,yes,27,31 2006.161.07:38:12.74/vb/04,04,usb,yes,28,28 2006.161.07:38:12.74/vb/05,04,usb,yes,27,30 2006.161.07:38:12.74/vb/06,04,usb,yes,28,30 2006.161.07:38:12.74/vb/07,04,usb,yes,29,29 2006.161.07:38:12.74/vb/08,04,usb,yes,27,30 2006.161.07:38:12.97/vblo/01,632.99,yes,locked 2006.161.07:38:12.97/vblo/02,640.99,yes,locked 2006.161.07:38:12.97/vblo/03,656.99,yes,locked 2006.161.07:38:12.97/vblo/04,712.99,yes,locked 2006.161.07:38:12.97/vblo/05,744.99,yes,locked 2006.161.07:38:12.97/vblo/06,752.99,yes,locked 2006.161.07:38:12.97/vblo/07,734.99,yes,locked 2006.161.07:38:12.97/vblo/08,744.99,yes,locked 2006.161.07:38:13.12/vabw/8 2006.161.07:38:13.27/vbbw/8 2006.161.07:38:13.47/xfe/off,on,15.0 2006.161.07:38:13.86/ifatt/23,28,28,28 2006.161.07:38:14.08/fmout-gps/S +4.48E-07 2006.161.07:38:14.16:!2006.161.07:39:10 2006.161.07:39:10.00:data_valid=off 2006.161.07:39:10.01:postob 2006.161.07:39:10.09/cable/+6.4998E-03 2006.161.07:39:10.09/wx/24.13,1001.9,85 2006.161.07:39:11.08/fmout-gps/S +4.47E-07 2006.161.07:39:11.08:scan_name=161-0740,k06161,60 2006.161.07:39:11.09:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.161.07:39:11.14#flagr#flagr/antenna,new-source 2006.161.07:39:12.14:checkk5 2006.161.07:39:12.86/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:39:13.29/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:39:13.69/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:39:14.08/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:39:14.49/chk_obsdata//k5ts1/T1610738??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:39:14.95/chk_obsdata//k5ts2/T1610738??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:39:15.64/chk_obsdata//k5ts3/T1610738??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:39:16.11/chk_obsdata//k5ts4/T1610738??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:39:17.45/k5log//k5ts1_log_newline 2006.161.07:39:18.69/k5log//k5ts2_log_newline 2006.161.07:39:19.38/k5log//k5ts3_log_newline 2006.161.07:39:20.44/k5log//k5ts4_log_newline 2006.161.07:39:20.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:39:20.46:4f8m12a=1 2006.161.07:39:20.46$4f8m12a/echo=on 2006.161.07:39:20.46$4f8m12a/pcalon 2006.161.07:39:20.46$pcalon/"no phase cal control is implemented here 2006.161.07:39:20.46$4f8m12a/"tpicd=stop 2006.161.07:39:20.46$4f8m12a/vc4f8 2006.161.07:39:20.46$vc4f8/valo=1,532.99 2006.161.07:39:20.47#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:39:20.47#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:39:20.47#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:20.47#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:20.47#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:20.47#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:20.47#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:39:20.47#ibcon#first serial, iclass 12, count 0 2006.161.07:39:20.47#ibcon#enter sib2, iclass 12, count 0 2006.161.07:39:20.47#ibcon#flushed, iclass 12, count 0 2006.161.07:39:20.47#ibcon#about to write, iclass 12, count 0 2006.161.07:39:20.47#ibcon#wrote, iclass 12, count 0 2006.161.07:39:20.47#ibcon#about to read 3, iclass 12, count 0 2006.161.07:39:20.48#ibcon#read 3, iclass 12, count 0 2006.161.07:39:20.48#ibcon#about to read 4, iclass 12, count 0 2006.161.07:39:20.48#ibcon#read 4, iclass 12, count 0 2006.161.07:39:20.48#ibcon#about to read 5, iclass 12, count 0 2006.161.07:39:20.48#ibcon#read 5, iclass 12, count 0 2006.161.07:39:20.48#ibcon#about to read 6, iclass 12, count 0 2006.161.07:39:20.48#ibcon#read 6, iclass 12, count 0 2006.161.07:39:20.48#ibcon#end of sib2, iclass 12, count 0 2006.161.07:39:20.48#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:39:20.48#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:39:20.48#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:39:20.48#ibcon#*before write, iclass 12, count 0 2006.161.07:39:20.48#ibcon#enter sib2, iclass 12, count 0 2006.161.07:39:20.48#ibcon#flushed, iclass 12, count 0 2006.161.07:39:20.48#ibcon#about to write, iclass 12, count 0 2006.161.07:39:20.48#ibcon#wrote, iclass 12, count 0 2006.161.07:39:20.48#ibcon#about to read 3, iclass 12, count 0 2006.161.07:39:20.53#ibcon#read 3, iclass 12, count 0 2006.161.07:39:20.53#ibcon#about to read 4, iclass 12, count 0 2006.161.07:39:20.53#ibcon#read 4, iclass 12, count 0 2006.161.07:39:20.53#ibcon#about to read 5, iclass 12, count 0 2006.161.07:39:20.53#ibcon#read 5, iclass 12, count 0 2006.161.07:39:20.53#ibcon#about to read 6, iclass 12, count 0 2006.161.07:39:20.53#ibcon#read 6, iclass 12, count 0 2006.161.07:39:20.53#ibcon#end of sib2, iclass 12, count 0 2006.161.07:39:20.53#ibcon#*after write, iclass 12, count 0 2006.161.07:39:20.53#ibcon#*before return 0, iclass 12, count 0 2006.161.07:39:20.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:20.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:20.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:39:20.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:39:20.53$vc4f8/va=1,8 2006.161.07:39:20.53#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:39:20.53#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:39:20.53#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:20.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:20.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:20.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:20.53#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:39:20.53#ibcon#first serial, iclass 14, count 2 2006.161.07:39:20.53#ibcon#enter sib2, iclass 14, count 2 2006.161.07:39:20.53#ibcon#flushed, iclass 14, count 2 2006.161.07:39:20.53#ibcon#about to write, iclass 14, count 2 2006.161.07:39:20.53#ibcon#wrote, iclass 14, count 2 2006.161.07:39:20.53#ibcon#about to read 3, iclass 14, count 2 2006.161.07:39:20.55#ibcon#read 3, iclass 14, count 2 2006.161.07:39:20.55#ibcon#about to read 4, iclass 14, count 2 2006.161.07:39:20.55#ibcon#read 4, iclass 14, count 2 2006.161.07:39:20.55#ibcon#about to read 5, iclass 14, count 2 2006.161.07:39:20.55#ibcon#read 5, iclass 14, count 2 2006.161.07:39:20.55#ibcon#about to read 6, iclass 14, count 2 2006.161.07:39:20.55#ibcon#read 6, iclass 14, count 2 2006.161.07:39:20.55#ibcon#end of sib2, iclass 14, count 2 2006.161.07:39:20.55#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:39:20.55#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:39:20.55#ibcon#[25=AT01-08\r\n] 2006.161.07:39:20.55#ibcon#*before write, iclass 14, count 2 2006.161.07:39:20.55#ibcon#enter sib2, iclass 14, count 2 2006.161.07:39:20.55#ibcon#flushed, iclass 14, count 2 2006.161.07:39:20.55#ibcon#about to write, iclass 14, count 2 2006.161.07:39:20.55#ibcon#wrote, iclass 14, count 2 2006.161.07:39:20.55#ibcon#about to read 3, iclass 14, count 2 2006.161.07:39:20.58#ibcon#read 3, iclass 14, count 2 2006.161.07:39:20.58#ibcon#about to read 4, iclass 14, count 2 2006.161.07:39:20.58#ibcon#read 4, iclass 14, count 2 2006.161.07:39:20.58#ibcon#about to read 5, iclass 14, count 2 2006.161.07:39:20.58#ibcon#read 5, iclass 14, count 2 2006.161.07:39:20.58#ibcon#about to read 6, iclass 14, count 2 2006.161.07:39:20.58#ibcon#read 6, iclass 14, count 2 2006.161.07:39:20.58#ibcon#end of sib2, iclass 14, count 2 2006.161.07:39:20.58#ibcon#*after write, iclass 14, count 2 2006.161.07:39:20.58#ibcon#*before return 0, iclass 14, count 2 2006.161.07:39:20.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:20.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:20.58#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:39:20.58#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:20.58#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:20.70#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:20.70#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:20.70#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:39:20.70#ibcon#first serial, iclass 14, count 0 2006.161.07:39:20.70#ibcon#enter sib2, iclass 14, count 0 2006.161.07:39:20.70#ibcon#flushed, iclass 14, count 0 2006.161.07:39:20.70#ibcon#about to write, iclass 14, count 0 2006.161.07:39:20.70#ibcon#wrote, iclass 14, count 0 2006.161.07:39:20.70#ibcon#about to read 3, iclass 14, count 0 2006.161.07:39:20.72#ibcon#read 3, iclass 14, count 0 2006.161.07:39:20.72#ibcon#about to read 4, iclass 14, count 0 2006.161.07:39:20.72#ibcon#read 4, iclass 14, count 0 2006.161.07:39:20.72#ibcon#about to read 5, iclass 14, count 0 2006.161.07:39:20.72#ibcon#read 5, iclass 14, count 0 2006.161.07:39:20.72#ibcon#about to read 6, iclass 14, count 0 2006.161.07:39:20.72#ibcon#read 6, iclass 14, count 0 2006.161.07:39:20.72#ibcon#end of sib2, iclass 14, count 0 2006.161.07:39:20.72#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:39:20.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:39:20.72#ibcon#[25=USB\r\n] 2006.161.07:39:20.72#ibcon#*before write, iclass 14, count 0 2006.161.07:39:20.72#ibcon#enter sib2, iclass 14, count 0 2006.161.07:39:20.72#ibcon#flushed, iclass 14, count 0 2006.161.07:39:20.72#ibcon#about to write, iclass 14, count 0 2006.161.07:39:20.72#ibcon#wrote, iclass 14, count 0 2006.161.07:39:20.72#ibcon#about to read 3, iclass 14, count 0 2006.161.07:39:20.75#ibcon#read 3, iclass 14, count 0 2006.161.07:39:20.75#ibcon#about to read 4, iclass 14, count 0 2006.161.07:39:20.75#ibcon#read 4, iclass 14, count 0 2006.161.07:39:20.75#ibcon#about to read 5, iclass 14, count 0 2006.161.07:39:20.75#ibcon#read 5, iclass 14, count 0 2006.161.07:39:20.75#ibcon#about to read 6, iclass 14, count 0 2006.161.07:39:20.75#ibcon#read 6, iclass 14, count 0 2006.161.07:39:20.75#ibcon#end of sib2, iclass 14, count 0 2006.161.07:39:20.75#ibcon#*after write, iclass 14, count 0 2006.161.07:39:20.75#ibcon#*before return 0, iclass 14, count 0 2006.161.07:39:20.75#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:20.75#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:20.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:39:20.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:39:20.75$vc4f8/valo=2,572.99 2006.161.07:39:20.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:39:20.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:39:20.75#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:20.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:20.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:20.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:20.75#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:39:20.75#ibcon#first serial, iclass 16, count 0 2006.161.07:39:20.75#ibcon#enter sib2, iclass 16, count 0 2006.161.07:39:20.75#ibcon#flushed, iclass 16, count 0 2006.161.07:39:20.75#ibcon#about to write, iclass 16, count 0 2006.161.07:39:20.75#ibcon#wrote, iclass 16, count 0 2006.161.07:39:20.75#ibcon#about to read 3, iclass 16, count 0 2006.161.07:39:20.77#ibcon#read 3, iclass 16, count 0 2006.161.07:39:20.77#ibcon#about to read 4, iclass 16, count 0 2006.161.07:39:20.77#ibcon#read 4, iclass 16, count 0 2006.161.07:39:20.77#ibcon#about to read 5, iclass 16, count 0 2006.161.07:39:20.77#ibcon#read 5, iclass 16, count 0 2006.161.07:39:20.77#ibcon#about to read 6, iclass 16, count 0 2006.161.07:39:20.77#ibcon#read 6, iclass 16, count 0 2006.161.07:39:20.77#ibcon#end of sib2, iclass 16, count 0 2006.161.07:39:20.77#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:39:20.77#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:39:20.77#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:39:20.77#ibcon#*before write, iclass 16, count 0 2006.161.07:39:20.77#ibcon#enter sib2, iclass 16, count 0 2006.161.07:39:20.77#ibcon#flushed, iclass 16, count 0 2006.161.07:39:20.77#ibcon#about to write, iclass 16, count 0 2006.161.07:39:20.77#ibcon#wrote, iclass 16, count 0 2006.161.07:39:20.77#ibcon#about to read 3, iclass 16, count 0 2006.161.07:39:20.81#ibcon#read 3, iclass 16, count 0 2006.161.07:39:20.81#ibcon#about to read 4, iclass 16, count 0 2006.161.07:39:20.81#ibcon#read 4, iclass 16, count 0 2006.161.07:39:20.81#ibcon#about to read 5, iclass 16, count 0 2006.161.07:39:20.81#ibcon#read 5, iclass 16, count 0 2006.161.07:39:20.81#ibcon#about to read 6, iclass 16, count 0 2006.161.07:39:20.81#ibcon#read 6, iclass 16, count 0 2006.161.07:39:20.81#ibcon#end of sib2, iclass 16, count 0 2006.161.07:39:20.81#ibcon#*after write, iclass 16, count 0 2006.161.07:39:20.81#ibcon#*before return 0, iclass 16, count 0 2006.161.07:39:20.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:20.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:20.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:39:20.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:39:20.81$vc4f8/va=2,7 2006.161.07:39:20.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:39:20.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:39:20.81#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:20.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:20.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:20.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:20.87#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:39:20.87#ibcon#first serial, iclass 18, count 2 2006.161.07:39:20.87#ibcon#enter sib2, iclass 18, count 2 2006.161.07:39:20.87#ibcon#flushed, iclass 18, count 2 2006.161.07:39:20.87#ibcon#about to write, iclass 18, count 2 2006.161.07:39:20.87#ibcon#wrote, iclass 18, count 2 2006.161.07:39:20.87#ibcon#about to read 3, iclass 18, count 2 2006.161.07:39:20.90#ibcon#read 3, iclass 18, count 2 2006.161.07:39:20.90#ibcon#about to read 4, iclass 18, count 2 2006.161.07:39:20.90#ibcon#read 4, iclass 18, count 2 2006.161.07:39:20.90#ibcon#about to read 5, iclass 18, count 2 2006.161.07:39:20.90#ibcon#read 5, iclass 18, count 2 2006.161.07:39:20.90#ibcon#about to read 6, iclass 18, count 2 2006.161.07:39:20.90#ibcon#read 6, iclass 18, count 2 2006.161.07:39:20.90#ibcon#end of sib2, iclass 18, count 2 2006.161.07:39:20.90#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:39:20.90#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:39:20.90#ibcon#[25=AT02-07\r\n] 2006.161.07:39:20.90#ibcon#*before write, iclass 18, count 2 2006.161.07:39:20.90#ibcon#enter sib2, iclass 18, count 2 2006.161.07:39:20.90#ibcon#flushed, iclass 18, count 2 2006.161.07:39:20.90#ibcon#about to write, iclass 18, count 2 2006.161.07:39:20.90#ibcon#wrote, iclass 18, count 2 2006.161.07:39:20.90#ibcon#about to read 3, iclass 18, count 2 2006.161.07:39:20.93#ibcon#read 3, iclass 18, count 2 2006.161.07:39:20.93#ibcon#about to read 4, iclass 18, count 2 2006.161.07:39:20.93#ibcon#read 4, iclass 18, count 2 2006.161.07:39:20.93#ibcon#about to read 5, iclass 18, count 2 2006.161.07:39:20.93#ibcon#read 5, iclass 18, count 2 2006.161.07:39:20.93#ibcon#about to read 6, iclass 18, count 2 2006.161.07:39:20.93#ibcon#read 6, iclass 18, count 2 2006.161.07:39:20.93#ibcon#end of sib2, iclass 18, count 2 2006.161.07:39:20.93#ibcon#*after write, iclass 18, count 2 2006.161.07:39:20.93#ibcon#*before return 0, iclass 18, count 2 2006.161.07:39:20.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:20.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:20.93#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:39:20.93#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:20.93#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:21.05#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:21.05#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:21.05#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:39:21.05#ibcon#first serial, iclass 18, count 0 2006.161.07:39:21.05#ibcon#enter sib2, iclass 18, count 0 2006.161.07:39:21.05#ibcon#flushed, iclass 18, count 0 2006.161.07:39:21.05#ibcon#about to write, iclass 18, count 0 2006.161.07:39:21.05#ibcon#wrote, iclass 18, count 0 2006.161.07:39:21.05#ibcon#about to read 3, iclass 18, count 0 2006.161.07:39:21.09#ibcon#read 3, iclass 18, count 0 2006.161.07:39:21.09#ibcon#about to read 4, iclass 18, count 0 2006.161.07:39:21.09#ibcon#read 4, iclass 18, count 0 2006.161.07:39:21.09#ibcon#about to read 5, iclass 18, count 0 2006.161.07:39:21.09#ibcon#read 5, iclass 18, count 0 2006.161.07:39:21.09#ibcon#about to read 6, iclass 18, count 0 2006.161.07:39:21.09#ibcon#read 6, iclass 18, count 0 2006.161.07:39:21.09#ibcon#end of sib2, iclass 18, count 0 2006.161.07:39:21.09#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:39:21.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:39:21.09#ibcon#[25=USB\r\n] 2006.161.07:39:21.09#ibcon#*before write, iclass 18, count 0 2006.161.07:39:21.09#ibcon#enter sib2, iclass 18, count 0 2006.161.07:39:21.09#ibcon#flushed, iclass 18, count 0 2006.161.07:39:21.09#ibcon#about to write, iclass 18, count 0 2006.161.07:39:21.09#ibcon#wrote, iclass 18, count 0 2006.161.07:39:21.09#ibcon#about to read 3, iclass 18, count 0 2006.161.07:39:21.12#ibcon#read 3, iclass 18, count 0 2006.161.07:39:21.12#ibcon#about to read 4, iclass 18, count 0 2006.161.07:39:21.12#ibcon#read 4, iclass 18, count 0 2006.161.07:39:21.12#ibcon#about to read 5, iclass 18, count 0 2006.161.07:39:21.12#ibcon#read 5, iclass 18, count 0 2006.161.07:39:21.12#ibcon#about to read 6, iclass 18, count 0 2006.161.07:39:21.12#ibcon#read 6, iclass 18, count 0 2006.161.07:39:21.12#ibcon#end of sib2, iclass 18, count 0 2006.161.07:39:21.12#ibcon#*after write, iclass 18, count 0 2006.161.07:39:21.12#ibcon#*before return 0, iclass 18, count 0 2006.161.07:39:21.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:21.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:21.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:39:21.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:39:21.12$vc4f8/valo=3,672.99 2006.161.07:39:21.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:39:21.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:39:21.12#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:21.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:21.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:21.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:21.12#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:39:21.12#ibcon#first serial, iclass 20, count 0 2006.161.07:39:21.12#ibcon#enter sib2, iclass 20, count 0 2006.161.07:39:21.12#ibcon#flushed, iclass 20, count 0 2006.161.07:39:21.12#ibcon#about to write, iclass 20, count 0 2006.161.07:39:21.12#ibcon#wrote, iclass 20, count 0 2006.161.07:39:21.12#ibcon#about to read 3, iclass 20, count 0 2006.161.07:39:21.14#ibcon#read 3, iclass 20, count 0 2006.161.07:39:21.14#ibcon#about to read 4, iclass 20, count 0 2006.161.07:39:21.14#ibcon#read 4, iclass 20, count 0 2006.161.07:39:21.14#ibcon#about to read 5, iclass 20, count 0 2006.161.07:39:21.14#ibcon#read 5, iclass 20, count 0 2006.161.07:39:21.14#ibcon#about to read 6, iclass 20, count 0 2006.161.07:39:21.14#ibcon#read 6, iclass 20, count 0 2006.161.07:39:21.14#ibcon#end of sib2, iclass 20, count 0 2006.161.07:39:21.14#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:39:21.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:39:21.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:39:21.14#ibcon#*before write, iclass 20, count 0 2006.161.07:39:21.14#ibcon#enter sib2, iclass 20, count 0 2006.161.07:39:21.14#ibcon#flushed, iclass 20, count 0 2006.161.07:39:21.14#ibcon#about to write, iclass 20, count 0 2006.161.07:39:21.14#ibcon#wrote, iclass 20, count 0 2006.161.07:39:21.14#ibcon#about to read 3, iclass 20, count 0 2006.161.07:39:21.18#ibcon#read 3, iclass 20, count 0 2006.161.07:39:21.18#ibcon#about to read 4, iclass 20, count 0 2006.161.07:39:21.18#ibcon#read 4, iclass 20, count 0 2006.161.07:39:21.18#ibcon#about to read 5, iclass 20, count 0 2006.161.07:39:21.18#ibcon#read 5, iclass 20, count 0 2006.161.07:39:21.18#ibcon#about to read 6, iclass 20, count 0 2006.161.07:39:21.18#ibcon#read 6, iclass 20, count 0 2006.161.07:39:21.18#ibcon#end of sib2, iclass 20, count 0 2006.161.07:39:21.18#ibcon#*after write, iclass 20, count 0 2006.161.07:39:21.18#ibcon#*before return 0, iclass 20, count 0 2006.161.07:39:21.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:21.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:21.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:39:21.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:39:21.18$vc4f8/va=3,6 2006.161.07:39:21.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:39:21.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:39:21.18#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:21.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:21.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:21.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:21.24#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:39:21.24#ibcon#first serial, iclass 22, count 2 2006.161.07:39:21.24#ibcon#enter sib2, iclass 22, count 2 2006.161.07:39:21.24#ibcon#flushed, iclass 22, count 2 2006.161.07:39:21.24#ibcon#about to write, iclass 22, count 2 2006.161.07:39:21.24#ibcon#wrote, iclass 22, count 2 2006.161.07:39:21.24#ibcon#about to read 3, iclass 22, count 2 2006.161.07:39:21.26#ibcon#read 3, iclass 22, count 2 2006.161.07:39:21.26#ibcon#about to read 4, iclass 22, count 2 2006.161.07:39:21.26#ibcon#read 4, iclass 22, count 2 2006.161.07:39:21.26#ibcon#about to read 5, iclass 22, count 2 2006.161.07:39:21.26#ibcon#read 5, iclass 22, count 2 2006.161.07:39:21.26#ibcon#about to read 6, iclass 22, count 2 2006.161.07:39:21.26#ibcon#read 6, iclass 22, count 2 2006.161.07:39:21.26#ibcon#end of sib2, iclass 22, count 2 2006.161.07:39:21.26#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:39:21.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:39:21.26#ibcon#[25=AT03-06\r\n] 2006.161.07:39:21.26#ibcon#*before write, iclass 22, count 2 2006.161.07:39:21.26#ibcon#enter sib2, iclass 22, count 2 2006.161.07:39:21.26#ibcon#flushed, iclass 22, count 2 2006.161.07:39:21.26#ibcon#about to write, iclass 22, count 2 2006.161.07:39:21.26#ibcon#wrote, iclass 22, count 2 2006.161.07:39:21.26#ibcon#about to read 3, iclass 22, count 2 2006.161.07:39:21.29#ibcon#read 3, iclass 22, count 2 2006.161.07:39:21.29#ibcon#about to read 4, iclass 22, count 2 2006.161.07:39:21.29#ibcon#read 4, iclass 22, count 2 2006.161.07:39:21.29#ibcon#about to read 5, iclass 22, count 2 2006.161.07:39:21.29#ibcon#read 5, iclass 22, count 2 2006.161.07:39:21.29#ibcon#about to read 6, iclass 22, count 2 2006.161.07:39:21.29#ibcon#read 6, iclass 22, count 2 2006.161.07:39:21.29#ibcon#end of sib2, iclass 22, count 2 2006.161.07:39:21.29#ibcon#*after write, iclass 22, count 2 2006.161.07:39:21.29#ibcon#*before return 0, iclass 22, count 2 2006.161.07:39:21.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:21.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:21.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:39:21.29#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:21.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:21.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:21.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:21.41#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:39:21.41#ibcon#first serial, iclass 22, count 0 2006.161.07:39:21.41#ibcon#enter sib2, iclass 22, count 0 2006.161.07:39:21.41#ibcon#flushed, iclass 22, count 0 2006.161.07:39:21.41#ibcon#about to write, iclass 22, count 0 2006.161.07:39:21.41#ibcon#wrote, iclass 22, count 0 2006.161.07:39:21.41#ibcon#about to read 3, iclass 22, count 0 2006.161.07:39:21.43#ibcon#read 3, iclass 22, count 0 2006.161.07:39:21.43#ibcon#about to read 4, iclass 22, count 0 2006.161.07:39:21.43#ibcon#read 4, iclass 22, count 0 2006.161.07:39:21.43#ibcon#about to read 5, iclass 22, count 0 2006.161.07:39:21.43#ibcon#read 5, iclass 22, count 0 2006.161.07:39:21.43#ibcon#about to read 6, iclass 22, count 0 2006.161.07:39:21.43#ibcon#read 6, iclass 22, count 0 2006.161.07:39:21.43#ibcon#end of sib2, iclass 22, count 0 2006.161.07:39:21.43#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:39:21.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:39:21.43#ibcon#[25=USB\r\n] 2006.161.07:39:21.43#ibcon#*before write, iclass 22, count 0 2006.161.07:39:21.43#ibcon#enter sib2, iclass 22, count 0 2006.161.07:39:21.43#ibcon#flushed, iclass 22, count 0 2006.161.07:39:21.43#ibcon#about to write, iclass 22, count 0 2006.161.07:39:21.43#ibcon#wrote, iclass 22, count 0 2006.161.07:39:21.43#ibcon#about to read 3, iclass 22, count 0 2006.161.07:39:21.46#ibcon#read 3, iclass 22, count 0 2006.161.07:39:21.46#ibcon#about to read 4, iclass 22, count 0 2006.161.07:39:21.46#ibcon#read 4, iclass 22, count 0 2006.161.07:39:21.46#ibcon#about to read 5, iclass 22, count 0 2006.161.07:39:21.46#ibcon#read 5, iclass 22, count 0 2006.161.07:39:21.46#ibcon#about to read 6, iclass 22, count 0 2006.161.07:39:21.46#ibcon#read 6, iclass 22, count 0 2006.161.07:39:21.46#ibcon#end of sib2, iclass 22, count 0 2006.161.07:39:21.46#ibcon#*after write, iclass 22, count 0 2006.161.07:39:21.46#ibcon#*before return 0, iclass 22, count 0 2006.161.07:39:21.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:21.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:21.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:39:21.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:39:21.46$vc4f8/valo=4,832.99 2006.161.07:39:21.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:39:21.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:39:21.46#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:21.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:21.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:21.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:21.46#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:39:21.46#ibcon#first serial, iclass 24, count 0 2006.161.07:39:21.46#ibcon#enter sib2, iclass 24, count 0 2006.161.07:39:21.46#ibcon#flushed, iclass 24, count 0 2006.161.07:39:21.46#ibcon#about to write, iclass 24, count 0 2006.161.07:39:21.46#ibcon#wrote, iclass 24, count 0 2006.161.07:39:21.46#ibcon#about to read 3, iclass 24, count 0 2006.161.07:39:21.48#ibcon#read 3, iclass 24, count 0 2006.161.07:39:21.48#ibcon#about to read 4, iclass 24, count 0 2006.161.07:39:21.48#ibcon#read 4, iclass 24, count 0 2006.161.07:39:21.48#ibcon#about to read 5, iclass 24, count 0 2006.161.07:39:21.48#ibcon#read 5, iclass 24, count 0 2006.161.07:39:21.48#ibcon#about to read 6, iclass 24, count 0 2006.161.07:39:21.48#ibcon#read 6, iclass 24, count 0 2006.161.07:39:21.48#ibcon#end of sib2, iclass 24, count 0 2006.161.07:39:21.48#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:39:21.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:39:21.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:39:21.48#ibcon#*before write, iclass 24, count 0 2006.161.07:39:21.48#ibcon#enter sib2, iclass 24, count 0 2006.161.07:39:21.48#ibcon#flushed, iclass 24, count 0 2006.161.07:39:21.48#ibcon#about to write, iclass 24, count 0 2006.161.07:39:21.48#ibcon#wrote, iclass 24, count 0 2006.161.07:39:21.48#ibcon#about to read 3, iclass 24, count 0 2006.161.07:39:21.52#ibcon#read 3, iclass 24, count 0 2006.161.07:39:21.52#ibcon#about to read 4, iclass 24, count 0 2006.161.07:39:21.52#ibcon#read 4, iclass 24, count 0 2006.161.07:39:21.52#ibcon#about to read 5, iclass 24, count 0 2006.161.07:39:21.52#ibcon#read 5, iclass 24, count 0 2006.161.07:39:21.52#ibcon#about to read 6, iclass 24, count 0 2006.161.07:39:21.52#ibcon#read 6, iclass 24, count 0 2006.161.07:39:21.52#ibcon#end of sib2, iclass 24, count 0 2006.161.07:39:21.52#ibcon#*after write, iclass 24, count 0 2006.161.07:39:21.52#ibcon#*before return 0, iclass 24, count 0 2006.161.07:39:21.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:21.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:21.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:39:21.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:39:21.52$vc4f8/va=4,7 2006.161.07:39:21.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:39:21.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:39:21.52#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:21.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:21.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:21.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:21.58#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:39:21.58#ibcon#first serial, iclass 26, count 2 2006.161.07:39:21.58#ibcon#enter sib2, iclass 26, count 2 2006.161.07:39:21.58#ibcon#flushed, iclass 26, count 2 2006.161.07:39:21.58#ibcon#about to write, iclass 26, count 2 2006.161.07:39:21.58#ibcon#wrote, iclass 26, count 2 2006.161.07:39:21.58#ibcon#about to read 3, iclass 26, count 2 2006.161.07:39:21.60#ibcon#read 3, iclass 26, count 2 2006.161.07:39:21.60#ibcon#about to read 4, iclass 26, count 2 2006.161.07:39:21.60#ibcon#read 4, iclass 26, count 2 2006.161.07:39:21.60#ibcon#about to read 5, iclass 26, count 2 2006.161.07:39:21.60#ibcon#read 5, iclass 26, count 2 2006.161.07:39:21.60#ibcon#about to read 6, iclass 26, count 2 2006.161.07:39:21.60#ibcon#read 6, iclass 26, count 2 2006.161.07:39:21.60#ibcon#end of sib2, iclass 26, count 2 2006.161.07:39:21.60#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:39:21.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:39:21.60#ibcon#[25=AT04-07\r\n] 2006.161.07:39:21.60#ibcon#*before write, iclass 26, count 2 2006.161.07:39:21.60#ibcon#enter sib2, iclass 26, count 2 2006.161.07:39:21.60#ibcon#flushed, iclass 26, count 2 2006.161.07:39:21.60#ibcon#about to write, iclass 26, count 2 2006.161.07:39:21.60#ibcon#wrote, iclass 26, count 2 2006.161.07:39:21.60#ibcon#about to read 3, iclass 26, count 2 2006.161.07:39:21.63#ibcon#read 3, iclass 26, count 2 2006.161.07:39:21.63#ibcon#about to read 4, iclass 26, count 2 2006.161.07:39:21.63#ibcon#read 4, iclass 26, count 2 2006.161.07:39:21.63#ibcon#about to read 5, iclass 26, count 2 2006.161.07:39:21.63#ibcon#read 5, iclass 26, count 2 2006.161.07:39:21.63#ibcon#about to read 6, iclass 26, count 2 2006.161.07:39:21.63#ibcon#read 6, iclass 26, count 2 2006.161.07:39:21.63#ibcon#end of sib2, iclass 26, count 2 2006.161.07:39:21.63#ibcon#*after write, iclass 26, count 2 2006.161.07:39:21.63#ibcon#*before return 0, iclass 26, count 2 2006.161.07:39:21.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:21.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:21.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:39:21.63#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:21.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:21.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:21.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:21.75#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:39:21.75#ibcon#first serial, iclass 26, count 0 2006.161.07:39:21.75#ibcon#enter sib2, iclass 26, count 0 2006.161.07:39:21.75#ibcon#flushed, iclass 26, count 0 2006.161.07:39:21.75#ibcon#about to write, iclass 26, count 0 2006.161.07:39:21.75#ibcon#wrote, iclass 26, count 0 2006.161.07:39:21.75#ibcon#about to read 3, iclass 26, count 0 2006.161.07:39:21.77#ibcon#read 3, iclass 26, count 0 2006.161.07:39:21.77#ibcon#about to read 4, iclass 26, count 0 2006.161.07:39:21.77#ibcon#read 4, iclass 26, count 0 2006.161.07:39:21.77#ibcon#about to read 5, iclass 26, count 0 2006.161.07:39:21.77#ibcon#read 5, iclass 26, count 0 2006.161.07:39:21.77#ibcon#about to read 6, iclass 26, count 0 2006.161.07:39:21.77#ibcon#read 6, iclass 26, count 0 2006.161.07:39:21.77#ibcon#end of sib2, iclass 26, count 0 2006.161.07:39:21.77#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:39:21.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:39:21.77#ibcon#[25=USB\r\n] 2006.161.07:39:21.77#ibcon#*before write, iclass 26, count 0 2006.161.07:39:21.77#ibcon#enter sib2, iclass 26, count 0 2006.161.07:39:21.77#ibcon#flushed, iclass 26, count 0 2006.161.07:39:21.77#ibcon#about to write, iclass 26, count 0 2006.161.07:39:21.77#ibcon#wrote, iclass 26, count 0 2006.161.07:39:21.77#ibcon#about to read 3, iclass 26, count 0 2006.161.07:39:21.80#ibcon#read 3, iclass 26, count 0 2006.161.07:39:21.80#ibcon#about to read 4, iclass 26, count 0 2006.161.07:39:21.80#ibcon#read 4, iclass 26, count 0 2006.161.07:39:21.80#ibcon#about to read 5, iclass 26, count 0 2006.161.07:39:21.80#ibcon#read 5, iclass 26, count 0 2006.161.07:39:21.80#ibcon#about to read 6, iclass 26, count 0 2006.161.07:39:21.80#ibcon#read 6, iclass 26, count 0 2006.161.07:39:21.80#ibcon#end of sib2, iclass 26, count 0 2006.161.07:39:21.80#ibcon#*after write, iclass 26, count 0 2006.161.07:39:21.80#ibcon#*before return 0, iclass 26, count 0 2006.161.07:39:21.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:21.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:21.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:39:21.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:39:21.80$vc4f8/valo=5,652.99 2006.161.07:39:21.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:39:21.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:39:21.80#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:21.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:21.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:21.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:21.80#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:39:21.80#ibcon#first serial, iclass 28, count 0 2006.161.07:39:21.80#ibcon#enter sib2, iclass 28, count 0 2006.161.07:39:21.80#ibcon#flushed, iclass 28, count 0 2006.161.07:39:21.80#ibcon#about to write, iclass 28, count 0 2006.161.07:39:21.80#ibcon#wrote, iclass 28, count 0 2006.161.07:39:21.80#ibcon#about to read 3, iclass 28, count 0 2006.161.07:39:21.82#ibcon#read 3, iclass 28, count 0 2006.161.07:39:21.82#ibcon#about to read 4, iclass 28, count 0 2006.161.07:39:21.82#ibcon#read 4, iclass 28, count 0 2006.161.07:39:21.82#ibcon#about to read 5, iclass 28, count 0 2006.161.07:39:21.82#ibcon#read 5, iclass 28, count 0 2006.161.07:39:21.82#ibcon#about to read 6, iclass 28, count 0 2006.161.07:39:21.82#ibcon#read 6, iclass 28, count 0 2006.161.07:39:21.82#ibcon#end of sib2, iclass 28, count 0 2006.161.07:39:21.82#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:39:21.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:39:21.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:39:21.82#ibcon#*before write, iclass 28, count 0 2006.161.07:39:21.82#ibcon#enter sib2, iclass 28, count 0 2006.161.07:39:21.82#ibcon#flushed, iclass 28, count 0 2006.161.07:39:21.82#ibcon#about to write, iclass 28, count 0 2006.161.07:39:21.82#ibcon#wrote, iclass 28, count 0 2006.161.07:39:21.82#ibcon#about to read 3, iclass 28, count 0 2006.161.07:39:21.86#ibcon#read 3, iclass 28, count 0 2006.161.07:39:21.86#ibcon#about to read 4, iclass 28, count 0 2006.161.07:39:21.86#ibcon#read 4, iclass 28, count 0 2006.161.07:39:21.86#ibcon#about to read 5, iclass 28, count 0 2006.161.07:39:21.86#ibcon#read 5, iclass 28, count 0 2006.161.07:39:21.86#ibcon#about to read 6, iclass 28, count 0 2006.161.07:39:21.86#ibcon#read 6, iclass 28, count 0 2006.161.07:39:21.86#ibcon#end of sib2, iclass 28, count 0 2006.161.07:39:21.86#ibcon#*after write, iclass 28, count 0 2006.161.07:39:21.86#ibcon#*before return 0, iclass 28, count 0 2006.161.07:39:21.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:21.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:21.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:39:21.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:39:21.86$vc4f8/va=5,7 2006.161.07:39:21.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.07:39:21.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.07:39:21.86#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:21.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:21.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:21.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:21.92#ibcon#enter wrdev, iclass 30, count 2 2006.161.07:39:21.92#ibcon#first serial, iclass 30, count 2 2006.161.07:39:21.92#ibcon#enter sib2, iclass 30, count 2 2006.161.07:39:21.92#ibcon#flushed, iclass 30, count 2 2006.161.07:39:21.92#ibcon#about to write, iclass 30, count 2 2006.161.07:39:21.92#ibcon#wrote, iclass 30, count 2 2006.161.07:39:21.92#ibcon#about to read 3, iclass 30, count 2 2006.161.07:39:21.94#ibcon#read 3, iclass 30, count 2 2006.161.07:39:21.94#ibcon#about to read 4, iclass 30, count 2 2006.161.07:39:21.94#ibcon#read 4, iclass 30, count 2 2006.161.07:39:21.94#ibcon#about to read 5, iclass 30, count 2 2006.161.07:39:21.94#ibcon#read 5, iclass 30, count 2 2006.161.07:39:21.94#ibcon#about to read 6, iclass 30, count 2 2006.161.07:39:21.94#ibcon#read 6, iclass 30, count 2 2006.161.07:39:21.94#ibcon#end of sib2, iclass 30, count 2 2006.161.07:39:21.94#ibcon#*mode == 0, iclass 30, count 2 2006.161.07:39:21.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.07:39:21.94#ibcon#[25=AT05-07\r\n] 2006.161.07:39:21.94#ibcon#*before write, iclass 30, count 2 2006.161.07:39:21.94#ibcon#enter sib2, iclass 30, count 2 2006.161.07:39:21.94#ibcon#flushed, iclass 30, count 2 2006.161.07:39:21.94#ibcon#about to write, iclass 30, count 2 2006.161.07:39:21.94#ibcon#wrote, iclass 30, count 2 2006.161.07:39:21.94#ibcon#about to read 3, iclass 30, count 2 2006.161.07:39:21.97#ibcon#read 3, iclass 30, count 2 2006.161.07:39:21.97#ibcon#about to read 4, iclass 30, count 2 2006.161.07:39:21.97#ibcon#read 4, iclass 30, count 2 2006.161.07:39:21.97#ibcon#about to read 5, iclass 30, count 2 2006.161.07:39:21.97#ibcon#read 5, iclass 30, count 2 2006.161.07:39:21.97#ibcon#about to read 6, iclass 30, count 2 2006.161.07:39:21.97#ibcon#read 6, iclass 30, count 2 2006.161.07:39:21.97#ibcon#end of sib2, iclass 30, count 2 2006.161.07:39:21.97#ibcon#*after write, iclass 30, count 2 2006.161.07:39:21.97#ibcon#*before return 0, iclass 30, count 2 2006.161.07:39:21.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:21.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:21.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.07:39:21.97#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:21.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:22.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:22.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:22.09#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:39:22.09#ibcon#first serial, iclass 30, count 0 2006.161.07:39:22.09#ibcon#enter sib2, iclass 30, count 0 2006.161.07:39:22.09#ibcon#flushed, iclass 30, count 0 2006.161.07:39:22.09#ibcon#about to write, iclass 30, count 0 2006.161.07:39:22.09#ibcon#wrote, iclass 30, count 0 2006.161.07:39:22.09#ibcon#about to read 3, iclass 30, count 0 2006.161.07:39:22.11#ibcon#read 3, iclass 30, count 0 2006.161.07:39:22.11#ibcon#about to read 4, iclass 30, count 0 2006.161.07:39:22.11#ibcon#read 4, iclass 30, count 0 2006.161.07:39:22.11#ibcon#about to read 5, iclass 30, count 0 2006.161.07:39:22.11#ibcon#read 5, iclass 30, count 0 2006.161.07:39:22.11#ibcon#about to read 6, iclass 30, count 0 2006.161.07:39:22.11#ibcon#read 6, iclass 30, count 0 2006.161.07:39:22.11#ibcon#end of sib2, iclass 30, count 0 2006.161.07:39:22.11#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:39:22.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:39:22.11#ibcon#[25=USB\r\n] 2006.161.07:39:22.11#ibcon#*before write, iclass 30, count 0 2006.161.07:39:22.11#ibcon#enter sib2, iclass 30, count 0 2006.161.07:39:22.11#ibcon#flushed, iclass 30, count 0 2006.161.07:39:22.11#ibcon#about to write, iclass 30, count 0 2006.161.07:39:22.11#ibcon#wrote, iclass 30, count 0 2006.161.07:39:22.11#ibcon#about to read 3, iclass 30, count 0 2006.161.07:39:22.14#ibcon#read 3, iclass 30, count 0 2006.161.07:39:22.14#ibcon#about to read 4, iclass 30, count 0 2006.161.07:39:22.14#ibcon#read 4, iclass 30, count 0 2006.161.07:39:22.14#ibcon#about to read 5, iclass 30, count 0 2006.161.07:39:22.14#ibcon#read 5, iclass 30, count 0 2006.161.07:39:22.14#ibcon#about to read 6, iclass 30, count 0 2006.161.07:39:22.14#ibcon#read 6, iclass 30, count 0 2006.161.07:39:22.14#ibcon#end of sib2, iclass 30, count 0 2006.161.07:39:22.14#ibcon#*after write, iclass 30, count 0 2006.161.07:39:22.14#ibcon#*before return 0, iclass 30, count 0 2006.161.07:39:22.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:22.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:22.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:39:22.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:39:22.14$vc4f8/valo=6,772.99 2006.161.07:39:22.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.07:39:22.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.07:39:22.14#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:22.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:39:22.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:39:22.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:39:22.14#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:39:22.14#ibcon#first serial, iclass 32, count 0 2006.161.07:39:22.14#ibcon#enter sib2, iclass 32, count 0 2006.161.07:39:22.14#ibcon#flushed, iclass 32, count 0 2006.161.07:39:22.14#ibcon#about to write, iclass 32, count 0 2006.161.07:39:22.14#ibcon#wrote, iclass 32, count 0 2006.161.07:39:22.14#ibcon#about to read 3, iclass 32, count 0 2006.161.07:39:22.16#ibcon#read 3, iclass 32, count 0 2006.161.07:39:22.16#ibcon#about to read 4, iclass 32, count 0 2006.161.07:39:22.16#ibcon#read 4, iclass 32, count 0 2006.161.07:39:22.16#ibcon#about to read 5, iclass 32, count 0 2006.161.07:39:22.16#ibcon#read 5, iclass 32, count 0 2006.161.07:39:22.16#ibcon#about to read 6, iclass 32, count 0 2006.161.07:39:22.16#ibcon#read 6, iclass 32, count 0 2006.161.07:39:22.16#ibcon#end of sib2, iclass 32, count 0 2006.161.07:39:22.16#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:39:22.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:39:22.16#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:39:22.16#ibcon#*before write, iclass 32, count 0 2006.161.07:39:22.16#ibcon#enter sib2, iclass 32, count 0 2006.161.07:39:22.16#ibcon#flushed, iclass 32, count 0 2006.161.07:39:22.16#ibcon#about to write, iclass 32, count 0 2006.161.07:39:22.16#ibcon#wrote, iclass 32, count 0 2006.161.07:39:22.16#ibcon#about to read 3, iclass 32, count 0 2006.161.07:39:22.20#ibcon#read 3, iclass 32, count 0 2006.161.07:39:22.20#ibcon#about to read 4, iclass 32, count 0 2006.161.07:39:22.20#ibcon#read 4, iclass 32, count 0 2006.161.07:39:22.20#ibcon#about to read 5, iclass 32, count 0 2006.161.07:39:22.20#ibcon#read 5, iclass 32, count 0 2006.161.07:39:22.20#ibcon#about to read 6, iclass 32, count 0 2006.161.07:39:22.20#ibcon#read 6, iclass 32, count 0 2006.161.07:39:22.20#ibcon#end of sib2, iclass 32, count 0 2006.161.07:39:22.20#ibcon#*after write, iclass 32, count 0 2006.161.07:39:22.20#ibcon#*before return 0, iclass 32, count 0 2006.161.07:39:22.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:39:22.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:39:22.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:39:22.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:39:22.20$vc4f8/va=6,6 2006.161.07:39:22.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.07:39:22.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.07:39:22.20#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:22.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:39:22.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:39:22.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:39:22.26#ibcon#enter wrdev, iclass 34, count 2 2006.161.07:39:22.26#ibcon#first serial, iclass 34, count 2 2006.161.07:39:22.26#ibcon#enter sib2, iclass 34, count 2 2006.161.07:39:22.26#ibcon#flushed, iclass 34, count 2 2006.161.07:39:22.26#ibcon#about to write, iclass 34, count 2 2006.161.07:39:22.26#ibcon#wrote, iclass 34, count 2 2006.161.07:39:22.26#ibcon#about to read 3, iclass 34, count 2 2006.161.07:39:22.28#ibcon#read 3, iclass 34, count 2 2006.161.07:39:22.28#ibcon#about to read 4, iclass 34, count 2 2006.161.07:39:22.28#ibcon#read 4, iclass 34, count 2 2006.161.07:39:22.28#ibcon#about to read 5, iclass 34, count 2 2006.161.07:39:22.28#ibcon#read 5, iclass 34, count 2 2006.161.07:39:22.28#ibcon#about to read 6, iclass 34, count 2 2006.161.07:39:22.28#ibcon#read 6, iclass 34, count 2 2006.161.07:39:22.28#ibcon#end of sib2, iclass 34, count 2 2006.161.07:39:22.28#ibcon#*mode == 0, iclass 34, count 2 2006.161.07:39:22.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.07:39:22.28#ibcon#[25=AT06-06\r\n] 2006.161.07:39:22.28#ibcon#*before write, iclass 34, count 2 2006.161.07:39:22.28#ibcon#enter sib2, iclass 34, count 2 2006.161.07:39:22.28#ibcon#flushed, iclass 34, count 2 2006.161.07:39:22.28#ibcon#about to write, iclass 34, count 2 2006.161.07:39:22.28#ibcon#wrote, iclass 34, count 2 2006.161.07:39:22.28#ibcon#about to read 3, iclass 34, count 2 2006.161.07:39:22.31#ibcon#read 3, iclass 34, count 2 2006.161.07:39:22.31#ibcon#about to read 4, iclass 34, count 2 2006.161.07:39:22.31#ibcon#read 4, iclass 34, count 2 2006.161.07:39:22.31#ibcon#about to read 5, iclass 34, count 2 2006.161.07:39:22.31#ibcon#read 5, iclass 34, count 2 2006.161.07:39:22.31#ibcon#about to read 6, iclass 34, count 2 2006.161.07:39:22.31#ibcon#read 6, iclass 34, count 2 2006.161.07:39:22.31#ibcon#end of sib2, iclass 34, count 2 2006.161.07:39:22.31#ibcon#*after write, iclass 34, count 2 2006.161.07:39:22.31#ibcon#*before return 0, iclass 34, count 2 2006.161.07:39:22.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:39:22.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:39:22.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.07:39:22.31#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:22.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:39:22.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:39:22.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:39:22.43#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:39:22.43#ibcon#first serial, iclass 34, count 0 2006.161.07:39:22.43#ibcon#enter sib2, iclass 34, count 0 2006.161.07:39:22.43#ibcon#flushed, iclass 34, count 0 2006.161.07:39:22.43#ibcon#about to write, iclass 34, count 0 2006.161.07:39:22.43#ibcon#wrote, iclass 34, count 0 2006.161.07:39:22.43#ibcon#about to read 3, iclass 34, count 0 2006.161.07:39:22.45#ibcon#read 3, iclass 34, count 0 2006.161.07:39:22.45#ibcon#about to read 4, iclass 34, count 0 2006.161.07:39:22.45#ibcon#read 4, iclass 34, count 0 2006.161.07:39:22.45#ibcon#about to read 5, iclass 34, count 0 2006.161.07:39:22.45#ibcon#read 5, iclass 34, count 0 2006.161.07:39:22.45#ibcon#about to read 6, iclass 34, count 0 2006.161.07:39:22.45#ibcon#read 6, iclass 34, count 0 2006.161.07:39:22.45#ibcon#end of sib2, iclass 34, count 0 2006.161.07:39:22.45#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:39:22.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:39:22.45#ibcon#[25=USB\r\n] 2006.161.07:39:22.45#ibcon#*before write, iclass 34, count 0 2006.161.07:39:22.45#ibcon#enter sib2, iclass 34, count 0 2006.161.07:39:22.45#ibcon#flushed, iclass 34, count 0 2006.161.07:39:22.45#ibcon#about to write, iclass 34, count 0 2006.161.07:39:22.45#ibcon#wrote, iclass 34, count 0 2006.161.07:39:22.45#ibcon#about to read 3, iclass 34, count 0 2006.161.07:39:22.48#ibcon#read 3, iclass 34, count 0 2006.161.07:39:22.48#ibcon#about to read 4, iclass 34, count 0 2006.161.07:39:22.48#ibcon#read 4, iclass 34, count 0 2006.161.07:39:22.48#ibcon#about to read 5, iclass 34, count 0 2006.161.07:39:22.48#ibcon#read 5, iclass 34, count 0 2006.161.07:39:22.48#ibcon#about to read 6, iclass 34, count 0 2006.161.07:39:22.48#ibcon#read 6, iclass 34, count 0 2006.161.07:39:22.48#ibcon#end of sib2, iclass 34, count 0 2006.161.07:39:22.48#ibcon#*after write, iclass 34, count 0 2006.161.07:39:22.48#ibcon#*before return 0, iclass 34, count 0 2006.161.07:39:22.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:39:22.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:39:22.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:39:22.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:39:22.48$vc4f8/valo=7,832.99 2006.161.07:39:22.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.07:39:22.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.07:39:22.48#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:22.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:39:22.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:39:22.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:39:22.48#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:39:22.48#ibcon#first serial, iclass 36, count 0 2006.161.07:39:22.48#ibcon#enter sib2, iclass 36, count 0 2006.161.07:39:22.48#ibcon#flushed, iclass 36, count 0 2006.161.07:39:22.48#ibcon#about to write, iclass 36, count 0 2006.161.07:39:22.48#ibcon#wrote, iclass 36, count 0 2006.161.07:39:22.48#ibcon#about to read 3, iclass 36, count 0 2006.161.07:39:22.50#ibcon#read 3, iclass 36, count 0 2006.161.07:39:22.50#ibcon#about to read 4, iclass 36, count 0 2006.161.07:39:22.50#ibcon#read 4, iclass 36, count 0 2006.161.07:39:22.50#ibcon#about to read 5, iclass 36, count 0 2006.161.07:39:22.50#ibcon#read 5, iclass 36, count 0 2006.161.07:39:22.50#ibcon#about to read 6, iclass 36, count 0 2006.161.07:39:22.50#ibcon#read 6, iclass 36, count 0 2006.161.07:39:22.50#ibcon#end of sib2, iclass 36, count 0 2006.161.07:39:22.50#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:39:22.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:39:22.50#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:39:22.50#ibcon#*before write, iclass 36, count 0 2006.161.07:39:22.50#ibcon#enter sib2, iclass 36, count 0 2006.161.07:39:22.50#ibcon#flushed, iclass 36, count 0 2006.161.07:39:22.50#ibcon#about to write, iclass 36, count 0 2006.161.07:39:22.50#ibcon#wrote, iclass 36, count 0 2006.161.07:39:22.50#ibcon#about to read 3, iclass 36, count 0 2006.161.07:39:22.54#ibcon#read 3, iclass 36, count 0 2006.161.07:39:22.54#ibcon#about to read 4, iclass 36, count 0 2006.161.07:39:22.54#ibcon#read 4, iclass 36, count 0 2006.161.07:39:22.54#ibcon#about to read 5, iclass 36, count 0 2006.161.07:39:22.54#ibcon#read 5, iclass 36, count 0 2006.161.07:39:22.54#ibcon#about to read 6, iclass 36, count 0 2006.161.07:39:22.54#ibcon#read 6, iclass 36, count 0 2006.161.07:39:22.54#ibcon#end of sib2, iclass 36, count 0 2006.161.07:39:22.54#ibcon#*after write, iclass 36, count 0 2006.161.07:39:22.54#ibcon#*before return 0, iclass 36, count 0 2006.161.07:39:22.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:39:22.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:39:22.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:39:22.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:39:22.54$vc4f8/va=7,6 2006.161.07:39:22.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.07:39:22.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.07:39:22.54#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:22.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:22.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:22.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:22.60#ibcon#enter wrdev, iclass 38, count 2 2006.161.07:39:22.60#ibcon#first serial, iclass 38, count 2 2006.161.07:39:22.60#ibcon#enter sib2, iclass 38, count 2 2006.161.07:39:22.60#ibcon#flushed, iclass 38, count 2 2006.161.07:39:22.60#ibcon#about to write, iclass 38, count 2 2006.161.07:39:22.60#ibcon#wrote, iclass 38, count 2 2006.161.07:39:22.60#ibcon#about to read 3, iclass 38, count 2 2006.161.07:39:22.62#ibcon#read 3, iclass 38, count 2 2006.161.07:39:22.62#ibcon#about to read 4, iclass 38, count 2 2006.161.07:39:22.62#ibcon#read 4, iclass 38, count 2 2006.161.07:39:22.62#ibcon#about to read 5, iclass 38, count 2 2006.161.07:39:22.62#ibcon#read 5, iclass 38, count 2 2006.161.07:39:22.62#ibcon#about to read 6, iclass 38, count 2 2006.161.07:39:22.62#ibcon#read 6, iclass 38, count 2 2006.161.07:39:22.62#ibcon#end of sib2, iclass 38, count 2 2006.161.07:39:22.62#ibcon#*mode == 0, iclass 38, count 2 2006.161.07:39:22.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.07:39:22.62#ibcon#[25=AT07-06\r\n] 2006.161.07:39:22.62#ibcon#*before write, iclass 38, count 2 2006.161.07:39:22.62#ibcon#enter sib2, iclass 38, count 2 2006.161.07:39:22.62#ibcon#flushed, iclass 38, count 2 2006.161.07:39:22.62#ibcon#about to write, iclass 38, count 2 2006.161.07:39:22.62#ibcon#wrote, iclass 38, count 2 2006.161.07:39:22.62#ibcon#about to read 3, iclass 38, count 2 2006.161.07:39:22.65#ibcon#read 3, iclass 38, count 2 2006.161.07:39:22.65#ibcon#about to read 4, iclass 38, count 2 2006.161.07:39:22.65#ibcon#read 4, iclass 38, count 2 2006.161.07:39:22.65#ibcon#about to read 5, iclass 38, count 2 2006.161.07:39:22.65#ibcon#read 5, iclass 38, count 2 2006.161.07:39:22.65#ibcon#about to read 6, iclass 38, count 2 2006.161.07:39:22.65#ibcon#read 6, iclass 38, count 2 2006.161.07:39:22.65#ibcon#end of sib2, iclass 38, count 2 2006.161.07:39:22.65#ibcon#*after write, iclass 38, count 2 2006.161.07:39:22.65#ibcon#*before return 0, iclass 38, count 2 2006.161.07:39:22.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:22.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:22.65#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.07:39:22.65#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:22.65#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:39:22.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:39:22.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:39:22.77#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:39:22.77#ibcon#first serial, iclass 38, count 0 2006.161.07:39:22.77#ibcon#enter sib2, iclass 38, count 0 2006.161.07:39:22.77#ibcon#flushed, iclass 38, count 0 2006.161.07:39:22.77#ibcon#about to write, iclass 38, count 0 2006.161.07:39:22.77#ibcon#wrote, iclass 38, count 0 2006.161.07:39:22.77#ibcon#about to read 3, iclass 38, count 0 2006.161.07:39:22.79#ibcon#read 3, iclass 38, count 0 2006.161.07:39:22.79#ibcon#about to read 4, iclass 38, count 0 2006.161.07:39:22.79#ibcon#read 4, iclass 38, count 0 2006.161.07:39:22.79#ibcon#about to read 5, iclass 38, count 0 2006.161.07:39:22.79#ibcon#read 5, iclass 38, count 0 2006.161.07:39:22.79#ibcon#about to read 6, iclass 38, count 0 2006.161.07:39:22.79#ibcon#read 6, iclass 38, count 0 2006.161.07:39:22.79#ibcon#end of sib2, iclass 38, count 0 2006.161.07:39:22.79#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:39:22.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:39:22.79#ibcon#[25=USB\r\n] 2006.161.07:39:22.79#ibcon#*before write, iclass 38, count 0 2006.161.07:39:22.79#ibcon#enter sib2, iclass 38, count 0 2006.161.07:39:22.79#ibcon#flushed, iclass 38, count 0 2006.161.07:39:22.79#ibcon#about to write, iclass 38, count 0 2006.161.07:39:22.79#ibcon#wrote, iclass 38, count 0 2006.161.07:39:22.79#ibcon#about to read 3, iclass 38, count 0 2006.161.07:39:22.82#ibcon#read 3, iclass 38, count 0 2006.161.07:39:22.82#ibcon#about to read 4, iclass 38, count 0 2006.161.07:39:22.82#ibcon#read 4, iclass 38, count 0 2006.161.07:39:22.82#ibcon#about to read 5, iclass 38, count 0 2006.161.07:39:22.82#ibcon#read 5, iclass 38, count 0 2006.161.07:39:22.82#ibcon#about to read 6, iclass 38, count 0 2006.161.07:39:22.82#ibcon#read 6, iclass 38, count 0 2006.161.07:39:22.82#ibcon#end of sib2, iclass 38, count 0 2006.161.07:39:22.82#ibcon#*after write, iclass 38, count 0 2006.161.07:39:22.82#ibcon#*before return 0, iclass 38, count 0 2006.161.07:39:22.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:39:22.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:39:22.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:39:22.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:39:22.82$vc4f8/valo=8,852.99 2006.161.07:39:22.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:39:22.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:39:22.82#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:22.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:39:22.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:39:22.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:39:22.82#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:39:22.82#ibcon#first serial, iclass 40, count 0 2006.161.07:39:22.82#ibcon#enter sib2, iclass 40, count 0 2006.161.07:39:22.82#ibcon#flushed, iclass 40, count 0 2006.161.07:39:22.82#ibcon#about to write, iclass 40, count 0 2006.161.07:39:22.82#ibcon#wrote, iclass 40, count 0 2006.161.07:39:22.82#ibcon#about to read 3, iclass 40, count 0 2006.161.07:39:22.85#ibcon#read 3, iclass 40, count 0 2006.161.07:39:22.85#ibcon#about to read 4, iclass 40, count 0 2006.161.07:39:22.85#ibcon#read 4, iclass 40, count 0 2006.161.07:39:22.85#ibcon#about to read 5, iclass 40, count 0 2006.161.07:39:22.85#ibcon#read 5, iclass 40, count 0 2006.161.07:39:22.85#ibcon#about to read 6, iclass 40, count 0 2006.161.07:39:22.85#ibcon#read 6, iclass 40, count 0 2006.161.07:39:22.85#ibcon#end of sib2, iclass 40, count 0 2006.161.07:39:22.85#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:39:22.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:39:22.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:39:22.85#ibcon#*before write, iclass 40, count 0 2006.161.07:39:22.85#ibcon#enter sib2, iclass 40, count 0 2006.161.07:39:22.85#ibcon#flushed, iclass 40, count 0 2006.161.07:39:22.85#ibcon#about to write, iclass 40, count 0 2006.161.07:39:22.85#ibcon#wrote, iclass 40, count 0 2006.161.07:39:22.85#ibcon#about to read 3, iclass 40, count 0 2006.161.07:39:22.89#ibcon#read 3, iclass 40, count 0 2006.161.07:39:22.89#ibcon#about to read 4, iclass 40, count 0 2006.161.07:39:22.89#ibcon#read 4, iclass 40, count 0 2006.161.07:39:22.89#ibcon#about to read 5, iclass 40, count 0 2006.161.07:39:22.89#ibcon#read 5, iclass 40, count 0 2006.161.07:39:22.89#ibcon#about to read 6, iclass 40, count 0 2006.161.07:39:22.89#ibcon#read 6, iclass 40, count 0 2006.161.07:39:22.89#ibcon#end of sib2, iclass 40, count 0 2006.161.07:39:22.89#ibcon#*after write, iclass 40, count 0 2006.161.07:39:22.89#ibcon#*before return 0, iclass 40, count 0 2006.161.07:39:22.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:39:22.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:39:22.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:39:22.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:39:22.89$vc4f8/va=8,7 2006.161.07:39:22.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:39:22.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:39:22.89#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:22.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:39:22.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:39:22.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:39:22.94#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:39:22.94#ibcon#first serial, iclass 4, count 2 2006.161.07:39:22.94#ibcon#enter sib2, iclass 4, count 2 2006.161.07:39:22.94#ibcon#flushed, iclass 4, count 2 2006.161.07:39:22.94#ibcon#about to write, iclass 4, count 2 2006.161.07:39:22.94#ibcon#wrote, iclass 4, count 2 2006.161.07:39:22.94#ibcon#about to read 3, iclass 4, count 2 2006.161.07:39:22.96#ibcon#read 3, iclass 4, count 2 2006.161.07:39:22.96#ibcon#about to read 4, iclass 4, count 2 2006.161.07:39:22.96#ibcon#read 4, iclass 4, count 2 2006.161.07:39:22.96#ibcon#about to read 5, iclass 4, count 2 2006.161.07:39:22.96#ibcon#read 5, iclass 4, count 2 2006.161.07:39:22.96#ibcon#about to read 6, iclass 4, count 2 2006.161.07:39:22.96#ibcon#read 6, iclass 4, count 2 2006.161.07:39:22.96#ibcon#end of sib2, iclass 4, count 2 2006.161.07:39:22.96#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:39:22.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:39:22.96#ibcon#[25=AT08-07\r\n] 2006.161.07:39:22.96#ibcon#*before write, iclass 4, count 2 2006.161.07:39:22.96#ibcon#enter sib2, iclass 4, count 2 2006.161.07:39:22.96#ibcon#flushed, iclass 4, count 2 2006.161.07:39:22.96#ibcon#about to write, iclass 4, count 2 2006.161.07:39:22.96#ibcon#wrote, iclass 4, count 2 2006.161.07:39:22.96#ibcon#about to read 3, iclass 4, count 2 2006.161.07:39:22.99#ibcon#read 3, iclass 4, count 2 2006.161.07:39:22.99#ibcon#about to read 4, iclass 4, count 2 2006.161.07:39:22.99#ibcon#read 4, iclass 4, count 2 2006.161.07:39:22.99#ibcon#about to read 5, iclass 4, count 2 2006.161.07:39:22.99#ibcon#read 5, iclass 4, count 2 2006.161.07:39:22.99#ibcon#about to read 6, iclass 4, count 2 2006.161.07:39:22.99#ibcon#read 6, iclass 4, count 2 2006.161.07:39:22.99#ibcon#end of sib2, iclass 4, count 2 2006.161.07:39:22.99#ibcon#*after write, iclass 4, count 2 2006.161.07:39:22.99#ibcon#*before return 0, iclass 4, count 2 2006.161.07:39:22.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:39:22.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:39:22.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:39:22.99#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:22.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:39:23.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:39:23.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:39:23.11#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:39:23.11#ibcon#first serial, iclass 4, count 0 2006.161.07:39:23.11#ibcon#enter sib2, iclass 4, count 0 2006.161.07:39:23.11#ibcon#flushed, iclass 4, count 0 2006.161.07:39:23.11#ibcon#about to write, iclass 4, count 0 2006.161.07:39:23.11#ibcon#wrote, iclass 4, count 0 2006.161.07:39:23.11#ibcon#about to read 3, iclass 4, count 0 2006.161.07:39:23.13#ibcon#read 3, iclass 4, count 0 2006.161.07:39:23.13#ibcon#about to read 4, iclass 4, count 0 2006.161.07:39:23.13#ibcon#read 4, iclass 4, count 0 2006.161.07:39:23.13#ibcon#about to read 5, iclass 4, count 0 2006.161.07:39:23.13#ibcon#read 5, iclass 4, count 0 2006.161.07:39:23.13#ibcon#about to read 6, iclass 4, count 0 2006.161.07:39:23.13#ibcon#read 6, iclass 4, count 0 2006.161.07:39:23.13#ibcon#end of sib2, iclass 4, count 0 2006.161.07:39:23.13#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:39:23.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:39:23.13#ibcon#[25=USB\r\n] 2006.161.07:39:23.13#ibcon#*before write, iclass 4, count 0 2006.161.07:39:23.13#ibcon#enter sib2, iclass 4, count 0 2006.161.07:39:23.13#ibcon#flushed, iclass 4, count 0 2006.161.07:39:23.13#ibcon#about to write, iclass 4, count 0 2006.161.07:39:23.13#ibcon#wrote, iclass 4, count 0 2006.161.07:39:23.13#ibcon#about to read 3, iclass 4, count 0 2006.161.07:39:23.16#ibcon#read 3, iclass 4, count 0 2006.161.07:39:23.16#ibcon#about to read 4, iclass 4, count 0 2006.161.07:39:23.16#ibcon#read 4, iclass 4, count 0 2006.161.07:39:23.16#ibcon#about to read 5, iclass 4, count 0 2006.161.07:39:23.16#ibcon#read 5, iclass 4, count 0 2006.161.07:39:23.16#ibcon#about to read 6, iclass 4, count 0 2006.161.07:39:23.16#ibcon#read 6, iclass 4, count 0 2006.161.07:39:23.16#ibcon#end of sib2, iclass 4, count 0 2006.161.07:39:23.16#ibcon#*after write, iclass 4, count 0 2006.161.07:39:23.16#ibcon#*before return 0, iclass 4, count 0 2006.161.07:39:23.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:39:23.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:39:23.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:39:23.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:39:23.16$vc4f8/vblo=1,632.99 2006.161.07:39:23.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:39:23.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:39:23.16#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:23.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:39:23.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:39:23.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:39:23.16#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:39:23.16#ibcon#first serial, iclass 6, count 0 2006.161.07:39:23.16#ibcon#enter sib2, iclass 6, count 0 2006.161.07:39:23.16#ibcon#flushed, iclass 6, count 0 2006.161.07:39:23.16#ibcon#about to write, iclass 6, count 0 2006.161.07:39:23.16#ibcon#wrote, iclass 6, count 0 2006.161.07:39:23.16#ibcon#about to read 3, iclass 6, count 0 2006.161.07:39:23.18#ibcon#read 3, iclass 6, count 0 2006.161.07:39:23.18#ibcon#about to read 4, iclass 6, count 0 2006.161.07:39:23.18#ibcon#read 4, iclass 6, count 0 2006.161.07:39:23.18#ibcon#about to read 5, iclass 6, count 0 2006.161.07:39:23.18#ibcon#read 5, iclass 6, count 0 2006.161.07:39:23.18#ibcon#about to read 6, iclass 6, count 0 2006.161.07:39:23.18#ibcon#read 6, iclass 6, count 0 2006.161.07:39:23.18#ibcon#end of sib2, iclass 6, count 0 2006.161.07:39:23.18#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:39:23.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:39:23.18#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:39:23.18#ibcon#*before write, iclass 6, count 0 2006.161.07:39:23.18#ibcon#enter sib2, iclass 6, count 0 2006.161.07:39:23.18#ibcon#flushed, iclass 6, count 0 2006.161.07:39:23.18#ibcon#about to write, iclass 6, count 0 2006.161.07:39:23.18#ibcon#wrote, iclass 6, count 0 2006.161.07:39:23.18#ibcon#about to read 3, iclass 6, count 0 2006.161.07:39:23.22#ibcon#read 3, iclass 6, count 0 2006.161.07:39:23.22#ibcon#about to read 4, iclass 6, count 0 2006.161.07:39:23.22#ibcon#read 4, iclass 6, count 0 2006.161.07:39:23.22#ibcon#about to read 5, iclass 6, count 0 2006.161.07:39:23.22#ibcon#read 5, iclass 6, count 0 2006.161.07:39:23.22#ibcon#about to read 6, iclass 6, count 0 2006.161.07:39:23.22#ibcon#read 6, iclass 6, count 0 2006.161.07:39:23.22#ibcon#end of sib2, iclass 6, count 0 2006.161.07:39:23.22#ibcon#*after write, iclass 6, count 0 2006.161.07:39:23.22#ibcon#*before return 0, iclass 6, count 0 2006.161.07:39:23.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:39:23.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:39:23.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:39:23.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:39:23.22$vc4f8/vb=1,4 2006.161.07:39:23.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:39:23.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:39:23.22#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:23.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:39:23.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:39:23.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:39:23.22#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:39:23.22#ibcon#first serial, iclass 10, count 2 2006.161.07:39:23.22#ibcon#enter sib2, iclass 10, count 2 2006.161.07:39:23.22#ibcon#flushed, iclass 10, count 2 2006.161.07:39:23.22#ibcon#about to write, iclass 10, count 2 2006.161.07:39:23.22#ibcon#wrote, iclass 10, count 2 2006.161.07:39:23.22#ibcon#about to read 3, iclass 10, count 2 2006.161.07:39:23.24#ibcon#read 3, iclass 10, count 2 2006.161.07:39:23.24#ibcon#about to read 4, iclass 10, count 2 2006.161.07:39:23.24#ibcon#read 4, iclass 10, count 2 2006.161.07:39:23.24#ibcon#about to read 5, iclass 10, count 2 2006.161.07:39:23.24#ibcon#read 5, iclass 10, count 2 2006.161.07:39:23.24#ibcon#about to read 6, iclass 10, count 2 2006.161.07:39:23.24#ibcon#read 6, iclass 10, count 2 2006.161.07:39:23.24#ibcon#end of sib2, iclass 10, count 2 2006.161.07:39:23.24#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:39:23.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:39:23.24#ibcon#[27=AT01-04\r\n] 2006.161.07:39:23.24#ibcon#*before write, iclass 10, count 2 2006.161.07:39:23.24#ibcon#enter sib2, iclass 10, count 2 2006.161.07:39:23.24#ibcon#flushed, iclass 10, count 2 2006.161.07:39:23.24#ibcon#about to write, iclass 10, count 2 2006.161.07:39:23.24#ibcon#wrote, iclass 10, count 2 2006.161.07:39:23.24#ibcon#about to read 3, iclass 10, count 2 2006.161.07:39:23.27#ibcon#read 3, iclass 10, count 2 2006.161.07:39:23.27#ibcon#about to read 4, iclass 10, count 2 2006.161.07:39:23.27#ibcon#read 4, iclass 10, count 2 2006.161.07:39:23.27#ibcon#about to read 5, iclass 10, count 2 2006.161.07:39:23.27#ibcon#read 5, iclass 10, count 2 2006.161.07:39:23.27#ibcon#about to read 6, iclass 10, count 2 2006.161.07:39:23.27#ibcon#read 6, iclass 10, count 2 2006.161.07:39:23.27#ibcon#end of sib2, iclass 10, count 2 2006.161.07:39:23.27#ibcon#*after write, iclass 10, count 2 2006.161.07:39:23.27#ibcon#*before return 0, iclass 10, count 2 2006.161.07:39:23.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:39:23.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:39:23.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:39:23.27#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:23.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:39:23.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:39:23.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:39:23.39#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:39:23.39#ibcon#first serial, iclass 10, count 0 2006.161.07:39:23.39#ibcon#enter sib2, iclass 10, count 0 2006.161.07:39:23.39#ibcon#flushed, iclass 10, count 0 2006.161.07:39:23.39#ibcon#about to write, iclass 10, count 0 2006.161.07:39:23.39#ibcon#wrote, iclass 10, count 0 2006.161.07:39:23.39#ibcon#about to read 3, iclass 10, count 0 2006.161.07:39:23.41#ibcon#read 3, iclass 10, count 0 2006.161.07:39:23.41#ibcon#about to read 4, iclass 10, count 0 2006.161.07:39:23.41#ibcon#read 4, iclass 10, count 0 2006.161.07:39:23.41#ibcon#about to read 5, iclass 10, count 0 2006.161.07:39:23.41#ibcon#read 5, iclass 10, count 0 2006.161.07:39:23.41#ibcon#about to read 6, iclass 10, count 0 2006.161.07:39:23.41#ibcon#read 6, iclass 10, count 0 2006.161.07:39:23.41#ibcon#end of sib2, iclass 10, count 0 2006.161.07:39:23.41#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:39:23.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:39:23.41#ibcon#[27=USB\r\n] 2006.161.07:39:23.41#ibcon#*before write, iclass 10, count 0 2006.161.07:39:23.41#ibcon#enter sib2, iclass 10, count 0 2006.161.07:39:23.41#ibcon#flushed, iclass 10, count 0 2006.161.07:39:23.41#ibcon#about to write, iclass 10, count 0 2006.161.07:39:23.41#ibcon#wrote, iclass 10, count 0 2006.161.07:39:23.41#ibcon#about to read 3, iclass 10, count 0 2006.161.07:39:23.44#ibcon#read 3, iclass 10, count 0 2006.161.07:39:23.44#ibcon#about to read 4, iclass 10, count 0 2006.161.07:39:23.44#ibcon#read 4, iclass 10, count 0 2006.161.07:39:23.44#ibcon#about to read 5, iclass 10, count 0 2006.161.07:39:23.44#ibcon#read 5, iclass 10, count 0 2006.161.07:39:23.44#ibcon#about to read 6, iclass 10, count 0 2006.161.07:39:23.44#ibcon#read 6, iclass 10, count 0 2006.161.07:39:23.44#ibcon#end of sib2, iclass 10, count 0 2006.161.07:39:23.44#ibcon#*after write, iclass 10, count 0 2006.161.07:39:23.44#ibcon#*before return 0, iclass 10, count 0 2006.161.07:39:23.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:39:23.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:39:23.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:39:23.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:39:23.44$vc4f8/vblo=2,640.99 2006.161.07:39:23.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:39:23.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:39:23.44#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:23.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:23.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:23.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:23.44#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:39:23.44#ibcon#first serial, iclass 12, count 0 2006.161.07:39:23.44#ibcon#enter sib2, iclass 12, count 0 2006.161.07:39:23.44#ibcon#flushed, iclass 12, count 0 2006.161.07:39:23.44#ibcon#about to write, iclass 12, count 0 2006.161.07:39:23.44#ibcon#wrote, iclass 12, count 0 2006.161.07:39:23.44#ibcon#about to read 3, iclass 12, count 0 2006.161.07:39:23.46#ibcon#read 3, iclass 12, count 0 2006.161.07:39:23.46#ibcon#about to read 4, iclass 12, count 0 2006.161.07:39:23.46#ibcon#read 4, iclass 12, count 0 2006.161.07:39:23.46#ibcon#about to read 5, iclass 12, count 0 2006.161.07:39:23.46#ibcon#read 5, iclass 12, count 0 2006.161.07:39:23.46#ibcon#about to read 6, iclass 12, count 0 2006.161.07:39:23.46#ibcon#read 6, iclass 12, count 0 2006.161.07:39:23.46#ibcon#end of sib2, iclass 12, count 0 2006.161.07:39:23.46#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:39:23.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:39:23.46#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:39:23.46#ibcon#*before write, iclass 12, count 0 2006.161.07:39:23.46#ibcon#enter sib2, iclass 12, count 0 2006.161.07:39:23.46#ibcon#flushed, iclass 12, count 0 2006.161.07:39:23.46#ibcon#about to write, iclass 12, count 0 2006.161.07:39:23.46#ibcon#wrote, iclass 12, count 0 2006.161.07:39:23.46#ibcon#about to read 3, iclass 12, count 0 2006.161.07:39:23.50#ibcon#read 3, iclass 12, count 0 2006.161.07:39:23.50#ibcon#about to read 4, iclass 12, count 0 2006.161.07:39:23.50#ibcon#read 4, iclass 12, count 0 2006.161.07:39:23.50#ibcon#about to read 5, iclass 12, count 0 2006.161.07:39:23.50#ibcon#read 5, iclass 12, count 0 2006.161.07:39:23.50#ibcon#about to read 6, iclass 12, count 0 2006.161.07:39:23.50#ibcon#read 6, iclass 12, count 0 2006.161.07:39:23.50#ibcon#end of sib2, iclass 12, count 0 2006.161.07:39:23.50#ibcon#*after write, iclass 12, count 0 2006.161.07:39:23.50#ibcon#*before return 0, iclass 12, count 0 2006.161.07:39:23.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:23.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:39:23.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:39:23.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:39:23.50$vc4f8/vb=2,4 2006.161.07:39:23.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:39:23.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:39:23.50#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:23.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:23.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:23.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:23.56#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:39:23.56#ibcon#first serial, iclass 14, count 2 2006.161.07:39:23.56#ibcon#enter sib2, iclass 14, count 2 2006.161.07:39:23.56#ibcon#flushed, iclass 14, count 2 2006.161.07:39:23.56#ibcon#about to write, iclass 14, count 2 2006.161.07:39:23.56#ibcon#wrote, iclass 14, count 2 2006.161.07:39:23.56#ibcon#about to read 3, iclass 14, count 2 2006.161.07:39:23.58#ibcon#read 3, iclass 14, count 2 2006.161.07:39:23.58#ibcon#about to read 4, iclass 14, count 2 2006.161.07:39:23.58#ibcon#read 4, iclass 14, count 2 2006.161.07:39:23.58#ibcon#about to read 5, iclass 14, count 2 2006.161.07:39:23.58#ibcon#read 5, iclass 14, count 2 2006.161.07:39:23.58#ibcon#about to read 6, iclass 14, count 2 2006.161.07:39:23.58#ibcon#read 6, iclass 14, count 2 2006.161.07:39:23.58#ibcon#end of sib2, iclass 14, count 2 2006.161.07:39:23.58#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:39:23.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:39:23.58#ibcon#[27=AT02-04\r\n] 2006.161.07:39:23.58#ibcon#*before write, iclass 14, count 2 2006.161.07:39:23.58#ibcon#enter sib2, iclass 14, count 2 2006.161.07:39:23.58#ibcon#flushed, iclass 14, count 2 2006.161.07:39:23.58#ibcon#about to write, iclass 14, count 2 2006.161.07:39:23.58#ibcon#wrote, iclass 14, count 2 2006.161.07:39:23.58#ibcon#about to read 3, iclass 14, count 2 2006.161.07:39:23.61#ibcon#read 3, iclass 14, count 2 2006.161.07:39:23.61#ibcon#about to read 4, iclass 14, count 2 2006.161.07:39:23.61#ibcon#read 4, iclass 14, count 2 2006.161.07:39:23.61#ibcon#about to read 5, iclass 14, count 2 2006.161.07:39:23.61#ibcon#read 5, iclass 14, count 2 2006.161.07:39:23.61#ibcon#about to read 6, iclass 14, count 2 2006.161.07:39:23.61#ibcon#read 6, iclass 14, count 2 2006.161.07:39:23.61#ibcon#end of sib2, iclass 14, count 2 2006.161.07:39:23.61#ibcon#*after write, iclass 14, count 2 2006.161.07:39:23.61#ibcon#*before return 0, iclass 14, count 2 2006.161.07:39:23.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:23.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:39:23.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:39:23.61#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:23.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:23.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:23.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:23.73#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:39:23.73#ibcon#first serial, iclass 14, count 0 2006.161.07:39:23.73#ibcon#enter sib2, iclass 14, count 0 2006.161.07:39:23.73#ibcon#flushed, iclass 14, count 0 2006.161.07:39:23.73#ibcon#about to write, iclass 14, count 0 2006.161.07:39:23.73#ibcon#wrote, iclass 14, count 0 2006.161.07:39:23.73#ibcon#about to read 3, iclass 14, count 0 2006.161.07:39:23.75#ibcon#read 3, iclass 14, count 0 2006.161.07:39:23.75#ibcon#about to read 4, iclass 14, count 0 2006.161.07:39:23.75#ibcon#read 4, iclass 14, count 0 2006.161.07:39:23.75#ibcon#about to read 5, iclass 14, count 0 2006.161.07:39:23.75#ibcon#read 5, iclass 14, count 0 2006.161.07:39:23.75#ibcon#about to read 6, iclass 14, count 0 2006.161.07:39:23.75#ibcon#read 6, iclass 14, count 0 2006.161.07:39:23.75#ibcon#end of sib2, iclass 14, count 0 2006.161.07:39:23.75#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:39:23.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:39:23.75#ibcon#[27=USB\r\n] 2006.161.07:39:23.75#ibcon#*before write, iclass 14, count 0 2006.161.07:39:23.75#ibcon#enter sib2, iclass 14, count 0 2006.161.07:39:23.75#ibcon#flushed, iclass 14, count 0 2006.161.07:39:23.75#ibcon#about to write, iclass 14, count 0 2006.161.07:39:23.75#ibcon#wrote, iclass 14, count 0 2006.161.07:39:23.75#ibcon#about to read 3, iclass 14, count 0 2006.161.07:39:23.78#ibcon#read 3, iclass 14, count 0 2006.161.07:39:23.78#ibcon#about to read 4, iclass 14, count 0 2006.161.07:39:23.78#ibcon#read 4, iclass 14, count 0 2006.161.07:39:23.78#ibcon#about to read 5, iclass 14, count 0 2006.161.07:39:23.78#ibcon#read 5, iclass 14, count 0 2006.161.07:39:23.78#ibcon#about to read 6, iclass 14, count 0 2006.161.07:39:23.78#ibcon#read 6, iclass 14, count 0 2006.161.07:39:23.78#ibcon#end of sib2, iclass 14, count 0 2006.161.07:39:23.78#ibcon#*after write, iclass 14, count 0 2006.161.07:39:23.78#ibcon#*before return 0, iclass 14, count 0 2006.161.07:39:23.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:23.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:39:23.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:39:23.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:39:23.78$vc4f8/vblo=3,656.99 2006.161.07:39:23.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:39:23.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:39:23.78#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:23.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:23.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:23.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:23.78#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:39:23.78#ibcon#first serial, iclass 16, count 0 2006.161.07:39:23.78#ibcon#enter sib2, iclass 16, count 0 2006.161.07:39:23.78#ibcon#flushed, iclass 16, count 0 2006.161.07:39:23.78#ibcon#about to write, iclass 16, count 0 2006.161.07:39:23.78#ibcon#wrote, iclass 16, count 0 2006.161.07:39:23.78#ibcon#about to read 3, iclass 16, count 0 2006.161.07:39:23.80#ibcon#read 3, iclass 16, count 0 2006.161.07:39:23.80#ibcon#about to read 4, iclass 16, count 0 2006.161.07:39:23.80#ibcon#read 4, iclass 16, count 0 2006.161.07:39:23.80#ibcon#about to read 5, iclass 16, count 0 2006.161.07:39:23.80#ibcon#read 5, iclass 16, count 0 2006.161.07:39:23.80#ibcon#about to read 6, iclass 16, count 0 2006.161.07:39:23.80#ibcon#read 6, iclass 16, count 0 2006.161.07:39:23.80#ibcon#end of sib2, iclass 16, count 0 2006.161.07:39:23.80#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:39:23.80#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:39:23.80#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:39:23.80#ibcon#*before write, iclass 16, count 0 2006.161.07:39:23.80#ibcon#enter sib2, iclass 16, count 0 2006.161.07:39:23.80#ibcon#flushed, iclass 16, count 0 2006.161.07:39:23.80#ibcon#about to write, iclass 16, count 0 2006.161.07:39:23.80#ibcon#wrote, iclass 16, count 0 2006.161.07:39:23.80#ibcon#about to read 3, iclass 16, count 0 2006.161.07:39:23.84#ibcon#read 3, iclass 16, count 0 2006.161.07:39:23.84#ibcon#about to read 4, iclass 16, count 0 2006.161.07:39:23.84#ibcon#read 4, iclass 16, count 0 2006.161.07:39:23.84#ibcon#about to read 5, iclass 16, count 0 2006.161.07:39:23.84#ibcon#read 5, iclass 16, count 0 2006.161.07:39:23.84#ibcon#about to read 6, iclass 16, count 0 2006.161.07:39:23.84#ibcon#read 6, iclass 16, count 0 2006.161.07:39:23.84#ibcon#end of sib2, iclass 16, count 0 2006.161.07:39:23.84#ibcon#*after write, iclass 16, count 0 2006.161.07:39:23.84#ibcon#*before return 0, iclass 16, count 0 2006.161.07:39:23.84#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:23.84#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:39:23.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:39:23.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:39:23.84$vc4f8/vb=3,4 2006.161.07:39:23.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:39:23.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:39:23.84#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:23.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:23.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:23.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:23.90#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:39:23.90#ibcon#first serial, iclass 18, count 2 2006.161.07:39:23.90#ibcon#enter sib2, iclass 18, count 2 2006.161.07:39:23.90#ibcon#flushed, iclass 18, count 2 2006.161.07:39:23.90#ibcon#about to write, iclass 18, count 2 2006.161.07:39:23.90#ibcon#wrote, iclass 18, count 2 2006.161.07:39:23.90#ibcon#about to read 3, iclass 18, count 2 2006.161.07:39:23.92#ibcon#read 3, iclass 18, count 2 2006.161.07:39:23.92#ibcon#about to read 4, iclass 18, count 2 2006.161.07:39:23.92#ibcon#read 4, iclass 18, count 2 2006.161.07:39:23.92#ibcon#about to read 5, iclass 18, count 2 2006.161.07:39:23.92#ibcon#read 5, iclass 18, count 2 2006.161.07:39:23.92#ibcon#about to read 6, iclass 18, count 2 2006.161.07:39:23.92#ibcon#read 6, iclass 18, count 2 2006.161.07:39:23.92#ibcon#end of sib2, iclass 18, count 2 2006.161.07:39:23.92#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:39:23.92#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:39:23.92#ibcon#[27=AT03-04\r\n] 2006.161.07:39:23.92#ibcon#*before write, iclass 18, count 2 2006.161.07:39:23.92#ibcon#enter sib2, iclass 18, count 2 2006.161.07:39:23.92#ibcon#flushed, iclass 18, count 2 2006.161.07:39:23.92#ibcon#about to write, iclass 18, count 2 2006.161.07:39:23.92#ibcon#wrote, iclass 18, count 2 2006.161.07:39:23.92#ibcon#about to read 3, iclass 18, count 2 2006.161.07:39:23.95#ibcon#read 3, iclass 18, count 2 2006.161.07:39:23.95#ibcon#about to read 4, iclass 18, count 2 2006.161.07:39:23.95#ibcon#read 4, iclass 18, count 2 2006.161.07:39:23.95#ibcon#about to read 5, iclass 18, count 2 2006.161.07:39:23.95#ibcon#read 5, iclass 18, count 2 2006.161.07:39:23.95#ibcon#about to read 6, iclass 18, count 2 2006.161.07:39:23.95#ibcon#read 6, iclass 18, count 2 2006.161.07:39:23.95#ibcon#end of sib2, iclass 18, count 2 2006.161.07:39:23.95#ibcon#*after write, iclass 18, count 2 2006.161.07:39:23.95#ibcon#*before return 0, iclass 18, count 2 2006.161.07:39:23.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:23.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:39:23.95#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:39:23.95#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:23.95#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:24.07#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:24.07#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:24.07#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:39:24.07#ibcon#first serial, iclass 18, count 0 2006.161.07:39:24.07#ibcon#enter sib2, iclass 18, count 0 2006.161.07:39:24.07#ibcon#flushed, iclass 18, count 0 2006.161.07:39:24.07#ibcon#about to write, iclass 18, count 0 2006.161.07:39:24.07#ibcon#wrote, iclass 18, count 0 2006.161.07:39:24.07#ibcon#about to read 3, iclass 18, count 0 2006.161.07:39:24.09#ibcon#read 3, iclass 18, count 0 2006.161.07:39:24.09#ibcon#about to read 4, iclass 18, count 0 2006.161.07:39:24.09#ibcon#read 4, iclass 18, count 0 2006.161.07:39:24.09#ibcon#about to read 5, iclass 18, count 0 2006.161.07:39:24.09#ibcon#read 5, iclass 18, count 0 2006.161.07:39:24.09#ibcon#about to read 6, iclass 18, count 0 2006.161.07:39:24.09#ibcon#read 6, iclass 18, count 0 2006.161.07:39:24.09#ibcon#end of sib2, iclass 18, count 0 2006.161.07:39:24.09#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:39:24.09#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:39:24.09#ibcon#[27=USB\r\n] 2006.161.07:39:24.09#ibcon#*before write, iclass 18, count 0 2006.161.07:39:24.09#ibcon#enter sib2, iclass 18, count 0 2006.161.07:39:24.09#ibcon#flushed, iclass 18, count 0 2006.161.07:39:24.09#ibcon#about to write, iclass 18, count 0 2006.161.07:39:24.09#ibcon#wrote, iclass 18, count 0 2006.161.07:39:24.09#ibcon#about to read 3, iclass 18, count 0 2006.161.07:39:24.12#ibcon#read 3, iclass 18, count 0 2006.161.07:39:24.12#ibcon#about to read 4, iclass 18, count 0 2006.161.07:39:24.12#ibcon#read 4, iclass 18, count 0 2006.161.07:39:24.12#ibcon#about to read 5, iclass 18, count 0 2006.161.07:39:24.12#ibcon#read 5, iclass 18, count 0 2006.161.07:39:24.12#ibcon#about to read 6, iclass 18, count 0 2006.161.07:39:24.12#ibcon#read 6, iclass 18, count 0 2006.161.07:39:24.12#ibcon#end of sib2, iclass 18, count 0 2006.161.07:39:24.12#ibcon#*after write, iclass 18, count 0 2006.161.07:39:24.12#ibcon#*before return 0, iclass 18, count 0 2006.161.07:39:24.12#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:24.12#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:39:24.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:39:24.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:39:24.12$vc4f8/vblo=4,712.99 2006.161.07:39:24.12#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:39:24.12#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:39:24.12#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:24.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:24.12#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:24.12#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:24.12#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:39:24.12#ibcon#first serial, iclass 20, count 0 2006.161.07:39:24.12#ibcon#enter sib2, iclass 20, count 0 2006.161.07:39:24.12#ibcon#flushed, iclass 20, count 0 2006.161.07:39:24.12#ibcon#about to write, iclass 20, count 0 2006.161.07:39:24.12#ibcon#wrote, iclass 20, count 0 2006.161.07:39:24.12#ibcon#about to read 3, iclass 20, count 0 2006.161.07:39:24.14#ibcon#read 3, iclass 20, count 0 2006.161.07:39:24.14#ibcon#about to read 4, iclass 20, count 0 2006.161.07:39:24.14#ibcon#read 4, iclass 20, count 0 2006.161.07:39:24.14#ibcon#about to read 5, iclass 20, count 0 2006.161.07:39:24.14#ibcon#read 5, iclass 20, count 0 2006.161.07:39:24.14#ibcon#about to read 6, iclass 20, count 0 2006.161.07:39:24.14#ibcon#read 6, iclass 20, count 0 2006.161.07:39:24.14#ibcon#end of sib2, iclass 20, count 0 2006.161.07:39:24.14#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:39:24.14#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:39:24.14#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:39:24.14#ibcon#*before write, iclass 20, count 0 2006.161.07:39:24.14#ibcon#enter sib2, iclass 20, count 0 2006.161.07:39:24.14#ibcon#flushed, iclass 20, count 0 2006.161.07:39:24.14#ibcon#about to write, iclass 20, count 0 2006.161.07:39:24.14#ibcon#wrote, iclass 20, count 0 2006.161.07:39:24.14#ibcon#about to read 3, iclass 20, count 0 2006.161.07:39:24.18#ibcon#read 3, iclass 20, count 0 2006.161.07:39:24.18#ibcon#about to read 4, iclass 20, count 0 2006.161.07:39:24.18#ibcon#read 4, iclass 20, count 0 2006.161.07:39:24.18#ibcon#about to read 5, iclass 20, count 0 2006.161.07:39:24.18#ibcon#read 5, iclass 20, count 0 2006.161.07:39:24.18#ibcon#about to read 6, iclass 20, count 0 2006.161.07:39:24.18#ibcon#read 6, iclass 20, count 0 2006.161.07:39:24.18#ibcon#end of sib2, iclass 20, count 0 2006.161.07:39:24.18#ibcon#*after write, iclass 20, count 0 2006.161.07:39:24.18#ibcon#*before return 0, iclass 20, count 0 2006.161.07:39:24.18#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:24.18#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:39:24.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:39:24.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:39:24.18$vc4f8/vb=4,4 2006.161.07:39:24.18#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:39:24.18#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:39:24.18#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:24.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:24.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:24.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:24.24#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:39:24.24#ibcon#first serial, iclass 22, count 2 2006.161.07:39:24.24#ibcon#enter sib2, iclass 22, count 2 2006.161.07:39:24.24#ibcon#flushed, iclass 22, count 2 2006.161.07:39:24.24#ibcon#about to write, iclass 22, count 2 2006.161.07:39:24.24#ibcon#wrote, iclass 22, count 2 2006.161.07:39:24.24#ibcon#about to read 3, iclass 22, count 2 2006.161.07:39:24.26#ibcon#read 3, iclass 22, count 2 2006.161.07:39:24.26#ibcon#about to read 4, iclass 22, count 2 2006.161.07:39:24.26#ibcon#read 4, iclass 22, count 2 2006.161.07:39:24.26#ibcon#about to read 5, iclass 22, count 2 2006.161.07:39:24.26#ibcon#read 5, iclass 22, count 2 2006.161.07:39:24.26#ibcon#about to read 6, iclass 22, count 2 2006.161.07:39:24.26#ibcon#read 6, iclass 22, count 2 2006.161.07:39:24.26#ibcon#end of sib2, iclass 22, count 2 2006.161.07:39:24.26#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:39:24.26#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:39:24.26#ibcon#[27=AT04-04\r\n] 2006.161.07:39:24.26#ibcon#*before write, iclass 22, count 2 2006.161.07:39:24.26#ibcon#enter sib2, iclass 22, count 2 2006.161.07:39:24.26#ibcon#flushed, iclass 22, count 2 2006.161.07:39:24.26#ibcon#about to write, iclass 22, count 2 2006.161.07:39:24.26#ibcon#wrote, iclass 22, count 2 2006.161.07:39:24.26#ibcon#about to read 3, iclass 22, count 2 2006.161.07:39:24.29#ibcon#read 3, iclass 22, count 2 2006.161.07:39:24.29#ibcon#about to read 4, iclass 22, count 2 2006.161.07:39:24.29#ibcon#read 4, iclass 22, count 2 2006.161.07:39:24.29#ibcon#about to read 5, iclass 22, count 2 2006.161.07:39:24.29#ibcon#read 5, iclass 22, count 2 2006.161.07:39:24.29#ibcon#about to read 6, iclass 22, count 2 2006.161.07:39:24.29#ibcon#read 6, iclass 22, count 2 2006.161.07:39:24.29#ibcon#end of sib2, iclass 22, count 2 2006.161.07:39:24.29#ibcon#*after write, iclass 22, count 2 2006.161.07:39:24.29#ibcon#*before return 0, iclass 22, count 2 2006.161.07:39:24.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:24.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:39:24.29#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:39:24.29#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:24.29#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:24.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:24.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:24.41#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:39:24.41#ibcon#first serial, iclass 22, count 0 2006.161.07:39:24.41#ibcon#enter sib2, iclass 22, count 0 2006.161.07:39:24.41#ibcon#flushed, iclass 22, count 0 2006.161.07:39:24.41#ibcon#about to write, iclass 22, count 0 2006.161.07:39:24.41#ibcon#wrote, iclass 22, count 0 2006.161.07:39:24.41#ibcon#about to read 3, iclass 22, count 0 2006.161.07:39:24.43#ibcon#read 3, iclass 22, count 0 2006.161.07:39:24.43#ibcon#about to read 4, iclass 22, count 0 2006.161.07:39:24.43#ibcon#read 4, iclass 22, count 0 2006.161.07:39:24.43#ibcon#about to read 5, iclass 22, count 0 2006.161.07:39:24.43#ibcon#read 5, iclass 22, count 0 2006.161.07:39:24.43#ibcon#about to read 6, iclass 22, count 0 2006.161.07:39:24.43#ibcon#read 6, iclass 22, count 0 2006.161.07:39:24.43#ibcon#end of sib2, iclass 22, count 0 2006.161.07:39:24.43#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:39:24.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:39:24.43#ibcon#[27=USB\r\n] 2006.161.07:39:24.43#ibcon#*before write, iclass 22, count 0 2006.161.07:39:24.43#ibcon#enter sib2, iclass 22, count 0 2006.161.07:39:24.43#ibcon#flushed, iclass 22, count 0 2006.161.07:39:24.43#ibcon#about to write, iclass 22, count 0 2006.161.07:39:24.43#ibcon#wrote, iclass 22, count 0 2006.161.07:39:24.43#ibcon#about to read 3, iclass 22, count 0 2006.161.07:39:24.46#ibcon#read 3, iclass 22, count 0 2006.161.07:39:24.46#ibcon#about to read 4, iclass 22, count 0 2006.161.07:39:24.46#ibcon#read 4, iclass 22, count 0 2006.161.07:39:24.46#ibcon#about to read 5, iclass 22, count 0 2006.161.07:39:24.46#ibcon#read 5, iclass 22, count 0 2006.161.07:39:24.46#ibcon#about to read 6, iclass 22, count 0 2006.161.07:39:24.46#ibcon#read 6, iclass 22, count 0 2006.161.07:39:24.46#ibcon#end of sib2, iclass 22, count 0 2006.161.07:39:24.46#ibcon#*after write, iclass 22, count 0 2006.161.07:39:24.46#ibcon#*before return 0, iclass 22, count 0 2006.161.07:39:24.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:24.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:39:24.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:39:24.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:39:24.46$vc4f8/vblo=5,744.99 2006.161.07:39:24.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:39:24.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:39:24.46#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:24.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:24.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:24.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:24.46#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:39:24.46#ibcon#first serial, iclass 24, count 0 2006.161.07:39:24.46#ibcon#enter sib2, iclass 24, count 0 2006.161.07:39:24.46#ibcon#flushed, iclass 24, count 0 2006.161.07:39:24.46#ibcon#about to write, iclass 24, count 0 2006.161.07:39:24.46#ibcon#wrote, iclass 24, count 0 2006.161.07:39:24.46#ibcon#about to read 3, iclass 24, count 0 2006.161.07:39:24.48#ibcon#read 3, iclass 24, count 0 2006.161.07:39:24.48#ibcon#about to read 4, iclass 24, count 0 2006.161.07:39:24.48#ibcon#read 4, iclass 24, count 0 2006.161.07:39:24.48#ibcon#about to read 5, iclass 24, count 0 2006.161.07:39:24.48#ibcon#read 5, iclass 24, count 0 2006.161.07:39:24.48#ibcon#about to read 6, iclass 24, count 0 2006.161.07:39:24.48#ibcon#read 6, iclass 24, count 0 2006.161.07:39:24.48#ibcon#end of sib2, iclass 24, count 0 2006.161.07:39:24.48#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:39:24.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:39:24.48#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:39:24.48#ibcon#*before write, iclass 24, count 0 2006.161.07:39:24.48#ibcon#enter sib2, iclass 24, count 0 2006.161.07:39:24.48#ibcon#flushed, iclass 24, count 0 2006.161.07:39:24.48#ibcon#about to write, iclass 24, count 0 2006.161.07:39:24.48#ibcon#wrote, iclass 24, count 0 2006.161.07:39:24.48#ibcon#about to read 3, iclass 24, count 0 2006.161.07:39:24.52#ibcon#read 3, iclass 24, count 0 2006.161.07:39:24.52#ibcon#about to read 4, iclass 24, count 0 2006.161.07:39:24.52#ibcon#read 4, iclass 24, count 0 2006.161.07:39:24.52#ibcon#about to read 5, iclass 24, count 0 2006.161.07:39:24.52#ibcon#read 5, iclass 24, count 0 2006.161.07:39:24.52#ibcon#about to read 6, iclass 24, count 0 2006.161.07:39:24.52#ibcon#read 6, iclass 24, count 0 2006.161.07:39:24.52#ibcon#end of sib2, iclass 24, count 0 2006.161.07:39:24.52#ibcon#*after write, iclass 24, count 0 2006.161.07:39:24.52#ibcon#*before return 0, iclass 24, count 0 2006.161.07:39:24.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:24.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:39:24.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:39:24.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:39:24.52$vc4f8/vb=5,4 2006.161.07:39:24.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:39:24.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:39:24.52#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:24.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:24.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:24.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:24.58#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:39:24.58#ibcon#first serial, iclass 26, count 2 2006.161.07:39:24.58#ibcon#enter sib2, iclass 26, count 2 2006.161.07:39:24.58#ibcon#flushed, iclass 26, count 2 2006.161.07:39:24.58#ibcon#about to write, iclass 26, count 2 2006.161.07:39:24.58#ibcon#wrote, iclass 26, count 2 2006.161.07:39:24.58#ibcon#about to read 3, iclass 26, count 2 2006.161.07:39:24.60#ibcon#read 3, iclass 26, count 2 2006.161.07:39:24.60#ibcon#about to read 4, iclass 26, count 2 2006.161.07:39:24.60#ibcon#read 4, iclass 26, count 2 2006.161.07:39:24.60#ibcon#about to read 5, iclass 26, count 2 2006.161.07:39:24.60#ibcon#read 5, iclass 26, count 2 2006.161.07:39:24.60#ibcon#about to read 6, iclass 26, count 2 2006.161.07:39:24.60#ibcon#read 6, iclass 26, count 2 2006.161.07:39:24.60#ibcon#end of sib2, iclass 26, count 2 2006.161.07:39:24.60#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:39:24.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:39:24.60#ibcon#[27=AT05-04\r\n] 2006.161.07:39:24.60#ibcon#*before write, iclass 26, count 2 2006.161.07:39:24.60#ibcon#enter sib2, iclass 26, count 2 2006.161.07:39:24.60#ibcon#flushed, iclass 26, count 2 2006.161.07:39:24.60#ibcon#about to write, iclass 26, count 2 2006.161.07:39:24.60#ibcon#wrote, iclass 26, count 2 2006.161.07:39:24.60#ibcon#about to read 3, iclass 26, count 2 2006.161.07:39:24.63#ibcon#read 3, iclass 26, count 2 2006.161.07:39:24.63#ibcon#about to read 4, iclass 26, count 2 2006.161.07:39:24.63#ibcon#read 4, iclass 26, count 2 2006.161.07:39:24.63#ibcon#about to read 5, iclass 26, count 2 2006.161.07:39:24.63#ibcon#read 5, iclass 26, count 2 2006.161.07:39:24.63#ibcon#about to read 6, iclass 26, count 2 2006.161.07:39:24.63#ibcon#read 6, iclass 26, count 2 2006.161.07:39:24.63#ibcon#end of sib2, iclass 26, count 2 2006.161.07:39:24.63#ibcon#*after write, iclass 26, count 2 2006.161.07:39:24.63#ibcon#*before return 0, iclass 26, count 2 2006.161.07:39:24.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:24.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:39:24.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:39:24.63#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:24.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:24.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:24.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:24.75#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:39:24.75#ibcon#first serial, iclass 26, count 0 2006.161.07:39:24.75#ibcon#enter sib2, iclass 26, count 0 2006.161.07:39:24.75#ibcon#flushed, iclass 26, count 0 2006.161.07:39:24.75#ibcon#about to write, iclass 26, count 0 2006.161.07:39:24.75#ibcon#wrote, iclass 26, count 0 2006.161.07:39:24.75#ibcon#about to read 3, iclass 26, count 0 2006.161.07:39:24.77#ibcon#read 3, iclass 26, count 0 2006.161.07:39:24.77#ibcon#about to read 4, iclass 26, count 0 2006.161.07:39:24.77#ibcon#read 4, iclass 26, count 0 2006.161.07:39:24.77#ibcon#about to read 5, iclass 26, count 0 2006.161.07:39:24.77#ibcon#read 5, iclass 26, count 0 2006.161.07:39:24.77#ibcon#about to read 6, iclass 26, count 0 2006.161.07:39:24.77#ibcon#read 6, iclass 26, count 0 2006.161.07:39:24.77#ibcon#end of sib2, iclass 26, count 0 2006.161.07:39:24.77#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:39:24.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:39:24.77#ibcon#[27=USB\r\n] 2006.161.07:39:24.77#ibcon#*before write, iclass 26, count 0 2006.161.07:39:24.77#ibcon#enter sib2, iclass 26, count 0 2006.161.07:39:24.77#ibcon#flushed, iclass 26, count 0 2006.161.07:39:24.77#ibcon#about to write, iclass 26, count 0 2006.161.07:39:24.77#ibcon#wrote, iclass 26, count 0 2006.161.07:39:24.77#ibcon#about to read 3, iclass 26, count 0 2006.161.07:39:24.80#ibcon#read 3, iclass 26, count 0 2006.161.07:39:24.80#ibcon#about to read 4, iclass 26, count 0 2006.161.07:39:24.80#ibcon#read 4, iclass 26, count 0 2006.161.07:39:24.80#ibcon#about to read 5, iclass 26, count 0 2006.161.07:39:24.80#ibcon#read 5, iclass 26, count 0 2006.161.07:39:24.80#ibcon#about to read 6, iclass 26, count 0 2006.161.07:39:24.80#ibcon#read 6, iclass 26, count 0 2006.161.07:39:24.80#ibcon#end of sib2, iclass 26, count 0 2006.161.07:39:24.80#ibcon#*after write, iclass 26, count 0 2006.161.07:39:24.80#ibcon#*before return 0, iclass 26, count 0 2006.161.07:39:24.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:24.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:39:24.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:39:24.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:39:24.80$vc4f8/vblo=6,752.99 2006.161.07:39:24.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:39:24.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:39:24.80#ibcon#ireg 17 cls_cnt 0 2006.161.07:39:24.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:24.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:24.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:24.80#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:39:24.80#ibcon#first serial, iclass 28, count 0 2006.161.07:39:24.80#ibcon#enter sib2, iclass 28, count 0 2006.161.07:39:24.80#ibcon#flushed, iclass 28, count 0 2006.161.07:39:24.80#ibcon#about to write, iclass 28, count 0 2006.161.07:39:24.80#ibcon#wrote, iclass 28, count 0 2006.161.07:39:24.80#ibcon#about to read 3, iclass 28, count 0 2006.161.07:39:24.82#ibcon#read 3, iclass 28, count 0 2006.161.07:39:24.82#ibcon#about to read 4, iclass 28, count 0 2006.161.07:39:24.82#ibcon#read 4, iclass 28, count 0 2006.161.07:39:24.82#ibcon#about to read 5, iclass 28, count 0 2006.161.07:39:24.82#ibcon#read 5, iclass 28, count 0 2006.161.07:39:24.82#ibcon#about to read 6, iclass 28, count 0 2006.161.07:39:24.82#ibcon#read 6, iclass 28, count 0 2006.161.07:39:24.82#ibcon#end of sib2, iclass 28, count 0 2006.161.07:39:24.82#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:39:24.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:39:24.82#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:39:24.82#ibcon#*before write, iclass 28, count 0 2006.161.07:39:24.82#ibcon#enter sib2, iclass 28, count 0 2006.161.07:39:24.82#ibcon#flushed, iclass 28, count 0 2006.161.07:39:24.82#ibcon#about to write, iclass 28, count 0 2006.161.07:39:24.82#ibcon#wrote, iclass 28, count 0 2006.161.07:39:24.82#ibcon#about to read 3, iclass 28, count 0 2006.161.07:39:24.86#ibcon#read 3, iclass 28, count 0 2006.161.07:39:24.86#ibcon#about to read 4, iclass 28, count 0 2006.161.07:39:24.86#ibcon#read 4, iclass 28, count 0 2006.161.07:39:24.86#ibcon#about to read 5, iclass 28, count 0 2006.161.07:39:24.86#ibcon#read 5, iclass 28, count 0 2006.161.07:39:24.86#ibcon#about to read 6, iclass 28, count 0 2006.161.07:39:24.86#ibcon#read 6, iclass 28, count 0 2006.161.07:39:24.86#ibcon#end of sib2, iclass 28, count 0 2006.161.07:39:24.86#ibcon#*after write, iclass 28, count 0 2006.161.07:39:24.86#ibcon#*before return 0, iclass 28, count 0 2006.161.07:39:24.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:24.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:39:24.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:39:24.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:39:24.86$vc4f8/vb=6,4 2006.161.07:39:24.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.07:39:24.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.07:39:24.86#ibcon#ireg 11 cls_cnt 2 2006.161.07:39:24.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:24.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:24.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:24.92#ibcon#enter wrdev, iclass 30, count 2 2006.161.07:39:24.92#ibcon#first serial, iclass 30, count 2 2006.161.07:39:24.92#ibcon#enter sib2, iclass 30, count 2 2006.161.07:39:24.92#ibcon#flushed, iclass 30, count 2 2006.161.07:39:24.92#ibcon#about to write, iclass 30, count 2 2006.161.07:39:24.92#ibcon#wrote, iclass 30, count 2 2006.161.07:39:24.92#ibcon#about to read 3, iclass 30, count 2 2006.161.07:39:24.94#ibcon#read 3, iclass 30, count 2 2006.161.07:39:24.94#ibcon#about to read 4, iclass 30, count 2 2006.161.07:39:24.94#ibcon#read 4, iclass 30, count 2 2006.161.07:39:24.94#ibcon#about to read 5, iclass 30, count 2 2006.161.07:39:24.94#ibcon#read 5, iclass 30, count 2 2006.161.07:39:24.94#ibcon#about to read 6, iclass 30, count 2 2006.161.07:39:24.94#ibcon#read 6, iclass 30, count 2 2006.161.07:39:24.94#ibcon#end of sib2, iclass 30, count 2 2006.161.07:39:24.94#ibcon#*mode == 0, iclass 30, count 2 2006.161.07:39:24.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.07:39:24.94#ibcon#[27=AT06-04\r\n] 2006.161.07:39:24.94#ibcon#*before write, iclass 30, count 2 2006.161.07:39:24.94#ibcon#enter sib2, iclass 30, count 2 2006.161.07:39:24.94#ibcon#flushed, iclass 30, count 2 2006.161.07:39:24.94#ibcon#about to write, iclass 30, count 2 2006.161.07:39:24.94#ibcon#wrote, iclass 30, count 2 2006.161.07:39:24.94#ibcon#about to read 3, iclass 30, count 2 2006.161.07:39:24.97#ibcon#read 3, iclass 30, count 2 2006.161.07:39:24.97#ibcon#about to read 4, iclass 30, count 2 2006.161.07:39:24.97#ibcon#read 4, iclass 30, count 2 2006.161.07:39:24.97#ibcon#about to read 5, iclass 30, count 2 2006.161.07:39:24.97#ibcon#read 5, iclass 30, count 2 2006.161.07:39:24.97#ibcon#about to read 6, iclass 30, count 2 2006.161.07:39:24.97#ibcon#read 6, iclass 30, count 2 2006.161.07:39:24.97#ibcon#end of sib2, iclass 30, count 2 2006.161.07:39:24.97#ibcon#*after write, iclass 30, count 2 2006.161.07:39:24.97#ibcon#*before return 0, iclass 30, count 2 2006.161.07:39:24.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:24.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:39:24.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.07:39:24.97#ibcon#ireg 7 cls_cnt 0 2006.161.07:39:24.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:25.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:25.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:25.09#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:39:25.09#ibcon#first serial, iclass 30, count 0 2006.161.07:39:25.09#ibcon#enter sib2, iclass 30, count 0 2006.161.07:39:25.09#ibcon#flushed, iclass 30, count 0 2006.161.07:39:25.09#ibcon#about to write, iclass 30, count 0 2006.161.07:39:25.09#ibcon#wrote, iclass 30, count 0 2006.161.07:39:25.09#ibcon#about to read 3, iclass 30, count 0 2006.161.07:39:25.11#ibcon#read 3, iclass 30, count 0 2006.161.07:39:25.11#ibcon#about to read 4, iclass 30, count 0 2006.161.07:39:25.11#ibcon#read 4, iclass 30, count 0 2006.161.07:39:25.11#ibcon#about to read 5, iclass 30, count 0 2006.161.07:39:25.11#ibcon#read 5, iclass 30, count 0 2006.161.07:39:25.11#ibcon#about to read 6, iclass 30, count 0 2006.161.07:39:25.11#ibcon#read 6, iclass 30, count 0 2006.161.07:39:25.11#ibcon#end of sib2, iclass 30, count 0 2006.161.07:39:25.11#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:39:25.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:39:25.11#ibcon#[27=USB\r\n] 2006.161.07:39:25.11#ibcon#*before write, iclass 30, count 0 2006.161.07:39:25.11#ibcon#enter sib2, iclass 30, count 0 2006.161.07:39:25.11#ibcon#flushed, iclass 30, count 0 2006.161.07:39:25.11#ibcon#about to write, iclass 30, count 0 2006.161.07:39:25.11#ibcon#wrote, iclass 30, count 0 2006.161.07:39:25.11#ibcon#about to read 3, iclass 30, count 0 2006.161.07:39:25.12#abcon#<5=/04 2.7 5.2 24.13 851001.9\r\n> 2006.161.07:39:25.14#abcon#{5=INTERFACE CLEAR} 2006.161.07:39:25.14#ibcon#read 3, iclass 30, count 0 2006.161.07:39:25.14#ibcon#about to read 4, iclass 30, count 0 2006.161.07:39:25.14#ibcon#read 4, iclass 30, count 0 2006.161.07:39:25.14#ibcon#about to read 5, iclass 30, count 0 2006.161.07:39:25.14#ibcon#read 5, iclass 30, count 0 2006.161.07:39:25.14#ibcon#about to read 6, iclass 30, count 0 2006.161.07:39:25.14#ibcon#read 6, iclass 30, count 0 2006.161.07:39:25.14#ibcon#end of sib2, iclass 30, count 0 2006.161.07:39:25.14#ibcon#*after write, iclass 30, count 0 2006.161.07:39:25.14#ibcon#*before return 0, iclass 30, count 0 2006.161.07:39:25.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:25.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:39:25.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:39:25.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:39:25.14$vc4f8/vabw=wide 2006.161.07:39:25.14#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.07:39:25.14#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.07:39:25.14#ibcon#ireg 8 cls_cnt 0 2006.161.07:39:25.14#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:39:25.14#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:39:25.14#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:39:25.14#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:39:25.14#ibcon#first serial, iclass 35, count 0 2006.161.07:39:25.14#ibcon#enter sib2, iclass 35, count 0 2006.161.07:39:25.14#ibcon#flushed, iclass 35, count 0 2006.161.07:39:25.14#ibcon#about to write, iclass 35, count 0 2006.161.07:39:25.14#ibcon#wrote, iclass 35, count 0 2006.161.07:39:25.14#ibcon#about to read 3, iclass 35, count 0 2006.161.07:39:25.16#ibcon#read 3, iclass 35, count 0 2006.161.07:39:25.16#ibcon#about to read 4, iclass 35, count 0 2006.161.07:39:25.16#ibcon#read 4, iclass 35, count 0 2006.161.07:39:25.16#ibcon#about to read 5, iclass 35, count 0 2006.161.07:39:25.16#ibcon#read 5, iclass 35, count 0 2006.161.07:39:25.16#ibcon#about to read 6, iclass 35, count 0 2006.161.07:39:25.16#ibcon#read 6, iclass 35, count 0 2006.161.07:39:25.16#ibcon#end of sib2, iclass 35, count 0 2006.161.07:39:25.16#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:39:25.16#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:39:25.16#ibcon#[25=BW32\r\n] 2006.161.07:39:25.16#ibcon#*before write, iclass 35, count 0 2006.161.07:39:25.16#ibcon#enter sib2, iclass 35, count 0 2006.161.07:39:25.16#ibcon#flushed, iclass 35, count 0 2006.161.07:39:25.16#ibcon#about to write, iclass 35, count 0 2006.161.07:39:25.16#ibcon#wrote, iclass 35, count 0 2006.161.07:39:25.16#ibcon#about to read 3, iclass 35, count 0 2006.161.07:39:25.19#ibcon#read 3, iclass 35, count 0 2006.161.07:39:25.19#ibcon#about to read 4, iclass 35, count 0 2006.161.07:39:25.19#ibcon#read 4, iclass 35, count 0 2006.161.07:39:25.19#ibcon#about to read 5, iclass 35, count 0 2006.161.07:39:25.19#ibcon#read 5, iclass 35, count 0 2006.161.07:39:25.19#ibcon#about to read 6, iclass 35, count 0 2006.161.07:39:25.19#ibcon#read 6, iclass 35, count 0 2006.161.07:39:25.19#ibcon#end of sib2, iclass 35, count 0 2006.161.07:39:25.19#ibcon#*after write, iclass 35, count 0 2006.161.07:39:25.19#ibcon#*before return 0, iclass 35, count 0 2006.161.07:39:25.19#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:39:25.19#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:39:25.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:39:25.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:39:25.19$vc4f8/vbbw=wide 2006.161.07:39:25.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.07:39:25.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.07:39:25.19#ibcon#ireg 8 cls_cnt 0 2006.161.07:39:25.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:39:25.20#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:39:25.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:39:25.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:39:25.26#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:39:25.26#ibcon#first serial, iclass 38, count 0 2006.161.07:39:25.26#ibcon#enter sib2, iclass 38, count 0 2006.161.07:39:25.26#ibcon#flushed, iclass 38, count 0 2006.161.07:39:25.26#ibcon#about to write, iclass 38, count 0 2006.161.07:39:25.26#ibcon#wrote, iclass 38, count 0 2006.161.07:39:25.26#ibcon#about to read 3, iclass 38, count 0 2006.161.07:39:25.28#ibcon#read 3, iclass 38, count 0 2006.161.07:39:25.28#ibcon#about to read 4, iclass 38, count 0 2006.161.07:39:25.28#ibcon#read 4, iclass 38, count 0 2006.161.07:39:25.28#ibcon#about to read 5, iclass 38, count 0 2006.161.07:39:25.28#ibcon#read 5, iclass 38, count 0 2006.161.07:39:25.28#ibcon#about to read 6, iclass 38, count 0 2006.161.07:39:25.28#ibcon#read 6, iclass 38, count 0 2006.161.07:39:25.28#ibcon#end of sib2, iclass 38, count 0 2006.161.07:39:25.28#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:39:25.28#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:39:25.28#ibcon#[27=BW32\r\n] 2006.161.07:39:25.28#ibcon#*before write, iclass 38, count 0 2006.161.07:39:25.28#ibcon#enter sib2, iclass 38, count 0 2006.161.07:39:25.28#ibcon#flushed, iclass 38, count 0 2006.161.07:39:25.28#ibcon#about to write, iclass 38, count 0 2006.161.07:39:25.28#ibcon#wrote, iclass 38, count 0 2006.161.07:39:25.28#ibcon#about to read 3, iclass 38, count 0 2006.161.07:39:25.31#ibcon#read 3, iclass 38, count 0 2006.161.07:39:25.31#ibcon#about to read 4, iclass 38, count 0 2006.161.07:39:25.31#ibcon#read 4, iclass 38, count 0 2006.161.07:39:25.31#ibcon#about to read 5, iclass 38, count 0 2006.161.07:39:25.31#ibcon#read 5, iclass 38, count 0 2006.161.07:39:25.31#ibcon#about to read 6, iclass 38, count 0 2006.161.07:39:25.31#ibcon#read 6, iclass 38, count 0 2006.161.07:39:25.31#ibcon#end of sib2, iclass 38, count 0 2006.161.07:39:25.31#ibcon#*after write, iclass 38, count 0 2006.161.07:39:25.31#ibcon#*before return 0, iclass 38, count 0 2006.161.07:39:25.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:39:25.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:39:25.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:39:25.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:39:25.31$4f8m12a/ifd4f 2006.161.07:39:25.31$ifd4f/lo= 2006.161.07:39:25.31$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:39:25.31$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:39:25.31$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:39:25.31$ifd4f/patch= 2006.161.07:39:25.31$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:39:25.31$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:39:25.31$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:39:25.31$4f8m12a/"form=m,16.000,1:2 2006.161.07:39:25.31$4f8m12a/"tpicd 2006.161.07:39:25.31$4f8m12a/echo=off 2006.161.07:39:25.31$4f8m12a/xlog=off 2006.161.07:39:25.31:!2006.161.07:39:50 2006.161.07:39:35.13#trakl#Source acquired 2006.161.07:39:35.13#flagr#flagr/antenna,acquired 2006.161.07:39:50.00:preob 2006.161.07:39:51.13/onsource/TRACKING 2006.161.07:39:51.13:!2006.161.07:40:00 2006.161.07:40:00.00:data_valid=on 2006.161.07:40:00.00:midob 2006.161.07:40:00.13/onsource/TRACKING 2006.161.07:40:00.13/wx/24.13,1002.0,85 2006.161.07:40:00.37/cable/+6.4972E-03 2006.161.07:40:01.46/va/01,08,usb,yes,34,35 2006.161.07:40:01.46/va/02,07,usb,yes,34,35 2006.161.07:40:01.46/va/03,06,usb,yes,36,36 2006.161.07:40:01.46/va/04,07,usb,yes,35,37 2006.161.07:40:01.46/va/05,07,usb,yes,35,37 2006.161.07:40:01.46/va/06,06,usb,yes,34,34 2006.161.07:40:01.46/va/07,06,usb,yes,34,34 2006.161.07:40:01.46/va/08,07,usb,yes,33,32 2006.161.07:40:01.69/valo/01,532.99,yes,locked 2006.161.07:40:01.69/valo/02,572.99,yes,locked 2006.161.07:40:01.69/valo/03,672.99,yes,locked 2006.161.07:40:01.69/valo/04,832.99,yes,locked 2006.161.07:40:01.69/valo/05,652.99,yes,locked 2006.161.07:40:01.69/valo/06,772.99,yes,locked 2006.161.07:40:01.69/valo/07,832.99,yes,locked 2006.161.07:40:01.69/valo/08,852.99,yes,locked 2006.161.07:40:02.78/vb/01,04,usb,yes,32,30 2006.161.07:40:02.78/vb/02,04,usb,yes,34,35 2006.161.07:40:02.78/vb/03,04,usb,yes,30,34 2006.161.07:40:02.78/vb/04,04,usb,yes,31,31 2006.161.07:40:02.78/vb/05,04,usb,yes,29,34 2006.161.07:40:02.78/vb/06,04,usb,yes,31,33 2006.161.07:40:02.78/vb/07,04,usb,yes,33,32 2006.161.07:40:02.78/vb/08,04,usb,yes,30,34 2006.161.07:40:03.02/vblo/01,632.99,yes,locked 2006.161.07:40:03.02/vblo/02,640.99,yes,locked 2006.161.07:40:03.02/vblo/03,656.99,yes,locked 2006.161.07:40:03.02/vblo/04,712.99,yes,locked 2006.161.07:40:03.02/vblo/05,744.99,yes,locked 2006.161.07:40:03.02/vblo/06,752.99,yes,locked 2006.161.07:40:03.02/vblo/07,734.99,yes,locked 2006.161.07:40:03.02/vblo/08,744.99,yes,locked 2006.161.07:40:03.17/vabw/8 2006.161.07:40:03.32/vbbw/8 2006.161.07:40:03.41/xfe/off,on,14.7 2006.161.07:40:03.78/ifatt/23,28,28,28 2006.161.07:40:04.08/fmout-gps/S +4.47E-07 2006.161.07:40:04.23:!2006.161.07:41:00 2006.161.07:41:00.01:data_valid=off 2006.161.07:41:00.02:postob 2006.161.07:41:00.16/cable/+6.4978E-03 2006.161.07:41:00.16/wx/24.13,1002.0,85 2006.161.07:41:01.08/fmout-gps/S +4.47E-07 2006.161.07:41:01.08:scan_name=161-0741,k06161,70 2006.161.07:41:01.09:source=1053+815,105811.54,811432.7,2000.0,neutral 2006.161.07:41:01.13#flagr#flagr/antenna,new-source 2006.161.07:41:02.13:checkk5 2006.161.07:41:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:41:02.93/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:41:03.37/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:41:03.82/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:41:04.23/chk_obsdata//k5ts1/T1610740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:41:04.68/chk_obsdata//k5ts2/T1610740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:41:05.12/chk_obsdata//k5ts3/T1610740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:41:05.62/chk_obsdata//k5ts4/T1610740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:41:06.45/k5log//k5ts1_log_newline 2006.161.07:41:07.45/k5log//k5ts2_log_newline 2006.161.07:41:08.65/k5log//k5ts3_log_newline 2006.161.07:41:09.43/k5log//k5ts4_log_newline 2006.161.07:41:09.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:41:09.45:4f8m12a=1 2006.161.07:41:09.45$4f8m12a/echo=on 2006.161.07:41:09.45$4f8m12a/pcalon 2006.161.07:41:09.45$pcalon/"no phase cal control is implemented here 2006.161.07:41:09.45$4f8m12a/"tpicd=stop 2006.161.07:41:09.45$4f8m12a/vc4f8 2006.161.07:41:09.45$vc4f8/valo=1,532.99 2006.161.07:41:09.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:41:09.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:41:09.45#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:09.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:09.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:09.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:09.45#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:41:09.45#ibcon#first serial, iclass 7, count 0 2006.161.07:41:09.45#ibcon#enter sib2, iclass 7, count 0 2006.161.07:41:09.45#ibcon#flushed, iclass 7, count 0 2006.161.07:41:09.45#ibcon#about to write, iclass 7, count 0 2006.161.07:41:09.45#ibcon#wrote, iclass 7, count 0 2006.161.07:41:09.45#ibcon#about to read 3, iclass 7, count 0 2006.161.07:41:09.50#ibcon#read 3, iclass 7, count 0 2006.161.07:41:09.50#ibcon#about to read 4, iclass 7, count 0 2006.161.07:41:09.50#ibcon#read 4, iclass 7, count 0 2006.161.07:41:09.50#ibcon#about to read 5, iclass 7, count 0 2006.161.07:41:09.50#ibcon#read 5, iclass 7, count 0 2006.161.07:41:09.50#ibcon#about to read 6, iclass 7, count 0 2006.161.07:41:09.50#ibcon#read 6, iclass 7, count 0 2006.161.07:41:09.50#ibcon#end of sib2, iclass 7, count 0 2006.161.07:41:09.50#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:41:09.50#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:41:09.50#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:41:09.50#ibcon#*before write, iclass 7, count 0 2006.161.07:41:09.50#ibcon#enter sib2, iclass 7, count 0 2006.161.07:41:09.50#ibcon#flushed, iclass 7, count 0 2006.161.07:41:09.50#ibcon#about to write, iclass 7, count 0 2006.161.07:41:09.50#ibcon#wrote, iclass 7, count 0 2006.161.07:41:09.50#ibcon#about to read 3, iclass 7, count 0 2006.161.07:41:09.54#ibcon#read 3, iclass 7, count 0 2006.161.07:41:09.54#ibcon#about to read 4, iclass 7, count 0 2006.161.07:41:09.54#ibcon#read 4, iclass 7, count 0 2006.161.07:41:09.54#ibcon#about to read 5, iclass 7, count 0 2006.161.07:41:09.54#ibcon#read 5, iclass 7, count 0 2006.161.07:41:09.54#ibcon#about to read 6, iclass 7, count 0 2006.161.07:41:09.54#ibcon#read 6, iclass 7, count 0 2006.161.07:41:09.54#ibcon#end of sib2, iclass 7, count 0 2006.161.07:41:09.54#ibcon#*after write, iclass 7, count 0 2006.161.07:41:09.54#ibcon#*before return 0, iclass 7, count 0 2006.161.07:41:09.54#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:09.54#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:09.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:41:09.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:41:09.54$vc4f8/va=1,8 2006.161.07:41:09.54#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:41:09.54#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:41:09.54#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:09.54#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:09.54#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:09.54#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:09.54#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:41:09.54#ibcon#first serial, iclass 11, count 2 2006.161.07:41:09.54#ibcon#enter sib2, iclass 11, count 2 2006.161.07:41:09.54#ibcon#flushed, iclass 11, count 2 2006.161.07:41:09.54#ibcon#about to write, iclass 11, count 2 2006.161.07:41:09.54#ibcon#wrote, iclass 11, count 2 2006.161.07:41:09.54#ibcon#about to read 3, iclass 11, count 2 2006.161.07:41:09.56#ibcon#read 3, iclass 11, count 2 2006.161.07:41:09.56#ibcon#about to read 4, iclass 11, count 2 2006.161.07:41:09.56#ibcon#read 4, iclass 11, count 2 2006.161.07:41:09.56#ibcon#about to read 5, iclass 11, count 2 2006.161.07:41:09.56#ibcon#read 5, iclass 11, count 2 2006.161.07:41:09.56#ibcon#about to read 6, iclass 11, count 2 2006.161.07:41:09.56#ibcon#read 6, iclass 11, count 2 2006.161.07:41:09.56#ibcon#end of sib2, iclass 11, count 2 2006.161.07:41:09.56#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:41:09.56#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:41:09.56#ibcon#[25=AT01-08\r\n] 2006.161.07:41:09.56#ibcon#*before write, iclass 11, count 2 2006.161.07:41:09.56#ibcon#enter sib2, iclass 11, count 2 2006.161.07:41:09.56#ibcon#flushed, iclass 11, count 2 2006.161.07:41:09.56#ibcon#about to write, iclass 11, count 2 2006.161.07:41:09.56#ibcon#wrote, iclass 11, count 2 2006.161.07:41:09.56#ibcon#about to read 3, iclass 11, count 2 2006.161.07:41:09.59#ibcon#read 3, iclass 11, count 2 2006.161.07:41:09.59#ibcon#about to read 4, iclass 11, count 2 2006.161.07:41:09.59#ibcon#read 4, iclass 11, count 2 2006.161.07:41:09.59#ibcon#about to read 5, iclass 11, count 2 2006.161.07:41:09.59#ibcon#read 5, iclass 11, count 2 2006.161.07:41:09.59#ibcon#about to read 6, iclass 11, count 2 2006.161.07:41:09.59#ibcon#read 6, iclass 11, count 2 2006.161.07:41:09.59#ibcon#end of sib2, iclass 11, count 2 2006.161.07:41:09.59#ibcon#*after write, iclass 11, count 2 2006.161.07:41:09.59#ibcon#*before return 0, iclass 11, count 2 2006.161.07:41:09.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:09.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:09.59#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:41:09.59#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:09.59#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:09.71#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:09.71#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:09.71#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:41:09.71#ibcon#first serial, iclass 11, count 0 2006.161.07:41:09.71#ibcon#enter sib2, iclass 11, count 0 2006.161.07:41:09.71#ibcon#flushed, iclass 11, count 0 2006.161.07:41:09.71#ibcon#about to write, iclass 11, count 0 2006.161.07:41:09.71#ibcon#wrote, iclass 11, count 0 2006.161.07:41:09.71#ibcon#about to read 3, iclass 11, count 0 2006.161.07:41:09.73#ibcon#read 3, iclass 11, count 0 2006.161.07:41:09.73#ibcon#about to read 4, iclass 11, count 0 2006.161.07:41:09.73#ibcon#read 4, iclass 11, count 0 2006.161.07:41:09.73#ibcon#about to read 5, iclass 11, count 0 2006.161.07:41:09.73#ibcon#read 5, iclass 11, count 0 2006.161.07:41:09.73#ibcon#about to read 6, iclass 11, count 0 2006.161.07:41:09.73#ibcon#read 6, iclass 11, count 0 2006.161.07:41:09.73#ibcon#end of sib2, iclass 11, count 0 2006.161.07:41:09.73#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:41:09.73#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:41:09.73#ibcon#[25=USB\r\n] 2006.161.07:41:09.73#ibcon#*before write, iclass 11, count 0 2006.161.07:41:09.73#ibcon#enter sib2, iclass 11, count 0 2006.161.07:41:09.73#ibcon#flushed, iclass 11, count 0 2006.161.07:41:09.73#ibcon#about to write, iclass 11, count 0 2006.161.07:41:09.73#ibcon#wrote, iclass 11, count 0 2006.161.07:41:09.73#ibcon#about to read 3, iclass 11, count 0 2006.161.07:41:09.76#ibcon#read 3, iclass 11, count 0 2006.161.07:41:09.76#ibcon#about to read 4, iclass 11, count 0 2006.161.07:41:09.76#ibcon#read 4, iclass 11, count 0 2006.161.07:41:09.76#ibcon#about to read 5, iclass 11, count 0 2006.161.07:41:09.76#ibcon#read 5, iclass 11, count 0 2006.161.07:41:09.76#ibcon#about to read 6, iclass 11, count 0 2006.161.07:41:09.76#ibcon#read 6, iclass 11, count 0 2006.161.07:41:09.76#ibcon#end of sib2, iclass 11, count 0 2006.161.07:41:09.76#ibcon#*after write, iclass 11, count 0 2006.161.07:41:09.76#ibcon#*before return 0, iclass 11, count 0 2006.161.07:41:09.76#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:09.76#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:09.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:41:09.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:41:09.76$vc4f8/valo=2,572.99 2006.161.07:41:09.76#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:41:09.76#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:41:09.76#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:09.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:09.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:09.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:09.76#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:41:09.76#ibcon#first serial, iclass 13, count 0 2006.161.07:41:09.76#ibcon#enter sib2, iclass 13, count 0 2006.161.07:41:09.76#ibcon#flushed, iclass 13, count 0 2006.161.07:41:09.76#ibcon#about to write, iclass 13, count 0 2006.161.07:41:09.76#ibcon#wrote, iclass 13, count 0 2006.161.07:41:09.76#ibcon#about to read 3, iclass 13, count 0 2006.161.07:41:09.78#ibcon#read 3, iclass 13, count 0 2006.161.07:41:09.78#ibcon#about to read 4, iclass 13, count 0 2006.161.07:41:09.78#ibcon#read 4, iclass 13, count 0 2006.161.07:41:09.78#ibcon#about to read 5, iclass 13, count 0 2006.161.07:41:09.78#ibcon#read 5, iclass 13, count 0 2006.161.07:41:09.78#ibcon#about to read 6, iclass 13, count 0 2006.161.07:41:09.78#ibcon#read 6, iclass 13, count 0 2006.161.07:41:09.78#ibcon#end of sib2, iclass 13, count 0 2006.161.07:41:09.78#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:41:09.78#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:41:09.78#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:41:09.78#ibcon#*before write, iclass 13, count 0 2006.161.07:41:09.78#ibcon#enter sib2, iclass 13, count 0 2006.161.07:41:09.78#ibcon#flushed, iclass 13, count 0 2006.161.07:41:09.78#ibcon#about to write, iclass 13, count 0 2006.161.07:41:09.78#ibcon#wrote, iclass 13, count 0 2006.161.07:41:09.78#ibcon#about to read 3, iclass 13, count 0 2006.161.07:41:09.82#ibcon#read 3, iclass 13, count 0 2006.161.07:41:09.82#ibcon#about to read 4, iclass 13, count 0 2006.161.07:41:09.82#ibcon#read 4, iclass 13, count 0 2006.161.07:41:09.82#ibcon#about to read 5, iclass 13, count 0 2006.161.07:41:09.82#ibcon#read 5, iclass 13, count 0 2006.161.07:41:09.82#ibcon#about to read 6, iclass 13, count 0 2006.161.07:41:09.82#ibcon#read 6, iclass 13, count 0 2006.161.07:41:09.82#ibcon#end of sib2, iclass 13, count 0 2006.161.07:41:09.82#ibcon#*after write, iclass 13, count 0 2006.161.07:41:09.82#ibcon#*before return 0, iclass 13, count 0 2006.161.07:41:09.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:09.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:09.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:41:09.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:41:09.82$vc4f8/va=2,7 2006.161.07:41:09.82#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:41:09.82#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:41:09.82#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:09.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:09.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:09.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:09.88#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:41:09.88#ibcon#first serial, iclass 15, count 2 2006.161.07:41:09.88#ibcon#enter sib2, iclass 15, count 2 2006.161.07:41:09.88#ibcon#flushed, iclass 15, count 2 2006.161.07:41:09.88#ibcon#about to write, iclass 15, count 2 2006.161.07:41:09.88#ibcon#wrote, iclass 15, count 2 2006.161.07:41:09.88#ibcon#about to read 3, iclass 15, count 2 2006.161.07:41:09.91#ibcon#read 3, iclass 15, count 2 2006.161.07:41:09.91#ibcon#about to read 4, iclass 15, count 2 2006.161.07:41:09.91#ibcon#read 4, iclass 15, count 2 2006.161.07:41:09.91#ibcon#about to read 5, iclass 15, count 2 2006.161.07:41:09.91#ibcon#read 5, iclass 15, count 2 2006.161.07:41:09.91#ibcon#about to read 6, iclass 15, count 2 2006.161.07:41:09.91#ibcon#read 6, iclass 15, count 2 2006.161.07:41:09.91#ibcon#end of sib2, iclass 15, count 2 2006.161.07:41:09.91#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:41:09.91#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:41:09.91#ibcon#[25=AT02-07\r\n] 2006.161.07:41:09.91#ibcon#*before write, iclass 15, count 2 2006.161.07:41:09.91#ibcon#enter sib2, iclass 15, count 2 2006.161.07:41:09.91#ibcon#flushed, iclass 15, count 2 2006.161.07:41:09.91#ibcon#about to write, iclass 15, count 2 2006.161.07:41:09.91#ibcon#wrote, iclass 15, count 2 2006.161.07:41:09.91#ibcon#about to read 3, iclass 15, count 2 2006.161.07:41:09.94#ibcon#read 3, iclass 15, count 2 2006.161.07:41:09.94#ibcon#about to read 4, iclass 15, count 2 2006.161.07:41:09.94#ibcon#read 4, iclass 15, count 2 2006.161.07:41:09.94#ibcon#about to read 5, iclass 15, count 2 2006.161.07:41:09.94#ibcon#read 5, iclass 15, count 2 2006.161.07:41:09.94#ibcon#about to read 6, iclass 15, count 2 2006.161.07:41:09.94#ibcon#read 6, iclass 15, count 2 2006.161.07:41:09.94#ibcon#end of sib2, iclass 15, count 2 2006.161.07:41:09.94#ibcon#*after write, iclass 15, count 2 2006.161.07:41:09.94#ibcon#*before return 0, iclass 15, count 2 2006.161.07:41:09.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:09.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:09.94#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:41:09.94#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:09.94#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:10.06#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:10.06#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:10.06#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:41:10.06#ibcon#first serial, iclass 15, count 0 2006.161.07:41:10.06#ibcon#enter sib2, iclass 15, count 0 2006.161.07:41:10.06#ibcon#flushed, iclass 15, count 0 2006.161.07:41:10.06#ibcon#about to write, iclass 15, count 0 2006.161.07:41:10.06#ibcon#wrote, iclass 15, count 0 2006.161.07:41:10.06#ibcon#about to read 3, iclass 15, count 0 2006.161.07:41:10.10#ibcon#read 3, iclass 15, count 0 2006.161.07:41:10.10#ibcon#about to read 4, iclass 15, count 0 2006.161.07:41:10.10#ibcon#read 4, iclass 15, count 0 2006.161.07:41:10.10#ibcon#about to read 5, iclass 15, count 0 2006.161.07:41:10.10#ibcon#read 5, iclass 15, count 0 2006.161.07:41:10.10#ibcon#about to read 6, iclass 15, count 0 2006.161.07:41:10.10#ibcon#read 6, iclass 15, count 0 2006.161.07:41:10.10#ibcon#end of sib2, iclass 15, count 0 2006.161.07:41:10.10#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:41:10.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:41:10.10#ibcon#[25=USB\r\n] 2006.161.07:41:10.10#ibcon#*before write, iclass 15, count 0 2006.161.07:41:10.10#ibcon#enter sib2, iclass 15, count 0 2006.161.07:41:10.10#ibcon#flushed, iclass 15, count 0 2006.161.07:41:10.10#ibcon#about to write, iclass 15, count 0 2006.161.07:41:10.10#ibcon#wrote, iclass 15, count 0 2006.161.07:41:10.10#ibcon#about to read 3, iclass 15, count 0 2006.161.07:41:10.13#ibcon#read 3, iclass 15, count 0 2006.161.07:41:10.13#ibcon#about to read 4, iclass 15, count 0 2006.161.07:41:10.13#ibcon#read 4, iclass 15, count 0 2006.161.07:41:10.13#ibcon#about to read 5, iclass 15, count 0 2006.161.07:41:10.13#ibcon#read 5, iclass 15, count 0 2006.161.07:41:10.13#ibcon#about to read 6, iclass 15, count 0 2006.161.07:41:10.13#ibcon#read 6, iclass 15, count 0 2006.161.07:41:10.13#ibcon#end of sib2, iclass 15, count 0 2006.161.07:41:10.13#ibcon#*after write, iclass 15, count 0 2006.161.07:41:10.13#ibcon#*before return 0, iclass 15, count 0 2006.161.07:41:10.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:10.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:10.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:41:10.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:41:10.13$vc4f8/valo=3,672.99 2006.161.07:41:10.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:41:10.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:41:10.13#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:10.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:10.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:10.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:10.13#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:41:10.13#ibcon#first serial, iclass 17, count 0 2006.161.07:41:10.13#ibcon#enter sib2, iclass 17, count 0 2006.161.07:41:10.13#ibcon#flushed, iclass 17, count 0 2006.161.07:41:10.13#ibcon#about to write, iclass 17, count 0 2006.161.07:41:10.13#ibcon#wrote, iclass 17, count 0 2006.161.07:41:10.13#ibcon#about to read 3, iclass 17, count 0 2006.161.07:41:10.15#ibcon#read 3, iclass 17, count 0 2006.161.07:41:10.15#ibcon#about to read 4, iclass 17, count 0 2006.161.07:41:10.15#ibcon#read 4, iclass 17, count 0 2006.161.07:41:10.15#ibcon#about to read 5, iclass 17, count 0 2006.161.07:41:10.15#ibcon#read 5, iclass 17, count 0 2006.161.07:41:10.15#ibcon#about to read 6, iclass 17, count 0 2006.161.07:41:10.15#ibcon#read 6, iclass 17, count 0 2006.161.07:41:10.15#ibcon#end of sib2, iclass 17, count 0 2006.161.07:41:10.15#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:41:10.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:41:10.15#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:41:10.15#ibcon#*before write, iclass 17, count 0 2006.161.07:41:10.15#ibcon#enter sib2, iclass 17, count 0 2006.161.07:41:10.15#ibcon#flushed, iclass 17, count 0 2006.161.07:41:10.15#ibcon#about to write, iclass 17, count 0 2006.161.07:41:10.15#ibcon#wrote, iclass 17, count 0 2006.161.07:41:10.15#ibcon#about to read 3, iclass 17, count 0 2006.161.07:41:10.19#ibcon#read 3, iclass 17, count 0 2006.161.07:41:10.19#ibcon#about to read 4, iclass 17, count 0 2006.161.07:41:10.19#ibcon#read 4, iclass 17, count 0 2006.161.07:41:10.19#ibcon#about to read 5, iclass 17, count 0 2006.161.07:41:10.19#ibcon#read 5, iclass 17, count 0 2006.161.07:41:10.19#ibcon#about to read 6, iclass 17, count 0 2006.161.07:41:10.19#ibcon#read 6, iclass 17, count 0 2006.161.07:41:10.19#ibcon#end of sib2, iclass 17, count 0 2006.161.07:41:10.19#ibcon#*after write, iclass 17, count 0 2006.161.07:41:10.19#ibcon#*before return 0, iclass 17, count 0 2006.161.07:41:10.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:10.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:10.19#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:41:10.19#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:41:10.19$vc4f8/va=3,6 2006.161.07:41:10.19#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.07:41:10.19#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.07:41:10.19#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:10.19#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:10.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:10.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:10.25#ibcon#enter wrdev, iclass 19, count 2 2006.161.07:41:10.25#ibcon#first serial, iclass 19, count 2 2006.161.07:41:10.25#ibcon#enter sib2, iclass 19, count 2 2006.161.07:41:10.25#ibcon#flushed, iclass 19, count 2 2006.161.07:41:10.25#ibcon#about to write, iclass 19, count 2 2006.161.07:41:10.25#ibcon#wrote, iclass 19, count 2 2006.161.07:41:10.25#ibcon#about to read 3, iclass 19, count 2 2006.161.07:41:10.27#ibcon#read 3, iclass 19, count 2 2006.161.07:41:10.27#ibcon#about to read 4, iclass 19, count 2 2006.161.07:41:10.27#ibcon#read 4, iclass 19, count 2 2006.161.07:41:10.27#ibcon#about to read 5, iclass 19, count 2 2006.161.07:41:10.27#ibcon#read 5, iclass 19, count 2 2006.161.07:41:10.27#ibcon#about to read 6, iclass 19, count 2 2006.161.07:41:10.27#ibcon#read 6, iclass 19, count 2 2006.161.07:41:10.27#ibcon#end of sib2, iclass 19, count 2 2006.161.07:41:10.27#ibcon#*mode == 0, iclass 19, count 2 2006.161.07:41:10.27#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.07:41:10.27#ibcon#[25=AT03-06\r\n] 2006.161.07:41:10.27#ibcon#*before write, iclass 19, count 2 2006.161.07:41:10.27#ibcon#enter sib2, iclass 19, count 2 2006.161.07:41:10.27#ibcon#flushed, iclass 19, count 2 2006.161.07:41:10.27#ibcon#about to write, iclass 19, count 2 2006.161.07:41:10.27#ibcon#wrote, iclass 19, count 2 2006.161.07:41:10.27#ibcon#about to read 3, iclass 19, count 2 2006.161.07:41:10.30#ibcon#read 3, iclass 19, count 2 2006.161.07:41:10.30#ibcon#about to read 4, iclass 19, count 2 2006.161.07:41:10.30#ibcon#read 4, iclass 19, count 2 2006.161.07:41:10.30#ibcon#about to read 5, iclass 19, count 2 2006.161.07:41:10.30#ibcon#read 5, iclass 19, count 2 2006.161.07:41:10.30#ibcon#about to read 6, iclass 19, count 2 2006.161.07:41:10.30#ibcon#read 6, iclass 19, count 2 2006.161.07:41:10.30#ibcon#end of sib2, iclass 19, count 2 2006.161.07:41:10.30#ibcon#*after write, iclass 19, count 2 2006.161.07:41:10.30#ibcon#*before return 0, iclass 19, count 2 2006.161.07:41:10.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:10.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:10.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.07:41:10.30#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:10.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:10.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:10.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:10.42#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:41:10.42#ibcon#first serial, iclass 19, count 0 2006.161.07:41:10.42#ibcon#enter sib2, iclass 19, count 0 2006.161.07:41:10.42#ibcon#flushed, iclass 19, count 0 2006.161.07:41:10.42#ibcon#about to write, iclass 19, count 0 2006.161.07:41:10.42#ibcon#wrote, iclass 19, count 0 2006.161.07:41:10.42#ibcon#about to read 3, iclass 19, count 0 2006.161.07:41:10.44#ibcon#read 3, iclass 19, count 0 2006.161.07:41:10.44#ibcon#about to read 4, iclass 19, count 0 2006.161.07:41:10.44#ibcon#read 4, iclass 19, count 0 2006.161.07:41:10.44#ibcon#about to read 5, iclass 19, count 0 2006.161.07:41:10.44#ibcon#read 5, iclass 19, count 0 2006.161.07:41:10.44#ibcon#about to read 6, iclass 19, count 0 2006.161.07:41:10.44#ibcon#read 6, iclass 19, count 0 2006.161.07:41:10.44#ibcon#end of sib2, iclass 19, count 0 2006.161.07:41:10.44#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:41:10.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:41:10.44#ibcon#[25=USB\r\n] 2006.161.07:41:10.44#ibcon#*before write, iclass 19, count 0 2006.161.07:41:10.44#ibcon#enter sib2, iclass 19, count 0 2006.161.07:41:10.44#ibcon#flushed, iclass 19, count 0 2006.161.07:41:10.44#ibcon#about to write, iclass 19, count 0 2006.161.07:41:10.44#ibcon#wrote, iclass 19, count 0 2006.161.07:41:10.44#ibcon#about to read 3, iclass 19, count 0 2006.161.07:41:10.47#ibcon#read 3, iclass 19, count 0 2006.161.07:41:10.47#ibcon#about to read 4, iclass 19, count 0 2006.161.07:41:10.47#ibcon#read 4, iclass 19, count 0 2006.161.07:41:10.47#ibcon#about to read 5, iclass 19, count 0 2006.161.07:41:10.47#ibcon#read 5, iclass 19, count 0 2006.161.07:41:10.47#ibcon#about to read 6, iclass 19, count 0 2006.161.07:41:10.47#ibcon#read 6, iclass 19, count 0 2006.161.07:41:10.47#ibcon#end of sib2, iclass 19, count 0 2006.161.07:41:10.47#ibcon#*after write, iclass 19, count 0 2006.161.07:41:10.47#ibcon#*before return 0, iclass 19, count 0 2006.161.07:41:10.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:10.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:10.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:41:10.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:41:10.47$vc4f8/valo=4,832.99 2006.161.07:41:10.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.07:41:10.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.07:41:10.47#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:10.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:10.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:10.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:10.47#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:41:10.47#ibcon#first serial, iclass 21, count 0 2006.161.07:41:10.47#ibcon#enter sib2, iclass 21, count 0 2006.161.07:41:10.47#ibcon#flushed, iclass 21, count 0 2006.161.07:41:10.47#ibcon#about to write, iclass 21, count 0 2006.161.07:41:10.47#ibcon#wrote, iclass 21, count 0 2006.161.07:41:10.47#ibcon#about to read 3, iclass 21, count 0 2006.161.07:41:10.49#ibcon#read 3, iclass 21, count 0 2006.161.07:41:10.49#ibcon#about to read 4, iclass 21, count 0 2006.161.07:41:10.49#ibcon#read 4, iclass 21, count 0 2006.161.07:41:10.49#ibcon#about to read 5, iclass 21, count 0 2006.161.07:41:10.49#ibcon#read 5, iclass 21, count 0 2006.161.07:41:10.49#ibcon#about to read 6, iclass 21, count 0 2006.161.07:41:10.49#ibcon#read 6, iclass 21, count 0 2006.161.07:41:10.49#ibcon#end of sib2, iclass 21, count 0 2006.161.07:41:10.49#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:41:10.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:41:10.49#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:41:10.49#ibcon#*before write, iclass 21, count 0 2006.161.07:41:10.49#ibcon#enter sib2, iclass 21, count 0 2006.161.07:41:10.49#ibcon#flushed, iclass 21, count 0 2006.161.07:41:10.49#ibcon#about to write, iclass 21, count 0 2006.161.07:41:10.49#ibcon#wrote, iclass 21, count 0 2006.161.07:41:10.49#ibcon#about to read 3, iclass 21, count 0 2006.161.07:41:10.53#ibcon#read 3, iclass 21, count 0 2006.161.07:41:10.53#ibcon#about to read 4, iclass 21, count 0 2006.161.07:41:10.53#ibcon#read 4, iclass 21, count 0 2006.161.07:41:10.53#ibcon#about to read 5, iclass 21, count 0 2006.161.07:41:10.53#ibcon#read 5, iclass 21, count 0 2006.161.07:41:10.53#ibcon#about to read 6, iclass 21, count 0 2006.161.07:41:10.53#ibcon#read 6, iclass 21, count 0 2006.161.07:41:10.53#ibcon#end of sib2, iclass 21, count 0 2006.161.07:41:10.53#ibcon#*after write, iclass 21, count 0 2006.161.07:41:10.53#ibcon#*before return 0, iclass 21, count 0 2006.161.07:41:10.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:10.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:10.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:41:10.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:41:10.53$vc4f8/va=4,7 2006.161.07:41:10.53#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.07:41:10.53#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.07:41:10.53#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:10.53#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:10.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:10.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:10.59#ibcon#enter wrdev, iclass 23, count 2 2006.161.07:41:10.59#ibcon#first serial, iclass 23, count 2 2006.161.07:41:10.59#ibcon#enter sib2, iclass 23, count 2 2006.161.07:41:10.59#ibcon#flushed, iclass 23, count 2 2006.161.07:41:10.59#ibcon#about to write, iclass 23, count 2 2006.161.07:41:10.59#ibcon#wrote, iclass 23, count 2 2006.161.07:41:10.59#ibcon#about to read 3, iclass 23, count 2 2006.161.07:41:10.61#ibcon#read 3, iclass 23, count 2 2006.161.07:41:10.61#ibcon#about to read 4, iclass 23, count 2 2006.161.07:41:10.61#ibcon#read 4, iclass 23, count 2 2006.161.07:41:10.61#ibcon#about to read 5, iclass 23, count 2 2006.161.07:41:10.61#ibcon#read 5, iclass 23, count 2 2006.161.07:41:10.61#ibcon#about to read 6, iclass 23, count 2 2006.161.07:41:10.61#ibcon#read 6, iclass 23, count 2 2006.161.07:41:10.61#ibcon#end of sib2, iclass 23, count 2 2006.161.07:41:10.61#ibcon#*mode == 0, iclass 23, count 2 2006.161.07:41:10.61#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.07:41:10.61#ibcon#[25=AT04-07\r\n] 2006.161.07:41:10.61#ibcon#*before write, iclass 23, count 2 2006.161.07:41:10.61#ibcon#enter sib2, iclass 23, count 2 2006.161.07:41:10.61#ibcon#flushed, iclass 23, count 2 2006.161.07:41:10.61#ibcon#about to write, iclass 23, count 2 2006.161.07:41:10.61#ibcon#wrote, iclass 23, count 2 2006.161.07:41:10.61#ibcon#about to read 3, iclass 23, count 2 2006.161.07:41:10.64#ibcon#read 3, iclass 23, count 2 2006.161.07:41:10.64#ibcon#about to read 4, iclass 23, count 2 2006.161.07:41:10.64#ibcon#read 4, iclass 23, count 2 2006.161.07:41:10.64#ibcon#about to read 5, iclass 23, count 2 2006.161.07:41:10.64#ibcon#read 5, iclass 23, count 2 2006.161.07:41:10.64#ibcon#about to read 6, iclass 23, count 2 2006.161.07:41:10.64#ibcon#read 6, iclass 23, count 2 2006.161.07:41:10.64#ibcon#end of sib2, iclass 23, count 2 2006.161.07:41:10.64#ibcon#*after write, iclass 23, count 2 2006.161.07:41:10.64#ibcon#*before return 0, iclass 23, count 2 2006.161.07:41:10.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:10.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:10.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.07:41:10.64#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:10.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:10.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:10.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:10.76#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:41:10.76#ibcon#first serial, iclass 23, count 0 2006.161.07:41:10.76#ibcon#enter sib2, iclass 23, count 0 2006.161.07:41:10.76#ibcon#flushed, iclass 23, count 0 2006.161.07:41:10.76#ibcon#about to write, iclass 23, count 0 2006.161.07:41:10.76#ibcon#wrote, iclass 23, count 0 2006.161.07:41:10.76#ibcon#about to read 3, iclass 23, count 0 2006.161.07:41:10.78#ibcon#read 3, iclass 23, count 0 2006.161.07:41:10.78#ibcon#about to read 4, iclass 23, count 0 2006.161.07:41:10.78#ibcon#read 4, iclass 23, count 0 2006.161.07:41:10.78#ibcon#about to read 5, iclass 23, count 0 2006.161.07:41:10.78#ibcon#read 5, iclass 23, count 0 2006.161.07:41:10.78#ibcon#about to read 6, iclass 23, count 0 2006.161.07:41:10.78#ibcon#read 6, iclass 23, count 0 2006.161.07:41:10.78#ibcon#end of sib2, iclass 23, count 0 2006.161.07:41:10.78#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:41:10.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:41:10.78#ibcon#[25=USB\r\n] 2006.161.07:41:10.78#ibcon#*before write, iclass 23, count 0 2006.161.07:41:10.78#ibcon#enter sib2, iclass 23, count 0 2006.161.07:41:10.78#ibcon#flushed, iclass 23, count 0 2006.161.07:41:10.78#ibcon#about to write, iclass 23, count 0 2006.161.07:41:10.78#ibcon#wrote, iclass 23, count 0 2006.161.07:41:10.78#ibcon#about to read 3, iclass 23, count 0 2006.161.07:41:10.81#ibcon#read 3, iclass 23, count 0 2006.161.07:41:10.81#ibcon#about to read 4, iclass 23, count 0 2006.161.07:41:10.81#ibcon#read 4, iclass 23, count 0 2006.161.07:41:10.81#ibcon#about to read 5, iclass 23, count 0 2006.161.07:41:10.81#ibcon#read 5, iclass 23, count 0 2006.161.07:41:10.81#ibcon#about to read 6, iclass 23, count 0 2006.161.07:41:10.81#ibcon#read 6, iclass 23, count 0 2006.161.07:41:10.81#ibcon#end of sib2, iclass 23, count 0 2006.161.07:41:10.81#ibcon#*after write, iclass 23, count 0 2006.161.07:41:10.81#ibcon#*before return 0, iclass 23, count 0 2006.161.07:41:10.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:10.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:10.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:41:10.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:41:10.81$vc4f8/valo=5,652.99 2006.161.07:41:10.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.07:41:10.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.07:41:10.81#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:10.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:10.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:10.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:10.81#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:41:10.81#ibcon#first serial, iclass 25, count 0 2006.161.07:41:10.81#ibcon#enter sib2, iclass 25, count 0 2006.161.07:41:10.81#ibcon#flushed, iclass 25, count 0 2006.161.07:41:10.81#ibcon#about to write, iclass 25, count 0 2006.161.07:41:10.81#ibcon#wrote, iclass 25, count 0 2006.161.07:41:10.81#ibcon#about to read 3, iclass 25, count 0 2006.161.07:41:10.83#ibcon#read 3, iclass 25, count 0 2006.161.07:41:10.83#ibcon#about to read 4, iclass 25, count 0 2006.161.07:41:10.83#ibcon#read 4, iclass 25, count 0 2006.161.07:41:10.83#ibcon#about to read 5, iclass 25, count 0 2006.161.07:41:10.83#ibcon#read 5, iclass 25, count 0 2006.161.07:41:10.83#ibcon#about to read 6, iclass 25, count 0 2006.161.07:41:10.83#ibcon#read 6, iclass 25, count 0 2006.161.07:41:10.83#ibcon#end of sib2, iclass 25, count 0 2006.161.07:41:10.83#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:41:10.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:41:10.83#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:41:10.83#ibcon#*before write, iclass 25, count 0 2006.161.07:41:10.83#ibcon#enter sib2, iclass 25, count 0 2006.161.07:41:10.83#ibcon#flushed, iclass 25, count 0 2006.161.07:41:10.83#ibcon#about to write, iclass 25, count 0 2006.161.07:41:10.83#ibcon#wrote, iclass 25, count 0 2006.161.07:41:10.83#ibcon#about to read 3, iclass 25, count 0 2006.161.07:41:10.87#ibcon#read 3, iclass 25, count 0 2006.161.07:41:10.87#ibcon#about to read 4, iclass 25, count 0 2006.161.07:41:10.87#ibcon#read 4, iclass 25, count 0 2006.161.07:41:10.87#ibcon#about to read 5, iclass 25, count 0 2006.161.07:41:10.87#ibcon#read 5, iclass 25, count 0 2006.161.07:41:10.87#ibcon#about to read 6, iclass 25, count 0 2006.161.07:41:10.87#ibcon#read 6, iclass 25, count 0 2006.161.07:41:10.87#ibcon#end of sib2, iclass 25, count 0 2006.161.07:41:10.87#ibcon#*after write, iclass 25, count 0 2006.161.07:41:10.87#ibcon#*before return 0, iclass 25, count 0 2006.161.07:41:10.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:10.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:10.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:41:10.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:41:10.87$vc4f8/va=5,7 2006.161.07:41:10.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.07:41:10.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.07:41:10.87#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:10.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:10.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:10.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:10.93#ibcon#enter wrdev, iclass 27, count 2 2006.161.07:41:10.93#ibcon#first serial, iclass 27, count 2 2006.161.07:41:10.93#ibcon#enter sib2, iclass 27, count 2 2006.161.07:41:10.93#ibcon#flushed, iclass 27, count 2 2006.161.07:41:10.93#ibcon#about to write, iclass 27, count 2 2006.161.07:41:10.93#ibcon#wrote, iclass 27, count 2 2006.161.07:41:10.93#ibcon#about to read 3, iclass 27, count 2 2006.161.07:41:10.95#ibcon#read 3, iclass 27, count 2 2006.161.07:41:10.95#ibcon#about to read 4, iclass 27, count 2 2006.161.07:41:10.95#ibcon#read 4, iclass 27, count 2 2006.161.07:41:10.95#ibcon#about to read 5, iclass 27, count 2 2006.161.07:41:10.95#ibcon#read 5, iclass 27, count 2 2006.161.07:41:10.95#ibcon#about to read 6, iclass 27, count 2 2006.161.07:41:10.95#ibcon#read 6, iclass 27, count 2 2006.161.07:41:10.95#ibcon#end of sib2, iclass 27, count 2 2006.161.07:41:10.95#ibcon#*mode == 0, iclass 27, count 2 2006.161.07:41:10.95#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.07:41:10.95#ibcon#[25=AT05-07\r\n] 2006.161.07:41:10.95#ibcon#*before write, iclass 27, count 2 2006.161.07:41:10.95#ibcon#enter sib2, iclass 27, count 2 2006.161.07:41:10.95#ibcon#flushed, iclass 27, count 2 2006.161.07:41:10.95#ibcon#about to write, iclass 27, count 2 2006.161.07:41:10.95#ibcon#wrote, iclass 27, count 2 2006.161.07:41:10.95#ibcon#about to read 3, iclass 27, count 2 2006.161.07:41:10.98#ibcon#read 3, iclass 27, count 2 2006.161.07:41:10.98#ibcon#about to read 4, iclass 27, count 2 2006.161.07:41:10.98#ibcon#read 4, iclass 27, count 2 2006.161.07:41:10.98#ibcon#about to read 5, iclass 27, count 2 2006.161.07:41:10.98#ibcon#read 5, iclass 27, count 2 2006.161.07:41:10.98#ibcon#about to read 6, iclass 27, count 2 2006.161.07:41:10.98#ibcon#read 6, iclass 27, count 2 2006.161.07:41:10.98#ibcon#end of sib2, iclass 27, count 2 2006.161.07:41:10.98#ibcon#*after write, iclass 27, count 2 2006.161.07:41:10.98#ibcon#*before return 0, iclass 27, count 2 2006.161.07:41:10.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:10.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:10.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.07:41:10.98#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:10.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:11.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:11.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:11.10#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:41:11.10#ibcon#first serial, iclass 27, count 0 2006.161.07:41:11.10#ibcon#enter sib2, iclass 27, count 0 2006.161.07:41:11.10#ibcon#flushed, iclass 27, count 0 2006.161.07:41:11.10#ibcon#about to write, iclass 27, count 0 2006.161.07:41:11.10#ibcon#wrote, iclass 27, count 0 2006.161.07:41:11.10#ibcon#about to read 3, iclass 27, count 0 2006.161.07:41:11.12#ibcon#read 3, iclass 27, count 0 2006.161.07:41:11.12#ibcon#about to read 4, iclass 27, count 0 2006.161.07:41:11.12#ibcon#read 4, iclass 27, count 0 2006.161.07:41:11.12#ibcon#about to read 5, iclass 27, count 0 2006.161.07:41:11.12#ibcon#read 5, iclass 27, count 0 2006.161.07:41:11.12#ibcon#about to read 6, iclass 27, count 0 2006.161.07:41:11.12#ibcon#read 6, iclass 27, count 0 2006.161.07:41:11.12#ibcon#end of sib2, iclass 27, count 0 2006.161.07:41:11.12#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:41:11.12#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:41:11.12#ibcon#[25=USB\r\n] 2006.161.07:41:11.12#ibcon#*before write, iclass 27, count 0 2006.161.07:41:11.12#ibcon#enter sib2, iclass 27, count 0 2006.161.07:41:11.12#ibcon#flushed, iclass 27, count 0 2006.161.07:41:11.12#ibcon#about to write, iclass 27, count 0 2006.161.07:41:11.12#ibcon#wrote, iclass 27, count 0 2006.161.07:41:11.12#ibcon#about to read 3, iclass 27, count 0 2006.161.07:41:11.15#ibcon#read 3, iclass 27, count 0 2006.161.07:41:11.15#ibcon#about to read 4, iclass 27, count 0 2006.161.07:41:11.15#ibcon#read 4, iclass 27, count 0 2006.161.07:41:11.15#ibcon#about to read 5, iclass 27, count 0 2006.161.07:41:11.15#ibcon#read 5, iclass 27, count 0 2006.161.07:41:11.15#ibcon#about to read 6, iclass 27, count 0 2006.161.07:41:11.15#ibcon#read 6, iclass 27, count 0 2006.161.07:41:11.15#ibcon#end of sib2, iclass 27, count 0 2006.161.07:41:11.15#ibcon#*after write, iclass 27, count 0 2006.161.07:41:11.15#ibcon#*before return 0, iclass 27, count 0 2006.161.07:41:11.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:11.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:11.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:41:11.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:41:11.15$vc4f8/valo=6,772.99 2006.161.07:41:11.15#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.07:41:11.15#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.07:41:11.15#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:11.15#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:11.15#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:11.15#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:11.15#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:41:11.15#ibcon#first serial, iclass 29, count 0 2006.161.07:41:11.15#ibcon#enter sib2, iclass 29, count 0 2006.161.07:41:11.15#ibcon#flushed, iclass 29, count 0 2006.161.07:41:11.15#ibcon#about to write, iclass 29, count 0 2006.161.07:41:11.15#ibcon#wrote, iclass 29, count 0 2006.161.07:41:11.15#ibcon#about to read 3, iclass 29, count 0 2006.161.07:41:11.17#ibcon#read 3, iclass 29, count 0 2006.161.07:41:11.17#ibcon#about to read 4, iclass 29, count 0 2006.161.07:41:11.17#ibcon#read 4, iclass 29, count 0 2006.161.07:41:11.17#ibcon#about to read 5, iclass 29, count 0 2006.161.07:41:11.17#ibcon#read 5, iclass 29, count 0 2006.161.07:41:11.17#ibcon#about to read 6, iclass 29, count 0 2006.161.07:41:11.17#ibcon#read 6, iclass 29, count 0 2006.161.07:41:11.17#ibcon#end of sib2, iclass 29, count 0 2006.161.07:41:11.17#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:41:11.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:41:11.17#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:41:11.17#ibcon#*before write, iclass 29, count 0 2006.161.07:41:11.17#ibcon#enter sib2, iclass 29, count 0 2006.161.07:41:11.17#ibcon#flushed, iclass 29, count 0 2006.161.07:41:11.17#ibcon#about to write, iclass 29, count 0 2006.161.07:41:11.17#ibcon#wrote, iclass 29, count 0 2006.161.07:41:11.17#ibcon#about to read 3, iclass 29, count 0 2006.161.07:41:11.21#ibcon#read 3, iclass 29, count 0 2006.161.07:41:11.21#ibcon#about to read 4, iclass 29, count 0 2006.161.07:41:11.21#ibcon#read 4, iclass 29, count 0 2006.161.07:41:11.21#ibcon#about to read 5, iclass 29, count 0 2006.161.07:41:11.21#ibcon#read 5, iclass 29, count 0 2006.161.07:41:11.21#ibcon#about to read 6, iclass 29, count 0 2006.161.07:41:11.21#ibcon#read 6, iclass 29, count 0 2006.161.07:41:11.21#ibcon#end of sib2, iclass 29, count 0 2006.161.07:41:11.21#ibcon#*after write, iclass 29, count 0 2006.161.07:41:11.21#ibcon#*before return 0, iclass 29, count 0 2006.161.07:41:11.21#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:11.21#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:11.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:41:11.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:41:11.21$vc4f8/va=6,6 2006.161.07:41:11.21#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.07:41:11.21#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.07:41:11.21#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:11.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:11.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:11.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:11.27#ibcon#enter wrdev, iclass 31, count 2 2006.161.07:41:11.27#ibcon#first serial, iclass 31, count 2 2006.161.07:41:11.27#ibcon#enter sib2, iclass 31, count 2 2006.161.07:41:11.27#ibcon#flushed, iclass 31, count 2 2006.161.07:41:11.27#ibcon#about to write, iclass 31, count 2 2006.161.07:41:11.27#ibcon#wrote, iclass 31, count 2 2006.161.07:41:11.27#ibcon#about to read 3, iclass 31, count 2 2006.161.07:41:11.29#ibcon#read 3, iclass 31, count 2 2006.161.07:41:11.29#ibcon#about to read 4, iclass 31, count 2 2006.161.07:41:11.29#ibcon#read 4, iclass 31, count 2 2006.161.07:41:11.29#ibcon#about to read 5, iclass 31, count 2 2006.161.07:41:11.29#ibcon#read 5, iclass 31, count 2 2006.161.07:41:11.29#ibcon#about to read 6, iclass 31, count 2 2006.161.07:41:11.29#ibcon#read 6, iclass 31, count 2 2006.161.07:41:11.29#ibcon#end of sib2, iclass 31, count 2 2006.161.07:41:11.29#ibcon#*mode == 0, iclass 31, count 2 2006.161.07:41:11.29#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.07:41:11.29#ibcon#[25=AT06-06\r\n] 2006.161.07:41:11.29#ibcon#*before write, iclass 31, count 2 2006.161.07:41:11.29#ibcon#enter sib2, iclass 31, count 2 2006.161.07:41:11.29#ibcon#flushed, iclass 31, count 2 2006.161.07:41:11.29#ibcon#about to write, iclass 31, count 2 2006.161.07:41:11.29#ibcon#wrote, iclass 31, count 2 2006.161.07:41:11.29#ibcon#about to read 3, iclass 31, count 2 2006.161.07:41:11.32#ibcon#read 3, iclass 31, count 2 2006.161.07:41:11.32#ibcon#about to read 4, iclass 31, count 2 2006.161.07:41:11.32#ibcon#read 4, iclass 31, count 2 2006.161.07:41:11.32#ibcon#about to read 5, iclass 31, count 2 2006.161.07:41:11.32#ibcon#read 5, iclass 31, count 2 2006.161.07:41:11.32#ibcon#about to read 6, iclass 31, count 2 2006.161.07:41:11.32#ibcon#read 6, iclass 31, count 2 2006.161.07:41:11.32#ibcon#end of sib2, iclass 31, count 2 2006.161.07:41:11.32#ibcon#*after write, iclass 31, count 2 2006.161.07:41:11.32#ibcon#*before return 0, iclass 31, count 2 2006.161.07:41:11.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:11.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:11.32#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.07:41:11.32#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:11.32#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:41:11.44#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:41:11.44#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:41:11.44#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:41:11.44#ibcon#first serial, iclass 31, count 0 2006.161.07:41:11.44#ibcon#enter sib2, iclass 31, count 0 2006.161.07:41:11.44#ibcon#flushed, iclass 31, count 0 2006.161.07:41:11.44#ibcon#about to write, iclass 31, count 0 2006.161.07:41:11.44#ibcon#wrote, iclass 31, count 0 2006.161.07:41:11.44#ibcon#about to read 3, iclass 31, count 0 2006.161.07:41:11.46#ibcon#read 3, iclass 31, count 0 2006.161.07:41:11.46#ibcon#about to read 4, iclass 31, count 0 2006.161.07:41:11.46#ibcon#read 4, iclass 31, count 0 2006.161.07:41:11.46#ibcon#about to read 5, iclass 31, count 0 2006.161.07:41:11.46#ibcon#read 5, iclass 31, count 0 2006.161.07:41:11.46#ibcon#about to read 6, iclass 31, count 0 2006.161.07:41:11.46#ibcon#read 6, iclass 31, count 0 2006.161.07:41:11.46#ibcon#end of sib2, iclass 31, count 0 2006.161.07:41:11.46#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:41:11.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:41:11.46#ibcon#[25=USB\r\n] 2006.161.07:41:11.46#ibcon#*before write, iclass 31, count 0 2006.161.07:41:11.46#ibcon#enter sib2, iclass 31, count 0 2006.161.07:41:11.46#ibcon#flushed, iclass 31, count 0 2006.161.07:41:11.46#ibcon#about to write, iclass 31, count 0 2006.161.07:41:11.46#ibcon#wrote, iclass 31, count 0 2006.161.07:41:11.46#ibcon#about to read 3, iclass 31, count 0 2006.161.07:41:11.49#ibcon#read 3, iclass 31, count 0 2006.161.07:41:11.49#ibcon#about to read 4, iclass 31, count 0 2006.161.07:41:11.49#ibcon#read 4, iclass 31, count 0 2006.161.07:41:11.49#ibcon#about to read 5, iclass 31, count 0 2006.161.07:41:11.49#ibcon#read 5, iclass 31, count 0 2006.161.07:41:11.49#ibcon#about to read 6, iclass 31, count 0 2006.161.07:41:11.49#ibcon#read 6, iclass 31, count 0 2006.161.07:41:11.49#ibcon#end of sib2, iclass 31, count 0 2006.161.07:41:11.49#ibcon#*after write, iclass 31, count 0 2006.161.07:41:11.49#ibcon#*before return 0, iclass 31, count 0 2006.161.07:41:11.49#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:41:11.49#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:41:11.49#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:41:11.49#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:41:11.49$vc4f8/valo=7,832.99 2006.161.07:41:11.49#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:41:11.49#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:41:11.49#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:11.49#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:41:11.49#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:41:11.49#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:41:11.49#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:41:11.49#ibcon#first serial, iclass 33, count 0 2006.161.07:41:11.49#ibcon#enter sib2, iclass 33, count 0 2006.161.07:41:11.49#ibcon#flushed, iclass 33, count 0 2006.161.07:41:11.49#ibcon#about to write, iclass 33, count 0 2006.161.07:41:11.49#ibcon#wrote, iclass 33, count 0 2006.161.07:41:11.49#ibcon#about to read 3, iclass 33, count 0 2006.161.07:41:11.51#ibcon#read 3, iclass 33, count 0 2006.161.07:41:11.51#ibcon#about to read 4, iclass 33, count 0 2006.161.07:41:11.51#ibcon#read 4, iclass 33, count 0 2006.161.07:41:11.51#ibcon#about to read 5, iclass 33, count 0 2006.161.07:41:11.51#ibcon#read 5, iclass 33, count 0 2006.161.07:41:11.51#ibcon#about to read 6, iclass 33, count 0 2006.161.07:41:11.51#ibcon#read 6, iclass 33, count 0 2006.161.07:41:11.51#ibcon#end of sib2, iclass 33, count 0 2006.161.07:41:11.51#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:41:11.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:41:11.51#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:41:11.51#ibcon#*before write, iclass 33, count 0 2006.161.07:41:11.51#ibcon#enter sib2, iclass 33, count 0 2006.161.07:41:11.51#ibcon#flushed, iclass 33, count 0 2006.161.07:41:11.51#ibcon#about to write, iclass 33, count 0 2006.161.07:41:11.51#ibcon#wrote, iclass 33, count 0 2006.161.07:41:11.51#ibcon#about to read 3, iclass 33, count 0 2006.161.07:41:11.55#ibcon#read 3, iclass 33, count 0 2006.161.07:41:11.55#ibcon#about to read 4, iclass 33, count 0 2006.161.07:41:11.55#ibcon#read 4, iclass 33, count 0 2006.161.07:41:11.55#ibcon#about to read 5, iclass 33, count 0 2006.161.07:41:11.55#ibcon#read 5, iclass 33, count 0 2006.161.07:41:11.55#ibcon#about to read 6, iclass 33, count 0 2006.161.07:41:11.55#ibcon#read 6, iclass 33, count 0 2006.161.07:41:11.55#ibcon#end of sib2, iclass 33, count 0 2006.161.07:41:11.55#ibcon#*after write, iclass 33, count 0 2006.161.07:41:11.55#ibcon#*before return 0, iclass 33, count 0 2006.161.07:41:11.55#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:41:11.55#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:41:11.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:41:11.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:41:11.55$vc4f8/va=7,6 2006.161.07:41:11.55#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.07:41:11.55#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.07:41:11.55#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:11.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:41:11.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:41:11.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:41:11.62#ibcon#enter wrdev, iclass 35, count 2 2006.161.07:41:11.62#ibcon#first serial, iclass 35, count 2 2006.161.07:41:11.62#ibcon#enter sib2, iclass 35, count 2 2006.161.07:41:11.62#ibcon#flushed, iclass 35, count 2 2006.161.07:41:11.62#ibcon#about to write, iclass 35, count 2 2006.161.07:41:11.62#ibcon#wrote, iclass 35, count 2 2006.161.07:41:11.62#ibcon#about to read 3, iclass 35, count 2 2006.161.07:41:11.63#ibcon#read 3, iclass 35, count 2 2006.161.07:41:11.63#ibcon#about to read 4, iclass 35, count 2 2006.161.07:41:11.63#ibcon#read 4, iclass 35, count 2 2006.161.07:41:11.63#ibcon#about to read 5, iclass 35, count 2 2006.161.07:41:11.63#ibcon#read 5, iclass 35, count 2 2006.161.07:41:11.63#ibcon#about to read 6, iclass 35, count 2 2006.161.07:41:11.63#ibcon#read 6, iclass 35, count 2 2006.161.07:41:11.63#ibcon#end of sib2, iclass 35, count 2 2006.161.07:41:11.63#ibcon#*mode == 0, iclass 35, count 2 2006.161.07:41:11.63#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.07:41:11.63#ibcon#[25=AT07-06\r\n] 2006.161.07:41:11.63#ibcon#*before write, iclass 35, count 2 2006.161.07:41:11.63#ibcon#enter sib2, iclass 35, count 2 2006.161.07:41:11.63#ibcon#flushed, iclass 35, count 2 2006.161.07:41:11.63#ibcon#about to write, iclass 35, count 2 2006.161.07:41:11.63#ibcon#wrote, iclass 35, count 2 2006.161.07:41:11.63#ibcon#about to read 3, iclass 35, count 2 2006.161.07:41:11.66#ibcon#read 3, iclass 35, count 2 2006.161.07:41:11.66#ibcon#about to read 4, iclass 35, count 2 2006.161.07:41:11.66#ibcon#read 4, iclass 35, count 2 2006.161.07:41:11.66#ibcon#about to read 5, iclass 35, count 2 2006.161.07:41:11.66#ibcon#read 5, iclass 35, count 2 2006.161.07:41:11.66#ibcon#about to read 6, iclass 35, count 2 2006.161.07:41:11.66#ibcon#read 6, iclass 35, count 2 2006.161.07:41:11.66#ibcon#end of sib2, iclass 35, count 2 2006.161.07:41:11.66#ibcon#*after write, iclass 35, count 2 2006.161.07:41:11.66#ibcon#*before return 0, iclass 35, count 2 2006.161.07:41:11.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:41:11.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:41:11.66#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.07:41:11.66#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:11.66#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:41:11.78#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:41:11.78#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:41:11.78#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:41:11.78#ibcon#first serial, iclass 35, count 0 2006.161.07:41:11.78#ibcon#enter sib2, iclass 35, count 0 2006.161.07:41:11.78#ibcon#flushed, iclass 35, count 0 2006.161.07:41:11.78#ibcon#about to write, iclass 35, count 0 2006.161.07:41:11.78#ibcon#wrote, iclass 35, count 0 2006.161.07:41:11.78#ibcon#about to read 3, iclass 35, count 0 2006.161.07:41:11.80#ibcon#read 3, iclass 35, count 0 2006.161.07:41:11.80#ibcon#about to read 4, iclass 35, count 0 2006.161.07:41:11.80#ibcon#read 4, iclass 35, count 0 2006.161.07:41:11.80#ibcon#about to read 5, iclass 35, count 0 2006.161.07:41:11.80#ibcon#read 5, iclass 35, count 0 2006.161.07:41:11.80#ibcon#about to read 6, iclass 35, count 0 2006.161.07:41:11.80#ibcon#read 6, iclass 35, count 0 2006.161.07:41:11.80#ibcon#end of sib2, iclass 35, count 0 2006.161.07:41:11.80#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:41:11.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:41:11.80#ibcon#[25=USB\r\n] 2006.161.07:41:11.80#ibcon#*before write, iclass 35, count 0 2006.161.07:41:11.80#ibcon#enter sib2, iclass 35, count 0 2006.161.07:41:11.80#ibcon#flushed, iclass 35, count 0 2006.161.07:41:11.80#ibcon#about to write, iclass 35, count 0 2006.161.07:41:11.80#ibcon#wrote, iclass 35, count 0 2006.161.07:41:11.80#ibcon#about to read 3, iclass 35, count 0 2006.161.07:41:11.83#ibcon#read 3, iclass 35, count 0 2006.161.07:41:11.83#ibcon#about to read 4, iclass 35, count 0 2006.161.07:41:11.83#ibcon#read 4, iclass 35, count 0 2006.161.07:41:11.83#ibcon#about to read 5, iclass 35, count 0 2006.161.07:41:11.83#ibcon#read 5, iclass 35, count 0 2006.161.07:41:11.83#ibcon#about to read 6, iclass 35, count 0 2006.161.07:41:11.83#ibcon#read 6, iclass 35, count 0 2006.161.07:41:11.83#ibcon#end of sib2, iclass 35, count 0 2006.161.07:41:11.83#ibcon#*after write, iclass 35, count 0 2006.161.07:41:11.83#ibcon#*before return 0, iclass 35, count 0 2006.161.07:41:11.83#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:41:11.83#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:41:11.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:41:11.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:41:11.83$vc4f8/valo=8,852.99 2006.161.07:41:11.83#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:41:11.83#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:41:11.83#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:11.83#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:41:11.83#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:41:11.83#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:41:11.83#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:41:11.83#ibcon#first serial, iclass 37, count 0 2006.161.07:41:11.83#ibcon#enter sib2, iclass 37, count 0 2006.161.07:41:11.83#ibcon#flushed, iclass 37, count 0 2006.161.07:41:11.83#ibcon#about to write, iclass 37, count 0 2006.161.07:41:11.83#ibcon#wrote, iclass 37, count 0 2006.161.07:41:11.83#ibcon#about to read 3, iclass 37, count 0 2006.161.07:41:11.85#ibcon#read 3, iclass 37, count 0 2006.161.07:41:11.85#ibcon#about to read 4, iclass 37, count 0 2006.161.07:41:11.85#ibcon#read 4, iclass 37, count 0 2006.161.07:41:11.85#ibcon#about to read 5, iclass 37, count 0 2006.161.07:41:11.85#ibcon#read 5, iclass 37, count 0 2006.161.07:41:11.85#ibcon#about to read 6, iclass 37, count 0 2006.161.07:41:11.85#ibcon#read 6, iclass 37, count 0 2006.161.07:41:11.85#ibcon#end of sib2, iclass 37, count 0 2006.161.07:41:11.85#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:41:11.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:41:11.85#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:41:11.85#ibcon#*before write, iclass 37, count 0 2006.161.07:41:11.85#ibcon#enter sib2, iclass 37, count 0 2006.161.07:41:11.85#ibcon#flushed, iclass 37, count 0 2006.161.07:41:11.85#ibcon#about to write, iclass 37, count 0 2006.161.07:41:11.85#ibcon#wrote, iclass 37, count 0 2006.161.07:41:11.85#ibcon#about to read 3, iclass 37, count 0 2006.161.07:41:11.89#ibcon#read 3, iclass 37, count 0 2006.161.07:41:11.89#ibcon#about to read 4, iclass 37, count 0 2006.161.07:41:11.89#ibcon#read 4, iclass 37, count 0 2006.161.07:41:11.89#ibcon#about to read 5, iclass 37, count 0 2006.161.07:41:11.89#ibcon#read 5, iclass 37, count 0 2006.161.07:41:11.89#ibcon#about to read 6, iclass 37, count 0 2006.161.07:41:11.89#ibcon#read 6, iclass 37, count 0 2006.161.07:41:11.89#ibcon#end of sib2, iclass 37, count 0 2006.161.07:41:11.89#ibcon#*after write, iclass 37, count 0 2006.161.07:41:11.89#ibcon#*before return 0, iclass 37, count 0 2006.161.07:41:11.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:41:11.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:41:11.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:41:11.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:41:11.89$vc4f8/va=8,7 2006.161.07:41:11.89#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.07:41:11.89#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.07:41:11.89#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:11.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:41:11.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:41:11.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:41:11.96#ibcon#enter wrdev, iclass 39, count 2 2006.161.07:41:11.96#ibcon#first serial, iclass 39, count 2 2006.161.07:41:11.96#ibcon#enter sib2, iclass 39, count 2 2006.161.07:41:11.96#ibcon#flushed, iclass 39, count 2 2006.161.07:41:11.96#ibcon#about to write, iclass 39, count 2 2006.161.07:41:11.96#ibcon#wrote, iclass 39, count 2 2006.161.07:41:11.96#ibcon#about to read 3, iclass 39, count 2 2006.161.07:41:11.97#ibcon#read 3, iclass 39, count 2 2006.161.07:41:11.97#ibcon#about to read 4, iclass 39, count 2 2006.161.07:41:11.97#ibcon#read 4, iclass 39, count 2 2006.161.07:41:11.97#ibcon#about to read 5, iclass 39, count 2 2006.161.07:41:11.97#ibcon#read 5, iclass 39, count 2 2006.161.07:41:11.97#ibcon#about to read 6, iclass 39, count 2 2006.161.07:41:11.97#ibcon#read 6, iclass 39, count 2 2006.161.07:41:11.97#ibcon#end of sib2, iclass 39, count 2 2006.161.07:41:11.97#ibcon#*mode == 0, iclass 39, count 2 2006.161.07:41:11.97#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.07:41:11.97#ibcon#[25=AT08-07\r\n] 2006.161.07:41:11.97#ibcon#*before write, iclass 39, count 2 2006.161.07:41:11.97#ibcon#enter sib2, iclass 39, count 2 2006.161.07:41:11.97#ibcon#flushed, iclass 39, count 2 2006.161.07:41:11.97#ibcon#about to write, iclass 39, count 2 2006.161.07:41:11.97#ibcon#wrote, iclass 39, count 2 2006.161.07:41:11.97#ibcon#about to read 3, iclass 39, count 2 2006.161.07:41:12.00#ibcon#read 3, iclass 39, count 2 2006.161.07:41:12.00#ibcon#about to read 4, iclass 39, count 2 2006.161.07:41:12.00#ibcon#read 4, iclass 39, count 2 2006.161.07:41:12.00#ibcon#about to read 5, iclass 39, count 2 2006.161.07:41:12.00#ibcon#read 5, iclass 39, count 2 2006.161.07:41:12.00#ibcon#about to read 6, iclass 39, count 2 2006.161.07:41:12.00#ibcon#read 6, iclass 39, count 2 2006.161.07:41:12.00#ibcon#end of sib2, iclass 39, count 2 2006.161.07:41:12.00#ibcon#*after write, iclass 39, count 2 2006.161.07:41:12.00#ibcon#*before return 0, iclass 39, count 2 2006.161.07:41:12.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:41:12.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:41:12.00#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.07:41:12.00#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:12.00#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:41:12.12#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:41:12.12#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:41:12.12#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:41:12.12#ibcon#first serial, iclass 39, count 0 2006.161.07:41:12.12#ibcon#enter sib2, iclass 39, count 0 2006.161.07:41:12.12#ibcon#flushed, iclass 39, count 0 2006.161.07:41:12.12#ibcon#about to write, iclass 39, count 0 2006.161.07:41:12.12#ibcon#wrote, iclass 39, count 0 2006.161.07:41:12.12#ibcon#about to read 3, iclass 39, count 0 2006.161.07:41:12.14#ibcon#read 3, iclass 39, count 0 2006.161.07:41:12.14#ibcon#about to read 4, iclass 39, count 0 2006.161.07:41:12.14#ibcon#read 4, iclass 39, count 0 2006.161.07:41:12.14#ibcon#about to read 5, iclass 39, count 0 2006.161.07:41:12.14#ibcon#read 5, iclass 39, count 0 2006.161.07:41:12.14#ibcon#about to read 6, iclass 39, count 0 2006.161.07:41:12.14#ibcon#read 6, iclass 39, count 0 2006.161.07:41:12.14#ibcon#end of sib2, iclass 39, count 0 2006.161.07:41:12.14#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:41:12.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:41:12.14#ibcon#[25=USB\r\n] 2006.161.07:41:12.14#ibcon#*before write, iclass 39, count 0 2006.161.07:41:12.14#ibcon#enter sib2, iclass 39, count 0 2006.161.07:41:12.14#ibcon#flushed, iclass 39, count 0 2006.161.07:41:12.14#ibcon#about to write, iclass 39, count 0 2006.161.07:41:12.14#ibcon#wrote, iclass 39, count 0 2006.161.07:41:12.14#ibcon#about to read 3, iclass 39, count 0 2006.161.07:41:12.17#ibcon#read 3, iclass 39, count 0 2006.161.07:41:12.17#ibcon#about to read 4, iclass 39, count 0 2006.161.07:41:12.17#ibcon#read 4, iclass 39, count 0 2006.161.07:41:12.17#ibcon#about to read 5, iclass 39, count 0 2006.161.07:41:12.17#ibcon#read 5, iclass 39, count 0 2006.161.07:41:12.17#ibcon#about to read 6, iclass 39, count 0 2006.161.07:41:12.17#ibcon#read 6, iclass 39, count 0 2006.161.07:41:12.17#ibcon#end of sib2, iclass 39, count 0 2006.161.07:41:12.17#ibcon#*after write, iclass 39, count 0 2006.161.07:41:12.17#ibcon#*before return 0, iclass 39, count 0 2006.161.07:41:12.17#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:41:12.17#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:41:12.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:41:12.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:41:12.17$vc4f8/vblo=1,632.99 2006.161.07:41:12.17#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.07:41:12.17#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.07:41:12.17#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:12.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:41:12.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:41:12.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:41:12.17#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:41:12.17#ibcon#first serial, iclass 3, count 0 2006.161.07:41:12.17#ibcon#enter sib2, iclass 3, count 0 2006.161.07:41:12.17#ibcon#flushed, iclass 3, count 0 2006.161.07:41:12.17#ibcon#about to write, iclass 3, count 0 2006.161.07:41:12.17#ibcon#wrote, iclass 3, count 0 2006.161.07:41:12.17#ibcon#about to read 3, iclass 3, count 0 2006.161.07:41:12.19#ibcon#read 3, iclass 3, count 0 2006.161.07:41:12.19#ibcon#about to read 4, iclass 3, count 0 2006.161.07:41:12.19#ibcon#read 4, iclass 3, count 0 2006.161.07:41:12.19#ibcon#about to read 5, iclass 3, count 0 2006.161.07:41:12.19#ibcon#read 5, iclass 3, count 0 2006.161.07:41:12.19#ibcon#about to read 6, iclass 3, count 0 2006.161.07:41:12.19#ibcon#read 6, iclass 3, count 0 2006.161.07:41:12.19#ibcon#end of sib2, iclass 3, count 0 2006.161.07:41:12.19#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:41:12.19#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:41:12.19#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:41:12.19#ibcon#*before write, iclass 3, count 0 2006.161.07:41:12.19#ibcon#enter sib2, iclass 3, count 0 2006.161.07:41:12.19#ibcon#flushed, iclass 3, count 0 2006.161.07:41:12.19#ibcon#about to write, iclass 3, count 0 2006.161.07:41:12.19#ibcon#wrote, iclass 3, count 0 2006.161.07:41:12.19#ibcon#about to read 3, iclass 3, count 0 2006.161.07:41:12.23#ibcon#read 3, iclass 3, count 0 2006.161.07:41:12.23#ibcon#about to read 4, iclass 3, count 0 2006.161.07:41:12.23#ibcon#read 4, iclass 3, count 0 2006.161.07:41:12.23#ibcon#about to read 5, iclass 3, count 0 2006.161.07:41:12.23#ibcon#read 5, iclass 3, count 0 2006.161.07:41:12.23#ibcon#about to read 6, iclass 3, count 0 2006.161.07:41:12.23#ibcon#read 6, iclass 3, count 0 2006.161.07:41:12.23#ibcon#end of sib2, iclass 3, count 0 2006.161.07:41:12.23#ibcon#*after write, iclass 3, count 0 2006.161.07:41:12.23#ibcon#*before return 0, iclass 3, count 0 2006.161.07:41:12.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:41:12.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:41:12.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:41:12.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:41:12.23$vc4f8/vb=1,4 2006.161.07:41:12.23#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.07:41:12.23#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.07:41:12.23#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:12.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:41:12.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:41:12.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:41:12.23#ibcon#enter wrdev, iclass 5, count 2 2006.161.07:41:12.23#ibcon#first serial, iclass 5, count 2 2006.161.07:41:12.23#ibcon#enter sib2, iclass 5, count 2 2006.161.07:41:12.23#ibcon#flushed, iclass 5, count 2 2006.161.07:41:12.23#ibcon#about to write, iclass 5, count 2 2006.161.07:41:12.23#ibcon#wrote, iclass 5, count 2 2006.161.07:41:12.23#ibcon#about to read 3, iclass 5, count 2 2006.161.07:41:12.25#ibcon#read 3, iclass 5, count 2 2006.161.07:41:12.25#ibcon#about to read 4, iclass 5, count 2 2006.161.07:41:12.25#ibcon#read 4, iclass 5, count 2 2006.161.07:41:12.25#ibcon#about to read 5, iclass 5, count 2 2006.161.07:41:12.25#ibcon#read 5, iclass 5, count 2 2006.161.07:41:12.25#ibcon#about to read 6, iclass 5, count 2 2006.161.07:41:12.25#ibcon#read 6, iclass 5, count 2 2006.161.07:41:12.25#ibcon#end of sib2, iclass 5, count 2 2006.161.07:41:12.25#ibcon#*mode == 0, iclass 5, count 2 2006.161.07:41:12.25#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.07:41:12.25#ibcon#[27=AT01-04\r\n] 2006.161.07:41:12.25#ibcon#*before write, iclass 5, count 2 2006.161.07:41:12.25#ibcon#enter sib2, iclass 5, count 2 2006.161.07:41:12.25#ibcon#flushed, iclass 5, count 2 2006.161.07:41:12.25#ibcon#about to write, iclass 5, count 2 2006.161.07:41:12.25#ibcon#wrote, iclass 5, count 2 2006.161.07:41:12.25#ibcon#about to read 3, iclass 5, count 2 2006.161.07:41:12.28#ibcon#read 3, iclass 5, count 2 2006.161.07:41:12.28#ibcon#about to read 4, iclass 5, count 2 2006.161.07:41:12.28#ibcon#read 4, iclass 5, count 2 2006.161.07:41:12.28#ibcon#about to read 5, iclass 5, count 2 2006.161.07:41:12.28#ibcon#read 5, iclass 5, count 2 2006.161.07:41:12.28#ibcon#about to read 6, iclass 5, count 2 2006.161.07:41:12.28#ibcon#read 6, iclass 5, count 2 2006.161.07:41:12.28#ibcon#end of sib2, iclass 5, count 2 2006.161.07:41:12.28#ibcon#*after write, iclass 5, count 2 2006.161.07:41:12.28#ibcon#*before return 0, iclass 5, count 2 2006.161.07:41:12.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:41:12.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:41:12.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.07:41:12.28#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:12.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:41:12.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:41:12.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:41:12.40#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:41:12.40#ibcon#first serial, iclass 5, count 0 2006.161.07:41:12.40#ibcon#enter sib2, iclass 5, count 0 2006.161.07:41:12.40#ibcon#flushed, iclass 5, count 0 2006.161.07:41:12.40#ibcon#about to write, iclass 5, count 0 2006.161.07:41:12.40#ibcon#wrote, iclass 5, count 0 2006.161.07:41:12.40#ibcon#about to read 3, iclass 5, count 0 2006.161.07:41:12.42#ibcon#read 3, iclass 5, count 0 2006.161.07:41:12.42#ibcon#about to read 4, iclass 5, count 0 2006.161.07:41:12.42#ibcon#read 4, iclass 5, count 0 2006.161.07:41:12.42#ibcon#about to read 5, iclass 5, count 0 2006.161.07:41:12.42#ibcon#read 5, iclass 5, count 0 2006.161.07:41:12.42#ibcon#about to read 6, iclass 5, count 0 2006.161.07:41:12.42#ibcon#read 6, iclass 5, count 0 2006.161.07:41:12.42#ibcon#end of sib2, iclass 5, count 0 2006.161.07:41:12.42#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:41:12.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:41:12.42#ibcon#[27=USB\r\n] 2006.161.07:41:12.42#ibcon#*before write, iclass 5, count 0 2006.161.07:41:12.42#ibcon#enter sib2, iclass 5, count 0 2006.161.07:41:12.42#ibcon#flushed, iclass 5, count 0 2006.161.07:41:12.42#ibcon#about to write, iclass 5, count 0 2006.161.07:41:12.42#ibcon#wrote, iclass 5, count 0 2006.161.07:41:12.42#ibcon#about to read 3, iclass 5, count 0 2006.161.07:41:12.45#ibcon#read 3, iclass 5, count 0 2006.161.07:41:12.45#ibcon#about to read 4, iclass 5, count 0 2006.161.07:41:12.45#ibcon#read 4, iclass 5, count 0 2006.161.07:41:12.45#ibcon#about to read 5, iclass 5, count 0 2006.161.07:41:12.45#ibcon#read 5, iclass 5, count 0 2006.161.07:41:12.45#ibcon#about to read 6, iclass 5, count 0 2006.161.07:41:12.45#ibcon#read 6, iclass 5, count 0 2006.161.07:41:12.45#ibcon#end of sib2, iclass 5, count 0 2006.161.07:41:12.45#ibcon#*after write, iclass 5, count 0 2006.161.07:41:12.45#ibcon#*before return 0, iclass 5, count 0 2006.161.07:41:12.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:41:12.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:41:12.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:41:12.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:41:12.45$vc4f8/vblo=2,640.99 2006.161.07:41:12.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:41:12.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:41:12.45#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:12.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:12.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:12.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:12.45#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:41:12.45#ibcon#first serial, iclass 7, count 0 2006.161.07:41:12.45#ibcon#enter sib2, iclass 7, count 0 2006.161.07:41:12.45#ibcon#flushed, iclass 7, count 0 2006.161.07:41:12.45#ibcon#about to write, iclass 7, count 0 2006.161.07:41:12.45#ibcon#wrote, iclass 7, count 0 2006.161.07:41:12.45#ibcon#about to read 3, iclass 7, count 0 2006.161.07:41:12.47#ibcon#read 3, iclass 7, count 0 2006.161.07:41:12.47#ibcon#about to read 4, iclass 7, count 0 2006.161.07:41:12.47#ibcon#read 4, iclass 7, count 0 2006.161.07:41:12.47#ibcon#about to read 5, iclass 7, count 0 2006.161.07:41:12.47#ibcon#read 5, iclass 7, count 0 2006.161.07:41:12.47#ibcon#about to read 6, iclass 7, count 0 2006.161.07:41:12.47#ibcon#read 6, iclass 7, count 0 2006.161.07:41:12.47#ibcon#end of sib2, iclass 7, count 0 2006.161.07:41:12.47#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:41:12.47#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:41:12.47#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:41:12.47#ibcon#*before write, iclass 7, count 0 2006.161.07:41:12.47#ibcon#enter sib2, iclass 7, count 0 2006.161.07:41:12.47#ibcon#flushed, iclass 7, count 0 2006.161.07:41:12.47#ibcon#about to write, iclass 7, count 0 2006.161.07:41:12.47#ibcon#wrote, iclass 7, count 0 2006.161.07:41:12.47#ibcon#about to read 3, iclass 7, count 0 2006.161.07:41:12.51#ibcon#read 3, iclass 7, count 0 2006.161.07:41:12.51#ibcon#about to read 4, iclass 7, count 0 2006.161.07:41:12.51#ibcon#read 4, iclass 7, count 0 2006.161.07:41:12.51#ibcon#about to read 5, iclass 7, count 0 2006.161.07:41:12.51#ibcon#read 5, iclass 7, count 0 2006.161.07:41:12.51#ibcon#about to read 6, iclass 7, count 0 2006.161.07:41:12.51#ibcon#read 6, iclass 7, count 0 2006.161.07:41:12.51#ibcon#end of sib2, iclass 7, count 0 2006.161.07:41:12.51#ibcon#*after write, iclass 7, count 0 2006.161.07:41:12.51#ibcon#*before return 0, iclass 7, count 0 2006.161.07:41:12.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:12.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:41:12.51#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:41:12.51#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:41:12.51$vc4f8/vb=2,4 2006.161.07:41:12.51#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:41:12.51#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:41:12.51#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:12.51#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:12.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:12.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:12.57#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:41:12.57#ibcon#first serial, iclass 11, count 2 2006.161.07:41:12.57#ibcon#enter sib2, iclass 11, count 2 2006.161.07:41:12.57#ibcon#flushed, iclass 11, count 2 2006.161.07:41:12.57#ibcon#about to write, iclass 11, count 2 2006.161.07:41:12.57#ibcon#wrote, iclass 11, count 2 2006.161.07:41:12.57#ibcon#about to read 3, iclass 11, count 2 2006.161.07:41:12.59#ibcon#read 3, iclass 11, count 2 2006.161.07:41:12.59#ibcon#about to read 4, iclass 11, count 2 2006.161.07:41:12.59#ibcon#read 4, iclass 11, count 2 2006.161.07:41:12.59#ibcon#about to read 5, iclass 11, count 2 2006.161.07:41:12.59#ibcon#read 5, iclass 11, count 2 2006.161.07:41:12.59#ibcon#about to read 6, iclass 11, count 2 2006.161.07:41:12.59#ibcon#read 6, iclass 11, count 2 2006.161.07:41:12.59#ibcon#end of sib2, iclass 11, count 2 2006.161.07:41:12.59#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:41:12.59#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:41:12.59#ibcon#[27=AT02-04\r\n] 2006.161.07:41:12.59#ibcon#*before write, iclass 11, count 2 2006.161.07:41:12.59#ibcon#enter sib2, iclass 11, count 2 2006.161.07:41:12.59#ibcon#flushed, iclass 11, count 2 2006.161.07:41:12.59#ibcon#about to write, iclass 11, count 2 2006.161.07:41:12.59#ibcon#wrote, iclass 11, count 2 2006.161.07:41:12.59#ibcon#about to read 3, iclass 11, count 2 2006.161.07:41:12.62#ibcon#read 3, iclass 11, count 2 2006.161.07:41:12.62#ibcon#about to read 4, iclass 11, count 2 2006.161.07:41:12.62#ibcon#read 4, iclass 11, count 2 2006.161.07:41:12.62#ibcon#about to read 5, iclass 11, count 2 2006.161.07:41:12.62#ibcon#read 5, iclass 11, count 2 2006.161.07:41:12.62#ibcon#about to read 6, iclass 11, count 2 2006.161.07:41:12.62#ibcon#read 6, iclass 11, count 2 2006.161.07:41:12.62#ibcon#end of sib2, iclass 11, count 2 2006.161.07:41:12.62#ibcon#*after write, iclass 11, count 2 2006.161.07:41:12.62#ibcon#*before return 0, iclass 11, count 2 2006.161.07:41:12.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:12.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:41:12.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:41:12.62#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:12.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:12.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:12.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:12.74#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:41:12.74#ibcon#first serial, iclass 11, count 0 2006.161.07:41:12.74#ibcon#enter sib2, iclass 11, count 0 2006.161.07:41:12.74#ibcon#flushed, iclass 11, count 0 2006.161.07:41:12.74#ibcon#about to write, iclass 11, count 0 2006.161.07:41:12.74#ibcon#wrote, iclass 11, count 0 2006.161.07:41:12.74#ibcon#about to read 3, iclass 11, count 0 2006.161.07:41:12.76#ibcon#read 3, iclass 11, count 0 2006.161.07:41:12.76#ibcon#about to read 4, iclass 11, count 0 2006.161.07:41:12.76#ibcon#read 4, iclass 11, count 0 2006.161.07:41:12.76#ibcon#about to read 5, iclass 11, count 0 2006.161.07:41:12.76#ibcon#read 5, iclass 11, count 0 2006.161.07:41:12.76#ibcon#about to read 6, iclass 11, count 0 2006.161.07:41:12.76#ibcon#read 6, iclass 11, count 0 2006.161.07:41:12.76#ibcon#end of sib2, iclass 11, count 0 2006.161.07:41:12.76#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:41:12.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:41:12.76#ibcon#[27=USB\r\n] 2006.161.07:41:12.76#ibcon#*before write, iclass 11, count 0 2006.161.07:41:12.76#ibcon#enter sib2, iclass 11, count 0 2006.161.07:41:12.76#ibcon#flushed, iclass 11, count 0 2006.161.07:41:12.76#ibcon#about to write, iclass 11, count 0 2006.161.07:41:12.76#ibcon#wrote, iclass 11, count 0 2006.161.07:41:12.76#ibcon#about to read 3, iclass 11, count 0 2006.161.07:41:12.79#ibcon#read 3, iclass 11, count 0 2006.161.07:41:12.79#ibcon#about to read 4, iclass 11, count 0 2006.161.07:41:12.79#ibcon#read 4, iclass 11, count 0 2006.161.07:41:12.79#ibcon#about to read 5, iclass 11, count 0 2006.161.07:41:12.79#ibcon#read 5, iclass 11, count 0 2006.161.07:41:12.79#ibcon#about to read 6, iclass 11, count 0 2006.161.07:41:12.79#ibcon#read 6, iclass 11, count 0 2006.161.07:41:12.79#ibcon#end of sib2, iclass 11, count 0 2006.161.07:41:12.79#ibcon#*after write, iclass 11, count 0 2006.161.07:41:12.79#ibcon#*before return 0, iclass 11, count 0 2006.161.07:41:12.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:12.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:41:12.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:41:12.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:41:12.79$vc4f8/vblo=3,656.99 2006.161.07:41:12.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:41:12.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:41:12.79#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:12.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:12.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:12.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:12.79#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:41:12.79#ibcon#first serial, iclass 13, count 0 2006.161.07:41:12.79#ibcon#enter sib2, iclass 13, count 0 2006.161.07:41:12.79#ibcon#flushed, iclass 13, count 0 2006.161.07:41:12.79#ibcon#about to write, iclass 13, count 0 2006.161.07:41:12.79#ibcon#wrote, iclass 13, count 0 2006.161.07:41:12.79#ibcon#about to read 3, iclass 13, count 0 2006.161.07:41:12.81#ibcon#read 3, iclass 13, count 0 2006.161.07:41:12.81#ibcon#about to read 4, iclass 13, count 0 2006.161.07:41:12.81#ibcon#read 4, iclass 13, count 0 2006.161.07:41:12.81#ibcon#about to read 5, iclass 13, count 0 2006.161.07:41:12.81#ibcon#read 5, iclass 13, count 0 2006.161.07:41:12.81#ibcon#about to read 6, iclass 13, count 0 2006.161.07:41:12.81#ibcon#read 6, iclass 13, count 0 2006.161.07:41:12.81#ibcon#end of sib2, iclass 13, count 0 2006.161.07:41:12.81#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:41:12.81#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:41:12.81#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:41:12.81#ibcon#*before write, iclass 13, count 0 2006.161.07:41:12.81#ibcon#enter sib2, iclass 13, count 0 2006.161.07:41:12.81#ibcon#flushed, iclass 13, count 0 2006.161.07:41:12.81#ibcon#about to write, iclass 13, count 0 2006.161.07:41:12.81#ibcon#wrote, iclass 13, count 0 2006.161.07:41:12.81#ibcon#about to read 3, iclass 13, count 0 2006.161.07:41:12.85#ibcon#read 3, iclass 13, count 0 2006.161.07:41:12.85#ibcon#about to read 4, iclass 13, count 0 2006.161.07:41:12.85#ibcon#read 4, iclass 13, count 0 2006.161.07:41:12.85#ibcon#about to read 5, iclass 13, count 0 2006.161.07:41:12.85#ibcon#read 5, iclass 13, count 0 2006.161.07:41:12.85#ibcon#about to read 6, iclass 13, count 0 2006.161.07:41:12.85#ibcon#read 6, iclass 13, count 0 2006.161.07:41:12.85#ibcon#end of sib2, iclass 13, count 0 2006.161.07:41:12.85#ibcon#*after write, iclass 13, count 0 2006.161.07:41:12.85#ibcon#*before return 0, iclass 13, count 0 2006.161.07:41:12.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:12.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:41:12.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:41:12.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:41:12.85$vc4f8/vb=3,4 2006.161.07:41:12.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:41:12.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:41:12.85#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:12.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:12.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:12.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:12.92#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:41:12.92#ibcon#first serial, iclass 15, count 2 2006.161.07:41:12.92#ibcon#enter sib2, iclass 15, count 2 2006.161.07:41:12.92#ibcon#flushed, iclass 15, count 2 2006.161.07:41:12.92#ibcon#about to write, iclass 15, count 2 2006.161.07:41:12.92#ibcon#wrote, iclass 15, count 2 2006.161.07:41:12.92#ibcon#about to read 3, iclass 15, count 2 2006.161.07:41:12.93#ibcon#read 3, iclass 15, count 2 2006.161.07:41:12.93#ibcon#about to read 4, iclass 15, count 2 2006.161.07:41:12.93#ibcon#read 4, iclass 15, count 2 2006.161.07:41:12.93#ibcon#about to read 5, iclass 15, count 2 2006.161.07:41:12.93#ibcon#read 5, iclass 15, count 2 2006.161.07:41:12.93#ibcon#about to read 6, iclass 15, count 2 2006.161.07:41:12.93#ibcon#read 6, iclass 15, count 2 2006.161.07:41:12.93#ibcon#end of sib2, iclass 15, count 2 2006.161.07:41:12.93#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:41:12.93#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:41:12.93#ibcon#[27=AT03-04\r\n] 2006.161.07:41:12.93#ibcon#*before write, iclass 15, count 2 2006.161.07:41:12.93#ibcon#enter sib2, iclass 15, count 2 2006.161.07:41:12.93#ibcon#flushed, iclass 15, count 2 2006.161.07:41:12.93#ibcon#about to write, iclass 15, count 2 2006.161.07:41:12.93#ibcon#wrote, iclass 15, count 2 2006.161.07:41:12.93#ibcon#about to read 3, iclass 15, count 2 2006.161.07:41:12.96#ibcon#read 3, iclass 15, count 2 2006.161.07:41:12.96#ibcon#about to read 4, iclass 15, count 2 2006.161.07:41:12.96#ibcon#read 4, iclass 15, count 2 2006.161.07:41:12.96#ibcon#about to read 5, iclass 15, count 2 2006.161.07:41:12.96#ibcon#read 5, iclass 15, count 2 2006.161.07:41:12.96#ibcon#about to read 6, iclass 15, count 2 2006.161.07:41:12.96#ibcon#read 6, iclass 15, count 2 2006.161.07:41:12.96#ibcon#end of sib2, iclass 15, count 2 2006.161.07:41:12.96#ibcon#*after write, iclass 15, count 2 2006.161.07:41:12.96#ibcon#*before return 0, iclass 15, count 2 2006.161.07:41:12.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:12.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:41:12.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:41:12.96#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:12.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:13.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:13.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:13.08#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:41:13.08#ibcon#first serial, iclass 15, count 0 2006.161.07:41:13.08#ibcon#enter sib2, iclass 15, count 0 2006.161.07:41:13.08#ibcon#flushed, iclass 15, count 0 2006.161.07:41:13.08#ibcon#about to write, iclass 15, count 0 2006.161.07:41:13.08#ibcon#wrote, iclass 15, count 0 2006.161.07:41:13.08#ibcon#about to read 3, iclass 15, count 0 2006.161.07:41:13.12#ibcon#read 3, iclass 15, count 0 2006.161.07:41:13.12#ibcon#about to read 4, iclass 15, count 0 2006.161.07:41:13.12#ibcon#read 4, iclass 15, count 0 2006.161.07:41:13.12#ibcon#about to read 5, iclass 15, count 0 2006.161.07:41:13.12#ibcon#read 5, iclass 15, count 0 2006.161.07:41:13.12#ibcon#about to read 6, iclass 15, count 0 2006.161.07:41:13.12#ibcon#read 6, iclass 15, count 0 2006.161.07:41:13.12#ibcon#end of sib2, iclass 15, count 0 2006.161.07:41:13.12#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:41:13.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:41:13.12#ibcon#[27=USB\r\n] 2006.161.07:41:13.12#ibcon#*before write, iclass 15, count 0 2006.161.07:41:13.12#ibcon#enter sib2, iclass 15, count 0 2006.161.07:41:13.12#ibcon#flushed, iclass 15, count 0 2006.161.07:41:13.12#ibcon#about to write, iclass 15, count 0 2006.161.07:41:13.12#ibcon#wrote, iclass 15, count 0 2006.161.07:41:13.12#ibcon#about to read 3, iclass 15, count 0 2006.161.07:41:13.15#ibcon#read 3, iclass 15, count 0 2006.161.07:41:13.15#ibcon#about to read 4, iclass 15, count 0 2006.161.07:41:13.15#ibcon#read 4, iclass 15, count 0 2006.161.07:41:13.15#ibcon#about to read 5, iclass 15, count 0 2006.161.07:41:13.15#ibcon#read 5, iclass 15, count 0 2006.161.07:41:13.15#ibcon#about to read 6, iclass 15, count 0 2006.161.07:41:13.15#ibcon#read 6, iclass 15, count 0 2006.161.07:41:13.15#ibcon#end of sib2, iclass 15, count 0 2006.161.07:41:13.15#ibcon#*after write, iclass 15, count 0 2006.161.07:41:13.15#ibcon#*before return 0, iclass 15, count 0 2006.161.07:41:13.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:13.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:41:13.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:41:13.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:41:13.15$vc4f8/vblo=4,712.99 2006.161.07:41:13.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:41:13.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:41:13.15#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:13.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:13.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:13.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:13.15#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:41:13.15#ibcon#first serial, iclass 17, count 0 2006.161.07:41:13.15#ibcon#enter sib2, iclass 17, count 0 2006.161.07:41:13.15#ibcon#flushed, iclass 17, count 0 2006.161.07:41:13.15#ibcon#about to write, iclass 17, count 0 2006.161.07:41:13.15#ibcon#wrote, iclass 17, count 0 2006.161.07:41:13.15#ibcon#about to read 3, iclass 17, count 0 2006.161.07:41:13.17#ibcon#read 3, iclass 17, count 0 2006.161.07:41:13.17#ibcon#about to read 4, iclass 17, count 0 2006.161.07:41:13.17#ibcon#read 4, iclass 17, count 0 2006.161.07:41:13.17#ibcon#about to read 5, iclass 17, count 0 2006.161.07:41:13.17#ibcon#read 5, iclass 17, count 0 2006.161.07:41:13.17#ibcon#about to read 6, iclass 17, count 0 2006.161.07:41:13.17#ibcon#read 6, iclass 17, count 0 2006.161.07:41:13.17#ibcon#end of sib2, iclass 17, count 0 2006.161.07:41:13.17#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:41:13.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:41:13.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:41:13.17#ibcon#*before write, iclass 17, count 0 2006.161.07:41:13.17#ibcon#enter sib2, iclass 17, count 0 2006.161.07:41:13.17#ibcon#flushed, iclass 17, count 0 2006.161.07:41:13.17#ibcon#about to write, iclass 17, count 0 2006.161.07:41:13.17#ibcon#wrote, iclass 17, count 0 2006.161.07:41:13.17#ibcon#about to read 3, iclass 17, count 0 2006.161.07:41:13.21#ibcon#read 3, iclass 17, count 0 2006.161.07:41:13.21#ibcon#about to read 4, iclass 17, count 0 2006.161.07:41:13.21#ibcon#read 4, iclass 17, count 0 2006.161.07:41:13.21#ibcon#about to read 5, iclass 17, count 0 2006.161.07:41:13.21#ibcon#read 5, iclass 17, count 0 2006.161.07:41:13.21#ibcon#about to read 6, iclass 17, count 0 2006.161.07:41:13.21#ibcon#read 6, iclass 17, count 0 2006.161.07:41:13.21#ibcon#end of sib2, iclass 17, count 0 2006.161.07:41:13.21#ibcon#*after write, iclass 17, count 0 2006.161.07:41:13.21#ibcon#*before return 0, iclass 17, count 0 2006.161.07:41:13.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:13.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:41:13.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:41:13.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:41:13.21$vc4f8/vb=4,4 2006.161.07:41:13.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.07:41:13.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.07:41:13.21#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:13.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:13.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:13.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:13.27#ibcon#enter wrdev, iclass 19, count 2 2006.161.07:41:13.27#ibcon#first serial, iclass 19, count 2 2006.161.07:41:13.27#ibcon#enter sib2, iclass 19, count 2 2006.161.07:41:13.27#ibcon#flushed, iclass 19, count 2 2006.161.07:41:13.27#ibcon#about to write, iclass 19, count 2 2006.161.07:41:13.27#ibcon#wrote, iclass 19, count 2 2006.161.07:41:13.27#ibcon#about to read 3, iclass 19, count 2 2006.161.07:41:13.29#ibcon#read 3, iclass 19, count 2 2006.161.07:41:13.29#ibcon#about to read 4, iclass 19, count 2 2006.161.07:41:13.29#ibcon#read 4, iclass 19, count 2 2006.161.07:41:13.29#ibcon#about to read 5, iclass 19, count 2 2006.161.07:41:13.29#ibcon#read 5, iclass 19, count 2 2006.161.07:41:13.29#ibcon#about to read 6, iclass 19, count 2 2006.161.07:41:13.29#ibcon#read 6, iclass 19, count 2 2006.161.07:41:13.29#ibcon#end of sib2, iclass 19, count 2 2006.161.07:41:13.29#ibcon#*mode == 0, iclass 19, count 2 2006.161.07:41:13.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.07:41:13.29#ibcon#[27=AT04-04\r\n] 2006.161.07:41:13.29#ibcon#*before write, iclass 19, count 2 2006.161.07:41:13.29#ibcon#enter sib2, iclass 19, count 2 2006.161.07:41:13.29#ibcon#flushed, iclass 19, count 2 2006.161.07:41:13.29#ibcon#about to write, iclass 19, count 2 2006.161.07:41:13.29#ibcon#wrote, iclass 19, count 2 2006.161.07:41:13.29#ibcon#about to read 3, iclass 19, count 2 2006.161.07:41:13.32#ibcon#read 3, iclass 19, count 2 2006.161.07:41:13.32#ibcon#about to read 4, iclass 19, count 2 2006.161.07:41:13.32#ibcon#read 4, iclass 19, count 2 2006.161.07:41:13.32#ibcon#about to read 5, iclass 19, count 2 2006.161.07:41:13.32#ibcon#read 5, iclass 19, count 2 2006.161.07:41:13.32#ibcon#about to read 6, iclass 19, count 2 2006.161.07:41:13.32#ibcon#read 6, iclass 19, count 2 2006.161.07:41:13.32#ibcon#end of sib2, iclass 19, count 2 2006.161.07:41:13.32#ibcon#*after write, iclass 19, count 2 2006.161.07:41:13.32#ibcon#*before return 0, iclass 19, count 2 2006.161.07:41:13.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:13.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:41:13.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.07:41:13.32#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:13.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:13.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:13.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:13.44#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:41:13.44#ibcon#first serial, iclass 19, count 0 2006.161.07:41:13.44#ibcon#enter sib2, iclass 19, count 0 2006.161.07:41:13.44#ibcon#flushed, iclass 19, count 0 2006.161.07:41:13.44#ibcon#about to write, iclass 19, count 0 2006.161.07:41:13.44#ibcon#wrote, iclass 19, count 0 2006.161.07:41:13.44#ibcon#about to read 3, iclass 19, count 0 2006.161.07:41:13.46#ibcon#read 3, iclass 19, count 0 2006.161.07:41:13.46#ibcon#about to read 4, iclass 19, count 0 2006.161.07:41:13.46#ibcon#read 4, iclass 19, count 0 2006.161.07:41:13.46#ibcon#about to read 5, iclass 19, count 0 2006.161.07:41:13.46#ibcon#read 5, iclass 19, count 0 2006.161.07:41:13.46#ibcon#about to read 6, iclass 19, count 0 2006.161.07:41:13.46#ibcon#read 6, iclass 19, count 0 2006.161.07:41:13.46#ibcon#end of sib2, iclass 19, count 0 2006.161.07:41:13.46#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:41:13.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:41:13.46#ibcon#[27=USB\r\n] 2006.161.07:41:13.46#ibcon#*before write, iclass 19, count 0 2006.161.07:41:13.46#ibcon#enter sib2, iclass 19, count 0 2006.161.07:41:13.46#ibcon#flushed, iclass 19, count 0 2006.161.07:41:13.46#ibcon#about to write, iclass 19, count 0 2006.161.07:41:13.46#ibcon#wrote, iclass 19, count 0 2006.161.07:41:13.46#ibcon#about to read 3, iclass 19, count 0 2006.161.07:41:13.49#ibcon#read 3, iclass 19, count 0 2006.161.07:41:13.49#ibcon#about to read 4, iclass 19, count 0 2006.161.07:41:13.49#ibcon#read 4, iclass 19, count 0 2006.161.07:41:13.49#ibcon#about to read 5, iclass 19, count 0 2006.161.07:41:13.49#ibcon#read 5, iclass 19, count 0 2006.161.07:41:13.49#ibcon#about to read 6, iclass 19, count 0 2006.161.07:41:13.49#ibcon#read 6, iclass 19, count 0 2006.161.07:41:13.49#ibcon#end of sib2, iclass 19, count 0 2006.161.07:41:13.49#ibcon#*after write, iclass 19, count 0 2006.161.07:41:13.49#ibcon#*before return 0, iclass 19, count 0 2006.161.07:41:13.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:13.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:41:13.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:41:13.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:41:13.49$vc4f8/vblo=5,744.99 2006.161.07:41:13.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.07:41:13.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.07:41:13.49#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:13.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:13.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:13.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:13.49#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:41:13.49#ibcon#first serial, iclass 21, count 0 2006.161.07:41:13.49#ibcon#enter sib2, iclass 21, count 0 2006.161.07:41:13.49#ibcon#flushed, iclass 21, count 0 2006.161.07:41:13.49#ibcon#about to write, iclass 21, count 0 2006.161.07:41:13.49#ibcon#wrote, iclass 21, count 0 2006.161.07:41:13.49#ibcon#about to read 3, iclass 21, count 0 2006.161.07:41:13.51#ibcon#read 3, iclass 21, count 0 2006.161.07:41:13.51#ibcon#about to read 4, iclass 21, count 0 2006.161.07:41:13.51#ibcon#read 4, iclass 21, count 0 2006.161.07:41:13.51#ibcon#about to read 5, iclass 21, count 0 2006.161.07:41:13.51#ibcon#read 5, iclass 21, count 0 2006.161.07:41:13.51#ibcon#about to read 6, iclass 21, count 0 2006.161.07:41:13.51#ibcon#read 6, iclass 21, count 0 2006.161.07:41:13.51#ibcon#end of sib2, iclass 21, count 0 2006.161.07:41:13.51#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:41:13.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:41:13.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:41:13.51#ibcon#*before write, iclass 21, count 0 2006.161.07:41:13.51#ibcon#enter sib2, iclass 21, count 0 2006.161.07:41:13.51#ibcon#flushed, iclass 21, count 0 2006.161.07:41:13.51#ibcon#about to write, iclass 21, count 0 2006.161.07:41:13.51#ibcon#wrote, iclass 21, count 0 2006.161.07:41:13.51#ibcon#about to read 3, iclass 21, count 0 2006.161.07:41:13.55#ibcon#read 3, iclass 21, count 0 2006.161.07:41:13.55#ibcon#about to read 4, iclass 21, count 0 2006.161.07:41:13.55#ibcon#read 4, iclass 21, count 0 2006.161.07:41:13.55#ibcon#about to read 5, iclass 21, count 0 2006.161.07:41:13.55#ibcon#read 5, iclass 21, count 0 2006.161.07:41:13.55#ibcon#about to read 6, iclass 21, count 0 2006.161.07:41:13.55#ibcon#read 6, iclass 21, count 0 2006.161.07:41:13.55#ibcon#end of sib2, iclass 21, count 0 2006.161.07:41:13.55#ibcon#*after write, iclass 21, count 0 2006.161.07:41:13.55#ibcon#*before return 0, iclass 21, count 0 2006.161.07:41:13.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:13.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:41:13.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:41:13.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:41:13.55$vc4f8/vb=5,4 2006.161.07:41:13.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.07:41:13.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.07:41:13.55#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:13.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:13.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:13.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:13.61#ibcon#enter wrdev, iclass 23, count 2 2006.161.07:41:13.61#ibcon#first serial, iclass 23, count 2 2006.161.07:41:13.61#ibcon#enter sib2, iclass 23, count 2 2006.161.07:41:13.61#ibcon#flushed, iclass 23, count 2 2006.161.07:41:13.61#ibcon#about to write, iclass 23, count 2 2006.161.07:41:13.61#ibcon#wrote, iclass 23, count 2 2006.161.07:41:13.61#ibcon#about to read 3, iclass 23, count 2 2006.161.07:41:13.63#ibcon#read 3, iclass 23, count 2 2006.161.07:41:13.63#ibcon#about to read 4, iclass 23, count 2 2006.161.07:41:13.63#ibcon#read 4, iclass 23, count 2 2006.161.07:41:13.63#ibcon#about to read 5, iclass 23, count 2 2006.161.07:41:13.63#ibcon#read 5, iclass 23, count 2 2006.161.07:41:13.63#ibcon#about to read 6, iclass 23, count 2 2006.161.07:41:13.63#ibcon#read 6, iclass 23, count 2 2006.161.07:41:13.63#ibcon#end of sib2, iclass 23, count 2 2006.161.07:41:13.63#ibcon#*mode == 0, iclass 23, count 2 2006.161.07:41:13.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.07:41:13.63#ibcon#[27=AT05-04\r\n] 2006.161.07:41:13.63#ibcon#*before write, iclass 23, count 2 2006.161.07:41:13.63#ibcon#enter sib2, iclass 23, count 2 2006.161.07:41:13.63#ibcon#flushed, iclass 23, count 2 2006.161.07:41:13.63#ibcon#about to write, iclass 23, count 2 2006.161.07:41:13.63#ibcon#wrote, iclass 23, count 2 2006.161.07:41:13.63#ibcon#about to read 3, iclass 23, count 2 2006.161.07:41:13.66#ibcon#read 3, iclass 23, count 2 2006.161.07:41:13.66#ibcon#about to read 4, iclass 23, count 2 2006.161.07:41:13.66#ibcon#read 4, iclass 23, count 2 2006.161.07:41:13.66#ibcon#about to read 5, iclass 23, count 2 2006.161.07:41:13.66#ibcon#read 5, iclass 23, count 2 2006.161.07:41:13.66#ibcon#about to read 6, iclass 23, count 2 2006.161.07:41:13.66#ibcon#read 6, iclass 23, count 2 2006.161.07:41:13.66#ibcon#end of sib2, iclass 23, count 2 2006.161.07:41:13.66#ibcon#*after write, iclass 23, count 2 2006.161.07:41:13.66#ibcon#*before return 0, iclass 23, count 2 2006.161.07:41:13.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:13.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:41:13.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.07:41:13.66#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:13.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:13.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:13.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:13.78#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:41:13.78#ibcon#first serial, iclass 23, count 0 2006.161.07:41:13.78#ibcon#enter sib2, iclass 23, count 0 2006.161.07:41:13.78#ibcon#flushed, iclass 23, count 0 2006.161.07:41:13.78#ibcon#about to write, iclass 23, count 0 2006.161.07:41:13.78#ibcon#wrote, iclass 23, count 0 2006.161.07:41:13.78#ibcon#about to read 3, iclass 23, count 0 2006.161.07:41:13.80#ibcon#read 3, iclass 23, count 0 2006.161.07:41:13.80#ibcon#about to read 4, iclass 23, count 0 2006.161.07:41:13.80#ibcon#read 4, iclass 23, count 0 2006.161.07:41:13.80#ibcon#about to read 5, iclass 23, count 0 2006.161.07:41:13.80#ibcon#read 5, iclass 23, count 0 2006.161.07:41:13.80#ibcon#about to read 6, iclass 23, count 0 2006.161.07:41:13.80#ibcon#read 6, iclass 23, count 0 2006.161.07:41:13.80#ibcon#end of sib2, iclass 23, count 0 2006.161.07:41:13.80#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:41:13.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:41:13.80#ibcon#[27=USB\r\n] 2006.161.07:41:13.80#ibcon#*before write, iclass 23, count 0 2006.161.07:41:13.80#ibcon#enter sib2, iclass 23, count 0 2006.161.07:41:13.80#ibcon#flushed, iclass 23, count 0 2006.161.07:41:13.80#ibcon#about to write, iclass 23, count 0 2006.161.07:41:13.80#ibcon#wrote, iclass 23, count 0 2006.161.07:41:13.80#ibcon#about to read 3, iclass 23, count 0 2006.161.07:41:13.83#ibcon#read 3, iclass 23, count 0 2006.161.07:41:13.83#ibcon#about to read 4, iclass 23, count 0 2006.161.07:41:13.83#ibcon#read 4, iclass 23, count 0 2006.161.07:41:13.83#ibcon#about to read 5, iclass 23, count 0 2006.161.07:41:13.83#ibcon#read 5, iclass 23, count 0 2006.161.07:41:13.83#ibcon#about to read 6, iclass 23, count 0 2006.161.07:41:13.83#ibcon#read 6, iclass 23, count 0 2006.161.07:41:13.83#ibcon#end of sib2, iclass 23, count 0 2006.161.07:41:13.83#ibcon#*after write, iclass 23, count 0 2006.161.07:41:13.83#ibcon#*before return 0, iclass 23, count 0 2006.161.07:41:13.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:13.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:41:13.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:41:13.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:41:13.83$vc4f8/vblo=6,752.99 2006.161.07:41:13.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.07:41:13.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.07:41:13.83#ibcon#ireg 17 cls_cnt 0 2006.161.07:41:13.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:13.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:13.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:13.83#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:41:13.83#ibcon#first serial, iclass 25, count 0 2006.161.07:41:13.83#ibcon#enter sib2, iclass 25, count 0 2006.161.07:41:13.83#ibcon#flushed, iclass 25, count 0 2006.161.07:41:13.83#ibcon#about to write, iclass 25, count 0 2006.161.07:41:13.83#ibcon#wrote, iclass 25, count 0 2006.161.07:41:13.83#ibcon#about to read 3, iclass 25, count 0 2006.161.07:41:13.85#ibcon#read 3, iclass 25, count 0 2006.161.07:41:13.85#ibcon#about to read 4, iclass 25, count 0 2006.161.07:41:13.85#ibcon#read 4, iclass 25, count 0 2006.161.07:41:13.85#ibcon#about to read 5, iclass 25, count 0 2006.161.07:41:13.85#ibcon#read 5, iclass 25, count 0 2006.161.07:41:13.85#ibcon#about to read 6, iclass 25, count 0 2006.161.07:41:13.85#ibcon#read 6, iclass 25, count 0 2006.161.07:41:13.85#ibcon#end of sib2, iclass 25, count 0 2006.161.07:41:13.85#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:41:13.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:41:13.85#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:41:13.85#ibcon#*before write, iclass 25, count 0 2006.161.07:41:13.85#ibcon#enter sib2, iclass 25, count 0 2006.161.07:41:13.85#ibcon#flushed, iclass 25, count 0 2006.161.07:41:13.85#ibcon#about to write, iclass 25, count 0 2006.161.07:41:13.85#ibcon#wrote, iclass 25, count 0 2006.161.07:41:13.85#ibcon#about to read 3, iclass 25, count 0 2006.161.07:41:13.89#ibcon#read 3, iclass 25, count 0 2006.161.07:41:13.89#ibcon#about to read 4, iclass 25, count 0 2006.161.07:41:13.89#ibcon#read 4, iclass 25, count 0 2006.161.07:41:13.89#ibcon#about to read 5, iclass 25, count 0 2006.161.07:41:13.89#ibcon#read 5, iclass 25, count 0 2006.161.07:41:13.89#ibcon#about to read 6, iclass 25, count 0 2006.161.07:41:13.89#ibcon#read 6, iclass 25, count 0 2006.161.07:41:13.89#ibcon#end of sib2, iclass 25, count 0 2006.161.07:41:13.89#ibcon#*after write, iclass 25, count 0 2006.161.07:41:13.89#ibcon#*before return 0, iclass 25, count 0 2006.161.07:41:13.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:13.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:41:13.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:41:13.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:41:13.89$vc4f8/vb=6,4 2006.161.07:41:13.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.07:41:13.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.07:41:13.89#ibcon#ireg 11 cls_cnt 2 2006.161.07:41:13.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:13.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:13.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:13.96#ibcon#enter wrdev, iclass 27, count 2 2006.161.07:41:13.96#ibcon#first serial, iclass 27, count 2 2006.161.07:41:13.96#ibcon#enter sib2, iclass 27, count 2 2006.161.07:41:13.96#ibcon#flushed, iclass 27, count 2 2006.161.07:41:13.96#ibcon#about to write, iclass 27, count 2 2006.161.07:41:13.96#ibcon#wrote, iclass 27, count 2 2006.161.07:41:13.96#ibcon#about to read 3, iclass 27, count 2 2006.161.07:41:13.97#ibcon#read 3, iclass 27, count 2 2006.161.07:41:13.97#ibcon#about to read 4, iclass 27, count 2 2006.161.07:41:13.97#ibcon#read 4, iclass 27, count 2 2006.161.07:41:13.97#ibcon#about to read 5, iclass 27, count 2 2006.161.07:41:13.97#ibcon#read 5, iclass 27, count 2 2006.161.07:41:13.97#ibcon#about to read 6, iclass 27, count 2 2006.161.07:41:13.97#ibcon#read 6, iclass 27, count 2 2006.161.07:41:13.97#ibcon#end of sib2, iclass 27, count 2 2006.161.07:41:13.97#ibcon#*mode == 0, iclass 27, count 2 2006.161.07:41:13.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.07:41:13.97#ibcon#[27=AT06-04\r\n] 2006.161.07:41:13.97#ibcon#*before write, iclass 27, count 2 2006.161.07:41:13.97#ibcon#enter sib2, iclass 27, count 2 2006.161.07:41:13.97#ibcon#flushed, iclass 27, count 2 2006.161.07:41:13.97#ibcon#about to write, iclass 27, count 2 2006.161.07:41:13.97#ibcon#wrote, iclass 27, count 2 2006.161.07:41:13.97#ibcon#about to read 3, iclass 27, count 2 2006.161.07:41:14.00#ibcon#read 3, iclass 27, count 2 2006.161.07:41:14.00#ibcon#about to read 4, iclass 27, count 2 2006.161.07:41:14.00#ibcon#read 4, iclass 27, count 2 2006.161.07:41:14.00#ibcon#about to read 5, iclass 27, count 2 2006.161.07:41:14.00#ibcon#read 5, iclass 27, count 2 2006.161.07:41:14.00#ibcon#about to read 6, iclass 27, count 2 2006.161.07:41:14.00#ibcon#read 6, iclass 27, count 2 2006.161.07:41:14.00#ibcon#end of sib2, iclass 27, count 2 2006.161.07:41:14.00#ibcon#*after write, iclass 27, count 2 2006.161.07:41:14.00#ibcon#*before return 0, iclass 27, count 2 2006.161.07:41:14.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:14.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:41:14.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.07:41:14.00#ibcon#ireg 7 cls_cnt 0 2006.161.07:41:14.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:14.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:14.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:14.12#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:41:14.12#ibcon#first serial, iclass 27, count 0 2006.161.07:41:14.12#ibcon#enter sib2, iclass 27, count 0 2006.161.07:41:14.12#ibcon#flushed, iclass 27, count 0 2006.161.07:41:14.12#ibcon#about to write, iclass 27, count 0 2006.161.07:41:14.12#ibcon#wrote, iclass 27, count 0 2006.161.07:41:14.12#ibcon#about to read 3, iclass 27, count 0 2006.161.07:41:14.14#ibcon#read 3, iclass 27, count 0 2006.161.07:41:14.14#ibcon#about to read 4, iclass 27, count 0 2006.161.07:41:14.14#ibcon#read 4, iclass 27, count 0 2006.161.07:41:14.14#ibcon#about to read 5, iclass 27, count 0 2006.161.07:41:14.14#ibcon#read 5, iclass 27, count 0 2006.161.07:41:14.14#ibcon#about to read 6, iclass 27, count 0 2006.161.07:41:14.14#ibcon#read 6, iclass 27, count 0 2006.161.07:41:14.14#ibcon#end of sib2, iclass 27, count 0 2006.161.07:41:14.14#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:41:14.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:41:14.14#ibcon#[27=USB\r\n] 2006.161.07:41:14.14#ibcon#*before write, iclass 27, count 0 2006.161.07:41:14.14#ibcon#enter sib2, iclass 27, count 0 2006.161.07:41:14.14#ibcon#flushed, iclass 27, count 0 2006.161.07:41:14.14#ibcon#about to write, iclass 27, count 0 2006.161.07:41:14.14#ibcon#wrote, iclass 27, count 0 2006.161.07:41:14.14#ibcon#about to read 3, iclass 27, count 0 2006.161.07:41:14.17#ibcon#read 3, iclass 27, count 0 2006.161.07:41:14.17#ibcon#about to read 4, iclass 27, count 0 2006.161.07:41:14.17#ibcon#read 4, iclass 27, count 0 2006.161.07:41:14.17#ibcon#about to read 5, iclass 27, count 0 2006.161.07:41:14.17#ibcon#read 5, iclass 27, count 0 2006.161.07:41:14.17#ibcon#about to read 6, iclass 27, count 0 2006.161.07:41:14.17#ibcon#read 6, iclass 27, count 0 2006.161.07:41:14.17#ibcon#end of sib2, iclass 27, count 0 2006.161.07:41:14.17#ibcon#*after write, iclass 27, count 0 2006.161.07:41:14.17#ibcon#*before return 0, iclass 27, count 0 2006.161.07:41:14.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:14.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:41:14.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:41:14.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:41:14.17$vc4f8/vabw=wide 2006.161.07:41:14.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.07:41:14.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.07:41:14.17#ibcon#ireg 8 cls_cnt 0 2006.161.07:41:14.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:14.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:14.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:14.17#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:41:14.17#ibcon#first serial, iclass 29, count 0 2006.161.07:41:14.17#ibcon#enter sib2, iclass 29, count 0 2006.161.07:41:14.17#ibcon#flushed, iclass 29, count 0 2006.161.07:41:14.17#ibcon#about to write, iclass 29, count 0 2006.161.07:41:14.17#ibcon#wrote, iclass 29, count 0 2006.161.07:41:14.17#ibcon#about to read 3, iclass 29, count 0 2006.161.07:41:14.19#ibcon#read 3, iclass 29, count 0 2006.161.07:41:14.19#ibcon#about to read 4, iclass 29, count 0 2006.161.07:41:14.19#ibcon#read 4, iclass 29, count 0 2006.161.07:41:14.19#ibcon#about to read 5, iclass 29, count 0 2006.161.07:41:14.19#ibcon#read 5, iclass 29, count 0 2006.161.07:41:14.19#ibcon#about to read 6, iclass 29, count 0 2006.161.07:41:14.19#ibcon#read 6, iclass 29, count 0 2006.161.07:41:14.19#ibcon#end of sib2, iclass 29, count 0 2006.161.07:41:14.19#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:41:14.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:41:14.19#ibcon#[25=BW32\r\n] 2006.161.07:41:14.19#ibcon#*before write, iclass 29, count 0 2006.161.07:41:14.19#ibcon#enter sib2, iclass 29, count 0 2006.161.07:41:14.19#ibcon#flushed, iclass 29, count 0 2006.161.07:41:14.19#ibcon#about to write, iclass 29, count 0 2006.161.07:41:14.19#ibcon#wrote, iclass 29, count 0 2006.161.07:41:14.19#ibcon#about to read 3, iclass 29, count 0 2006.161.07:41:14.22#ibcon#read 3, iclass 29, count 0 2006.161.07:41:14.22#ibcon#about to read 4, iclass 29, count 0 2006.161.07:41:14.22#ibcon#read 4, iclass 29, count 0 2006.161.07:41:14.22#ibcon#about to read 5, iclass 29, count 0 2006.161.07:41:14.22#ibcon#read 5, iclass 29, count 0 2006.161.07:41:14.22#ibcon#about to read 6, iclass 29, count 0 2006.161.07:41:14.22#ibcon#read 6, iclass 29, count 0 2006.161.07:41:14.22#ibcon#end of sib2, iclass 29, count 0 2006.161.07:41:14.22#ibcon#*after write, iclass 29, count 0 2006.161.07:41:14.22#ibcon#*before return 0, iclass 29, count 0 2006.161.07:41:14.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:14.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:41:14.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:41:14.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:41:14.22$vc4f8/vbbw=wide 2006.161.07:41:14.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.07:41:14.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.07:41:14.22#ibcon#ireg 8 cls_cnt 0 2006.161.07:41:14.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:41:14.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:41:14.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:41:14.29#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:41:14.29#ibcon#first serial, iclass 31, count 0 2006.161.07:41:14.29#ibcon#enter sib2, iclass 31, count 0 2006.161.07:41:14.29#ibcon#flushed, iclass 31, count 0 2006.161.07:41:14.29#ibcon#about to write, iclass 31, count 0 2006.161.07:41:14.29#ibcon#wrote, iclass 31, count 0 2006.161.07:41:14.29#ibcon#about to read 3, iclass 31, count 0 2006.161.07:41:14.31#ibcon#read 3, iclass 31, count 0 2006.161.07:41:14.31#ibcon#about to read 4, iclass 31, count 0 2006.161.07:41:14.31#ibcon#read 4, iclass 31, count 0 2006.161.07:41:14.31#ibcon#about to read 5, iclass 31, count 0 2006.161.07:41:14.31#ibcon#read 5, iclass 31, count 0 2006.161.07:41:14.31#ibcon#about to read 6, iclass 31, count 0 2006.161.07:41:14.31#ibcon#read 6, iclass 31, count 0 2006.161.07:41:14.31#ibcon#end of sib2, iclass 31, count 0 2006.161.07:41:14.31#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:41:14.31#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:41:14.31#ibcon#[27=BW32\r\n] 2006.161.07:41:14.31#ibcon#*before write, iclass 31, count 0 2006.161.07:41:14.31#ibcon#enter sib2, iclass 31, count 0 2006.161.07:41:14.31#ibcon#flushed, iclass 31, count 0 2006.161.07:41:14.31#ibcon#about to write, iclass 31, count 0 2006.161.07:41:14.31#ibcon#wrote, iclass 31, count 0 2006.161.07:41:14.31#ibcon#about to read 3, iclass 31, count 0 2006.161.07:41:14.34#ibcon#read 3, iclass 31, count 0 2006.161.07:41:14.34#ibcon#about to read 4, iclass 31, count 0 2006.161.07:41:14.34#ibcon#read 4, iclass 31, count 0 2006.161.07:41:14.34#ibcon#about to read 5, iclass 31, count 0 2006.161.07:41:14.34#ibcon#read 5, iclass 31, count 0 2006.161.07:41:14.34#ibcon#about to read 6, iclass 31, count 0 2006.161.07:41:14.34#ibcon#read 6, iclass 31, count 0 2006.161.07:41:14.34#ibcon#end of sib2, iclass 31, count 0 2006.161.07:41:14.34#ibcon#*after write, iclass 31, count 0 2006.161.07:41:14.34#ibcon#*before return 0, iclass 31, count 0 2006.161.07:41:14.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:41:14.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:41:14.34#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:41:14.34#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:41:14.34$4f8m12a/ifd4f 2006.161.07:41:14.34$ifd4f/lo= 2006.161.07:41:14.34$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:41:14.34$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:41:14.34$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:41:14.34$ifd4f/patch= 2006.161.07:41:14.34$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:41:14.34$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:41:14.34$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:41:14.34$4f8m12a/"form=m,16.000,1:2 2006.161.07:41:14.34$4f8m12a/"tpicd 2006.161.07:41:14.34$4f8m12a/echo=off 2006.161.07:41:14.34$4f8m12a/xlog=off 2006.161.07:41:14.34:!2006.161.07:41:40 2006.161.07:41:24.14#trakl#Source acquired 2006.161.07:41:25.14#flagr#flagr/antenna,acquired 2006.161.07:41:40.00:preob 2006.161.07:41:41.14/onsource/TRACKING 2006.161.07:41:41.14:!2006.161.07:41:50 2006.161.07:41:50.00:data_valid=on 2006.161.07:41:50.00:midob 2006.161.07:41:50.14/onsource/TRACKING 2006.161.07:41:50.14/wx/24.13,1002.0,84 2006.161.07:41:50.34/cable/+6.4996E-03 2006.161.07:41:51.43/va/01,08,usb,yes,29,30 2006.161.07:41:51.43/va/02,07,usb,yes,29,30 2006.161.07:41:51.43/va/03,06,usb,yes,30,30 2006.161.07:41:51.43/va/04,07,usb,yes,29,32 2006.161.07:41:51.43/va/05,07,usb,yes,29,31 2006.161.07:41:51.43/va/06,06,usb,yes,28,28 2006.161.07:41:51.43/va/07,06,usb,yes,29,29 2006.161.07:41:51.43/va/08,07,usb,yes,27,27 2006.161.07:41:51.66/valo/01,532.99,yes,locked 2006.161.07:41:51.66/valo/02,572.99,yes,locked 2006.161.07:41:51.66/valo/03,672.99,yes,locked 2006.161.07:41:51.66/valo/04,832.99,yes,locked 2006.161.07:41:51.66/valo/05,652.99,yes,locked 2006.161.07:41:51.66/valo/06,772.99,yes,locked 2006.161.07:41:51.66/valo/07,832.99,yes,locked 2006.161.07:41:51.66/valo/08,852.99,yes,locked 2006.161.07:41:52.75/vb/01,04,usb,yes,29,28 2006.161.07:41:52.75/vb/02,04,usb,yes,31,32 2006.161.07:41:52.75/vb/03,04,usb,yes,27,31 2006.161.07:41:52.75/vb/04,04,usb,yes,28,28 2006.161.07:41:52.75/vb/05,04,usb,yes,27,30 2006.161.07:41:52.75/vb/06,04,usb,yes,27,30 2006.161.07:41:52.75/vb/07,04,usb,yes,29,29 2006.161.07:41:52.75/vb/08,04,usb,yes,27,30 2006.161.07:41:52.98/vblo/01,632.99,yes,locked 2006.161.07:41:52.98/vblo/02,640.99,yes,locked 2006.161.07:41:52.98/vblo/03,656.99,yes,locked 2006.161.07:41:52.98/vblo/04,712.99,yes,locked 2006.161.07:41:52.98/vblo/05,744.99,yes,locked 2006.161.07:41:52.98/vblo/06,752.99,yes,locked 2006.161.07:41:52.98/vblo/07,734.99,yes,locked 2006.161.07:41:52.98/vblo/08,744.99,yes,locked 2006.161.07:41:53.13/vabw/8 2006.161.07:41:53.28/vbbw/8 2006.161.07:41:53.39/xfe/off,on,15.2 2006.161.07:41:53.78/ifatt/23,28,28,28 2006.161.07:41:54.08/fmout-gps/S +4.47E-07 2006.161.07:41:54.16:!2006.161.07:43:00 2006.161.07:43:00.00:data_valid=off 2006.161.07:43:00.00:postob 2006.161.07:43:00.20/cable/+6.4982E-03 2006.161.07:43:00.20/wx/24.12,1002.0,85 2006.161.07:43:01.08/fmout-gps/S +4.47E-07 2006.161.07:43:01.08:scan_name=161-0743,k06161,60 2006.161.07:43:01.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.161.07:43:02.14#flagr#flagr/antenna,new-source 2006.161.07:43:02.14:checkk5 2006.161.07:43:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:43:03.15/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:43:03.56/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:43:03.98/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:43:04.42/chk_obsdata//k5ts1/T1610741??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.161.07:43:04.81/chk_obsdata//k5ts2/T1610741??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.161.07:43:05.20/chk_obsdata//k5ts3/T1610741??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.161.07:43:05.64/chk_obsdata//k5ts4/T1610741??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.161.07:43:06.56/k5log//k5ts1_log_newline 2006.161.07:43:07.35/k5log//k5ts2_log_newline 2006.161.07:43:08.62/k5log//k5ts3_log_newline 2006.161.07:43:09.44/k5log//k5ts4_log_newline 2006.161.07:43:09.46/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:43:09.46:4f8m12a=1 2006.161.07:43:09.46$4f8m12a/echo=on 2006.161.07:43:09.46$4f8m12a/pcalon 2006.161.07:43:09.46$pcalon/"no phase cal control is implemented here 2006.161.07:43:09.46$4f8m12a/"tpicd=stop 2006.161.07:43:09.46$4f8m12a/vc4f8 2006.161.07:43:09.46$vc4f8/valo=1,532.99 2006.161.07:43:09.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:43:09.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:43:09.47#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:09.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:09.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:09.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:09.47#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:43:09.47#ibcon#first serial, iclass 10, count 0 2006.161.07:43:09.47#ibcon#enter sib2, iclass 10, count 0 2006.161.07:43:09.47#ibcon#flushed, iclass 10, count 0 2006.161.07:43:09.47#ibcon#about to write, iclass 10, count 0 2006.161.07:43:09.47#ibcon#wrote, iclass 10, count 0 2006.161.07:43:09.47#ibcon#about to read 3, iclass 10, count 0 2006.161.07:43:09.51#ibcon#read 3, iclass 10, count 0 2006.161.07:43:09.51#ibcon#about to read 4, iclass 10, count 0 2006.161.07:43:09.51#ibcon#read 4, iclass 10, count 0 2006.161.07:43:09.51#ibcon#about to read 5, iclass 10, count 0 2006.161.07:43:09.51#ibcon#read 5, iclass 10, count 0 2006.161.07:43:09.51#ibcon#about to read 6, iclass 10, count 0 2006.161.07:43:09.51#ibcon#read 6, iclass 10, count 0 2006.161.07:43:09.51#ibcon#end of sib2, iclass 10, count 0 2006.161.07:43:09.51#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:43:09.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:43:09.51#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:43:09.51#ibcon#*before write, iclass 10, count 0 2006.161.07:43:09.51#ibcon#enter sib2, iclass 10, count 0 2006.161.07:43:09.51#ibcon#flushed, iclass 10, count 0 2006.161.07:43:09.51#ibcon#about to write, iclass 10, count 0 2006.161.07:43:09.51#ibcon#wrote, iclass 10, count 0 2006.161.07:43:09.51#ibcon#about to read 3, iclass 10, count 0 2006.161.07:43:09.55#ibcon#read 3, iclass 10, count 0 2006.161.07:43:09.55#ibcon#about to read 4, iclass 10, count 0 2006.161.07:43:09.55#ibcon#read 4, iclass 10, count 0 2006.161.07:43:09.55#ibcon#about to read 5, iclass 10, count 0 2006.161.07:43:09.55#ibcon#read 5, iclass 10, count 0 2006.161.07:43:09.55#ibcon#about to read 6, iclass 10, count 0 2006.161.07:43:09.55#ibcon#read 6, iclass 10, count 0 2006.161.07:43:09.55#ibcon#end of sib2, iclass 10, count 0 2006.161.07:43:09.55#ibcon#*after write, iclass 10, count 0 2006.161.07:43:09.55#ibcon#*before return 0, iclass 10, count 0 2006.161.07:43:09.55#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:09.55#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:09.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:43:09.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:43:09.55$vc4f8/va=1,8 2006.161.07:43:09.55#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.07:43:09.55#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.07:43:09.55#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:09.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:09.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:09.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:09.55#ibcon#enter wrdev, iclass 12, count 2 2006.161.07:43:09.55#ibcon#first serial, iclass 12, count 2 2006.161.07:43:09.55#ibcon#enter sib2, iclass 12, count 2 2006.161.07:43:09.55#ibcon#flushed, iclass 12, count 2 2006.161.07:43:09.55#ibcon#about to write, iclass 12, count 2 2006.161.07:43:09.55#ibcon#wrote, iclass 12, count 2 2006.161.07:43:09.55#ibcon#about to read 3, iclass 12, count 2 2006.161.07:43:09.57#ibcon#read 3, iclass 12, count 2 2006.161.07:43:09.57#ibcon#about to read 4, iclass 12, count 2 2006.161.07:43:09.57#ibcon#read 4, iclass 12, count 2 2006.161.07:43:09.57#ibcon#about to read 5, iclass 12, count 2 2006.161.07:43:09.57#ibcon#read 5, iclass 12, count 2 2006.161.07:43:09.57#ibcon#about to read 6, iclass 12, count 2 2006.161.07:43:09.57#ibcon#read 6, iclass 12, count 2 2006.161.07:43:09.57#ibcon#end of sib2, iclass 12, count 2 2006.161.07:43:09.57#ibcon#*mode == 0, iclass 12, count 2 2006.161.07:43:09.57#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.07:43:09.57#ibcon#[25=AT01-08\r\n] 2006.161.07:43:09.57#ibcon#*before write, iclass 12, count 2 2006.161.07:43:09.57#ibcon#enter sib2, iclass 12, count 2 2006.161.07:43:09.57#ibcon#flushed, iclass 12, count 2 2006.161.07:43:09.57#ibcon#about to write, iclass 12, count 2 2006.161.07:43:09.57#ibcon#wrote, iclass 12, count 2 2006.161.07:43:09.57#ibcon#about to read 3, iclass 12, count 2 2006.161.07:43:09.60#ibcon#read 3, iclass 12, count 2 2006.161.07:43:09.60#ibcon#about to read 4, iclass 12, count 2 2006.161.07:43:09.60#ibcon#read 4, iclass 12, count 2 2006.161.07:43:09.60#ibcon#about to read 5, iclass 12, count 2 2006.161.07:43:09.60#ibcon#read 5, iclass 12, count 2 2006.161.07:43:09.60#ibcon#about to read 6, iclass 12, count 2 2006.161.07:43:09.60#ibcon#read 6, iclass 12, count 2 2006.161.07:43:09.60#ibcon#end of sib2, iclass 12, count 2 2006.161.07:43:09.60#ibcon#*after write, iclass 12, count 2 2006.161.07:43:09.60#ibcon#*before return 0, iclass 12, count 2 2006.161.07:43:09.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:09.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:09.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.07:43:09.60#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:09.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:09.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:09.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:09.72#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:43:09.72#ibcon#first serial, iclass 12, count 0 2006.161.07:43:09.72#ibcon#enter sib2, iclass 12, count 0 2006.161.07:43:09.72#ibcon#flushed, iclass 12, count 0 2006.161.07:43:09.72#ibcon#about to write, iclass 12, count 0 2006.161.07:43:09.72#ibcon#wrote, iclass 12, count 0 2006.161.07:43:09.72#ibcon#about to read 3, iclass 12, count 0 2006.161.07:43:09.74#ibcon#read 3, iclass 12, count 0 2006.161.07:43:09.74#ibcon#about to read 4, iclass 12, count 0 2006.161.07:43:09.74#ibcon#read 4, iclass 12, count 0 2006.161.07:43:09.74#ibcon#about to read 5, iclass 12, count 0 2006.161.07:43:09.74#ibcon#read 5, iclass 12, count 0 2006.161.07:43:09.74#ibcon#about to read 6, iclass 12, count 0 2006.161.07:43:09.74#ibcon#read 6, iclass 12, count 0 2006.161.07:43:09.74#ibcon#end of sib2, iclass 12, count 0 2006.161.07:43:09.74#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:43:09.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:43:09.74#ibcon#[25=USB\r\n] 2006.161.07:43:09.74#ibcon#*before write, iclass 12, count 0 2006.161.07:43:09.74#ibcon#enter sib2, iclass 12, count 0 2006.161.07:43:09.74#ibcon#flushed, iclass 12, count 0 2006.161.07:43:09.74#ibcon#about to write, iclass 12, count 0 2006.161.07:43:09.74#ibcon#wrote, iclass 12, count 0 2006.161.07:43:09.74#ibcon#about to read 3, iclass 12, count 0 2006.161.07:43:09.77#ibcon#read 3, iclass 12, count 0 2006.161.07:43:09.77#ibcon#about to read 4, iclass 12, count 0 2006.161.07:43:09.77#ibcon#read 4, iclass 12, count 0 2006.161.07:43:09.77#ibcon#about to read 5, iclass 12, count 0 2006.161.07:43:09.77#ibcon#read 5, iclass 12, count 0 2006.161.07:43:09.77#ibcon#about to read 6, iclass 12, count 0 2006.161.07:43:09.77#ibcon#read 6, iclass 12, count 0 2006.161.07:43:09.77#ibcon#end of sib2, iclass 12, count 0 2006.161.07:43:09.77#ibcon#*after write, iclass 12, count 0 2006.161.07:43:09.77#ibcon#*before return 0, iclass 12, count 0 2006.161.07:43:09.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:09.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:09.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:43:09.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:43:09.77$vc4f8/valo=2,572.99 2006.161.07:43:09.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.07:43:09.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.07:43:09.77#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:09.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:09.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:09.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:09.77#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:43:09.77#ibcon#first serial, iclass 14, count 0 2006.161.07:43:09.77#ibcon#enter sib2, iclass 14, count 0 2006.161.07:43:09.77#ibcon#flushed, iclass 14, count 0 2006.161.07:43:09.77#ibcon#about to write, iclass 14, count 0 2006.161.07:43:09.77#ibcon#wrote, iclass 14, count 0 2006.161.07:43:09.77#ibcon#about to read 3, iclass 14, count 0 2006.161.07:43:09.79#ibcon#read 3, iclass 14, count 0 2006.161.07:43:09.79#ibcon#about to read 4, iclass 14, count 0 2006.161.07:43:09.79#ibcon#read 4, iclass 14, count 0 2006.161.07:43:09.79#ibcon#about to read 5, iclass 14, count 0 2006.161.07:43:09.79#ibcon#read 5, iclass 14, count 0 2006.161.07:43:09.79#ibcon#about to read 6, iclass 14, count 0 2006.161.07:43:09.79#ibcon#read 6, iclass 14, count 0 2006.161.07:43:09.79#ibcon#end of sib2, iclass 14, count 0 2006.161.07:43:09.79#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:43:09.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:43:09.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:43:09.79#ibcon#*before write, iclass 14, count 0 2006.161.07:43:09.79#ibcon#enter sib2, iclass 14, count 0 2006.161.07:43:09.79#ibcon#flushed, iclass 14, count 0 2006.161.07:43:09.79#ibcon#about to write, iclass 14, count 0 2006.161.07:43:09.79#ibcon#wrote, iclass 14, count 0 2006.161.07:43:09.79#ibcon#about to read 3, iclass 14, count 0 2006.161.07:43:09.83#ibcon#read 3, iclass 14, count 0 2006.161.07:43:09.83#ibcon#about to read 4, iclass 14, count 0 2006.161.07:43:09.83#ibcon#read 4, iclass 14, count 0 2006.161.07:43:09.83#ibcon#about to read 5, iclass 14, count 0 2006.161.07:43:09.83#ibcon#read 5, iclass 14, count 0 2006.161.07:43:09.83#ibcon#about to read 6, iclass 14, count 0 2006.161.07:43:09.83#ibcon#read 6, iclass 14, count 0 2006.161.07:43:09.83#ibcon#end of sib2, iclass 14, count 0 2006.161.07:43:09.83#ibcon#*after write, iclass 14, count 0 2006.161.07:43:09.83#ibcon#*before return 0, iclass 14, count 0 2006.161.07:43:09.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:09.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:09.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:43:09.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:43:09.83$vc4f8/va=2,7 2006.161.07:43:09.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.07:43:09.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.07:43:09.83#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:09.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:09.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:09.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:09.89#ibcon#enter wrdev, iclass 16, count 2 2006.161.07:43:09.89#ibcon#first serial, iclass 16, count 2 2006.161.07:43:09.89#ibcon#enter sib2, iclass 16, count 2 2006.161.07:43:09.89#ibcon#flushed, iclass 16, count 2 2006.161.07:43:09.89#ibcon#about to write, iclass 16, count 2 2006.161.07:43:09.89#ibcon#wrote, iclass 16, count 2 2006.161.07:43:09.89#ibcon#about to read 3, iclass 16, count 2 2006.161.07:43:09.92#ibcon#read 3, iclass 16, count 2 2006.161.07:43:09.92#ibcon#about to read 4, iclass 16, count 2 2006.161.07:43:09.92#ibcon#read 4, iclass 16, count 2 2006.161.07:43:09.92#ibcon#about to read 5, iclass 16, count 2 2006.161.07:43:09.92#ibcon#read 5, iclass 16, count 2 2006.161.07:43:09.92#ibcon#about to read 6, iclass 16, count 2 2006.161.07:43:09.92#ibcon#read 6, iclass 16, count 2 2006.161.07:43:09.92#ibcon#end of sib2, iclass 16, count 2 2006.161.07:43:09.92#ibcon#*mode == 0, iclass 16, count 2 2006.161.07:43:09.92#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.07:43:09.92#ibcon#[25=AT02-07\r\n] 2006.161.07:43:09.92#ibcon#*before write, iclass 16, count 2 2006.161.07:43:09.92#ibcon#enter sib2, iclass 16, count 2 2006.161.07:43:09.92#ibcon#flushed, iclass 16, count 2 2006.161.07:43:09.92#ibcon#about to write, iclass 16, count 2 2006.161.07:43:09.92#ibcon#wrote, iclass 16, count 2 2006.161.07:43:09.92#ibcon#about to read 3, iclass 16, count 2 2006.161.07:43:09.95#ibcon#read 3, iclass 16, count 2 2006.161.07:43:09.95#ibcon#about to read 4, iclass 16, count 2 2006.161.07:43:09.95#ibcon#read 4, iclass 16, count 2 2006.161.07:43:09.95#ibcon#about to read 5, iclass 16, count 2 2006.161.07:43:09.95#ibcon#read 5, iclass 16, count 2 2006.161.07:43:09.95#ibcon#about to read 6, iclass 16, count 2 2006.161.07:43:09.95#ibcon#read 6, iclass 16, count 2 2006.161.07:43:09.95#ibcon#end of sib2, iclass 16, count 2 2006.161.07:43:09.95#ibcon#*after write, iclass 16, count 2 2006.161.07:43:09.95#ibcon#*before return 0, iclass 16, count 2 2006.161.07:43:09.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:09.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:09.95#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.07:43:09.95#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:09.95#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:10.07#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:10.07#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:10.07#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:43:10.07#ibcon#first serial, iclass 16, count 0 2006.161.07:43:10.07#ibcon#enter sib2, iclass 16, count 0 2006.161.07:43:10.07#ibcon#flushed, iclass 16, count 0 2006.161.07:43:10.07#ibcon#about to write, iclass 16, count 0 2006.161.07:43:10.07#ibcon#wrote, iclass 16, count 0 2006.161.07:43:10.07#ibcon#about to read 3, iclass 16, count 0 2006.161.07:43:10.11#ibcon#read 3, iclass 16, count 0 2006.161.07:43:10.11#ibcon#about to read 4, iclass 16, count 0 2006.161.07:43:10.11#ibcon#read 4, iclass 16, count 0 2006.161.07:43:10.11#ibcon#about to read 5, iclass 16, count 0 2006.161.07:43:10.11#ibcon#read 5, iclass 16, count 0 2006.161.07:43:10.11#ibcon#about to read 6, iclass 16, count 0 2006.161.07:43:10.11#ibcon#read 6, iclass 16, count 0 2006.161.07:43:10.11#ibcon#end of sib2, iclass 16, count 0 2006.161.07:43:10.11#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:43:10.11#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:43:10.11#ibcon#[25=USB\r\n] 2006.161.07:43:10.11#ibcon#*before write, iclass 16, count 0 2006.161.07:43:10.11#ibcon#enter sib2, iclass 16, count 0 2006.161.07:43:10.11#ibcon#flushed, iclass 16, count 0 2006.161.07:43:10.11#ibcon#about to write, iclass 16, count 0 2006.161.07:43:10.11#ibcon#wrote, iclass 16, count 0 2006.161.07:43:10.11#ibcon#about to read 3, iclass 16, count 0 2006.161.07:43:10.14#ibcon#read 3, iclass 16, count 0 2006.161.07:43:10.14#ibcon#about to read 4, iclass 16, count 0 2006.161.07:43:10.14#ibcon#read 4, iclass 16, count 0 2006.161.07:43:10.14#ibcon#about to read 5, iclass 16, count 0 2006.161.07:43:10.14#ibcon#read 5, iclass 16, count 0 2006.161.07:43:10.14#ibcon#about to read 6, iclass 16, count 0 2006.161.07:43:10.14#ibcon#read 6, iclass 16, count 0 2006.161.07:43:10.14#ibcon#end of sib2, iclass 16, count 0 2006.161.07:43:10.14#ibcon#*after write, iclass 16, count 0 2006.161.07:43:10.14#ibcon#*before return 0, iclass 16, count 0 2006.161.07:43:10.14#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:10.14#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:10.14#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:43:10.14#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:43:10.14$vc4f8/valo=3,672.99 2006.161.07:43:10.14#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.07:43:10.14#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.07:43:10.14#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:10.14#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:10.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:10.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:10.14#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:43:10.14#ibcon#first serial, iclass 18, count 0 2006.161.07:43:10.14#ibcon#enter sib2, iclass 18, count 0 2006.161.07:43:10.14#ibcon#flushed, iclass 18, count 0 2006.161.07:43:10.14#ibcon#about to write, iclass 18, count 0 2006.161.07:43:10.14#ibcon#wrote, iclass 18, count 0 2006.161.07:43:10.14#ibcon#about to read 3, iclass 18, count 0 2006.161.07:43:10.16#ibcon#read 3, iclass 18, count 0 2006.161.07:43:10.16#ibcon#about to read 4, iclass 18, count 0 2006.161.07:43:10.16#ibcon#read 4, iclass 18, count 0 2006.161.07:43:10.16#ibcon#about to read 5, iclass 18, count 0 2006.161.07:43:10.16#ibcon#read 5, iclass 18, count 0 2006.161.07:43:10.16#ibcon#about to read 6, iclass 18, count 0 2006.161.07:43:10.16#ibcon#read 6, iclass 18, count 0 2006.161.07:43:10.16#ibcon#end of sib2, iclass 18, count 0 2006.161.07:43:10.16#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:43:10.16#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:43:10.16#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:43:10.16#ibcon#*before write, iclass 18, count 0 2006.161.07:43:10.16#ibcon#enter sib2, iclass 18, count 0 2006.161.07:43:10.16#ibcon#flushed, iclass 18, count 0 2006.161.07:43:10.16#ibcon#about to write, iclass 18, count 0 2006.161.07:43:10.16#ibcon#wrote, iclass 18, count 0 2006.161.07:43:10.16#ibcon#about to read 3, iclass 18, count 0 2006.161.07:43:10.20#ibcon#read 3, iclass 18, count 0 2006.161.07:43:10.20#ibcon#about to read 4, iclass 18, count 0 2006.161.07:43:10.20#ibcon#read 4, iclass 18, count 0 2006.161.07:43:10.20#ibcon#about to read 5, iclass 18, count 0 2006.161.07:43:10.20#ibcon#read 5, iclass 18, count 0 2006.161.07:43:10.20#ibcon#about to read 6, iclass 18, count 0 2006.161.07:43:10.20#ibcon#read 6, iclass 18, count 0 2006.161.07:43:10.20#ibcon#end of sib2, iclass 18, count 0 2006.161.07:43:10.20#ibcon#*after write, iclass 18, count 0 2006.161.07:43:10.20#ibcon#*before return 0, iclass 18, count 0 2006.161.07:43:10.20#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:10.20#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:10.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:43:10.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:43:10.20$vc4f8/va=3,6 2006.161.07:43:10.20#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.07:43:10.20#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.07:43:10.20#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:10.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:10.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:10.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:10.26#ibcon#enter wrdev, iclass 20, count 2 2006.161.07:43:10.26#ibcon#first serial, iclass 20, count 2 2006.161.07:43:10.26#ibcon#enter sib2, iclass 20, count 2 2006.161.07:43:10.26#ibcon#flushed, iclass 20, count 2 2006.161.07:43:10.26#ibcon#about to write, iclass 20, count 2 2006.161.07:43:10.26#ibcon#wrote, iclass 20, count 2 2006.161.07:43:10.26#ibcon#about to read 3, iclass 20, count 2 2006.161.07:43:10.28#ibcon#read 3, iclass 20, count 2 2006.161.07:43:10.28#ibcon#about to read 4, iclass 20, count 2 2006.161.07:43:10.28#ibcon#read 4, iclass 20, count 2 2006.161.07:43:10.28#ibcon#about to read 5, iclass 20, count 2 2006.161.07:43:10.28#ibcon#read 5, iclass 20, count 2 2006.161.07:43:10.28#ibcon#about to read 6, iclass 20, count 2 2006.161.07:43:10.28#ibcon#read 6, iclass 20, count 2 2006.161.07:43:10.28#ibcon#end of sib2, iclass 20, count 2 2006.161.07:43:10.28#ibcon#*mode == 0, iclass 20, count 2 2006.161.07:43:10.28#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.07:43:10.28#ibcon#[25=AT03-06\r\n] 2006.161.07:43:10.28#ibcon#*before write, iclass 20, count 2 2006.161.07:43:10.28#ibcon#enter sib2, iclass 20, count 2 2006.161.07:43:10.28#ibcon#flushed, iclass 20, count 2 2006.161.07:43:10.28#ibcon#about to write, iclass 20, count 2 2006.161.07:43:10.28#ibcon#wrote, iclass 20, count 2 2006.161.07:43:10.28#ibcon#about to read 3, iclass 20, count 2 2006.161.07:43:10.31#ibcon#read 3, iclass 20, count 2 2006.161.07:43:10.31#ibcon#about to read 4, iclass 20, count 2 2006.161.07:43:10.31#ibcon#read 4, iclass 20, count 2 2006.161.07:43:10.31#ibcon#about to read 5, iclass 20, count 2 2006.161.07:43:10.31#ibcon#read 5, iclass 20, count 2 2006.161.07:43:10.31#ibcon#about to read 6, iclass 20, count 2 2006.161.07:43:10.31#ibcon#read 6, iclass 20, count 2 2006.161.07:43:10.31#ibcon#end of sib2, iclass 20, count 2 2006.161.07:43:10.31#ibcon#*after write, iclass 20, count 2 2006.161.07:43:10.31#ibcon#*before return 0, iclass 20, count 2 2006.161.07:43:10.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:10.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:10.31#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.07:43:10.31#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:10.31#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:10.43#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:10.43#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:10.43#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:43:10.43#ibcon#first serial, iclass 20, count 0 2006.161.07:43:10.43#ibcon#enter sib2, iclass 20, count 0 2006.161.07:43:10.43#ibcon#flushed, iclass 20, count 0 2006.161.07:43:10.43#ibcon#about to write, iclass 20, count 0 2006.161.07:43:10.43#ibcon#wrote, iclass 20, count 0 2006.161.07:43:10.43#ibcon#about to read 3, iclass 20, count 0 2006.161.07:43:10.45#ibcon#read 3, iclass 20, count 0 2006.161.07:43:10.45#ibcon#about to read 4, iclass 20, count 0 2006.161.07:43:10.45#ibcon#read 4, iclass 20, count 0 2006.161.07:43:10.45#ibcon#about to read 5, iclass 20, count 0 2006.161.07:43:10.45#ibcon#read 5, iclass 20, count 0 2006.161.07:43:10.45#ibcon#about to read 6, iclass 20, count 0 2006.161.07:43:10.45#ibcon#read 6, iclass 20, count 0 2006.161.07:43:10.45#ibcon#end of sib2, iclass 20, count 0 2006.161.07:43:10.45#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:43:10.45#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:43:10.45#ibcon#[25=USB\r\n] 2006.161.07:43:10.45#ibcon#*before write, iclass 20, count 0 2006.161.07:43:10.45#ibcon#enter sib2, iclass 20, count 0 2006.161.07:43:10.45#ibcon#flushed, iclass 20, count 0 2006.161.07:43:10.45#ibcon#about to write, iclass 20, count 0 2006.161.07:43:10.45#ibcon#wrote, iclass 20, count 0 2006.161.07:43:10.45#ibcon#about to read 3, iclass 20, count 0 2006.161.07:43:10.48#ibcon#read 3, iclass 20, count 0 2006.161.07:43:10.48#ibcon#about to read 4, iclass 20, count 0 2006.161.07:43:10.48#ibcon#read 4, iclass 20, count 0 2006.161.07:43:10.48#ibcon#about to read 5, iclass 20, count 0 2006.161.07:43:10.48#ibcon#read 5, iclass 20, count 0 2006.161.07:43:10.48#ibcon#about to read 6, iclass 20, count 0 2006.161.07:43:10.48#ibcon#read 6, iclass 20, count 0 2006.161.07:43:10.48#ibcon#end of sib2, iclass 20, count 0 2006.161.07:43:10.48#ibcon#*after write, iclass 20, count 0 2006.161.07:43:10.48#ibcon#*before return 0, iclass 20, count 0 2006.161.07:43:10.48#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:10.48#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:10.48#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:43:10.48#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:43:10.48$vc4f8/valo=4,832.99 2006.161.07:43:10.48#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.07:43:10.48#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.07:43:10.48#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:10.48#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:10.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:10.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:10.48#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:43:10.48#ibcon#first serial, iclass 22, count 0 2006.161.07:43:10.48#ibcon#enter sib2, iclass 22, count 0 2006.161.07:43:10.48#ibcon#flushed, iclass 22, count 0 2006.161.07:43:10.48#ibcon#about to write, iclass 22, count 0 2006.161.07:43:10.48#ibcon#wrote, iclass 22, count 0 2006.161.07:43:10.48#ibcon#about to read 3, iclass 22, count 0 2006.161.07:43:10.50#ibcon#read 3, iclass 22, count 0 2006.161.07:43:10.50#ibcon#about to read 4, iclass 22, count 0 2006.161.07:43:10.50#ibcon#read 4, iclass 22, count 0 2006.161.07:43:10.50#ibcon#about to read 5, iclass 22, count 0 2006.161.07:43:10.50#ibcon#read 5, iclass 22, count 0 2006.161.07:43:10.50#ibcon#about to read 6, iclass 22, count 0 2006.161.07:43:10.50#ibcon#read 6, iclass 22, count 0 2006.161.07:43:10.50#ibcon#end of sib2, iclass 22, count 0 2006.161.07:43:10.50#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:43:10.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:43:10.50#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:43:10.50#ibcon#*before write, iclass 22, count 0 2006.161.07:43:10.50#ibcon#enter sib2, iclass 22, count 0 2006.161.07:43:10.50#ibcon#flushed, iclass 22, count 0 2006.161.07:43:10.50#ibcon#about to write, iclass 22, count 0 2006.161.07:43:10.50#ibcon#wrote, iclass 22, count 0 2006.161.07:43:10.50#ibcon#about to read 3, iclass 22, count 0 2006.161.07:43:10.54#ibcon#read 3, iclass 22, count 0 2006.161.07:43:10.54#ibcon#about to read 4, iclass 22, count 0 2006.161.07:43:10.54#ibcon#read 4, iclass 22, count 0 2006.161.07:43:10.54#ibcon#about to read 5, iclass 22, count 0 2006.161.07:43:10.54#ibcon#read 5, iclass 22, count 0 2006.161.07:43:10.54#ibcon#about to read 6, iclass 22, count 0 2006.161.07:43:10.54#ibcon#read 6, iclass 22, count 0 2006.161.07:43:10.54#ibcon#end of sib2, iclass 22, count 0 2006.161.07:43:10.54#ibcon#*after write, iclass 22, count 0 2006.161.07:43:10.54#ibcon#*before return 0, iclass 22, count 0 2006.161.07:43:10.54#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:10.54#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:10.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:43:10.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:43:10.54$vc4f8/va=4,7 2006.161.07:43:10.54#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.07:43:10.54#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.07:43:10.54#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:10.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:10.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:10.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:10.60#ibcon#enter wrdev, iclass 24, count 2 2006.161.07:43:10.60#ibcon#first serial, iclass 24, count 2 2006.161.07:43:10.60#ibcon#enter sib2, iclass 24, count 2 2006.161.07:43:10.60#ibcon#flushed, iclass 24, count 2 2006.161.07:43:10.60#ibcon#about to write, iclass 24, count 2 2006.161.07:43:10.60#ibcon#wrote, iclass 24, count 2 2006.161.07:43:10.60#ibcon#about to read 3, iclass 24, count 2 2006.161.07:43:10.62#ibcon#read 3, iclass 24, count 2 2006.161.07:43:10.62#ibcon#about to read 4, iclass 24, count 2 2006.161.07:43:10.62#ibcon#read 4, iclass 24, count 2 2006.161.07:43:10.62#ibcon#about to read 5, iclass 24, count 2 2006.161.07:43:10.62#ibcon#read 5, iclass 24, count 2 2006.161.07:43:10.62#ibcon#about to read 6, iclass 24, count 2 2006.161.07:43:10.62#ibcon#read 6, iclass 24, count 2 2006.161.07:43:10.62#ibcon#end of sib2, iclass 24, count 2 2006.161.07:43:10.62#ibcon#*mode == 0, iclass 24, count 2 2006.161.07:43:10.62#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.07:43:10.62#ibcon#[25=AT04-07\r\n] 2006.161.07:43:10.62#ibcon#*before write, iclass 24, count 2 2006.161.07:43:10.62#ibcon#enter sib2, iclass 24, count 2 2006.161.07:43:10.62#ibcon#flushed, iclass 24, count 2 2006.161.07:43:10.62#ibcon#about to write, iclass 24, count 2 2006.161.07:43:10.62#ibcon#wrote, iclass 24, count 2 2006.161.07:43:10.62#ibcon#about to read 3, iclass 24, count 2 2006.161.07:43:10.65#ibcon#read 3, iclass 24, count 2 2006.161.07:43:10.65#ibcon#about to read 4, iclass 24, count 2 2006.161.07:43:10.65#ibcon#read 4, iclass 24, count 2 2006.161.07:43:10.65#ibcon#about to read 5, iclass 24, count 2 2006.161.07:43:10.65#ibcon#read 5, iclass 24, count 2 2006.161.07:43:10.65#ibcon#about to read 6, iclass 24, count 2 2006.161.07:43:10.65#ibcon#read 6, iclass 24, count 2 2006.161.07:43:10.65#ibcon#end of sib2, iclass 24, count 2 2006.161.07:43:10.65#ibcon#*after write, iclass 24, count 2 2006.161.07:43:10.65#ibcon#*before return 0, iclass 24, count 2 2006.161.07:43:10.65#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:10.65#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:10.65#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.07:43:10.65#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:10.65#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:10.77#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:10.77#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:10.77#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:43:10.77#ibcon#first serial, iclass 24, count 0 2006.161.07:43:10.77#ibcon#enter sib2, iclass 24, count 0 2006.161.07:43:10.77#ibcon#flushed, iclass 24, count 0 2006.161.07:43:10.77#ibcon#about to write, iclass 24, count 0 2006.161.07:43:10.77#ibcon#wrote, iclass 24, count 0 2006.161.07:43:10.77#ibcon#about to read 3, iclass 24, count 0 2006.161.07:43:10.79#ibcon#read 3, iclass 24, count 0 2006.161.07:43:10.79#ibcon#about to read 4, iclass 24, count 0 2006.161.07:43:10.79#ibcon#read 4, iclass 24, count 0 2006.161.07:43:10.79#ibcon#about to read 5, iclass 24, count 0 2006.161.07:43:10.79#ibcon#read 5, iclass 24, count 0 2006.161.07:43:10.79#ibcon#about to read 6, iclass 24, count 0 2006.161.07:43:10.79#ibcon#read 6, iclass 24, count 0 2006.161.07:43:10.79#ibcon#end of sib2, iclass 24, count 0 2006.161.07:43:10.79#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:43:10.79#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:43:10.79#ibcon#[25=USB\r\n] 2006.161.07:43:10.79#ibcon#*before write, iclass 24, count 0 2006.161.07:43:10.79#ibcon#enter sib2, iclass 24, count 0 2006.161.07:43:10.79#ibcon#flushed, iclass 24, count 0 2006.161.07:43:10.79#ibcon#about to write, iclass 24, count 0 2006.161.07:43:10.79#ibcon#wrote, iclass 24, count 0 2006.161.07:43:10.79#ibcon#about to read 3, iclass 24, count 0 2006.161.07:43:10.82#ibcon#read 3, iclass 24, count 0 2006.161.07:43:10.82#ibcon#about to read 4, iclass 24, count 0 2006.161.07:43:10.82#ibcon#read 4, iclass 24, count 0 2006.161.07:43:10.82#ibcon#about to read 5, iclass 24, count 0 2006.161.07:43:10.82#ibcon#read 5, iclass 24, count 0 2006.161.07:43:10.82#ibcon#about to read 6, iclass 24, count 0 2006.161.07:43:10.82#ibcon#read 6, iclass 24, count 0 2006.161.07:43:10.82#ibcon#end of sib2, iclass 24, count 0 2006.161.07:43:10.82#ibcon#*after write, iclass 24, count 0 2006.161.07:43:10.82#ibcon#*before return 0, iclass 24, count 0 2006.161.07:43:10.82#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:10.82#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:10.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:43:10.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:43:10.82$vc4f8/valo=5,652.99 2006.161.07:43:10.82#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:43:10.82#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:43:10.82#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:10.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:10.82#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:10.82#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:10.82#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:43:10.82#ibcon#first serial, iclass 26, count 0 2006.161.07:43:10.82#ibcon#enter sib2, iclass 26, count 0 2006.161.07:43:10.82#ibcon#flushed, iclass 26, count 0 2006.161.07:43:10.82#ibcon#about to write, iclass 26, count 0 2006.161.07:43:10.82#ibcon#wrote, iclass 26, count 0 2006.161.07:43:10.82#ibcon#about to read 3, iclass 26, count 0 2006.161.07:43:10.84#ibcon#read 3, iclass 26, count 0 2006.161.07:43:10.84#ibcon#about to read 4, iclass 26, count 0 2006.161.07:43:10.84#ibcon#read 4, iclass 26, count 0 2006.161.07:43:10.84#ibcon#about to read 5, iclass 26, count 0 2006.161.07:43:10.84#ibcon#read 5, iclass 26, count 0 2006.161.07:43:10.84#ibcon#about to read 6, iclass 26, count 0 2006.161.07:43:10.84#ibcon#read 6, iclass 26, count 0 2006.161.07:43:10.84#ibcon#end of sib2, iclass 26, count 0 2006.161.07:43:10.84#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:43:10.84#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:43:10.84#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:43:10.84#ibcon#*before write, iclass 26, count 0 2006.161.07:43:10.84#ibcon#enter sib2, iclass 26, count 0 2006.161.07:43:10.84#ibcon#flushed, iclass 26, count 0 2006.161.07:43:10.84#ibcon#about to write, iclass 26, count 0 2006.161.07:43:10.84#ibcon#wrote, iclass 26, count 0 2006.161.07:43:10.84#ibcon#about to read 3, iclass 26, count 0 2006.161.07:43:10.88#ibcon#read 3, iclass 26, count 0 2006.161.07:43:10.88#ibcon#about to read 4, iclass 26, count 0 2006.161.07:43:10.88#ibcon#read 4, iclass 26, count 0 2006.161.07:43:10.88#ibcon#about to read 5, iclass 26, count 0 2006.161.07:43:10.88#ibcon#read 5, iclass 26, count 0 2006.161.07:43:10.88#ibcon#about to read 6, iclass 26, count 0 2006.161.07:43:10.88#ibcon#read 6, iclass 26, count 0 2006.161.07:43:10.88#ibcon#end of sib2, iclass 26, count 0 2006.161.07:43:10.88#ibcon#*after write, iclass 26, count 0 2006.161.07:43:10.88#ibcon#*before return 0, iclass 26, count 0 2006.161.07:43:10.88#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:10.88#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:10.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:43:10.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:43:10.88$vc4f8/va=5,7 2006.161.07:43:10.88#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.07:43:10.88#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.07:43:10.88#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:10.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:10.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:10.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:10.94#ibcon#enter wrdev, iclass 28, count 2 2006.161.07:43:10.94#ibcon#first serial, iclass 28, count 2 2006.161.07:43:10.94#ibcon#enter sib2, iclass 28, count 2 2006.161.07:43:10.94#ibcon#flushed, iclass 28, count 2 2006.161.07:43:10.94#ibcon#about to write, iclass 28, count 2 2006.161.07:43:10.94#ibcon#wrote, iclass 28, count 2 2006.161.07:43:10.94#ibcon#about to read 3, iclass 28, count 2 2006.161.07:43:10.96#ibcon#read 3, iclass 28, count 2 2006.161.07:43:10.96#ibcon#about to read 4, iclass 28, count 2 2006.161.07:43:10.96#ibcon#read 4, iclass 28, count 2 2006.161.07:43:10.96#ibcon#about to read 5, iclass 28, count 2 2006.161.07:43:10.96#ibcon#read 5, iclass 28, count 2 2006.161.07:43:10.96#ibcon#about to read 6, iclass 28, count 2 2006.161.07:43:10.96#ibcon#read 6, iclass 28, count 2 2006.161.07:43:10.96#ibcon#end of sib2, iclass 28, count 2 2006.161.07:43:10.96#ibcon#*mode == 0, iclass 28, count 2 2006.161.07:43:10.96#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.07:43:10.96#ibcon#[25=AT05-07\r\n] 2006.161.07:43:10.96#ibcon#*before write, iclass 28, count 2 2006.161.07:43:10.96#ibcon#enter sib2, iclass 28, count 2 2006.161.07:43:10.96#ibcon#flushed, iclass 28, count 2 2006.161.07:43:10.96#ibcon#about to write, iclass 28, count 2 2006.161.07:43:10.96#ibcon#wrote, iclass 28, count 2 2006.161.07:43:10.96#ibcon#about to read 3, iclass 28, count 2 2006.161.07:43:10.99#ibcon#read 3, iclass 28, count 2 2006.161.07:43:10.99#ibcon#about to read 4, iclass 28, count 2 2006.161.07:43:10.99#ibcon#read 4, iclass 28, count 2 2006.161.07:43:10.99#ibcon#about to read 5, iclass 28, count 2 2006.161.07:43:10.99#ibcon#read 5, iclass 28, count 2 2006.161.07:43:10.99#ibcon#about to read 6, iclass 28, count 2 2006.161.07:43:10.99#ibcon#read 6, iclass 28, count 2 2006.161.07:43:10.99#ibcon#end of sib2, iclass 28, count 2 2006.161.07:43:10.99#ibcon#*after write, iclass 28, count 2 2006.161.07:43:10.99#ibcon#*before return 0, iclass 28, count 2 2006.161.07:43:10.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:10.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:10.99#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.07:43:10.99#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:10.99#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:11.11#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:11.11#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:11.11#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:43:11.11#ibcon#first serial, iclass 28, count 0 2006.161.07:43:11.11#ibcon#enter sib2, iclass 28, count 0 2006.161.07:43:11.11#ibcon#flushed, iclass 28, count 0 2006.161.07:43:11.11#ibcon#about to write, iclass 28, count 0 2006.161.07:43:11.11#ibcon#wrote, iclass 28, count 0 2006.161.07:43:11.11#ibcon#about to read 3, iclass 28, count 0 2006.161.07:43:11.13#ibcon#read 3, iclass 28, count 0 2006.161.07:43:11.13#ibcon#about to read 4, iclass 28, count 0 2006.161.07:43:11.13#ibcon#read 4, iclass 28, count 0 2006.161.07:43:11.13#ibcon#about to read 5, iclass 28, count 0 2006.161.07:43:11.13#ibcon#read 5, iclass 28, count 0 2006.161.07:43:11.13#ibcon#about to read 6, iclass 28, count 0 2006.161.07:43:11.13#ibcon#read 6, iclass 28, count 0 2006.161.07:43:11.13#ibcon#end of sib2, iclass 28, count 0 2006.161.07:43:11.13#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:43:11.13#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:43:11.13#ibcon#[25=USB\r\n] 2006.161.07:43:11.13#ibcon#*before write, iclass 28, count 0 2006.161.07:43:11.13#ibcon#enter sib2, iclass 28, count 0 2006.161.07:43:11.13#ibcon#flushed, iclass 28, count 0 2006.161.07:43:11.13#ibcon#about to write, iclass 28, count 0 2006.161.07:43:11.13#ibcon#wrote, iclass 28, count 0 2006.161.07:43:11.13#ibcon#about to read 3, iclass 28, count 0 2006.161.07:43:11.16#ibcon#read 3, iclass 28, count 0 2006.161.07:43:11.16#ibcon#about to read 4, iclass 28, count 0 2006.161.07:43:11.16#ibcon#read 4, iclass 28, count 0 2006.161.07:43:11.16#ibcon#about to read 5, iclass 28, count 0 2006.161.07:43:11.16#ibcon#read 5, iclass 28, count 0 2006.161.07:43:11.16#ibcon#about to read 6, iclass 28, count 0 2006.161.07:43:11.16#ibcon#read 6, iclass 28, count 0 2006.161.07:43:11.16#ibcon#end of sib2, iclass 28, count 0 2006.161.07:43:11.16#ibcon#*after write, iclass 28, count 0 2006.161.07:43:11.16#ibcon#*before return 0, iclass 28, count 0 2006.161.07:43:11.16#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:11.16#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:11.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:43:11.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:43:11.16$vc4f8/valo=6,772.99 2006.161.07:43:11.16#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:43:11.16#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:43:11.16#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:11.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:11.16#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:11.16#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:11.16#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:43:11.16#ibcon#first serial, iclass 30, count 0 2006.161.07:43:11.16#ibcon#enter sib2, iclass 30, count 0 2006.161.07:43:11.16#ibcon#flushed, iclass 30, count 0 2006.161.07:43:11.16#ibcon#about to write, iclass 30, count 0 2006.161.07:43:11.16#ibcon#wrote, iclass 30, count 0 2006.161.07:43:11.16#ibcon#about to read 3, iclass 30, count 0 2006.161.07:43:11.19#ibcon#read 3, iclass 30, count 0 2006.161.07:43:11.19#ibcon#about to read 4, iclass 30, count 0 2006.161.07:43:11.19#ibcon#read 4, iclass 30, count 0 2006.161.07:43:11.19#ibcon#about to read 5, iclass 30, count 0 2006.161.07:43:11.19#ibcon#read 5, iclass 30, count 0 2006.161.07:43:11.19#ibcon#about to read 6, iclass 30, count 0 2006.161.07:43:11.19#ibcon#read 6, iclass 30, count 0 2006.161.07:43:11.19#ibcon#end of sib2, iclass 30, count 0 2006.161.07:43:11.19#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:43:11.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:43:11.19#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:43:11.19#ibcon#*before write, iclass 30, count 0 2006.161.07:43:11.19#ibcon#enter sib2, iclass 30, count 0 2006.161.07:43:11.19#ibcon#flushed, iclass 30, count 0 2006.161.07:43:11.19#ibcon#about to write, iclass 30, count 0 2006.161.07:43:11.19#ibcon#wrote, iclass 30, count 0 2006.161.07:43:11.19#ibcon#about to read 3, iclass 30, count 0 2006.161.07:43:11.23#ibcon#read 3, iclass 30, count 0 2006.161.07:43:11.23#ibcon#about to read 4, iclass 30, count 0 2006.161.07:43:11.23#ibcon#read 4, iclass 30, count 0 2006.161.07:43:11.23#ibcon#about to read 5, iclass 30, count 0 2006.161.07:43:11.23#ibcon#read 5, iclass 30, count 0 2006.161.07:43:11.23#ibcon#about to read 6, iclass 30, count 0 2006.161.07:43:11.23#ibcon#read 6, iclass 30, count 0 2006.161.07:43:11.23#ibcon#end of sib2, iclass 30, count 0 2006.161.07:43:11.23#ibcon#*after write, iclass 30, count 0 2006.161.07:43:11.23#ibcon#*before return 0, iclass 30, count 0 2006.161.07:43:11.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:11.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:11.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:43:11.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:43:11.23$vc4f8/va=6,6 2006.161.07:43:11.23#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:43:11.23#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:43:11.23#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:11.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:11.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:11.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:11.28#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:43:11.28#ibcon#first serial, iclass 32, count 2 2006.161.07:43:11.28#ibcon#enter sib2, iclass 32, count 2 2006.161.07:43:11.28#ibcon#flushed, iclass 32, count 2 2006.161.07:43:11.28#ibcon#about to write, iclass 32, count 2 2006.161.07:43:11.28#ibcon#wrote, iclass 32, count 2 2006.161.07:43:11.28#ibcon#about to read 3, iclass 32, count 2 2006.161.07:43:11.30#ibcon#read 3, iclass 32, count 2 2006.161.07:43:11.30#ibcon#about to read 4, iclass 32, count 2 2006.161.07:43:11.30#ibcon#read 4, iclass 32, count 2 2006.161.07:43:11.30#ibcon#about to read 5, iclass 32, count 2 2006.161.07:43:11.30#ibcon#read 5, iclass 32, count 2 2006.161.07:43:11.30#ibcon#about to read 6, iclass 32, count 2 2006.161.07:43:11.30#ibcon#read 6, iclass 32, count 2 2006.161.07:43:11.30#ibcon#end of sib2, iclass 32, count 2 2006.161.07:43:11.30#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:43:11.30#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:43:11.30#ibcon#[25=AT06-06\r\n] 2006.161.07:43:11.30#ibcon#*before write, iclass 32, count 2 2006.161.07:43:11.30#ibcon#enter sib2, iclass 32, count 2 2006.161.07:43:11.30#ibcon#flushed, iclass 32, count 2 2006.161.07:43:11.30#ibcon#about to write, iclass 32, count 2 2006.161.07:43:11.30#ibcon#wrote, iclass 32, count 2 2006.161.07:43:11.30#ibcon#about to read 3, iclass 32, count 2 2006.161.07:43:11.33#ibcon#read 3, iclass 32, count 2 2006.161.07:43:11.33#ibcon#about to read 4, iclass 32, count 2 2006.161.07:43:11.33#ibcon#read 4, iclass 32, count 2 2006.161.07:43:11.33#ibcon#about to read 5, iclass 32, count 2 2006.161.07:43:11.33#ibcon#read 5, iclass 32, count 2 2006.161.07:43:11.33#ibcon#about to read 6, iclass 32, count 2 2006.161.07:43:11.33#ibcon#read 6, iclass 32, count 2 2006.161.07:43:11.33#ibcon#end of sib2, iclass 32, count 2 2006.161.07:43:11.33#ibcon#*after write, iclass 32, count 2 2006.161.07:43:11.33#ibcon#*before return 0, iclass 32, count 2 2006.161.07:43:11.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:11.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:11.33#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:43:11.33#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:11.33#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:43:11.45#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:43:11.45#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:43:11.45#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:43:11.45#ibcon#first serial, iclass 32, count 0 2006.161.07:43:11.45#ibcon#enter sib2, iclass 32, count 0 2006.161.07:43:11.45#ibcon#flushed, iclass 32, count 0 2006.161.07:43:11.45#ibcon#about to write, iclass 32, count 0 2006.161.07:43:11.45#ibcon#wrote, iclass 32, count 0 2006.161.07:43:11.45#ibcon#about to read 3, iclass 32, count 0 2006.161.07:43:11.47#ibcon#read 3, iclass 32, count 0 2006.161.07:43:11.47#ibcon#about to read 4, iclass 32, count 0 2006.161.07:43:11.47#ibcon#read 4, iclass 32, count 0 2006.161.07:43:11.47#ibcon#about to read 5, iclass 32, count 0 2006.161.07:43:11.47#ibcon#read 5, iclass 32, count 0 2006.161.07:43:11.47#ibcon#about to read 6, iclass 32, count 0 2006.161.07:43:11.47#ibcon#read 6, iclass 32, count 0 2006.161.07:43:11.47#ibcon#end of sib2, iclass 32, count 0 2006.161.07:43:11.47#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:43:11.47#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:43:11.47#ibcon#[25=USB\r\n] 2006.161.07:43:11.47#ibcon#*before write, iclass 32, count 0 2006.161.07:43:11.47#ibcon#enter sib2, iclass 32, count 0 2006.161.07:43:11.47#ibcon#flushed, iclass 32, count 0 2006.161.07:43:11.47#ibcon#about to write, iclass 32, count 0 2006.161.07:43:11.47#ibcon#wrote, iclass 32, count 0 2006.161.07:43:11.47#ibcon#about to read 3, iclass 32, count 0 2006.161.07:43:11.50#ibcon#read 3, iclass 32, count 0 2006.161.07:43:11.50#ibcon#about to read 4, iclass 32, count 0 2006.161.07:43:11.50#ibcon#read 4, iclass 32, count 0 2006.161.07:43:11.50#ibcon#about to read 5, iclass 32, count 0 2006.161.07:43:11.50#ibcon#read 5, iclass 32, count 0 2006.161.07:43:11.50#ibcon#about to read 6, iclass 32, count 0 2006.161.07:43:11.50#ibcon#read 6, iclass 32, count 0 2006.161.07:43:11.50#ibcon#end of sib2, iclass 32, count 0 2006.161.07:43:11.50#ibcon#*after write, iclass 32, count 0 2006.161.07:43:11.50#ibcon#*before return 0, iclass 32, count 0 2006.161.07:43:11.50#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:43:11.50#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:43:11.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:43:11.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:43:11.50$vc4f8/valo=7,832.99 2006.161.07:43:11.50#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.07:43:11.50#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.07:43:11.50#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:11.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:43:11.50#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:43:11.50#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:43:11.50#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:43:11.50#ibcon#first serial, iclass 34, count 0 2006.161.07:43:11.50#ibcon#enter sib2, iclass 34, count 0 2006.161.07:43:11.50#ibcon#flushed, iclass 34, count 0 2006.161.07:43:11.50#ibcon#about to write, iclass 34, count 0 2006.161.07:43:11.50#ibcon#wrote, iclass 34, count 0 2006.161.07:43:11.50#ibcon#about to read 3, iclass 34, count 0 2006.161.07:43:11.52#ibcon#read 3, iclass 34, count 0 2006.161.07:43:11.52#ibcon#about to read 4, iclass 34, count 0 2006.161.07:43:11.52#ibcon#read 4, iclass 34, count 0 2006.161.07:43:11.52#ibcon#about to read 5, iclass 34, count 0 2006.161.07:43:11.52#ibcon#read 5, iclass 34, count 0 2006.161.07:43:11.52#ibcon#about to read 6, iclass 34, count 0 2006.161.07:43:11.52#ibcon#read 6, iclass 34, count 0 2006.161.07:43:11.52#ibcon#end of sib2, iclass 34, count 0 2006.161.07:43:11.52#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:43:11.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:43:11.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:43:11.52#ibcon#*before write, iclass 34, count 0 2006.161.07:43:11.52#ibcon#enter sib2, iclass 34, count 0 2006.161.07:43:11.52#ibcon#flushed, iclass 34, count 0 2006.161.07:43:11.52#ibcon#about to write, iclass 34, count 0 2006.161.07:43:11.52#ibcon#wrote, iclass 34, count 0 2006.161.07:43:11.52#ibcon#about to read 3, iclass 34, count 0 2006.161.07:43:11.56#ibcon#read 3, iclass 34, count 0 2006.161.07:43:11.56#ibcon#about to read 4, iclass 34, count 0 2006.161.07:43:11.56#ibcon#read 4, iclass 34, count 0 2006.161.07:43:11.56#ibcon#about to read 5, iclass 34, count 0 2006.161.07:43:11.56#ibcon#read 5, iclass 34, count 0 2006.161.07:43:11.56#ibcon#about to read 6, iclass 34, count 0 2006.161.07:43:11.56#ibcon#read 6, iclass 34, count 0 2006.161.07:43:11.56#ibcon#end of sib2, iclass 34, count 0 2006.161.07:43:11.56#ibcon#*after write, iclass 34, count 0 2006.161.07:43:11.56#ibcon#*before return 0, iclass 34, count 0 2006.161.07:43:11.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:43:11.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:43:11.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:43:11.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:43:11.56$vc4f8/va=7,6 2006.161.07:43:11.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.07:43:11.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.07:43:11.56#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:11.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:43:11.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:43:11.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:43:11.62#ibcon#enter wrdev, iclass 36, count 2 2006.161.07:43:11.62#ibcon#first serial, iclass 36, count 2 2006.161.07:43:11.62#ibcon#enter sib2, iclass 36, count 2 2006.161.07:43:11.62#ibcon#flushed, iclass 36, count 2 2006.161.07:43:11.62#ibcon#about to write, iclass 36, count 2 2006.161.07:43:11.62#ibcon#wrote, iclass 36, count 2 2006.161.07:43:11.62#ibcon#about to read 3, iclass 36, count 2 2006.161.07:43:11.64#ibcon#read 3, iclass 36, count 2 2006.161.07:43:11.64#ibcon#about to read 4, iclass 36, count 2 2006.161.07:43:11.64#ibcon#read 4, iclass 36, count 2 2006.161.07:43:11.64#ibcon#about to read 5, iclass 36, count 2 2006.161.07:43:11.64#ibcon#read 5, iclass 36, count 2 2006.161.07:43:11.64#ibcon#about to read 6, iclass 36, count 2 2006.161.07:43:11.64#ibcon#read 6, iclass 36, count 2 2006.161.07:43:11.64#ibcon#end of sib2, iclass 36, count 2 2006.161.07:43:11.64#ibcon#*mode == 0, iclass 36, count 2 2006.161.07:43:11.64#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.07:43:11.64#ibcon#[25=AT07-06\r\n] 2006.161.07:43:11.64#ibcon#*before write, iclass 36, count 2 2006.161.07:43:11.64#ibcon#enter sib2, iclass 36, count 2 2006.161.07:43:11.64#ibcon#flushed, iclass 36, count 2 2006.161.07:43:11.64#ibcon#about to write, iclass 36, count 2 2006.161.07:43:11.64#ibcon#wrote, iclass 36, count 2 2006.161.07:43:11.64#ibcon#about to read 3, iclass 36, count 2 2006.161.07:43:11.67#ibcon#read 3, iclass 36, count 2 2006.161.07:43:11.67#ibcon#about to read 4, iclass 36, count 2 2006.161.07:43:11.67#ibcon#read 4, iclass 36, count 2 2006.161.07:43:11.67#ibcon#about to read 5, iclass 36, count 2 2006.161.07:43:11.67#ibcon#read 5, iclass 36, count 2 2006.161.07:43:11.67#ibcon#about to read 6, iclass 36, count 2 2006.161.07:43:11.67#ibcon#read 6, iclass 36, count 2 2006.161.07:43:11.67#ibcon#end of sib2, iclass 36, count 2 2006.161.07:43:11.67#ibcon#*after write, iclass 36, count 2 2006.161.07:43:11.67#ibcon#*before return 0, iclass 36, count 2 2006.161.07:43:11.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:43:11.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:43:11.67#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.07:43:11.67#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:11.67#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:43:11.79#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:43:11.79#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:43:11.79#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:43:11.79#ibcon#first serial, iclass 36, count 0 2006.161.07:43:11.79#ibcon#enter sib2, iclass 36, count 0 2006.161.07:43:11.79#ibcon#flushed, iclass 36, count 0 2006.161.07:43:11.79#ibcon#about to write, iclass 36, count 0 2006.161.07:43:11.79#ibcon#wrote, iclass 36, count 0 2006.161.07:43:11.79#ibcon#about to read 3, iclass 36, count 0 2006.161.07:43:11.81#ibcon#read 3, iclass 36, count 0 2006.161.07:43:11.81#ibcon#about to read 4, iclass 36, count 0 2006.161.07:43:11.81#ibcon#read 4, iclass 36, count 0 2006.161.07:43:11.81#ibcon#about to read 5, iclass 36, count 0 2006.161.07:43:11.81#ibcon#read 5, iclass 36, count 0 2006.161.07:43:11.81#ibcon#about to read 6, iclass 36, count 0 2006.161.07:43:11.81#ibcon#read 6, iclass 36, count 0 2006.161.07:43:11.81#ibcon#end of sib2, iclass 36, count 0 2006.161.07:43:11.81#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:43:11.81#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:43:11.81#ibcon#[25=USB\r\n] 2006.161.07:43:11.81#ibcon#*before write, iclass 36, count 0 2006.161.07:43:11.81#ibcon#enter sib2, iclass 36, count 0 2006.161.07:43:11.81#ibcon#flushed, iclass 36, count 0 2006.161.07:43:11.81#ibcon#about to write, iclass 36, count 0 2006.161.07:43:11.81#ibcon#wrote, iclass 36, count 0 2006.161.07:43:11.81#ibcon#about to read 3, iclass 36, count 0 2006.161.07:43:11.84#ibcon#read 3, iclass 36, count 0 2006.161.07:43:11.84#ibcon#about to read 4, iclass 36, count 0 2006.161.07:43:11.84#ibcon#read 4, iclass 36, count 0 2006.161.07:43:11.84#ibcon#about to read 5, iclass 36, count 0 2006.161.07:43:11.84#ibcon#read 5, iclass 36, count 0 2006.161.07:43:11.84#ibcon#about to read 6, iclass 36, count 0 2006.161.07:43:11.84#ibcon#read 6, iclass 36, count 0 2006.161.07:43:11.84#ibcon#end of sib2, iclass 36, count 0 2006.161.07:43:11.84#ibcon#*after write, iclass 36, count 0 2006.161.07:43:11.84#ibcon#*before return 0, iclass 36, count 0 2006.161.07:43:11.84#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:43:11.84#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:43:11.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:43:11.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:43:11.84$vc4f8/valo=8,852.99 2006.161.07:43:11.84#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.07:43:11.84#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.07:43:11.84#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:11.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:43:11.84#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:43:11.84#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:43:11.84#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:43:11.84#ibcon#first serial, iclass 38, count 0 2006.161.07:43:11.84#ibcon#enter sib2, iclass 38, count 0 2006.161.07:43:11.84#ibcon#flushed, iclass 38, count 0 2006.161.07:43:11.84#ibcon#about to write, iclass 38, count 0 2006.161.07:43:11.84#ibcon#wrote, iclass 38, count 0 2006.161.07:43:11.84#ibcon#about to read 3, iclass 38, count 0 2006.161.07:43:11.86#ibcon#read 3, iclass 38, count 0 2006.161.07:43:11.86#ibcon#about to read 4, iclass 38, count 0 2006.161.07:43:11.86#ibcon#read 4, iclass 38, count 0 2006.161.07:43:11.86#ibcon#about to read 5, iclass 38, count 0 2006.161.07:43:11.86#ibcon#read 5, iclass 38, count 0 2006.161.07:43:11.86#ibcon#about to read 6, iclass 38, count 0 2006.161.07:43:11.86#ibcon#read 6, iclass 38, count 0 2006.161.07:43:11.86#ibcon#end of sib2, iclass 38, count 0 2006.161.07:43:11.86#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:43:11.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:43:11.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:43:11.86#ibcon#*before write, iclass 38, count 0 2006.161.07:43:11.86#ibcon#enter sib2, iclass 38, count 0 2006.161.07:43:11.86#ibcon#flushed, iclass 38, count 0 2006.161.07:43:11.86#ibcon#about to write, iclass 38, count 0 2006.161.07:43:11.86#ibcon#wrote, iclass 38, count 0 2006.161.07:43:11.86#ibcon#about to read 3, iclass 38, count 0 2006.161.07:43:11.90#ibcon#read 3, iclass 38, count 0 2006.161.07:43:11.90#ibcon#about to read 4, iclass 38, count 0 2006.161.07:43:11.90#ibcon#read 4, iclass 38, count 0 2006.161.07:43:11.90#ibcon#about to read 5, iclass 38, count 0 2006.161.07:43:11.90#ibcon#read 5, iclass 38, count 0 2006.161.07:43:11.90#ibcon#about to read 6, iclass 38, count 0 2006.161.07:43:11.90#ibcon#read 6, iclass 38, count 0 2006.161.07:43:11.90#ibcon#end of sib2, iclass 38, count 0 2006.161.07:43:11.90#ibcon#*after write, iclass 38, count 0 2006.161.07:43:11.90#ibcon#*before return 0, iclass 38, count 0 2006.161.07:43:11.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:43:11.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:43:11.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:43:11.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:43:11.90$vc4f8/va=8,7 2006.161.07:43:11.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.07:43:11.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.07:43:11.90#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:11.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:43:11.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:43:11.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:43:11.96#ibcon#enter wrdev, iclass 40, count 2 2006.161.07:43:11.96#ibcon#first serial, iclass 40, count 2 2006.161.07:43:11.96#ibcon#enter sib2, iclass 40, count 2 2006.161.07:43:11.96#ibcon#flushed, iclass 40, count 2 2006.161.07:43:11.96#ibcon#about to write, iclass 40, count 2 2006.161.07:43:11.96#ibcon#wrote, iclass 40, count 2 2006.161.07:43:11.96#ibcon#about to read 3, iclass 40, count 2 2006.161.07:43:11.99#ibcon#read 3, iclass 40, count 2 2006.161.07:43:11.99#ibcon#about to read 4, iclass 40, count 2 2006.161.07:43:11.99#ibcon#read 4, iclass 40, count 2 2006.161.07:43:11.99#ibcon#about to read 5, iclass 40, count 2 2006.161.07:43:11.99#ibcon#read 5, iclass 40, count 2 2006.161.07:43:11.99#ibcon#about to read 6, iclass 40, count 2 2006.161.07:43:11.99#ibcon#read 6, iclass 40, count 2 2006.161.07:43:11.99#ibcon#end of sib2, iclass 40, count 2 2006.161.07:43:11.99#ibcon#*mode == 0, iclass 40, count 2 2006.161.07:43:11.99#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.07:43:11.99#ibcon#[25=AT08-07\r\n] 2006.161.07:43:11.99#ibcon#*before write, iclass 40, count 2 2006.161.07:43:11.99#ibcon#enter sib2, iclass 40, count 2 2006.161.07:43:11.99#ibcon#flushed, iclass 40, count 2 2006.161.07:43:11.99#ibcon#about to write, iclass 40, count 2 2006.161.07:43:11.99#ibcon#wrote, iclass 40, count 2 2006.161.07:43:11.99#ibcon#about to read 3, iclass 40, count 2 2006.161.07:43:12.02#ibcon#read 3, iclass 40, count 2 2006.161.07:43:12.02#ibcon#about to read 4, iclass 40, count 2 2006.161.07:43:12.02#ibcon#read 4, iclass 40, count 2 2006.161.07:43:12.02#ibcon#about to read 5, iclass 40, count 2 2006.161.07:43:12.02#ibcon#read 5, iclass 40, count 2 2006.161.07:43:12.02#ibcon#about to read 6, iclass 40, count 2 2006.161.07:43:12.02#ibcon#read 6, iclass 40, count 2 2006.161.07:43:12.02#ibcon#end of sib2, iclass 40, count 2 2006.161.07:43:12.02#ibcon#*after write, iclass 40, count 2 2006.161.07:43:12.02#ibcon#*before return 0, iclass 40, count 2 2006.161.07:43:12.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:43:12.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:43:12.02#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.07:43:12.02#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:12.02#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:43:12.14#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:43:12.14#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:43:12.14#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:43:12.14#ibcon#first serial, iclass 40, count 0 2006.161.07:43:12.14#ibcon#enter sib2, iclass 40, count 0 2006.161.07:43:12.14#ibcon#flushed, iclass 40, count 0 2006.161.07:43:12.14#ibcon#about to write, iclass 40, count 0 2006.161.07:43:12.14#ibcon#wrote, iclass 40, count 0 2006.161.07:43:12.14#ibcon#about to read 3, iclass 40, count 0 2006.161.07:43:12.16#ibcon#read 3, iclass 40, count 0 2006.161.07:43:12.16#ibcon#about to read 4, iclass 40, count 0 2006.161.07:43:12.16#ibcon#read 4, iclass 40, count 0 2006.161.07:43:12.16#ibcon#about to read 5, iclass 40, count 0 2006.161.07:43:12.16#ibcon#read 5, iclass 40, count 0 2006.161.07:43:12.16#ibcon#about to read 6, iclass 40, count 0 2006.161.07:43:12.16#ibcon#read 6, iclass 40, count 0 2006.161.07:43:12.16#ibcon#end of sib2, iclass 40, count 0 2006.161.07:43:12.16#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:43:12.16#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:43:12.16#ibcon#[25=USB\r\n] 2006.161.07:43:12.16#ibcon#*before write, iclass 40, count 0 2006.161.07:43:12.16#ibcon#enter sib2, iclass 40, count 0 2006.161.07:43:12.16#ibcon#flushed, iclass 40, count 0 2006.161.07:43:12.16#ibcon#about to write, iclass 40, count 0 2006.161.07:43:12.16#ibcon#wrote, iclass 40, count 0 2006.161.07:43:12.16#ibcon#about to read 3, iclass 40, count 0 2006.161.07:43:12.19#ibcon#read 3, iclass 40, count 0 2006.161.07:43:12.19#ibcon#about to read 4, iclass 40, count 0 2006.161.07:43:12.19#ibcon#read 4, iclass 40, count 0 2006.161.07:43:12.19#ibcon#about to read 5, iclass 40, count 0 2006.161.07:43:12.19#ibcon#read 5, iclass 40, count 0 2006.161.07:43:12.19#ibcon#about to read 6, iclass 40, count 0 2006.161.07:43:12.19#ibcon#read 6, iclass 40, count 0 2006.161.07:43:12.19#ibcon#end of sib2, iclass 40, count 0 2006.161.07:43:12.19#ibcon#*after write, iclass 40, count 0 2006.161.07:43:12.19#ibcon#*before return 0, iclass 40, count 0 2006.161.07:43:12.19#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:43:12.19#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:43:12.19#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:43:12.19#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:43:12.19$vc4f8/vblo=1,632.99 2006.161.07:43:12.19#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.07:43:12.19#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.07:43:12.19#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:12.19#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:43:12.19#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:43:12.19#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:43:12.19#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:43:12.19#ibcon#first serial, iclass 4, count 0 2006.161.07:43:12.19#ibcon#enter sib2, iclass 4, count 0 2006.161.07:43:12.19#ibcon#flushed, iclass 4, count 0 2006.161.07:43:12.19#ibcon#about to write, iclass 4, count 0 2006.161.07:43:12.19#ibcon#wrote, iclass 4, count 0 2006.161.07:43:12.19#ibcon#about to read 3, iclass 4, count 0 2006.161.07:43:12.21#ibcon#read 3, iclass 4, count 0 2006.161.07:43:12.21#ibcon#about to read 4, iclass 4, count 0 2006.161.07:43:12.21#ibcon#read 4, iclass 4, count 0 2006.161.07:43:12.21#ibcon#about to read 5, iclass 4, count 0 2006.161.07:43:12.21#ibcon#read 5, iclass 4, count 0 2006.161.07:43:12.21#ibcon#about to read 6, iclass 4, count 0 2006.161.07:43:12.21#ibcon#read 6, iclass 4, count 0 2006.161.07:43:12.21#ibcon#end of sib2, iclass 4, count 0 2006.161.07:43:12.21#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:43:12.21#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:43:12.21#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:43:12.21#ibcon#*before write, iclass 4, count 0 2006.161.07:43:12.21#ibcon#enter sib2, iclass 4, count 0 2006.161.07:43:12.21#ibcon#flushed, iclass 4, count 0 2006.161.07:43:12.21#ibcon#about to write, iclass 4, count 0 2006.161.07:43:12.21#ibcon#wrote, iclass 4, count 0 2006.161.07:43:12.21#ibcon#about to read 3, iclass 4, count 0 2006.161.07:43:12.25#ibcon#read 3, iclass 4, count 0 2006.161.07:43:12.25#ibcon#about to read 4, iclass 4, count 0 2006.161.07:43:12.25#ibcon#read 4, iclass 4, count 0 2006.161.07:43:12.25#ibcon#about to read 5, iclass 4, count 0 2006.161.07:43:12.25#ibcon#read 5, iclass 4, count 0 2006.161.07:43:12.25#ibcon#about to read 6, iclass 4, count 0 2006.161.07:43:12.25#ibcon#read 6, iclass 4, count 0 2006.161.07:43:12.25#ibcon#end of sib2, iclass 4, count 0 2006.161.07:43:12.25#ibcon#*after write, iclass 4, count 0 2006.161.07:43:12.25#ibcon#*before return 0, iclass 4, count 0 2006.161.07:43:12.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:43:12.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:43:12.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:43:12.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:43:12.25$vc4f8/vb=1,4 2006.161.07:43:12.25#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.07:43:12.25#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.07:43:12.25#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:12.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:43:12.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:43:12.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:43:12.25#ibcon#enter wrdev, iclass 6, count 2 2006.161.07:43:12.25#ibcon#first serial, iclass 6, count 2 2006.161.07:43:12.25#ibcon#enter sib2, iclass 6, count 2 2006.161.07:43:12.25#ibcon#flushed, iclass 6, count 2 2006.161.07:43:12.25#ibcon#about to write, iclass 6, count 2 2006.161.07:43:12.25#ibcon#wrote, iclass 6, count 2 2006.161.07:43:12.25#ibcon#about to read 3, iclass 6, count 2 2006.161.07:43:12.27#ibcon#read 3, iclass 6, count 2 2006.161.07:43:12.27#ibcon#about to read 4, iclass 6, count 2 2006.161.07:43:12.27#ibcon#read 4, iclass 6, count 2 2006.161.07:43:12.27#ibcon#about to read 5, iclass 6, count 2 2006.161.07:43:12.27#ibcon#read 5, iclass 6, count 2 2006.161.07:43:12.27#ibcon#about to read 6, iclass 6, count 2 2006.161.07:43:12.27#ibcon#read 6, iclass 6, count 2 2006.161.07:43:12.27#ibcon#end of sib2, iclass 6, count 2 2006.161.07:43:12.27#ibcon#*mode == 0, iclass 6, count 2 2006.161.07:43:12.27#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.07:43:12.27#ibcon#[27=AT01-04\r\n] 2006.161.07:43:12.27#ibcon#*before write, iclass 6, count 2 2006.161.07:43:12.27#ibcon#enter sib2, iclass 6, count 2 2006.161.07:43:12.27#ibcon#flushed, iclass 6, count 2 2006.161.07:43:12.27#ibcon#about to write, iclass 6, count 2 2006.161.07:43:12.27#ibcon#wrote, iclass 6, count 2 2006.161.07:43:12.27#ibcon#about to read 3, iclass 6, count 2 2006.161.07:43:12.30#ibcon#read 3, iclass 6, count 2 2006.161.07:43:12.30#ibcon#about to read 4, iclass 6, count 2 2006.161.07:43:12.30#ibcon#read 4, iclass 6, count 2 2006.161.07:43:12.30#ibcon#about to read 5, iclass 6, count 2 2006.161.07:43:12.30#ibcon#read 5, iclass 6, count 2 2006.161.07:43:12.30#ibcon#about to read 6, iclass 6, count 2 2006.161.07:43:12.30#ibcon#read 6, iclass 6, count 2 2006.161.07:43:12.30#ibcon#end of sib2, iclass 6, count 2 2006.161.07:43:12.30#ibcon#*after write, iclass 6, count 2 2006.161.07:43:12.30#ibcon#*before return 0, iclass 6, count 2 2006.161.07:43:12.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:43:12.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:43:12.30#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.07:43:12.30#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:12.30#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:43:12.42#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:43:12.42#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:43:12.42#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:43:12.42#ibcon#first serial, iclass 6, count 0 2006.161.07:43:12.42#ibcon#enter sib2, iclass 6, count 0 2006.161.07:43:12.42#ibcon#flushed, iclass 6, count 0 2006.161.07:43:12.42#ibcon#about to write, iclass 6, count 0 2006.161.07:43:12.42#ibcon#wrote, iclass 6, count 0 2006.161.07:43:12.42#ibcon#about to read 3, iclass 6, count 0 2006.161.07:43:12.44#ibcon#read 3, iclass 6, count 0 2006.161.07:43:12.44#ibcon#about to read 4, iclass 6, count 0 2006.161.07:43:12.44#ibcon#read 4, iclass 6, count 0 2006.161.07:43:12.44#ibcon#about to read 5, iclass 6, count 0 2006.161.07:43:12.44#ibcon#read 5, iclass 6, count 0 2006.161.07:43:12.44#ibcon#about to read 6, iclass 6, count 0 2006.161.07:43:12.44#ibcon#read 6, iclass 6, count 0 2006.161.07:43:12.44#ibcon#end of sib2, iclass 6, count 0 2006.161.07:43:12.44#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:43:12.44#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:43:12.44#ibcon#[27=USB\r\n] 2006.161.07:43:12.44#ibcon#*before write, iclass 6, count 0 2006.161.07:43:12.44#ibcon#enter sib2, iclass 6, count 0 2006.161.07:43:12.44#ibcon#flushed, iclass 6, count 0 2006.161.07:43:12.44#ibcon#about to write, iclass 6, count 0 2006.161.07:43:12.44#ibcon#wrote, iclass 6, count 0 2006.161.07:43:12.44#ibcon#about to read 3, iclass 6, count 0 2006.161.07:43:12.47#ibcon#read 3, iclass 6, count 0 2006.161.07:43:12.47#ibcon#about to read 4, iclass 6, count 0 2006.161.07:43:12.47#ibcon#read 4, iclass 6, count 0 2006.161.07:43:12.47#ibcon#about to read 5, iclass 6, count 0 2006.161.07:43:12.47#ibcon#read 5, iclass 6, count 0 2006.161.07:43:12.47#ibcon#about to read 6, iclass 6, count 0 2006.161.07:43:12.47#ibcon#read 6, iclass 6, count 0 2006.161.07:43:12.47#ibcon#end of sib2, iclass 6, count 0 2006.161.07:43:12.47#ibcon#*after write, iclass 6, count 0 2006.161.07:43:12.47#ibcon#*before return 0, iclass 6, count 0 2006.161.07:43:12.47#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:43:12.47#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:43:12.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:43:12.47#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:43:12.47$vc4f8/vblo=2,640.99 2006.161.07:43:12.47#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:43:12.47#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:43:12.47#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:12.47#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:12.47#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:12.47#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:12.47#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:43:12.47#ibcon#first serial, iclass 10, count 0 2006.161.07:43:12.47#ibcon#enter sib2, iclass 10, count 0 2006.161.07:43:12.47#ibcon#flushed, iclass 10, count 0 2006.161.07:43:12.47#ibcon#about to write, iclass 10, count 0 2006.161.07:43:12.47#ibcon#wrote, iclass 10, count 0 2006.161.07:43:12.47#ibcon#about to read 3, iclass 10, count 0 2006.161.07:43:12.49#ibcon#read 3, iclass 10, count 0 2006.161.07:43:12.49#ibcon#about to read 4, iclass 10, count 0 2006.161.07:43:12.49#ibcon#read 4, iclass 10, count 0 2006.161.07:43:12.49#ibcon#about to read 5, iclass 10, count 0 2006.161.07:43:12.49#ibcon#read 5, iclass 10, count 0 2006.161.07:43:12.49#ibcon#about to read 6, iclass 10, count 0 2006.161.07:43:12.49#ibcon#read 6, iclass 10, count 0 2006.161.07:43:12.49#ibcon#end of sib2, iclass 10, count 0 2006.161.07:43:12.49#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:43:12.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:43:12.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:43:12.49#ibcon#*before write, iclass 10, count 0 2006.161.07:43:12.49#ibcon#enter sib2, iclass 10, count 0 2006.161.07:43:12.49#ibcon#flushed, iclass 10, count 0 2006.161.07:43:12.49#ibcon#about to write, iclass 10, count 0 2006.161.07:43:12.49#ibcon#wrote, iclass 10, count 0 2006.161.07:43:12.49#ibcon#about to read 3, iclass 10, count 0 2006.161.07:43:12.53#ibcon#read 3, iclass 10, count 0 2006.161.07:43:12.53#ibcon#about to read 4, iclass 10, count 0 2006.161.07:43:12.53#ibcon#read 4, iclass 10, count 0 2006.161.07:43:12.53#ibcon#about to read 5, iclass 10, count 0 2006.161.07:43:12.53#ibcon#read 5, iclass 10, count 0 2006.161.07:43:12.53#ibcon#about to read 6, iclass 10, count 0 2006.161.07:43:12.53#ibcon#read 6, iclass 10, count 0 2006.161.07:43:12.53#ibcon#end of sib2, iclass 10, count 0 2006.161.07:43:12.53#ibcon#*after write, iclass 10, count 0 2006.161.07:43:12.53#ibcon#*before return 0, iclass 10, count 0 2006.161.07:43:12.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:12.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:43:12.53#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:43:12.53#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:43:12.53$vc4f8/vb=2,4 2006.161.07:43:12.53#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.07:43:12.53#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.07:43:12.53#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:12.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:12.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:12.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:12.59#ibcon#enter wrdev, iclass 12, count 2 2006.161.07:43:12.59#ibcon#first serial, iclass 12, count 2 2006.161.07:43:12.59#ibcon#enter sib2, iclass 12, count 2 2006.161.07:43:12.59#ibcon#flushed, iclass 12, count 2 2006.161.07:43:12.59#ibcon#about to write, iclass 12, count 2 2006.161.07:43:12.59#ibcon#wrote, iclass 12, count 2 2006.161.07:43:12.59#ibcon#about to read 3, iclass 12, count 2 2006.161.07:43:12.61#ibcon#read 3, iclass 12, count 2 2006.161.07:43:12.61#ibcon#about to read 4, iclass 12, count 2 2006.161.07:43:12.61#ibcon#read 4, iclass 12, count 2 2006.161.07:43:12.61#ibcon#about to read 5, iclass 12, count 2 2006.161.07:43:12.61#ibcon#read 5, iclass 12, count 2 2006.161.07:43:12.61#ibcon#about to read 6, iclass 12, count 2 2006.161.07:43:12.61#ibcon#read 6, iclass 12, count 2 2006.161.07:43:12.61#ibcon#end of sib2, iclass 12, count 2 2006.161.07:43:12.61#ibcon#*mode == 0, iclass 12, count 2 2006.161.07:43:12.61#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.07:43:12.61#ibcon#[27=AT02-04\r\n] 2006.161.07:43:12.61#ibcon#*before write, iclass 12, count 2 2006.161.07:43:12.61#ibcon#enter sib2, iclass 12, count 2 2006.161.07:43:12.61#ibcon#flushed, iclass 12, count 2 2006.161.07:43:12.61#ibcon#about to write, iclass 12, count 2 2006.161.07:43:12.61#ibcon#wrote, iclass 12, count 2 2006.161.07:43:12.61#ibcon#about to read 3, iclass 12, count 2 2006.161.07:43:12.64#ibcon#read 3, iclass 12, count 2 2006.161.07:43:12.64#ibcon#about to read 4, iclass 12, count 2 2006.161.07:43:12.64#ibcon#read 4, iclass 12, count 2 2006.161.07:43:12.64#ibcon#about to read 5, iclass 12, count 2 2006.161.07:43:12.64#ibcon#read 5, iclass 12, count 2 2006.161.07:43:12.64#ibcon#about to read 6, iclass 12, count 2 2006.161.07:43:12.64#ibcon#read 6, iclass 12, count 2 2006.161.07:43:12.64#ibcon#end of sib2, iclass 12, count 2 2006.161.07:43:12.64#ibcon#*after write, iclass 12, count 2 2006.161.07:43:12.64#ibcon#*before return 0, iclass 12, count 2 2006.161.07:43:12.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:12.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:43:12.64#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.07:43:12.64#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:12.64#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:12.76#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:12.76#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:12.76#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:43:12.76#ibcon#first serial, iclass 12, count 0 2006.161.07:43:12.76#ibcon#enter sib2, iclass 12, count 0 2006.161.07:43:12.76#ibcon#flushed, iclass 12, count 0 2006.161.07:43:12.76#ibcon#about to write, iclass 12, count 0 2006.161.07:43:12.76#ibcon#wrote, iclass 12, count 0 2006.161.07:43:12.76#ibcon#about to read 3, iclass 12, count 0 2006.161.07:43:12.78#ibcon#read 3, iclass 12, count 0 2006.161.07:43:12.78#ibcon#about to read 4, iclass 12, count 0 2006.161.07:43:12.78#ibcon#read 4, iclass 12, count 0 2006.161.07:43:12.78#ibcon#about to read 5, iclass 12, count 0 2006.161.07:43:12.78#ibcon#read 5, iclass 12, count 0 2006.161.07:43:12.78#ibcon#about to read 6, iclass 12, count 0 2006.161.07:43:12.78#ibcon#read 6, iclass 12, count 0 2006.161.07:43:12.78#ibcon#end of sib2, iclass 12, count 0 2006.161.07:43:12.78#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:43:12.78#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:43:12.78#ibcon#[27=USB\r\n] 2006.161.07:43:12.78#ibcon#*before write, iclass 12, count 0 2006.161.07:43:12.78#ibcon#enter sib2, iclass 12, count 0 2006.161.07:43:12.78#ibcon#flushed, iclass 12, count 0 2006.161.07:43:12.78#ibcon#about to write, iclass 12, count 0 2006.161.07:43:12.78#ibcon#wrote, iclass 12, count 0 2006.161.07:43:12.78#ibcon#about to read 3, iclass 12, count 0 2006.161.07:43:12.81#ibcon#read 3, iclass 12, count 0 2006.161.07:43:12.81#ibcon#about to read 4, iclass 12, count 0 2006.161.07:43:12.81#ibcon#read 4, iclass 12, count 0 2006.161.07:43:12.81#ibcon#about to read 5, iclass 12, count 0 2006.161.07:43:12.81#ibcon#read 5, iclass 12, count 0 2006.161.07:43:12.81#ibcon#about to read 6, iclass 12, count 0 2006.161.07:43:12.81#ibcon#read 6, iclass 12, count 0 2006.161.07:43:12.81#ibcon#end of sib2, iclass 12, count 0 2006.161.07:43:12.81#ibcon#*after write, iclass 12, count 0 2006.161.07:43:12.81#ibcon#*before return 0, iclass 12, count 0 2006.161.07:43:12.81#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:12.81#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:43:12.81#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:43:12.81#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:43:12.81$vc4f8/vblo=3,656.99 2006.161.07:43:12.81#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.07:43:12.81#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.07:43:12.81#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:12.81#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:12.81#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:12.81#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:12.81#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:43:12.81#ibcon#first serial, iclass 14, count 0 2006.161.07:43:12.81#ibcon#enter sib2, iclass 14, count 0 2006.161.07:43:12.81#ibcon#flushed, iclass 14, count 0 2006.161.07:43:12.81#ibcon#about to write, iclass 14, count 0 2006.161.07:43:12.81#ibcon#wrote, iclass 14, count 0 2006.161.07:43:12.81#ibcon#about to read 3, iclass 14, count 0 2006.161.07:43:12.83#ibcon#read 3, iclass 14, count 0 2006.161.07:43:12.83#ibcon#about to read 4, iclass 14, count 0 2006.161.07:43:12.83#ibcon#read 4, iclass 14, count 0 2006.161.07:43:12.83#ibcon#about to read 5, iclass 14, count 0 2006.161.07:43:12.83#ibcon#read 5, iclass 14, count 0 2006.161.07:43:12.83#ibcon#about to read 6, iclass 14, count 0 2006.161.07:43:12.83#ibcon#read 6, iclass 14, count 0 2006.161.07:43:12.83#ibcon#end of sib2, iclass 14, count 0 2006.161.07:43:12.83#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:43:12.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:43:12.83#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:43:12.83#ibcon#*before write, iclass 14, count 0 2006.161.07:43:12.83#ibcon#enter sib2, iclass 14, count 0 2006.161.07:43:12.83#ibcon#flushed, iclass 14, count 0 2006.161.07:43:12.83#ibcon#about to write, iclass 14, count 0 2006.161.07:43:12.83#ibcon#wrote, iclass 14, count 0 2006.161.07:43:12.83#ibcon#about to read 3, iclass 14, count 0 2006.161.07:43:12.87#ibcon#read 3, iclass 14, count 0 2006.161.07:43:12.87#ibcon#about to read 4, iclass 14, count 0 2006.161.07:43:12.87#ibcon#read 4, iclass 14, count 0 2006.161.07:43:12.87#ibcon#about to read 5, iclass 14, count 0 2006.161.07:43:12.87#ibcon#read 5, iclass 14, count 0 2006.161.07:43:12.87#ibcon#about to read 6, iclass 14, count 0 2006.161.07:43:12.87#ibcon#read 6, iclass 14, count 0 2006.161.07:43:12.87#ibcon#end of sib2, iclass 14, count 0 2006.161.07:43:12.87#ibcon#*after write, iclass 14, count 0 2006.161.07:43:12.87#ibcon#*before return 0, iclass 14, count 0 2006.161.07:43:12.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:12.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:43:12.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:43:12.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:43:12.87$vc4f8/vb=3,4 2006.161.07:43:12.87#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.07:43:12.87#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.07:43:12.87#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:12.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:12.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:12.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:12.93#ibcon#enter wrdev, iclass 16, count 2 2006.161.07:43:12.93#ibcon#first serial, iclass 16, count 2 2006.161.07:43:12.93#ibcon#enter sib2, iclass 16, count 2 2006.161.07:43:12.93#ibcon#flushed, iclass 16, count 2 2006.161.07:43:12.93#ibcon#about to write, iclass 16, count 2 2006.161.07:43:12.93#ibcon#wrote, iclass 16, count 2 2006.161.07:43:12.93#ibcon#about to read 3, iclass 16, count 2 2006.161.07:43:12.95#ibcon#read 3, iclass 16, count 2 2006.161.07:43:12.95#ibcon#about to read 4, iclass 16, count 2 2006.161.07:43:12.95#ibcon#read 4, iclass 16, count 2 2006.161.07:43:12.95#ibcon#about to read 5, iclass 16, count 2 2006.161.07:43:12.95#ibcon#read 5, iclass 16, count 2 2006.161.07:43:12.95#ibcon#about to read 6, iclass 16, count 2 2006.161.07:43:12.95#ibcon#read 6, iclass 16, count 2 2006.161.07:43:12.95#ibcon#end of sib2, iclass 16, count 2 2006.161.07:43:12.95#ibcon#*mode == 0, iclass 16, count 2 2006.161.07:43:12.95#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.07:43:12.95#ibcon#[27=AT03-04\r\n] 2006.161.07:43:12.95#ibcon#*before write, iclass 16, count 2 2006.161.07:43:12.95#ibcon#enter sib2, iclass 16, count 2 2006.161.07:43:12.95#ibcon#flushed, iclass 16, count 2 2006.161.07:43:12.95#ibcon#about to write, iclass 16, count 2 2006.161.07:43:12.95#ibcon#wrote, iclass 16, count 2 2006.161.07:43:12.95#ibcon#about to read 3, iclass 16, count 2 2006.161.07:43:12.98#ibcon#read 3, iclass 16, count 2 2006.161.07:43:12.98#ibcon#about to read 4, iclass 16, count 2 2006.161.07:43:12.98#ibcon#read 4, iclass 16, count 2 2006.161.07:43:12.98#ibcon#about to read 5, iclass 16, count 2 2006.161.07:43:12.98#ibcon#read 5, iclass 16, count 2 2006.161.07:43:12.98#ibcon#about to read 6, iclass 16, count 2 2006.161.07:43:12.98#ibcon#read 6, iclass 16, count 2 2006.161.07:43:12.98#ibcon#end of sib2, iclass 16, count 2 2006.161.07:43:12.98#ibcon#*after write, iclass 16, count 2 2006.161.07:43:12.98#ibcon#*before return 0, iclass 16, count 2 2006.161.07:43:12.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:12.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:43:12.98#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.07:43:12.98#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:12.98#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:13.10#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:13.10#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:13.10#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:43:13.10#ibcon#first serial, iclass 16, count 0 2006.161.07:43:13.10#ibcon#enter sib2, iclass 16, count 0 2006.161.07:43:13.10#ibcon#flushed, iclass 16, count 0 2006.161.07:43:13.10#ibcon#about to write, iclass 16, count 0 2006.161.07:43:13.10#ibcon#wrote, iclass 16, count 0 2006.161.07:43:13.10#ibcon#about to read 3, iclass 16, count 0 2006.161.07:43:13.12#ibcon#read 3, iclass 16, count 0 2006.161.07:43:13.12#ibcon#about to read 4, iclass 16, count 0 2006.161.07:43:13.12#ibcon#read 4, iclass 16, count 0 2006.161.07:43:13.12#ibcon#about to read 5, iclass 16, count 0 2006.161.07:43:13.12#ibcon#read 5, iclass 16, count 0 2006.161.07:43:13.12#ibcon#about to read 6, iclass 16, count 0 2006.161.07:43:13.12#ibcon#read 6, iclass 16, count 0 2006.161.07:43:13.12#ibcon#end of sib2, iclass 16, count 0 2006.161.07:43:13.12#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:43:13.12#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:43:13.12#ibcon#[27=USB\r\n] 2006.161.07:43:13.12#ibcon#*before write, iclass 16, count 0 2006.161.07:43:13.12#ibcon#enter sib2, iclass 16, count 0 2006.161.07:43:13.12#ibcon#flushed, iclass 16, count 0 2006.161.07:43:13.12#ibcon#about to write, iclass 16, count 0 2006.161.07:43:13.12#ibcon#wrote, iclass 16, count 0 2006.161.07:43:13.12#ibcon#about to read 3, iclass 16, count 0 2006.161.07:43:13.15#ibcon#read 3, iclass 16, count 0 2006.161.07:43:13.15#ibcon#about to read 4, iclass 16, count 0 2006.161.07:43:13.15#ibcon#read 4, iclass 16, count 0 2006.161.07:43:13.15#ibcon#about to read 5, iclass 16, count 0 2006.161.07:43:13.15#ibcon#read 5, iclass 16, count 0 2006.161.07:43:13.15#ibcon#about to read 6, iclass 16, count 0 2006.161.07:43:13.15#ibcon#read 6, iclass 16, count 0 2006.161.07:43:13.15#ibcon#end of sib2, iclass 16, count 0 2006.161.07:43:13.15#ibcon#*after write, iclass 16, count 0 2006.161.07:43:13.15#ibcon#*before return 0, iclass 16, count 0 2006.161.07:43:13.15#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:13.15#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:43:13.15#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:43:13.15#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:43:13.15$vc4f8/vblo=4,712.99 2006.161.07:43:13.15#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.07:43:13.15#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.07:43:13.15#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:13.15#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:13.15#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:13.15#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:13.15#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:43:13.15#ibcon#first serial, iclass 18, count 0 2006.161.07:43:13.15#ibcon#enter sib2, iclass 18, count 0 2006.161.07:43:13.15#ibcon#flushed, iclass 18, count 0 2006.161.07:43:13.15#ibcon#about to write, iclass 18, count 0 2006.161.07:43:13.15#ibcon#wrote, iclass 18, count 0 2006.161.07:43:13.15#ibcon#about to read 3, iclass 18, count 0 2006.161.07:43:13.17#ibcon#read 3, iclass 18, count 0 2006.161.07:43:13.17#ibcon#about to read 4, iclass 18, count 0 2006.161.07:43:13.17#ibcon#read 4, iclass 18, count 0 2006.161.07:43:13.17#ibcon#about to read 5, iclass 18, count 0 2006.161.07:43:13.17#ibcon#read 5, iclass 18, count 0 2006.161.07:43:13.17#ibcon#about to read 6, iclass 18, count 0 2006.161.07:43:13.17#ibcon#read 6, iclass 18, count 0 2006.161.07:43:13.17#ibcon#end of sib2, iclass 18, count 0 2006.161.07:43:13.17#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:43:13.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:43:13.17#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:43:13.17#ibcon#*before write, iclass 18, count 0 2006.161.07:43:13.17#ibcon#enter sib2, iclass 18, count 0 2006.161.07:43:13.17#ibcon#flushed, iclass 18, count 0 2006.161.07:43:13.17#ibcon#about to write, iclass 18, count 0 2006.161.07:43:13.17#ibcon#wrote, iclass 18, count 0 2006.161.07:43:13.17#ibcon#about to read 3, iclass 18, count 0 2006.161.07:43:13.21#ibcon#read 3, iclass 18, count 0 2006.161.07:43:13.21#ibcon#about to read 4, iclass 18, count 0 2006.161.07:43:13.21#ibcon#read 4, iclass 18, count 0 2006.161.07:43:13.21#ibcon#about to read 5, iclass 18, count 0 2006.161.07:43:13.21#ibcon#read 5, iclass 18, count 0 2006.161.07:43:13.21#ibcon#about to read 6, iclass 18, count 0 2006.161.07:43:13.21#ibcon#read 6, iclass 18, count 0 2006.161.07:43:13.21#ibcon#end of sib2, iclass 18, count 0 2006.161.07:43:13.21#ibcon#*after write, iclass 18, count 0 2006.161.07:43:13.21#ibcon#*before return 0, iclass 18, count 0 2006.161.07:43:13.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:13.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:43:13.21#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:43:13.21#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:43:13.21$vc4f8/vb=4,4 2006.161.07:43:13.21#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.07:43:13.21#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.07:43:13.21#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:13.21#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:13.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:13.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:13.27#ibcon#enter wrdev, iclass 20, count 2 2006.161.07:43:13.27#ibcon#first serial, iclass 20, count 2 2006.161.07:43:13.27#ibcon#enter sib2, iclass 20, count 2 2006.161.07:43:13.27#ibcon#flushed, iclass 20, count 2 2006.161.07:43:13.27#ibcon#about to write, iclass 20, count 2 2006.161.07:43:13.27#ibcon#wrote, iclass 20, count 2 2006.161.07:43:13.27#ibcon#about to read 3, iclass 20, count 2 2006.161.07:43:13.29#ibcon#read 3, iclass 20, count 2 2006.161.07:43:13.29#ibcon#about to read 4, iclass 20, count 2 2006.161.07:43:13.29#ibcon#read 4, iclass 20, count 2 2006.161.07:43:13.29#ibcon#about to read 5, iclass 20, count 2 2006.161.07:43:13.29#ibcon#read 5, iclass 20, count 2 2006.161.07:43:13.29#ibcon#about to read 6, iclass 20, count 2 2006.161.07:43:13.29#ibcon#read 6, iclass 20, count 2 2006.161.07:43:13.29#ibcon#end of sib2, iclass 20, count 2 2006.161.07:43:13.29#ibcon#*mode == 0, iclass 20, count 2 2006.161.07:43:13.29#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.07:43:13.29#ibcon#[27=AT04-04\r\n] 2006.161.07:43:13.29#ibcon#*before write, iclass 20, count 2 2006.161.07:43:13.29#ibcon#enter sib2, iclass 20, count 2 2006.161.07:43:13.29#ibcon#flushed, iclass 20, count 2 2006.161.07:43:13.29#ibcon#about to write, iclass 20, count 2 2006.161.07:43:13.29#ibcon#wrote, iclass 20, count 2 2006.161.07:43:13.29#ibcon#about to read 3, iclass 20, count 2 2006.161.07:43:13.32#ibcon#read 3, iclass 20, count 2 2006.161.07:43:13.32#ibcon#about to read 4, iclass 20, count 2 2006.161.07:43:13.32#ibcon#read 4, iclass 20, count 2 2006.161.07:43:13.32#ibcon#about to read 5, iclass 20, count 2 2006.161.07:43:13.32#ibcon#read 5, iclass 20, count 2 2006.161.07:43:13.32#ibcon#about to read 6, iclass 20, count 2 2006.161.07:43:13.32#ibcon#read 6, iclass 20, count 2 2006.161.07:43:13.32#ibcon#end of sib2, iclass 20, count 2 2006.161.07:43:13.32#ibcon#*after write, iclass 20, count 2 2006.161.07:43:13.32#ibcon#*before return 0, iclass 20, count 2 2006.161.07:43:13.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:13.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:43:13.32#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.07:43:13.32#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:13.32#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:13.44#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:13.44#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:13.44#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:43:13.44#ibcon#first serial, iclass 20, count 0 2006.161.07:43:13.44#ibcon#enter sib2, iclass 20, count 0 2006.161.07:43:13.44#ibcon#flushed, iclass 20, count 0 2006.161.07:43:13.44#ibcon#about to write, iclass 20, count 0 2006.161.07:43:13.44#ibcon#wrote, iclass 20, count 0 2006.161.07:43:13.44#ibcon#about to read 3, iclass 20, count 0 2006.161.07:43:13.46#ibcon#read 3, iclass 20, count 0 2006.161.07:43:13.46#ibcon#about to read 4, iclass 20, count 0 2006.161.07:43:13.46#ibcon#read 4, iclass 20, count 0 2006.161.07:43:13.46#ibcon#about to read 5, iclass 20, count 0 2006.161.07:43:13.46#ibcon#read 5, iclass 20, count 0 2006.161.07:43:13.46#ibcon#about to read 6, iclass 20, count 0 2006.161.07:43:13.46#ibcon#read 6, iclass 20, count 0 2006.161.07:43:13.46#ibcon#end of sib2, iclass 20, count 0 2006.161.07:43:13.46#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:43:13.46#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:43:13.46#ibcon#[27=USB\r\n] 2006.161.07:43:13.46#ibcon#*before write, iclass 20, count 0 2006.161.07:43:13.46#ibcon#enter sib2, iclass 20, count 0 2006.161.07:43:13.46#ibcon#flushed, iclass 20, count 0 2006.161.07:43:13.46#ibcon#about to write, iclass 20, count 0 2006.161.07:43:13.46#ibcon#wrote, iclass 20, count 0 2006.161.07:43:13.46#ibcon#about to read 3, iclass 20, count 0 2006.161.07:43:13.49#ibcon#read 3, iclass 20, count 0 2006.161.07:43:13.49#ibcon#about to read 4, iclass 20, count 0 2006.161.07:43:13.49#ibcon#read 4, iclass 20, count 0 2006.161.07:43:13.49#ibcon#about to read 5, iclass 20, count 0 2006.161.07:43:13.49#ibcon#read 5, iclass 20, count 0 2006.161.07:43:13.49#ibcon#about to read 6, iclass 20, count 0 2006.161.07:43:13.49#ibcon#read 6, iclass 20, count 0 2006.161.07:43:13.49#ibcon#end of sib2, iclass 20, count 0 2006.161.07:43:13.49#ibcon#*after write, iclass 20, count 0 2006.161.07:43:13.49#ibcon#*before return 0, iclass 20, count 0 2006.161.07:43:13.49#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:13.49#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:43:13.49#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:43:13.49#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:43:13.49$vc4f8/vblo=5,744.99 2006.161.07:43:13.49#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.07:43:13.49#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.07:43:13.49#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:13.49#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:13.49#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:13.49#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:13.49#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:43:13.49#ibcon#first serial, iclass 22, count 0 2006.161.07:43:13.49#ibcon#enter sib2, iclass 22, count 0 2006.161.07:43:13.49#ibcon#flushed, iclass 22, count 0 2006.161.07:43:13.49#ibcon#about to write, iclass 22, count 0 2006.161.07:43:13.49#ibcon#wrote, iclass 22, count 0 2006.161.07:43:13.49#ibcon#about to read 3, iclass 22, count 0 2006.161.07:43:13.51#ibcon#read 3, iclass 22, count 0 2006.161.07:43:13.51#ibcon#about to read 4, iclass 22, count 0 2006.161.07:43:13.51#ibcon#read 4, iclass 22, count 0 2006.161.07:43:13.51#ibcon#about to read 5, iclass 22, count 0 2006.161.07:43:13.51#ibcon#read 5, iclass 22, count 0 2006.161.07:43:13.51#ibcon#about to read 6, iclass 22, count 0 2006.161.07:43:13.51#ibcon#read 6, iclass 22, count 0 2006.161.07:43:13.51#ibcon#end of sib2, iclass 22, count 0 2006.161.07:43:13.51#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:43:13.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:43:13.51#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:43:13.51#ibcon#*before write, iclass 22, count 0 2006.161.07:43:13.51#ibcon#enter sib2, iclass 22, count 0 2006.161.07:43:13.51#ibcon#flushed, iclass 22, count 0 2006.161.07:43:13.51#ibcon#about to write, iclass 22, count 0 2006.161.07:43:13.51#ibcon#wrote, iclass 22, count 0 2006.161.07:43:13.51#ibcon#about to read 3, iclass 22, count 0 2006.161.07:43:13.55#ibcon#read 3, iclass 22, count 0 2006.161.07:43:13.55#ibcon#about to read 4, iclass 22, count 0 2006.161.07:43:13.55#ibcon#read 4, iclass 22, count 0 2006.161.07:43:13.55#ibcon#about to read 5, iclass 22, count 0 2006.161.07:43:13.55#ibcon#read 5, iclass 22, count 0 2006.161.07:43:13.55#ibcon#about to read 6, iclass 22, count 0 2006.161.07:43:13.55#ibcon#read 6, iclass 22, count 0 2006.161.07:43:13.55#ibcon#end of sib2, iclass 22, count 0 2006.161.07:43:13.55#ibcon#*after write, iclass 22, count 0 2006.161.07:43:13.55#ibcon#*before return 0, iclass 22, count 0 2006.161.07:43:13.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:13.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:43:13.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:43:13.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:43:13.55$vc4f8/vb=5,4 2006.161.07:43:13.55#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.07:43:13.55#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.07:43:13.55#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:13.55#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:13.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:13.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:13.61#ibcon#enter wrdev, iclass 24, count 2 2006.161.07:43:13.61#ibcon#first serial, iclass 24, count 2 2006.161.07:43:13.61#ibcon#enter sib2, iclass 24, count 2 2006.161.07:43:13.61#ibcon#flushed, iclass 24, count 2 2006.161.07:43:13.61#ibcon#about to write, iclass 24, count 2 2006.161.07:43:13.61#ibcon#wrote, iclass 24, count 2 2006.161.07:43:13.61#ibcon#about to read 3, iclass 24, count 2 2006.161.07:43:13.64#ibcon#read 3, iclass 24, count 2 2006.161.07:43:13.64#ibcon#about to read 4, iclass 24, count 2 2006.161.07:43:13.64#ibcon#read 4, iclass 24, count 2 2006.161.07:43:13.64#ibcon#about to read 5, iclass 24, count 2 2006.161.07:43:13.64#ibcon#read 5, iclass 24, count 2 2006.161.07:43:13.64#ibcon#about to read 6, iclass 24, count 2 2006.161.07:43:13.64#ibcon#read 6, iclass 24, count 2 2006.161.07:43:13.64#ibcon#end of sib2, iclass 24, count 2 2006.161.07:43:13.64#ibcon#*mode == 0, iclass 24, count 2 2006.161.07:43:13.64#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.07:43:13.64#ibcon#[27=AT05-04\r\n] 2006.161.07:43:13.64#ibcon#*before write, iclass 24, count 2 2006.161.07:43:13.64#ibcon#enter sib2, iclass 24, count 2 2006.161.07:43:13.64#ibcon#flushed, iclass 24, count 2 2006.161.07:43:13.64#ibcon#about to write, iclass 24, count 2 2006.161.07:43:13.64#ibcon#wrote, iclass 24, count 2 2006.161.07:43:13.64#ibcon#about to read 3, iclass 24, count 2 2006.161.07:43:13.67#ibcon#read 3, iclass 24, count 2 2006.161.07:43:13.67#ibcon#about to read 4, iclass 24, count 2 2006.161.07:43:13.67#ibcon#read 4, iclass 24, count 2 2006.161.07:43:13.67#ibcon#about to read 5, iclass 24, count 2 2006.161.07:43:13.67#ibcon#read 5, iclass 24, count 2 2006.161.07:43:13.67#ibcon#about to read 6, iclass 24, count 2 2006.161.07:43:13.67#ibcon#read 6, iclass 24, count 2 2006.161.07:43:13.67#ibcon#end of sib2, iclass 24, count 2 2006.161.07:43:13.67#ibcon#*after write, iclass 24, count 2 2006.161.07:43:13.67#ibcon#*before return 0, iclass 24, count 2 2006.161.07:43:13.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:13.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:43:13.67#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.07:43:13.67#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:13.67#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:13.79#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:13.79#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:13.79#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:43:13.79#ibcon#first serial, iclass 24, count 0 2006.161.07:43:13.79#ibcon#enter sib2, iclass 24, count 0 2006.161.07:43:13.79#ibcon#flushed, iclass 24, count 0 2006.161.07:43:13.79#ibcon#about to write, iclass 24, count 0 2006.161.07:43:13.79#ibcon#wrote, iclass 24, count 0 2006.161.07:43:13.79#ibcon#about to read 3, iclass 24, count 0 2006.161.07:43:13.81#ibcon#read 3, iclass 24, count 0 2006.161.07:43:13.81#ibcon#about to read 4, iclass 24, count 0 2006.161.07:43:13.81#ibcon#read 4, iclass 24, count 0 2006.161.07:43:13.81#ibcon#about to read 5, iclass 24, count 0 2006.161.07:43:13.81#ibcon#read 5, iclass 24, count 0 2006.161.07:43:13.81#ibcon#about to read 6, iclass 24, count 0 2006.161.07:43:13.81#ibcon#read 6, iclass 24, count 0 2006.161.07:43:13.81#ibcon#end of sib2, iclass 24, count 0 2006.161.07:43:13.81#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:43:13.81#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:43:13.81#ibcon#[27=USB\r\n] 2006.161.07:43:13.81#ibcon#*before write, iclass 24, count 0 2006.161.07:43:13.81#ibcon#enter sib2, iclass 24, count 0 2006.161.07:43:13.81#ibcon#flushed, iclass 24, count 0 2006.161.07:43:13.81#ibcon#about to write, iclass 24, count 0 2006.161.07:43:13.81#ibcon#wrote, iclass 24, count 0 2006.161.07:43:13.81#ibcon#about to read 3, iclass 24, count 0 2006.161.07:43:13.84#ibcon#read 3, iclass 24, count 0 2006.161.07:43:13.84#ibcon#about to read 4, iclass 24, count 0 2006.161.07:43:13.84#ibcon#read 4, iclass 24, count 0 2006.161.07:43:13.84#ibcon#about to read 5, iclass 24, count 0 2006.161.07:43:13.84#ibcon#read 5, iclass 24, count 0 2006.161.07:43:13.84#ibcon#about to read 6, iclass 24, count 0 2006.161.07:43:13.84#ibcon#read 6, iclass 24, count 0 2006.161.07:43:13.84#ibcon#end of sib2, iclass 24, count 0 2006.161.07:43:13.84#ibcon#*after write, iclass 24, count 0 2006.161.07:43:13.84#ibcon#*before return 0, iclass 24, count 0 2006.161.07:43:13.84#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:13.84#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:43:13.84#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:43:13.84#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:43:13.84$vc4f8/vblo=6,752.99 2006.161.07:43:13.84#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:43:13.84#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:43:13.84#ibcon#ireg 17 cls_cnt 0 2006.161.07:43:13.84#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:13.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:13.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:13.84#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:43:13.84#ibcon#first serial, iclass 26, count 0 2006.161.07:43:13.84#ibcon#enter sib2, iclass 26, count 0 2006.161.07:43:13.84#ibcon#flushed, iclass 26, count 0 2006.161.07:43:13.84#ibcon#about to write, iclass 26, count 0 2006.161.07:43:13.84#ibcon#wrote, iclass 26, count 0 2006.161.07:43:13.84#ibcon#about to read 3, iclass 26, count 0 2006.161.07:43:13.86#ibcon#read 3, iclass 26, count 0 2006.161.07:43:13.86#ibcon#about to read 4, iclass 26, count 0 2006.161.07:43:13.86#ibcon#read 4, iclass 26, count 0 2006.161.07:43:13.86#ibcon#about to read 5, iclass 26, count 0 2006.161.07:43:13.86#ibcon#read 5, iclass 26, count 0 2006.161.07:43:13.86#ibcon#about to read 6, iclass 26, count 0 2006.161.07:43:13.86#ibcon#read 6, iclass 26, count 0 2006.161.07:43:13.86#ibcon#end of sib2, iclass 26, count 0 2006.161.07:43:13.86#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:43:13.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:43:13.86#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:43:13.86#ibcon#*before write, iclass 26, count 0 2006.161.07:43:13.86#ibcon#enter sib2, iclass 26, count 0 2006.161.07:43:13.86#ibcon#flushed, iclass 26, count 0 2006.161.07:43:13.86#ibcon#about to write, iclass 26, count 0 2006.161.07:43:13.86#ibcon#wrote, iclass 26, count 0 2006.161.07:43:13.86#ibcon#about to read 3, iclass 26, count 0 2006.161.07:43:13.90#ibcon#read 3, iclass 26, count 0 2006.161.07:43:13.90#ibcon#about to read 4, iclass 26, count 0 2006.161.07:43:13.90#ibcon#read 4, iclass 26, count 0 2006.161.07:43:13.90#ibcon#about to read 5, iclass 26, count 0 2006.161.07:43:13.90#ibcon#read 5, iclass 26, count 0 2006.161.07:43:13.90#ibcon#about to read 6, iclass 26, count 0 2006.161.07:43:13.90#ibcon#read 6, iclass 26, count 0 2006.161.07:43:13.90#ibcon#end of sib2, iclass 26, count 0 2006.161.07:43:13.90#ibcon#*after write, iclass 26, count 0 2006.161.07:43:13.90#ibcon#*before return 0, iclass 26, count 0 2006.161.07:43:13.90#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:13.90#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:43:13.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:43:13.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:43:13.90$vc4f8/vb=6,4 2006.161.07:43:13.90#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.07:43:13.90#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.07:43:13.90#ibcon#ireg 11 cls_cnt 2 2006.161.07:43:13.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:13.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:13.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:13.96#ibcon#enter wrdev, iclass 28, count 2 2006.161.07:43:13.96#ibcon#first serial, iclass 28, count 2 2006.161.07:43:13.96#ibcon#enter sib2, iclass 28, count 2 2006.161.07:43:13.96#ibcon#flushed, iclass 28, count 2 2006.161.07:43:13.96#ibcon#about to write, iclass 28, count 2 2006.161.07:43:13.96#ibcon#wrote, iclass 28, count 2 2006.161.07:43:13.96#ibcon#about to read 3, iclass 28, count 2 2006.161.07:43:13.98#ibcon#read 3, iclass 28, count 2 2006.161.07:43:13.98#ibcon#about to read 4, iclass 28, count 2 2006.161.07:43:13.98#ibcon#read 4, iclass 28, count 2 2006.161.07:43:13.98#ibcon#about to read 5, iclass 28, count 2 2006.161.07:43:13.98#ibcon#read 5, iclass 28, count 2 2006.161.07:43:13.98#ibcon#about to read 6, iclass 28, count 2 2006.161.07:43:13.98#ibcon#read 6, iclass 28, count 2 2006.161.07:43:13.98#ibcon#end of sib2, iclass 28, count 2 2006.161.07:43:13.98#ibcon#*mode == 0, iclass 28, count 2 2006.161.07:43:13.98#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.07:43:13.98#ibcon#[27=AT06-04\r\n] 2006.161.07:43:13.98#ibcon#*before write, iclass 28, count 2 2006.161.07:43:13.98#ibcon#enter sib2, iclass 28, count 2 2006.161.07:43:13.98#ibcon#flushed, iclass 28, count 2 2006.161.07:43:13.98#ibcon#about to write, iclass 28, count 2 2006.161.07:43:13.98#ibcon#wrote, iclass 28, count 2 2006.161.07:43:13.98#ibcon#about to read 3, iclass 28, count 2 2006.161.07:43:14.01#ibcon#read 3, iclass 28, count 2 2006.161.07:43:14.01#ibcon#about to read 4, iclass 28, count 2 2006.161.07:43:14.01#ibcon#read 4, iclass 28, count 2 2006.161.07:43:14.01#ibcon#about to read 5, iclass 28, count 2 2006.161.07:43:14.01#ibcon#read 5, iclass 28, count 2 2006.161.07:43:14.01#ibcon#about to read 6, iclass 28, count 2 2006.161.07:43:14.01#ibcon#read 6, iclass 28, count 2 2006.161.07:43:14.01#ibcon#end of sib2, iclass 28, count 2 2006.161.07:43:14.01#ibcon#*after write, iclass 28, count 2 2006.161.07:43:14.01#ibcon#*before return 0, iclass 28, count 2 2006.161.07:43:14.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:14.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:43:14.01#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.07:43:14.01#ibcon#ireg 7 cls_cnt 0 2006.161.07:43:14.01#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:14.13#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:14.13#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:14.13#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:43:14.13#ibcon#first serial, iclass 28, count 0 2006.161.07:43:14.13#ibcon#enter sib2, iclass 28, count 0 2006.161.07:43:14.13#ibcon#flushed, iclass 28, count 0 2006.161.07:43:14.13#ibcon#about to write, iclass 28, count 0 2006.161.07:43:14.13#ibcon#wrote, iclass 28, count 0 2006.161.07:43:14.13#ibcon#about to read 3, iclass 28, count 0 2006.161.07:43:14.15#ibcon#read 3, iclass 28, count 0 2006.161.07:43:14.15#ibcon#about to read 4, iclass 28, count 0 2006.161.07:43:14.15#ibcon#read 4, iclass 28, count 0 2006.161.07:43:14.15#ibcon#about to read 5, iclass 28, count 0 2006.161.07:43:14.15#ibcon#read 5, iclass 28, count 0 2006.161.07:43:14.15#ibcon#about to read 6, iclass 28, count 0 2006.161.07:43:14.15#ibcon#read 6, iclass 28, count 0 2006.161.07:43:14.15#ibcon#end of sib2, iclass 28, count 0 2006.161.07:43:14.15#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:43:14.15#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:43:14.15#ibcon#[27=USB\r\n] 2006.161.07:43:14.15#ibcon#*before write, iclass 28, count 0 2006.161.07:43:14.15#ibcon#enter sib2, iclass 28, count 0 2006.161.07:43:14.15#ibcon#flushed, iclass 28, count 0 2006.161.07:43:14.15#ibcon#about to write, iclass 28, count 0 2006.161.07:43:14.15#ibcon#wrote, iclass 28, count 0 2006.161.07:43:14.15#ibcon#about to read 3, iclass 28, count 0 2006.161.07:43:14.18#ibcon#read 3, iclass 28, count 0 2006.161.07:43:14.18#ibcon#about to read 4, iclass 28, count 0 2006.161.07:43:14.18#ibcon#read 4, iclass 28, count 0 2006.161.07:43:14.18#ibcon#about to read 5, iclass 28, count 0 2006.161.07:43:14.18#ibcon#read 5, iclass 28, count 0 2006.161.07:43:14.18#ibcon#about to read 6, iclass 28, count 0 2006.161.07:43:14.18#ibcon#read 6, iclass 28, count 0 2006.161.07:43:14.18#ibcon#end of sib2, iclass 28, count 0 2006.161.07:43:14.18#ibcon#*after write, iclass 28, count 0 2006.161.07:43:14.18#ibcon#*before return 0, iclass 28, count 0 2006.161.07:43:14.18#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:14.18#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:43:14.18#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:43:14.18#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:43:14.18$vc4f8/vabw=wide 2006.161.07:43:14.18#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:43:14.18#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:43:14.18#ibcon#ireg 8 cls_cnt 0 2006.161.07:43:14.18#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:14.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:14.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:14.18#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:43:14.18#ibcon#first serial, iclass 30, count 0 2006.161.07:43:14.18#ibcon#enter sib2, iclass 30, count 0 2006.161.07:43:14.18#ibcon#flushed, iclass 30, count 0 2006.161.07:43:14.18#ibcon#about to write, iclass 30, count 0 2006.161.07:43:14.18#ibcon#wrote, iclass 30, count 0 2006.161.07:43:14.18#ibcon#about to read 3, iclass 30, count 0 2006.161.07:43:14.20#ibcon#read 3, iclass 30, count 0 2006.161.07:43:14.20#ibcon#about to read 4, iclass 30, count 0 2006.161.07:43:14.20#ibcon#read 4, iclass 30, count 0 2006.161.07:43:14.20#ibcon#about to read 5, iclass 30, count 0 2006.161.07:43:14.20#ibcon#read 5, iclass 30, count 0 2006.161.07:43:14.20#ibcon#about to read 6, iclass 30, count 0 2006.161.07:43:14.20#ibcon#read 6, iclass 30, count 0 2006.161.07:43:14.20#ibcon#end of sib2, iclass 30, count 0 2006.161.07:43:14.20#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:43:14.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:43:14.20#ibcon#[25=BW32\r\n] 2006.161.07:43:14.20#ibcon#*before write, iclass 30, count 0 2006.161.07:43:14.20#ibcon#enter sib2, iclass 30, count 0 2006.161.07:43:14.20#ibcon#flushed, iclass 30, count 0 2006.161.07:43:14.20#ibcon#about to write, iclass 30, count 0 2006.161.07:43:14.20#ibcon#wrote, iclass 30, count 0 2006.161.07:43:14.20#ibcon#about to read 3, iclass 30, count 0 2006.161.07:43:14.23#ibcon#read 3, iclass 30, count 0 2006.161.07:43:14.23#ibcon#about to read 4, iclass 30, count 0 2006.161.07:43:14.23#ibcon#read 4, iclass 30, count 0 2006.161.07:43:14.23#ibcon#about to read 5, iclass 30, count 0 2006.161.07:43:14.23#ibcon#read 5, iclass 30, count 0 2006.161.07:43:14.23#ibcon#about to read 6, iclass 30, count 0 2006.161.07:43:14.23#ibcon#read 6, iclass 30, count 0 2006.161.07:43:14.23#ibcon#end of sib2, iclass 30, count 0 2006.161.07:43:14.23#ibcon#*after write, iclass 30, count 0 2006.161.07:43:14.23#ibcon#*before return 0, iclass 30, count 0 2006.161.07:43:14.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:14.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:43:14.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:43:14.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:43:14.23$vc4f8/vbbw=wide 2006.161.07:43:14.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.07:43:14.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.07:43:14.23#ibcon#ireg 8 cls_cnt 0 2006.161.07:43:14.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:43:14.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:43:14.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:43:14.30#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:43:14.30#ibcon#first serial, iclass 32, count 0 2006.161.07:43:14.30#ibcon#enter sib2, iclass 32, count 0 2006.161.07:43:14.30#ibcon#flushed, iclass 32, count 0 2006.161.07:43:14.30#ibcon#about to write, iclass 32, count 0 2006.161.07:43:14.30#ibcon#wrote, iclass 32, count 0 2006.161.07:43:14.30#ibcon#about to read 3, iclass 32, count 0 2006.161.07:43:14.33#ibcon#read 3, iclass 32, count 0 2006.161.07:43:14.33#ibcon#about to read 4, iclass 32, count 0 2006.161.07:43:14.33#ibcon#read 4, iclass 32, count 0 2006.161.07:43:14.33#ibcon#about to read 5, iclass 32, count 0 2006.161.07:43:14.33#ibcon#read 5, iclass 32, count 0 2006.161.07:43:14.33#ibcon#about to read 6, iclass 32, count 0 2006.161.07:43:14.33#ibcon#read 6, iclass 32, count 0 2006.161.07:43:14.33#ibcon#end of sib2, iclass 32, count 0 2006.161.07:43:14.33#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:43:14.33#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:43:14.33#ibcon#[27=BW32\r\n] 2006.161.07:43:14.33#ibcon#*before write, iclass 32, count 0 2006.161.07:43:14.33#ibcon#enter sib2, iclass 32, count 0 2006.161.07:43:14.33#ibcon#flushed, iclass 32, count 0 2006.161.07:43:14.33#ibcon#about to write, iclass 32, count 0 2006.161.07:43:14.33#ibcon#wrote, iclass 32, count 0 2006.161.07:43:14.33#ibcon#about to read 3, iclass 32, count 0 2006.161.07:43:14.36#ibcon#read 3, iclass 32, count 0 2006.161.07:43:14.36#ibcon#about to read 4, iclass 32, count 0 2006.161.07:43:14.36#ibcon#read 4, iclass 32, count 0 2006.161.07:43:14.36#ibcon#about to read 5, iclass 32, count 0 2006.161.07:43:14.36#ibcon#read 5, iclass 32, count 0 2006.161.07:43:14.36#ibcon#about to read 6, iclass 32, count 0 2006.161.07:43:14.36#ibcon#read 6, iclass 32, count 0 2006.161.07:43:14.36#ibcon#end of sib2, iclass 32, count 0 2006.161.07:43:14.36#ibcon#*after write, iclass 32, count 0 2006.161.07:43:14.36#ibcon#*before return 0, iclass 32, count 0 2006.161.07:43:14.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:43:14.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:43:14.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:43:14.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:43:14.36$4f8m12a/ifd4f 2006.161.07:43:14.36$ifd4f/lo= 2006.161.07:43:14.36$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:43:14.36$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:43:14.36$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:43:14.36$ifd4f/patch= 2006.161.07:43:14.36$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:43:14.36$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:43:14.36$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:43:14.36$4f8m12a/"form=m,16.000,1:2 2006.161.07:43:14.36$4f8m12a/"tpicd 2006.161.07:43:14.36$4f8m12a/echo=off 2006.161.07:43:14.36$4f8m12a/xlog=off 2006.161.07:43:14.36:!2006.161.07:43:40 2006.161.07:43:23.14#trakl#Source acquired 2006.161.07:43:24.14#flagr#flagr/antenna,acquired 2006.161.07:43:40.00:preob 2006.161.07:43:40.14/onsource/TRACKING 2006.161.07:43:40.14:!2006.161.07:43:50 2006.161.07:43:50.00:data_valid=on 2006.161.07:43:50.00:midob 2006.161.07:43:51.14/onsource/TRACKING 2006.161.07:43:51.14/wx/24.11,1002.0,84 2006.161.07:43:51.20/cable/+6.4991E-03 2006.161.07:43:52.29/va/01,08,usb,yes,28,30 2006.161.07:43:52.29/va/02,07,usb,yes,28,30 2006.161.07:43:52.29/va/03,06,usb,yes,30,30 2006.161.07:43:52.29/va/04,07,usb,yes,29,31 2006.161.07:43:52.29/va/05,07,usb,yes,29,31 2006.161.07:43:52.29/va/06,06,usb,yes,28,28 2006.161.07:43:52.29/va/07,06,usb,yes,28,28 2006.161.07:43:52.29/va/08,07,usb,yes,27,27 2006.161.07:43:52.52/valo/01,532.99,yes,locked 2006.161.07:43:52.52/valo/02,572.99,yes,locked 2006.161.07:43:52.52/valo/03,672.99,yes,locked 2006.161.07:43:52.52/valo/04,832.99,yes,locked 2006.161.07:43:52.52/valo/05,652.99,yes,locked 2006.161.07:43:52.52/valo/06,772.99,yes,locked 2006.161.07:43:52.52/valo/07,832.99,yes,locked 2006.161.07:43:52.52/valo/08,852.99,yes,locked 2006.161.07:43:53.61/vb/01,04,usb,yes,29,27 2006.161.07:43:53.61/vb/02,04,usb,yes,30,32 2006.161.07:43:53.61/vb/03,04,usb,yes,27,30 2006.161.07:43:53.61/vb/04,04,usb,yes,28,28 2006.161.07:43:53.61/vb/05,04,usb,yes,26,30 2006.161.07:43:53.61/vb/06,04,usb,yes,27,30 2006.161.07:43:53.61/vb/07,04,usb,yes,29,29 2006.161.07:43:53.61/vb/08,04,usb,yes,27,30 2006.161.07:43:53.85/vblo/01,632.99,yes,locked 2006.161.07:43:53.85/vblo/02,640.99,yes,locked 2006.161.07:43:53.85/vblo/03,656.99,yes,locked 2006.161.07:43:53.85/vblo/04,712.99,yes,locked 2006.161.07:43:53.85/vblo/05,744.99,yes,locked 2006.161.07:43:53.85/vblo/06,752.99,yes,locked 2006.161.07:43:53.85/vblo/07,734.99,yes,locked 2006.161.07:43:53.85/vblo/08,744.99,yes,locked 2006.161.07:43:54.00/vabw/8 2006.161.07:43:54.15/vbbw/8 2006.161.07:43:54.24/xfe/off,on,15.2 2006.161.07:43:54.63/ifatt/23,28,28,28 2006.161.07:43:55.08/fmout-gps/S +4.48E-07 2006.161.07:43:55.12:!2006.161.07:44:50 2006.161.07:44:50.00:data_valid=off 2006.161.07:44:50.00:postob 2006.161.07:44:50.17/cable/+6.5001E-03 2006.161.07:44:50.17/wx/24.10,1002.0,85 2006.161.07:44:51.07/fmout-gps/S +4.47E-07 2006.161.07:44:51.07:scan_name=161-0745,k06161,60 2006.161.07:44:51.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.161.07:44:51.14#flagr#flagr/antenna,new-source 2006.161.07:44:52.14:checkk5 2006.161.07:44:52.54/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:44:52.97/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:44:53.38/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:44:53.89/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:44:54.29/chk_obsdata//k5ts1/T1610743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:44:55.11/chk_obsdata//k5ts2/T1610743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:44:55.52/chk_obsdata//k5ts3/T1610743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:44:55.97/chk_obsdata//k5ts4/T1610743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:44:57.02/k5log//k5ts1_log_newline 2006.161.07:44:57.72/k5log//k5ts2_log_newline 2006.161.07:44:58.78/k5log//k5ts3_log_newline 2006.161.07:45:00.05/k5log//k5ts4_log_newline 2006.161.07:45:00.11/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:45:00.11:4f8m12a=1 2006.161.07:45:00.11$4f8m12a/echo=on 2006.161.07:45:00.11$4f8m12a/pcalon 2006.161.07:45:00.11$pcalon/"no phase cal control is implemented here 2006.161.07:45:00.11$4f8m12a/"tpicd=stop 2006.161.07:45:00.11$4f8m12a/vc4f8 2006.161.07:45:00.11$vc4f8/valo=1,532.99 2006.161.07:45:00.12#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.07:45:00.12#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.07:45:00.12#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:00.12#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:00.12#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:00.12#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:00.12#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:45:00.12#ibcon#first serial, iclass 39, count 0 2006.161.07:45:00.12#ibcon#enter sib2, iclass 39, count 0 2006.161.07:45:00.12#ibcon#flushed, iclass 39, count 0 2006.161.07:45:00.12#ibcon#about to write, iclass 39, count 0 2006.161.07:45:00.12#ibcon#wrote, iclass 39, count 0 2006.161.07:45:00.12#ibcon#about to read 3, iclass 39, count 0 2006.161.07:45:00.14#ibcon#read 3, iclass 39, count 0 2006.161.07:45:00.14#ibcon#about to read 4, iclass 39, count 0 2006.161.07:45:00.14#ibcon#read 4, iclass 39, count 0 2006.161.07:45:00.14#ibcon#about to read 5, iclass 39, count 0 2006.161.07:45:00.14#ibcon#read 5, iclass 39, count 0 2006.161.07:45:00.14#ibcon#about to read 6, iclass 39, count 0 2006.161.07:45:00.14#ibcon#read 6, iclass 39, count 0 2006.161.07:45:00.14#ibcon#end of sib2, iclass 39, count 0 2006.161.07:45:00.14#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:45:00.14#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:45:00.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:45:00.14#ibcon#*before write, iclass 39, count 0 2006.161.07:45:00.14#ibcon#enter sib2, iclass 39, count 0 2006.161.07:45:00.14#ibcon#flushed, iclass 39, count 0 2006.161.07:45:00.14#ibcon#about to write, iclass 39, count 0 2006.161.07:45:00.14#ibcon#wrote, iclass 39, count 0 2006.161.07:45:00.14#ibcon#about to read 3, iclass 39, count 0 2006.161.07:45:00.19#ibcon#read 3, iclass 39, count 0 2006.161.07:45:00.19#ibcon#about to read 4, iclass 39, count 0 2006.161.07:45:00.19#ibcon#read 4, iclass 39, count 0 2006.161.07:45:00.19#ibcon#about to read 5, iclass 39, count 0 2006.161.07:45:00.19#ibcon#read 5, iclass 39, count 0 2006.161.07:45:00.19#ibcon#about to read 6, iclass 39, count 0 2006.161.07:45:00.19#ibcon#read 6, iclass 39, count 0 2006.161.07:45:00.19#ibcon#end of sib2, iclass 39, count 0 2006.161.07:45:00.19#ibcon#*after write, iclass 39, count 0 2006.161.07:45:00.19#ibcon#*before return 0, iclass 39, count 0 2006.161.07:45:00.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:00.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:00.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:45:00.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:45:00.19$vc4f8/va=1,8 2006.161.07:45:00.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.07:45:00.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.07:45:00.19#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:00.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:00.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:00.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:00.19#ibcon#enter wrdev, iclass 3, count 2 2006.161.07:45:00.19#ibcon#first serial, iclass 3, count 2 2006.161.07:45:00.19#ibcon#enter sib2, iclass 3, count 2 2006.161.07:45:00.19#ibcon#flushed, iclass 3, count 2 2006.161.07:45:00.19#ibcon#about to write, iclass 3, count 2 2006.161.07:45:00.19#ibcon#wrote, iclass 3, count 2 2006.161.07:45:00.19#ibcon#about to read 3, iclass 3, count 2 2006.161.07:45:00.21#ibcon#read 3, iclass 3, count 2 2006.161.07:45:00.21#ibcon#about to read 4, iclass 3, count 2 2006.161.07:45:00.21#ibcon#read 4, iclass 3, count 2 2006.161.07:45:00.21#ibcon#about to read 5, iclass 3, count 2 2006.161.07:45:00.21#ibcon#read 5, iclass 3, count 2 2006.161.07:45:00.21#ibcon#about to read 6, iclass 3, count 2 2006.161.07:45:00.21#ibcon#read 6, iclass 3, count 2 2006.161.07:45:00.21#ibcon#end of sib2, iclass 3, count 2 2006.161.07:45:00.21#ibcon#*mode == 0, iclass 3, count 2 2006.161.07:45:00.21#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.07:45:00.21#ibcon#[25=AT01-08\r\n] 2006.161.07:45:00.21#ibcon#*before write, iclass 3, count 2 2006.161.07:45:00.21#ibcon#enter sib2, iclass 3, count 2 2006.161.07:45:00.21#ibcon#flushed, iclass 3, count 2 2006.161.07:45:00.21#ibcon#about to write, iclass 3, count 2 2006.161.07:45:00.21#ibcon#wrote, iclass 3, count 2 2006.161.07:45:00.21#ibcon#about to read 3, iclass 3, count 2 2006.161.07:45:00.24#ibcon#read 3, iclass 3, count 2 2006.161.07:45:00.24#ibcon#about to read 4, iclass 3, count 2 2006.161.07:45:00.24#ibcon#read 4, iclass 3, count 2 2006.161.07:45:00.24#ibcon#about to read 5, iclass 3, count 2 2006.161.07:45:00.24#ibcon#read 5, iclass 3, count 2 2006.161.07:45:00.24#ibcon#about to read 6, iclass 3, count 2 2006.161.07:45:00.24#ibcon#read 6, iclass 3, count 2 2006.161.07:45:00.24#ibcon#end of sib2, iclass 3, count 2 2006.161.07:45:00.24#ibcon#*after write, iclass 3, count 2 2006.161.07:45:00.24#ibcon#*before return 0, iclass 3, count 2 2006.161.07:45:00.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:00.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:00.24#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.07:45:00.24#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:00.24#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:00.36#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:00.36#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:00.36#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:45:00.36#ibcon#first serial, iclass 3, count 0 2006.161.07:45:00.36#ibcon#enter sib2, iclass 3, count 0 2006.161.07:45:00.36#ibcon#flushed, iclass 3, count 0 2006.161.07:45:00.36#ibcon#about to write, iclass 3, count 0 2006.161.07:45:00.36#ibcon#wrote, iclass 3, count 0 2006.161.07:45:00.36#ibcon#about to read 3, iclass 3, count 0 2006.161.07:45:00.38#ibcon#read 3, iclass 3, count 0 2006.161.07:45:00.38#ibcon#about to read 4, iclass 3, count 0 2006.161.07:45:00.38#ibcon#read 4, iclass 3, count 0 2006.161.07:45:00.38#ibcon#about to read 5, iclass 3, count 0 2006.161.07:45:00.38#ibcon#read 5, iclass 3, count 0 2006.161.07:45:00.38#ibcon#about to read 6, iclass 3, count 0 2006.161.07:45:00.38#ibcon#read 6, iclass 3, count 0 2006.161.07:45:00.38#ibcon#end of sib2, iclass 3, count 0 2006.161.07:45:00.38#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:45:00.38#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:45:00.38#ibcon#[25=USB\r\n] 2006.161.07:45:00.38#ibcon#*before write, iclass 3, count 0 2006.161.07:45:00.38#ibcon#enter sib2, iclass 3, count 0 2006.161.07:45:00.38#ibcon#flushed, iclass 3, count 0 2006.161.07:45:00.38#ibcon#about to write, iclass 3, count 0 2006.161.07:45:00.38#ibcon#wrote, iclass 3, count 0 2006.161.07:45:00.38#ibcon#about to read 3, iclass 3, count 0 2006.161.07:45:00.41#ibcon#read 3, iclass 3, count 0 2006.161.07:45:00.41#ibcon#about to read 4, iclass 3, count 0 2006.161.07:45:00.41#ibcon#read 4, iclass 3, count 0 2006.161.07:45:00.41#ibcon#about to read 5, iclass 3, count 0 2006.161.07:45:00.41#ibcon#read 5, iclass 3, count 0 2006.161.07:45:00.41#ibcon#about to read 6, iclass 3, count 0 2006.161.07:45:00.41#ibcon#read 6, iclass 3, count 0 2006.161.07:45:00.41#ibcon#end of sib2, iclass 3, count 0 2006.161.07:45:00.41#ibcon#*after write, iclass 3, count 0 2006.161.07:45:00.41#ibcon#*before return 0, iclass 3, count 0 2006.161.07:45:00.41#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:00.41#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:00.41#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:45:00.41#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:45:00.41$vc4f8/valo=2,572.99 2006.161.07:45:00.41#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.07:45:00.41#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.07:45:00.41#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:00.41#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:00.41#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:00.41#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:00.41#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:45:00.41#ibcon#first serial, iclass 5, count 0 2006.161.07:45:00.41#ibcon#enter sib2, iclass 5, count 0 2006.161.07:45:00.41#ibcon#flushed, iclass 5, count 0 2006.161.07:45:00.41#ibcon#about to write, iclass 5, count 0 2006.161.07:45:00.41#ibcon#wrote, iclass 5, count 0 2006.161.07:45:00.41#ibcon#about to read 3, iclass 5, count 0 2006.161.07:45:00.43#ibcon#read 3, iclass 5, count 0 2006.161.07:45:00.43#ibcon#about to read 4, iclass 5, count 0 2006.161.07:45:00.43#ibcon#read 4, iclass 5, count 0 2006.161.07:45:00.43#ibcon#about to read 5, iclass 5, count 0 2006.161.07:45:00.43#ibcon#read 5, iclass 5, count 0 2006.161.07:45:00.43#ibcon#about to read 6, iclass 5, count 0 2006.161.07:45:00.43#ibcon#read 6, iclass 5, count 0 2006.161.07:45:00.43#ibcon#end of sib2, iclass 5, count 0 2006.161.07:45:00.43#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:45:00.43#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:45:00.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:45:00.43#ibcon#*before write, iclass 5, count 0 2006.161.07:45:00.43#ibcon#enter sib2, iclass 5, count 0 2006.161.07:45:00.43#ibcon#flushed, iclass 5, count 0 2006.161.07:45:00.43#ibcon#about to write, iclass 5, count 0 2006.161.07:45:00.43#ibcon#wrote, iclass 5, count 0 2006.161.07:45:00.43#ibcon#about to read 3, iclass 5, count 0 2006.161.07:45:00.47#ibcon#read 3, iclass 5, count 0 2006.161.07:45:00.47#ibcon#about to read 4, iclass 5, count 0 2006.161.07:45:00.47#ibcon#read 4, iclass 5, count 0 2006.161.07:45:00.47#ibcon#about to read 5, iclass 5, count 0 2006.161.07:45:00.47#ibcon#read 5, iclass 5, count 0 2006.161.07:45:00.47#ibcon#about to read 6, iclass 5, count 0 2006.161.07:45:00.47#ibcon#read 6, iclass 5, count 0 2006.161.07:45:00.47#ibcon#end of sib2, iclass 5, count 0 2006.161.07:45:00.47#ibcon#*after write, iclass 5, count 0 2006.161.07:45:00.47#ibcon#*before return 0, iclass 5, count 0 2006.161.07:45:00.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:00.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:00.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:45:00.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:45:00.47$vc4f8/va=2,7 2006.161.07:45:00.47#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.07:45:00.47#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.07:45:00.47#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:00.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:00.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:00.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:00.53#ibcon#enter wrdev, iclass 7, count 2 2006.161.07:45:00.53#ibcon#first serial, iclass 7, count 2 2006.161.07:45:00.53#ibcon#enter sib2, iclass 7, count 2 2006.161.07:45:00.53#ibcon#flushed, iclass 7, count 2 2006.161.07:45:00.53#ibcon#about to write, iclass 7, count 2 2006.161.07:45:00.53#ibcon#wrote, iclass 7, count 2 2006.161.07:45:00.53#ibcon#about to read 3, iclass 7, count 2 2006.161.07:45:00.56#ibcon#read 3, iclass 7, count 2 2006.161.07:45:00.56#ibcon#about to read 4, iclass 7, count 2 2006.161.07:45:00.56#ibcon#read 4, iclass 7, count 2 2006.161.07:45:00.56#ibcon#about to read 5, iclass 7, count 2 2006.161.07:45:00.56#ibcon#read 5, iclass 7, count 2 2006.161.07:45:00.56#ibcon#about to read 6, iclass 7, count 2 2006.161.07:45:00.56#ibcon#read 6, iclass 7, count 2 2006.161.07:45:00.56#ibcon#end of sib2, iclass 7, count 2 2006.161.07:45:00.56#ibcon#*mode == 0, iclass 7, count 2 2006.161.07:45:00.56#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.07:45:00.56#ibcon#[25=AT02-07\r\n] 2006.161.07:45:00.56#ibcon#*before write, iclass 7, count 2 2006.161.07:45:00.56#ibcon#enter sib2, iclass 7, count 2 2006.161.07:45:00.56#ibcon#flushed, iclass 7, count 2 2006.161.07:45:00.56#ibcon#about to write, iclass 7, count 2 2006.161.07:45:00.56#ibcon#wrote, iclass 7, count 2 2006.161.07:45:00.56#ibcon#about to read 3, iclass 7, count 2 2006.161.07:45:00.59#ibcon#read 3, iclass 7, count 2 2006.161.07:45:00.59#ibcon#about to read 4, iclass 7, count 2 2006.161.07:45:00.59#ibcon#read 4, iclass 7, count 2 2006.161.07:45:00.59#ibcon#about to read 5, iclass 7, count 2 2006.161.07:45:00.59#ibcon#read 5, iclass 7, count 2 2006.161.07:45:00.59#ibcon#about to read 6, iclass 7, count 2 2006.161.07:45:00.59#ibcon#read 6, iclass 7, count 2 2006.161.07:45:00.59#ibcon#end of sib2, iclass 7, count 2 2006.161.07:45:00.59#ibcon#*after write, iclass 7, count 2 2006.161.07:45:00.59#ibcon#*before return 0, iclass 7, count 2 2006.161.07:45:00.59#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:00.59#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:00.59#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.07:45:00.59#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:00.59#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:00.71#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:00.71#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:00.71#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:45:00.71#ibcon#first serial, iclass 7, count 0 2006.161.07:45:00.71#ibcon#enter sib2, iclass 7, count 0 2006.161.07:45:00.71#ibcon#flushed, iclass 7, count 0 2006.161.07:45:00.71#ibcon#about to write, iclass 7, count 0 2006.161.07:45:00.71#ibcon#wrote, iclass 7, count 0 2006.161.07:45:00.71#ibcon#about to read 3, iclass 7, count 0 2006.161.07:45:00.73#ibcon#read 3, iclass 7, count 0 2006.161.07:45:00.73#ibcon#about to read 4, iclass 7, count 0 2006.161.07:45:00.73#ibcon#read 4, iclass 7, count 0 2006.161.07:45:00.73#ibcon#about to read 5, iclass 7, count 0 2006.161.07:45:00.73#ibcon#read 5, iclass 7, count 0 2006.161.07:45:00.73#ibcon#about to read 6, iclass 7, count 0 2006.161.07:45:00.73#ibcon#read 6, iclass 7, count 0 2006.161.07:45:00.73#ibcon#end of sib2, iclass 7, count 0 2006.161.07:45:00.73#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:45:00.73#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:45:00.73#ibcon#[25=USB\r\n] 2006.161.07:45:00.73#ibcon#*before write, iclass 7, count 0 2006.161.07:45:00.73#ibcon#enter sib2, iclass 7, count 0 2006.161.07:45:00.73#ibcon#flushed, iclass 7, count 0 2006.161.07:45:00.73#ibcon#about to write, iclass 7, count 0 2006.161.07:45:00.73#ibcon#wrote, iclass 7, count 0 2006.161.07:45:00.73#ibcon#about to read 3, iclass 7, count 0 2006.161.07:45:00.76#ibcon#read 3, iclass 7, count 0 2006.161.07:45:00.76#ibcon#about to read 4, iclass 7, count 0 2006.161.07:45:00.76#ibcon#read 4, iclass 7, count 0 2006.161.07:45:00.76#ibcon#about to read 5, iclass 7, count 0 2006.161.07:45:00.76#ibcon#read 5, iclass 7, count 0 2006.161.07:45:00.76#ibcon#about to read 6, iclass 7, count 0 2006.161.07:45:00.76#ibcon#read 6, iclass 7, count 0 2006.161.07:45:00.76#ibcon#end of sib2, iclass 7, count 0 2006.161.07:45:00.76#ibcon#*after write, iclass 7, count 0 2006.161.07:45:00.76#ibcon#*before return 0, iclass 7, count 0 2006.161.07:45:00.76#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:00.76#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:00.76#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:45:00.76#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:45:00.76$vc4f8/valo=3,672.99 2006.161.07:45:00.76#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:45:00.76#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:45:00.76#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:00.76#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:00.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:00.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:00.76#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:45:00.76#ibcon#first serial, iclass 11, count 0 2006.161.07:45:00.76#ibcon#enter sib2, iclass 11, count 0 2006.161.07:45:00.76#ibcon#flushed, iclass 11, count 0 2006.161.07:45:00.76#ibcon#about to write, iclass 11, count 0 2006.161.07:45:00.76#ibcon#wrote, iclass 11, count 0 2006.161.07:45:00.76#ibcon#about to read 3, iclass 11, count 0 2006.161.07:45:00.79#ibcon#read 3, iclass 11, count 0 2006.161.07:45:00.79#ibcon#about to read 4, iclass 11, count 0 2006.161.07:45:00.79#ibcon#read 4, iclass 11, count 0 2006.161.07:45:00.79#ibcon#about to read 5, iclass 11, count 0 2006.161.07:45:00.79#ibcon#read 5, iclass 11, count 0 2006.161.07:45:00.79#ibcon#about to read 6, iclass 11, count 0 2006.161.07:45:00.79#ibcon#read 6, iclass 11, count 0 2006.161.07:45:00.79#ibcon#end of sib2, iclass 11, count 0 2006.161.07:45:00.79#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:45:00.79#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:45:00.79#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:45:00.79#ibcon#*before write, iclass 11, count 0 2006.161.07:45:00.79#ibcon#enter sib2, iclass 11, count 0 2006.161.07:45:00.79#ibcon#flushed, iclass 11, count 0 2006.161.07:45:00.79#ibcon#about to write, iclass 11, count 0 2006.161.07:45:00.79#ibcon#wrote, iclass 11, count 0 2006.161.07:45:00.79#ibcon#about to read 3, iclass 11, count 0 2006.161.07:45:00.83#ibcon#read 3, iclass 11, count 0 2006.161.07:45:00.83#ibcon#about to read 4, iclass 11, count 0 2006.161.07:45:00.83#ibcon#read 4, iclass 11, count 0 2006.161.07:45:00.83#ibcon#about to read 5, iclass 11, count 0 2006.161.07:45:00.83#ibcon#read 5, iclass 11, count 0 2006.161.07:45:00.83#ibcon#about to read 6, iclass 11, count 0 2006.161.07:45:00.83#ibcon#read 6, iclass 11, count 0 2006.161.07:45:00.83#ibcon#end of sib2, iclass 11, count 0 2006.161.07:45:00.83#ibcon#*after write, iclass 11, count 0 2006.161.07:45:00.83#ibcon#*before return 0, iclass 11, count 0 2006.161.07:45:00.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:00.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:00.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:45:00.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:45:00.83$vc4f8/va=3,6 2006.161.07:45:00.83#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:45:00.83#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:45:00.83#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:00.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:00.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:00.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:00.88#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:45:00.88#ibcon#first serial, iclass 13, count 2 2006.161.07:45:00.88#ibcon#enter sib2, iclass 13, count 2 2006.161.07:45:00.88#ibcon#flushed, iclass 13, count 2 2006.161.07:45:00.88#ibcon#about to write, iclass 13, count 2 2006.161.07:45:00.88#ibcon#wrote, iclass 13, count 2 2006.161.07:45:00.88#ibcon#about to read 3, iclass 13, count 2 2006.161.07:45:00.91#ibcon#read 3, iclass 13, count 2 2006.161.07:45:00.91#ibcon#about to read 4, iclass 13, count 2 2006.161.07:45:00.91#ibcon#read 4, iclass 13, count 2 2006.161.07:45:00.91#ibcon#about to read 5, iclass 13, count 2 2006.161.07:45:00.91#ibcon#read 5, iclass 13, count 2 2006.161.07:45:00.91#ibcon#about to read 6, iclass 13, count 2 2006.161.07:45:00.91#ibcon#read 6, iclass 13, count 2 2006.161.07:45:00.91#ibcon#end of sib2, iclass 13, count 2 2006.161.07:45:00.91#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:45:00.91#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:45:00.91#ibcon#[25=AT03-06\r\n] 2006.161.07:45:00.91#ibcon#*before write, iclass 13, count 2 2006.161.07:45:00.91#ibcon#enter sib2, iclass 13, count 2 2006.161.07:45:00.91#ibcon#flushed, iclass 13, count 2 2006.161.07:45:00.91#ibcon#about to write, iclass 13, count 2 2006.161.07:45:00.91#ibcon#wrote, iclass 13, count 2 2006.161.07:45:00.91#ibcon#about to read 3, iclass 13, count 2 2006.161.07:45:00.94#ibcon#read 3, iclass 13, count 2 2006.161.07:45:00.94#ibcon#about to read 4, iclass 13, count 2 2006.161.07:45:00.94#ibcon#read 4, iclass 13, count 2 2006.161.07:45:00.94#ibcon#about to read 5, iclass 13, count 2 2006.161.07:45:00.94#ibcon#read 5, iclass 13, count 2 2006.161.07:45:00.94#ibcon#about to read 6, iclass 13, count 2 2006.161.07:45:00.94#ibcon#read 6, iclass 13, count 2 2006.161.07:45:00.94#ibcon#end of sib2, iclass 13, count 2 2006.161.07:45:00.94#ibcon#*after write, iclass 13, count 2 2006.161.07:45:00.94#ibcon#*before return 0, iclass 13, count 2 2006.161.07:45:00.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:00.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:00.94#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:45:00.94#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:00.94#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:00.97#abcon#<5=/05 3.0 5.7 24.10 851002.1\r\n> 2006.161.07:45:00.99#abcon#{5=INTERFACE CLEAR} 2006.161.07:45:01.05#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:45:01.06#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:01.06#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:01.06#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:45:01.06#ibcon#first serial, iclass 13, count 0 2006.161.07:45:01.06#ibcon#enter sib2, iclass 13, count 0 2006.161.07:45:01.06#ibcon#flushed, iclass 13, count 0 2006.161.07:45:01.06#ibcon#about to write, iclass 13, count 0 2006.161.07:45:01.06#ibcon#wrote, iclass 13, count 0 2006.161.07:45:01.06#ibcon#about to read 3, iclass 13, count 0 2006.161.07:45:01.08#ibcon#read 3, iclass 13, count 0 2006.161.07:45:01.08#ibcon#about to read 4, iclass 13, count 0 2006.161.07:45:01.08#ibcon#read 4, iclass 13, count 0 2006.161.07:45:01.08#ibcon#about to read 5, iclass 13, count 0 2006.161.07:45:01.08#ibcon#read 5, iclass 13, count 0 2006.161.07:45:01.08#ibcon#about to read 6, iclass 13, count 0 2006.161.07:45:01.08#ibcon#read 6, iclass 13, count 0 2006.161.07:45:01.08#ibcon#end of sib2, iclass 13, count 0 2006.161.07:45:01.08#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:45:01.08#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:45:01.08#ibcon#[25=USB\r\n] 2006.161.07:45:01.08#ibcon#*before write, iclass 13, count 0 2006.161.07:45:01.08#ibcon#enter sib2, iclass 13, count 0 2006.161.07:45:01.08#ibcon#flushed, iclass 13, count 0 2006.161.07:45:01.08#ibcon#about to write, iclass 13, count 0 2006.161.07:45:01.08#ibcon#wrote, iclass 13, count 0 2006.161.07:45:01.08#ibcon#about to read 3, iclass 13, count 0 2006.161.07:45:01.11#ibcon#read 3, iclass 13, count 0 2006.161.07:45:01.11#ibcon#about to read 4, iclass 13, count 0 2006.161.07:45:01.11#ibcon#read 4, iclass 13, count 0 2006.161.07:45:01.11#ibcon#about to read 5, iclass 13, count 0 2006.161.07:45:01.11#ibcon#read 5, iclass 13, count 0 2006.161.07:45:01.11#ibcon#about to read 6, iclass 13, count 0 2006.161.07:45:01.11#ibcon#read 6, iclass 13, count 0 2006.161.07:45:01.11#ibcon#end of sib2, iclass 13, count 0 2006.161.07:45:01.11#ibcon#*after write, iclass 13, count 0 2006.161.07:45:01.11#ibcon#*before return 0, iclass 13, count 0 2006.161.07:45:01.11#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:01.11#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:01.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:45:01.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:45:01.11$vc4f8/valo=4,832.99 2006.161.07:45:01.11#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:45:01.11#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:45:01.11#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:01.11#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:01.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:01.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:01.11#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:45:01.11#ibcon#first serial, iclass 19, count 0 2006.161.07:45:01.11#ibcon#enter sib2, iclass 19, count 0 2006.161.07:45:01.11#ibcon#flushed, iclass 19, count 0 2006.161.07:45:01.11#ibcon#about to write, iclass 19, count 0 2006.161.07:45:01.11#ibcon#wrote, iclass 19, count 0 2006.161.07:45:01.11#ibcon#about to read 3, iclass 19, count 0 2006.161.07:45:01.13#ibcon#read 3, iclass 19, count 0 2006.161.07:45:01.13#ibcon#about to read 4, iclass 19, count 0 2006.161.07:45:01.13#ibcon#read 4, iclass 19, count 0 2006.161.07:45:01.13#ibcon#about to read 5, iclass 19, count 0 2006.161.07:45:01.13#ibcon#read 5, iclass 19, count 0 2006.161.07:45:01.13#ibcon#about to read 6, iclass 19, count 0 2006.161.07:45:01.13#ibcon#read 6, iclass 19, count 0 2006.161.07:45:01.13#ibcon#end of sib2, iclass 19, count 0 2006.161.07:45:01.13#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:45:01.13#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:45:01.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:45:01.13#ibcon#*before write, iclass 19, count 0 2006.161.07:45:01.13#ibcon#enter sib2, iclass 19, count 0 2006.161.07:45:01.13#ibcon#flushed, iclass 19, count 0 2006.161.07:45:01.13#ibcon#about to write, iclass 19, count 0 2006.161.07:45:01.13#ibcon#wrote, iclass 19, count 0 2006.161.07:45:01.13#ibcon#about to read 3, iclass 19, count 0 2006.161.07:45:01.17#ibcon#read 3, iclass 19, count 0 2006.161.07:45:01.17#ibcon#about to read 4, iclass 19, count 0 2006.161.07:45:01.17#ibcon#read 4, iclass 19, count 0 2006.161.07:45:01.17#ibcon#about to read 5, iclass 19, count 0 2006.161.07:45:01.17#ibcon#read 5, iclass 19, count 0 2006.161.07:45:01.17#ibcon#about to read 6, iclass 19, count 0 2006.161.07:45:01.17#ibcon#read 6, iclass 19, count 0 2006.161.07:45:01.17#ibcon#end of sib2, iclass 19, count 0 2006.161.07:45:01.17#ibcon#*after write, iclass 19, count 0 2006.161.07:45:01.17#ibcon#*before return 0, iclass 19, count 0 2006.161.07:45:01.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:01.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:01.17#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:45:01.17#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:45:01.17$vc4f8/va=4,7 2006.161.07:45:01.17#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:45:01.17#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:45:01.17#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:01.17#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:01.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:01.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:01.23#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:45:01.23#ibcon#first serial, iclass 21, count 2 2006.161.07:45:01.23#ibcon#enter sib2, iclass 21, count 2 2006.161.07:45:01.23#ibcon#flushed, iclass 21, count 2 2006.161.07:45:01.23#ibcon#about to write, iclass 21, count 2 2006.161.07:45:01.23#ibcon#wrote, iclass 21, count 2 2006.161.07:45:01.23#ibcon#about to read 3, iclass 21, count 2 2006.161.07:45:01.25#ibcon#read 3, iclass 21, count 2 2006.161.07:45:01.25#ibcon#about to read 4, iclass 21, count 2 2006.161.07:45:01.25#ibcon#read 4, iclass 21, count 2 2006.161.07:45:01.25#ibcon#about to read 5, iclass 21, count 2 2006.161.07:45:01.25#ibcon#read 5, iclass 21, count 2 2006.161.07:45:01.25#ibcon#about to read 6, iclass 21, count 2 2006.161.07:45:01.25#ibcon#read 6, iclass 21, count 2 2006.161.07:45:01.25#ibcon#end of sib2, iclass 21, count 2 2006.161.07:45:01.25#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:45:01.25#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:45:01.25#ibcon#[25=AT04-07\r\n] 2006.161.07:45:01.25#ibcon#*before write, iclass 21, count 2 2006.161.07:45:01.25#ibcon#enter sib2, iclass 21, count 2 2006.161.07:45:01.25#ibcon#flushed, iclass 21, count 2 2006.161.07:45:01.25#ibcon#about to write, iclass 21, count 2 2006.161.07:45:01.25#ibcon#wrote, iclass 21, count 2 2006.161.07:45:01.25#ibcon#about to read 3, iclass 21, count 2 2006.161.07:45:01.28#ibcon#read 3, iclass 21, count 2 2006.161.07:45:01.28#ibcon#about to read 4, iclass 21, count 2 2006.161.07:45:01.28#ibcon#read 4, iclass 21, count 2 2006.161.07:45:01.28#ibcon#about to read 5, iclass 21, count 2 2006.161.07:45:01.28#ibcon#read 5, iclass 21, count 2 2006.161.07:45:01.28#ibcon#about to read 6, iclass 21, count 2 2006.161.07:45:01.28#ibcon#read 6, iclass 21, count 2 2006.161.07:45:01.28#ibcon#end of sib2, iclass 21, count 2 2006.161.07:45:01.28#ibcon#*after write, iclass 21, count 2 2006.161.07:45:01.28#ibcon#*before return 0, iclass 21, count 2 2006.161.07:45:01.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:01.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:01.28#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:45:01.28#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:01.28#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:01.40#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:01.40#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:01.40#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:45:01.40#ibcon#first serial, iclass 21, count 0 2006.161.07:45:01.40#ibcon#enter sib2, iclass 21, count 0 2006.161.07:45:01.40#ibcon#flushed, iclass 21, count 0 2006.161.07:45:01.40#ibcon#about to write, iclass 21, count 0 2006.161.07:45:01.40#ibcon#wrote, iclass 21, count 0 2006.161.07:45:01.40#ibcon#about to read 3, iclass 21, count 0 2006.161.07:45:01.42#ibcon#read 3, iclass 21, count 0 2006.161.07:45:01.42#ibcon#about to read 4, iclass 21, count 0 2006.161.07:45:01.42#ibcon#read 4, iclass 21, count 0 2006.161.07:45:01.42#ibcon#about to read 5, iclass 21, count 0 2006.161.07:45:01.42#ibcon#read 5, iclass 21, count 0 2006.161.07:45:01.42#ibcon#about to read 6, iclass 21, count 0 2006.161.07:45:01.42#ibcon#read 6, iclass 21, count 0 2006.161.07:45:01.42#ibcon#end of sib2, iclass 21, count 0 2006.161.07:45:01.42#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:45:01.42#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:45:01.42#ibcon#[25=USB\r\n] 2006.161.07:45:01.42#ibcon#*before write, iclass 21, count 0 2006.161.07:45:01.42#ibcon#enter sib2, iclass 21, count 0 2006.161.07:45:01.42#ibcon#flushed, iclass 21, count 0 2006.161.07:45:01.42#ibcon#about to write, iclass 21, count 0 2006.161.07:45:01.42#ibcon#wrote, iclass 21, count 0 2006.161.07:45:01.42#ibcon#about to read 3, iclass 21, count 0 2006.161.07:45:01.45#ibcon#read 3, iclass 21, count 0 2006.161.07:45:01.45#ibcon#about to read 4, iclass 21, count 0 2006.161.07:45:01.45#ibcon#read 4, iclass 21, count 0 2006.161.07:45:01.45#ibcon#about to read 5, iclass 21, count 0 2006.161.07:45:01.45#ibcon#read 5, iclass 21, count 0 2006.161.07:45:01.45#ibcon#about to read 6, iclass 21, count 0 2006.161.07:45:01.45#ibcon#read 6, iclass 21, count 0 2006.161.07:45:01.45#ibcon#end of sib2, iclass 21, count 0 2006.161.07:45:01.45#ibcon#*after write, iclass 21, count 0 2006.161.07:45:01.45#ibcon#*before return 0, iclass 21, count 0 2006.161.07:45:01.45#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:01.45#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:01.45#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:45:01.45#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:45:01.45$vc4f8/valo=5,652.99 2006.161.07:45:01.45#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:45:01.45#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:45:01.45#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:01.45#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:01.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:01.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:01.45#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:45:01.45#ibcon#first serial, iclass 23, count 0 2006.161.07:45:01.45#ibcon#enter sib2, iclass 23, count 0 2006.161.07:45:01.45#ibcon#flushed, iclass 23, count 0 2006.161.07:45:01.45#ibcon#about to write, iclass 23, count 0 2006.161.07:45:01.45#ibcon#wrote, iclass 23, count 0 2006.161.07:45:01.45#ibcon#about to read 3, iclass 23, count 0 2006.161.07:45:01.47#ibcon#read 3, iclass 23, count 0 2006.161.07:45:01.47#ibcon#about to read 4, iclass 23, count 0 2006.161.07:45:01.47#ibcon#read 4, iclass 23, count 0 2006.161.07:45:01.47#ibcon#about to read 5, iclass 23, count 0 2006.161.07:45:01.47#ibcon#read 5, iclass 23, count 0 2006.161.07:45:01.47#ibcon#about to read 6, iclass 23, count 0 2006.161.07:45:01.47#ibcon#read 6, iclass 23, count 0 2006.161.07:45:01.47#ibcon#end of sib2, iclass 23, count 0 2006.161.07:45:01.47#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:45:01.47#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:45:01.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:45:01.47#ibcon#*before write, iclass 23, count 0 2006.161.07:45:01.47#ibcon#enter sib2, iclass 23, count 0 2006.161.07:45:01.47#ibcon#flushed, iclass 23, count 0 2006.161.07:45:01.47#ibcon#about to write, iclass 23, count 0 2006.161.07:45:01.47#ibcon#wrote, iclass 23, count 0 2006.161.07:45:01.47#ibcon#about to read 3, iclass 23, count 0 2006.161.07:45:01.51#ibcon#read 3, iclass 23, count 0 2006.161.07:45:01.51#ibcon#about to read 4, iclass 23, count 0 2006.161.07:45:01.51#ibcon#read 4, iclass 23, count 0 2006.161.07:45:01.51#ibcon#about to read 5, iclass 23, count 0 2006.161.07:45:01.51#ibcon#read 5, iclass 23, count 0 2006.161.07:45:01.51#ibcon#about to read 6, iclass 23, count 0 2006.161.07:45:01.51#ibcon#read 6, iclass 23, count 0 2006.161.07:45:01.51#ibcon#end of sib2, iclass 23, count 0 2006.161.07:45:01.51#ibcon#*after write, iclass 23, count 0 2006.161.07:45:01.51#ibcon#*before return 0, iclass 23, count 0 2006.161.07:45:01.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:01.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:01.51#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:45:01.51#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:45:01.51$vc4f8/va=5,7 2006.161.07:45:01.51#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:45:01.51#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:45:01.51#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:01.51#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:01.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:01.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:01.57#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:45:01.57#ibcon#first serial, iclass 25, count 2 2006.161.07:45:01.57#ibcon#enter sib2, iclass 25, count 2 2006.161.07:45:01.57#ibcon#flushed, iclass 25, count 2 2006.161.07:45:01.57#ibcon#about to write, iclass 25, count 2 2006.161.07:45:01.57#ibcon#wrote, iclass 25, count 2 2006.161.07:45:01.57#ibcon#about to read 3, iclass 25, count 2 2006.161.07:45:01.60#ibcon#read 3, iclass 25, count 2 2006.161.07:45:01.60#ibcon#about to read 4, iclass 25, count 2 2006.161.07:45:01.60#ibcon#read 4, iclass 25, count 2 2006.161.07:45:01.60#ibcon#about to read 5, iclass 25, count 2 2006.161.07:45:01.60#ibcon#read 5, iclass 25, count 2 2006.161.07:45:01.60#ibcon#about to read 6, iclass 25, count 2 2006.161.07:45:01.60#ibcon#read 6, iclass 25, count 2 2006.161.07:45:01.60#ibcon#end of sib2, iclass 25, count 2 2006.161.07:45:01.60#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:45:01.60#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:45:01.60#ibcon#[25=AT05-07\r\n] 2006.161.07:45:01.60#ibcon#*before write, iclass 25, count 2 2006.161.07:45:01.60#ibcon#enter sib2, iclass 25, count 2 2006.161.07:45:01.60#ibcon#flushed, iclass 25, count 2 2006.161.07:45:01.60#ibcon#about to write, iclass 25, count 2 2006.161.07:45:01.60#ibcon#wrote, iclass 25, count 2 2006.161.07:45:01.60#ibcon#about to read 3, iclass 25, count 2 2006.161.07:45:01.63#ibcon#read 3, iclass 25, count 2 2006.161.07:45:01.63#ibcon#about to read 4, iclass 25, count 2 2006.161.07:45:01.63#ibcon#read 4, iclass 25, count 2 2006.161.07:45:01.63#ibcon#about to read 5, iclass 25, count 2 2006.161.07:45:01.63#ibcon#read 5, iclass 25, count 2 2006.161.07:45:01.63#ibcon#about to read 6, iclass 25, count 2 2006.161.07:45:01.63#ibcon#read 6, iclass 25, count 2 2006.161.07:45:01.63#ibcon#end of sib2, iclass 25, count 2 2006.161.07:45:01.63#ibcon#*after write, iclass 25, count 2 2006.161.07:45:01.63#ibcon#*before return 0, iclass 25, count 2 2006.161.07:45:01.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:01.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:01.63#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:45:01.63#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:01.63#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:01.75#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:01.75#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:01.75#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:45:01.75#ibcon#first serial, iclass 25, count 0 2006.161.07:45:01.75#ibcon#enter sib2, iclass 25, count 0 2006.161.07:45:01.75#ibcon#flushed, iclass 25, count 0 2006.161.07:45:01.75#ibcon#about to write, iclass 25, count 0 2006.161.07:45:01.75#ibcon#wrote, iclass 25, count 0 2006.161.07:45:01.75#ibcon#about to read 3, iclass 25, count 0 2006.161.07:45:01.77#ibcon#read 3, iclass 25, count 0 2006.161.07:45:01.77#ibcon#about to read 4, iclass 25, count 0 2006.161.07:45:01.77#ibcon#read 4, iclass 25, count 0 2006.161.07:45:01.77#ibcon#about to read 5, iclass 25, count 0 2006.161.07:45:01.77#ibcon#read 5, iclass 25, count 0 2006.161.07:45:01.77#ibcon#about to read 6, iclass 25, count 0 2006.161.07:45:01.77#ibcon#read 6, iclass 25, count 0 2006.161.07:45:01.77#ibcon#end of sib2, iclass 25, count 0 2006.161.07:45:01.77#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:45:01.77#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:45:01.77#ibcon#[25=USB\r\n] 2006.161.07:45:01.77#ibcon#*before write, iclass 25, count 0 2006.161.07:45:01.77#ibcon#enter sib2, iclass 25, count 0 2006.161.07:45:01.77#ibcon#flushed, iclass 25, count 0 2006.161.07:45:01.77#ibcon#about to write, iclass 25, count 0 2006.161.07:45:01.77#ibcon#wrote, iclass 25, count 0 2006.161.07:45:01.77#ibcon#about to read 3, iclass 25, count 0 2006.161.07:45:01.80#ibcon#read 3, iclass 25, count 0 2006.161.07:45:01.80#ibcon#about to read 4, iclass 25, count 0 2006.161.07:45:01.80#ibcon#read 4, iclass 25, count 0 2006.161.07:45:01.80#ibcon#about to read 5, iclass 25, count 0 2006.161.07:45:01.80#ibcon#read 5, iclass 25, count 0 2006.161.07:45:01.80#ibcon#about to read 6, iclass 25, count 0 2006.161.07:45:01.80#ibcon#read 6, iclass 25, count 0 2006.161.07:45:01.80#ibcon#end of sib2, iclass 25, count 0 2006.161.07:45:01.80#ibcon#*after write, iclass 25, count 0 2006.161.07:45:01.80#ibcon#*before return 0, iclass 25, count 0 2006.161.07:45:01.80#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:01.80#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:01.80#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:45:01.80#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:45:01.80$vc4f8/valo=6,772.99 2006.161.07:45:01.80#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.07:45:01.80#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.07:45:01.80#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:01.80#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:01.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:01.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:01.80#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:45:01.80#ibcon#first serial, iclass 27, count 0 2006.161.07:45:01.80#ibcon#enter sib2, iclass 27, count 0 2006.161.07:45:01.80#ibcon#flushed, iclass 27, count 0 2006.161.07:45:01.80#ibcon#about to write, iclass 27, count 0 2006.161.07:45:01.80#ibcon#wrote, iclass 27, count 0 2006.161.07:45:01.80#ibcon#about to read 3, iclass 27, count 0 2006.161.07:45:01.82#ibcon#read 3, iclass 27, count 0 2006.161.07:45:01.82#ibcon#about to read 4, iclass 27, count 0 2006.161.07:45:01.82#ibcon#read 4, iclass 27, count 0 2006.161.07:45:01.82#ibcon#about to read 5, iclass 27, count 0 2006.161.07:45:01.82#ibcon#read 5, iclass 27, count 0 2006.161.07:45:01.82#ibcon#about to read 6, iclass 27, count 0 2006.161.07:45:01.82#ibcon#read 6, iclass 27, count 0 2006.161.07:45:01.82#ibcon#end of sib2, iclass 27, count 0 2006.161.07:45:01.82#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:45:01.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:45:01.82#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:45:01.82#ibcon#*before write, iclass 27, count 0 2006.161.07:45:01.82#ibcon#enter sib2, iclass 27, count 0 2006.161.07:45:01.82#ibcon#flushed, iclass 27, count 0 2006.161.07:45:01.82#ibcon#about to write, iclass 27, count 0 2006.161.07:45:01.82#ibcon#wrote, iclass 27, count 0 2006.161.07:45:01.82#ibcon#about to read 3, iclass 27, count 0 2006.161.07:45:01.86#ibcon#read 3, iclass 27, count 0 2006.161.07:45:01.86#ibcon#about to read 4, iclass 27, count 0 2006.161.07:45:01.86#ibcon#read 4, iclass 27, count 0 2006.161.07:45:01.86#ibcon#about to read 5, iclass 27, count 0 2006.161.07:45:01.86#ibcon#read 5, iclass 27, count 0 2006.161.07:45:01.86#ibcon#about to read 6, iclass 27, count 0 2006.161.07:45:01.86#ibcon#read 6, iclass 27, count 0 2006.161.07:45:01.86#ibcon#end of sib2, iclass 27, count 0 2006.161.07:45:01.86#ibcon#*after write, iclass 27, count 0 2006.161.07:45:01.86#ibcon#*before return 0, iclass 27, count 0 2006.161.07:45:01.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:01.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:01.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:45:01.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:45:01.86$vc4f8/va=6,6 2006.161.07:45:01.86#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.07:45:01.86#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.07:45:01.86#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:01.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:01.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:01.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:01.92#ibcon#enter wrdev, iclass 29, count 2 2006.161.07:45:01.92#ibcon#first serial, iclass 29, count 2 2006.161.07:45:01.92#ibcon#enter sib2, iclass 29, count 2 2006.161.07:45:01.92#ibcon#flushed, iclass 29, count 2 2006.161.07:45:01.92#ibcon#about to write, iclass 29, count 2 2006.161.07:45:01.92#ibcon#wrote, iclass 29, count 2 2006.161.07:45:01.92#ibcon#about to read 3, iclass 29, count 2 2006.161.07:45:01.94#ibcon#read 3, iclass 29, count 2 2006.161.07:45:01.94#ibcon#about to read 4, iclass 29, count 2 2006.161.07:45:01.94#ibcon#read 4, iclass 29, count 2 2006.161.07:45:01.94#ibcon#about to read 5, iclass 29, count 2 2006.161.07:45:01.94#ibcon#read 5, iclass 29, count 2 2006.161.07:45:01.94#ibcon#about to read 6, iclass 29, count 2 2006.161.07:45:01.94#ibcon#read 6, iclass 29, count 2 2006.161.07:45:01.94#ibcon#end of sib2, iclass 29, count 2 2006.161.07:45:01.94#ibcon#*mode == 0, iclass 29, count 2 2006.161.07:45:01.94#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.07:45:01.94#ibcon#[25=AT06-06\r\n] 2006.161.07:45:01.94#ibcon#*before write, iclass 29, count 2 2006.161.07:45:01.94#ibcon#enter sib2, iclass 29, count 2 2006.161.07:45:01.94#ibcon#flushed, iclass 29, count 2 2006.161.07:45:01.94#ibcon#about to write, iclass 29, count 2 2006.161.07:45:01.94#ibcon#wrote, iclass 29, count 2 2006.161.07:45:01.94#ibcon#about to read 3, iclass 29, count 2 2006.161.07:45:01.97#ibcon#read 3, iclass 29, count 2 2006.161.07:45:01.97#ibcon#about to read 4, iclass 29, count 2 2006.161.07:45:01.97#ibcon#read 4, iclass 29, count 2 2006.161.07:45:01.97#ibcon#about to read 5, iclass 29, count 2 2006.161.07:45:01.97#ibcon#read 5, iclass 29, count 2 2006.161.07:45:01.97#ibcon#about to read 6, iclass 29, count 2 2006.161.07:45:01.97#ibcon#read 6, iclass 29, count 2 2006.161.07:45:01.97#ibcon#end of sib2, iclass 29, count 2 2006.161.07:45:01.97#ibcon#*after write, iclass 29, count 2 2006.161.07:45:01.97#ibcon#*before return 0, iclass 29, count 2 2006.161.07:45:01.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:01.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:01.97#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.07:45:01.97#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:01.97#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:45:02.09#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:45:02.09#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:45:02.09#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:45:02.09#ibcon#first serial, iclass 29, count 0 2006.161.07:45:02.09#ibcon#enter sib2, iclass 29, count 0 2006.161.07:45:02.09#ibcon#flushed, iclass 29, count 0 2006.161.07:45:02.09#ibcon#about to write, iclass 29, count 0 2006.161.07:45:02.09#ibcon#wrote, iclass 29, count 0 2006.161.07:45:02.09#ibcon#about to read 3, iclass 29, count 0 2006.161.07:45:02.11#ibcon#read 3, iclass 29, count 0 2006.161.07:45:02.11#ibcon#about to read 4, iclass 29, count 0 2006.161.07:45:02.11#ibcon#read 4, iclass 29, count 0 2006.161.07:45:02.11#ibcon#about to read 5, iclass 29, count 0 2006.161.07:45:02.11#ibcon#read 5, iclass 29, count 0 2006.161.07:45:02.11#ibcon#about to read 6, iclass 29, count 0 2006.161.07:45:02.11#ibcon#read 6, iclass 29, count 0 2006.161.07:45:02.11#ibcon#end of sib2, iclass 29, count 0 2006.161.07:45:02.11#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:45:02.11#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:45:02.11#ibcon#[25=USB\r\n] 2006.161.07:45:02.11#ibcon#*before write, iclass 29, count 0 2006.161.07:45:02.11#ibcon#enter sib2, iclass 29, count 0 2006.161.07:45:02.11#ibcon#flushed, iclass 29, count 0 2006.161.07:45:02.11#ibcon#about to write, iclass 29, count 0 2006.161.07:45:02.11#ibcon#wrote, iclass 29, count 0 2006.161.07:45:02.11#ibcon#about to read 3, iclass 29, count 0 2006.161.07:45:02.14#ibcon#read 3, iclass 29, count 0 2006.161.07:45:02.14#ibcon#about to read 4, iclass 29, count 0 2006.161.07:45:02.14#ibcon#read 4, iclass 29, count 0 2006.161.07:45:02.14#ibcon#about to read 5, iclass 29, count 0 2006.161.07:45:02.14#ibcon#read 5, iclass 29, count 0 2006.161.07:45:02.14#ibcon#about to read 6, iclass 29, count 0 2006.161.07:45:02.14#ibcon#read 6, iclass 29, count 0 2006.161.07:45:02.14#ibcon#end of sib2, iclass 29, count 0 2006.161.07:45:02.14#ibcon#*after write, iclass 29, count 0 2006.161.07:45:02.14#ibcon#*before return 0, iclass 29, count 0 2006.161.07:45:02.14#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:45:02.14#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:45:02.14#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:45:02.14#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:45:02.14$vc4f8/valo=7,832.99 2006.161.07:45:02.14#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.07:45:02.14#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.07:45:02.14#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:02.14#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:45:02.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:45:02.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:45:02.14#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:45:02.14#ibcon#first serial, iclass 31, count 0 2006.161.07:45:02.14#ibcon#enter sib2, iclass 31, count 0 2006.161.07:45:02.14#ibcon#flushed, iclass 31, count 0 2006.161.07:45:02.14#ibcon#about to write, iclass 31, count 0 2006.161.07:45:02.14#ibcon#wrote, iclass 31, count 0 2006.161.07:45:02.14#ibcon#about to read 3, iclass 31, count 0 2006.161.07:45:02.16#ibcon#read 3, iclass 31, count 0 2006.161.07:45:02.16#ibcon#about to read 4, iclass 31, count 0 2006.161.07:45:02.16#ibcon#read 4, iclass 31, count 0 2006.161.07:45:02.16#ibcon#about to read 5, iclass 31, count 0 2006.161.07:45:02.16#ibcon#read 5, iclass 31, count 0 2006.161.07:45:02.16#ibcon#about to read 6, iclass 31, count 0 2006.161.07:45:02.16#ibcon#read 6, iclass 31, count 0 2006.161.07:45:02.16#ibcon#end of sib2, iclass 31, count 0 2006.161.07:45:02.16#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:45:02.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:45:02.16#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:45:02.16#ibcon#*before write, iclass 31, count 0 2006.161.07:45:02.16#ibcon#enter sib2, iclass 31, count 0 2006.161.07:45:02.16#ibcon#flushed, iclass 31, count 0 2006.161.07:45:02.16#ibcon#about to write, iclass 31, count 0 2006.161.07:45:02.16#ibcon#wrote, iclass 31, count 0 2006.161.07:45:02.16#ibcon#about to read 3, iclass 31, count 0 2006.161.07:45:02.20#ibcon#read 3, iclass 31, count 0 2006.161.07:45:02.20#ibcon#about to read 4, iclass 31, count 0 2006.161.07:45:02.20#ibcon#read 4, iclass 31, count 0 2006.161.07:45:02.20#ibcon#about to read 5, iclass 31, count 0 2006.161.07:45:02.20#ibcon#read 5, iclass 31, count 0 2006.161.07:45:02.20#ibcon#about to read 6, iclass 31, count 0 2006.161.07:45:02.20#ibcon#read 6, iclass 31, count 0 2006.161.07:45:02.20#ibcon#end of sib2, iclass 31, count 0 2006.161.07:45:02.20#ibcon#*after write, iclass 31, count 0 2006.161.07:45:02.20#ibcon#*before return 0, iclass 31, count 0 2006.161.07:45:02.20#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:45:02.20#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:45:02.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:45:02.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:45:02.20$vc4f8/va=7,6 2006.161.07:45:02.20#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.07:45:02.20#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.07:45:02.20#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:02.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:45:02.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:45:02.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:45:02.26#ibcon#enter wrdev, iclass 33, count 2 2006.161.07:45:02.26#ibcon#first serial, iclass 33, count 2 2006.161.07:45:02.26#ibcon#enter sib2, iclass 33, count 2 2006.161.07:45:02.26#ibcon#flushed, iclass 33, count 2 2006.161.07:45:02.26#ibcon#about to write, iclass 33, count 2 2006.161.07:45:02.26#ibcon#wrote, iclass 33, count 2 2006.161.07:45:02.26#ibcon#about to read 3, iclass 33, count 2 2006.161.07:45:02.29#ibcon#read 3, iclass 33, count 2 2006.161.07:45:02.29#ibcon#about to read 4, iclass 33, count 2 2006.161.07:45:02.29#ibcon#read 4, iclass 33, count 2 2006.161.07:45:02.29#ibcon#about to read 5, iclass 33, count 2 2006.161.07:45:02.29#ibcon#read 5, iclass 33, count 2 2006.161.07:45:02.29#ibcon#about to read 6, iclass 33, count 2 2006.161.07:45:02.29#ibcon#read 6, iclass 33, count 2 2006.161.07:45:02.29#ibcon#end of sib2, iclass 33, count 2 2006.161.07:45:02.29#ibcon#*mode == 0, iclass 33, count 2 2006.161.07:45:02.29#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.07:45:02.29#ibcon#[25=AT07-06\r\n] 2006.161.07:45:02.29#ibcon#*before write, iclass 33, count 2 2006.161.07:45:02.29#ibcon#enter sib2, iclass 33, count 2 2006.161.07:45:02.29#ibcon#flushed, iclass 33, count 2 2006.161.07:45:02.29#ibcon#about to write, iclass 33, count 2 2006.161.07:45:02.29#ibcon#wrote, iclass 33, count 2 2006.161.07:45:02.29#ibcon#about to read 3, iclass 33, count 2 2006.161.07:45:02.32#ibcon#read 3, iclass 33, count 2 2006.161.07:45:02.32#ibcon#about to read 4, iclass 33, count 2 2006.161.07:45:02.32#ibcon#read 4, iclass 33, count 2 2006.161.07:45:02.32#ibcon#about to read 5, iclass 33, count 2 2006.161.07:45:02.32#ibcon#read 5, iclass 33, count 2 2006.161.07:45:02.32#ibcon#about to read 6, iclass 33, count 2 2006.161.07:45:02.32#ibcon#read 6, iclass 33, count 2 2006.161.07:45:02.32#ibcon#end of sib2, iclass 33, count 2 2006.161.07:45:02.32#ibcon#*after write, iclass 33, count 2 2006.161.07:45:02.32#ibcon#*before return 0, iclass 33, count 2 2006.161.07:45:02.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:45:02.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.07:45:02.32#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.07:45:02.32#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:02.32#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:45:02.44#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:45:02.44#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:45:02.44#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:45:02.44#ibcon#first serial, iclass 33, count 0 2006.161.07:45:02.44#ibcon#enter sib2, iclass 33, count 0 2006.161.07:45:02.44#ibcon#flushed, iclass 33, count 0 2006.161.07:45:02.44#ibcon#about to write, iclass 33, count 0 2006.161.07:45:02.44#ibcon#wrote, iclass 33, count 0 2006.161.07:45:02.44#ibcon#about to read 3, iclass 33, count 0 2006.161.07:45:02.46#ibcon#read 3, iclass 33, count 0 2006.161.07:45:02.46#ibcon#about to read 4, iclass 33, count 0 2006.161.07:45:02.46#ibcon#read 4, iclass 33, count 0 2006.161.07:45:02.46#ibcon#about to read 5, iclass 33, count 0 2006.161.07:45:02.46#ibcon#read 5, iclass 33, count 0 2006.161.07:45:02.46#ibcon#about to read 6, iclass 33, count 0 2006.161.07:45:02.46#ibcon#read 6, iclass 33, count 0 2006.161.07:45:02.46#ibcon#end of sib2, iclass 33, count 0 2006.161.07:45:02.46#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:45:02.46#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:45:02.46#ibcon#[25=USB\r\n] 2006.161.07:45:02.46#ibcon#*before write, iclass 33, count 0 2006.161.07:45:02.46#ibcon#enter sib2, iclass 33, count 0 2006.161.07:45:02.46#ibcon#flushed, iclass 33, count 0 2006.161.07:45:02.46#ibcon#about to write, iclass 33, count 0 2006.161.07:45:02.46#ibcon#wrote, iclass 33, count 0 2006.161.07:45:02.46#ibcon#about to read 3, iclass 33, count 0 2006.161.07:45:02.49#ibcon#read 3, iclass 33, count 0 2006.161.07:45:02.49#ibcon#about to read 4, iclass 33, count 0 2006.161.07:45:02.49#ibcon#read 4, iclass 33, count 0 2006.161.07:45:02.49#ibcon#about to read 5, iclass 33, count 0 2006.161.07:45:02.49#ibcon#read 5, iclass 33, count 0 2006.161.07:45:02.49#ibcon#about to read 6, iclass 33, count 0 2006.161.07:45:02.49#ibcon#read 6, iclass 33, count 0 2006.161.07:45:02.49#ibcon#end of sib2, iclass 33, count 0 2006.161.07:45:02.49#ibcon#*after write, iclass 33, count 0 2006.161.07:45:02.49#ibcon#*before return 0, iclass 33, count 0 2006.161.07:45:02.49#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:45:02.49#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.07:45:02.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:45:02.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:45:02.49$vc4f8/valo=8,852.99 2006.161.07:45:02.49#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.07:45:02.49#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.07:45:02.49#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:02.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:45:02.49#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:45:02.49#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:45:02.49#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:45:02.49#ibcon#first serial, iclass 35, count 0 2006.161.07:45:02.49#ibcon#enter sib2, iclass 35, count 0 2006.161.07:45:02.49#ibcon#flushed, iclass 35, count 0 2006.161.07:45:02.49#ibcon#about to write, iclass 35, count 0 2006.161.07:45:02.49#ibcon#wrote, iclass 35, count 0 2006.161.07:45:02.49#ibcon#about to read 3, iclass 35, count 0 2006.161.07:45:02.51#ibcon#read 3, iclass 35, count 0 2006.161.07:45:02.51#ibcon#about to read 4, iclass 35, count 0 2006.161.07:45:02.51#ibcon#read 4, iclass 35, count 0 2006.161.07:45:02.51#ibcon#about to read 5, iclass 35, count 0 2006.161.07:45:02.51#ibcon#read 5, iclass 35, count 0 2006.161.07:45:02.51#ibcon#about to read 6, iclass 35, count 0 2006.161.07:45:02.51#ibcon#read 6, iclass 35, count 0 2006.161.07:45:02.51#ibcon#end of sib2, iclass 35, count 0 2006.161.07:45:02.51#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:45:02.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:45:02.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:45:02.51#ibcon#*before write, iclass 35, count 0 2006.161.07:45:02.51#ibcon#enter sib2, iclass 35, count 0 2006.161.07:45:02.51#ibcon#flushed, iclass 35, count 0 2006.161.07:45:02.51#ibcon#about to write, iclass 35, count 0 2006.161.07:45:02.51#ibcon#wrote, iclass 35, count 0 2006.161.07:45:02.51#ibcon#about to read 3, iclass 35, count 0 2006.161.07:45:02.55#ibcon#read 3, iclass 35, count 0 2006.161.07:45:02.55#ibcon#about to read 4, iclass 35, count 0 2006.161.07:45:02.55#ibcon#read 4, iclass 35, count 0 2006.161.07:45:02.55#ibcon#about to read 5, iclass 35, count 0 2006.161.07:45:02.55#ibcon#read 5, iclass 35, count 0 2006.161.07:45:02.55#ibcon#about to read 6, iclass 35, count 0 2006.161.07:45:02.55#ibcon#read 6, iclass 35, count 0 2006.161.07:45:02.55#ibcon#end of sib2, iclass 35, count 0 2006.161.07:45:02.55#ibcon#*after write, iclass 35, count 0 2006.161.07:45:02.55#ibcon#*before return 0, iclass 35, count 0 2006.161.07:45:02.55#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:45:02.55#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:45:02.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:45:02.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:45:02.55$vc4f8/va=8,7 2006.161.07:45:02.55#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.07:45:02.55#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.07:45:02.55#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:02.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:45:02.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:45:02.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:45:02.61#ibcon#enter wrdev, iclass 37, count 2 2006.161.07:45:02.61#ibcon#first serial, iclass 37, count 2 2006.161.07:45:02.61#ibcon#enter sib2, iclass 37, count 2 2006.161.07:45:02.61#ibcon#flushed, iclass 37, count 2 2006.161.07:45:02.61#ibcon#about to write, iclass 37, count 2 2006.161.07:45:02.61#ibcon#wrote, iclass 37, count 2 2006.161.07:45:02.61#ibcon#about to read 3, iclass 37, count 2 2006.161.07:45:02.63#ibcon#read 3, iclass 37, count 2 2006.161.07:45:02.63#ibcon#about to read 4, iclass 37, count 2 2006.161.07:45:02.63#ibcon#read 4, iclass 37, count 2 2006.161.07:45:02.63#ibcon#about to read 5, iclass 37, count 2 2006.161.07:45:02.63#ibcon#read 5, iclass 37, count 2 2006.161.07:45:02.63#ibcon#about to read 6, iclass 37, count 2 2006.161.07:45:02.63#ibcon#read 6, iclass 37, count 2 2006.161.07:45:02.63#ibcon#end of sib2, iclass 37, count 2 2006.161.07:45:02.63#ibcon#*mode == 0, iclass 37, count 2 2006.161.07:45:02.63#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.07:45:02.63#ibcon#[25=AT08-07\r\n] 2006.161.07:45:02.63#ibcon#*before write, iclass 37, count 2 2006.161.07:45:02.63#ibcon#enter sib2, iclass 37, count 2 2006.161.07:45:02.63#ibcon#flushed, iclass 37, count 2 2006.161.07:45:02.63#ibcon#about to write, iclass 37, count 2 2006.161.07:45:02.63#ibcon#wrote, iclass 37, count 2 2006.161.07:45:02.63#ibcon#about to read 3, iclass 37, count 2 2006.161.07:45:02.66#ibcon#read 3, iclass 37, count 2 2006.161.07:45:02.66#ibcon#about to read 4, iclass 37, count 2 2006.161.07:45:02.66#ibcon#read 4, iclass 37, count 2 2006.161.07:45:02.66#ibcon#about to read 5, iclass 37, count 2 2006.161.07:45:02.66#ibcon#read 5, iclass 37, count 2 2006.161.07:45:02.66#ibcon#about to read 6, iclass 37, count 2 2006.161.07:45:02.66#ibcon#read 6, iclass 37, count 2 2006.161.07:45:02.66#ibcon#end of sib2, iclass 37, count 2 2006.161.07:45:02.66#ibcon#*after write, iclass 37, count 2 2006.161.07:45:02.66#ibcon#*before return 0, iclass 37, count 2 2006.161.07:45:02.66#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:45:02.66#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:45:02.66#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.07:45:02.66#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:02.66#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:45:02.78#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:45:02.78#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:45:02.78#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:45:02.78#ibcon#first serial, iclass 37, count 0 2006.161.07:45:02.78#ibcon#enter sib2, iclass 37, count 0 2006.161.07:45:02.78#ibcon#flushed, iclass 37, count 0 2006.161.07:45:02.78#ibcon#about to write, iclass 37, count 0 2006.161.07:45:02.78#ibcon#wrote, iclass 37, count 0 2006.161.07:45:02.78#ibcon#about to read 3, iclass 37, count 0 2006.161.07:45:02.80#ibcon#read 3, iclass 37, count 0 2006.161.07:45:02.80#ibcon#about to read 4, iclass 37, count 0 2006.161.07:45:02.80#ibcon#read 4, iclass 37, count 0 2006.161.07:45:02.80#ibcon#about to read 5, iclass 37, count 0 2006.161.07:45:02.80#ibcon#read 5, iclass 37, count 0 2006.161.07:45:02.80#ibcon#about to read 6, iclass 37, count 0 2006.161.07:45:02.80#ibcon#read 6, iclass 37, count 0 2006.161.07:45:02.80#ibcon#end of sib2, iclass 37, count 0 2006.161.07:45:02.80#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:45:02.80#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:45:02.80#ibcon#[25=USB\r\n] 2006.161.07:45:02.80#ibcon#*before write, iclass 37, count 0 2006.161.07:45:02.80#ibcon#enter sib2, iclass 37, count 0 2006.161.07:45:02.80#ibcon#flushed, iclass 37, count 0 2006.161.07:45:02.80#ibcon#about to write, iclass 37, count 0 2006.161.07:45:02.80#ibcon#wrote, iclass 37, count 0 2006.161.07:45:02.80#ibcon#about to read 3, iclass 37, count 0 2006.161.07:45:02.83#ibcon#read 3, iclass 37, count 0 2006.161.07:45:02.83#ibcon#about to read 4, iclass 37, count 0 2006.161.07:45:02.83#ibcon#read 4, iclass 37, count 0 2006.161.07:45:02.83#ibcon#about to read 5, iclass 37, count 0 2006.161.07:45:02.83#ibcon#read 5, iclass 37, count 0 2006.161.07:45:02.83#ibcon#about to read 6, iclass 37, count 0 2006.161.07:45:02.83#ibcon#read 6, iclass 37, count 0 2006.161.07:45:02.83#ibcon#end of sib2, iclass 37, count 0 2006.161.07:45:02.83#ibcon#*after write, iclass 37, count 0 2006.161.07:45:02.83#ibcon#*before return 0, iclass 37, count 0 2006.161.07:45:02.83#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:45:02.83#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:45:02.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:45:02.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:45:02.83$vc4f8/vblo=1,632.99 2006.161.07:45:02.83#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.07:45:02.83#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.07:45:02.83#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:02.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:02.83#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:02.83#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:02.83#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:45:02.83#ibcon#first serial, iclass 39, count 0 2006.161.07:45:02.83#ibcon#enter sib2, iclass 39, count 0 2006.161.07:45:02.83#ibcon#flushed, iclass 39, count 0 2006.161.07:45:02.83#ibcon#about to write, iclass 39, count 0 2006.161.07:45:02.83#ibcon#wrote, iclass 39, count 0 2006.161.07:45:02.83#ibcon#about to read 3, iclass 39, count 0 2006.161.07:45:02.85#ibcon#read 3, iclass 39, count 0 2006.161.07:45:02.85#ibcon#about to read 4, iclass 39, count 0 2006.161.07:45:02.85#ibcon#read 4, iclass 39, count 0 2006.161.07:45:02.85#ibcon#about to read 5, iclass 39, count 0 2006.161.07:45:02.85#ibcon#read 5, iclass 39, count 0 2006.161.07:45:02.85#ibcon#about to read 6, iclass 39, count 0 2006.161.07:45:02.85#ibcon#read 6, iclass 39, count 0 2006.161.07:45:02.85#ibcon#end of sib2, iclass 39, count 0 2006.161.07:45:02.85#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:45:02.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:45:02.85#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:45:02.85#ibcon#*before write, iclass 39, count 0 2006.161.07:45:02.85#ibcon#enter sib2, iclass 39, count 0 2006.161.07:45:02.85#ibcon#flushed, iclass 39, count 0 2006.161.07:45:02.85#ibcon#about to write, iclass 39, count 0 2006.161.07:45:02.85#ibcon#wrote, iclass 39, count 0 2006.161.07:45:02.85#ibcon#about to read 3, iclass 39, count 0 2006.161.07:45:02.89#ibcon#read 3, iclass 39, count 0 2006.161.07:45:02.89#ibcon#about to read 4, iclass 39, count 0 2006.161.07:45:02.89#ibcon#read 4, iclass 39, count 0 2006.161.07:45:02.89#ibcon#about to read 5, iclass 39, count 0 2006.161.07:45:02.89#ibcon#read 5, iclass 39, count 0 2006.161.07:45:02.89#ibcon#about to read 6, iclass 39, count 0 2006.161.07:45:02.89#ibcon#read 6, iclass 39, count 0 2006.161.07:45:02.89#ibcon#end of sib2, iclass 39, count 0 2006.161.07:45:02.89#ibcon#*after write, iclass 39, count 0 2006.161.07:45:02.89#ibcon#*before return 0, iclass 39, count 0 2006.161.07:45:02.89#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:02.89#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:45:02.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:45:02.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:45:02.89$vc4f8/vb=1,4 2006.161.07:45:02.89#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.07:45:02.89#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.07:45:02.89#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:02.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:02.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:02.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:02.89#ibcon#enter wrdev, iclass 3, count 2 2006.161.07:45:02.89#ibcon#first serial, iclass 3, count 2 2006.161.07:45:02.89#ibcon#enter sib2, iclass 3, count 2 2006.161.07:45:02.89#ibcon#flushed, iclass 3, count 2 2006.161.07:45:02.89#ibcon#about to write, iclass 3, count 2 2006.161.07:45:02.89#ibcon#wrote, iclass 3, count 2 2006.161.07:45:02.89#ibcon#about to read 3, iclass 3, count 2 2006.161.07:45:02.91#ibcon#read 3, iclass 3, count 2 2006.161.07:45:02.91#ibcon#about to read 4, iclass 3, count 2 2006.161.07:45:02.91#ibcon#read 4, iclass 3, count 2 2006.161.07:45:02.91#ibcon#about to read 5, iclass 3, count 2 2006.161.07:45:02.91#ibcon#read 5, iclass 3, count 2 2006.161.07:45:02.91#ibcon#about to read 6, iclass 3, count 2 2006.161.07:45:02.91#ibcon#read 6, iclass 3, count 2 2006.161.07:45:02.91#ibcon#end of sib2, iclass 3, count 2 2006.161.07:45:02.91#ibcon#*mode == 0, iclass 3, count 2 2006.161.07:45:02.91#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.07:45:02.91#ibcon#[27=AT01-04\r\n] 2006.161.07:45:02.91#ibcon#*before write, iclass 3, count 2 2006.161.07:45:02.91#ibcon#enter sib2, iclass 3, count 2 2006.161.07:45:02.91#ibcon#flushed, iclass 3, count 2 2006.161.07:45:02.91#ibcon#about to write, iclass 3, count 2 2006.161.07:45:02.91#ibcon#wrote, iclass 3, count 2 2006.161.07:45:02.91#ibcon#about to read 3, iclass 3, count 2 2006.161.07:45:02.94#ibcon#read 3, iclass 3, count 2 2006.161.07:45:02.94#ibcon#about to read 4, iclass 3, count 2 2006.161.07:45:02.94#ibcon#read 4, iclass 3, count 2 2006.161.07:45:02.94#ibcon#about to read 5, iclass 3, count 2 2006.161.07:45:02.94#ibcon#read 5, iclass 3, count 2 2006.161.07:45:02.94#ibcon#about to read 6, iclass 3, count 2 2006.161.07:45:02.94#ibcon#read 6, iclass 3, count 2 2006.161.07:45:02.94#ibcon#end of sib2, iclass 3, count 2 2006.161.07:45:02.94#ibcon#*after write, iclass 3, count 2 2006.161.07:45:02.94#ibcon#*before return 0, iclass 3, count 2 2006.161.07:45:02.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:02.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:45:02.94#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.07:45:02.94#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:02.94#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:03.06#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:03.06#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:03.06#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:45:03.06#ibcon#first serial, iclass 3, count 0 2006.161.07:45:03.06#ibcon#enter sib2, iclass 3, count 0 2006.161.07:45:03.06#ibcon#flushed, iclass 3, count 0 2006.161.07:45:03.06#ibcon#about to write, iclass 3, count 0 2006.161.07:45:03.06#ibcon#wrote, iclass 3, count 0 2006.161.07:45:03.06#ibcon#about to read 3, iclass 3, count 0 2006.161.07:45:03.08#ibcon#read 3, iclass 3, count 0 2006.161.07:45:03.08#ibcon#about to read 4, iclass 3, count 0 2006.161.07:45:03.08#ibcon#read 4, iclass 3, count 0 2006.161.07:45:03.08#ibcon#about to read 5, iclass 3, count 0 2006.161.07:45:03.08#ibcon#read 5, iclass 3, count 0 2006.161.07:45:03.08#ibcon#about to read 6, iclass 3, count 0 2006.161.07:45:03.08#ibcon#read 6, iclass 3, count 0 2006.161.07:45:03.08#ibcon#end of sib2, iclass 3, count 0 2006.161.07:45:03.08#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:45:03.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:45:03.08#ibcon#[27=USB\r\n] 2006.161.07:45:03.08#ibcon#*before write, iclass 3, count 0 2006.161.07:45:03.08#ibcon#enter sib2, iclass 3, count 0 2006.161.07:45:03.08#ibcon#flushed, iclass 3, count 0 2006.161.07:45:03.08#ibcon#about to write, iclass 3, count 0 2006.161.07:45:03.08#ibcon#wrote, iclass 3, count 0 2006.161.07:45:03.08#ibcon#about to read 3, iclass 3, count 0 2006.161.07:45:03.11#ibcon#read 3, iclass 3, count 0 2006.161.07:45:03.11#ibcon#about to read 4, iclass 3, count 0 2006.161.07:45:03.11#ibcon#read 4, iclass 3, count 0 2006.161.07:45:03.11#ibcon#about to read 5, iclass 3, count 0 2006.161.07:45:03.11#ibcon#read 5, iclass 3, count 0 2006.161.07:45:03.11#ibcon#about to read 6, iclass 3, count 0 2006.161.07:45:03.11#ibcon#read 6, iclass 3, count 0 2006.161.07:45:03.11#ibcon#end of sib2, iclass 3, count 0 2006.161.07:45:03.11#ibcon#*after write, iclass 3, count 0 2006.161.07:45:03.11#ibcon#*before return 0, iclass 3, count 0 2006.161.07:45:03.11#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:03.11#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:45:03.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:45:03.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:45:03.11$vc4f8/vblo=2,640.99 2006.161.07:45:03.11#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.07:45:03.11#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.07:45:03.11#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:03.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:03.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:03.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:03.11#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:45:03.11#ibcon#first serial, iclass 5, count 0 2006.161.07:45:03.11#ibcon#enter sib2, iclass 5, count 0 2006.161.07:45:03.11#ibcon#flushed, iclass 5, count 0 2006.161.07:45:03.11#ibcon#about to write, iclass 5, count 0 2006.161.07:45:03.11#ibcon#wrote, iclass 5, count 0 2006.161.07:45:03.11#ibcon#about to read 3, iclass 5, count 0 2006.161.07:45:03.13#ibcon#read 3, iclass 5, count 0 2006.161.07:45:03.13#ibcon#about to read 4, iclass 5, count 0 2006.161.07:45:03.13#ibcon#read 4, iclass 5, count 0 2006.161.07:45:03.13#ibcon#about to read 5, iclass 5, count 0 2006.161.07:45:03.13#ibcon#read 5, iclass 5, count 0 2006.161.07:45:03.13#ibcon#about to read 6, iclass 5, count 0 2006.161.07:45:03.13#ibcon#read 6, iclass 5, count 0 2006.161.07:45:03.13#ibcon#end of sib2, iclass 5, count 0 2006.161.07:45:03.13#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:45:03.13#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:45:03.13#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:45:03.13#ibcon#*before write, iclass 5, count 0 2006.161.07:45:03.13#ibcon#enter sib2, iclass 5, count 0 2006.161.07:45:03.13#ibcon#flushed, iclass 5, count 0 2006.161.07:45:03.13#ibcon#about to write, iclass 5, count 0 2006.161.07:45:03.13#ibcon#wrote, iclass 5, count 0 2006.161.07:45:03.13#ibcon#about to read 3, iclass 5, count 0 2006.161.07:45:03.17#ibcon#read 3, iclass 5, count 0 2006.161.07:45:03.17#ibcon#about to read 4, iclass 5, count 0 2006.161.07:45:03.17#ibcon#read 4, iclass 5, count 0 2006.161.07:45:03.17#ibcon#about to read 5, iclass 5, count 0 2006.161.07:45:03.17#ibcon#read 5, iclass 5, count 0 2006.161.07:45:03.17#ibcon#about to read 6, iclass 5, count 0 2006.161.07:45:03.17#ibcon#read 6, iclass 5, count 0 2006.161.07:45:03.17#ibcon#end of sib2, iclass 5, count 0 2006.161.07:45:03.17#ibcon#*after write, iclass 5, count 0 2006.161.07:45:03.17#ibcon#*before return 0, iclass 5, count 0 2006.161.07:45:03.17#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:03.17#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:45:03.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:45:03.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:45:03.18$vc4f8/vb=2,4 2006.161.07:45:03.18#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.07:45:03.18#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.07:45:03.18#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:03.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:03.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:03.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:03.22#ibcon#enter wrdev, iclass 7, count 2 2006.161.07:45:03.22#ibcon#first serial, iclass 7, count 2 2006.161.07:45:03.22#ibcon#enter sib2, iclass 7, count 2 2006.161.07:45:03.22#ibcon#flushed, iclass 7, count 2 2006.161.07:45:03.22#ibcon#about to write, iclass 7, count 2 2006.161.07:45:03.22#ibcon#wrote, iclass 7, count 2 2006.161.07:45:03.22#ibcon#about to read 3, iclass 7, count 2 2006.161.07:45:03.24#ibcon#read 3, iclass 7, count 2 2006.161.07:45:03.24#ibcon#about to read 4, iclass 7, count 2 2006.161.07:45:03.24#ibcon#read 4, iclass 7, count 2 2006.161.07:45:03.24#ibcon#about to read 5, iclass 7, count 2 2006.161.07:45:03.24#ibcon#read 5, iclass 7, count 2 2006.161.07:45:03.24#ibcon#about to read 6, iclass 7, count 2 2006.161.07:45:03.24#ibcon#read 6, iclass 7, count 2 2006.161.07:45:03.24#ibcon#end of sib2, iclass 7, count 2 2006.161.07:45:03.24#ibcon#*mode == 0, iclass 7, count 2 2006.161.07:45:03.24#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.07:45:03.24#ibcon#[27=AT02-04\r\n] 2006.161.07:45:03.24#ibcon#*before write, iclass 7, count 2 2006.161.07:45:03.24#ibcon#enter sib2, iclass 7, count 2 2006.161.07:45:03.24#ibcon#flushed, iclass 7, count 2 2006.161.07:45:03.24#ibcon#about to write, iclass 7, count 2 2006.161.07:45:03.24#ibcon#wrote, iclass 7, count 2 2006.161.07:45:03.24#ibcon#about to read 3, iclass 7, count 2 2006.161.07:45:03.27#ibcon#read 3, iclass 7, count 2 2006.161.07:45:03.27#ibcon#about to read 4, iclass 7, count 2 2006.161.07:45:03.27#ibcon#read 4, iclass 7, count 2 2006.161.07:45:03.27#ibcon#about to read 5, iclass 7, count 2 2006.161.07:45:03.27#ibcon#read 5, iclass 7, count 2 2006.161.07:45:03.27#ibcon#about to read 6, iclass 7, count 2 2006.161.07:45:03.27#ibcon#read 6, iclass 7, count 2 2006.161.07:45:03.27#ibcon#end of sib2, iclass 7, count 2 2006.161.07:45:03.27#ibcon#*after write, iclass 7, count 2 2006.161.07:45:03.27#ibcon#*before return 0, iclass 7, count 2 2006.161.07:45:03.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:03.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:45:03.27#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.07:45:03.27#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:03.27#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:03.39#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:03.39#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:03.39#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:45:03.39#ibcon#first serial, iclass 7, count 0 2006.161.07:45:03.39#ibcon#enter sib2, iclass 7, count 0 2006.161.07:45:03.39#ibcon#flushed, iclass 7, count 0 2006.161.07:45:03.39#ibcon#about to write, iclass 7, count 0 2006.161.07:45:03.39#ibcon#wrote, iclass 7, count 0 2006.161.07:45:03.39#ibcon#about to read 3, iclass 7, count 0 2006.161.07:45:03.41#ibcon#read 3, iclass 7, count 0 2006.161.07:45:03.41#ibcon#about to read 4, iclass 7, count 0 2006.161.07:45:03.41#ibcon#read 4, iclass 7, count 0 2006.161.07:45:03.41#ibcon#about to read 5, iclass 7, count 0 2006.161.07:45:03.41#ibcon#read 5, iclass 7, count 0 2006.161.07:45:03.41#ibcon#about to read 6, iclass 7, count 0 2006.161.07:45:03.41#ibcon#read 6, iclass 7, count 0 2006.161.07:45:03.41#ibcon#end of sib2, iclass 7, count 0 2006.161.07:45:03.41#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:45:03.41#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:45:03.41#ibcon#[27=USB\r\n] 2006.161.07:45:03.41#ibcon#*before write, iclass 7, count 0 2006.161.07:45:03.41#ibcon#enter sib2, iclass 7, count 0 2006.161.07:45:03.41#ibcon#flushed, iclass 7, count 0 2006.161.07:45:03.41#ibcon#about to write, iclass 7, count 0 2006.161.07:45:03.41#ibcon#wrote, iclass 7, count 0 2006.161.07:45:03.41#ibcon#about to read 3, iclass 7, count 0 2006.161.07:45:03.44#ibcon#read 3, iclass 7, count 0 2006.161.07:45:03.44#ibcon#about to read 4, iclass 7, count 0 2006.161.07:45:03.44#ibcon#read 4, iclass 7, count 0 2006.161.07:45:03.44#ibcon#about to read 5, iclass 7, count 0 2006.161.07:45:03.44#ibcon#read 5, iclass 7, count 0 2006.161.07:45:03.44#ibcon#about to read 6, iclass 7, count 0 2006.161.07:45:03.44#ibcon#read 6, iclass 7, count 0 2006.161.07:45:03.44#ibcon#end of sib2, iclass 7, count 0 2006.161.07:45:03.44#ibcon#*after write, iclass 7, count 0 2006.161.07:45:03.44#ibcon#*before return 0, iclass 7, count 0 2006.161.07:45:03.44#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:03.44#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:45:03.44#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:45:03.44#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:45:03.44$vc4f8/vblo=3,656.99 2006.161.07:45:03.44#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:45:03.44#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:45:03.44#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:03.44#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:03.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:03.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:03.44#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:45:03.44#ibcon#first serial, iclass 11, count 0 2006.161.07:45:03.44#ibcon#enter sib2, iclass 11, count 0 2006.161.07:45:03.44#ibcon#flushed, iclass 11, count 0 2006.161.07:45:03.44#ibcon#about to write, iclass 11, count 0 2006.161.07:45:03.44#ibcon#wrote, iclass 11, count 0 2006.161.07:45:03.44#ibcon#about to read 3, iclass 11, count 0 2006.161.07:45:03.46#ibcon#read 3, iclass 11, count 0 2006.161.07:45:03.46#ibcon#about to read 4, iclass 11, count 0 2006.161.07:45:03.46#ibcon#read 4, iclass 11, count 0 2006.161.07:45:03.46#ibcon#about to read 5, iclass 11, count 0 2006.161.07:45:03.46#ibcon#read 5, iclass 11, count 0 2006.161.07:45:03.46#ibcon#about to read 6, iclass 11, count 0 2006.161.07:45:03.46#ibcon#read 6, iclass 11, count 0 2006.161.07:45:03.46#ibcon#end of sib2, iclass 11, count 0 2006.161.07:45:03.46#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:45:03.46#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:45:03.46#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:45:03.46#ibcon#*before write, iclass 11, count 0 2006.161.07:45:03.46#ibcon#enter sib2, iclass 11, count 0 2006.161.07:45:03.46#ibcon#flushed, iclass 11, count 0 2006.161.07:45:03.46#ibcon#about to write, iclass 11, count 0 2006.161.07:45:03.46#ibcon#wrote, iclass 11, count 0 2006.161.07:45:03.46#ibcon#about to read 3, iclass 11, count 0 2006.161.07:45:03.50#ibcon#read 3, iclass 11, count 0 2006.161.07:45:03.50#ibcon#about to read 4, iclass 11, count 0 2006.161.07:45:03.50#ibcon#read 4, iclass 11, count 0 2006.161.07:45:03.50#ibcon#about to read 5, iclass 11, count 0 2006.161.07:45:03.50#ibcon#read 5, iclass 11, count 0 2006.161.07:45:03.50#ibcon#about to read 6, iclass 11, count 0 2006.161.07:45:03.50#ibcon#read 6, iclass 11, count 0 2006.161.07:45:03.50#ibcon#end of sib2, iclass 11, count 0 2006.161.07:45:03.50#ibcon#*after write, iclass 11, count 0 2006.161.07:45:03.50#ibcon#*before return 0, iclass 11, count 0 2006.161.07:45:03.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:03.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:45:03.50#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:45:03.50#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:45:03.50$vc4f8/vb=3,4 2006.161.07:45:03.50#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:45:03.50#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:45:03.50#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:03.50#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:03.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:03.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:03.56#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:45:03.56#ibcon#first serial, iclass 13, count 2 2006.161.07:45:03.56#ibcon#enter sib2, iclass 13, count 2 2006.161.07:45:03.56#ibcon#flushed, iclass 13, count 2 2006.161.07:45:03.56#ibcon#about to write, iclass 13, count 2 2006.161.07:45:03.56#ibcon#wrote, iclass 13, count 2 2006.161.07:45:03.56#ibcon#about to read 3, iclass 13, count 2 2006.161.07:45:03.58#ibcon#read 3, iclass 13, count 2 2006.161.07:45:03.58#ibcon#about to read 4, iclass 13, count 2 2006.161.07:45:03.58#ibcon#read 4, iclass 13, count 2 2006.161.07:45:03.58#ibcon#about to read 5, iclass 13, count 2 2006.161.07:45:03.58#ibcon#read 5, iclass 13, count 2 2006.161.07:45:03.58#ibcon#about to read 6, iclass 13, count 2 2006.161.07:45:03.58#ibcon#read 6, iclass 13, count 2 2006.161.07:45:03.58#ibcon#end of sib2, iclass 13, count 2 2006.161.07:45:03.58#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:45:03.58#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:45:03.58#ibcon#[27=AT03-04\r\n] 2006.161.07:45:03.58#ibcon#*before write, iclass 13, count 2 2006.161.07:45:03.58#ibcon#enter sib2, iclass 13, count 2 2006.161.07:45:03.58#ibcon#flushed, iclass 13, count 2 2006.161.07:45:03.58#ibcon#about to write, iclass 13, count 2 2006.161.07:45:03.58#ibcon#wrote, iclass 13, count 2 2006.161.07:45:03.58#ibcon#about to read 3, iclass 13, count 2 2006.161.07:45:03.61#ibcon#read 3, iclass 13, count 2 2006.161.07:45:03.61#ibcon#about to read 4, iclass 13, count 2 2006.161.07:45:03.61#ibcon#read 4, iclass 13, count 2 2006.161.07:45:03.61#ibcon#about to read 5, iclass 13, count 2 2006.161.07:45:03.61#ibcon#read 5, iclass 13, count 2 2006.161.07:45:03.61#ibcon#about to read 6, iclass 13, count 2 2006.161.07:45:03.61#ibcon#read 6, iclass 13, count 2 2006.161.07:45:03.61#ibcon#end of sib2, iclass 13, count 2 2006.161.07:45:03.61#ibcon#*after write, iclass 13, count 2 2006.161.07:45:03.61#ibcon#*before return 0, iclass 13, count 2 2006.161.07:45:03.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:03.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:45:03.61#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:45:03.61#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:03.61#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:03.73#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:03.73#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:03.73#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:45:03.73#ibcon#first serial, iclass 13, count 0 2006.161.07:45:03.73#ibcon#enter sib2, iclass 13, count 0 2006.161.07:45:03.73#ibcon#flushed, iclass 13, count 0 2006.161.07:45:03.73#ibcon#about to write, iclass 13, count 0 2006.161.07:45:03.73#ibcon#wrote, iclass 13, count 0 2006.161.07:45:03.73#ibcon#about to read 3, iclass 13, count 0 2006.161.07:45:03.75#ibcon#read 3, iclass 13, count 0 2006.161.07:45:03.75#ibcon#about to read 4, iclass 13, count 0 2006.161.07:45:03.75#ibcon#read 4, iclass 13, count 0 2006.161.07:45:03.75#ibcon#about to read 5, iclass 13, count 0 2006.161.07:45:03.75#ibcon#read 5, iclass 13, count 0 2006.161.07:45:03.75#ibcon#about to read 6, iclass 13, count 0 2006.161.07:45:03.75#ibcon#read 6, iclass 13, count 0 2006.161.07:45:03.75#ibcon#end of sib2, iclass 13, count 0 2006.161.07:45:03.75#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:45:03.75#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:45:03.75#ibcon#[27=USB\r\n] 2006.161.07:45:03.75#ibcon#*before write, iclass 13, count 0 2006.161.07:45:03.75#ibcon#enter sib2, iclass 13, count 0 2006.161.07:45:03.75#ibcon#flushed, iclass 13, count 0 2006.161.07:45:03.75#ibcon#about to write, iclass 13, count 0 2006.161.07:45:03.75#ibcon#wrote, iclass 13, count 0 2006.161.07:45:03.75#ibcon#about to read 3, iclass 13, count 0 2006.161.07:45:03.78#ibcon#read 3, iclass 13, count 0 2006.161.07:45:03.78#ibcon#about to read 4, iclass 13, count 0 2006.161.07:45:03.78#ibcon#read 4, iclass 13, count 0 2006.161.07:45:03.78#ibcon#about to read 5, iclass 13, count 0 2006.161.07:45:03.78#ibcon#read 5, iclass 13, count 0 2006.161.07:45:03.78#ibcon#about to read 6, iclass 13, count 0 2006.161.07:45:03.78#ibcon#read 6, iclass 13, count 0 2006.161.07:45:03.78#ibcon#end of sib2, iclass 13, count 0 2006.161.07:45:03.78#ibcon#*after write, iclass 13, count 0 2006.161.07:45:03.78#ibcon#*before return 0, iclass 13, count 0 2006.161.07:45:03.78#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:03.78#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:45:03.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:45:03.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:45:03.78$vc4f8/vblo=4,712.99 2006.161.07:45:03.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.07:45:03.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.07:45:03.78#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:03.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:45:03.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:45:03.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:45:03.78#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:45:03.78#ibcon#first serial, iclass 15, count 0 2006.161.07:45:03.78#ibcon#enter sib2, iclass 15, count 0 2006.161.07:45:03.78#ibcon#flushed, iclass 15, count 0 2006.161.07:45:03.78#ibcon#about to write, iclass 15, count 0 2006.161.07:45:03.78#ibcon#wrote, iclass 15, count 0 2006.161.07:45:03.78#ibcon#about to read 3, iclass 15, count 0 2006.161.07:45:03.80#ibcon#read 3, iclass 15, count 0 2006.161.07:45:03.80#ibcon#about to read 4, iclass 15, count 0 2006.161.07:45:03.80#ibcon#read 4, iclass 15, count 0 2006.161.07:45:03.80#ibcon#about to read 5, iclass 15, count 0 2006.161.07:45:03.80#ibcon#read 5, iclass 15, count 0 2006.161.07:45:03.80#ibcon#about to read 6, iclass 15, count 0 2006.161.07:45:03.80#ibcon#read 6, iclass 15, count 0 2006.161.07:45:03.80#ibcon#end of sib2, iclass 15, count 0 2006.161.07:45:03.80#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:45:03.80#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:45:03.80#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:45:03.80#ibcon#*before write, iclass 15, count 0 2006.161.07:45:03.80#ibcon#enter sib2, iclass 15, count 0 2006.161.07:45:03.80#ibcon#flushed, iclass 15, count 0 2006.161.07:45:03.80#ibcon#about to write, iclass 15, count 0 2006.161.07:45:03.80#ibcon#wrote, iclass 15, count 0 2006.161.07:45:03.80#ibcon#about to read 3, iclass 15, count 0 2006.161.07:45:03.84#ibcon#read 3, iclass 15, count 0 2006.161.07:45:03.84#ibcon#about to read 4, iclass 15, count 0 2006.161.07:45:03.84#ibcon#read 4, iclass 15, count 0 2006.161.07:45:03.84#ibcon#about to read 5, iclass 15, count 0 2006.161.07:45:03.84#ibcon#read 5, iclass 15, count 0 2006.161.07:45:03.84#ibcon#about to read 6, iclass 15, count 0 2006.161.07:45:03.84#ibcon#read 6, iclass 15, count 0 2006.161.07:45:03.84#ibcon#end of sib2, iclass 15, count 0 2006.161.07:45:03.84#ibcon#*after write, iclass 15, count 0 2006.161.07:45:03.84#ibcon#*before return 0, iclass 15, count 0 2006.161.07:45:03.84#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:45:03.84#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:45:03.84#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:45:03.84#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:45:03.84$vc4f8/vb=4,4 2006.161.07:45:03.84#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.07:45:03.84#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.07:45:03.84#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:03.84#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:45:03.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:45:03.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:45:03.90#ibcon#enter wrdev, iclass 17, count 2 2006.161.07:45:03.90#ibcon#first serial, iclass 17, count 2 2006.161.07:45:03.90#ibcon#enter sib2, iclass 17, count 2 2006.161.07:45:03.90#ibcon#flushed, iclass 17, count 2 2006.161.07:45:03.90#ibcon#about to write, iclass 17, count 2 2006.161.07:45:03.90#ibcon#wrote, iclass 17, count 2 2006.161.07:45:03.90#ibcon#about to read 3, iclass 17, count 2 2006.161.07:45:03.92#ibcon#read 3, iclass 17, count 2 2006.161.07:45:03.92#ibcon#about to read 4, iclass 17, count 2 2006.161.07:45:03.92#ibcon#read 4, iclass 17, count 2 2006.161.07:45:03.92#ibcon#about to read 5, iclass 17, count 2 2006.161.07:45:03.92#ibcon#read 5, iclass 17, count 2 2006.161.07:45:03.92#ibcon#about to read 6, iclass 17, count 2 2006.161.07:45:03.92#ibcon#read 6, iclass 17, count 2 2006.161.07:45:03.92#ibcon#end of sib2, iclass 17, count 2 2006.161.07:45:03.92#ibcon#*mode == 0, iclass 17, count 2 2006.161.07:45:03.92#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.07:45:03.92#ibcon#[27=AT04-04\r\n] 2006.161.07:45:03.92#ibcon#*before write, iclass 17, count 2 2006.161.07:45:03.92#ibcon#enter sib2, iclass 17, count 2 2006.161.07:45:03.92#ibcon#flushed, iclass 17, count 2 2006.161.07:45:03.92#ibcon#about to write, iclass 17, count 2 2006.161.07:45:03.92#ibcon#wrote, iclass 17, count 2 2006.161.07:45:03.92#ibcon#about to read 3, iclass 17, count 2 2006.161.07:45:03.95#ibcon#read 3, iclass 17, count 2 2006.161.07:45:03.95#ibcon#about to read 4, iclass 17, count 2 2006.161.07:45:03.95#ibcon#read 4, iclass 17, count 2 2006.161.07:45:03.95#ibcon#about to read 5, iclass 17, count 2 2006.161.07:45:03.95#ibcon#read 5, iclass 17, count 2 2006.161.07:45:03.95#ibcon#about to read 6, iclass 17, count 2 2006.161.07:45:03.95#ibcon#read 6, iclass 17, count 2 2006.161.07:45:03.95#ibcon#end of sib2, iclass 17, count 2 2006.161.07:45:03.95#ibcon#*after write, iclass 17, count 2 2006.161.07:45:03.95#ibcon#*before return 0, iclass 17, count 2 2006.161.07:45:03.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:45:03.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:45:03.95#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.07:45:03.95#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:03.95#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:45:04.07#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:45:04.07#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:45:04.07#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:45:04.07#ibcon#first serial, iclass 17, count 0 2006.161.07:45:04.07#ibcon#enter sib2, iclass 17, count 0 2006.161.07:45:04.07#ibcon#flushed, iclass 17, count 0 2006.161.07:45:04.07#ibcon#about to write, iclass 17, count 0 2006.161.07:45:04.07#ibcon#wrote, iclass 17, count 0 2006.161.07:45:04.07#ibcon#about to read 3, iclass 17, count 0 2006.161.07:45:04.09#ibcon#read 3, iclass 17, count 0 2006.161.07:45:04.09#ibcon#about to read 4, iclass 17, count 0 2006.161.07:45:04.09#ibcon#read 4, iclass 17, count 0 2006.161.07:45:04.09#ibcon#about to read 5, iclass 17, count 0 2006.161.07:45:04.09#ibcon#read 5, iclass 17, count 0 2006.161.07:45:04.09#ibcon#about to read 6, iclass 17, count 0 2006.161.07:45:04.09#ibcon#read 6, iclass 17, count 0 2006.161.07:45:04.09#ibcon#end of sib2, iclass 17, count 0 2006.161.07:45:04.09#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:45:04.09#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:45:04.09#ibcon#[27=USB\r\n] 2006.161.07:45:04.09#ibcon#*before write, iclass 17, count 0 2006.161.07:45:04.09#ibcon#enter sib2, iclass 17, count 0 2006.161.07:45:04.09#ibcon#flushed, iclass 17, count 0 2006.161.07:45:04.09#ibcon#about to write, iclass 17, count 0 2006.161.07:45:04.09#ibcon#wrote, iclass 17, count 0 2006.161.07:45:04.09#ibcon#about to read 3, iclass 17, count 0 2006.161.07:45:04.12#ibcon#read 3, iclass 17, count 0 2006.161.07:45:04.12#ibcon#about to read 4, iclass 17, count 0 2006.161.07:45:04.12#ibcon#read 4, iclass 17, count 0 2006.161.07:45:04.12#ibcon#about to read 5, iclass 17, count 0 2006.161.07:45:04.12#ibcon#read 5, iclass 17, count 0 2006.161.07:45:04.12#ibcon#about to read 6, iclass 17, count 0 2006.161.07:45:04.12#ibcon#read 6, iclass 17, count 0 2006.161.07:45:04.12#ibcon#end of sib2, iclass 17, count 0 2006.161.07:45:04.12#ibcon#*after write, iclass 17, count 0 2006.161.07:45:04.12#ibcon#*before return 0, iclass 17, count 0 2006.161.07:45:04.12#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:45:04.12#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:45:04.12#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:45:04.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:45:04.12$vc4f8/vblo=5,744.99 2006.161.07:45:04.12#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:45:04.12#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:45:04.12#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:04.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:04.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:04.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:04.12#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:45:04.12#ibcon#first serial, iclass 19, count 0 2006.161.07:45:04.12#ibcon#enter sib2, iclass 19, count 0 2006.161.07:45:04.12#ibcon#flushed, iclass 19, count 0 2006.161.07:45:04.12#ibcon#about to write, iclass 19, count 0 2006.161.07:45:04.12#ibcon#wrote, iclass 19, count 0 2006.161.07:45:04.12#ibcon#about to read 3, iclass 19, count 0 2006.161.07:45:04.14#ibcon#read 3, iclass 19, count 0 2006.161.07:45:04.14#ibcon#about to read 4, iclass 19, count 0 2006.161.07:45:04.14#ibcon#read 4, iclass 19, count 0 2006.161.07:45:04.14#ibcon#about to read 5, iclass 19, count 0 2006.161.07:45:04.14#ibcon#read 5, iclass 19, count 0 2006.161.07:45:04.14#ibcon#about to read 6, iclass 19, count 0 2006.161.07:45:04.14#ibcon#read 6, iclass 19, count 0 2006.161.07:45:04.14#ibcon#end of sib2, iclass 19, count 0 2006.161.07:45:04.14#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:45:04.14#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:45:04.14#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:45:04.14#ibcon#*before write, iclass 19, count 0 2006.161.07:45:04.14#ibcon#enter sib2, iclass 19, count 0 2006.161.07:45:04.14#ibcon#flushed, iclass 19, count 0 2006.161.07:45:04.14#ibcon#about to write, iclass 19, count 0 2006.161.07:45:04.14#ibcon#wrote, iclass 19, count 0 2006.161.07:45:04.14#ibcon#about to read 3, iclass 19, count 0 2006.161.07:45:04.18#ibcon#read 3, iclass 19, count 0 2006.161.07:45:04.18#ibcon#about to read 4, iclass 19, count 0 2006.161.07:45:04.18#ibcon#read 4, iclass 19, count 0 2006.161.07:45:04.18#ibcon#about to read 5, iclass 19, count 0 2006.161.07:45:04.18#ibcon#read 5, iclass 19, count 0 2006.161.07:45:04.18#ibcon#about to read 6, iclass 19, count 0 2006.161.07:45:04.18#ibcon#read 6, iclass 19, count 0 2006.161.07:45:04.18#ibcon#end of sib2, iclass 19, count 0 2006.161.07:45:04.18#ibcon#*after write, iclass 19, count 0 2006.161.07:45:04.18#ibcon#*before return 0, iclass 19, count 0 2006.161.07:45:04.18#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:04.18#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:45:04.18#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:45:04.18#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:45:04.18$vc4f8/vb=5,4 2006.161.07:45:04.18#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:45:04.18#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:45:04.18#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:04.18#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:04.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:04.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:04.25#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:45:04.25#ibcon#first serial, iclass 21, count 2 2006.161.07:45:04.25#ibcon#enter sib2, iclass 21, count 2 2006.161.07:45:04.25#ibcon#flushed, iclass 21, count 2 2006.161.07:45:04.25#ibcon#about to write, iclass 21, count 2 2006.161.07:45:04.25#ibcon#wrote, iclass 21, count 2 2006.161.07:45:04.25#ibcon#about to read 3, iclass 21, count 2 2006.161.07:45:04.27#ibcon#read 3, iclass 21, count 2 2006.161.07:45:04.27#ibcon#about to read 4, iclass 21, count 2 2006.161.07:45:04.27#ibcon#read 4, iclass 21, count 2 2006.161.07:45:04.27#ibcon#about to read 5, iclass 21, count 2 2006.161.07:45:04.27#ibcon#read 5, iclass 21, count 2 2006.161.07:45:04.27#ibcon#about to read 6, iclass 21, count 2 2006.161.07:45:04.27#ibcon#read 6, iclass 21, count 2 2006.161.07:45:04.27#ibcon#end of sib2, iclass 21, count 2 2006.161.07:45:04.27#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:45:04.27#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:45:04.27#ibcon#[27=AT05-04\r\n] 2006.161.07:45:04.27#ibcon#*before write, iclass 21, count 2 2006.161.07:45:04.27#ibcon#enter sib2, iclass 21, count 2 2006.161.07:45:04.27#ibcon#flushed, iclass 21, count 2 2006.161.07:45:04.27#ibcon#about to write, iclass 21, count 2 2006.161.07:45:04.27#ibcon#wrote, iclass 21, count 2 2006.161.07:45:04.27#ibcon#about to read 3, iclass 21, count 2 2006.161.07:45:04.30#ibcon#read 3, iclass 21, count 2 2006.161.07:45:04.30#ibcon#about to read 4, iclass 21, count 2 2006.161.07:45:04.30#ibcon#read 4, iclass 21, count 2 2006.161.07:45:04.30#ibcon#about to read 5, iclass 21, count 2 2006.161.07:45:04.30#ibcon#read 5, iclass 21, count 2 2006.161.07:45:04.30#ibcon#about to read 6, iclass 21, count 2 2006.161.07:45:04.30#ibcon#read 6, iclass 21, count 2 2006.161.07:45:04.30#ibcon#end of sib2, iclass 21, count 2 2006.161.07:45:04.30#ibcon#*after write, iclass 21, count 2 2006.161.07:45:04.30#ibcon#*before return 0, iclass 21, count 2 2006.161.07:45:04.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:04.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:45:04.30#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:45:04.30#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:04.30#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:04.42#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:04.42#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:04.42#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:45:04.42#ibcon#first serial, iclass 21, count 0 2006.161.07:45:04.42#ibcon#enter sib2, iclass 21, count 0 2006.161.07:45:04.42#ibcon#flushed, iclass 21, count 0 2006.161.07:45:04.42#ibcon#about to write, iclass 21, count 0 2006.161.07:45:04.42#ibcon#wrote, iclass 21, count 0 2006.161.07:45:04.42#ibcon#about to read 3, iclass 21, count 0 2006.161.07:45:04.44#ibcon#read 3, iclass 21, count 0 2006.161.07:45:04.44#ibcon#about to read 4, iclass 21, count 0 2006.161.07:45:04.44#ibcon#read 4, iclass 21, count 0 2006.161.07:45:04.44#ibcon#about to read 5, iclass 21, count 0 2006.161.07:45:04.44#ibcon#read 5, iclass 21, count 0 2006.161.07:45:04.44#ibcon#about to read 6, iclass 21, count 0 2006.161.07:45:04.44#ibcon#read 6, iclass 21, count 0 2006.161.07:45:04.44#ibcon#end of sib2, iclass 21, count 0 2006.161.07:45:04.44#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:45:04.44#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:45:04.44#ibcon#[27=USB\r\n] 2006.161.07:45:04.44#ibcon#*before write, iclass 21, count 0 2006.161.07:45:04.44#ibcon#enter sib2, iclass 21, count 0 2006.161.07:45:04.44#ibcon#flushed, iclass 21, count 0 2006.161.07:45:04.44#ibcon#about to write, iclass 21, count 0 2006.161.07:45:04.44#ibcon#wrote, iclass 21, count 0 2006.161.07:45:04.44#ibcon#about to read 3, iclass 21, count 0 2006.161.07:45:04.47#ibcon#read 3, iclass 21, count 0 2006.161.07:45:04.47#ibcon#about to read 4, iclass 21, count 0 2006.161.07:45:04.47#ibcon#read 4, iclass 21, count 0 2006.161.07:45:04.47#ibcon#about to read 5, iclass 21, count 0 2006.161.07:45:04.47#ibcon#read 5, iclass 21, count 0 2006.161.07:45:04.47#ibcon#about to read 6, iclass 21, count 0 2006.161.07:45:04.47#ibcon#read 6, iclass 21, count 0 2006.161.07:45:04.47#ibcon#end of sib2, iclass 21, count 0 2006.161.07:45:04.47#ibcon#*after write, iclass 21, count 0 2006.161.07:45:04.47#ibcon#*before return 0, iclass 21, count 0 2006.161.07:45:04.47#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:04.47#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:45:04.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:45:04.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:45:04.47$vc4f8/vblo=6,752.99 2006.161.07:45:04.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:45:04.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:45:04.47#ibcon#ireg 17 cls_cnt 0 2006.161.07:45:04.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:04.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:04.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:04.47#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:45:04.47#ibcon#first serial, iclass 23, count 0 2006.161.07:45:04.47#ibcon#enter sib2, iclass 23, count 0 2006.161.07:45:04.47#ibcon#flushed, iclass 23, count 0 2006.161.07:45:04.47#ibcon#about to write, iclass 23, count 0 2006.161.07:45:04.47#ibcon#wrote, iclass 23, count 0 2006.161.07:45:04.47#ibcon#about to read 3, iclass 23, count 0 2006.161.07:45:04.49#ibcon#read 3, iclass 23, count 0 2006.161.07:45:04.49#ibcon#about to read 4, iclass 23, count 0 2006.161.07:45:04.49#ibcon#read 4, iclass 23, count 0 2006.161.07:45:04.49#ibcon#about to read 5, iclass 23, count 0 2006.161.07:45:04.49#ibcon#read 5, iclass 23, count 0 2006.161.07:45:04.49#ibcon#about to read 6, iclass 23, count 0 2006.161.07:45:04.49#ibcon#read 6, iclass 23, count 0 2006.161.07:45:04.49#ibcon#end of sib2, iclass 23, count 0 2006.161.07:45:04.49#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:45:04.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:45:04.49#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:45:04.49#ibcon#*before write, iclass 23, count 0 2006.161.07:45:04.49#ibcon#enter sib2, iclass 23, count 0 2006.161.07:45:04.49#ibcon#flushed, iclass 23, count 0 2006.161.07:45:04.49#ibcon#about to write, iclass 23, count 0 2006.161.07:45:04.49#ibcon#wrote, iclass 23, count 0 2006.161.07:45:04.49#ibcon#about to read 3, iclass 23, count 0 2006.161.07:45:04.53#ibcon#read 3, iclass 23, count 0 2006.161.07:45:04.53#ibcon#about to read 4, iclass 23, count 0 2006.161.07:45:04.53#ibcon#read 4, iclass 23, count 0 2006.161.07:45:04.53#ibcon#about to read 5, iclass 23, count 0 2006.161.07:45:04.53#ibcon#read 5, iclass 23, count 0 2006.161.07:45:04.53#ibcon#about to read 6, iclass 23, count 0 2006.161.07:45:04.53#ibcon#read 6, iclass 23, count 0 2006.161.07:45:04.53#ibcon#end of sib2, iclass 23, count 0 2006.161.07:45:04.53#ibcon#*after write, iclass 23, count 0 2006.161.07:45:04.53#ibcon#*before return 0, iclass 23, count 0 2006.161.07:45:04.53#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:04.53#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:45:04.53#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:45:04.53#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:45:04.53$vc4f8/vb=6,4 2006.161.07:45:04.53#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:45:04.53#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:45:04.53#ibcon#ireg 11 cls_cnt 2 2006.161.07:45:04.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:04.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:04.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:04.59#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:45:04.59#ibcon#first serial, iclass 25, count 2 2006.161.07:45:04.59#ibcon#enter sib2, iclass 25, count 2 2006.161.07:45:04.59#ibcon#flushed, iclass 25, count 2 2006.161.07:45:04.59#ibcon#about to write, iclass 25, count 2 2006.161.07:45:04.59#ibcon#wrote, iclass 25, count 2 2006.161.07:45:04.59#ibcon#about to read 3, iclass 25, count 2 2006.161.07:45:04.61#ibcon#read 3, iclass 25, count 2 2006.161.07:45:04.61#ibcon#about to read 4, iclass 25, count 2 2006.161.07:45:04.61#ibcon#read 4, iclass 25, count 2 2006.161.07:45:04.61#ibcon#about to read 5, iclass 25, count 2 2006.161.07:45:04.61#ibcon#read 5, iclass 25, count 2 2006.161.07:45:04.61#ibcon#about to read 6, iclass 25, count 2 2006.161.07:45:04.61#ibcon#read 6, iclass 25, count 2 2006.161.07:45:04.61#ibcon#end of sib2, iclass 25, count 2 2006.161.07:45:04.61#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:45:04.61#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:45:04.61#ibcon#[27=AT06-04\r\n] 2006.161.07:45:04.61#ibcon#*before write, iclass 25, count 2 2006.161.07:45:04.61#ibcon#enter sib2, iclass 25, count 2 2006.161.07:45:04.61#ibcon#flushed, iclass 25, count 2 2006.161.07:45:04.61#ibcon#about to write, iclass 25, count 2 2006.161.07:45:04.61#ibcon#wrote, iclass 25, count 2 2006.161.07:45:04.61#ibcon#about to read 3, iclass 25, count 2 2006.161.07:45:04.64#ibcon#read 3, iclass 25, count 2 2006.161.07:45:04.64#ibcon#about to read 4, iclass 25, count 2 2006.161.07:45:04.64#ibcon#read 4, iclass 25, count 2 2006.161.07:45:04.64#ibcon#about to read 5, iclass 25, count 2 2006.161.07:45:04.64#ibcon#read 5, iclass 25, count 2 2006.161.07:45:04.64#ibcon#about to read 6, iclass 25, count 2 2006.161.07:45:04.64#ibcon#read 6, iclass 25, count 2 2006.161.07:45:04.64#ibcon#end of sib2, iclass 25, count 2 2006.161.07:45:04.64#ibcon#*after write, iclass 25, count 2 2006.161.07:45:04.64#ibcon#*before return 0, iclass 25, count 2 2006.161.07:45:04.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:04.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:45:04.64#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:45:04.64#ibcon#ireg 7 cls_cnt 0 2006.161.07:45:04.64#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:04.76#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:04.76#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:04.76#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:45:04.76#ibcon#first serial, iclass 25, count 0 2006.161.07:45:04.76#ibcon#enter sib2, iclass 25, count 0 2006.161.07:45:04.76#ibcon#flushed, iclass 25, count 0 2006.161.07:45:04.76#ibcon#about to write, iclass 25, count 0 2006.161.07:45:04.76#ibcon#wrote, iclass 25, count 0 2006.161.07:45:04.76#ibcon#about to read 3, iclass 25, count 0 2006.161.07:45:04.78#ibcon#read 3, iclass 25, count 0 2006.161.07:45:04.78#ibcon#about to read 4, iclass 25, count 0 2006.161.07:45:04.78#ibcon#read 4, iclass 25, count 0 2006.161.07:45:04.78#ibcon#about to read 5, iclass 25, count 0 2006.161.07:45:04.78#ibcon#read 5, iclass 25, count 0 2006.161.07:45:04.78#ibcon#about to read 6, iclass 25, count 0 2006.161.07:45:04.78#ibcon#read 6, iclass 25, count 0 2006.161.07:45:04.78#ibcon#end of sib2, iclass 25, count 0 2006.161.07:45:04.78#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:45:04.78#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:45:04.78#ibcon#[27=USB\r\n] 2006.161.07:45:04.78#ibcon#*before write, iclass 25, count 0 2006.161.07:45:04.78#ibcon#enter sib2, iclass 25, count 0 2006.161.07:45:04.78#ibcon#flushed, iclass 25, count 0 2006.161.07:45:04.78#ibcon#about to write, iclass 25, count 0 2006.161.07:45:04.78#ibcon#wrote, iclass 25, count 0 2006.161.07:45:04.78#ibcon#about to read 3, iclass 25, count 0 2006.161.07:45:04.81#ibcon#read 3, iclass 25, count 0 2006.161.07:45:04.81#ibcon#about to read 4, iclass 25, count 0 2006.161.07:45:04.81#ibcon#read 4, iclass 25, count 0 2006.161.07:45:04.81#ibcon#about to read 5, iclass 25, count 0 2006.161.07:45:04.81#ibcon#read 5, iclass 25, count 0 2006.161.07:45:04.81#ibcon#about to read 6, iclass 25, count 0 2006.161.07:45:04.81#ibcon#read 6, iclass 25, count 0 2006.161.07:45:04.81#ibcon#end of sib2, iclass 25, count 0 2006.161.07:45:04.81#ibcon#*after write, iclass 25, count 0 2006.161.07:45:04.81#ibcon#*before return 0, iclass 25, count 0 2006.161.07:45:04.81#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:04.81#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:45:04.81#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:45:04.81#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:45:04.81$vc4f8/vabw=wide 2006.161.07:45:04.81#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.07:45:04.81#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.07:45:04.81#ibcon#ireg 8 cls_cnt 0 2006.161.07:45:04.81#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:04.81#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:04.81#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:04.81#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:45:04.81#ibcon#first serial, iclass 27, count 0 2006.161.07:45:04.81#ibcon#enter sib2, iclass 27, count 0 2006.161.07:45:04.81#ibcon#flushed, iclass 27, count 0 2006.161.07:45:04.81#ibcon#about to write, iclass 27, count 0 2006.161.07:45:04.81#ibcon#wrote, iclass 27, count 0 2006.161.07:45:04.81#ibcon#about to read 3, iclass 27, count 0 2006.161.07:45:04.83#ibcon#read 3, iclass 27, count 0 2006.161.07:45:04.83#ibcon#about to read 4, iclass 27, count 0 2006.161.07:45:04.83#ibcon#read 4, iclass 27, count 0 2006.161.07:45:04.83#ibcon#about to read 5, iclass 27, count 0 2006.161.07:45:04.83#ibcon#read 5, iclass 27, count 0 2006.161.07:45:04.83#ibcon#about to read 6, iclass 27, count 0 2006.161.07:45:04.83#ibcon#read 6, iclass 27, count 0 2006.161.07:45:04.83#ibcon#end of sib2, iclass 27, count 0 2006.161.07:45:04.83#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:45:04.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:45:04.83#ibcon#[25=BW32\r\n] 2006.161.07:45:04.83#ibcon#*before write, iclass 27, count 0 2006.161.07:45:04.83#ibcon#enter sib2, iclass 27, count 0 2006.161.07:45:04.83#ibcon#flushed, iclass 27, count 0 2006.161.07:45:04.83#ibcon#about to write, iclass 27, count 0 2006.161.07:45:04.83#ibcon#wrote, iclass 27, count 0 2006.161.07:45:04.83#ibcon#about to read 3, iclass 27, count 0 2006.161.07:45:04.86#ibcon#read 3, iclass 27, count 0 2006.161.07:45:04.86#ibcon#about to read 4, iclass 27, count 0 2006.161.07:45:04.86#ibcon#read 4, iclass 27, count 0 2006.161.07:45:04.86#ibcon#about to read 5, iclass 27, count 0 2006.161.07:45:04.86#ibcon#read 5, iclass 27, count 0 2006.161.07:45:04.86#ibcon#about to read 6, iclass 27, count 0 2006.161.07:45:04.86#ibcon#read 6, iclass 27, count 0 2006.161.07:45:04.86#ibcon#end of sib2, iclass 27, count 0 2006.161.07:45:04.86#ibcon#*after write, iclass 27, count 0 2006.161.07:45:04.86#ibcon#*before return 0, iclass 27, count 0 2006.161.07:45:04.86#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:04.86#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:45:04.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:45:04.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:45:04.86$vc4f8/vbbw=wide 2006.161.07:45:04.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.07:45:04.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.07:45:04.86#ibcon#ireg 8 cls_cnt 0 2006.161.07:45:04.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:45:04.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:45:04.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:45:04.93#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:45:04.93#ibcon#first serial, iclass 29, count 0 2006.161.07:45:04.93#ibcon#enter sib2, iclass 29, count 0 2006.161.07:45:04.93#ibcon#flushed, iclass 29, count 0 2006.161.07:45:04.93#ibcon#about to write, iclass 29, count 0 2006.161.07:45:04.93#ibcon#wrote, iclass 29, count 0 2006.161.07:45:04.93#ibcon#about to read 3, iclass 29, count 0 2006.161.07:45:04.95#ibcon#read 3, iclass 29, count 0 2006.161.07:45:04.95#ibcon#about to read 4, iclass 29, count 0 2006.161.07:45:04.95#ibcon#read 4, iclass 29, count 0 2006.161.07:45:04.95#ibcon#about to read 5, iclass 29, count 0 2006.161.07:45:04.95#ibcon#read 5, iclass 29, count 0 2006.161.07:45:04.95#ibcon#about to read 6, iclass 29, count 0 2006.161.07:45:04.95#ibcon#read 6, iclass 29, count 0 2006.161.07:45:04.95#ibcon#end of sib2, iclass 29, count 0 2006.161.07:45:04.95#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:45:04.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:45:04.95#ibcon#[27=BW32\r\n] 2006.161.07:45:04.95#ibcon#*before write, iclass 29, count 0 2006.161.07:45:04.95#ibcon#enter sib2, iclass 29, count 0 2006.161.07:45:04.95#ibcon#flushed, iclass 29, count 0 2006.161.07:45:04.95#ibcon#about to write, iclass 29, count 0 2006.161.07:45:04.95#ibcon#wrote, iclass 29, count 0 2006.161.07:45:04.95#ibcon#about to read 3, iclass 29, count 0 2006.161.07:45:04.98#ibcon#read 3, iclass 29, count 0 2006.161.07:45:04.98#ibcon#about to read 4, iclass 29, count 0 2006.161.07:45:04.98#ibcon#read 4, iclass 29, count 0 2006.161.07:45:04.98#ibcon#about to read 5, iclass 29, count 0 2006.161.07:45:04.98#ibcon#read 5, iclass 29, count 0 2006.161.07:45:04.98#ibcon#about to read 6, iclass 29, count 0 2006.161.07:45:04.98#ibcon#read 6, iclass 29, count 0 2006.161.07:45:04.98#ibcon#end of sib2, iclass 29, count 0 2006.161.07:45:04.98#ibcon#*after write, iclass 29, count 0 2006.161.07:45:04.98#ibcon#*before return 0, iclass 29, count 0 2006.161.07:45:04.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:45:04.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:45:04.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:45:04.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:45:04.98$4f8m12a/ifd4f 2006.161.07:45:04.98$ifd4f/lo= 2006.161.07:45:04.98$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:45:04.98$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:45:04.98$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:45:04.98$ifd4f/patch= 2006.161.07:45:04.98$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:45:04.98$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:45:04.98$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:45:04.98$4f8m12a/"form=m,16.000,1:2 2006.161.07:45:04.98$4f8m12a/"tpicd 2006.161.07:45:04.98$4f8m12a/echo=off 2006.161.07:45:04.98$4f8m12a/xlog=off 2006.161.07:45:04.98:!2006.161.07:45:30 2006.161.07:45:10.14#trakl#Source acquired 2006.161.07:45:12.14#flagr#flagr/antenna,acquired 2006.161.07:45:30.00:preob 2006.161.07:45:31.14/onsource/TRACKING 2006.161.07:45:31.14:!2006.161.07:45:40 2006.161.07:45:40.00:data_valid=on 2006.161.07:45:40.00:midob 2006.161.07:45:40.14/onsource/TRACKING 2006.161.07:45:40.14/wx/24.09,1002.0,85 2006.161.07:45:40.28/cable/+6.5001E-03 2006.161.07:45:41.37/va/01,08,usb,yes,28,30 2006.161.07:45:41.37/va/02,07,usb,yes,29,30 2006.161.07:45:41.37/va/03,06,usb,yes,30,30 2006.161.07:45:41.37/va/04,07,usb,yes,29,31 2006.161.07:45:41.37/va/05,07,usb,yes,29,31 2006.161.07:45:41.37/va/06,06,usb,yes,28,28 2006.161.07:45:41.37/va/07,06,usb,yes,29,29 2006.161.07:45:41.37/va/08,07,usb,yes,27,27 2006.161.07:45:41.60/valo/01,532.99,yes,locked 2006.161.07:45:41.60/valo/02,572.99,yes,locked 2006.161.07:45:41.60/valo/03,672.99,yes,locked 2006.161.07:45:41.60/valo/04,832.99,yes,locked 2006.161.07:45:41.60/valo/05,652.99,yes,locked 2006.161.07:45:41.60/valo/06,772.99,yes,locked 2006.161.07:45:41.60/valo/07,832.99,yes,locked 2006.161.07:45:41.60/valo/08,852.99,yes,locked 2006.161.07:45:42.69/vb/01,04,usb,yes,28,27 2006.161.07:45:42.69/vb/02,04,usb,yes,30,32 2006.161.07:45:42.69/vb/03,04,usb,yes,27,30 2006.161.07:45:42.69/vb/04,04,usb,yes,28,28 2006.161.07:45:42.69/vb/05,04,usb,yes,26,30 2006.161.07:45:42.69/vb/06,04,usb,yes,27,30 2006.161.07:45:42.69/vb/07,04,usb,yes,29,29 2006.161.07:45:42.69/vb/08,04,usb,yes,27,30 2006.161.07:45:42.92/vblo/01,632.99,yes,locked 2006.161.07:45:42.92/vblo/02,640.99,yes,locked 2006.161.07:45:42.92/vblo/03,656.99,yes,locked 2006.161.07:45:42.92/vblo/04,712.99,yes,locked 2006.161.07:45:42.92/vblo/05,744.99,yes,locked 2006.161.07:45:42.92/vblo/06,752.99,yes,locked 2006.161.07:45:42.92/vblo/07,734.99,yes,locked 2006.161.07:45:42.92/vblo/08,744.99,yes,locked 2006.161.07:45:43.07/vabw/8 2006.161.07:45:43.22/vbbw/8 2006.161.07:45:43.31/xfe/off,on,14.5 2006.161.07:45:43.68/ifatt/23,28,28,28 2006.161.07:45:44.07/fmout-gps/S +4.47E-07 2006.161.07:45:44.15:!2006.161.07:46:40 2006.161.07:46:40.00:data_valid=off 2006.161.07:46:40.00:postob 2006.161.07:46:40.09/cable/+6.4988E-03 2006.161.07:46:40.09/wx/24.08,1002.0,85 2006.161.07:46:41.07/fmout-gps/S +4.47E-07 2006.161.07:46:41.07:scan_name=161-0747,k06161,60 2006.161.07:46:41.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.161.07:46:41.14#flagr#flagr/antenna,new-source 2006.161.07:46:42.14:checkk5 2006.161.07:46:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:46:42.99/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:46:43.42/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:46:43.85/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:46:44.48/chk_obsdata//k5ts1/T1610745??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:46:44.95/chk_obsdata//k5ts2/T1610745??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:46:45.38/chk_obsdata//k5ts3/T1610745??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:46:45.82/chk_obsdata//k5ts4/T1610745??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:46:46.64/k5log//k5ts1_log_newline 2006.161.07:46:47.58/k5log//k5ts2_log_newline 2006.161.07:46:48.35/k5log//k5ts3_log_newline 2006.161.07:46:49.17/k5log//k5ts4_log_newline 2006.161.07:46:49.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:46:49.24:4f8m12a=1 2006.161.07:46:49.24$4f8m12a/echo=on 2006.161.07:46:49.24$4f8m12a/pcalon 2006.161.07:46:49.24$pcalon/"no phase cal control is implemented here 2006.161.07:46:49.24$4f8m12a/"tpicd=stop 2006.161.07:46:49.24$4f8m12a/vc4f8 2006.161.07:46:49.24$vc4f8/valo=1,532.99 2006.161.07:46:49.24#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.07:46:49.24#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.07:46:49.24#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:49.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:49.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:49.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:49.24#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:46:49.24#ibcon#first serial, iclass 36, count 0 2006.161.07:46:49.24#ibcon#enter sib2, iclass 36, count 0 2006.161.07:46:49.24#ibcon#flushed, iclass 36, count 0 2006.161.07:46:49.24#ibcon#about to write, iclass 36, count 0 2006.161.07:46:49.24#ibcon#wrote, iclass 36, count 0 2006.161.07:46:49.24#ibcon#about to read 3, iclass 36, count 0 2006.161.07:46:49.26#ibcon#read 3, iclass 36, count 0 2006.161.07:46:49.26#ibcon#about to read 4, iclass 36, count 0 2006.161.07:46:49.26#ibcon#read 4, iclass 36, count 0 2006.161.07:46:49.26#ibcon#about to read 5, iclass 36, count 0 2006.161.07:46:49.26#ibcon#read 5, iclass 36, count 0 2006.161.07:46:49.26#ibcon#about to read 6, iclass 36, count 0 2006.161.07:46:49.26#ibcon#read 6, iclass 36, count 0 2006.161.07:46:49.26#ibcon#end of sib2, iclass 36, count 0 2006.161.07:46:49.26#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:46:49.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:46:49.26#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:46:49.26#ibcon#*before write, iclass 36, count 0 2006.161.07:46:49.26#ibcon#enter sib2, iclass 36, count 0 2006.161.07:46:49.26#ibcon#flushed, iclass 36, count 0 2006.161.07:46:49.26#ibcon#about to write, iclass 36, count 0 2006.161.07:46:49.26#ibcon#wrote, iclass 36, count 0 2006.161.07:46:49.26#ibcon#about to read 3, iclass 36, count 0 2006.161.07:46:49.31#ibcon#read 3, iclass 36, count 0 2006.161.07:46:49.31#ibcon#about to read 4, iclass 36, count 0 2006.161.07:46:49.31#ibcon#read 4, iclass 36, count 0 2006.161.07:46:49.31#ibcon#about to read 5, iclass 36, count 0 2006.161.07:46:49.31#ibcon#read 5, iclass 36, count 0 2006.161.07:46:49.31#ibcon#about to read 6, iclass 36, count 0 2006.161.07:46:49.31#ibcon#read 6, iclass 36, count 0 2006.161.07:46:49.31#ibcon#end of sib2, iclass 36, count 0 2006.161.07:46:49.31#ibcon#*after write, iclass 36, count 0 2006.161.07:46:49.31#ibcon#*before return 0, iclass 36, count 0 2006.161.07:46:49.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:49.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:49.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:46:49.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:46:49.31$vc4f8/va=1,8 2006.161.07:46:49.31#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.07:46:49.31#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.07:46:49.31#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:49.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:49.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:49.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:49.31#ibcon#enter wrdev, iclass 38, count 2 2006.161.07:46:49.31#ibcon#first serial, iclass 38, count 2 2006.161.07:46:49.31#ibcon#enter sib2, iclass 38, count 2 2006.161.07:46:49.31#ibcon#flushed, iclass 38, count 2 2006.161.07:46:49.31#ibcon#about to write, iclass 38, count 2 2006.161.07:46:49.31#ibcon#wrote, iclass 38, count 2 2006.161.07:46:49.31#ibcon#about to read 3, iclass 38, count 2 2006.161.07:46:49.33#ibcon#read 3, iclass 38, count 2 2006.161.07:46:49.33#ibcon#about to read 4, iclass 38, count 2 2006.161.07:46:49.33#ibcon#read 4, iclass 38, count 2 2006.161.07:46:49.33#ibcon#about to read 5, iclass 38, count 2 2006.161.07:46:49.33#ibcon#read 5, iclass 38, count 2 2006.161.07:46:49.33#ibcon#about to read 6, iclass 38, count 2 2006.161.07:46:49.33#ibcon#read 6, iclass 38, count 2 2006.161.07:46:49.33#ibcon#end of sib2, iclass 38, count 2 2006.161.07:46:49.33#ibcon#*mode == 0, iclass 38, count 2 2006.161.07:46:49.33#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.07:46:49.33#ibcon#[25=AT01-08\r\n] 2006.161.07:46:49.33#ibcon#*before write, iclass 38, count 2 2006.161.07:46:49.33#ibcon#enter sib2, iclass 38, count 2 2006.161.07:46:49.33#ibcon#flushed, iclass 38, count 2 2006.161.07:46:49.33#ibcon#about to write, iclass 38, count 2 2006.161.07:46:49.33#ibcon#wrote, iclass 38, count 2 2006.161.07:46:49.33#ibcon#about to read 3, iclass 38, count 2 2006.161.07:46:49.36#ibcon#read 3, iclass 38, count 2 2006.161.07:46:49.36#ibcon#about to read 4, iclass 38, count 2 2006.161.07:46:49.36#ibcon#read 4, iclass 38, count 2 2006.161.07:46:49.36#ibcon#about to read 5, iclass 38, count 2 2006.161.07:46:49.36#ibcon#read 5, iclass 38, count 2 2006.161.07:46:49.36#ibcon#about to read 6, iclass 38, count 2 2006.161.07:46:49.36#ibcon#read 6, iclass 38, count 2 2006.161.07:46:49.36#ibcon#end of sib2, iclass 38, count 2 2006.161.07:46:49.36#ibcon#*after write, iclass 38, count 2 2006.161.07:46:49.36#ibcon#*before return 0, iclass 38, count 2 2006.161.07:46:49.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:49.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:49.36#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.07:46:49.36#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:49.36#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:49.48#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:49.48#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:49.48#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:46:49.48#ibcon#first serial, iclass 38, count 0 2006.161.07:46:49.48#ibcon#enter sib2, iclass 38, count 0 2006.161.07:46:49.48#ibcon#flushed, iclass 38, count 0 2006.161.07:46:49.48#ibcon#about to write, iclass 38, count 0 2006.161.07:46:49.48#ibcon#wrote, iclass 38, count 0 2006.161.07:46:49.48#ibcon#about to read 3, iclass 38, count 0 2006.161.07:46:49.50#ibcon#read 3, iclass 38, count 0 2006.161.07:46:49.50#ibcon#about to read 4, iclass 38, count 0 2006.161.07:46:49.50#ibcon#read 4, iclass 38, count 0 2006.161.07:46:49.50#ibcon#about to read 5, iclass 38, count 0 2006.161.07:46:49.50#ibcon#read 5, iclass 38, count 0 2006.161.07:46:49.50#ibcon#about to read 6, iclass 38, count 0 2006.161.07:46:49.50#ibcon#read 6, iclass 38, count 0 2006.161.07:46:49.50#ibcon#end of sib2, iclass 38, count 0 2006.161.07:46:49.50#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:46:49.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:46:49.50#ibcon#[25=USB\r\n] 2006.161.07:46:49.50#ibcon#*before write, iclass 38, count 0 2006.161.07:46:49.50#ibcon#enter sib2, iclass 38, count 0 2006.161.07:46:49.50#ibcon#flushed, iclass 38, count 0 2006.161.07:46:49.50#ibcon#about to write, iclass 38, count 0 2006.161.07:46:49.50#ibcon#wrote, iclass 38, count 0 2006.161.07:46:49.50#ibcon#about to read 3, iclass 38, count 0 2006.161.07:46:49.53#ibcon#read 3, iclass 38, count 0 2006.161.07:46:49.53#ibcon#about to read 4, iclass 38, count 0 2006.161.07:46:49.53#ibcon#read 4, iclass 38, count 0 2006.161.07:46:49.53#ibcon#about to read 5, iclass 38, count 0 2006.161.07:46:49.53#ibcon#read 5, iclass 38, count 0 2006.161.07:46:49.53#ibcon#about to read 6, iclass 38, count 0 2006.161.07:46:49.53#ibcon#read 6, iclass 38, count 0 2006.161.07:46:49.53#ibcon#end of sib2, iclass 38, count 0 2006.161.07:46:49.53#ibcon#*after write, iclass 38, count 0 2006.161.07:46:49.53#ibcon#*before return 0, iclass 38, count 0 2006.161.07:46:49.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:49.53#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:49.53#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:46:49.53#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:46:49.53$vc4f8/valo=2,572.99 2006.161.07:46:49.53#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:46:49.53#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:46:49.53#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:49.53#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:49.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:49.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:49.53#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:46:49.53#ibcon#first serial, iclass 40, count 0 2006.161.07:46:49.53#ibcon#enter sib2, iclass 40, count 0 2006.161.07:46:49.53#ibcon#flushed, iclass 40, count 0 2006.161.07:46:49.53#ibcon#about to write, iclass 40, count 0 2006.161.07:46:49.53#ibcon#wrote, iclass 40, count 0 2006.161.07:46:49.53#ibcon#about to read 3, iclass 40, count 0 2006.161.07:46:49.55#ibcon#read 3, iclass 40, count 0 2006.161.07:46:49.55#ibcon#about to read 4, iclass 40, count 0 2006.161.07:46:49.55#ibcon#read 4, iclass 40, count 0 2006.161.07:46:49.55#ibcon#about to read 5, iclass 40, count 0 2006.161.07:46:49.55#ibcon#read 5, iclass 40, count 0 2006.161.07:46:49.55#ibcon#about to read 6, iclass 40, count 0 2006.161.07:46:49.55#ibcon#read 6, iclass 40, count 0 2006.161.07:46:49.55#ibcon#end of sib2, iclass 40, count 0 2006.161.07:46:49.55#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:46:49.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:46:49.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:46:49.55#ibcon#*before write, iclass 40, count 0 2006.161.07:46:49.55#ibcon#enter sib2, iclass 40, count 0 2006.161.07:46:49.55#ibcon#flushed, iclass 40, count 0 2006.161.07:46:49.55#ibcon#about to write, iclass 40, count 0 2006.161.07:46:49.55#ibcon#wrote, iclass 40, count 0 2006.161.07:46:49.55#ibcon#about to read 3, iclass 40, count 0 2006.161.07:46:49.59#ibcon#read 3, iclass 40, count 0 2006.161.07:46:49.59#ibcon#about to read 4, iclass 40, count 0 2006.161.07:46:49.59#ibcon#read 4, iclass 40, count 0 2006.161.07:46:49.59#ibcon#about to read 5, iclass 40, count 0 2006.161.07:46:49.59#ibcon#read 5, iclass 40, count 0 2006.161.07:46:49.59#ibcon#about to read 6, iclass 40, count 0 2006.161.07:46:49.59#ibcon#read 6, iclass 40, count 0 2006.161.07:46:49.59#ibcon#end of sib2, iclass 40, count 0 2006.161.07:46:49.59#ibcon#*after write, iclass 40, count 0 2006.161.07:46:49.59#ibcon#*before return 0, iclass 40, count 0 2006.161.07:46:49.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:49.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:49.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:46:49.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:46:49.59$vc4f8/va=2,7 2006.161.07:46:49.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:46:49.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:46:49.59#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:49.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:49.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:49.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:49.65#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:46:49.65#ibcon#first serial, iclass 4, count 2 2006.161.07:46:49.65#ibcon#enter sib2, iclass 4, count 2 2006.161.07:46:49.65#ibcon#flushed, iclass 4, count 2 2006.161.07:46:49.65#ibcon#about to write, iclass 4, count 2 2006.161.07:46:49.65#ibcon#wrote, iclass 4, count 2 2006.161.07:46:49.65#ibcon#about to read 3, iclass 4, count 2 2006.161.07:46:49.68#ibcon#read 3, iclass 4, count 2 2006.161.07:46:49.68#ibcon#about to read 4, iclass 4, count 2 2006.161.07:46:49.68#ibcon#read 4, iclass 4, count 2 2006.161.07:46:49.68#ibcon#about to read 5, iclass 4, count 2 2006.161.07:46:49.68#ibcon#read 5, iclass 4, count 2 2006.161.07:46:49.68#ibcon#about to read 6, iclass 4, count 2 2006.161.07:46:49.68#ibcon#read 6, iclass 4, count 2 2006.161.07:46:49.68#ibcon#end of sib2, iclass 4, count 2 2006.161.07:46:49.68#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:46:49.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:46:49.68#ibcon#[25=AT02-07\r\n] 2006.161.07:46:49.68#ibcon#*before write, iclass 4, count 2 2006.161.07:46:49.68#ibcon#enter sib2, iclass 4, count 2 2006.161.07:46:49.68#ibcon#flushed, iclass 4, count 2 2006.161.07:46:49.68#ibcon#about to write, iclass 4, count 2 2006.161.07:46:49.68#ibcon#wrote, iclass 4, count 2 2006.161.07:46:49.68#ibcon#about to read 3, iclass 4, count 2 2006.161.07:46:49.71#ibcon#read 3, iclass 4, count 2 2006.161.07:46:49.71#ibcon#about to read 4, iclass 4, count 2 2006.161.07:46:49.71#ibcon#read 4, iclass 4, count 2 2006.161.07:46:49.71#ibcon#about to read 5, iclass 4, count 2 2006.161.07:46:49.71#ibcon#read 5, iclass 4, count 2 2006.161.07:46:49.71#ibcon#about to read 6, iclass 4, count 2 2006.161.07:46:49.71#ibcon#read 6, iclass 4, count 2 2006.161.07:46:49.71#ibcon#end of sib2, iclass 4, count 2 2006.161.07:46:49.71#ibcon#*after write, iclass 4, count 2 2006.161.07:46:49.71#ibcon#*before return 0, iclass 4, count 2 2006.161.07:46:49.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:49.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:49.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:46:49.71#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:49.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:49.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:49.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:49.83#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:46:49.83#ibcon#first serial, iclass 4, count 0 2006.161.07:46:49.83#ibcon#enter sib2, iclass 4, count 0 2006.161.07:46:49.83#ibcon#flushed, iclass 4, count 0 2006.161.07:46:49.83#ibcon#about to write, iclass 4, count 0 2006.161.07:46:49.83#ibcon#wrote, iclass 4, count 0 2006.161.07:46:49.83#ibcon#about to read 3, iclass 4, count 0 2006.161.07:46:49.85#ibcon#read 3, iclass 4, count 0 2006.161.07:46:49.85#ibcon#about to read 4, iclass 4, count 0 2006.161.07:46:49.85#ibcon#read 4, iclass 4, count 0 2006.161.07:46:49.85#ibcon#about to read 5, iclass 4, count 0 2006.161.07:46:49.85#ibcon#read 5, iclass 4, count 0 2006.161.07:46:49.85#ibcon#about to read 6, iclass 4, count 0 2006.161.07:46:49.85#ibcon#read 6, iclass 4, count 0 2006.161.07:46:49.85#ibcon#end of sib2, iclass 4, count 0 2006.161.07:46:49.85#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:46:49.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:46:49.85#ibcon#[25=USB\r\n] 2006.161.07:46:49.85#ibcon#*before write, iclass 4, count 0 2006.161.07:46:49.85#ibcon#enter sib2, iclass 4, count 0 2006.161.07:46:49.85#ibcon#flushed, iclass 4, count 0 2006.161.07:46:49.85#ibcon#about to write, iclass 4, count 0 2006.161.07:46:49.85#ibcon#wrote, iclass 4, count 0 2006.161.07:46:49.85#ibcon#about to read 3, iclass 4, count 0 2006.161.07:46:49.88#ibcon#read 3, iclass 4, count 0 2006.161.07:46:49.88#ibcon#about to read 4, iclass 4, count 0 2006.161.07:46:49.88#ibcon#read 4, iclass 4, count 0 2006.161.07:46:49.88#ibcon#about to read 5, iclass 4, count 0 2006.161.07:46:49.88#ibcon#read 5, iclass 4, count 0 2006.161.07:46:49.88#ibcon#about to read 6, iclass 4, count 0 2006.161.07:46:49.88#ibcon#read 6, iclass 4, count 0 2006.161.07:46:49.88#ibcon#end of sib2, iclass 4, count 0 2006.161.07:46:49.88#ibcon#*after write, iclass 4, count 0 2006.161.07:46:49.88#ibcon#*before return 0, iclass 4, count 0 2006.161.07:46:49.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:49.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:49.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:46:49.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:46:49.88$vc4f8/valo=3,672.99 2006.161.07:46:49.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:46:49.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:46:49.88#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:49.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:46:49.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:46:49.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:46:49.88#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:46:49.88#ibcon#first serial, iclass 6, count 0 2006.161.07:46:49.88#ibcon#enter sib2, iclass 6, count 0 2006.161.07:46:49.88#ibcon#flushed, iclass 6, count 0 2006.161.07:46:49.88#ibcon#about to write, iclass 6, count 0 2006.161.07:46:49.88#ibcon#wrote, iclass 6, count 0 2006.161.07:46:49.88#ibcon#about to read 3, iclass 6, count 0 2006.161.07:46:49.90#ibcon#read 3, iclass 6, count 0 2006.161.07:46:49.90#ibcon#about to read 4, iclass 6, count 0 2006.161.07:46:49.90#ibcon#read 4, iclass 6, count 0 2006.161.07:46:49.90#ibcon#about to read 5, iclass 6, count 0 2006.161.07:46:49.90#ibcon#read 5, iclass 6, count 0 2006.161.07:46:49.90#ibcon#about to read 6, iclass 6, count 0 2006.161.07:46:49.90#ibcon#read 6, iclass 6, count 0 2006.161.07:46:49.90#ibcon#end of sib2, iclass 6, count 0 2006.161.07:46:49.90#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:46:49.90#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:46:49.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:46:49.90#ibcon#*before write, iclass 6, count 0 2006.161.07:46:49.90#ibcon#enter sib2, iclass 6, count 0 2006.161.07:46:49.90#ibcon#flushed, iclass 6, count 0 2006.161.07:46:49.90#ibcon#about to write, iclass 6, count 0 2006.161.07:46:49.90#ibcon#wrote, iclass 6, count 0 2006.161.07:46:49.90#ibcon#about to read 3, iclass 6, count 0 2006.161.07:46:49.94#ibcon#read 3, iclass 6, count 0 2006.161.07:46:49.94#ibcon#about to read 4, iclass 6, count 0 2006.161.07:46:49.94#ibcon#read 4, iclass 6, count 0 2006.161.07:46:49.94#ibcon#about to read 5, iclass 6, count 0 2006.161.07:46:49.94#ibcon#read 5, iclass 6, count 0 2006.161.07:46:49.94#ibcon#about to read 6, iclass 6, count 0 2006.161.07:46:49.94#ibcon#read 6, iclass 6, count 0 2006.161.07:46:49.94#ibcon#end of sib2, iclass 6, count 0 2006.161.07:46:49.94#ibcon#*after write, iclass 6, count 0 2006.161.07:46:49.94#ibcon#*before return 0, iclass 6, count 0 2006.161.07:46:49.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:46:49.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:46:49.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:46:49.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:46:49.94$vc4f8/va=3,6 2006.161.07:46:49.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:46:49.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:46:49.94#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:49.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:46:50.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:46:50.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:46:50.00#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:46:50.00#ibcon#first serial, iclass 10, count 2 2006.161.07:46:50.00#ibcon#enter sib2, iclass 10, count 2 2006.161.07:46:50.00#ibcon#flushed, iclass 10, count 2 2006.161.07:46:50.00#ibcon#about to write, iclass 10, count 2 2006.161.07:46:50.00#ibcon#wrote, iclass 10, count 2 2006.161.07:46:50.00#ibcon#about to read 3, iclass 10, count 2 2006.161.07:46:50.02#ibcon#read 3, iclass 10, count 2 2006.161.07:46:50.02#ibcon#about to read 4, iclass 10, count 2 2006.161.07:46:50.02#ibcon#read 4, iclass 10, count 2 2006.161.07:46:50.02#ibcon#about to read 5, iclass 10, count 2 2006.161.07:46:50.02#ibcon#read 5, iclass 10, count 2 2006.161.07:46:50.02#ibcon#about to read 6, iclass 10, count 2 2006.161.07:46:50.02#ibcon#read 6, iclass 10, count 2 2006.161.07:46:50.02#ibcon#end of sib2, iclass 10, count 2 2006.161.07:46:50.02#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:46:50.02#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:46:50.02#ibcon#[25=AT03-06\r\n] 2006.161.07:46:50.02#ibcon#*before write, iclass 10, count 2 2006.161.07:46:50.02#ibcon#enter sib2, iclass 10, count 2 2006.161.07:46:50.02#ibcon#flushed, iclass 10, count 2 2006.161.07:46:50.02#ibcon#about to write, iclass 10, count 2 2006.161.07:46:50.02#ibcon#wrote, iclass 10, count 2 2006.161.07:46:50.02#ibcon#about to read 3, iclass 10, count 2 2006.161.07:46:50.05#ibcon#read 3, iclass 10, count 2 2006.161.07:46:50.05#ibcon#about to read 4, iclass 10, count 2 2006.161.07:46:50.05#ibcon#read 4, iclass 10, count 2 2006.161.07:46:50.05#ibcon#about to read 5, iclass 10, count 2 2006.161.07:46:50.05#ibcon#read 5, iclass 10, count 2 2006.161.07:46:50.05#ibcon#about to read 6, iclass 10, count 2 2006.161.07:46:50.05#ibcon#read 6, iclass 10, count 2 2006.161.07:46:50.05#ibcon#end of sib2, iclass 10, count 2 2006.161.07:46:50.05#ibcon#*after write, iclass 10, count 2 2006.161.07:46:50.05#ibcon#*before return 0, iclass 10, count 2 2006.161.07:46:50.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:46:50.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:46:50.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:46:50.05#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:50.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:46:50.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:46:50.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:46:50.17#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:46:50.17#ibcon#first serial, iclass 10, count 0 2006.161.07:46:50.17#ibcon#enter sib2, iclass 10, count 0 2006.161.07:46:50.17#ibcon#flushed, iclass 10, count 0 2006.161.07:46:50.17#ibcon#about to write, iclass 10, count 0 2006.161.07:46:50.17#ibcon#wrote, iclass 10, count 0 2006.161.07:46:50.17#ibcon#about to read 3, iclass 10, count 0 2006.161.07:46:50.19#ibcon#read 3, iclass 10, count 0 2006.161.07:46:50.19#ibcon#about to read 4, iclass 10, count 0 2006.161.07:46:50.19#ibcon#read 4, iclass 10, count 0 2006.161.07:46:50.19#ibcon#about to read 5, iclass 10, count 0 2006.161.07:46:50.19#ibcon#read 5, iclass 10, count 0 2006.161.07:46:50.19#ibcon#about to read 6, iclass 10, count 0 2006.161.07:46:50.19#ibcon#read 6, iclass 10, count 0 2006.161.07:46:50.19#ibcon#end of sib2, iclass 10, count 0 2006.161.07:46:50.19#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:46:50.19#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:46:50.19#ibcon#[25=USB\r\n] 2006.161.07:46:50.19#ibcon#*before write, iclass 10, count 0 2006.161.07:46:50.19#ibcon#enter sib2, iclass 10, count 0 2006.161.07:46:50.19#ibcon#flushed, iclass 10, count 0 2006.161.07:46:50.19#ibcon#about to write, iclass 10, count 0 2006.161.07:46:50.19#ibcon#wrote, iclass 10, count 0 2006.161.07:46:50.19#ibcon#about to read 3, iclass 10, count 0 2006.161.07:46:50.22#ibcon#read 3, iclass 10, count 0 2006.161.07:46:50.22#ibcon#about to read 4, iclass 10, count 0 2006.161.07:46:50.22#ibcon#read 4, iclass 10, count 0 2006.161.07:46:50.22#ibcon#about to read 5, iclass 10, count 0 2006.161.07:46:50.22#ibcon#read 5, iclass 10, count 0 2006.161.07:46:50.22#ibcon#about to read 6, iclass 10, count 0 2006.161.07:46:50.22#ibcon#read 6, iclass 10, count 0 2006.161.07:46:50.22#ibcon#end of sib2, iclass 10, count 0 2006.161.07:46:50.22#ibcon#*after write, iclass 10, count 0 2006.161.07:46:50.22#ibcon#*before return 0, iclass 10, count 0 2006.161.07:46:50.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:46:50.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:46:50.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:46:50.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:46:50.22$vc4f8/valo=4,832.99 2006.161.07:46:50.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:46:50.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:46:50.22#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:50.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:46:50.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:46:50.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:46:50.22#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:46:50.22#ibcon#first serial, iclass 12, count 0 2006.161.07:46:50.22#ibcon#enter sib2, iclass 12, count 0 2006.161.07:46:50.22#ibcon#flushed, iclass 12, count 0 2006.161.07:46:50.22#ibcon#about to write, iclass 12, count 0 2006.161.07:46:50.22#ibcon#wrote, iclass 12, count 0 2006.161.07:46:50.22#ibcon#about to read 3, iclass 12, count 0 2006.161.07:46:50.24#ibcon#read 3, iclass 12, count 0 2006.161.07:46:50.24#ibcon#about to read 4, iclass 12, count 0 2006.161.07:46:50.24#ibcon#read 4, iclass 12, count 0 2006.161.07:46:50.24#ibcon#about to read 5, iclass 12, count 0 2006.161.07:46:50.24#ibcon#read 5, iclass 12, count 0 2006.161.07:46:50.24#ibcon#about to read 6, iclass 12, count 0 2006.161.07:46:50.24#ibcon#read 6, iclass 12, count 0 2006.161.07:46:50.24#ibcon#end of sib2, iclass 12, count 0 2006.161.07:46:50.24#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:46:50.24#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:46:50.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:46:50.24#ibcon#*before write, iclass 12, count 0 2006.161.07:46:50.24#ibcon#enter sib2, iclass 12, count 0 2006.161.07:46:50.24#ibcon#flushed, iclass 12, count 0 2006.161.07:46:50.24#ibcon#about to write, iclass 12, count 0 2006.161.07:46:50.24#ibcon#wrote, iclass 12, count 0 2006.161.07:46:50.24#ibcon#about to read 3, iclass 12, count 0 2006.161.07:46:50.28#ibcon#read 3, iclass 12, count 0 2006.161.07:46:50.28#ibcon#about to read 4, iclass 12, count 0 2006.161.07:46:50.28#ibcon#read 4, iclass 12, count 0 2006.161.07:46:50.28#ibcon#about to read 5, iclass 12, count 0 2006.161.07:46:50.28#ibcon#read 5, iclass 12, count 0 2006.161.07:46:50.28#ibcon#about to read 6, iclass 12, count 0 2006.161.07:46:50.28#ibcon#read 6, iclass 12, count 0 2006.161.07:46:50.28#ibcon#end of sib2, iclass 12, count 0 2006.161.07:46:50.28#ibcon#*after write, iclass 12, count 0 2006.161.07:46:50.28#ibcon#*before return 0, iclass 12, count 0 2006.161.07:46:50.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:46:50.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:46:50.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:46:50.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:46:50.28$vc4f8/va=4,7 2006.161.07:46:50.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:46:50.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:46:50.28#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:50.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:50.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:50.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:50.34#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:46:50.34#ibcon#first serial, iclass 14, count 2 2006.161.07:46:50.34#ibcon#enter sib2, iclass 14, count 2 2006.161.07:46:50.34#ibcon#flushed, iclass 14, count 2 2006.161.07:46:50.34#ibcon#about to write, iclass 14, count 2 2006.161.07:46:50.34#ibcon#wrote, iclass 14, count 2 2006.161.07:46:50.34#ibcon#about to read 3, iclass 14, count 2 2006.161.07:46:50.36#ibcon#read 3, iclass 14, count 2 2006.161.07:46:50.36#ibcon#about to read 4, iclass 14, count 2 2006.161.07:46:50.36#ibcon#read 4, iclass 14, count 2 2006.161.07:46:50.36#ibcon#about to read 5, iclass 14, count 2 2006.161.07:46:50.36#ibcon#read 5, iclass 14, count 2 2006.161.07:46:50.36#ibcon#about to read 6, iclass 14, count 2 2006.161.07:46:50.36#ibcon#read 6, iclass 14, count 2 2006.161.07:46:50.36#ibcon#end of sib2, iclass 14, count 2 2006.161.07:46:50.36#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:46:50.36#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:46:50.36#ibcon#[25=AT04-07\r\n] 2006.161.07:46:50.36#ibcon#*before write, iclass 14, count 2 2006.161.07:46:50.36#ibcon#enter sib2, iclass 14, count 2 2006.161.07:46:50.36#ibcon#flushed, iclass 14, count 2 2006.161.07:46:50.36#ibcon#about to write, iclass 14, count 2 2006.161.07:46:50.36#ibcon#wrote, iclass 14, count 2 2006.161.07:46:50.36#ibcon#about to read 3, iclass 14, count 2 2006.161.07:46:50.39#ibcon#read 3, iclass 14, count 2 2006.161.07:46:50.39#ibcon#about to read 4, iclass 14, count 2 2006.161.07:46:50.39#ibcon#read 4, iclass 14, count 2 2006.161.07:46:50.39#ibcon#about to read 5, iclass 14, count 2 2006.161.07:46:50.39#ibcon#read 5, iclass 14, count 2 2006.161.07:46:50.39#ibcon#about to read 6, iclass 14, count 2 2006.161.07:46:50.39#ibcon#read 6, iclass 14, count 2 2006.161.07:46:50.39#ibcon#end of sib2, iclass 14, count 2 2006.161.07:46:50.39#ibcon#*after write, iclass 14, count 2 2006.161.07:46:50.39#ibcon#*before return 0, iclass 14, count 2 2006.161.07:46:50.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:50.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:50.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:46:50.39#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:50.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:50.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:50.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:50.51#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:46:50.51#ibcon#first serial, iclass 14, count 0 2006.161.07:46:50.51#ibcon#enter sib2, iclass 14, count 0 2006.161.07:46:50.51#ibcon#flushed, iclass 14, count 0 2006.161.07:46:50.51#ibcon#about to write, iclass 14, count 0 2006.161.07:46:50.51#ibcon#wrote, iclass 14, count 0 2006.161.07:46:50.51#ibcon#about to read 3, iclass 14, count 0 2006.161.07:46:50.53#ibcon#read 3, iclass 14, count 0 2006.161.07:46:50.53#ibcon#about to read 4, iclass 14, count 0 2006.161.07:46:50.53#ibcon#read 4, iclass 14, count 0 2006.161.07:46:50.53#ibcon#about to read 5, iclass 14, count 0 2006.161.07:46:50.53#ibcon#read 5, iclass 14, count 0 2006.161.07:46:50.53#ibcon#about to read 6, iclass 14, count 0 2006.161.07:46:50.53#ibcon#read 6, iclass 14, count 0 2006.161.07:46:50.53#ibcon#end of sib2, iclass 14, count 0 2006.161.07:46:50.53#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:46:50.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:46:50.53#ibcon#[25=USB\r\n] 2006.161.07:46:50.53#ibcon#*before write, iclass 14, count 0 2006.161.07:46:50.53#ibcon#enter sib2, iclass 14, count 0 2006.161.07:46:50.53#ibcon#flushed, iclass 14, count 0 2006.161.07:46:50.53#ibcon#about to write, iclass 14, count 0 2006.161.07:46:50.53#ibcon#wrote, iclass 14, count 0 2006.161.07:46:50.53#ibcon#about to read 3, iclass 14, count 0 2006.161.07:46:50.56#ibcon#read 3, iclass 14, count 0 2006.161.07:46:50.56#ibcon#about to read 4, iclass 14, count 0 2006.161.07:46:50.56#ibcon#read 4, iclass 14, count 0 2006.161.07:46:50.56#ibcon#about to read 5, iclass 14, count 0 2006.161.07:46:50.56#ibcon#read 5, iclass 14, count 0 2006.161.07:46:50.56#ibcon#about to read 6, iclass 14, count 0 2006.161.07:46:50.56#ibcon#read 6, iclass 14, count 0 2006.161.07:46:50.56#ibcon#end of sib2, iclass 14, count 0 2006.161.07:46:50.56#ibcon#*after write, iclass 14, count 0 2006.161.07:46:50.56#ibcon#*before return 0, iclass 14, count 0 2006.161.07:46:50.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:50.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:50.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:46:50.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:46:50.56$vc4f8/valo=5,652.99 2006.161.07:46:50.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:46:50.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:46:50.56#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:50.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:50.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:50.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:50.56#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:46:50.56#ibcon#first serial, iclass 16, count 0 2006.161.07:46:50.56#ibcon#enter sib2, iclass 16, count 0 2006.161.07:46:50.56#ibcon#flushed, iclass 16, count 0 2006.161.07:46:50.56#ibcon#about to write, iclass 16, count 0 2006.161.07:46:50.56#ibcon#wrote, iclass 16, count 0 2006.161.07:46:50.56#ibcon#about to read 3, iclass 16, count 0 2006.161.07:46:50.58#ibcon#read 3, iclass 16, count 0 2006.161.07:46:50.58#ibcon#about to read 4, iclass 16, count 0 2006.161.07:46:50.58#ibcon#read 4, iclass 16, count 0 2006.161.07:46:50.58#ibcon#about to read 5, iclass 16, count 0 2006.161.07:46:50.58#ibcon#read 5, iclass 16, count 0 2006.161.07:46:50.58#ibcon#about to read 6, iclass 16, count 0 2006.161.07:46:50.58#ibcon#read 6, iclass 16, count 0 2006.161.07:46:50.58#ibcon#end of sib2, iclass 16, count 0 2006.161.07:46:50.58#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:46:50.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:46:50.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:46:50.58#ibcon#*before write, iclass 16, count 0 2006.161.07:46:50.58#ibcon#enter sib2, iclass 16, count 0 2006.161.07:46:50.58#ibcon#flushed, iclass 16, count 0 2006.161.07:46:50.58#ibcon#about to write, iclass 16, count 0 2006.161.07:46:50.58#ibcon#wrote, iclass 16, count 0 2006.161.07:46:50.58#ibcon#about to read 3, iclass 16, count 0 2006.161.07:46:50.62#ibcon#read 3, iclass 16, count 0 2006.161.07:46:50.62#ibcon#about to read 4, iclass 16, count 0 2006.161.07:46:50.62#ibcon#read 4, iclass 16, count 0 2006.161.07:46:50.62#ibcon#about to read 5, iclass 16, count 0 2006.161.07:46:50.62#ibcon#read 5, iclass 16, count 0 2006.161.07:46:50.62#ibcon#about to read 6, iclass 16, count 0 2006.161.07:46:50.62#ibcon#read 6, iclass 16, count 0 2006.161.07:46:50.62#ibcon#end of sib2, iclass 16, count 0 2006.161.07:46:50.62#ibcon#*after write, iclass 16, count 0 2006.161.07:46:50.62#ibcon#*before return 0, iclass 16, count 0 2006.161.07:46:50.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:50.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:50.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:46:50.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:46:50.62$vc4f8/va=5,7 2006.161.07:46:50.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:46:50.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:46:50.62#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:50.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:50.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:50.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:50.68#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:46:50.68#ibcon#first serial, iclass 18, count 2 2006.161.07:46:50.68#ibcon#enter sib2, iclass 18, count 2 2006.161.07:46:50.68#ibcon#flushed, iclass 18, count 2 2006.161.07:46:50.68#ibcon#about to write, iclass 18, count 2 2006.161.07:46:50.68#ibcon#wrote, iclass 18, count 2 2006.161.07:46:50.68#ibcon#about to read 3, iclass 18, count 2 2006.161.07:46:50.70#ibcon#read 3, iclass 18, count 2 2006.161.07:46:50.70#ibcon#about to read 4, iclass 18, count 2 2006.161.07:46:50.70#ibcon#read 4, iclass 18, count 2 2006.161.07:46:50.70#ibcon#about to read 5, iclass 18, count 2 2006.161.07:46:50.70#ibcon#read 5, iclass 18, count 2 2006.161.07:46:50.70#ibcon#about to read 6, iclass 18, count 2 2006.161.07:46:50.70#ibcon#read 6, iclass 18, count 2 2006.161.07:46:50.70#ibcon#end of sib2, iclass 18, count 2 2006.161.07:46:50.70#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:46:50.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:46:50.70#ibcon#[25=AT05-07\r\n] 2006.161.07:46:50.70#ibcon#*before write, iclass 18, count 2 2006.161.07:46:50.70#ibcon#enter sib2, iclass 18, count 2 2006.161.07:46:50.70#ibcon#flushed, iclass 18, count 2 2006.161.07:46:50.70#ibcon#about to write, iclass 18, count 2 2006.161.07:46:50.70#ibcon#wrote, iclass 18, count 2 2006.161.07:46:50.70#ibcon#about to read 3, iclass 18, count 2 2006.161.07:46:50.73#ibcon#read 3, iclass 18, count 2 2006.161.07:46:50.73#ibcon#about to read 4, iclass 18, count 2 2006.161.07:46:50.73#ibcon#read 4, iclass 18, count 2 2006.161.07:46:50.73#ibcon#about to read 5, iclass 18, count 2 2006.161.07:46:50.73#ibcon#read 5, iclass 18, count 2 2006.161.07:46:50.73#ibcon#about to read 6, iclass 18, count 2 2006.161.07:46:50.73#ibcon#read 6, iclass 18, count 2 2006.161.07:46:50.73#ibcon#end of sib2, iclass 18, count 2 2006.161.07:46:50.73#ibcon#*after write, iclass 18, count 2 2006.161.07:46:50.73#ibcon#*before return 0, iclass 18, count 2 2006.161.07:46:50.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:50.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:50.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:46:50.73#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:50.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:50.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:50.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:50.85#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:46:50.85#ibcon#first serial, iclass 18, count 0 2006.161.07:46:50.85#ibcon#enter sib2, iclass 18, count 0 2006.161.07:46:50.85#ibcon#flushed, iclass 18, count 0 2006.161.07:46:50.85#ibcon#about to write, iclass 18, count 0 2006.161.07:46:50.85#ibcon#wrote, iclass 18, count 0 2006.161.07:46:50.85#ibcon#about to read 3, iclass 18, count 0 2006.161.07:46:50.87#ibcon#read 3, iclass 18, count 0 2006.161.07:46:50.87#ibcon#about to read 4, iclass 18, count 0 2006.161.07:46:50.87#ibcon#read 4, iclass 18, count 0 2006.161.07:46:50.87#ibcon#about to read 5, iclass 18, count 0 2006.161.07:46:50.87#ibcon#read 5, iclass 18, count 0 2006.161.07:46:50.87#ibcon#about to read 6, iclass 18, count 0 2006.161.07:46:50.87#ibcon#read 6, iclass 18, count 0 2006.161.07:46:50.87#ibcon#end of sib2, iclass 18, count 0 2006.161.07:46:50.87#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:46:50.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:46:50.87#ibcon#[25=USB\r\n] 2006.161.07:46:50.87#ibcon#*before write, iclass 18, count 0 2006.161.07:46:50.87#ibcon#enter sib2, iclass 18, count 0 2006.161.07:46:50.87#ibcon#flushed, iclass 18, count 0 2006.161.07:46:50.87#ibcon#about to write, iclass 18, count 0 2006.161.07:46:50.87#ibcon#wrote, iclass 18, count 0 2006.161.07:46:50.87#ibcon#about to read 3, iclass 18, count 0 2006.161.07:46:50.90#ibcon#read 3, iclass 18, count 0 2006.161.07:46:50.90#ibcon#about to read 4, iclass 18, count 0 2006.161.07:46:50.90#ibcon#read 4, iclass 18, count 0 2006.161.07:46:50.90#ibcon#about to read 5, iclass 18, count 0 2006.161.07:46:50.90#ibcon#read 5, iclass 18, count 0 2006.161.07:46:50.90#ibcon#about to read 6, iclass 18, count 0 2006.161.07:46:50.90#ibcon#read 6, iclass 18, count 0 2006.161.07:46:50.90#ibcon#end of sib2, iclass 18, count 0 2006.161.07:46:50.90#ibcon#*after write, iclass 18, count 0 2006.161.07:46:50.90#ibcon#*before return 0, iclass 18, count 0 2006.161.07:46:50.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:50.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:50.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:46:50.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:46:50.90$vc4f8/valo=6,772.99 2006.161.07:46:50.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:46:50.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:46:50.90#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:50.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:50.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:50.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:50.90#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:46:50.90#ibcon#first serial, iclass 20, count 0 2006.161.07:46:50.90#ibcon#enter sib2, iclass 20, count 0 2006.161.07:46:50.90#ibcon#flushed, iclass 20, count 0 2006.161.07:46:50.90#ibcon#about to write, iclass 20, count 0 2006.161.07:46:50.90#ibcon#wrote, iclass 20, count 0 2006.161.07:46:50.90#ibcon#about to read 3, iclass 20, count 0 2006.161.07:46:50.92#ibcon#read 3, iclass 20, count 0 2006.161.07:46:50.92#ibcon#about to read 4, iclass 20, count 0 2006.161.07:46:50.92#ibcon#read 4, iclass 20, count 0 2006.161.07:46:50.92#ibcon#about to read 5, iclass 20, count 0 2006.161.07:46:50.92#ibcon#read 5, iclass 20, count 0 2006.161.07:46:50.92#ibcon#about to read 6, iclass 20, count 0 2006.161.07:46:50.92#ibcon#read 6, iclass 20, count 0 2006.161.07:46:50.92#ibcon#end of sib2, iclass 20, count 0 2006.161.07:46:50.92#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:46:50.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:46:50.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:46:50.92#ibcon#*before write, iclass 20, count 0 2006.161.07:46:50.92#ibcon#enter sib2, iclass 20, count 0 2006.161.07:46:50.92#ibcon#flushed, iclass 20, count 0 2006.161.07:46:50.92#ibcon#about to write, iclass 20, count 0 2006.161.07:46:50.92#ibcon#wrote, iclass 20, count 0 2006.161.07:46:50.92#ibcon#about to read 3, iclass 20, count 0 2006.161.07:46:50.96#ibcon#read 3, iclass 20, count 0 2006.161.07:46:50.96#ibcon#about to read 4, iclass 20, count 0 2006.161.07:46:50.96#ibcon#read 4, iclass 20, count 0 2006.161.07:46:50.96#ibcon#about to read 5, iclass 20, count 0 2006.161.07:46:50.96#ibcon#read 5, iclass 20, count 0 2006.161.07:46:50.96#ibcon#about to read 6, iclass 20, count 0 2006.161.07:46:50.96#ibcon#read 6, iclass 20, count 0 2006.161.07:46:50.96#ibcon#end of sib2, iclass 20, count 0 2006.161.07:46:50.96#ibcon#*after write, iclass 20, count 0 2006.161.07:46:50.96#ibcon#*before return 0, iclass 20, count 0 2006.161.07:46:50.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:50.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:50.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:46:50.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:46:50.96$vc4f8/va=6,6 2006.161.07:46:50.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:46:50.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:46:50.96#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:50.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:51.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:51.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:51.02#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:46:51.02#ibcon#first serial, iclass 22, count 2 2006.161.07:46:51.02#ibcon#enter sib2, iclass 22, count 2 2006.161.07:46:51.02#ibcon#flushed, iclass 22, count 2 2006.161.07:46:51.02#ibcon#about to write, iclass 22, count 2 2006.161.07:46:51.02#ibcon#wrote, iclass 22, count 2 2006.161.07:46:51.02#ibcon#about to read 3, iclass 22, count 2 2006.161.07:46:51.04#ibcon#read 3, iclass 22, count 2 2006.161.07:46:51.04#ibcon#about to read 4, iclass 22, count 2 2006.161.07:46:51.04#ibcon#read 4, iclass 22, count 2 2006.161.07:46:51.04#ibcon#about to read 5, iclass 22, count 2 2006.161.07:46:51.04#ibcon#read 5, iclass 22, count 2 2006.161.07:46:51.04#ibcon#about to read 6, iclass 22, count 2 2006.161.07:46:51.04#ibcon#read 6, iclass 22, count 2 2006.161.07:46:51.04#ibcon#end of sib2, iclass 22, count 2 2006.161.07:46:51.04#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:46:51.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:46:51.04#ibcon#[25=AT06-06\r\n] 2006.161.07:46:51.04#ibcon#*before write, iclass 22, count 2 2006.161.07:46:51.04#ibcon#enter sib2, iclass 22, count 2 2006.161.07:46:51.04#ibcon#flushed, iclass 22, count 2 2006.161.07:46:51.04#ibcon#about to write, iclass 22, count 2 2006.161.07:46:51.04#ibcon#wrote, iclass 22, count 2 2006.161.07:46:51.04#ibcon#about to read 3, iclass 22, count 2 2006.161.07:46:51.07#ibcon#read 3, iclass 22, count 2 2006.161.07:46:51.07#ibcon#about to read 4, iclass 22, count 2 2006.161.07:46:51.07#ibcon#read 4, iclass 22, count 2 2006.161.07:46:51.07#ibcon#about to read 5, iclass 22, count 2 2006.161.07:46:51.07#ibcon#read 5, iclass 22, count 2 2006.161.07:46:51.07#ibcon#about to read 6, iclass 22, count 2 2006.161.07:46:51.07#ibcon#read 6, iclass 22, count 2 2006.161.07:46:51.07#ibcon#end of sib2, iclass 22, count 2 2006.161.07:46:51.07#ibcon#*after write, iclass 22, count 2 2006.161.07:46:51.07#ibcon#*before return 0, iclass 22, count 2 2006.161.07:46:51.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:51.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:51.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:46:51.07#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:51.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:51.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:51.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:51.19#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:46:51.19#ibcon#first serial, iclass 22, count 0 2006.161.07:46:51.19#ibcon#enter sib2, iclass 22, count 0 2006.161.07:46:51.19#ibcon#flushed, iclass 22, count 0 2006.161.07:46:51.19#ibcon#about to write, iclass 22, count 0 2006.161.07:46:51.19#ibcon#wrote, iclass 22, count 0 2006.161.07:46:51.19#ibcon#about to read 3, iclass 22, count 0 2006.161.07:46:51.21#ibcon#read 3, iclass 22, count 0 2006.161.07:46:51.21#ibcon#about to read 4, iclass 22, count 0 2006.161.07:46:51.21#ibcon#read 4, iclass 22, count 0 2006.161.07:46:51.21#ibcon#about to read 5, iclass 22, count 0 2006.161.07:46:51.21#ibcon#read 5, iclass 22, count 0 2006.161.07:46:51.21#ibcon#about to read 6, iclass 22, count 0 2006.161.07:46:51.21#ibcon#read 6, iclass 22, count 0 2006.161.07:46:51.21#ibcon#end of sib2, iclass 22, count 0 2006.161.07:46:51.21#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:46:51.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:46:51.21#ibcon#[25=USB\r\n] 2006.161.07:46:51.21#ibcon#*before write, iclass 22, count 0 2006.161.07:46:51.21#ibcon#enter sib2, iclass 22, count 0 2006.161.07:46:51.21#ibcon#flushed, iclass 22, count 0 2006.161.07:46:51.21#ibcon#about to write, iclass 22, count 0 2006.161.07:46:51.21#ibcon#wrote, iclass 22, count 0 2006.161.07:46:51.21#ibcon#about to read 3, iclass 22, count 0 2006.161.07:46:51.24#ibcon#read 3, iclass 22, count 0 2006.161.07:46:51.24#ibcon#about to read 4, iclass 22, count 0 2006.161.07:46:51.24#ibcon#read 4, iclass 22, count 0 2006.161.07:46:51.24#ibcon#about to read 5, iclass 22, count 0 2006.161.07:46:51.24#ibcon#read 5, iclass 22, count 0 2006.161.07:46:51.24#ibcon#about to read 6, iclass 22, count 0 2006.161.07:46:51.24#ibcon#read 6, iclass 22, count 0 2006.161.07:46:51.24#ibcon#end of sib2, iclass 22, count 0 2006.161.07:46:51.24#ibcon#*after write, iclass 22, count 0 2006.161.07:46:51.24#ibcon#*before return 0, iclass 22, count 0 2006.161.07:46:51.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:51.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:51.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:46:51.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:46:51.24$vc4f8/valo=7,832.99 2006.161.07:46:51.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:46:51.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:46:51.24#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:51.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:51.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:51.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:51.24#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:46:51.24#ibcon#first serial, iclass 24, count 0 2006.161.07:46:51.24#ibcon#enter sib2, iclass 24, count 0 2006.161.07:46:51.24#ibcon#flushed, iclass 24, count 0 2006.161.07:46:51.24#ibcon#about to write, iclass 24, count 0 2006.161.07:46:51.24#ibcon#wrote, iclass 24, count 0 2006.161.07:46:51.24#ibcon#about to read 3, iclass 24, count 0 2006.161.07:46:51.26#ibcon#read 3, iclass 24, count 0 2006.161.07:46:51.26#ibcon#about to read 4, iclass 24, count 0 2006.161.07:46:51.26#ibcon#read 4, iclass 24, count 0 2006.161.07:46:51.26#ibcon#about to read 5, iclass 24, count 0 2006.161.07:46:51.26#ibcon#read 5, iclass 24, count 0 2006.161.07:46:51.26#ibcon#about to read 6, iclass 24, count 0 2006.161.07:46:51.26#ibcon#read 6, iclass 24, count 0 2006.161.07:46:51.26#ibcon#end of sib2, iclass 24, count 0 2006.161.07:46:51.26#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:46:51.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:46:51.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:46:51.26#ibcon#*before write, iclass 24, count 0 2006.161.07:46:51.26#ibcon#enter sib2, iclass 24, count 0 2006.161.07:46:51.26#ibcon#flushed, iclass 24, count 0 2006.161.07:46:51.26#ibcon#about to write, iclass 24, count 0 2006.161.07:46:51.26#ibcon#wrote, iclass 24, count 0 2006.161.07:46:51.26#ibcon#about to read 3, iclass 24, count 0 2006.161.07:46:51.30#ibcon#read 3, iclass 24, count 0 2006.161.07:46:51.30#ibcon#about to read 4, iclass 24, count 0 2006.161.07:46:51.30#ibcon#read 4, iclass 24, count 0 2006.161.07:46:51.30#ibcon#about to read 5, iclass 24, count 0 2006.161.07:46:51.30#ibcon#read 5, iclass 24, count 0 2006.161.07:46:51.30#ibcon#about to read 6, iclass 24, count 0 2006.161.07:46:51.30#ibcon#read 6, iclass 24, count 0 2006.161.07:46:51.30#ibcon#end of sib2, iclass 24, count 0 2006.161.07:46:51.30#ibcon#*after write, iclass 24, count 0 2006.161.07:46:51.30#ibcon#*before return 0, iclass 24, count 0 2006.161.07:46:51.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:51.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:51.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:46:51.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:46:51.30$vc4f8/va=7,6 2006.161.07:46:51.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:46:51.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:46:51.30#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:51.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:51.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:51.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:51.36#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:46:51.36#ibcon#first serial, iclass 26, count 2 2006.161.07:46:51.36#ibcon#enter sib2, iclass 26, count 2 2006.161.07:46:51.36#ibcon#flushed, iclass 26, count 2 2006.161.07:46:51.36#ibcon#about to write, iclass 26, count 2 2006.161.07:46:51.36#ibcon#wrote, iclass 26, count 2 2006.161.07:46:51.36#ibcon#about to read 3, iclass 26, count 2 2006.161.07:46:51.38#ibcon#read 3, iclass 26, count 2 2006.161.07:46:51.38#ibcon#about to read 4, iclass 26, count 2 2006.161.07:46:51.38#ibcon#read 4, iclass 26, count 2 2006.161.07:46:51.38#ibcon#about to read 5, iclass 26, count 2 2006.161.07:46:51.38#ibcon#read 5, iclass 26, count 2 2006.161.07:46:51.38#ibcon#about to read 6, iclass 26, count 2 2006.161.07:46:51.38#ibcon#read 6, iclass 26, count 2 2006.161.07:46:51.38#ibcon#end of sib2, iclass 26, count 2 2006.161.07:46:51.38#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:46:51.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:46:51.38#ibcon#[25=AT07-06\r\n] 2006.161.07:46:51.38#ibcon#*before write, iclass 26, count 2 2006.161.07:46:51.38#ibcon#enter sib2, iclass 26, count 2 2006.161.07:46:51.38#ibcon#flushed, iclass 26, count 2 2006.161.07:46:51.38#ibcon#about to write, iclass 26, count 2 2006.161.07:46:51.38#ibcon#wrote, iclass 26, count 2 2006.161.07:46:51.38#ibcon#about to read 3, iclass 26, count 2 2006.161.07:46:51.41#ibcon#read 3, iclass 26, count 2 2006.161.07:46:51.41#ibcon#about to read 4, iclass 26, count 2 2006.161.07:46:51.41#ibcon#read 4, iclass 26, count 2 2006.161.07:46:51.41#ibcon#about to read 5, iclass 26, count 2 2006.161.07:46:51.41#ibcon#read 5, iclass 26, count 2 2006.161.07:46:51.41#ibcon#about to read 6, iclass 26, count 2 2006.161.07:46:51.41#ibcon#read 6, iclass 26, count 2 2006.161.07:46:51.41#ibcon#end of sib2, iclass 26, count 2 2006.161.07:46:51.41#ibcon#*after write, iclass 26, count 2 2006.161.07:46:51.41#ibcon#*before return 0, iclass 26, count 2 2006.161.07:46:51.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:51.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:51.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:46:51.41#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:51.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:46:51.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:46:51.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:46:51.54#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:46:51.54#ibcon#first serial, iclass 26, count 0 2006.161.07:46:51.54#ibcon#enter sib2, iclass 26, count 0 2006.161.07:46:51.54#ibcon#flushed, iclass 26, count 0 2006.161.07:46:51.54#ibcon#about to write, iclass 26, count 0 2006.161.07:46:51.54#ibcon#wrote, iclass 26, count 0 2006.161.07:46:51.54#ibcon#about to read 3, iclass 26, count 0 2006.161.07:46:51.56#ibcon#read 3, iclass 26, count 0 2006.161.07:46:51.56#ibcon#about to read 4, iclass 26, count 0 2006.161.07:46:51.56#ibcon#read 4, iclass 26, count 0 2006.161.07:46:51.56#ibcon#about to read 5, iclass 26, count 0 2006.161.07:46:51.56#ibcon#read 5, iclass 26, count 0 2006.161.07:46:51.56#ibcon#about to read 6, iclass 26, count 0 2006.161.07:46:51.56#ibcon#read 6, iclass 26, count 0 2006.161.07:46:51.56#ibcon#end of sib2, iclass 26, count 0 2006.161.07:46:51.56#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:46:51.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:46:51.56#ibcon#[25=USB\r\n] 2006.161.07:46:51.56#ibcon#*before write, iclass 26, count 0 2006.161.07:46:51.56#ibcon#enter sib2, iclass 26, count 0 2006.161.07:46:51.56#ibcon#flushed, iclass 26, count 0 2006.161.07:46:51.56#ibcon#about to write, iclass 26, count 0 2006.161.07:46:51.56#ibcon#wrote, iclass 26, count 0 2006.161.07:46:51.56#ibcon#about to read 3, iclass 26, count 0 2006.161.07:46:51.59#ibcon#read 3, iclass 26, count 0 2006.161.07:46:51.59#ibcon#about to read 4, iclass 26, count 0 2006.161.07:46:51.59#ibcon#read 4, iclass 26, count 0 2006.161.07:46:51.59#ibcon#about to read 5, iclass 26, count 0 2006.161.07:46:51.59#ibcon#read 5, iclass 26, count 0 2006.161.07:46:51.59#ibcon#about to read 6, iclass 26, count 0 2006.161.07:46:51.59#ibcon#read 6, iclass 26, count 0 2006.161.07:46:51.59#ibcon#end of sib2, iclass 26, count 0 2006.161.07:46:51.59#ibcon#*after write, iclass 26, count 0 2006.161.07:46:51.59#ibcon#*before return 0, iclass 26, count 0 2006.161.07:46:51.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:46:51.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:46:51.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:46:51.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:46:51.59$vc4f8/valo=8,852.99 2006.161.07:46:51.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:46:51.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:46:51.59#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:51.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:46:51.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:46:51.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:46:51.59#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:46:51.59#ibcon#first serial, iclass 28, count 0 2006.161.07:46:51.59#ibcon#enter sib2, iclass 28, count 0 2006.161.07:46:51.59#ibcon#flushed, iclass 28, count 0 2006.161.07:46:51.59#ibcon#about to write, iclass 28, count 0 2006.161.07:46:51.59#ibcon#wrote, iclass 28, count 0 2006.161.07:46:51.59#ibcon#about to read 3, iclass 28, count 0 2006.161.07:46:51.61#ibcon#read 3, iclass 28, count 0 2006.161.07:46:51.61#ibcon#about to read 4, iclass 28, count 0 2006.161.07:46:51.61#ibcon#read 4, iclass 28, count 0 2006.161.07:46:51.61#ibcon#about to read 5, iclass 28, count 0 2006.161.07:46:51.61#ibcon#read 5, iclass 28, count 0 2006.161.07:46:51.61#ibcon#about to read 6, iclass 28, count 0 2006.161.07:46:51.61#ibcon#read 6, iclass 28, count 0 2006.161.07:46:51.61#ibcon#end of sib2, iclass 28, count 0 2006.161.07:46:51.61#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:46:51.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:46:51.61#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:46:51.61#ibcon#*before write, iclass 28, count 0 2006.161.07:46:51.61#ibcon#enter sib2, iclass 28, count 0 2006.161.07:46:51.61#ibcon#flushed, iclass 28, count 0 2006.161.07:46:51.61#ibcon#about to write, iclass 28, count 0 2006.161.07:46:51.61#ibcon#wrote, iclass 28, count 0 2006.161.07:46:51.61#ibcon#about to read 3, iclass 28, count 0 2006.161.07:46:51.65#ibcon#read 3, iclass 28, count 0 2006.161.07:46:51.65#ibcon#about to read 4, iclass 28, count 0 2006.161.07:46:51.65#ibcon#read 4, iclass 28, count 0 2006.161.07:46:51.65#ibcon#about to read 5, iclass 28, count 0 2006.161.07:46:51.65#ibcon#read 5, iclass 28, count 0 2006.161.07:46:51.65#ibcon#about to read 6, iclass 28, count 0 2006.161.07:46:51.65#ibcon#read 6, iclass 28, count 0 2006.161.07:46:51.65#ibcon#end of sib2, iclass 28, count 0 2006.161.07:46:51.65#ibcon#*after write, iclass 28, count 0 2006.161.07:46:51.65#ibcon#*before return 0, iclass 28, count 0 2006.161.07:46:51.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:46:51.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:46:51.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:46:51.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:46:51.65$vc4f8/va=8,7 2006.161.07:46:51.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.07:46:51.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.07:46:51.65#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:51.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:46:51.71#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:46:51.71#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:46:51.71#ibcon#enter wrdev, iclass 30, count 2 2006.161.07:46:51.71#ibcon#first serial, iclass 30, count 2 2006.161.07:46:51.71#ibcon#enter sib2, iclass 30, count 2 2006.161.07:46:51.71#ibcon#flushed, iclass 30, count 2 2006.161.07:46:51.71#ibcon#about to write, iclass 30, count 2 2006.161.07:46:51.71#ibcon#wrote, iclass 30, count 2 2006.161.07:46:51.71#ibcon#about to read 3, iclass 30, count 2 2006.161.07:46:51.73#ibcon#read 3, iclass 30, count 2 2006.161.07:46:51.73#ibcon#about to read 4, iclass 30, count 2 2006.161.07:46:51.73#ibcon#read 4, iclass 30, count 2 2006.161.07:46:51.73#ibcon#about to read 5, iclass 30, count 2 2006.161.07:46:51.73#ibcon#read 5, iclass 30, count 2 2006.161.07:46:51.73#ibcon#about to read 6, iclass 30, count 2 2006.161.07:46:51.73#ibcon#read 6, iclass 30, count 2 2006.161.07:46:51.73#ibcon#end of sib2, iclass 30, count 2 2006.161.07:46:51.73#ibcon#*mode == 0, iclass 30, count 2 2006.161.07:46:51.73#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.07:46:51.73#ibcon#[25=AT08-07\r\n] 2006.161.07:46:51.73#ibcon#*before write, iclass 30, count 2 2006.161.07:46:51.73#ibcon#enter sib2, iclass 30, count 2 2006.161.07:46:51.73#ibcon#flushed, iclass 30, count 2 2006.161.07:46:51.73#ibcon#about to write, iclass 30, count 2 2006.161.07:46:51.73#ibcon#wrote, iclass 30, count 2 2006.161.07:46:51.73#ibcon#about to read 3, iclass 30, count 2 2006.161.07:46:51.76#ibcon#read 3, iclass 30, count 2 2006.161.07:46:51.76#ibcon#about to read 4, iclass 30, count 2 2006.161.07:46:51.76#ibcon#read 4, iclass 30, count 2 2006.161.07:46:51.76#ibcon#about to read 5, iclass 30, count 2 2006.161.07:46:51.76#ibcon#read 5, iclass 30, count 2 2006.161.07:46:51.76#ibcon#about to read 6, iclass 30, count 2 2006.161.07:46:51.76#ibcon#read 6, iclass 30, count 2 2006.161.07:46:51.76#ibcon#end of sib2, iclass 30, count 2 2006.161.07:46:51.76#ibcon#*after write, iclass 30, count 2 2006.161.07:46:51.76#ibcon#*before return 0, iclass 30, count 2 2006.161.07:46:51.76#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:46:51.76#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:46:51.76#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.07:46:51.76#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:51.76#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:46:51.88#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:46:51.88#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:46:51.88#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:46:51.88#ibcon#first serial, iclass 30, count 0 2006.161.07:46:51.88#ibcon#enter sib2, iclass 30, count 0 2006.161.07:46:51.88#ibcon#flushed, iclass 30, count 0 2006.161.07:46:51.88#ibcon#about to write, iclass 30, count 0 2006.161.07:46:51.88#ibcon#wrote, iclass 30, count 0 2006.161.07:46:51.88#ibcon#about to read 3, iclass 30, count 0 2006.161.07:46:51.90#ibcon#read 3, iclass 30, count 0 2006.161.07:46:51.90#ibcon#about to read 4, iclass 30, count 0 2006.161.07:46:51.90#ibcon#read 4, iclass 30, count 0 2006.161.07:46:51.90#ibcon#about to read 5, iclass 30, count 0 2006.161.07:46:51.90#ibcon#read 5, iclass 30, count 0 2006.161.07:46:51.90#ibcon#about to read 6, iclass 30, count 0 2006.161.07:46:51.90#ibcon#read 6, iclass 30, count 0 2006.161.07:46:51.90#ibcon#end of sib2, iclass 30, count 0 2006.161.07:46:51.90#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:46:51.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:46:51.90#ibcon#[25=USB\r\n] 2006.161.07:46:51.90#ibcon#*before write, iclass 30, count 0 2006.161.07:46:51.90#ibcon#enter sib2, iclass 30, count 0 2006.161.07:46:51.90#ibcon#flushed, iclass 30, count 0 2006.161.07:46:51.90#ibcon#about to write, iclass 30, count 0 2006.161.07:46:51.90#ibcon#wrote, iclass 30, count 0 2006.161.07:46:51.90#ibcon#about to read 3, iclass 30, count 0 2006.161.07:46:51.93#ibcon#read 3, iclass 30, count 0 2006.161.07:46:51.93#ibcon#about to read 4, iclass 30, count 0 2006.161.07:46:51.93#ibcon#read 4, iclass 30, count 0 2006.161.07:46:51.93#ibcon#about to read 5, iclass 30, count 0 2006.161.07:46:51.93#ibcon#read 5, iclass 30, count 0 2006.161.07:46:51.93#ibcon#about to read 6, iclass 30, count 0 2006.161.07:46:51.93#ibcon#read 6, iclass 30, count 0 2006.161.07:46:51.93#ibcon#end of sib2, iclass 30, count 0 2006.161.07:46:51.93#ibcon#*after write, iclass 30, count 0 2006.161.07:46:51.93#ibcon#*before return 0, iclass 30, count 0 2006.161.07:46:51.93#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:46:51.93#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:46:51.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:46:51.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:46:51.93$vc4f8/vblo=1,632.99 2006.161.07:46:51.93#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.07:46:51.93#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.07:46:51.93#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:51.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:46:51.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:46:51.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:46:51.93#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:46:51.93#ibcon#first serial, iclass 32, count 0 2006.161.07:46:51.93#ibcon#enter sib2, iclass 32, count 0 2006.161.07:46:51.93#ibcon#flushed, iclass 32, count 0 2006.161.07:46:51.93#ibcon#about to write, iclass 32, count 0 2006.161.07:46:51.93#ibcon#wrote, iclass 32, count 0 2006.161.07:46:51.93#ibcon#about to read 3, iclass 32, count 0 2006.161.07:46:51.95#ibcon#read 3, iclass 32, count 0 2006.161.07:46:51.95#ibcon#about to read 4, iclass 32, count 0 2006.161.07:46:51.95#ibcon#read 4, iclass 32, count 0 2006.161.07:46:51.95#ibcon#about to read 5, iclass 32, count 0 2006.161.07:46:51.95#ibcon#read 5, iclass 32, count 0 2006.161.07:46:51.95#ibcon#about to read 6, iclass 32, count 0 2006.161.07:46:51.95#ibcon#read 6, iclass 32, count 0 2006.161.07:46:51.95#ibcon#end of sib2, iclass 32, count 0 2006.161.07:46:51.95#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:46:51.95#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:46:51.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:46:51.95#ibcon#*before write, iclass 32, count 0 2006.161.07:46:51.95#ibcon#enter sib2, iclass 32, count 0 2006.161.07:46:51.95#ibcon#flushed, iclass 32, count 0 2006.161.07:46:51.95#ibcon#about to write, iclass 32, count 0 2006.161.07:46:51.95#ibcon#wrote, iclass 32, count 0 2006.161.07:46:51.95#ibcon#about to read 3, iclass 32, count 0 2006.161.07:46:51.99#ibcon#read 3, iclass 32, count 0 2006.161.07:46:51.99#ibcon#about to read 4, iclass 32, count 0 2006.161.07:46:51.99#ibcon#read 4, iclass 32, count 0 2006.161.07:46:51.99#ibcon#about to read 5, iclass 32, count 0 2006.161.07:46:51.99#ibcon#read 5, iclass 32, count 0 2006.161.07:46:51.99#ibcon#about to read 6, iclass 32, count 0 2006.161.07:46:51.99#ibcon#read 6, iclass 32, count 0 2006.161.07:46:51.99#ibcon#end of sib2, iclass 32, count 0 2006.161.07:46:51.99#ibcon#*after write, iclass 32, count 0 2006.161.07:46:51.99#ibcon#*before return 0, iclass 32, count 0 2006.161.07:46:51.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:46:51.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:46:51.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:46:51.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:46:51.99$vc4f8/vb=1,4 2006.161.07:46:51.99#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.07:46:51.99#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.07:46:51.99#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:51.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:46:51.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:46:51.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:46:51.99#ibcon#enter wrdev, iclass 34, count 2 2006.161.07:46:51.99#ibcon#first serial, iclass 34, count 2 2006.161.07:46:51.99#ibcon#enter sib2, iclass 34, count 2 2006.161.07:46:51.99#ibcon#flushed, iclass 34, count 2 2006.161.07:46:51.99#ibcon#about to write, iclass 34, count 2 2006.161.07:46:51.99#ibcon#wrote, iclass 34, count 2 2006.161.07:46:51.99#ibcon#about to read 3, iclass 34, count 2 2006.161.07:46:52.01#ibcon#read 3, iclass 34, count 2 2006.161.07:46:52.01#ibcon#about to read 4, iclass 34, count 2 2006.161.07:46:52.01#ibcon#read 4, iclass 34, count 2 2006.161.07:46:52.01#ibcon#about to read 5, iclass 34, count 2 2006.161.07:46:52.01#ibcon#read 5, iclass 34, count 2 2006.161.07:46:52.01#ibcon#about to read 6, iclass 34, count 2 2006.161.07:46:52.01#ibcon#read 6, iclass 34, count 2 2006.161.07:46:52.01#ibcon#end of sib2, iclass 34, count 2 2006.161.07:46:52.01#ibcon#*mode == 0, iclass 34, count 2 2006.161.07:46:52.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.07:46:52.01#ibcon#[27=AT01-04\r\n] 2006.161.07:46:52.01#ibcon#*before write, iclass 34, count 2 2006.161.07:46:52.01#ibcon#enter sib2, iclass 34, count 2 2006.161.07:46:52.01#ibcon#flushed, iclass 34, count 2 2006.161.07:46:52.01#ibcon#about to write, iclass 34, count 2 2006.161.07:46:52.01#ibcon#wrote, iclass 34, count 2 2006.161.07:46:52.01#ibcon#about to read 3, iclass 34, count 2 2006.161.07:46:52.04#ibcon#read 3, iclass 34, count 2 2006.161.07:46:52.04#ibcon#about to read 4, iclass 34, count 2 2006.161.07:46:52.04#ibcon#read 4, iclass 34, count 2 2006.161.07:46:52.04#ibcon#about to read 5, iclass 34, count 2 2006.161.07:46:52.04#ibcon#read 5, iclass 34, count 2 2006.161.07:46:52.04#ibcon#about to read 6, iclass 34, count 2 2006.161.07:46:52.04#ibcon#read 6, iclass 34, count 2 2006.161.07:46:52.04#ibcon#end of sib2, iclass 34, count 2 2006.161.07:46:52.04#ibcon#*after write, iclass 34, count 2 2006.161.07:46:52.04#ibcon#*before return 0, iclass 34, count 2 2006.161.07:46:52.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:46:52.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:46:52.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.07:46:52.04#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:52.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:46:52.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:46:52.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:46:52.16#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:46:52.16#ibcon#first serial, iclass 34, count 0 2006.161.07:46:52.16#ibcon#enter sib2, iclass 34, count 0 2006.161.07:46:52.16#ibcon#flushed, iclass 34, count 0 2006.161.07:46:52.16#ibcon#about to write, iclass 34, count 0 2006.161.07:46:52.16#ibcon#wrote, iclass 34, count 0 2006.161.07:46:52.16#ibcon#about to read 3, iclass 34, count 0 2006.161.07:46:52.18#ibcon#read 3, iclass 34, count 0 2006.161.07:46:52.18#ibcon#about to read 4, iclass 34, count 0 2006.161.07:46:52.18#ibcon#read 4, iclass 34, count 0 2006.161.07:46:52.18#ibcon#about to read 5, iclass 34, count 0 2006.161.07:46:52.18#ibcon#read 5, iclass 34, count 0 2006.161.07:46:52.18#ibcon#about to read 6, iclass 34, count 0 2006.161.07:46:52.18#ibcon#read 6, iclass 34, count 0 2006.161.07:46:52.18#ibcon#end of sib2, iclass 34, count 0 2006.161.07:46:52.18#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:46:52.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:46:52.18#ibcon#[27=USB\r\n] 2006.161.07:46:52.18#ibcon#*before write, iclass 34, count 0 2006.161.07:46:52.18#ibcon#enter sib2, iclass 34, count 0 2006.161.07:46:52.18#ibcon#flushed, iclass 34, count 0 2006.161.07:46:52.18#ibcon#about to write, iclass 34, count 0 2006.161.07:46:52.18#ibcon#wrote, iclass 34, count 0 2006.161.07:46:52.18#ibcon#about to read 3, iclass 34, count 0 2006.161.07:46:52.21#ibcon#read 3, iclass 34, count 0 2006.161.07:46:52.21#ibcon#about to read 4, iclass 34, count 0 2006.161.07:46:52.21#ibcon#read 4, iclass 34, count 0 2006.161.07:46:52.21#ibcon#about to read 5, iclass 34, count 0 2006.161.07:46:52.21#ibcon#read 5, iclass 34, count 0 2006.161.07:46:52.21#ibcon#about to read 6, iclass 34, count 0 2006.161.07:46:52.21#ibcon#read 6, iclass 34, count 0 2006.161.07:46:52.21#ibcon#end of sib2, iclass 34, count 0 2006.161.07:46:52.21#ibcon#*after write, iclass 34, count 0 2006.161.07:46:52.21#ibcon#*before return 0, iclass 34, count 0 2006.161.07:46:52.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:46:52.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:46:52.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:46:52.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:46:52.21$vc4f8/vblo=2,640.99 2006.161.07:46:52.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.07:46:52.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.07:46:52.21#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:52.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:52.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:52.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:52.21#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:46:52.21#ibcon#first serial, iclass 36, count 0 2006.161.07:46:52.21#ibcon#enter sib2, iclass 36, count 0 2006.161.07:46:52.21#ibcon#flushed, iclass 36, count 0 2006.161.07:46:52.21#ibcon#about to write, iclass 36, count 0 2006.161.07:46:52.21#ibcon#wrote, iclass 36, count 0 2006.161.07:46:52.21#ibcon#about to read 3, iclass 36, count 0 2006.161.07:46:52.23#ibcon#read 3, iclass 36, count 0 2006.161.07:46:52.23#ibcon#about to read 4, iclass 36, count 0 2006.161.07:46:52.23#ibcon#read 4, iclass 36, count 0 2006.161.07:46:52.23#ibcon#about to read 5, iclass 36, count 0 2006.161.07:46:52.23#ibcon#read 5, iclass 36, count 0 2006.161.07:46:52.23#ibcon#about to read 6, iclass 36, count 0 2006.161.07:46:52.23#ibcon#read 6, iclass 36, count 0 2006.161.07:46:52.23#ibcon#end of sib2, iclass 36, count 0 2006.161.07:46:52.23#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:46:52.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:46:52.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:46:52.23#ibcon#*before write, iclass 36, count 0 2006.161.07:46:52.23#ibcon#enter sib2, iclass 36, count 0 2006.161.07:46:52.23#ibcon#flushed, iclass 36, count 0 2006.161.07:46:52.23#ibcon#about to write, iclass 36, count 0 2006.161.07:46:52.23#ibcon#wrote, iclass 36, count 0 2006.161.07:46:52.23#ibcon#about to read 3, iclass 36, count 0 2006.161.07:46:52.27#ibcon#read 3, iclass 36, count 0 2006.161.07:46:52.27#ibcon#about to read 4, iclass 36, count 0 2006.161.07:46:52.27#ibcon#read 4, iclass 36, count 0 2006.161.07:46:52.27#ibcon#about to read 5, iclass 36, count 0 2006.161.07:46:52.27#ibcon#read 5, iclass 36, count 0 2006.161.07:46:52.27#ibcon#about to read 6, iclass 36, count 0 2006.161.07:46:52.27#ibcon#read 6, iclass 36, count 0 2006.161.07:46:52.27#ibcon#end of sib2, iclass 36, count 0 2006.161.07:46:52.27#ibcon#*after write, iclass 36, count 0 2006.161.07:46:52.27#ibcon#*before return 0, iclass 36, count 0 2006.161.07:46:52.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:52.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:46:52.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:46:52.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:46:52.27$vc4f8/vb=2,4 2006.161.07:46:52.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.07:46:52.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.07:46:52.27#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:52.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:52.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:52.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:52.33#ibcon#enter wrdev, iclass 38, count 2 2006.161.07:46:52.33#ibcon#first serial, iclass 38, count 2 2006.161.07:46:52.33#ibcon#enter sib2, iclass 38, count 2 2006.161.07:46:52.33#ibcon#flushed, iclass 38, count 2 2006.161.07:46:52.33#ibcon#about to write, iclass 38, count 2 2006.161.07:46:52.33#ibcon#wrote, iclass 38, count 2 2006.161.07:46:52.33#ibcon#about to read 3, iclass 38, count 2 2006.161.07:46:52.35#ibcon#read 3, iclass 38, count 2 2006.161.07:46:52.35#ibcon#about to read 4, iclass 38, count 2 2006.161.07:46:52.35#ibcon#read 4, iclass 38, count 2 2006.161.07:46:52.35#ibcon#about to read 5, iclass 38, count 2 2006.161.07:46:52.35#ibcon#read 5, iclass 38, count 2 2006.161.07:46:52.35#ibcon#about to read 6, iclass 38, count 2 2006.161.07:46:52.35#ibcon#read 6, iclass 38, count 2 2006.161.07:46:52.35#ibcon#end of sib2, iclass 38, count 2 2006.161.07:46:52.35#ibcon#*mode == 0, iclass 38, count 2 2006.161.07:46:52.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.07:46:52.35#ibcon#[27=AT02-04\r\n] 2006.161.07:46:52.35#ibcon#*before write, iclass 38, count 2 2006.161.07:46:52.35#ibcon#enter sib2, iclass 38, count 2 2006.161.07:46:52.35#ibcon#flushed, iclass 38, count 2 2006.161.07:46:52.35#ibcon#about to write, iclass 38, count 2 2006.161.07:46:52.35#ibcon#wrote, iclass 38, count 2 2006.161.07:46:52.35#ibcon#about to read 3, iclass 38, count 2 2006.161.07:46:52.38#ibcon#read 3, iclass 38, count 2 2006.161.07:46:52.38#ibcon#about to read 4, iclass 38, count 2 2006.161.07:46:52.38#ibcon#read 4, iclass 38, count 2 2006.161.07:46:52.38#ibcon#about to read 5, iclass 38, count 2 2006.161.07:46:52.38#ibcon#read 5, iclass 38, count 2 2006.161.07:46:52.38#ibcon#about to read 6, iclass 38, count 2 2006.161.07:46:52.38#ibcon#read 6, iclass 38, count 2 2006.161.07:46:52.38#ibcon#end of sib2, iclass 38, count 2 2006.161.07:46:52.38#ibcon#*after write, iclass 38, count 2 2006.161.07:46:52.38#ibcon#*before return 0, iclass 38, count 2 2006.161.07:46:52.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:52.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:46:52.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.07:46:52.38#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:52.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:52.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:52.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:52.50#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:46:52.50#ibcon#first serial, iclass 38, count 0 2006.161.07:46:52.50#ibcon#enter sib2, iclass 38, count 0 2006.161.07:46:52.50#ibcon#flushed, iclass 38, count 0 2006.161.07:46:52.50#ibcon#about to write, iclass 38, count 0 2006.161.07:46:52.50#ibcon#wrote, iclass 38, count 0 2006.161.07:46:52.50#ibcon#about to read 3, iclass 38, count 0 2006.161.07:46:52.52#ibcon#read 3, iclass 38, count 0 2006.161.07:46:52.52#ibcon#about to read 4, iclass 38, count 0 2006.161.07:46:52.52#ibcon#read 4, iclass 38, count 0 2006.161.07:46:52.52#ibcon#about to read 5, iclass 38, count 0 2006.161.07:46:52.52#ibcon#read 5, iclass 38, count 0 2006.161.07:46:52.52#ibcon#about to read 6, iclass 38, count 0 2006.161.07:46:52.52#ibcon#read 6, iclass 38, count 0 2006.161.07:46:52.52#ibcon#end of sib2, iclass 38, count 0 2006.161.07:46:52.52#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:46:52.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:46:52.52#ibcon#[27=USB\r\n] 2006.161.07:46:52.52#ibcon#*before write, iclass 38, count 0 2006.161.07:46:52.52#ibcon#enter sib2, iclass 38, count 0 2006.161.07:46:52.52#ibcon#flushed, iclass 38, count 0 2006.161.07:46:52.52#ibcon#about to write, iclass 38, count 0 2006.161.07:46:52.52#ibcon#wrote, iclass 38, count 0 2006.161.07:46:52.52#ibcon#about to read 3, iclass 38, count 0 2006.161.07:46:52.55#ibcon#read 3, iclass 38, count 0 2006.161.07:46:52.55#ibcon#about to read 4, iclass 38, count 0 2006.161.07:46:52.55#ibcon#read 4, iclass 38, count 0 2006.161.07:46:52.55#ibcon#about to read 5, iclass 38, count 0 2006.161.07:46:52.55#ibcon#read 5, iclass 38, count 0 2006.161.07:46:52.55#ibcon#about to read 6, iclass 38, count 0 2006.161.07:46:52.55#ibcon#read 6, iclass 38, count 0 2006.161.07:46:52.55#ibcon#end of sib2, iclass 38, count 0 2006.161.07:46:52.55#ibcon#*after write, iclass 38, count 0 2006.161.07:46:52.55#ibcon#*before return 0, iclass 38, count 0 2006.161.07:46:52.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:52.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:46:52.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:46:52.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:46:52.55$vc4f8/vblo=3,656.99 2006.161.07:46:52.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:46:52.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:46:52.55#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:52.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:52.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:52.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:52.55#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:46:52.55#ibcon#first serial, iclass 40, count 0 2006.161.07:46:52.55#ibcon#enter sib2, iclass 40, count 0 2006.161.07:46:52.55#ibcon#flushed, iclass 40, count 0 2006.161.07:46:52.55#ibcon#about to write, iclass 40, count 0 2006.161.07:46:52.55#ibcon#wrote, iclass 40, count 0 2006.161.07:46:52.55#ibcon#about to read 3, iclass 40, count 0 2006.161.07:46:52.57#ibcon#read 3, iclass 40, count 0 2006.161.07:46:52.57#ibcon#about to read 4, iclass 40, count 0 2006.161.07:46:52.57#ibcon#read 4, iclass 40, count 0 2006.161.07:46:52.57#ibcon#about to read 5, iclass 40, count 0 2006.161.07:46:52.57#ibcon#read 5, iclass 40, count 0 2006.161.07:46:52.57#ibcon#about to read 6, iclass 40, count 0 2006.161.07:46:52.57#ibcon#read 6, iclass 40, count 0 2006.161.07:46:52.57#ibcon#end of sib2, iclass 40, count 0 2006.161.07:46:52.57#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:46:52.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:46:52.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:46:52.57#ibcon#*before write, iclass 40, count 0 2006.161.07:46:52.57#ibcon#enter sib2, iclass 40, count 0 2006.161.07:46:52.57#ibcon#flushed, iclass 40, count 0 2006.161.07:46:52.57#ibcon#about to write, iclass 40, count 0 2006.161.07:46:52.57#ibcon#wrote, iclass 40, count 0 2006.161.07:46:52.57#ibcon#about to read 3, iclass 40, count 0 2006.161.07:46:52.61#ibcon#read 3, iclass 40, count 0 2006.161.07:46:52.61#ibcon#about to read 4, iclass 40, count 0 2006.161.07:46:52.61#ibcon#read 4, iclass 40, count 0 2006.161.07:46:52.61#ibcon#about to read 5, iclass 40, count 0 2006.161.07:46:52.61#ibcon#read 5, iclass 40, count 0 2006.161.07:46:52.61#ibcon#about to read 6, iclass 40, count 0 2006.161.07:46:52.61#ibcon#read 6, iclass 40, count 0 2006.161.07:46:52.61#ibcon#end of sib2, iclass 40, count 0 2006.161.07:46:52.61#ibcon#*after write, iclass 40, count 0 2006.161.07:46:52.61#ibcon#*before return 0, iclass 40, count 0 2006.161.07:46:52.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:52.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:46:52.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:46:52.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:46:52.61$vc4f8/vb=3,4 2006.161.07:46:52.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:46:52.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:46:52.61#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:52.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:52.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:52.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:52.67#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:46:52.67#ibcon#first serial, iclass 4, count 2 2006.161.07:46:52.67#ibcon#enter sib2, iclass 4, count 2 2006.161.07:46:52.67#ibcon#flushed, iclass 4, count 2 2006.161.07:46:52.67#ibcon#about to write, iclass 4, count 2 2006.161.07:46:52.67#ibcon#wrote, iclass 4, count 2 2006.161.07:46:52.67#ibcon#about to read 3, iclass 4, count 2 2006.161.07:46:52.69#ibcon#read 3, iclass 4, count 2 2006.161.07:46:52.69#ibcon#about to read 4, iclass 4, count 2 2006.161.07:46:52.69#ibcon#read 4, iclass 4, count 2 2006.161.07:46:52.69#ibcon#about to read 5, iclass 4, count 2 2006.161.07:46:52.69#ibcon#read 5, iclass 4, count 2 2006.161.07:46:52.69#ibcon#about to read 6, iclass 4, count 2 2006.161.07:46:52.69#ibcon#read 6, iclass 4, count 2 2006.161.07:46:52.69#ibcon#end of sib2, iclass 4, count 2 2006.161.07:46:52.69#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:46:52.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:46:52.69#ibcon#[27=AT03-04\r\n] 2006.161.07:46:52.69#ibcon#*before write, iclass 4, count 2 2006.161.07:46:52.69#ibcon#enter sib2, iclass 4, count 2 2006.161.07:46:52.69#ibcon#flushed, iclass 4, count 2 2006.161.07:46:52.69#ibcon#about to write, iclass 4, count 2 2006.161.07:46:52.69#ibcon#wrote, iclass 4, count 2 2006.161.07:46:52.69#ibcon#about to read 3, iclass 4, count 2 2006.161.07:46:52.72#ibcon#read 3, iclass 4, count 2 2006.161.07:46:52.72#ibcon#about to read 4, iclass 4, count 2 2006.161.07:46:52.72#ibcon#read 4, iclass 4, count 2 2006.161.07:46:52.72#ibcon#about to read 5, iclass 4, count 2 2006.161.07:46:52.72#ibcon#read 5, iclass 4, count 2 2006.161.07:46:52.72#ibcon#about to read 6, iclass 4, count 2 2006.161.07:46:52.72#ibcon#read 6, iclass 4, count 2 2006.161.07:46:52.72#ibcon#end of sib2, iclass 4, count 2 2006.161.07:46:52.72#ibcon#*after write, iclass 4, count 2 2006.161.07:46:52.72#ibcon#*before return 0, iclass 4, count 2 2006.161.07:46:52.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:52.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:46:52.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:46:52.72#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:52.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:52.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:52.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:52.84#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:46:52.84#ibcon#first serial, iclass 4, count 0 2006.161.07:46:52.84#ibcon#enter sib2, iclass 4, count 0 2006.161.07:46:52.84#ibcon#flushed, iclass 4, count 0 2006.161.07:46:52.84#ibcon#about to write, iclass 4, count 0 2006.161.07:46:52.84#ibcon#wrote, iclass 4, count 0 2006.161.07:46:52.84#ibcon#about to read 3, iclass 4, count 0 2006.161.07:46:52.85#abcon#<5=/05 3.2 5.7 24.08 861002.0\r\n> 2006.161.07:46:52.86#ibcon#read 3, iclass 4, count 0 2006.161.07:46:52.86#ibcon#about to read 4, iclass 4, count 0 2006.161.07:46:52.86#ibcon#read 4, iclass 4, count 0 2006.161.07:46:52.86#ibcon#about to read 5, iclass 4, count 0 2006.161.07:46:52.86#ibcon#read 5, iclass 4, count 0 2006.161.07:46:52.86#ibcon#about to read 6, iclass 4, count 0 2006.161.07:46:52.86#ibcon#read 6, iclass 4, count 0 2006.161.07:46:52.86#ibcon#end of sib2, iclass 4, count 0 2006.161.07:46:52.86#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:46:52.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:46:52.86#ibcon#[27=USB\r\n] 2006.161.07:46:52.86#ibcon#*before write, iclass 4, count 0 2006.161.07:46:52.86#ibcon#enter sib2, iclass 4, count 0 2006.161.07:46:52.86#ibcon#flushed, iclass 4, count 0 2006.161.07:46:52.86#ibcon#about to write, iclass 4, count 0 2006.161.07:46:52.86#ibcon#wrote, iclass 4, count 0 2006.161.07:46:52.86#ibcon#about to read 3, iclass 4, count 0 2006.161.07:46:52.87#abcon#{5=INTERFACE CLEAR} 2006.161.07:46:52.89#ibcon#read 3, iclass 4, count 0 2006.161.07:46:52.89#ibcon#about to read 4, iclass 4, count 0 2006.161.07:46:52.89#ibcon#read 4, iclass 4, count 0 2006.161.07:46:52.89#ibcon#about to read 5, iclass 4, count 0 2006.161.07:46:52.89#ibcon#read 5, iclass 4, count 0 2006.161.07:46:52.89#ibcon#about to read 6, iclass 4, count 0 2006.161.07:46:52.89#ibcon#read 6, iclass 4, count 0 2006.161.07:46:52.89#ibcon#end of sib2, iclass 4, count 0 2006.161.07:46:52.89#ibcon#*after write, iclass 4, count 0 2006.161.07:46:52.89#ibcon#*before return 0, iclass 4, count 0 2006.161.07:46:52.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:52.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:46:52.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:46:52.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:46:52.89$vc4f8/vblo=4,712.99 2006.161.07:46:52.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:46:52.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:46:52.89#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:52.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:46:52.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:46:52.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:46:52.89#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:46:52.89#ibcon#first serial, iclass 11, count 0 2006.161.07:46:52.89#ibcon#enter sib2, iclass 11, count 0 2006.161.07:46:52.89#ibcon#flushed, iclass 11, count 0 2006.161.07:46:52.89#ibcon#about to write, iclass 11, count 0 2006.161.07:46:52.89#ibcon#wrote, iclass 11, count 0 2006.161.07:46:52.89#ibcon#about to read 3, iclass 11, count 0 2006.161.07:46:52.91#ibcon#read 3, iclass 11, count 0 2006.161.07:46:52.91#ibcon#about to read 4, iclass 11, count 0 2006.161.07:46:52.91#ibcon#read 4, iclass 11, count 0 2006.161.07:46:52.91#ibcon#about to read 5, iclass 11, count 0 2006.161.07:46:52.91#ibcon#read 5, iclass 11, count 0 2006.161.07:46:52.91#ibcon#about to read 6, iclass 11, count 0 2006.161.07:46:52.91#ibcon#read 6, iclass 11, count 0 2006.161.07:46:52.91#ibcon#end of sib2, iclass 11, count 0 2006.161.07:46:52.91#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:46:52.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:46:52.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:46:52.91#ibcon#*before write, iclass 11, count 0 2006.161.07:46:52.91#ibcon#enter sib2, iclass 11, count 0 2006.161.07:46:52.91#ibcon#flushed, iclass 11, count 0 2006.161.07:46:52.91#ibcon#about to write, iclass 11, count 0 2006.161.07:46:52.91#ibcon#wrote, iclass 11, count 0 2006.161.07:46:52.91#ibcon#about to read 3, iclass 11, count 0 2006.161.07:46:52.93#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:46:52.95#ibcon#read 3, iclass 11, count 0 2006.161.07:46:52.95#ibcon#about to read 4, iclass 11, count 0 2006.161.07:46:52.95#ibcon#read 4, iclass 11, count 0 2006.161.07:46:52.95#ibcon#about to read 5, iclass 11, count 0 2006.161.07:46:52.95#ibcon#read 5, iclass 11, count 0 2006.161.07:46:52.95#ibcon#about to read 6, iclass 11, count 0 2006.161.07:46:52.95#ibcon#read 6, iclass 11, count 0 2006.161.07:46:52.95#ibcon#end of sib2, iclass 11, count 0 2006.161.07:46:52.95#ibcon#*after write, iclass 11, count 0 2006.161.07:46:52.95#ibcon#*before return 0, iclass 11, count 0 2006.161.07:46:52.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:46:52.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:46:52.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:46:52.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:46:52.95$vc4f8/vb=4,4 2006.161.07:46:52.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:46:52.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:46:52.95#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:52.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:53.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:53.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:53.01#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:46:53.01#ibcon#first serial, iclass 14, count 2 2006.161.07:46:53.01#ibcon#enter sib2, iclass 14, count 2 2006.161.07:46:53.01#ibcon#flushed, iclass 14, count 2 2006.161.07:46:53.01#ibcon#about to write, iclass 14, count 2 2006.161.07:46:53.01#ibcon#wrote, iclass 14, count 2 2006.161.07:46:53.01#ibcon#about to read 3, iclass 14, count 2 2006.161.07:46:53.03#ibcon#read 3, iclass 14, count 2 2006.161.07:46:53.03#ibcon#about to read 4, iclass 14, count 2 2006.161.07:46:53.03#ibcon#read 4, iclass 14, count 2 2006.161.07:46:53.03#ibcon#about to read 5, iclass 14, count 2 2006.161.07:46:53.03#ibcon#read 5, iclass 14, count 2 2006.161.07:46:53.03#ibcon#about to read 6, iclass 14, count 2 2006.161.07:46:53.03#ibcon#read 6, iclass 14, count 2 2006.161.07:46:53.03#ibcon#end of sib2, iclass 14, count 2 2006.161.07:46:53.03#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:46:53.03#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:46:53.03#ibcon#[27=AT04-04\r\n] 2006.161.07:46:53.03#ibcon#*before write, iclass 14, count 2 2006.161.07:46:53.03#ibcon#enter sib2, iclass 14, count 2 2006.161.07:46:53.03#ibcon#flushed, iclass 14, count 2 2006.161.07:46:53.03#ibcon#about to write, iclass 14, count 2 2006.161.07:46:53.03#ibcon#wrote, iclass 14, count 2 2006.161.07:46:53.03#ibcon#about to read 3, iclass 14, count 2 2006.161.07:46:53.06#ibcon#read 3, iclass 14, count 2 2006.161.07:46:53.06#ibcon#about to read 4, iclass 14, count 2 2006.161.07:46:53.06#ibcon#read 4, iclass 14, count 2 2006.161.07:46:53.06#ibcon#about to read 5, iclass 14, count 2 2006.161.07:46:53.06#ibcon#read 5, iclass 14, count 2 2006.161.07:46:53.06#ibcon#about to read 6, iclass 14, count 2 2006.161.07:46:53.06#ibcon#read 6, iclass 14, count 2 2006.161.07:46:53.06#ibcon#end of sib2, iclass 14, count 2 2006.161.07:46:53.06#ibcon#*after write, iclass 14, count 2 2006.161.07:46:53.06#ibcon#*before return 0, iclass 14, count 2 2006.161.07:46:53.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:53.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:46:53.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:46:53.06#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:53.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:53.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:53.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:53.18#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:46:53.18#ibcon#first serial, iclass 14, count 0 2006.161.07:46:53.18#ibcon#enter sib2, iclass 14, count 0 2006.161.07:46:53.18#ibcon#flushed, iclass 14, count 0 2006.161.07:46:53.18#ibcon#about to write, iclass 14, count 0 2006.161.07:46:53.18#ibcon#wrote, iclass 14, count 0 2006.161.07:46:53.18#ibcon#about to read 3, iclass 14, count 0 2006.161.07:46:53.20#ibcon#read 3, iclass 14, count 0 2006.161.07:46:53.20#ibcon#about to read 4, iclass 14, count 0 2006.161.07:46:53.20#ibcon#read 4, iclass 14, count 0 2006.161.07:46:53.20#ibcon#about to read 5, iclass 14, count 0 2006.161.07:46:53.20#ibcon#read 5, iclass 14, count 0 2006.161.07:46:53.20#ibcon#about to read 6, iclass 14, count 0 2006.161.07:46:53.20#ibcon#read 6, iclass 14, count 0 2006.161.07:46:53.20#ibcon#end of sib2, iclass 14, count 0 2006.161.07:46:53.20#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:46:53.20#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:46:53.20#ibcon#[27=USB\r\n] 2006.161.07:46:53.20#ibcon#*before write, iclass 14, count 0 2006.161.07:46:53.20#ibcon#enter sib2, iclass 14, count 0 2006.161.07:46:53.20#ibcon#flushed, iclass 14, count 0 2006.161.07:46:53.20#ibcon#about to write, iclass 14, count 0 2006.161.07:46:53.20#ibcon#wrote, iclass 14, count 0 2006.161.07:46:53.20#ibcon#about to read 3, iclass 14, count 0 2006.161.07:46:53.23#ibcon#read 3, iclass 14, count 0 2006.161.07:46:53.23#ibcon#about to read 4, iclass 14, count 0 2006.161.07:46:53.23#ibcon#read 4, iclass 14, count 0 2006.161.07:46:53.23#ibcon#about to read 5, iclass 14, count 0 2006.161.07:46:53.23#ibcon#read 5, iclass 14, count 0 2006.161.07:46:53.23#ibcon#about to read 6, iclass 14, count 0 2006.161.07:46:53.23#ibcon#read 6, iclass 14, count 0 2006.161.07:46:53.23#ibcon#end of sib2, iclass 14, count 0 2006.161.07:46:53.23#ibcon#*after write, iclass 14, count 0 2006.161.07:46:53.23#ibcon#*before return 0, iclass 14, count 0 2006.161.07:46:53.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:53.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:46:53.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:46:53.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:46:53.23$vc4f8/vblo=5,744.99 2006.161.07:46:53.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:46:53.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:46:53.23#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:53.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:53.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:53.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:53.23#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:46:53.23#ibcon#first serial, iclass 16, count 0 2006.161.07:46:53.23#ibcon#enter sib2, iclass 16, count 0 2006.161.07:46:53.23#ibcon#flushed, iclass 16, count 0 2006.161.07:46:53.23#ibcon#about to write, iclass 16, count 0 2006.161.07:46:53.23#ibcon#wrote, iclass 16, count 0 2006.161.07:46:53.23#ibcon#about to read 3, iclass 16, count 0 2006.161.07:46:53.25#ibcon#read 3, iclass 16, count 0 2006.161.07:46:53.25#ibcon#about to read 4, iclass 16, count 0 2006.161.07:46:53.25#ibcon#read 4, iclass 16, count 0 2006.161.07:46:53.25#ibcon#about to read 5, iclass 16, count 0 2006.161.07:46:53.25#ibcon#read 5, iclass 16, count 0 2006.161.07:46:53.25#ibcon#about to read 6, iclass 16, count 0 2006.161.07:46:53.25#ibcon#read 6, iclass 16, count 0 2006.161.07:46:53.25#ibcon#end of sib2, iclass 16, count 0 2006.161.07:46:53.25#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:46:53.25#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:46:53.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:46:53.25#ibcon#*before write, iclass 16, count 0 2006.161.07:46:53.25#ibcon#enter sib2, iclass 16, count 0 2006.161.07:46:53.25#ibcon#flushed, iclass 16, count 0 2006.161.07:46:53.25#ibcon#about to write, iclass 16, count 0 2006.161.07:46:53.25#ibcon#wrote, iclass 16, count 0 2006.161.07:46:53.25#ibcon#about to read 3, iclass 16, count 0 2006.161.07:46:53.29#ibcon#read 3, iclass 16, count 0 2006.161.07:46:53.29#ibcon#about to read 4, iclass 16, count 0 2006.161.07:46:53.29#ibcon#read 4, iclass 16, count 0 2006.161.07:46:53.29#ibcon#about to read 5, iclass 16, count 0 2006.161.07:46:53.29#ibcon#read 5, iclass 16, count 0 2006.161.07:46:53.29#ibcon#about to read 6, iclass 16, count 0 2006.161.07:46:53.29#ibcon#read 6, iclass 16, count 0 2006.161.07:46:53.29#ibcon#end of sib2, iclass 16, count 0 2006.161.07:46:53.29#ibcon#*after write, iclass 16, count 0 2006.161.07:46:53.29#ibcon#*before return 0, iclass 16, count 0 2006.161.07:46:53.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:53.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:46:53.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:46:53.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:46:53.29$vc4f8/vb=5,4 2006.161.07:46:53.29#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:46:53.29#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:46:53.29#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:53.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:53.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:53.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:53.35#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:46:53.35#ibcon#first serial, iclass 18, count 2 2006.161.07:46:53.35#ibcon#enter sib2, iclass 18, count 2 2006.161.07:46:53.35#ibcon#flushed, iclass 18, count 2 2006.161.07:46:53.35#ibcon#about to write, iclass 18, count 2 2006.161.07:46:53.35#ibcon#wrote, iclass 18, count 2 2006.161.07:46:53.35#ibcon#about to read 3, iclass 18, count 2 2006.161.07:46:53.37#ibcon#read 3, iclass 18, count 2 2006.161.07:46:53.37#ibcon#about to read 4, iclass 18, count 2 2006.161.07:46:53.37#ibcon#read 4, iclass 18, count 2 2006.161.07:46:53.37#ibcon#about to read 5, iclass 18, count 2 2006.161.07:46:53.37#ibcon#read 5, iclass 18, count 2 2006.161.07:46:53.37#ibcon#about to read 6, iclass 18, count 2 2006.161.07:46:53.37#ibcon#read 6, iclass 18, count 2 2006.161.07:46:53.37#ibcon#end of sib2, iclass 18, count 2 2006.161.07:46:53.37#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:46:53.37#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:46:53.37#ibcon#[27=AT05-04\r\n] 2006.161.07:46:53.37#ibcon#*before write, iclass 18, count 2 2006.161.07:46:53.37#ibcon#enter sib2, iclass 18, count 2 2006.161.07:46:53.37#ibcon#flushed, iclass 18, count 2 2006.161.07:46:53.37#ibcon#about to write, iclass 18, count 2 2006.161.07:46:53.37#ibcon#wrote, iclass 18, count 2 2006.161.07:46:53.37#ibcon#about to read 3, iclass 18, count 2 2006.161.07:46:53.40#ibcon#read 3, iclass 18, count 2 2006.161.07:46:53.40#ibcon#about to read 4, iclass 18, count 2 2006.161.07:46:53.40#ibcon#read 4, iclass 18, count 2 2006.161.07:46:53.40#ibcon#about to read 5, iclass 18, count 2 2006.161.07:46:53.40#ibcon#read 5, iclass 18, count 2 2006.161.07:46:53.40#ibcon#about to read 6, iclass 18, count 2 2006.161.07:46:53.40#ibcon#read 6, iclass 18, count 2 2006.161.07:46:53.40#ibcon#end of sib2, iclass 18, count 2 2006.161.07:46:53.40#ibcon#*after write, iclass 18, count 2 2006.161.07:46:53.40#ibcon#*before return 0, iclass 18, count 2 2006.161.07:46:53.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:53.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:46:53.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:46:53.40#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:53.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:53.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:53.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:53.52#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:46:53.52#ibcon#first serial, iclass 18, count 0 2006.161.07:46:53.52#ibcon#enter sib2, iclass 18, count 0 2006.161.07:46:53.52#ibcon#flushed, iclass 18, count 0 2006.161.07:46:53.52#ibcon#about to write, iclass 18, count 0 2006.161.07:46:53.52#ibcon#wrote, iclass 18, count 0 2006.161.07:46:53.52#ibcon#about to read 3, iclass 18, count 0 2006.161.07:46:53.54#ibcon#read 3, iclass 18, count 0 2006.161.07:46:53.54#ibcon#about to read 4, iclass 18, count 0 2006.161.07:46:53.54#ibcon#read 4, iclass 18, count 0 2006.161.07:46:53.54#ibcon#about to read 5, iclass 18, count 0 2006.161.07:46:53.54#ibcon#read 5, iclass 18, count 0 2006.161.07:46:53.54#ibcon#about to read 6, iclass 18, count 0 2006.161.07:46:53.54#ibcon#read 6, iclass 18, count 0 2006.161.07:46:53.54#ibcon#end of sib2, iclass 18, count 0 2006.161.07:46:53.54#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:46:53.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:46:53.54#ibcon#[27=USB\r\n] 2006.161.07:46:53.54#ibcon#*before write, iclass 18, count 0 2006.161.07:46:53.54#ibcon#enter sib2, iclass 18, count 0 2006.161.07:46:53.54#ibcon#flushed, iclass 18, count 0 2006.161.07:46:53.54#ibcon#about to write, iclass 18, count 0 2006.161.07:46:53.54#ibcon#wrote, iclass 18, count 0 2006.161.07:46:53.54#ibcon#about to read 3, iclass 18, count 0 2006.161.07:46:53.57#ibcon#read 3, iclass 18, count 0 2006.161.07:46:53.57#ibcon#about to read 4, iclass 18, count 0 2006.161.07:46:53.57#ibcon#read 4, iclass 18, count 0 2006.161.07:46:53.57#ibcon#about to read 5, iclass 18, count 0 2006.161.07:46:53.57#ibcon#read 5, iclass 18, count 0 2006.161.07:46:53.57#ibcon#about to read 6, iclass 18, count 0 2006.161.07:46:53.57#ibcon#read 6, iclass 18, count 0 2006.161.07:46:53.57#ibcon#end of sib2, iclass 18, count 0 2006.161.07:46:53.57#ibcon#*after write, iclass 18, count 0 2006.161.07:46:53.57#ibcon#*before return 0, iclass 18, count 0 2006.161.07:46:53.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:53.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:46:53.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:46:53.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:46:53.57$vc4f8/vblo=6,752.99 2006.161.07:46:53.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:46:53.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:46:53.57#ibcon#ireg 17 cls_cnt 0 2006.161.07:46:53.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:53.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:53.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:53.57#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:46:53.57#ibcon#first serial, iclass 20, count 0 2006.161.07:46:53.57#ibcon#enter sib2, iclass 20, count 0 2006.161.07:46:53.57#ibcon#flushed, iclass 20, count 0 2006.161.07:46:53.57#ibcon#about to write, iclass 20, count 0 2006.161.07:46:53.57#ibcon#wrote, iclass 20, count 0 2006.161.07:46:53.57#ibcon#about to read 3, iclass 20, count 0 2006.161.07:46:53.59#ibcon#read 3, iclass 20, count 0 2006.161.07:46:53.59#ibcon#about to read 4, iclass 20, count 0 2006.161.07:46:53.59#ibcon#read 4, iclass 20, count 0 2006.161.07:46:53.59#ibcon#about to read 5, iclass 20, count 0 2006.161.07:46:53.59#ibcon#read 5, iclass 20, count 0 2006.161.07:46:53.59#ibcon#about to read 6, iclass 20, count 0 2006.161.07:46:53.59#ibcon#read 6, iclass 20, count 0 2006.161.07:46:53.59#ibcon#end of sib2, iclass 20, count 0 2006.161.07:46:53.59#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:46:53.59#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:46:53.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:46:53.59#ibcon#*before write, iclass 20, count 0 2006.161.07:46:53.59#ibcon#enter sib2, iclass 20, count 0 2006.161.07:46:53.59#ibcon#flushed, iclass 20, count 0 2006.161.07:46:53.59#ibcon#about to write, iclass 20, count 0 2006.161.07:46:53.59#ibcon#wrote, iclass 20, count 0 2006.161.07:46:53.59#ibcon#about to read 3, iclass 20, count 0 2006.161.07:46:53.63#ibcon#read 3, iclass 20, count 0 2006.161.07:46:53.63#ibcon#about to read 4, iclass 20, count 0 2006.161.07:46:53.63#ibcon#read 4, iclass 20, count 0 2006.161.07:46:53.63#ibcon#about to read 5, iclass 20, count 0 2006.161.07:46:53.63#ibcon#read 5, iclass 20, count 0 2006.161.07:46:53.63#ibcon#about to read 6, iclass 20, count 0 2006.161.07:46:53.63#ibcon#read 6, iclass 20, count 0 2006.161.07:46:53.63#ibcon#end of sib2, iclass 20, count 0 2006.161.07:46:53.63#ibcon#*after write, iclass 20, count 0 2006.161.07:46:53.63#ibcon#*before return 0, iclass 20, count 0 2006.161.07:46:53.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:53.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:46:53.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:46:53.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:46:53.63$vc4f8/vb=6,4 2006.161.07:46:53.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:46:53.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:46:53.63#ibcon#ireg 11 cls_cnt 2 2006.161.07:46:53.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:53.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:53.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:53.69#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:46:53.69#ibcon#first serial, iclass 22, count 2 2006.161.07:46:53.69#ibcon#enter sib2, iclass 22, count 2 2006.161.07:46:53.69#ibcon#flushed, iclass 22, count 2 2006.161.07:46:53.69#ibcon#about to write, iclass 22, count 2 2006.161.07:46:53.69#ibcon#wrote, iclass 22, count 2 2006.161.07:46:53.69#ibcon#about to read 3, iclass 22, count 2 2006.161.07:46:53.71#ibcon#read 3, iclass 22, count 2 2006.161.07:46:53.71#ibcon#about to read 4, iclass 22, count 2 2006.161.07:46:53.71#ibcon#read 4, iclass 22, count 2 2006.161.07:46:53.71#ibcon#about to read 5, iclass 22, count 2 2006.161.07:46:53.71#ibcon#read 5, iclass 22, count 2 2006.161.07:46:53.71#ibcon#about to read 6, iclass 22, count 2 2006.161.07:46:53.71#ibcon#read 6, iclass 22, count 2 2006.161.07:46:53.71#ibcon#end of sib2, iclass 22, count 2 2006.161.07:46:53.71#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:46:53.71#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:46:53.71#ibcon#[27=AT06-04\r\n] 2006.161.07:46:53.71#ibcon#*before write, iclass 22, count 2 2006.161.07:46:53.71#ibcon#enter sib2, iclass 22, count 2 2006.161.07:46:53.71#ibcon#flushed, iclass 22, count 2 2006.161.07:46:53.71#ibcon#about to write, iclass 22, count 2 2006.161.07:46:53.71#ibcon#wrote, iclass 22, count 2 2006.161.07:46:53.71#ibcon#about to read 3, iclass 22, count 2 2006.161.07:46:53.74#ibcon#read 3, iclass 22, count 2 2006.161.07:46:53.74#ibcon#about to read 4, iclass 22, count 2 2006.161.07:46:53.74#ibcon#read 4, iclass 22, count 2 2006.161.07:46:53.74#ibcon#about to read 5, iclass 22, count 2 2006.161.07:46:53.74#ibcon#read 5, iclass 22, count 2 2006.161.07:46:53.74#ibcon#about to read 6, iclass 22, count 2 2006.161.07:46:53.74#ibcon#read 6, iclass 22, count 2 2006.161.07:46:53.74#ibcon#end of sib2, iclass 22, count 2 2006.161.07:46:53.74#ibcon#*after write, iclass 22, count 2 2006.161.07:46:53.74#ibcon#*before return 0, iclass 22, count 2 2006.161.07:46:53.74#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:53.74#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:46:53.74#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:46:53.74#ibcon#ireg 7 cls_cnt 0 2006.161.07:46:53.74#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:53.86#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:53.86#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:53.86#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:46:53.86#ibcon#first serial, iclass 22, count 0 2006.161.07:46:53.86#ibcon#enter sib2, iclass 22, count 0 2006.161.07:46:53.86#ibcon#flushed, iclass 22, count 0 2006.161.07:46:53.86#ibcon#about to write, iclass 22, count 0 2006.161.07:46:53.86#ibcon#wrote, iclass 22, count 0 2006.161.07:46:53.86#ibcon#about to read 3, iclass 22, count 0 2006.161.07:46:53.88#ibcon#read 3, iclass 22, count 0 2006.161.07:46:53.88#ibcon#about to read 4, iclass 22, count 0 2006.161.07:46:53.88#ibcon#read 4, iclass 22, count 0 2006.161.07:46:53.88#ibcon#about to read 5, iclass 22, count 0 2006.161.07:46:53.88#ibcon#read 5, iclass 22, count 0 2006.161.07:46:53.88#ibcon#about to read 6, iclass 22, count 0 2006.161.07:46:53.88#ibcon#read 6, iclass 22, count 0 2006.161.07:46:53.88#ibcon#end of sib2, iclass 22, count 0 2006.161.07:46:53.88#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:46:53.88#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:46:53.88#ibcon#[27=USB\r\n] 2006.161.07:46:53.88#ibcon#*before write, iclass 22, count 0 2006.161.07:46:53.88#ibcon#enter sib2, iclass 22, count 0 2006.161.07:46:53.88#ibcon#flushed, iclass 22, count 0 2006.161.07:46:53.88#ibcon#about to write, iclass 22, count 0 2006.161.07:46:53.88#ibcon#wrote, iclass 22, count 0 2006.161.07:46:53.88#ibcon#about to read 3, iclass 22, count 0 2006.161.07:46:53.91#ibcon#read 3, iclass 22, count 0 2006.161.07:46:53.91#ibcon#about to read 4, iclass 22, count 0 2006.161.07:46:53.91#ibcon#read 4, iclass 22, count 0 2006.161.07:46:53.91#ibcon#about to read 5, iclass 22, count 0 2006.161.07:46:53.91#ibcon#read 5, iclass 22, count 0 2006.161.07:46:53.91#ibcon#about to read 6, iclass 22, count 0 2006.161.07:46:53.91#ibcon#read 6, iclass 22, count 0 2006.161.07:46:53.91#ibcon#end of sib2, iclass 22, count 0 2006.161.07:46:53.91#ibcon#*after write, iclass 22, count 0 2006.161.07:46:53.91#ibcon#*before return 0, iclass 22, count 0 2006.161.07:46:53.91#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:53.91#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:46:53.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:46:53.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:46:53.91$vc4f8/vabw=wide 2006.161.07:46:53.91#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:46:53.91#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:46:53.91#ibcon#ireg 8 cls_cnt 0 2006.161.07:46:53.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:53.91#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:53.91#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:53.91#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:46:53.91#ibcon#first serial, iclass 24, count 0 2006.161.07:46:53.91#ibcon#enter sib2, iclass 24, count 0 2006.161.07:46:53.91#ibcon#flushed, iclass 24, count 0 2006.161.07:46:53.91#ibcon#about to write, iclass 24, count 0 2006.161.07:46:53.91#ibcon#wrote, iclass 24, count 0 2006.161.07:46:53.91#ibcon#about to read 3, iclass 24, count 0 2006.161.07:46:53.93#ibcon#read 3, iclass 24, count 0 2006.161.07:46:53.93#ibcon#about to read 4, iclass 24, count 0 2006.161.07:46:53.93#ibcon#read 4, iclass 24, count 0 2006.161.07:46:53.93#ibcon#about to read 5, iclass 24, count 0 2006.161.07:46:53.93#ibcon#read 5, iclass 24, count 0 2006.161.07:46:53.93#ibcon#about to read 6, iclass 24, count 0 2006.161.07:46:53.93#ibcon#read 6, iclass 24, count 0 2006.161.07:46:53.93#ibcon#end of sib2, iclass 24, count 0 2006.161.07:46:53.93#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:46:53.93#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:46:53.93#ibcon#[25=BW32\r\n] 2006.161.07:46:53.93#ibcon#*before write, iclass 24, count 0 2006.161.07:46:53.93#ibcon#enter sib2, iclass 24, count 0 2006.161.07:46:53.93#ibcon#flushed, iclass 24, count 0 2006.161.07:46:53.93#ibcon#about to write, iclass 24, count 0 2006.161.07:46:53.93#ibcon#wrote, iclass 24, count 0 2006.161.07:46:53.93#ibcon#about to read 3, iclass 24, count 0 2006.161.07:46:53.96#ibcon#read 3, iclass 24, count 0 2006.161.07:46:53.96#ibcon#about to read 4, iclass 24, count 0 2006.161.07:46:53.96#ibcon#read 4, iclass 24, count 0 2006.161.07:46:53.96#ibcon#about to read 5, iclass 24, count 0 2006.161.07:46:53.96#ibcon#read 5, iclass 24, count 0 2006.161.07:46:53.96#ibcon#about to read 6, iclass 24, count 0 2006.161.07:46:53.96#ibcon#read 6, iclass 24, count 0 2006.161.07:46:53.96#ibcon#end of sib2, iclass 24, count 0 2006.161.07:46:53.96#ibcon#*after write, iclass 24, count 0 2006.161.07:46:53.96#ibcon#*before return 0, iclass 24, count 0 2006.161.07:46:53.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:53.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:46:53.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:46:53.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:46:53.96$vc4f8/vbbw=wide 2006.161.07:46:53.96#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:46:53.96#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:46:53.96#ibcon#ireg 8 cls_cnt 0 2006.161.07:46:53.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:46:54.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:46:54.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:46:54.03#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:46:54.03#ibcon#first serial, iclass 26, count 0 2006.161.07:46:54.03#ibcon#enter sib2, iclass 26, count 0 2006.161.07:46:54.03#ibcon#flushed, iclass 26, count 0 2006.161.07:46:54.03#ibcon#about to write, iclass 26, count 0 2006.161.07:46:54.03#ibcon#wrote, iclass 26, count 0 2006.161.07:46:54.03#ibcon#about to read 3, iclass 26, count 0 2006.161.07:46:54.05#ibcon#read 3, iclass 26, count 0 2006.161.07:46:54.05#ibcon#about to read 4, iclass 26, count 0 2006.161.07:46:54.05#ibcon#read 4, iclass 26, count 0 2006.161.07:46:54.05#ibcon#about to read 5, iclass 26, count 0 2006.161.07:46:54.05#ibcon#read 5, iclass 26, count 0 2006.161.07:46:54.05#ibcon#about to read 6, iclass 26, count 0 2006.161.07:46:54.05#ibcon#read 6, iclass 26, count 0 2006.161.07:46:54.05#ibcon#end of sib2, iclass 26, count 0 2006.161.07:46:54.05#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:46:54.05#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:46:54.05#ibcon#[27=BW32\r\n] 2006.161.07:46:54.05#ibcon#*before write, iclass 26, count 0 2006.161.07:46:54.05#ibcon#enter sib2, iclass 26, count 0 2006.161.07:46:54.05#ibcon#flushed, iclass 26, count 0 2006.161.07:46:54.05#ibcon#about to write, iclass 26, count 0 2006.161.07:46:54.05#ibcon#wrote, iclass 26, count 0 2006.161.07:46:54.05#ibcon#about to read 3, iclass 26, count 0 2006.161.07:46:54.08#ibcon#read 3, iclass 26, count 0 2006.161.07:46:54.08#ibcon#about to read 4, iclass 26, count 0 2006.161.07:46:54.08#ibcon#read 4, iclass 26, count 0 2006.161.07:46:54.08#ibcon#about to read 5, iclass 26, count 0 2006.161.07:46:54.08#ibcon#read 5, iclass 26, count 0 2006.161.07:46:54.08#ibcon#about to read 6, iclass 26, count 0 2006.161.07:46:54.08#ibcon#read 6, iclass 26, count 0 2006.161.07:46:54.08#ibcon#end of sib2, iclass 26, count 0 2006.161.07:46:54.08#ibcon#*after write, iclass 26, count 0 2006.161.07:46:54.08#ibcon#*before return 0, iclass 26, count 0 2006.161.07:46:54.08#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:46:54.08#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:46:54.08#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:46:54.08#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:46:54.08$4f8m12a/ifd4f 2006.161.07:46:54.08$ifd4f/lo= 2006.161.07:46:54.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:46:54.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:46:54.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:46:54.08$ifd4f/patch= 2006.161.07:46:54.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:46:54.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:46:54.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:46:54.08$4f8m12a/"form=m,16.000,1:2 2006.161.07:46:54.08$4f8m12a/"tpicd 2006.161.07:46:54.08$4f8m12a/echo=off 2006.161.07:46:54.08$4f8m12a/xlog=off 2006.161.07:46:54.08:!2006.161.07:47:20 2006.161.07:47:02.14#trakl#Source acquired 2006.161.07:47:02.14#flagr#flagr/antenna,acquired 2006.161.07:47:20.00:preob 2006.161.07:47:21.14/onsource/TRACKING 2006.161.07:47:21.14:!2006.161.07:47:30 2006.161.07:47:30.00:data_valid=on 2006.161.07:47:30.00:midob 2006.161.07:47:30.14/onsource/TRACKING 2006.161.07:47:30.14/wx/24.08,1002.0,86 2006.161.07:47:30.21/cable/+6.4990E-03 2006.161.07:47:31.30/va/01,08,usb,yes,29,30 2006.161.07:47:31.30/va/02,07,usb,yes,29,30 2006.161.07:47:31.30/va/03,06,usb,yes,30,31 2006.161.07:47:31.30/va/04,07,usb,yes,30,32 2006.161.07:47:31.30/va/05,07,usb,yes,30,31 2006.161.07:47:31.30/va/06,06,usb,yes,29,29 2006.161.07:47:31.30/va/07,06,usb,yes,29,29 2006.161.07:47:31.30/va/08,07,usb,yes,28,27 2006.161.07:47:31.53/valo/01,532.99,yes,locked 2006.161.07:47:31.53/valo/02,572.99,yes,locked 2006.161.07:47:31.53/valo/03,672.99,yes,locked 2006.161.07:47:31.53/valo/04,832.99,yes,locked 2006.161.07:47:31.53/valo/05,652.99,yes,locked 2006.161.07:47:31.53/valo/06,772.99,yes,locked 2006.161.07:47:31.53/valo/07,832.99,yes,locked 2006.161.07:47:31.53/valo/08,852.99,yes,locked 2006.161.07:47:32.62/vb/01,04,usb,yes,29,28 2006.161.07:47:32.62/vb/02,04,usb,yes,30,32 2006.161.07:47:32.62/vb/03,04,usb,yes,27,31 2006.161.07:47:32.62/vb/04,04,usb,yes,28,28 2006.161.07:47:32.62/vb/05,04,usb,yes,26,30 2006.161.07:47:32.62/vb/06,04,usb,yes,27,30 2006.161.07:47:32.62/vb/07,04,usb,yes,29,29 2006.161.07:47:32.62/vb/08,04,usb,yes,27,30 2006.161.07:47:32.86/vblo/01,632.99,yes,locked 2006.161.07:47:32.86/vblo/02,640.99,yes,locked 2006.161.07:47:32.86/vblo/03,656.99,yes,locked 2006.161.07:47:32.86/vblo/04,712.99,yes,locked 2006.161.07:47:32.86/vblo/05,744.99,yes,locked 2006.161.07:47:32.86/vblo/06,752.99,yes,locked 2006.161.07:47:32.86/vblo/07,734.99,yes,locked 2006.161.07:47:32.86/vblo/08,744.99,yes,locked 2006.161.07:47:33.01/vabw/8 2006.161.07:47:33.16/vbbw/8 2006.161.07:47:33.25/xfe/off,on,14.2 2006.161.07:47:33.63/ifatt/23,28,28,28 2006.161.07:47:34.08/fmout-gps/S +4.47E-07 2006.161.07:47:34.12:!2006.161.07:48:30 2006.161.07:48:30.01:data_valid=off 2006.161.07:48:30.01:postob 2006.161.07:48:30.25/cable/+6.4992E-03 2006.161.07:48:30.25/wx/24.07,1002.1,86 2006.161.07:48:31.08/fmout-gps/S +4.47E-07 2006.161.07:48:31.08:scan_name=161-0749,k06161,140 2006.161.07:48:31.09:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.161.07:48:31.13#flagr#flagr/antenna,new-source 2006.161.07:48:32.13:checkk5 2006.161.07:48:32.54/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:48:32.96/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:48:33.41/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:48:33.86/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:48:34.32/chk_obsdata//k5ts1/T1610747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:48:34.74/chk_obsdata//k5ts2/T1610747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:48:35.38/chk_obsdata//k5ts3/T1610747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:48:35.82/chk_obsdata//k5ts4/T1610747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:48:36.71/k5log//k5ts1_log_newline 2006.161.07:48:37.52/k5log//k5ts2_log_newline 2006.161.07:48:38.30/k5log//k5ts3_log_newline 2006.161.07:48:39.15/k5log//k5ts4_log_newline 2006.161.07:48:39.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:48:39.22:4f8m12a=1 2006.161.07:48:39.22$4f8m12a/echo=on 2006.161.07:48:39.22$4f8m12a/pcalon 2006.161.07:48:39.22$pcalon/"no phase cal control is implemented here 2006.161.07:48:39.22$4f8m12a/"tpicd=stop 2006.161.07:48:39.22$4f8m12a/vc4f8 2006.161.07:48:39.22$vc4f8/valo=1,532.99 2006.161.07:48:39.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:48:39.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:48:39.22#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:39.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:39.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:39.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:39.22#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:48:39.22#ibcon#first serial, iclass 33, count 0 2006.161.07:48:39.22#ibcon#enter sib2, iclass 33, count 0 2006.161.07:48:39.22#ibcon#flushed, iclass 33, count 0 2006.161.07:48:39.22#ibcon#about to write, iclass 33, count 0 2006.161.07:48:39.22#ibcon#wrote, iclass 33, count 0 2006.161.07:48:39.22#ibcon#about to read 3, iclass 33, count 0 2006.161.07:48:39.24#ibcon#read 3, iclass 33, count 0 2006.161.07:48:39.24#ibcon#about to read 4, iclass 33, count 0 2006.161.07:48:39.24#ibcon#read 4, iclass 33, count 0 2006.161.07:48:39.24#ibcon#about to read 5, iclass 33, count 0 2006.161.07:48:39.24#ibcon#read 5, iclass 33, count 0 2006.161.07:48:39.24#ibcon#about to read 6, iclass 33, count 0 2006.161.07:48:39.24#ibcon#read 6, iclass 33, count 0 2006.161.07:48:39.24#ibcon#end of sib2, iclass 33, count 0 2006.161.07:48:39.24#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:48:39.24#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:48:39.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:48:39.24#ibcon#*before write, iclass 33, count 0 2006.161.07:48:39.24#ibcon#enter sib2, iclass 33, count 0 2006.161.07:48:39.24#ibcon#flushed, iclass 33, count 0 2006.161.07:48:39.24#ibcon#about to write, iclass 33, count 0 2006.161.07:48:39.24#ibcon#wrote, iclass 33, count 0 2006.161.07:48:39.24#ibcon#about to read 3, iclass 33, count 0 2006.161.07:48:39.29#ibcon#read 3, iclass 33, count 0 2006.161.07:48:39.29#ibcon#about to read 4, iclass 33, count 0 2006.161.07:48:39.29#ibcon#read 4, iclass 33, count 0 2006.161.07:48:39.29#ibcon#about to read 5, iclass 33, count 0 2006.161.07:48:39.29#ibcon#read 5, iclass 33, count 0 2006.161.07:48:39.29#ibcon#about to read 6, iclass 33, count 0 2006.161.07:48:39.29#ibcon#read 6, iclass 33, count 0 2006.161.07:48:39.29#ibcon#end of sib2, iclass 33, count 0 2006.161.07:48:39.29#ibcon#*after write, iclass 33, count 0 2006.161.07:48:39.29#ibcon#*before return 0, iclass 33, count 0 2006.161.07:48:39.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:39.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:39.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:48:39.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:48:39.29$vc4f8/va=1,8 2006.161.07:48:39.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.07:48:39.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.07:48:39.29#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:39.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:39.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:39.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:39.29#ibcon#enter wrdev, iclass 35, count 2 2006.161.07:48:39.29#ibcon#first serial, iclass 35, count 2 2006.161.07:48:39.29#ibcon#enter sib2, iclass 35, count 2 2006.161.07:48:39.29#ibcon#flushed, iclass 35, count 2 2006.161.07:48:39.29#ibcon#about to write, iclass 35, count 2 2006.161.07:48:39.29#ibcon#wrote, iclass 35, count 2 2006.161.07:48:39.29#ibcon#about to read 3, iclass 35, count 2 2006.161.07:48:39.31#ibcon#read 3, iclass 35, count 2 2006.161.07:48:39.31#ibcon#about to read 4, iclass 35, count 2 2006.161.07:48:39.31#ibcon#read 4, iclass 35, count 2 2006.161.07:48:39.31#ibcon#about to read 5, iclass 35, count 2 2006.161.07:48:39.31#ibcon#read 5, iclass 35, count 2 2006.161.07:48:39.31#ibcon#about to read 6, iclass 35, count 2 2006.161.07:48:39.31#ibcon#read 6, iclass 35, count 2 2006.161.07:48:39.31#ibcon#end of sib2, iclass 35, count 2 2006.161.07:48:39.31#ibcon#*mode == 0, iclass 35, count 2 2006.161.07:48:39.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.07:48:39.31#ibcon#[25=AT01-08\r\n] 2006.161.07:48:39.31#ibcon#*before write, iclass 35, count 2 2006.161.07:48:39.31#ibcon#enter sib2, iclass 35, count 2 2006.161.07:48:39.31#ibcon#flushed, iclass 35, count 2 2006.161.07:48:39.31#ibcon#about to write, iclass 35, count 2 2006.161.07:48:39.31#ibcon#wrote, iclass 35, count 2 2006.161.07:48:39.31#ibcon#about to read 3, iclass 35, count 2 2006.161.07:48:39.34#ibcon#read 3, iclass 35, count 2 2006.161.07:48:39.34#ibcon#about to read 4, iclass 35, count 2 2006.161.07:48:39.34#ibcon#read 4, iclass 35, count 2 2006.161.07:48:39.34#ibcon#about to read 5, iclass 35, count 2 2006.161.07:48:39.34#ibcon#read 5, iclass 35, count 2 2006.161.07:48:39.34#ibcon#about to read 6, iclass 35, count 2 2006.161.07:48:39.34#ibcon#read 6, iclass 35, count 2 2006.161.07:48:39.34#ibcon#end of sib2, iclass 35, count 2 2006.161.07:48:39.34#ibcon#*after write, iclass 35, count 2 2006.161.07:48:39.34#ibcon#*before return 0, iclass 35, count 2 2006.161.07:48:39.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:39.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:39.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.07:48:39.34#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:39.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:39.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:39.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:39.46#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:48:39.46#ibcon#first serial, iclass 35, count 0 2006.161.07:48:39.46#ibcon#enter sib2, iclass 35, count 0 2006.161.07:48:39.46#ibcon#flushed, iclass 35, count 0 2006.161.07:48:39.46#ibcon#about to write, iclass 35, count 0 2006.161.07:48:39.46#ibcon#wrote, iclass 35, count 0 2006.161.07:48:39.46#ibcon#about to read 3, iclass 35, count 0 2006.161.07:48:39.48#ibcon#read 3, iclass 35, count 0 2006.161.07:48:39.48#ibcon#about to read 4, iclass 35, count 0 2006.161.07:48:39.48#ibcon#read 4, iclass 35, count 0 2006.161.07:48:39.48#ibcon#about to read 5, iclass 35, count 0 2006.161.07:48:39.48#ibcon#read 5, iclass 35, count 0 2006.161.07:48:39.48#ibcon#about to read 6, iclass 35, count 0 2006.161.07:48:39.48#ibcon#read 6, iclass 35, count 0 2006.161.07:48:39.48#ibcon#end of sib2, iclass 35, count 0 2006.161.07:48:39.48#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:48:39.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:48:39.48#ibcon#[25=USB\r\n] 2006.161.07:48:39.48#ibcon#*before write, iclass 35, count 0 2006.161.07:48:39.48#ibcon#enter sib2, iclass 35, count 0 2006.161.07:48:39.48#ibcon#flushed, iclass 35, count 0 2006.161.07:48:39.48#ibcon#about to write, iclass 35, count 0 2006.161.07:48:39.48#ibcon#wrote, iclass 35, count 0 2006.161.07:48:39.48#ibcon#about to read 3, iclass 35, count 0 2006.161.07:48:39.51#ibcon#read 3, iclass 35, count 0 2006.161.07:48:39.51#ibcon#about to read 4, iclass 35, count 0 2006.161.07:48:39.51#ibcon#read 4, iclass 35, count 0 2006.161.07:48:39.51#ibcon#about to read 5, iclass 35, count 0 2006.161.07:48:39.51#ibcon#read 5, iclass 35, count 0 2006.161.07:48:39.51#ibcon#about to read 6, iclass 35, count 0 2006.161.07:48:39.51#ibcon#read 6, iclass 35, count 0 2006.161.07:48:39.51#ibcon#end of sib2, iclass 35, count 0 2006.161.07:48:39.51#ibcon#*after write, iclass 35, count 0 2006.161.07:48:39.51#ibcon#*before return 0, iclass 35, count 0 2006.161.07:48:39.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:39.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:39.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:48:39.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:48:39.51$vc4f8/valo=2,572.99 2006.161.07:48:39.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:48:39.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:48:39.51#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:39.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:39.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:39.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:39.51#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:48:39.51#ibcon#first serial, iclass 37, count 0 2006.161.07:48:39.51#ibcon#enter sib2, iclass 37, count 0 2006.161.07:48:39.51#ibcon#flushed, iclass 37, count 0 2006.161.07:48:39.51#ibcon#about to write, iclass 37, count 0 2006.161.07:48:39.51#ibcon#wrote, iclass 37, count 0 2006.161.07:48:39.51#ibcon#about to read 3, iclass 37, count 0 2006.161.07:48:39.53#ibcon#read 3, iclass 37, count 0 2006.161.07:48:39.53#ibcon#about to read 4, iclass 37, count 0 2006.161.07:48:39.53#ibcon#read 4, iclass 37, count 0 2006.161.07:48:39.53#ibcon#about to read 5, iclass 37, count 0 2006.161.07:48:39.53#ibcon#read 5, iclass 37, count 0 2006.161.07:48:39.53#ibcon#about to read 6, iclass 37, count 0 2006.161.07:48:39.53#ibcon#read 6, iclass 37, count 0 2006.161.07:48:39.53#ibcon#end of sib2, iclass 37, count 0 2006.161.07:48:39.53#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:48:39.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:48:39.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:48:39.53#ibcon#*before write, iclass 37, count 0 2006.161.07:48:39.53#ibcon#enter sib2, iclass 37, count 0 2006.161.07:48:39.53#ibcon#flushed, iclass 37, count 0 2006.161.07:48:39.53#ibcon#about to write, iclass 37, count 0 2006.161.07:48:39.53#ibcon#wrote, iclass 37, count 0 2006.161.07:48:39.53#ibcon#about to read 3, iclass 37, count 0 2006.161.07:48:39.57#ibcon#read 3, iclass 37, count 0 2006.161.07:48:39.57#ibcon#about to read 4, iclass 37, count 0 2006.161.07:48:39.57#ibcon#read 4, iclass 37, count 0 2006.161.07:48:39.57#ibcon#about to read 5, iclass 37, count 0 2006.161.07:48:39.57#ibcon#read 5, iclass 37, count 0 2006.161.07:48:39.57#ibcon#about to read 6, iclass 37, count 0 2006.161.07:48:39.57#ibcon#read 6, iclass 37, count 0 2006.161.07:48:39.57#ibcon#end of sib2, iclass 37, count 0 2006.161.07:48:39.57#ibcon#*after write, iclass 37, count 0 2006.161.07:48:39.57#ibcon#*before return 0, iclass 37, count 0 2006.161.07:48:39.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:39.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:39.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:48:39.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:48:39.57$vc4f8/va=2,7 2006.161.07:48:39.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.07:48:39.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.07:48:39.57#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:39.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:39.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:39.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:39.63#ibcon#enter wrdev, iclass 39, count 2 2006.161.07:48:39.63#ibcon#first serial, iclass 39, count 2 2006.161.07:48:39.63#ibcon#enter sib2, iclass 39, count 2 2006.161.07:48:39.63#ibcon#flushed, iclass 39, count 2 2006.161.07:48:39.63#ibcon#about to write, iclass 39, count 2 2006.161.07:48:39.63#ibcon#wrote, iclass 39, count 2 2006.161.07:48:39.63#ibcon#about to read 3, iclass 39, count 2 2006.161.07:48:39.66#ibcon#read 3, iclass 39, count 2 2006.161.07:48:39.66#ibcon#about to read 4, iclass 39, count 2 2006.161.07:48:39.66#ibcon#read 4, iclass 39, count 2 2006.161.07:48:39.66#ibcon#about to read 5, iclass 39, count 2 2006.161.07:48:39.66#ibcon#read 5, iclass 39, count 2 2006.161.07:48:39.66#ibcon#about to read 6, iclass 39, count 2 2006.161.07:48:39.66#ibcon#read 6, iclass 39, count 2 2006.161.07:48:39.66#ibcon#end of sib2, iclass 39, count 2 2006.161.07:48:39.66#ibcon#*mode == 0, iclass 39, count 2 2006.161.07:48:39.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.07:48:39.66#ibcon#[25=AT02-07\r\n] 2006.161.07:48:39.66#ibcon#*before write, iclass 39, count 2 2006.161.07:48:39.66#ibcon#enter sib2, iclass 39, count 2 2006.161.07:48:39.66#ibcon#flushed, iclass 39, count 2 2006.161.07:48:39.66#ibcon#about to write, iclass 39, count 2 2006.161.07:48:39.66#ibcon#wrote, iclass 39, count 2 2006.161.07:48:39.66#ibcon#about to read 3, iclass 39, count 2 2006.161.07:48:39.69#ibcon#read 3, iclass 39, count 2 2006.161.07:48:39.69#ibcon#about to read 4, iclass 39, count 2 2006.161.07:48:39.69#ibcon#read 4, iclass 39, count 2 2006.161.07:48:39.69#ibcon#about to read 5, iclass 39, count 2 2006.161.07:48:39.69#ibcon#read 5, iclass 39, count 2 2006.161.07:48:39.69#ibcon#about to read 6, iclass 39, count 2 2006.161.07:48:39.69#ibcon#read 6, iclass 39, count 2 2006.161.07:48:39.69#ibcon#end of sib2, iclass 39, count 2 2006.161.07:48:39.69#ibcon#*after write, iclass 39, count 2 2006.161.07:48:39.69#ibcon#*before return 0, iclass 39, count 2 2006.161.07:48:39.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:39.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:39.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.07:48:39.69#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:39.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:39.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:39.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:39.81#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:48:39.81#ibcon#first serial, iclass 39, count 0 2006.161.07:48:39.81#ibcon#enter sib2, iclass 39, count 0 2006.161.07:48:39.81#ibcon#flushed, iclass 39, count 0 2006.161.07:48:39.81#ibcon#about to write, iclass 39, count 0 2006.161.07:48:39.81#ibcon#wrote, iclass 39, count 0 2006.161.07:48:39.81#ibcon#about to read 3, iclass 39, count 0 2006.161.07:48:39.83#ibcon#read 3, iclass 39, count 0 2006.161.07:48:39.83#ibcon#about to read 4, iclass 39, count 0 2006.161.07:48:39.83#ibcon#read 4, iclass 39, count 0 2006.161.07:48:39.83#ibcon#about to read 5, iclass 39, count 0 2006.161.07:48:39.83#ibcon#read 5, iclass 39, count 0 2006.161.07:48:39.83#ibcon#about to read 6, iclass 39, count 0 2006.161.07:48:39.83#ibcon#read 6, iclass 39, count 0 2006.161.07:48:39.83#ibcon#end of sib2, iclass 39, count 0 2006.161.07:48:39.83#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:48:39.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:48:39.83#ibcon#[25=USB\r\n] 2006.161.07:48:39.83#ibcon#*before write, iclass 39, count 0 2006.161.07:48:39.83#ibcon#enter sib2, iclass 39, count 0 2006.161.07:48:39.83#ibcon#flushed, iclass 39, count 0 2006.161.07:48:39.83#ibcon#about to write, iclass 39, count 0 2006.161.07:48:39.83#ibcon#wrote, iclass 39, count 0 2006.161.07:48:39.83#ibcon#about to read 3, iclass 39, count 0 2006.161.07:48:39.86#ibcon#read 3, iclass 39, count 0 2006.161.07:48:39.86#ibcon#about to read 4, iclass 39, count 0 2006.161.07:48:39.86#ibcon#read 4, iclass 39, count 0 2006.161.07:48:39.86#ibcon#about to read 5, iclass 39, count 0 2006.161.07:48:39.86#ibcon#read 5, iclass 39, count 0 2006.161.07:48:39.86#ibcon#about to read 6, iclass 39, count 0 2006.161.07:48:39.86#ibcon#read 6, iclass 39, count 0 2006.161.07:48:39.86#ibcon#end of sib2, iclass 39, count 0 2006.161.07:48:39.86#ibcon#*after write, iclass 39, count 0 2006.161.07:48:39.86#ibcon#*before return 0, iclass 39, count 0 2006.161.07:48:39.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:39.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:39.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:48:39.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:48:39.86$vc4f8/valo=3,672.99 2006.161.07:48:39.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.07:48:39.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.07:48:39.86#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:39.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:39.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:39.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:39.86#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:48:39.86#ibcon#first serial, iclass 3, count 0 2006.161.07:48:39.86#ibcon#enter sib2, iclass 3, count 0 2006.161.07:48:39.86#ibcon#flushed, iclass 3, count 0 2006.161.07:48:39.86#ibcon#about to write, iclass 3, count 0 2006.161.07:48:39.86#ibcon#wrote, iclass 3, count 0 2006.161.07:48:39.86#ibcon#about to read 3, iclass 3, count 0 2006.161.07:48:39.88#ibcon#read 3, iclass 3, count 0 2006.161.07:48:39.88#ibcon#about to read 4, iclass 3, count 0 2006.161.07:48:39.88#ibcon#read 4, iclass 3, count 0 2006.161.07:48:39.88#ibcon#about to read 5, iclass 3, count 0 2006.161.07:48:39.88#ibcon#read 5, iclass 3, count 0 2006.161.07:48:39.88#ibcon#about to read 6, iclass 3, count 0 2006.161.07:48:39.88#ibcon#read 6, iclass 3, count 0 2006.161.07:48:39.88#ibcon#end of sib2, iclass 3, count 0 2006.161.07:48:39.88#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:48:39.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:48:39.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:48:39.88#ibcon#*before write, iclass 3, count 0 2006.161.07:48:39.88#ibcon#enter sib2, iclass 3, count 0 2006.161.07:48:39.88#ibcon#flushed, iclass 3, count 0 2006.161.07:48:39.88#ibcon#about to write, iclass 3, count 0 2006.161.07:48:39.88#ibcon#wrote, iclass 3, count 0 2006.161.07:48:39.88#ibcon#about to read 3, iclass 3, count 0 2006.161.07:48:39.92#ibcon#read 3, iclass 3, count 0 2006.161.07:48:39.92#ibcon#about to read 4, iclass 3, count 0 2006.161.07:48:39.92#ibcon#read 4, iclass 3, count 0 2006.161.07:48:39.92#ibcon#about to read 5, iclass 3, count 0 2006.161.07:48:39.92#ibcon#read 5, iclass 3, count 0 2006.161.07:48:39.92#ibcon#about to read 6, iclass 3, count 0 2006.161.07:48:39.92#ibcon#read 6, iclass 3, count 0 2006.161.07:48:39.92#ibcon#end of sib2, iclass 3, count 0 2006.161.07:48:39.92#ibcon#*after write, iclass 3, count 0 2006.161.07:48:39.92#ibcon#*before return 0, iclass 3, count 0 2006.161.07:48:39.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:39.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:39.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:48:39.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:48:39.92$vc4f8/va=3,6 2006.161.07:48:39.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.07:48:39.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.07:48:39.92#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:39.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:39.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:39.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:39.98#ibcon#enter wrdev, iclass 5, count 2 2006.161.07:48:39.98#ibcon#first serial, iclass 5, count 2 2006.161.07:48:39.98#ibcon#enter sib2, iclass 5, count 2 2006.161.07:48:39.98#ibcon#flushed, iclass 5, count 2 2006.161.07:48:39.98#ibcon#about to write, iclass 5, count 2 2006.161.07:48:39.98#ibcon#wrote, iclass 5, count 2 2006.161.07:48:39.98#ibcon#about to read 3, iclass 5, count 2 2006.161.07:48:40.01#ibcon#read 3, iclass 5, count 2 2006.161.07:48:40.01#ibcon#about to read 4, iclass 5, count 2 2006.161.07:48:40.01#ibcon#read 4, iclass 5, count 2 2006.161.07:48:40.01#ibcon#about to read 5, iclass 5, count 2 2006.161.07:48:40.01#ibcon#read 5, iclass 5, count 2 2006.161.07:48:40.01#ibcon#about to read 6, iclass 5, count 2 2006.161.07:48:40.01#ibcon#read 6, iclass 5, count 2 2006.161.07:48:40.01#ibcon#end of sib2, iclass 5, count 2 2006.161.07:48:40.01#ibcon#*mode == 0, iclass 5, count 2 2006.161.07:48:40.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.07:48:40.01#ibcon#[25=AT03-06\r\n] 2006.161.07:48:40.01#ibcon#*before write, iclass 5, count 2 2006.161.07:48:40.01#ibcon#enter sib2, iclass 5, count 2 2006.161.07:48:40.01#ibcon#flushed, iclass 5, count 2 2006.161.07:48:40.01#ibcon#about to write, iclass 5, count 2 2006.161.07:48:40.01#ibcon#wrote, iclass 5, count 2 2006.161.07:48:40.01#ibcon#about to read 3, iclass 5, count 2 2006.161.07:48:40.04#ibcon#read 3, iclass 5, count 2 2006.161.07:48:40.04#ibcon#about to read 4, iclass 5, count 2 2006.161.07:48:40.04#ibcon#read 4, iclass 5, count 2 2006.161.07:48:40.04#ibcon#about to read 5, iclass 5, count 2 2006.161.07:48:40.04#ibcon#read 5, iclass 5, count 2 2006.161.07:48:40.04#ibcon#about to read 6, iclass 5, count 2 2006.161.07:48:40.04#ibcon#read 6, iclass 5, count 2 2006.161.07:48:40.04#ibcon#end of sib2, iclass 5, count 2 2006.161.07:48:40.04#ibcon#*after write, iclass 5, count 2 2006.161.07:48:40.04#ibcon#*before return 0, iclass 5, count 2 2006.161.07:48:40.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:40.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:40.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.07:48:40.04#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:40.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:40.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:40.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:40.16#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:48:40.16#ibcon#first serial, iclass 5, count 0 2006.161.07:48:40.16#ibcon#enter sib2, iclass 5, count 0 2006.161.07:48:40.16#ibcon#flushed, iclass 5, count 0 2006.161.07:48:40.16#ibcon#about to write, iclass 5, count 0 2006.161.07:48:40.16#ibcon#wrote, iclass 5, count 0 2006.161.07:48:40.16#ibcon#about to read 3, iclass 5, count 0 2006.161.07:48:40.18#ibcon#read 3, iclass 5, count 0 2006.161.07:48:40.18#ibcon#about to read 4, iclass 5, count 0 2006.161.07:48:40.18#ibcon#read 4, iclass 5, count 0 2006.161.07:48:40.18#ibcon#about to read 5, iclass 5, count 0 2006.161.07:48:40.18#ibcon#read 5, iclass 5, count 0 2006.161.07:48:40.18#ibcon#about to read 6, iclass 5, count 0 2006.161.07:48:40.18#ibcon#read 6, iclass 5, count 0 2006.161.07:48:40.18#ibcon#end of sib2, iclass 5, count 0 2006.161.07:48:40.18#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:48:40.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:48:40.18#ibcon#[25=USB\r\n] 2006.161.07:48:40.18#ibcon#*before write, iclass 5, count 0 2006.161.07:48:40.18#ibcon#enter sib2, iclass 5, count 0 2006.161.07:48:40.18#ibcon#flushed, iclass 5, count 0 2006.161.07:48:40.18#ibcon#about to write, iclass 5, count 0 2006.161.07:48:40.18#ibcon#wrote, iclass 5, count 0 2006.161.07:48:40.18#ibcon#about to read 3, iclass 5, count 0 2006.161.07:48:40.21#ibcon#read 3, iclass 5, count 0 2006.161.07:48:40.21#ibcon#about to read 4, iclass 5, count 0 2006.161.07:48:40.21#ibcon#read 4, iclass 5, count 0 2006.161.07:48:40.21#ibcon#about to read 5, iclass 5, count 0 2006.161.07:48:40.21#ibcon#read 5, iclass 5, count 0 2006.161.07:48:40.21#ibcon#about to read 6, iclass 5, count 0 2006.161.07:48:40.21#ibcon#read 6, iclass 5, count 0 2006.161.07:48:40.21#ibcon#end of sib2, iclass 5, count 0 2006.161.07:48:40.21#ibcon#*after write, iclass 5, count 0 2006.161.07:48:40.21#ibcon#*before return 0, iclass 5, count 0 2006.161.07:48:40.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:40.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:40.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:48:40.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:48:40.21$vc4f8/valo=4,832.99 2006.161.07:48:40.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:48:40.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:48:40.21#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:40.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:40.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:40.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:40.21#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:48:40.21#ibcon#first serial, iclass 7, count 0 2006.161.07:48:40.21#ibcon#enter sib2, iclass 7, count 0 2006.161.07:48:40.21#ibcon#flushed, iclass 7, count 0 2006.161.07:48:40.21#ibcon#about to write, iclass 7, count 0 2006.161.07:48:40.21#ibcon#wrote, iclass 7, count 0 2006.161.07:48:40.21#ibcon#about to read 3, iclass 7, count 0 2006.161.07:48:40.23#ibcon#read 3, iclass 7, count 0 2006.161.07:48:40.23#ibcon#about to read 4, iclass 7, count 0 2006.161.07:48:40.23#ibcon#read 4, iclass 7, count 0 2006.161.07:48:40.23#ibcon#about to read 5, iclass 7, count 0 2006.161.07:48:40.23#ibcon#read 5, iclass 7, count 0 2006.161.07:48:40.23#ibcon#about to read 6, iclass 7, count 0 2006.161.07:48:40.23#ibcon#read 6, iclass 7, count 0 2006.161.07:48:40.23#ibcon#end of sib2, iclass 7, count 0 2006.161.07:48:40.23#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:48:40.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:48:40.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:48:40.23#ibcon#*before write, iclass 7, count 0 2006.161.07:48:40.23#ibcon#enter sib2, iclass 7, count 0 2006.161.07:48:40.23#ibcon#flushed, iclass 7, count 0 2006.161.07:48:40.23#ibcon#about to write, iclass 7, count 0 2006.161.07:48:40.23#ibcon#wrote, iclass 7, count 0 2006.161.07:48:40.23#ibcon#about to read 3, iclass 7, count 0 2006.161.07:48:40.27#ibcon#read 3, iclass 7, count 0 2006.161.07:48:40.27#ibcon#about to read 4, iclass 7, count 0 2006.161.07:48:40.27#ibcon#read 4, iclass 7, count 0 2006.161.07:48:40.27#ibcon#about to read 5, iclass 7, count 0 2006.161.07:48:40.27#ibcon#read 5, iclass 7, count 0 2006.161.07:48:40.27#ibcon#about to read 6, iclass 7, count 0 2006.161.07:48:40.27#ibcon#read 6, iclass 7, count 0 2006.161.07:48:40.27#ibcon#end of sib2, iclass 7, count 0 2006.161.07:48:40.27#ibcon#*after write, iclass 7, count 0 2006.161.07:48:40.27#ibcon#*before return 0, iclass 7, count 0 2006.161.07:48:40.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:40.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:40.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:48:40.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:48:40.27$vc4f8/va=4,7 2006.161.07:48:40.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:48:40.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:48:40.27#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:40.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:40.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:40.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:40.33#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:48:40.33#ibcon#first serial, iclass 11, count 2 2006.161.07:48:40.33#ibcon#enter sib2, iclass 11, count 2 2006.161.07:48:40.33#ibcon#flushed, iclass 11, count 2 2006.161.07:48:40.33#ibcon#about to write, iclass 11, count 2 2006.161.07:48:40.33#ibcon#wrote, iclass 11, count 2 2006.161.07:48:40.33#ibcon#about to read 3, iclass 11, count 2 2006.161.07:48:40.35#ibcon#read 3, iclass 11, count 2 2006.161.07:48:40.35#ibcon#about to read 4, iclass 11, count 2 2006.161.07:48:40.35#ibcon#read 4, iclass 11, count 2 2006.161.07:48:40.35#ibcon#about to read 5, iclass 11, count 2 2006.161.07:48:40.35#ibcon#read 5, iclass 11, count 2 2006.161.07:48:40.35#ibcon#about to read 6, iclass 11, count 2 2006.161.07:48:40.35#ibcon#read 6, iclass 11, count 2 2006.161.07:48:40.35#ibcon#end of sib2, iclass 11, count 2 2006.161.07:48:40.35#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:48:40.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:48:40.35#ibcon#[25=AT04-07\r\n] 2006.161.07:48:40.35#ibcon#*before write, iclass 11, count 2 2006.161.07:48:40.35#ibcon#enter sib2, iclass 11, count 2 2006.161.07:48:40.35#ibcon#flushed, iclass 11, count 2 2006.161.07:48:40.35#ibcon#about to write, iclass 11, count 2 2006.161.07:48:40.35#ibcon#wrote, iclass 11, count 2 2006.161.07:48:40.35#ibcon#about to read 3, iclass 11, count 2 2006.161.07:48:40.38#ibcon#read 3, iclass 11, count 2 2006.161.07:48:40.38#ibcon#about to read 4, iclass 11, count 2 2006.161.07:48:40.38#ibcon#read 4, iclass 11, count 2 2006.161.07:48:40.38#ibcon#about to read 5, iclass 11, count 2 2006.161.07:48:40.38#ibcon#read 5, iclass 11, count 2 2006.161.07:48:40.38#ibcon#about to read 6, iclass 11, count 2 2006.161.07:48:40.38#ibcon#read 6, iclass 11, count 2 2006.161.07:48:40.38#ibcon#end of sib2, iclass 11, count 2 2006.161.07:48:40.38#ibcon#*after write, iclass 11, count 2 2006.161.07:48:40.38#ibcon#*before return 0, iclass 11, count 2 2006.161.07:48:40.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:40.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:40.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:48:40.38#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:40.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:40.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:40.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:40.50#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:48:40.50#ibcon#first serial, iclass 11, count 0 2006.161.07:48:40.50#ibcon#enter sib2, iclass 11, count 0 2006.161.07:48:40.50#ibcon#flushed, iclass 11, count 0 2006.161.07:48:40.50#ibcon#about to write, iclass 11, count 0 2006.161.07:48:40.50#ibcon#wrote, iclass 11, count 0 2006.161.07:48:40.50#ibcon#about to read 3, iclass 11, count 0 2006.161.07:48:40.52#ibcon#read 3, iclass 11, count 0 2006.161.07:48:40.52#ibcon#about to read 4, iclass 11, count 0 2006.161.07:48:40.52#ibcon#read 4, iclass 11, count 0 2006.161.07:48:40.52#ibcon#about to read 5, iclass 11, count 0 2006.161.07:48:40.52#ibcon#read 5, iclass 11, count 0 2006.161.07:48:40.52#ibcon#about to read 6, iclass 11, count 0 2006.161.07:48:40.52#ibcon#read 6, iclass 11, count 0 2006.161.07:48:40.52#ibcon#end of sib2, iclass 11, count 0 2006.161.07:48:40.52#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:48:40.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:48:40.52#ibcon#[25=USB\r\n] 2006.161.07:48:40.52#ibcon#*before write, iclass 11, count 0 2006.161.07:48:40.52#ibcon#enter sib2, iclass 11, count 0 2006.161.07:48:40.52#ibcon#flushed, iclass 11, count 0 2006.161.07:48:40.52#ibcon#about to write, iclass 11, count 0 2006.161.07:48:40.52#ibcon#wrote, iclass 11, count 0 2006.161.07:48:40.52#ibcon#about to read 3, iclass 11, count 0 2006.161.07:48:40.55#ibcon#read 3, iclass 11, count 0 2006.161.07:48:40.55#ibcon#about to read 4, iclass 11, count 0 2006.161.07:48:40.55#ibcon#read 4, iclass 11, count 0 2006.161.07:48:40.55#ibcon#about to read 5, iclass 11, count 0 2006.161.07:48:40.55#ibcon#read 5, iclass 11, count 0 2006.161.07:48:40.55#ibcon#about to read 6, iclass 11, count 0 2006.161.07:48:40.55#ibcon#read 6, iclass 11, count 0 2006.161.07:48:40.55#ibcon#end of sib2, iclass 11, count 0 2006.161.07:48:40.55#ibcon#*after write, iclass 11, count 0 2006.161.07:48:40.55#ibcon#*before return 0, iclass 11, count 0 2006.161.07:48:40.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:40.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:40.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:48:40.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:48:40.55$vc4f8/valo=5,652.99 2006.161.07:48:40.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:48:40.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:48:40.55#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:40.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:40.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:40.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:40.55#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:48:40.55#ibcon#first serial, iclass 13, count 0 2006.161.07:48:40.55#ibcon#enter sib2, iclass 13, count 0 2006.161.07:48:40.55#ibcon#flushed, iclass 13, count 0 2006.161.07:48:40.55#ibcon#about to write, iclass 13, count 0 2006.161.07:48:40.55#ibcon#wrote, iclass 13, count 0 2006.161.07:48:40.55#ibcon#about to read 3, iclass 13, count 0 2006.161.07:48:40.58#ibcon#read 3, iclass 13, count 0 2006.161.07:48:40.58#ibcon#about to read 4, iclass 13, count 0 2006.161.07:48:40.58#ibcon#read 4, iclass 13, count 0 2006.161.07:48:40.58#ibcon#about to read 5, iclass 13, count 0 2006.161.07:48:40.58#ibcon#read 5, iclass 13, count 0 2006.161.07:48:40.58#ibcon#about to read 6, iclass 13, count 0 2006.161.07:48:40.58#ibcon#read 6, iclass 13, count 0 2006.161.07:48:40.58#ibcon#end of sib2, iclass 13, count 0 2006.161.07:48:40.58#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:48:40.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:48:40.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:48:40.58#ibcon#*before write, iclass 13, count 0 2006.161.07:48:40.58#ibcon#enter sib2, iclass 13, count 0 2006.161.07:48:40.58#ibcon#flushed, iclass 13, count 0 2006.161.07:48:40.58#ibcon#about to write, iclass 13, count 0 2006.161.07:48:40.58#ibcon#wrote, iclass 13, count 0 2006.161.07:48:40.58#ibcon#about to read 3, iclass 13, count 0 2006.161.07:48:40.62#ibcon#read 3, iclass 13, count 0 2006.161.07:48:40.62#ibcon#about to read 4, iclass 13, count 0 2006.161.07:48:40.62#ibcon#read 4, iclass 13, count 0 2006.161.07:48:40.62#ibcon#about to read 5, iclass 13, count 0 2006.161.07:48:40.62#ibcon#read 5, iclass 13, count 0 2006.161.07:48:40.62#ibcon#about to read 6, iclass 13, count 0 2006.161.07:48:40.62#ibcon#read 6, iclass 13, count 0 2006.161.07:48:40.62#ibcon#end of sib2, iclass 13, count 0 2006.161.07:48:40.62#ibcon#*after write, iclass 13, count 0 2006.161.07:48:40.62#ibcon#*before return 0, iclass 13, count 0 2006.161.07:48:40.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:40.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:40.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:48:40.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:48:40.62$vc4f8/va=5,7 2006.161.07:48:40.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:48:40.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:48:40.62#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:40.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:40.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:40.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:40.67#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:48:40.67#ibcon#first serial, iclass 15, count 2 2006.161.07:48:40.67#ibcon#enter sib2, iclass 15, count 2 2006.161.07:48:40.67#ibcon#flushed, iclass 15, count 2 2006.161.07:48:40.67#ibcon#about to write, iclass 15, count 2 2006.161.07:48:40.67#ibcon#wrote, iclass 15, count 2 2006.161.07:48:40.67#ibcon#about to read 3, iclass 15, count 2 2006.161.07:48:40.70#ibcon#read 3, iclass 15, count 2 2006.161.07:48:40.70#ibcon#about to read 4, iclass 15, count 2 2006.161.07:48:40.70#ibcon#read 4, iclass 15, count 2 2006.161.07:48:40.70#ibcon#about to read 5, iclass 15, count 2 2006.161.07:48:40.70#ibcon#read 5, iclass 15, count 2 2006.161.07:48:40.70#ibcon#about to read 6, iclass 15, count 2 2006.161.07:48:40.70#ibcon#read 6, iclass 15, count 2 2006.161.07:48:40.70#ibcon#end of sib2, iclass 15, count 2 2006.161.07:48:40.70#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:48:40.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:48:40.70#ibcon#[25=AT05-07\r\n] 2006.161.07:48:40.70#ibcon#*before write, iclass 15, count 2 2006.161.07:48:40.70#ibcon#enter sib2, iclass 15, count 2 2006.161.07:48:40.70#ibcon#flushed, iclass 15, count 2 2006.161.07:48:40.70#ibcon#about to write, iclass 15, count 2 2006.161.07:48:40.70#ibcon#wrote, iclass 15, count 2 2006.161.07:48:40.70#ibcon#about to read 3, iclass 15, count 2 2006.161.07:48:40.73#ibcon#read 3, iclass 15, count 2 2006.161.07:48:40.73#ibcon#about to read 4, iclass 15, count 2 2006.161.07:48:40.73#ibcon#read 4, iclass 15, count 2 2006.161.07:48:40.73#ibcon#about to read 5, iclass 15, count 2 2006.161.07:48:40.73#ibcon#read 5, iclass 15, count 2 2006.161.07:48:40.73#ibcon#about to read 6, iclass 15, count 2 2006.161.07:48:40.73#ibcon#read 6, iclass 15, count 2 2006.161.07:48:40.73#ibcon#end of sib2, iclass 15, count 2 2006.161.07:48:40.73#ibcon#*after write, iclass 15, count 2 2006.161.07:48:40.73#ibcon#*before return 0, iclass 15, count 2 2006.161.07:48:40.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:40.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:40.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:48:40.73#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:40.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:40.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:40.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:40.85#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:48:40.85#ibcon#first serial, iclass 15, count 0 2006.161.07:48:40.85#ibcon#enter sib2, iclass 15, count 0 2006.161.07:48:40.85#ibcon#flushed, iclass 15, count 0 2006.161.07:48:40.85#ibcon#about to write, iclass 15, count 0 2006.161.07:48:40.85#ibcon#wrote, iclass 15, count 0 2006.161.07:48:40.85#ibcon#about to read 3, iclass 15, count 0 2006.161.07:48:40.87#ibcon#read 3, iclass 15, count 0 2006.161.07:48:40.87#ibcon#about to read 4, iclass 15, count 0 2006.161.07:48:40.87#ibcon#read 4, iclass 15, count 0 2006.161.07:48:40.87#ibcon#about to read 5, iclass 15, count 0 2006.161.07:48:40.87#ibcon#read 5, iclass 15, count 0 2006.161.07:48:40.87#ibcon#about to read 6, iclass 15, count 0 2006.161.07:48:40.87#ibcon#read 6, iclass 15, count 0 2006.161.07:48:40.87#ibcon#end of sib2, iclass 15, count 0 2006.161.07:48:40.87#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:48:40.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:48:40.87#ibcon#[25=USB\r\n] 2006.161.07:48:40.87#ibcon#*before write, iclass 15, count 0 2006.161.07:48:40.87#ibcon#enter sib2, iclass 15, count 0 2006.161.07:48:40.87#ibcon#flushed, iclass 15, count 0 2006.161.07:48:40.87#ibcon#about to write, iclass 15, count 0 2006.161.07:48:40.87#ibcon#wrote, iclass 15, count 0 2006.161.07:48:40.87#ibcon#about to read 3, iclass 15, count 0 2006.161.07:48:40.90#ibcon#read 3, iclass 15, count 0 2006.161.07:48:40.90#ibcon#about to read 4, iclass 15, count 0 2006.161.07:48:40.90#ibcon#read 4, iclass 15, count 0 2006.161.07:48:40.90#ibcon#about to read 5, iclass 15, count 0 2006.161.07:48:40.90#ibcon#read 5, iclass 15, count 0 2006.161.07:48:40.90#ibcon#about to read 6, iclass 15, count 0 2006.161.07:48:40.90#ibcon#read 6, iclass 15, count 0 2006.161.07:48:40.90#ibcon#end of sib2, iclass 15, count 0 2006.161.07:48:40.90#ibcon#*after write, iclass 15, count 0 2006.161.07:48:40.90#ibcon#*before return 0, iclass 15, count 0 2006.161.07:48:40.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:40.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:40.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:48:40.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:48:40.90$vc4f8/valo=6,772.99 2006.161.07:48:40.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:48:40.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:48:40.90#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:40.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:40.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:40.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:40.90#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:48:40.90#ibcon#first serial, iclass 17, count 0 2006.161.07:48:40.90#ibcon#enter sib2, iclass 17, count 0 2006.161.07:48:40.90#ibcon#flushed, iclass 17, count 0 2006.161.07:48:40.90#ibcon#about to write, iclass 17, count 0 2006.161.07:48:40.90#ibcon#wrote, iclass 17, count 0 2006.161.07:48:40.90#ibcon#about to read 3, iclass 17, count 0 2006.161.07:48:40.92#ibcon#read 3, iclass 17, count 0 2006.161.07:48:40.92#ibcon#about to read 4, iclass 17, count 0 2006.161.07:48:40.92#ibcon#read 4, iclass 17, count 0 2006.161.07:48:40.92#ibcon#about to read 5, iclass 17, count 0 2006.161.07:48:40.92#ibcon#read 5, iclass 17, count 0 2006.161.07:48:40.92#ibcon#about to read 6, iclass 17, count 0 2006.161.07:48:40.92#ibcon#read 6, iclass 17, count 0 2006.161.07:48:40.92#ibcon#end of sib2, iclass 17, count 0 2006.161.07:48:40.92#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:48:40.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:48:40.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:48:40.92#ibcon#*before write, iclass 17, count 0 2006.161.07:48:40.92#ibcon#enter sib2, iclass 17, count 0 2006.161.07:48:40.92#ibcon#flushed, iclass 17, count 0 2006.161.07:48:40.92#ibcon#about to write, iclass 17, count 0 2006.161.07:48:40.92#ibcon#wrote, iclass 17, count 0 2006.161.07:48:40.92#ibcon#about to read 3, iclass 17, count 0 2006.161.07:48:40.96#ibcon#read 3, iclass 17, count 0 2006.161.07:48:40.96#ibcon#about to read 4, iclass 17, count 0 2006.161.07:48:40.96#ibcon#read 4, iclass 17, count 0 2006.161.07:48:40.96#ibcon#about to read 5, iclass 17, count 0 2006.161.07:48:40.96#ibcon#read 5, iclass 17, count 0 2006.161.07:48:40.96#ibcon#about to read 6, iclass 17, count 0 2006.161.07:48:40.96#ibcon#read 6, iclass 17, count 0 2006.161.07:48:40.96#ibcon#end of sib2, iclass 17, count 0 2006.161.07:48:40.96#ibcon#*after write, iclass 17, count 0 2006.161.07:48:40.96#ibcon#*before return 0, iclass 17, count 0 2006.161.07:48:40.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:40.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:40.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:48:40.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:48:40.96$vc4f8/va=6,6 2006.161.07:48:40.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.07:48:40.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.07:48:40.96#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:40.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:41.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:41.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:41.02#ibcon#enter wrdev, iclass 19, count 2 2006.161.07:48:41.02#ibcon#first serial, iclass 19, count 2 2006.161.07:48:41.02#ibcon#enter sib2, iclass 19, count 2 2006.161.07:48:41.02#ibcon#flushed, iclass 19, count 2 2006.161.07:48:41.02#ibcon#about to write, iclass 19, count 2 2006.161.07:48:41.02#ibcon#wrote, iclass 19, count 2 2006.161.07:48:41.02#ibcon#about to read 3, iclass 19, count 2 2006.161.07:48:41.04#ibcon#read 3, iclass 19, count 2 2006.161.07:48:41.04#ibcon#about to read 4, iclass 19, count 2 2006.161.07:48:41.04#ibcon#read 4, iclass 19, count 2 2006.161.07:48:41.04#ibcon#about to read 5, iclass 19, count 2 2006.161.07:48:41.04#ibcon#read 5, iclass 19, count 2 2006.161.07:48:41.04#ibcon#about to read 6, iclass 19, count 2 2006.161.07:48:41.04#ibcon#read 6, iclass 19, count 2 2006.161.07:48:41.04#ibcon#end of sib2, iclass 19, count 2 2006.161.07:48:41.04#ibcon#*mode == 0, iclass 19, count 2 2006.161.07:48:41.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.07:48:41.04#ibcon#[25=AT06-06\r\n] 2006.161.07:48:41.04#ibcon#*before write, iclass 19, count 2 2006.161.07:48:41.04#ibcon#enter sib2, iclass 19, count 2 2006.161.07:48:41.04#ibcon#flushed, iclass 19, count 2 2006.161.07:48:41.04#ibcon#about to write, iclass 19, count 2 2006.161.07:48:41.04#ibcon#wrote, iclass 19, count 2 2006.161.07:48:41.04#ibcon#about to read 3, iclass 19, count 2 2006.161.07:48:41.07#ibcon#read 3, iclass 19, count 2 2006.161.07:48:41.07#ibcon#about to read 4, iclass 19, count 2 2006.161.07:48:41.07#ibcon#read 4, iclass 19, count 2 2006.161.07:48:41.07#ibcon#about to read 5, iclass 19, count 2 2006.161.07:48:41.07#ibcon#read 5, iclass 19, count 2 2006.161.07:48:41.07#ibcon#about to read 6, iclass 19, count 2 2006.161.07:48:41.07#ibcon#read 6, iclass 19, count 2 2006.161.07:48:41.07#ibcon#end of sib2, iclass 19, count 2 2006.161.07:48:41.07#ibcon#*after write, iclass 19, count 2 2006.161.07:48:41.07#ibcon#*before return 0, iclass 19, count 2 2006.161.07:48:41.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:41.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:41.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.07:48:41.07#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:41.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:48:41.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:48:41.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:48:41.19#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:48:41.19#ibcon#first serial, iclass 19, count 0 2006.161.07:48:41.19#ibcon#enter sib2, iclass 19, count 0 2006.161.07:48:41.19#ibcon#flushed, iclass 19, count 0 2006.161.07:48:41.19#ibcon#about to write, iclass 19, count 0 2006.161.07:48:41.19#ibcon#wrote, iclass 19, count 0 2006.161.07:48:41.19#ibcon#about to read 3, iclass 19, count 0 2006.161.07:48:41.21#ibcon#read 3, iclass 19, count 0 2006.161.07:48:41.21#ibcon#about to read 4, iclass 19, count 0 2006.161.07:48:41.21#ibcon#read 4, iclass 19, count 0 2006.161.07:48:41.21#ibcon#about to read 5, iclass 19, count 0 2006.161.07:48:41.21#ibcon#read 5, iclass 19, count 0 2006.161.07:48:41.21#ibcon#about to read 6, iclass 19, count 0 2006.161.07:48:41.21#ibcon#read 6, iclass 19, count 0 2006.161.07:48:41.21#ibcon#end of sib2, iclass 19, count 0 2006.161.07:48:41.21#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:48:41.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:48:41.21#ibcon#[25=USB\r\n] 2006.161.07:48:41.21#ibcon#*before write, iclass 19, count 0 2006.161.07:48:41.21#ibcon#enter sib2, iclass 19, count 0 2006.161.07:48:41.21#ibcon#flushed, iclass 19, count 0 2006.161.07:48:41.21#ibcon#about to write, iclass 19, count 0 2006.161.07:48:41.21#ibcon#wrote, iclass 19, count 0 2006.161.07:48:41.21#ibcon#about to read 3, iclass 19, count 0 2006.161.07:48:41.24#ibcon#read 3, iclass 19, count 0 2006.161.07:48:41.24#ibcon#about to read 4, iclass 19, count 0 2006.161.07:48:41.24#ibcon#read 4, iclass 19, count 0 2006.161.07:48:41.24#ibcon#about to read 5, iclass 19, count 0 2006.161.07:48:41.24#ibcon#read 5, iclass 19, count 0 2006.161.07:48:41.24#ibcon#about to read 6, iclass 19, count 0 2006.161.07:48:41.24#ibcon#read 6, iclass 19, count 0 2006.161.07:48:41.24#ibcon#end of sib2, iclass 19, count 0 2006.161.07:48:41.24#ibcon#*after write, iclass 19, count 0 2006.161.07:48:41.24#ibcon#*before return 0, iclass 19, count 0 2006.161.07:48:41.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:48:41.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.07:48:41.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:48:41.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:48:41.24$vc4f8/valo=7,832.99 2006.161.07:48:41.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.07:48:41.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.07:48:41.24#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:41.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:48:41.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:48:41.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:48:41.24#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:48:41.24#ibcon#first serial, iclass 21, count 0 2006.161.07:48:41.24#ibcon#enter sib2, iclass 21, count 0 2006.161.07:48:41.24#ibcon#flushed, iclass 21, count 0 2006.161.07:48:41.24#ibcon#about to write, iclass 21, count 0 2006.161.07:48:41.24#ibcon#wrote, iclass 21, count 0 2006.161.07:48:41.24#ibcon#about to read 3, iclass 21, count 0 2006.161.07:48:41.26#ibcon#read 3, iclass 21, count 0 2006.161.07:48:41.26#ibcon#about to read 4, iclass 21, count 0 2006.161.07:48:41.26#ibcon#read 4, iclass 21, count 0 2006.161.07:48:41.26#ibcon#about to read 5, iclass 21, count 0 2006.161.07:48:41.26#ibcon#read 5, iclass 21, count 0 2006.161.07:48:41.26#ibcon#about to read 6, iclass 21, count 0 2006.161.07:48:41.26#ibcon#read 6, iclass 21, count 0 2006.161.07:48:41.26#ibcon#end of sib2, iclass 21, count 0 2006.161.07:48:41.26#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:48:41.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:48:41.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:48:41.26#ibcon#*before write, iclass 21, count 0 2006.161.07:48:41.26#ibcon#enter sib2, iclass 21, count 0 2006.161.07:48:41.26#ibcon#flushed, iclass 21, count 0 2006.161.07:48:41.26#ibcon#about to write, iclass 21, count 0 2006.161.07:48:41.26#ibcon#wrote, iclass 21, count 0 2006.161.07:48:41.26#ibcon#about to read 3, iclass 21, count 0 2006.161.07:48:41.30#ibcon#read 3, iclass 21, count 0 2006.161.07:48:41.30#ibcon#about to read 4, iclass 21, count 0 2006.161.07:48:41.30#ibcon#read 4, iclass 21, count 0 2006.161.07:48:41.30#ibcon#about to read 5, iclass 21, count 0 2006.161.07:48:41.30#ibcon#read 5, iclass 21, count 0 2006.161.07:48:41.30#ibcon#about to read 6, iclass 21, count 0 2006.161.07:48:41.30#ibcon#read 6, iclass 21, count 0 2006.161.07:48:41.30#ibcon#end of sib2, iclass 21, count 0 2006.161.07:48:41.30#ibcon#*after write, iclass 21, count 0 2006.161.07:48:41.30#ibcon#*before return 0, iclass 21, count 0 2006.161.07:48:41.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:48:41.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.07:48:41.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:48:41.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:48:41.30$vc4f8/va=7,6 2006.161.07:48:41.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.07:48:41.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.07:48:41.30#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:41.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:48:41.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:48:41.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:48:41.36#ibcon#enter wrdev, iclass 23, count 2 2006.161.07:48:41.36#ibcon#first serial, iclass 23, count 2 2006.161.07:48:41.36#ibcon#enter sib2, iclass 23, count 2 2006.161.07:48:41.36#ibcon#flushed, iclass 23, count 2 2006.161.07:48:41.36#ibcon#about to write, iclass 23, count 2 2006.161.07:48:41.36#ibcon#wrote, iclass 23, count 2 2006.161.07:48:41.36#ibcon#about to read 3, iclass 23, count 2 2006.161.07:48:41.38#ibcon#read 3, iclass 23, count 2 2006.161.07:48:41.38#ibcon#about to read 4, iclass 23, count 2 2006.161.07:48:41.38#ibcon#read 4, iclass 23, count 2 2006.161.07:48:41.38#ibcon#about to read 5, iclass 23, count 2 2006.161.07:48:41.38#ibcon#read 5, iclass 23, count 2 2006.161.07:48:41.38#ibcon#about to read 6, iclass 23, count 2 2006.161.07:48:41.38#ibcon#read 6, iclass 23, count 2 2006.161.07:48:41.38#ibcon#end of sib2, iclass 23, count 2 2006.161.07:48:41.38#ibcon#*mode == 0, iclass 23, count 2 2006.161.07:48:41.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.07:48:41.38#ibcon#[25=AT07-06\r\n] 2006.161.07:48:41.38#ibcon#*before write, iclass 23, count 2 2006.161.07:48:41.38#ibcon#enter sib2, iclass 23, count 2 2006.161.07:48:41.38#ibcon#flushed, iclass 23, count 2 2006.161.07:48:41.38#ibcon#about to write, iclass 23, count 2 2006.161.07:48:41.38#ibcon#wrote, iclass 23, count 2 2006.161.07:48:41.38#ibcon#about to read 3, iclass 23, count 2 2006.161.07:48:41.41#ibcon#read 3, iclass 23, count 2 2006.161.07:48:41.41#ibcon#about to read 4, iclass 23, count 2 2006.161.07:48:41.41#ibcon#read 4, iclass 23, count 2 2006.161.07:48:41.41#ibcon#about to read 5, iclass 23, count 2 2006.161.07:48:41.41#ibcon#read 5, iclass 23, count 2 2006.161.07:48:41.41#ibcon#about to read 6, iclass 23, count 2 2006.161.07:48:41.41#ibcon#read 6, iclass 23, count 2 2006.161.07:48:41.41#ibcon#end of sib2, iclass 23, count 2 2006.161.07:48:41.41#ibcon#*after write, iclass 23, count 2 2006.161.07:48:41.41#ibcon#*before return 0, iclass 23, count 2 2006.161.07:48:41.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:48:41.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.07:48:41.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.07:48:41.41#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:41.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:48:41.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:48:41.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:48:41.53#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:48:41.53#ibcon#first serial, iclass 23, count 0 2006.161.07:48:41.53#ibcon#enter sib2, iclass 23, count 0 2006.161.07:48:41.53#ibcon#flushed, iclass 23, count 0 2006.161.07:48:41.53#ibcon#about to write, iclass 23, count 0 2006.161.07:48:41.53#ibcon#wrote, iclass 23, count 0 2006.161.07:48:41.53#ibcon#about to read 3, iclass 23, count 0 2006.161.07:48:41.55#ibcon#read 3, iclass 23, count 0 2006.161.07:48:41.55#ibcon#about to read 4, iclass 23, count 0 2006.161.07:48:41.55#ibcon#read 4, iclass 23, count 0 2006.161.07:48:41.55#ibcon#about to read 5, iclass 23, count 0 2006.161.07:48:41.55#ibcon#read 5, iclass 23, count 0 2006.161.07:48:41.55#ibcon#about to read 6, iclass 23, count 0 2006.161.07:48:41.55#ibcon#read 6, iclass 23, count 0 2006.161.07:48:41.55#ibcon#end of sib2, iclass 23, count 0 2006.161.07:48:41.55#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:48:41.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:48:41.55#ibcon#[25=USB\r\n] 2006.161.07:48:41.55#ibcon#*before write, iclass 23, count 0 2006.161.07:48:41.55#ibcon#enter sib2, iclass 23, count 0 2006.161.07:48:41.55#ibcon#flushed, iclass 23, count 0 2006.161.07:48:41.55#ibcon#about to write, iclass 23, count 0 2006.161.07:48:41.55#ibcon#wrote, iclass 23, count 0 2006.161.07:48:41.55#ibcon#about to read 3, iclass 23, count 0 2006.161.07:48:41.58#ibcon#read 3, iclass 23, count 0 2006.161.07:48:41.58#ibcon#about to read 4, iclass 23, count 0 2006.161.07:48:41.58#ibcon#read 4, iclass 23, count 0 2006.161.07:48:41.58#ibcon#about to read 5, iclass 23, count 0 2006.161.07:48:41.58#ibcon#read 5, iclass 23, count 0 2006.161.07:48:41.58#ibcon#about to read 6, iclass 23, count 0 2006.161.07:48:41.58#ibcon#read 6, iclass 23, count 0 2006.161.07:48:41.58#ibcon#end of sib2, iclass 23, count 0 2006.161.07:48:41.58#ibcon#*after write, iclass 23, count 0 2006.161.07:48:41.58#ibcon#*before return 0, iclass 23, count 0 2006.161.07:48:41.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:48:41.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.07:48:41.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:48:41.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:48:41.58$vc4f8/valo=8,852.99 2006.161.07:48:41.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.07:48:41.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.07:48:41.58#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:41.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:48:41.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:48:41.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:48:41.58#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:48:41.58#ibcon#first serial, iclass 25, count 0 2006.161.07:48:41.58#ibcon#enter sib2, iclass 25, count 0 2006.161.07:48:41.58#ibcon#flushed, iclass 25, count 0 2006.161.07:48:41.58#ibcon#about to write, iclass 25, count 0 2006.161.07:48:41.58#ibcon#wrote, iclass 25, count 0 2006.161.07:48:41.58#ibcon#about to read 3, iclass 25, count 0 2006.161.07:48:41.60#ibcon#read 3, iclass 25, count 0 2006.161.07:48:41.60#ibcon#about to read 4, iclass 25, count 0 2006.161.07:48:41.60#ibcon#read 4, iclass 25, count 0 2006.161.07:48:41.60#ibcon#about to read 5, iclass 25, count 0 2006.161.07:48:41.60#ibcon#read 5, iclass 25, count 0 2006.161.07:48:41.60#ibcon#about to read 6, iclass 25, count 0 2006.161.07:48:41.60#ibcon#read 6, iclass 25, count 0 2006.161.07:48:41.60#ibcon#end of sib2, iclass 25, count 0 2006.161.07:48:41.60#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:48:41.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:48:41.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:48:41.60#ibcon#*before write, iclass 25, count 0 2006.161.07:48:41.60#ibcon#enter sib2, iclass 25, count 0 2006.161.07:48:41.60#ibcon#flushed, iclass 25, count 0 2006.161.07:48:41.60#ibcon#about to write, iclass 25, count 0 2006.161.07:48:41.60#ibcon#wrote, iclass 25, count 0 2006.161.07:48:41.60#ibcon#about to read 3, iclass 25, count 0 2006.161.07:48:41.64#ibcon#read 3, iclass 25, count 0 2006.161.07:48:41.64#ibcon#about to read 4, iclass 25, count 0 2006.161.07:48:41.64#ibcon#read 4, iclass 25, count 0 2006.161.07:48:41.64#ibcon#about to read 5, iclass 25, count 0 2006.161.07:48:41.64#ibcon#read 5, iclass 25, count 0 2006.161.07:48:41.64#ibcon#about to read 6, iclass 25, count 0 2006.161.07:48:41.64#ibcon#read 6, iclass 25, count 0 2006.161.07:48:41.64#ibcon#end of sib2, iclass 25, count 0 2006.161.07:48:41.64#ibcon#*after write, iclass 25, count 0 2006.161.07:48:41.64#ibcon#*before return 0, iclass 25, count 0 2006.161.07:48:41.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:48:41.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.07:48:41.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:48:41.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:48:41.64$vc4f8/va=8,7 2006.161.07:48:41.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.07:48:41.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.07:48:41.64#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:41.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:48:41.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:48:41.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:48:41.70#ibcon#enter wrdev, iclass 27, count 2 2006.161.07:48:41.70#ibcon#first serial, iclass 27, count 2 2006.161.07:48:41.70#ibcon#enter sib2, iclass 27, count 2 2006.161.07:48:41.70#ibcon#flushed, iclass 27, count 2 2006.161.07:48:41.70#ibcon#about to write, iclass 27, count 2 2006.161.07:48:41.70#ibcon#wrote, iclass 27, count 2 2006.161.07:48:41.70#ibcon#about to read 3, iclass 27, count 2 2006.161.07:48:41.72#ibcon#read 3, iclass 27, count 2 2006.161.07:48:41.72#ibcon#about to read 4, iclass 27, count 2 2006.161.07:48:41.72#ibcon#read 4, iclass 27, count 2 2006.161.07:48:41.72#ibcon#about to read 5, iclass 27, count 2 2006.161.07:48:41.72#ibcon#read 5, iclass 27, count 2 2006.161.07:48:41.72#ibcon#about to read 6, iclass 27, count 2 2006.161.07:48:41.72#ibcon#read 6, iclass 27, count 2 2006.161.07:48:41.72#ibcon#end of sib2, iclass 27, count 2 2006.161.07:48:41.72#ibcon#*mode == 0, iclass 27, count 2 2006.161.07:48:41.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.07:48:41.72#ibcon#[25=AT08-07\r\n] 2006.161.07:48:41.72#ibcon#*before write, iclass 27, count 2 2006.161.07:48:41.72#ibcon#enter sib2, iclass 27, count 2 2006.161.07:48:41.72#ibcon#flushed, iclass 27, count 2 2006.161.07:48:41.72#ibcon#about to write, iclass 27, count 2 2006.161.07:48:41.72#ibcon#wrote, iclass 27, count 2 2006.161.07:48:41.72#ibcon#about to read 3, iclass 27, count 2 2006.161.07:48:41.75#ibcon#read 3, iclass 27, count 2 2006.161.07:48:41.75#ibcon#about to read 4, iclass 27, count 2 2006.161.07:48:41.75#ibcon#read 4, iclass 27, count 2 2006.161.07:48:41.75#ibcon#about to read 5, iclass 27, count 2 2006.161.07:48:41.75#ibcon#read 5, iclass 27, count 2 2006.161.07:48:41.75#ibcon#about to read 6, iclass 27, count 2 2006.161.07:48:41.75#ibcon#read 6, iclass 27, count 2 2006.161.07:48:41.75#ibcon#end of sib2, iclass 27, count 2 2006.161.07:48:41.75#ibcon#*after write, iclass 27, count 2 2006.161.07:48:41.75#ibcon#*before return 0, iclass 27, count 2 2006.161.07:48:41.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:48:41.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.07:48:41.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.07:48:41.75#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:41.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:48:41.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:48:41.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:48:41.87#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:48:41.87#ibcon#first serial, iclass 27, count 0 2006.161.07:48:41.87#ibcon#enter sib2, iclass 27, count 0 2006.161.07:48:41.87#ibcon#flushed, iclass 27, count 0 2006.161.07:48:41.87#ibcon#about to write, iclass 27, count 0 2006.161.07:48:41.87#ibcon#wrote, iclass 27, count 0 2006.161.07:48:41.87#ibcon#about to read 3, iclass 27, count 0 2006.161.07:48:41.89#ibcon#read 3, iclass 27, count 0 2006.161.07:48:41.89#ibcon#about to read 4, iclass 27, count 0 2006.161.07:48:41.89#ibcon#read 4, iclass 27, count 0 2006.161.07:48:41.89#ibcon#about to read 5, iclass 27, count 0 2006.161.07:48:41.89#ibcon#read 5, iclass 27, count 0 2006.161.07:48:41.89#ibcon#about to read 6, iclass 27, count 0 2006.161.07:48:41.89#ibcon#read 6, iclass 27, count 0 2006.161.07:48:41.89#ibcon#end of sib2, iclass 27, count 0 2006.161.07:48:41.89#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:48:41.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:48:41.89#ibcon#[25=USB\r\n] 2006.161.07:48:41.89#ibcon#*before write, iclass 27, count 0 2006.161.07:48:41.89#ibcon#enter sib2, iclass 27, count 0 2006.161.07:48:41.89#ibcon#flushed, iclass 27, count 0 2006.161.07:48:41.89#ibcon#about to write, iclass 27, count 0 2006.161.07:48:41.89#ibcon#wrote, iclass 27, count 0 2006.161.07:48:41.89#ibcon#about to read 3, iclass 27, count 0 2006.161.07:48:41.92#ibcon#read 3, iclass 27, count 0 2006.161.07:48:41.92#ibcon#about to read 4, iclass 27, count 0 2006.161.07:48:41.92#ibcon#read 4, iclass 27, count 0 2006.161.07:48:41.92#ibcon#about to read 5, iclass 27, count 0 2006.161.07:48:41.92#ibcon#read 5, iclass 27, count 0 2006.161.07:48:41.92#ibcon#about to read 6, iclass 27, count 0 2006.161.07:48:41.92#ibcon#read 6, iclass 27, count 0 2006.161.07:48:41.92#ibcon#end of sib2, iclass 27, count 0 2006.161.07:48:41.92#ibcon#*after write, iclass 27, count 0 2006.161.07:48:41.92#ibcon#*before return 0, iclass 27, count 0 2006.161.07:48:41.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:48:41.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.07:48:41.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:48:41.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:48:41.92$vc4f8/vblo=1,632.99 2006.161.07:48:41.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.07:48:41.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.07:48:41.92#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:41.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:48:41.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:48:41.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:48:41.92#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:48:41.92#ibcon#first serial, iclass 29, count 0 2006.161.07:48:41.92#ibcon#enter sib2, iclass 29, count 0 2006.161.07:48:41.92#ibcon#flushed, iclass 29, count 0 2006.161.07:48:41.92#ibcon#about to write, iclass 29, count 0 2006.161.07:48:41.92#ibcon#wrote, iclass 29, count 0 2006.161.07:48:41.92#ibcon#about to read 3, iclass 29, count 0 2006.161.07:48:41.94#ibcon#read 3, iclass 29, count 0 2006.161.07:48:41.94#ibcon#about to read 4, iclass 29, count 0 2006.161.07:48:41.94#ibcon#read 4, iclass 29, count 0 2006.161.07:48:41.94#ibcon#about to read 5, iclass 29, count 0 2006.161.07:48:41.94#ibcon#read 5, iclass 29, count 0 2006.161.07:48:41.94#ibcon#about to read 6, iclass 29, count 0 2006.161.07:48:41.94#ibcon#read 6, iclass 29, count 0 2006.161.07:48:41.94#ibcon#end of sib2, iclass 29, count 0 2006.161.07:48:41.94#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:48:41.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:48:41.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:48:41.94#ibcon#*before write, iclass 29, count 0 2006.161.07:48:41.94#ibcon#enter sib2, iclass 29, count 0 2006.161.07:48:41.94#ibcon#flushed, iclass 29, count 0 2006.161.07:48:41.94#ibcon#about to write, iclass 29, count 0 2006.161.07:48:41.94#ibcon#wrote, iclass 29, count 0 2006.161.07:48:41.94#ibcon#about to read 3, iclass 29, count 0 2006.161.07:48:41.98#ibcon#read 3, iclass 29, count 0 2006.161.07:48:41.98#ibcon#about to read 4, iclass 29, count 0 2006.161.07:48:41.98#ibcon#read 4, iclass 29, count 0 2006.161.07:48:41.98#ibcon#about to read 5, iclass 29, count 0 2006.161.07:48:41.98#ibcon#read 5, iclass 29, count 0 2006.161.07:48:41.98#ibcon#about to read 6, iclass 29, count 0 2006.161.07:48:41.98#ibcon#read 6, iclass 29, count 0 2006.161.07:48:41.98#ibcon#end of sib2, iclass 29, count 0 2006.161.07:48:41.98#ibcon#*after write, iclass 29, count 0 2006.161.07:48:41.98#ibcon#*before return 0, iclass 29, count 0 2006.161.07:48:41.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:48:41.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.07:48:41.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:48:41.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:48:41.98$vc4f8/vb=1,4 2006.161.07:48:41.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.07:48:41.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.07:48:41.98#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:41.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:48:41.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:48:41.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:48:41.98#ibcon#enter wrdev, iclass 31, count 2 2006.161.07:48:41.98#ibcon#first serial, iclass 31, count 2 2006.161.07:48:41.98#ibcon#enter sib2, iclass 31, count 2 2006.161.07:48:41.98#ibcon#flushed, iclass 31, count 2 2006.161.07:48:41.98#ibcon#about to write, iclass 31, count 2 2006.161.07:48:41.98#ibcon#wrote, iclass 31, count 2 2006.161.07:48:41.98#ibcon#about to read 3, iclass 31, count 2 2006.161.07:48:42.00#ibcon#read 3, iclass 31, count 2 2006.161.07:48:42.00#ibcon#about to read 4, iclass 31, count 2 2006.161.07:48:42.00#ibcon#read 4, iclass 31, count 2 2006.161.07:48:42.00#ibcon#about to read 5, iclass 31, count 2 2006.161.07:48:42.00#ibcon#read 5, iclass 31, count 2 2006.161.07:48:42.00#ibcon#about to read 6, iclass 31, count 2 2006.161.07:48:42.00#ibcon#read 6, iclass 31, count 2 2006.161.07:48:42.00#ibcon#end of sib2, iclass 31, count 2 2006.161.07:48:42.00#ibcon#*mode == 0, iclass 31, count 2 2006.161.07:48:42.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.07:48:42.00#ibcon#[27=AT01-04\r\n] 2006.161.07:48:42.00#ibcon#*before write, iclass 31, count 2 2006.161.07:48:42.00#ibcon#enter sib2, iclass 31, count 2 2006.161.07:48:42.00#ibcon#flushed, iclass 31, count 2 2006.161.07:48:42.00#ibcon#about to write, iclass 31, count 2 2006.161.07:48:42.00#ibcon#wrote, iclass 31, count 2 2006.161.07:48:42.00#ibcon#about to read 3, iclass 31, count 2 2006.161.07:48:42.03#ibcon#read 3, iclass 31, count 2 2006.161.07:48:42.03#ibcon#about to read 4, iclass 31, count 2 2006.161.07:48:42.03#ibcon#read 4, iclass 31, count 2 2006.161.07:48:42.03#ibcon#about to read 5, iclass 31, count 2 2006.161.07:48:42.03#ibcon#read 5, iclass 31, count 2 2006.161.07:48:42.03#ibcon#about to read 6, iclass 31, count 2 2006.161.07:48:42.03#ibcon#read 6, iclass 31, count 2 2006.161.07:48:42.03#ibcon#end of sib2, iclass 31, count 2 2006.161.07:48:42.03#ibcon#*after write, iclass 31, count 2 2006.161.07:48:42.03#ibcon#*before return 0, iclass 31, count 2 2006.161.07:48:42.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:48:42.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.07:48:42.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.07:48:42.03#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:42.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:48:42.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:48:42.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:48:42.15#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:48:42.15#ibcon#first serial, iclass 31, count 0 2006.161.07:48:42.15#ibcon#enter sib2, iclass 31, count 0 2006.161.07:48:42.15#ibcon#flushed, iclass 31, count 0 2006.161.07:48:42.15#ibcon#about to write, iclass 31, count 0 2006.161.07:48:42.15#ibcon#wrote, iclass 31, count 0 2006.161.07:48:42.15#ibcon#about to read 3, iclass 31, count 0 2006.161.07:48:42.17#ibcon#read 3, iclass 31, count 0 2006.161.07:48:42.17#ibcon#about to read 4, iclass 31, count 0 2006.161.07:48:42.17#ibcon#read 4, iclass 31, count 0 2006.161.07:48:42.17#ibcon#about to read 5, iclass 31, count 0 2006.161.07:48:42.17#ibcon#read 5, iclass 31, count 0 2006.161.07:48:42.17#ibcon#about to read 6, iclass 31, count 0 2006.161.07:48:42.17#ibcon#read 6, iclass 31, count 0 2006.161.07:48:42.17#ibcon#end of sib2, iclass 31, count 0 2006.161.07:48:42.17#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:48:42.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:48:42.17#ibcon#[27=USB\r\n] 2006.161.07:48:42.17#ibcon#*before write, iclass 31, count 0 2006.161.07:48:42.17#ibcon#enter sib2, iclass 31, count 0 2006.161.07:48:42.17#ibcon#flushed, iclass 31, count 0 2006.161.07:48:42.17#ibcon#about to write, iclass 31, count 0 2006.161.07:48:42.17#ibcon#wrote, iclass 31, count 0 2006.161.07:48:42.17#ibcon#about to read 3, iclass 31, count 0 2006.161.07:48:42.20#ibcon#read 3, iclass 31, count 0 2006.161.07:48:42.20#ibcon#about to read 4, iclass 31, count 0 2006.161.07:48:42.20#ibcon#read 4, iclass 31, count 0 2006.161.07:48:42.20#ibcon#about to read 5, iclass 31, count 0 2006.161.07:48:42.20#ibcon#read 5, iclass 31, count 0 2006.161.07:48:42.20#ibcon#about to read 6, iclass 31, count 0 2006.161.07:48:42.20#ibcon#read 6, iclass 31, count 0 2006.161.07:48:42.20#ibcon#end of sib2, iclass 31, count 0 2006.161.07:48:42.20#ibcon#*after write, iclass 31, count 0 2006.161.07:48:42.20#ibcon#*before return 0, iclass 31, count 0 2006.161.07:48:42.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:48:42.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.07:48:42.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:48:42.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:48:42.20$vc4f8/vblo=2,640.99 2006.161.07:48:42.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:48:42.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:48:42.20#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:42.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:42.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:42.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:42.20#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:48:42.20#ibcon#first serial, iclass 33, count 0 2006.161.07:48:42.20#ibcon#enter sib2, iclass 33, count 0 2006.161.07:48:42.20#ibcon#flushed, iclass 33, count 0 2006.161.07:48:42.20#ibcon#about to write, iclass 33, count 0 2006.161.07:48:42.20#ibcon#wrote, iclass 33, count 0 2006.161.07:48:42.20#ibcon#about to read 3, iclass 33, count 0 2006.161.07:48:42.22#ibcon#read 3, iclass 33, count 0 2006.161.07:48:42.22#ibcon#about to read 4, iclass 33, count 0 2006.161.07:48:42.22#ibcon#read 4, iclass 33, count 0 2006.161.07:48:42.22#ibcon#about to read 5, iclass 33, count 0 2006.161.07:48:42.22#ibcon#read 5, iclass 33, count 0 2006.161.07:48:42.22#ibcon#about to read 6, iclass 33, count 0 2006.161.07:48:42.22#ibcon#read 6, iclass 33, count 0 2006.161.07:48:42.22#ibcon#end of sib2, iclass 33, count 0 2006.161.07:48:42.22#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:48:42.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:48:42.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:48:42.22#ibcon#*before write, iclass 33, count 0 2006.161.07:48:42.22#ibcon#enter sib2, iclass 33, count 0 2006.161.07:48:42.22#ibcon#flushed, iclass 33, count 0 2006.161.07:48:42.22#ibcon#about to write, iclass 33, count 0 2006.161.07:48:42.22#ibcon#wrote, iclass 33, count 0 2006.161.07:48:42.22#ibcon#about to read 3, iclass 33, count 0 2006.161.07:48:42.26#ibcon#read 3, iclass 33, count 0 2006.161.07:48:42.26#ibcon#about to read 4, iclass 33, count 0 2006.161.07:48:42.26#ibcon#read 4, iclass 33, count 0 2006.161.07:48:42.26#ibcon#about to read 5, iclass 33, count 0 2006.161.07:48:42.26#ibcon#read 5, iclass 33, count 0 2006.161.07:48:42.26#ibcon#about to read 6, iclass 33, count 0 2006.161.07:48:42.26#ibcon#read 6, iclass 33, count 0 2006.161.07:48:42.26#ibcon#end of sib2, iclass 33, count 0 2006.161.07:48:42.26#ibcon#*after write, iclass 33, count 0 2006.161.07:48:42.26#ibcon#*before return 0, iclass 33, count 0 2006.161.07:48:42.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:42.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:48:42.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:48:42.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:48:42.26$vc4f8/vb=2,4 2006.161.07:48:42.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.07:48:42.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.07:48:42.26#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:42.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:42.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:42.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:42.32#ibcon#enter wrdev, iclass 35, count 2 2006.161.07:48:42.32#ibcon#first serial, iclass 35, count 2 2006.161.07:48:42.32#ibcon#enter sib2, iclass 35, count 2 2006.161.07:48:42.32#ibcon#flushed, iclass 35, count 2 2006.161.07:48:42.32#ibcon#about to write, iclass 35, count 2 2006.161.07:48:42.32#ibcon#wrote, iclass 35, count 2 2006.161.07:48:42.32#ibcon#about to read 3, iclass 35, count 2 2006.161.07:48:42.34#ibcon#read 3, iclass 35, count 2 2006.161.07:48:42.34#ibcon#about to read 4, iclass 35, count 2 2006.161.07:48:42.34#ibcon#read 4, iclass 35, count 2 2006.161.07:48:42.34#ibcon#about to read 5, iclass 35, count 2 2006.161.07:48:42.34#ibcon#read 5, iclass 35, count 2 2006.161.07:48:42.34#ibcon#about to read 6, iclass 35, count 2 2006.161.07:48:42.34#ibcon#read 6, iclass 35, count 2 2006.161.07:48:42.34#ibcon#end of sib2, iclass 35, count 2 2006.161.07:48:42.34#ibcon#*mode == 0, iclass 35, count 2 2006.161.07:48:42.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.07:48:42.34#ibcon#[27=AT02-04\r\n] 2006.161.07:48:42.34#ibcon#*before write, iclass 35, count 2 2006.161.07:48:42.34#ibcon#enter sib2, iclass 35, count 2 2006.161.07:48:42.34#ibcon#flushed, iclass 35, count 2 2006.161.07:48:42.34#ibcon#about to write, iclass 35, count 2 2006.161.07:48:42.34#ibcon#wrote, iclass 35, count 2 2006.161.07:48:42.34#ibcon#about to read 3, iclass 35, count 2 2006.161.07:48:42.37#ibcon#read 3, iclass 35, count 2 2006.161.07:48:42.37#ibcon#about to read 4, iclass 35, count 2 2006.161.07:48:42.37#ibcon#read 4, iclass 35, count 2 2006.161.07:48:42.37#ibcon#about to read 5, iclass 35, count 2 2006.161.07:48:42.37#ibcon#read 5, iclass 35, count 2 2006.161.07:48:42.37#ibcon#about to read 6, iclass 35, count 2 2006.161.07:48:42.37#ibcon#read 6, iclass 35, count 2 2006.161.07:48:42.37#ibcon#end of sib2, iclass 35, count 2 2006.161.07:48:42.37#ibcon#*after write, iclass 35, count 2 2006.161.07:48:42.37#ibcon#*before return 0, iclass 35, count 2 2006.161.07:48:42.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:42.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.07:48:42.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.07:48:42.37#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:42.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:42.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:42.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:42.49#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:48:42.49#ibcon#first serial, iclass 35, count 0 2006.161.07:48:42.49#ibcon#enter sib2, iclass 35, count 0 2006.161.07:48:42.49#ibcon#flushed, iclass 35, count 0 2006.161.07:48:42.49#ibcon#about to write, iclass 35, count 0 2006.161.07:48:42.49#ibcon#wrote, iclass 35, count 0 2006.161.07:48:42.49#ibcon#about to read 3, iclass 35, count 0 2006.161.07:48:42.51#ibcon#read 3, iclass 35, count 0 2006.161.07:48:42.51#ibcon#about to read 4, iclass 35, count 0 2006.161.07:48:42.51#ibcon#read 4, iclass 35, count 0 2006.161.07:48:42.51#ibcon#about to read 5, iclass 35, count 0 2006.161.07:48:42.51#ibcon#read 5, iclass 35, count 0 2006.161.07:48:42.51#ibcon#about to read 6, iclass 35, count 0 2006.161.07:48:42.51#ibcon#read 6, iclass 35, count 0 2006.161.07:48:42.51#ibcon#end of sib2, iclass 35, count 0 2006.161.07:48:42.51#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:48:42.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:48:42.51#ibcon#[27=USB\r\n] 2006.161.07:48:42.51#ibcon#*before write, iclass 35, count 0 2006.161.07:48:42.51#ibcon#enter sib2, iclass 35, count 0 2006.161.07:48:42.51#ibcon#flushed, iclass 35, count 0 2006.161.07:48:42.51#ibcon#about to write, iclass 35, count 0 2006.161.07:48:42.51#ibcon#wrote, iclass 35, count 0 2006.161.07:48:42.51#ibcon#about to read 3, iclass 35, count 0 2006.161.07:48:42.54#ibcon#read 3, iclass 35, count 0 2006.161.07:48:42.54#ibcon#about to read 4, iclass 35, count 0 2006.161.07:48:42.54#ibcon#read 4, iclass 35, count 0 2006.161.07:48:42.54#ibcon#about to read 5, iclass 35, count 0 2006.161.07:48:42.54#ibcon#read 5, iclass 35, count 0 2006.161.07:48:42.54#ibcon#about to read 6, iclass 35, count 0 2006.161.07:48:42.54#ibcon#read 6, iclass 35, count 0 2006.161.07:48:42.54#ibcon#end of sib2, iclass 35, count 0 2006.161.07:48:42.54#ibcon#*after write, iclass 35, count 0 2006.161.07:48:42.54#ibcon#*before return 0, iclass 35, count 0 2006.161.07:48:42.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:42.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.07:48:42.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:48:42.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:48:42.54$vc4f8/vblo=3,656.99 2006.161.07:48:42.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.07:48:42.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.07:48:42.54#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:42.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:42.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:42.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:42.54#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:48:42.54#ibcon#first serial, iclass 37, count 0 2006.161.07:48:42.54#ibcon#enter sib2, iclass 37, count 0 2006.161.07:48:42.54#ibcon#flushed, iclass 37, count 0 2006.161.07:48:42.54#ibcon#about to write, iclass 37, count 0 2006.161.07:48:42.54#ibcon#wrote, iclass 37, count 0 2006.161.07:48:42.54#ibcon#about to read 3, iclass 37, count 0 2006.161.07:48:42.56#ibcon#read 3, iclass 37, count 0 2006.161.07:48:42.56#ibcon#about to read 4, iclass 37, count 0 2006.161.07:48:42.56#ibcon#read 4, iclass 37, count 0 2006.161.07:48:42.56#ibcon#about to read 5, iclass 37, count 0 2006.161.07:48:42.56#ibcon#read 5, iclass 37, count 0 2006.161.07:48:42.56#ibcon#about to read 6, iclass 37, count 0 2006.161.07:48:42.56#ibcon#read 6, iclass 37, count 0 2006.161.07:48:42.56#ibcon#end of sib2, iclass 37, count 0 2006.161.07:48:42.56#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:48:42.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:48:42.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:48:42.56#ibcon#*before write, iclass 37, count 0 2006.161.07:48:42.56#ibcon#enter sib2, iclass 37, count 0 2006.161.07:48:42.56#ibcon#flushed, iclass 37, count 0 2006.161.07:48:42.56#ibcon#about to write, iclass 37, count 0 2006.161.07:48:42.56#ibcon#wrote, iclass 37, count 0 2006.161.07:48:42.56#ibcon#about to read 3, iclass 37, count 0 2006.161.07:48:42.60#ibcon#read 3, iclass 37, count 0 2006.161.07:48:42.60#ibcon#about to read 4, iclass 37, count 0 2006.161.07:48:42.60#ibcon#read 4, iclass 37, count 0 2006.161.07:48:42.60#ibcon#about to read 5, iclass 37, count 0 2006.161.07:48:42.60#ibcon#read 5, iclass 37, count 0 2006.161.07:48:42.60#ibcon#about to read 6, iclass 37, count 0 2006.161.07:48:42.60#ibcon#read 6, iclass 37, count 0 2006.161.07:48:42.60#ibcon#end of sib2, iclass 37, count 0 2006.161.07:48:42.60#ibcon#*after write, iclass 37, count 0 2006.161.07:48:42.60#ibcon#*before return 0, iclass 37, count 0 2006.161.07:48:42.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:42.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.07:48:42.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:48:42.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:48:42.60$vc4f8/vb=3,4 2006.161.07:48:42.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.07:48:42.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.07:48:42.60#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:42.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:42.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:42.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:42.66#ibcon#enter wrdev, iclass 39, count 2 2006.161.07:48:42.66#ibcon#first serial, iclass 39, count 2 2006.161.07:48:42.66#ibcon#enter sib2, iclass 39, count 2 2006.161.07:48:42.66#ibcon#flushed, iclass 39, count 2 2006.161.07:48:42.66#ibcon#about to write, iclass 39, count 2 2006.161.07:48:42.66#ibcon#wrote, iclass 39, count 2 2006.161.07:48:42.66#ibcon#about to read 3, iclass 39, count 2 2006.161.07:48:42.68#ibcon#read 3, iclass 39, count 2 2006.161.07:48:42.68#ibcon#about to read 4, iclass 39, count 2 2006.161.07:48:42.68#ibcon#read 4, iclass 39, count 2 2006.161.07:48:42.68#ibcon#about to read 5, iclass 39, count 2 2006.161.07:48:42.68#ibcon#read 5, iclass 39, count 2 2006.161.07:48:42.68#ibcon#about to read 6, iclass 39, count 2 2006.161.07:48:42.68#ibcon#read 6, iclass 39, count 2 2006.161.07:48:42.68#ibcon#end of sib2, iclass 39, count 2 2006.161.07:48:42.68#ibcon#*mode == 0, iclass 39, count 2 2006.161.07:48:42.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.07:48:42.68#ibcon#[27=AT03-04\r\n] 2006.161.07:48:42.68#ibcon#*before write, iclass 39, count 2 2006.161.07:48:42.68#ibcon#enter sib2, iclass 39, count 2 2006.161.07:48:42.68#ibcon#flushed, iclass 39, count 2 2006.161.07:48:42.68#ibcon#about to write, iclass 39, count 2 2006.161.07:48:42.68#ibcon#wrote, iclass 39, count 2 2006.161.07:48:42.68#ibcon#about to read 3, iclass 39, count 2 2006.161.07:48:42.71#ibcon#read 3, iclass 39, count 2 2006.161.07:48:42.71#ibcon#about to read 4, iclass 39, count 2 2006.161.07:48:42.71#ibcon#read 4, iclass 39, count 2 2006.161.07:48:42.71#ibcon#about to read 5, iclass 39, count 2 2006.161.07:48:42.71#ibcon#read 5, iclass 39, count 2 2006.161.07:48:42.71#ibcon#about to read 6, iclass 39, count 2 2006.161.07:48:42.71#ibcon#read 6, iclass 39, count 2 2006.161.07:48:42.71#ibcon#end of sib2, iclass 39, count 2 2006.161.07:48:42.71#ibcon#*after write, iclass 39, count 2 2006.161.07:48:42.71#ibcon#*before return 0, iclass 39, count 2 2006.161.07:48:42.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:42.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.07:48:42.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.07:48:42.71#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:42.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:42.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:42.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:42.83#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:48:42.83#ibcon#first serial, iclass 39, count 0 2006.161.07:48:42.83#ibcon#enter sib2, iclass 39, count 0 2006.161.07:48:42.83#ibcon#flushed, iclass 39, count 0 2006.161.07:48:42.83#ibcon#about to write, iclass 39, count 0 2006.161.07:48:42.83#ibcon#wrote, iclass 39, count 0 2006.161.07:48:42.83#ibcon#about to read 3, iclass 39, count 0 2006.161.07:48:42.85#ibcon#read 3, iclass 39, count 0 2006.161.07:48:42.85#ibcon#about to read 4, iclass 39, count 0 2006.161.07:48:42.85#ibcon#read 4, iclass 39, count 0 2006.161.07:48:42.85#ibcon#about to read 5, iclass 39, count 0 2006.161.07:48:42.85#ibcon#read 5, iclass 39, count 0 2006.161.07:48:42.85#ibcon#about to read 6, iclass 39, count 0 2006.161.07:48:42.85#ibcon#read 6, iclass 39, count 0 2006.161.07:48:42.85#ibcon#end of sib2, iclass 39, count 0 2006.161.07:48:42.85#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:48:42.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:48:42.85#ibcon#[27=USB\r\n] 2006.161.07:48:42.85#ibcon#*before write, iclass 39, count 0 2006.161.07:48:42.85#ibcon#enter sib2, iclass 39, count 0 2006.161.07:48:42.85#ibcon#flushed, iclass 39, count 0 2006.161.07:48:42.85#ibcon#about to write, iclass 39, count 0 2006.161.07:48:42.85#ibcon#wrote, iclass 39, count 0 2006.161.07:48:42.85#ibcon#about to read 3, iclass 39, count 0 2006.161.07:48:42.88#ibcon#read 3, iclass 39, count 0 2006.161.07:48:42.88#ibcon#about to read 4, iclass 39, count 0 2006.161.07:48:42.88#ibcon#read 4, iclass 39, count 0 2006.161.07:48:42.88#ibcon#about to read 5, iclass 39, count 0 2006.161.07:48:42.88#ibcon#read 5, iclass 39, count 0 2006.161.07:48:42.88#ibcon#about to read 6, iclass 39, count 0 2006.161.07:48:42.88#ibcon#read 6, iclass 39, count 0 2006.161.07:48:42.88#ibcon#end of sib2, iclass 39, count 0 2006.161.07:48:42.88#ibcon#*after write, iclass 39, count 0 2006.161.07:48:42.88#ibcon#*before return 0, iclass 39, count 0 2006.161.07:48:42.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:42.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.07:48:42.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:48:42.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:48:42.88$vc4f8/vblo=4,712.99 2006.161.07:48:42.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.07:48:42.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.07:48:42.88#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:42.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:42.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:42.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:42.88#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:48:42.88#ibcon#first serial, iclass 3, count 0 2006.161.07:48:42.88#ibcon#enter sib2, iclass 3, count 0 2006.161.07:48:42.88#ibcon#flushed, iclass 3, count 0 2006.161.07:48:42.88#ibcon#about to write, iclass 3, count 0 2006.161.07:48:42.88#ibcon#wrote, iclass 3, count 0 2006.161.07:48:42.88#ibcon#about to read 3, iclass 3, count 0 2006.161.07:48:42.90#ibcon#read 3, iclass 3, count 0 2006.161.07:48:42.90#ibcon#about to read 4, iclass 3, count 0 2006.161.07:48:42.90#ibcon#read 4, iclass 3, count 0 2006.161.07:48:42.90#ibcon#about to read 5, iclass 3, count 0 2006.161.07:48:42.90#ibcon#read 5, iclass 3, count 0 2006.161.07:48:42.90#ibcon#about to read 6, iclass 3, count 0 2006.161.07:48:42.90#ibcon#read 6, iclass 3, count 0 2006.161.07:48:42.90#ibcon#end of sib2, iclass 3, count 0 2006.161.07:48:42.90#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:48:42.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:48:42.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:48:42.90#ibcon#*before write, iclass 3, count 0 2006.161.07:48:42.90#ibcon#enter sib2, iclass 3, count 0 2006.161.07:48:42.90#ibcon#flushed, iclass 3, count 0 2006.161.07:48:42.90#ibcon#about to write, iclass 3, count 0 2006.161.07:48:42.90#ibcon#wrote, iclass 3, count 0 2006.161.07:48:42.90#ibcon#about to read 3, iclass 3, count 0 2006.161.07:48:42.94#ibcon#read 3, iclass 3, count 0 2006.161.07:48:42.94#ibcon#about to read 4, iclass 3, count 0 2006.161.07:48:42.94#ibcon#read 4, iclass 3, count 0 2006.161.07:48:42.94#ibcon#about to read 5, iclass 3, count 0 2006.161.07:48:42.94#ibcon#read 5, iclass 3, count 0 2006.161.07:48:42.94#ibcon#about to read 6, iclass 3, count 0 2006.161.07:48:42.94#ibcon#read 6, iclass 3, count 0 2006.161.07:48:42.94#ibcon#end of sib2, iclass 3, count 0 2006.161.07:48:42.94#ibcon#*after write, iclass 3, count 0 2006.161.07:48:42.94#ibcon#*before return 0, iclass 3, count 0 2006.161.07:48:42.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:42.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.07:48:42.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:48:42.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:48:42.94$vc4f8/vb=4,4 2006.161.07:48:42.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.07:48:42.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.07:48:42.94#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:42.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:43.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:43.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:43.00#ibcon#enter wrdev, iclass 5, count 2 2006.161.07:48:43.00#ibcon#first serial, iclass 5, count 2 2006.161.07:48:43.00#ibcon#enter sib2, iclass 5, count 2 2006.161.07:48:43.00#ibcon#flushed, iclass 5, count 2 2006.161.07:48:43.00#ibcon#about to write, iclass 5, count 2 2006.161.07:48:43.00#ibcon#wrote, iclass 5, count 2 2006.161.07:48:43.00#ibcon#about to read 3, iclass 5, count 2 2006.161.07:48:43.02#ibcon#read 3, iclass 5, count 2 2006.161.07:48:43.02#ibcon#about to read 4, iclass 5, count 2 2006.161.07:48:43.02#ibcon#read 4, iclass 5, count 2 2006.161.07:48:43.02#ibcon#about to read 5, iclass 5, count 2 2006.161.07:48:43.02#ibcon#read 5, iclass 5, count 2 2006.161.07:48:43.02#ibcon#about to read 6, iclass 5, count 2 2006.161.07:48:43.02#ibcon#read 6, iclass 5, count 2 2006.161.07:48:43.02#ibcon#end of sib2, iclass 5, count 2 2006.161.07:48:43.02#ibcon#*mode == 0, iclass 5, count 2 2006.161.07:48:43.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.07:48:43.02#ibcon#[27=AT04-04\r\n] 2006.161.07:48:43.02#ibcon#*before write, iclass 5, count 2 2006.161.07:48:43.02#ibcon#enter sib2, iclass 5, count 2 2006.161.07:48:43.02#ibcon#flushed, iclass 5, count 2 2006.161.07:48:43.02#ibcon#about to write, iclass 5, count 2 2006.161.07:48:43.02#ibcon#wrote, iclass 5, count 2 2006.161.07:48:43.02#ibcon#about to read 3, iclass 5, count 2 2006.161.07:48:43.05#ibcon#read 3, iclass 5, count 2 2006.161.07:48:43.05#ibcon#about to read 4, iclass 5, count 2 2006.161.07:48:43.05#ibcon#read 4, iclass 5, count 2 2006.161.07:48:43.05#ibcon#about to read 5, iclass 5, count 2 2006.161.07:48:43.05#ibcon#read 5, iclass 5, count 2 2006.161.07:48:43.05#ibcon#about to read 6, iclass 5, count 2 2006.161.07:48:43.05#ibcon#read 6, iclass 5, count 2 2006.161.07:48:43.05#ibcon#end of sib2, iclass 5, count 2 2006.161.07:48:43.05#ibcon#*after write, iclass 5, count 2 2006.161.07:48:43.05#ibcon#*before return 0, iclass 5, count 2 2006.161.07:48:43.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:43.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.07:48:43.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.07:48:43.05#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:43.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:43.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:43.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:43.17#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:48:43.17#ibcon#first serial, iclass 5, count 0 2006.161.07:48:43.17#ibcon#enter sib2, iclass 5, count 0 2006.161.07:48:43.17#ibcon#flushed, iclass 5, count 0 2006.161.07:48:43.17#ibcon#about to write, iclass 5, count 0 2006.161.07:48:43.17#ibcon#wrote, iclass 5, count 0 2006.161.07:48:43.17#ibcon#about to read 3, iclass 5, count 0 2006.161.07:48:43.19#ibcon#read 3, iclass 5, count 0 2006.161.07:48:43.19#ibcon#about to read 4, iclass 5, count 0 2006.161.07:48:43.19#ibcon#read 4, iclass 5, count 0 2006.161.07:48:43.19#ibcon#about to read 5, iclass 5, count 0 2006.161.07:48:43.19#ibcon#read 5, iclass 5, count 0 2006.161.07:48:43.19#ibcon#about to read 6, iclass 5, count 0 2006.161.07:48:43.19#ibcon#read 6, iclass 5, count 0 2006.161.07:48:43.19#ibcon#end of sib2, iclass 5, count 0 2006.161.07:48:43.19#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:48:43.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:48:43.19#ibcon#[27=USB\r\n] 2006.161.07:48:43.19#ibcon#*before write, iclass 5, count 0 2006.161.07:48:43.19#ibcon#enter sib2, iclass 5, count 0 2006.161.07:48:43.19#ibcon#flushed, iclass 5, count 0 2006.161.07:48:43.19#ibcon#about to write, iclass 5, count 0 2006.161.07:48:43.19#ibcon#wrote, iclass 5, count 0 2006.161.07:48:43.19#ibcon#about to read 3, iclass 5, count 0 2006.161.07:48:43.22#ibcon#read 3, iclass 5, count 0 2006.161.07:48:43.22#ibcon#about to read 4, iclass 5, count 0 2006.161.07:48:43.22#ibcon#read 4, iclass 5, count 0 2006.161.07:48:43.22#ibcon#about to read 5, iclass 5, count 0 2006.161.07:48:43.22#ibcon#read 5, iclass 5, count 0 2006.161.07:48:43.22#ibcon#about to read 6, iclass 5, count 0 2006.161.07:48:43.22#ibcon#read 6, iclass 5, count 0 2006.161.07:48:43.22#ibcon#end of sib2, iclass 5, count 0 2006.161.07:48:43.22#ibcon#*after write, iclass 5, count 0 2006.161.07:48:43.22#ibcon#*before return 0, iclass 5, count 0 2006.161.07:48:43.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:43.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.07:48:43.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:48:43.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:48:43.22$vc4f8/vblo=5,744.99 2006.161.07:48:43.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.07:48:43.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.07:48:43.22#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:43.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:43.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:43.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:43.22#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:48:43.22#ibcon#first serial, iclass 7, count 0 2006.161.07:48:43.22#ibcon#enter sib2, iclass 7, count 0 2006.161.07:48:43.22#ibcon#flushed, iclass 7, count 0 2006.161.07:48:43.22#ibcon#about to write, iclass 7, count 0 2006.161.07:48:43.22#ibcon#wrote, iclass 7, count 0 2006.161.07:48:43.22#ibcon#about to read 3, iclass 7, count 0 2006.161.07:48:43.24#ibcon#read 3, iclass 7, count 0 2006.161.07:48:43.24#ibcon#about to read 4, iclass 7, count 0 2006.161.07:48:43.24#ibcon#read 4, iclass 7, count 0 2006.161.07:48:43.24#ibcon#about to read 5, iclass 7, count 0 2006.161.07:48:43.24#ibcon#read 5, iclass 7, count 0 2006.161.07:48:43.24#ibcon#about to read 6, iclass 7, count 0 2006.161.07:48:43.24#ibcon#read 6, iclass 7, count 0 2006.161.07:48:43.24#ibcon#end of sib2, iclass 7, count 0 2006.161.07:48:43.24#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:48:43.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:48:43.24#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:48:43.24#ibcon#*before write, iclass 7, count 0 2006.161.07:48:43.24#ibcon#enter sib2, iclass 7, count 0 2006.161.07:48:43.24#ibcon#flushed, iclass 7, count 0 2006.161.07:48:43.24#ibcon#about to write, iclass 7, count 0 2006.161.07:48:43.24#ibcon#wrote, iclass 7, count 0 2006.161.07:48:43.24#ibcon#about to read 3, iclass 7, count 0 2006.161.07:48:43.28#ibcon#read 3, iclass 7, count 0 2006.161.07:48:43.28#ibcon#about to read 4, iclass 7, count 0 2006.161.07:48:43.28#ibcon#read 4, iclass 7, count 0 2006.161.07:48:43.28#ibcon#about to read 5, iclass 7, count 0 2006.161.07:48:43.28#ibcon#read 5, iclass 7, count 0 2006.161.07:48:43.28#ibcon#about to read 6, iclass 7, count 0 2006.161.07:48:43.28#ibcon#read 6, iclass 7, count 0 2006.161.07:48:43.28#ibcon#end of sib2, iclass 7, count 0 2006.161.07:48:43.28#ibcon#*after write, iclass 7, count 0 2006.161.07:48:43.28#ibcon#*before return 0, iclass 7, count 0 2006.161.07:48:43.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:43.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.07:48:43.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:48:43.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:48:43.28$vc4f8/vb=5,4 2006.161.07:48:43.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.07:48:43.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.07:48:43.28#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:43.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:43.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:43.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:43.34#ibcon#enter wrdev, iclass 11, count 2 2006.161.07:48:43.34#ibcon#first serial, iclass 11, count 2 2006.161.07:48:43.34#ibcon#enter sib2, iclass 11, count 2 2006.161.07:48:43.34#ibcon#flushed, iclass 11, count 2 2006.161.07:48:43.34#ibcon#about to write, iclass 11, count 2 2006.161.07:48:43.34#ibcon#wrote, iclass 11, count 2 2006.161.07:48:43.34#ibcon#about to read 3, iclass 11, count 2 2006.161.07:48:43.36#ibcon#read 3, iclass 11, count 2 2006.161.07:48:43.36#ibcon#about to read 4, iclass 11, count 2 2006.161.07:48:43.36#ibcon#read 4, iclass 11, count 2 2006.161.07:48:43.36#ibcon#about to read 5, iclass 11, count 2 2006.161.07:48:43.36#ibcon#read 5, iclass 11, count 2 2006.161.07:48:43.36#ibcon#about to read 6, iclass 11, count 2 2006.161.07:48:43.36#ibcon#read 6, iclass 11, count 2 2006.161.07:48:43.36#ibcon#end of sib2, iclass 11, count 2 2006.161.07:48:43.36#ibcon#*mode == 0, iclass 11, count 2 2006.161.07:48:43.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.07:48:43.36#ibcon#[27=AT05-04\r\n] 2006.161.07:48:43.36#ibcon#*before write, iclass 11, count 2 2006.161.07:48:43.36#ibcon#enter sib2, iclass 11, count 2 2006.161.07:48:43.36#ibcon#flushed, iclass 11, count 2 2006.161.07:48:43.36#ibcon#about to write, iclass 11, count 2 2006.161.07:48:43.36#ibcon#wrote, iclass 11, count 2 2006.161.07:48:43.36#ibcon#about to read 3, iclass 11, count 2 2006.161.07:48:43.39#ibcon#read 3, iclass 11, count 2 2006.161.07:48:43.39#ibcon#about to read 4, iclass 11, count 2 2006.161.07:48:43.39#ibcon#read 4, iclass 11, count 2 2006.161.07:48:43.39#ibcon#about to read 5, iclass 11, count 2 2006.161.07:48:43.39#ibcon#read 5, iclass 11, count 2 2006.161.07:48:43.39#ibcon#about to read 6, iclass 11, count 2 2006.161.07:48:43.39#ibcon#read 6, iclass 11, count 2 2006.161.07:48:43.39#ibcon#end of sib2, iclass 11, count 2 2006.161.07:48:43.39#ibcon#*after write, iclass 11, count 2 2006.161.07:48:43.39#ibcon#*before return 0, iclass 11, count 2 2006.161.07:48:43.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:43.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.07:48:43.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.07:48:43.39#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:43.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:43.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:43.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:43.51#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:48:43.51#ibcon#first serial, iclass 11, count 0 2006.161.07:48:43.51#ibcon#enter sib2, iclass 11, count 0 2006.161.07:48:43.51#ibcon#flushed, iclass 11, count 0 2006.161.07:48:43.51#ibcon#about to write, iclass 11, count 0 2006.161.07:48:43.51#ibcon#wrote, iclass 11, count 0 2006.161.07:48:43.51#ibcon#about to read 3, iclass 11, count 0 2006.161.07:48:43.53#ibcon#read 3, iclass 11, count 0 2006.161.07:48:43.53#ibcon#about to read 4, iclass 11, count 0 2006.161.07:48:43.53#ibcon#read 4, iclass 11, count 0 2006.161.07:48:43.53#ibcon#about to read 5, iclass 11, count 0 2006.161.07:48:43.53#ibcon#read 5, iclass 11, count 0 2006.161.07:48:43.53#ibcon#about to read 6, iclass 11, count 0 2006.161.07:48:43.53#ibcon#read 6, iclass 11, count 0 2006.161.07:48:43.53#ibcon#end of sib2, iclass 11, count 0 2006.161.07:48:43.53#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:48:43.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:48:43.53#ibcon#[27=USB\r\n] 2006.161.07:48:43.53#ibcon#*before write, iclass 11, count 0 2006.161.07:48:43.53#ibcon#enter sib2, iclass 11, count 0 2006.161.07:48:43.53#ibcon#flushed, iclass 11, count 0 2006.161.07:48:43.53#ibcon#about to write, iclass 11, count 0 2006.161.07:48:43.53#ibcon#wrote, iclass 11, count 0 2006.161.07:48:43.53#ibcon#about to read 3, iclass 11, count 0 2006.161.07:48:43.56#ibcon#read 3, iclass 11, count 0 2006.161.07:48:43.56#ibcon#about to read 4, iclass 11, count 0 2006.161.07:48:43.56#ibcon#read 4, iclass 11, count 0 2006.161.07:48:43.56#ibcon#about to read 5, iclass 11, count 0 2006.161.07:48:43.56#ibcon#read 5, iclass 11, count 0 2006.161.07:48:43.56#ibcon#about to read 6, iclass 11, count 0 2006.161.07:48:43.56#ibcon#read 6, iclass 11, count 0 2006.161.07:48:43.56#ibcon#end of sib2, iclass 11, count 0 2006.161.07:48:43.56#ibcon#*after write, iclass 11, count 0 2006.161.07:48:43.56#ibcon#*before return 0, iclass 11, count 0 2006.161.07:48:43.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:43.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.07:48:43.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:48:43.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:48:43.56$vc4f8/vblo=6,752.99 2006.161.07:48:43.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.07:48:43.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.07:48:43.56#ibcon#ireg 17 cls_cnt 0 2006.161.07:48:43.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:43.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:43.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:43.56#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:48:43.56#ibcon#first serial, iclass 13, count 0 2006.161.07:48:43.56#ibcon#enter sib2, iclass 13, count 0 2006.161.07:48:43.56#ibcon#flushed, iclass 13, count 0 2006.161.07:48:43.56#ibcon#about to write, iclass 13, count 0 2006.161.07:48:43.56#ibcon#wrote, iclass 13, count 0 2006.161.07:48:43.56#ibcon#about to read 3, iclass 13, count 0 2006.161.07:48:43.58#ibcon#read 3, iclass 13, count 0 2006.161.07:48:43.58#ibcon#about to read 4, iclass 13, count 0 2006.161.07:48:43.58#ibcon#read 4, iclass 13, count 0 2006.161.07:48:43.58#ibcon#about to read 5, iclass 13, count 0 2006.161.07:48:43.58#ibcon#read 5, iclass 13, count 0 2006.161.07:48:43.58#ibcon#about to read 6, iclass 13, count 0 2006.161.07:48:43.58#ibcon#read 6, iclass 13, count 0 2006.161.07:48:43.58#ibcon#end of sib2, iclass 13, count 0 2006.161.07:48:43.58#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:48:43.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:48:43.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:48:43.58#ibcon#*before write, iclass 13, count 0 2006.161.07:48:43.58#ibcon#enter sib2, iclass 13, count 0 2006.161.07:48:43.58#ibcon#flushed, iclass 13, count 0 2006.161.07:48:43.58#ibcon#about to write, iclass 13, count 0 2006.161.07:48:43.58#ibcon#wrote, iclass 13, count 0 2006.161.07:48:43.58#ibcon#about to read 3, iclass 13, count 0 2006.161.07:48:43.62#ibcon#read 3, iclass 13, count 0 2006.161.07:48:43.62#ibcon#about to read 4, iclass 13, count 0 2006.161.07:48:43.62#ibcon#read 4, iclass 13, count 0 2006.161.07:48:43.62#ibcon#about to read 5, iclass 13, count 0 2006.161.07:48:43.62#ibcon#read 5, iclass 13, count 0 2006.161.07:48:43.62#ibcon#about to read 6, iclass 13, count 0 2006.161.07:48:43.62#ibcon#read 6, iclass 13, count 0 2006.161.07:48:43.62#ibcon#end of sib2, iclass 13, count 0 2006.161.07:48:43.62#ibcon#*after write, iclass 13, count 0 2006.161.07:48:43.62#ibcon#*before return 0, iclass 13, count 0 2006.161.07:48:43.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:43.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.07:48:43.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:48:43.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:48:43.62$vc4f8/vb=6,4 2006.161.07:48:43.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.07:48:43.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.07:48:43.62#ibcon#ireg 11 cls_cnt 2 2006.161.07:48:43.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:43.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:43.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:43.68#ibcon#enter wrdev, iclass 15, count 2 2006.161.07:48:43.68#ibcon#first serial, iclass 15, count 2 2006.161.07:48:43.68#ibcon#enter sib2, iclass 15, count 2 2006.161.07:48:43.68#ibcon#flushed, iclass 15, count 2 2006.161.07:48:43.68#ibcon#about to write, iclass 15, count 2 2006.161.07:48:43.68#ibcon#wrote, iclass 15, count 2 2006.161.07:48:43.68#ibcon#about to read 3, iclass 15, count 2 2006.161.07:48:43.70#ibcon#read 3, iclass 15, count 2 2006.161.07:48:43.70#ibcon#about to read 4, iclass 15, count 2 2006.161.07:48:43.70#ibcon#read 4, iclass 15, count 2 2006.161.07:48:43.70#ibcon#about to read 5, iclass 15, count 2 2006.161.07:48:43.70#ibcon#read 5, iclass 15, count 2 2006.161.07:48:43.70#ibcon#about to read 6, iclass 15, count 2 2006.161.07:48:43.70#ibcon#read 6, iclass 15, count 2 2006.161.07:48:43.70#ibcon#end of sib2, iclass 15, count 2 2006.161.07:48:43.70#ibcon#*mode == 0, iclass 15, count 2 2006.161.07:48:43.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.07:48:43.70#ibcon#[27=AT06-04\r\n] 2006.161.07:48:43.70#ibcon#*before write, iclass 15, count 2 2006.161.07:48:43.70#ibcon#enter sib2, iclass 15, count 2 2006.161.07:48:43.70#ibcon#flushed, iclass 15, count 2 2006.161.07:48:43.70#ibcon#about to write, iclass 15, count 2 2006.161.07:48:43.70#ibcon#wrote, iclass 15, count 2 2006.161.07:48:43.70#ibcon#about to read 3, iclass 15, count 2 2006.161.07:48:43.73#ibcon#read 3, iclass 15, count 2 2006.161.07:48:43.73#ibcon#about to read 4, iclass 15, count 2 2006.161.07:48:43.73#ibcon#read 4, iclass 15, count 2 2006.161.07:48:43.73#ibcon#about to read 5, iclass 15, count 2 2006.161.07:48:43.73#ibcon#read 5, iclass 15, count 2 2006.161.07:48:43.73#ibcon#about to read 6, iclass 15, count 2 2006.161.07:48:43.73#ibcon#read 6, iclass 15, count 2 2006.161.07:48:43.73#ibcon#end of sib2, iclass 15, count 2 2006.161.07:48:43.73#ibcon#*after write, iclass 15, count 2 2006.161.07:48:43.73#ibcon#*before return 0, iclass 15, count 2 2006.161.07:48:43.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:43.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.07:48:43.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.07:48:43.73#ibcon#ireg 7 cls_cnt 0 2006.161.07:48:43.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:43.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:43.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:43.85#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:48:43.85#ibcon#first serial, iclass 15, count 0 2006.161.07:48:43.85#ibcon#enter sib2, iclass 15, count 0 2006.161.07:48:43.85#ibcon#flushed, iclass 15, count 0 2006.161.07:48:43.85#ibcon#about to write, iclass 15, count 0 2006.161.07:48:43.85#ibcon#wrote, iclass 15, count 0 2006.161.07:48:43.85#ibcon#about to read 3, iclass 15, count 0 2006.161.07:48:43.87#ibcon#read 3, iclass 15, count 0 2006.161.07:48:43.87#ibcon#about to read 4, iclass 15, count 0 2006.161.07:48:43.87#ibcon#read 4, iclass 15, count 0 2006.161.07:48:43.87#ibcon#about to read 5, iclass 15, count 0 2006.161.07:48:43.87#ibcon#read 5, iclass 15, count 0 2006.161.07:48:43.87#ibcon#about to read 6, iclass 15, count 0 2006.161.07:48:43.87#ibcon#read 6, iclass 15, count 0 2006.161.07:48:43.87#ibcon#end of sib2, iclass 15, count 0 2006.161.07:48:43.87#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:48:43.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:48:43.87#ibcon#[27=USB\r\n] 2006.161.07:48:43.87#ibcon#*before write, iclass 15, count 0 2006.161.07:48:43.87#ibcon#enter sib2, iclass 15, count 0 2006.161.07:48:43.87#ibcon#flushed, iclass 15, count 0 2006.161.07:48:43.87#ibcon#about to write, iclass 15, count 0 2006.161.07:48:43.87#ibcon#wrote, iclass 15, count 0 2006.161.07:48:43.87#ibcon#about to read 3, iclass 15, count 0 2006.161.07:48:43.90#ibcon#read 3, iclass 15, count 0 2006.161.07:48:43.90#ibcon#about to read 4, iclass 15, count 0 2006.161.07:48:43.90#ibcon#read 4, iclass 15, count 0 2006.161.07:48:43.90#ibcon#about to read 5, iclass 15, count 0 2006.161.07:48:43.90#ibcon#read 5, iclass 15, count 0 2006.161.07:48:43.90#ibcon#about to read 6, iclass 15, count 0 2006.161.07:48:43.90#ibcon#read 6, iclass 15, count 0 2006.161.07:48:43.90#ibcon#end of sib2, iclass 15, count 0 2006.161.07:48:43.90#ibcon#*after write, iclass 15, count 0 2006.161.07:48:43.90#ibcon#*before return 0, iclass 15, count 0 2006.161.07:48:43.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:43.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.07:48:43.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:48:43.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:48:43.90$vc4f8/vabw=wide 2006.161.07:48:43.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.07:48:43.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.07:48:43.90#ibcon#ireg 8 cls_cnt 0 2006.161.07:48:43.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:43.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:43.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:43.90#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:48:43.90#ibcon#first serial, iclass 17, count 0 2006.161.07:48:43.90#ibcon#enter sib2, iclass 17, count 0 2006.161.07:48:43.90#ibcon#flushed, iclass 17, count 0 2006.161.07:48:43.90#ibcon#about to write, iclass 17, count 0 2006.161.07:48:43.90#ibcon#wrote, iclass 17, count 0 2006.161.07:48:43.90#ibcon#about to read 3, iclass 17, count 0 2006.161.07:48:43.92#ibcon#read 3, iclass 17, count 0 2006.161.07:48:43.92#ibcon#about to read 4, iclass 17, count 0 2006.161.07:48:43.92#ibcon#read 4, iclass 17, count 0 2006.161.07:48:43.92#ibcon#about to read 5, iclass 17, count 0 2006.161.07:48:43.92#ibcon#read 5, iclass 17, count 0 2006.161.07:48:43.92#ibcon#about to read 6, iclass 17, count 0 2006.161.07:48:43.92#ibcon#read 6, iclass 17, count 0 2006.161.07:48:43.92#ibcon#end of sib2, iclass 17, count 0 2006.161.07:48:43.92#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:48:43.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:48:43.92#ibcon#[25=BW32\r\n] 2006.161.07:48:43.92#ibcon#*before write, iclass 17, count 0 2006.161.07:48:43.92#ibcon#enter sib2, iclass 17, count 0 2006.161.07:48:43.92#ibcon#flushed, iclass 17, count 0 2006.161.07:48:43.92#ibcon#about to write, iclass 17, count 0 2006.161.07:48:43.92#ibcon#wrote, iclass 17, count 0 2006.161.07:48:43.92#ibcon#about to read 3, iclass 17, count 0 2006.161.07:48:43.95#ibcon#read 3, iclass 17, count 0 2006.161.07:48:43.95#ibcon#about to read 4, iclass 17, count 0 2006.161.07:48:43.95#ibcon#read 4, iclass 17, count 0 2006.161.07:48:43.95#ibcon#about to read 5, iclass 17, count 0 2006.161.07:48:43.95#ibcon#read 5, iclass 17, count 0 2006.161.07:48:43.95#ibcon#about to read 6, iclass 17, count 0 2006.161.07:48:43.95#ibcon#read 6, iclass 17, count 0 2006.161.07:48:43.95#ibcon#end of sib2, iclass 17, count 0 2006.161.07:48:43.95#ibcon#*after write, iclass 17, count 0 2006.161.07:48:43.95#ibcon#*before return 0, iclass 17, count 0 2006.161.07:48:43.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:43.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.07:48:43.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:48:43.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:48:43.95$vc4f8/vbbw=wide 2006.161.07:48:43.95#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:48:43.95#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:48:43.95#ibcon#ireg 8 cls_cnt 0 2006.161.07:48:43.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:48:44.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:48:44.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:48:44.02#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:48:44.02#ibcon#first serial, iclass 19, count 0 2006.161.07:48:44.02#ibcon#enter sib2, iclass 19, count 0 2006.161.07:48:44.02#ibcon#flushed, iclass 19, count 0 2006.161.07:48:44.02#ibcon#about to write, iclass 19, count 0 2006.161.07:48:44.02#ibcon#wrote, iclass 19, count 0 2006.161.07:48:44.02#ibcon#about to read 3, iclass 19, count 0 2006.161.07:48:44.04#ibcon#read 3, iclass 19, count 0 2006.161.07:48:44.04#ibcon#about to read 4, iclass 19, count 0 2006.161.07:48:44.04#ibcon#read 4, iclass 19, count 0 2006.161.07:48:44.04#ibcon#about to read 5, iclass 19, count 0 2006.161.07:48:44.04#ibcon#read 5, iclass 19, count 0 2006.161.07:48:44.04#ibcon#about to read 6, iclass 19, count 0 2006.161.07:48:44.04#ibcon#read 6, iclass 19, count 0 2006.161.07:48:44.04#ibcon#end of sib2, iclass 19, count 0 2006.161.07:48:44.04#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:48:44.04#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:48:44.04#ibcon#[27=BW32\r\n] 2006.161.07:48:44.04#ibcon#*before write, iclass 19, count 0 2006.161.07:48:44.04#ibcon#enter sib2, iclass 19, count 0 2006.161.07:48:44.04#ibcon#flushed, iclass 19, count 0 2006.161.07:48:44.04#ibcon#about to write, iclass 19, count 0 2006.161.07:48:44.04#ibcon#wrote, iclass 19, count 0 2006.161.07:48:44.04#ibcon#about to read 3, iclass 19, count 0 2006.161.07:48:44.07#ibcon#read 3, iclass 19, count 0 2006.161.07:48:44.07#ibcon#about to read 4, iclass 19, count 0 2006.161.07:48:44.07#ibcon#read 4, iclass 19, count 0 2006.161.07:48:44.07#ibcon#about to read 5, iclass 19, count 0 2006.161.07:48:44.07#ibcon#read 5, iclass 19, count 0 2006.161.07:48:44.07#ibcon#about to read 6, iclass 19, count 0 2006.161.07:48:44.07#ibcon#read 6, iclass 19, count 0 2006.161.07:48:44.07#ibcon#end of sib2, iclass 19, count 0 2006.161.07:48:44.07#ibcon#*after write, iclass 19, count 0 2006.161.07:48:44.07#ibcon#*before return 0, iclass 19, count 0 2006.161.07:48:44.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:48:44.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:48:44.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:48:44.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:48:44.07$4f8m12a/ifd4f 2006.161.07:48:44.07$ifd4f/lo= 2006.161.07:48:44.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:48:44.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:48:44.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:48:44.07$ifd4f/patch= 2006.161.07:48:44.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:48:44.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:48:44.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:48:44.07$4f8m12a/"form=m,16.000,1:2 2006.161.07:48:44.07$4f8m12a/"tpicd 2006.161.07:48:44.07$4f8m12a/echo=off 2006.161.07:48:44.07$4f8m12a/xlog=off 2006.161.07:48:44.07:!2006.161.07:49:10 2006.161.07:48:55.13#trakl#Source acquired 2006.161.07:48:55.13#flagr#flagr/antenna,acquired 2006.161.07:49:10.00:preob 2006.161.07:49:11.13/onsource/TRACKING 2006.161.07:49:11.13:!2006.161.07:49:20 2006.161.07:49:20.00:data_valid=on 2006.161.07:49:20.00:midob 2006.161.07:49:20.13/onsource/TRACKING 2006.161.07:49:20.13/wx/24.07,1002.1,86 2006.161.07:49:20.26/cable/+6.5009E-03 2006.161.07:49:21.35/va/01,08,usb,yes,29,30 2006.161.07:49:21.35/va/02,07,usb,yes,29,30 2006.161.07:49:21.35/va/03,06,usb,yes,30,30 2006.161.07:49:21.35/va/04,07,usb,yes,29,31 2006.161.07:49:21.35/va/05,07,usb,yes,29,31 2006.161.07:49:21.35/va/06,06,usb,yes,28,28 2006.161.07:49:21.35/va/07,06,usb,yes,29,28 2006.161.07:49:21.35/va/08,07,usb,yes,27,27 2006.161.07:49:21.58/valo/01,532.99,yes,locked 2006.161.07:49:21.58/valo/02,572.99,yes,locked 2006.161.07:49:21.58/valo/03,672.99,yes,locked 2006.161.07:49:21.58/valo/04,832.99,yes,locked 2006.161.07:49:21.58/valo/05,652.99,yes,locked 2006.161.07:49:21.58/valo/06,772.99,yes,locked 2006.161.07:49:21.58/valo/07,832.99,yes,locked 2006.161.07:49:21.58/valo/08,852.99,yes,locked 2006.161.07:49:22.67/vb/01,04,usb,yes,29,27 2006.161.07:49:22.67/vb/02,04,usb,yes,30,32 2006.161.07:49:22.67/vb/03,04,usb,yes,27,31 2006.161.07:49:22.67/vb/04,04,usb,yes,28,28 2006.161.07:49:22.67/vb/05,04,usb,yes,26,30 2006.161.07:49:22.67/vb/06,04,usb,yes,27,30 2006.161.07:49:22.67/vb/07,04,usb,yes,29,29 2006.161.07:49:22.67/vb/08,04,usb,yes,27,30 2006.161.07:49:22.90/vblo/01,632.99,yes,locked 2006.161.07:49:22.90/vblo/02,640.99,yes,locked 2006.161.07:49:22.90/vblo/03,656.99,yes,locked 2006.161.07:49:22.90/vblo/04,712.99,yes,locked 2006.161.07:49:22.90/vblo/05,744.99,yes,locked 2006.161.07:49:22.90/vblo/06,752.99,yes,locked 2006.161.07:49:22.90/vblo/07,734.99,yes,locked 2006.161.07:49:22.90/vblo/08,744.99,yes,locked 2006.161.07:49:23.05/vabw/8 2006.161.07:49:23.20/vbbw/8 2006.161.07:49:23.29/xfe/off,on,14.5 2006.161.07:49:23.68/ifatt/23,28,28,28 2006.161.07:49:24.08/fmout-gps/S +4.47E-07 2006.161.07:49:24.12:!2006.161.07:51:40 2006.161.07:51:40.00:data_valid=off 2006.161.07:51:40.00:postob 2006.161.07:51:40.12/cable/+6.4985E-03 2006.161.07:51:40.12/wx/24.05,1002.2,85 2006.161.07:51:41.08/fmout-gps/S +4.46E-07 2006.161.07:51:41.08:scan_name=161-0753,k06161,60 2006.161.07:51:41.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.161.07:51:42.14#flagr#flagr/antenna,new-source 2006.161.07:51:42.14:checkk5 2006.161.07:51:42.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:51:43.14/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:51:43.58/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:51:44.02/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:51:44.41/chk_obsdata//k5ts1/T1610749??a.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.161.07:51:44.87/chk_obsdata//k5ts2/T1610749??b.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.161.07:51:45.30/chk_obsdata//k5ts3/T1610749??c.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.161.07:51:45.70/chk_obsdata//k5ts4/T1610749??d.dat file size is correct (nominal:1120MB, actual:1112MB). 2006.161.07:51:46.68/k5log//k5ts1_log_newline 2006.161.07:51:47.65/k5log//k5ts2_log_newline 2006.161.07:51:48.46/k5log//k5ts3_log_newline 2006.161.07:51:49.42/k5log//k5ts4_log_newline 2006.161.07:51:49.45/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:51:49.45:4f8m12a=2 2006.161.07:51:49.45$4f8m12a/echo=on 2006.161.07:51:49.45$4f8m12a/pcalon 2006.161.07:51:49.45$pcalon/"no phase cal control is implemented here 2006.161.07:51:49.45$4f8m12a/"tpicd=stop 2006.161.07:51:49.45$4f8m12a/vc4f8 2006.161.07:51:49.45$vc4f8/valo=1,532.99 2006.161.07:51:49.45#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:51:49.45#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:51:49.45#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:49.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:49.45#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:49.45#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:49.45#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:51:49.45#ibcon#first serial, iclass 26, count 0 2006.161.07:51:49.45#ibcon#enter sib2, iclass 26, count 0 2006.161.07:51:49.45#ibcon#flushed, iclass 26, count 0 2006.161.07:51:49.45#ibcon#about to write, iclass 26, count 0 2006.161.07:51:49.45#ibcon#wrote, iclass 26, count 0 2006.161.07:51:49.45#ibcon#about to read 3, iclass 26, count 0 2006.161.07:51:49.49#ibcon#read 3, iclass 26, count 0 2006.161.07:51:49.49#ibcon#about to read 4, iclass 26, count 0 2006.161.07:51:49.49#ibcon#read 4, iclass 26, count 0 2006.161.07:51:49.49#ibcon#about to read 5, iclass 26, count 0 2006.161.07:51:49.49#ibcon#read 5, iclass 26, count 0 2006.161.07:51:49.49#ibcon#about to read 6, iclass 26, count 0 2006.161.07:51:49.49#ibcon#read 6, iclass 26, count 0 2006.161.07:51:49.49#ibcon#end of sib2, iclass 26, count 0 2006.161.07:51:49.49#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:51:49.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:51:49.49#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:51:49.49#ibcon#*before write, iclass 26, count 0 2006.161.07:51:49.49#ibcon#enter sib2, iclass 26, count 0 2006.161.07:51:49.49#ibcon#flushed, iclass 26, count 0 2006.161.07:51:49.49#ibcon#about to write, iclass 26, count 0 2006.161.07:51:49.49#ibcon#wrote, iclass 26, count 0 2006.161.07:51:49.49#ibcon#about to read 3, iclass 26, count 0 2006.161.07:51:49.54#ibcon#read 3, iclass 26, count 0 2006.161.07:51:49.54#ibcon#about to read 4, iclass 26, count 0 2006.161.07:51:49.54#ibcon#read 4, iclass 26, count 0 2006.161.07:51:49.54#ibcon#about to read 5, iclass 26, count 0 2006.161.07:51:49.54#ibcon#read 5, iclass 26, count 0 2006.161.07:51:49.54#ibcon#about to read 6, iclass 26, count 0 2006.161.07:51:49.54#ibcon#read 6, iclass 26, count 0 2006.161.07:51:49.54#ibcon#end of sib2, iclass 26, count 0 2006.161.07:51:49.54#ibcon#*after write, iclass 26, count 0 2006.161.07:51:49.54#ibcon#*before return 0, iclass 26, count 0 2006.161.07:51:49.54#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:49.54#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:49.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:51:49.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:51:49.54$vc4f8/va=1,8 2006.161.07:51:49.54#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.07:51:49.54#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.07:51:49.54#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:49.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:49.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:49.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:49.54#ibcon#enter wrdev, iclass 28, count 2 2006.161.07:51:49.54#ibcon#first serial, iclass 28, count 2 2006.161.07:51:49.54#ibcon#enter sib2, iclass 28, count 2 2006.161.07:51:49.54#ibcon#flushed, iclass 28, count 2 2006.161.07:51:49.54#ibcon#about to write, iclass 28, count 2 2006.161.07:51:49.54#ibcon#wrote, iclass 28, count 2 2006.161.07:51:49.54#ibcon#about to read 3, iclass 28, count 2 2006.161.07:51:49.56#ibcon#read 3, iclass 28, count 2 2006.161.07:51:49.56#ibcon#about to read 4, iclass 28, count 2 2006.161.07:51:49.56#ibcon#read 4, iclass 28, count 2 2006.161.07:51:49.56#ibcon#about to read 5, iclass 28, count 2 2006.161.07:51:49.56#ibcon#read 5, iclass 28, count 2 2006.161.07:51:49.56#ibcon#about to read 6, iclass 28, count 2 2006.161.07:51:49.56#ibcon#read 6, iclass 28, count 2 2006.161.07:51:49.56#ibcon#end of sib2, iclass 28, count 2 2006.161.07:51:49.56#ibcon#*mode == 0, iclass 28, count 2 2006.161.07:51:49.56#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.07:51:49.56#ibcon#[25=AT01-08\r\n] 2006.161.07:51:49.56#ibcon#*before write, iclass 28, count 2 2006.161.07:51:49.56#ibcon#enter sib2, iclass 28, count 2 2006.161.07:51:49.56#ibcon#flushed, iclass 28, count 2 2006.161.07:51:49.56#ibcon#about to write, iclass 28, count 2 2006.161.07:51:49.56#ibcon#wrote, iclass 28, count 2 2006.161.07:51:49.56#ibcon#about to read 3, iclass 28, count 2 2006.161.07:51:49.59#ibcon#read 3, iclass 28, count 2 2006.161.07:51:49.59#ibcon#about to read 4, iclass 28, count 2 2006.161.07:51:49.59#ibcon#read 4, iclass 28, count 2 2006.161.07:51:49.59#ibcon#about to read 5, iclass 28, count 2 2006.161.07:51:49.59#ibcon#read 5, iclass 28, count 2 2006.161.07:51:49.59#ibcon#about to read 6, iclass 28, count 2 2006.161.07:51:49.59#ibcon#read 6, iclass 28, count 2 2006.161.07:51:49.59#ibcon#end of sib2, iclass 28, count 2 2006.161.07:51:49.59#ibcon#*after write, iclass 28, count 2 2006.161.07:51:49.59#ibcon#*before return 0, iclass 28, count 2 2006.161.07:51:49.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:49.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:49.59#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.07:51:49.59#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:49.59#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:49.71#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:49.71#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:49.71#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:51:49.71#ibcon#first serial, iclass 28, count 0 2006.161.07:51:49.71#ibcon#enter sib2, iclass 28, count 0 2006.161.07:51:49.71#ibcon#flushed, iclass 28, count 0 2006.161.07:51:49.71#ibcon#about to write, iclass 28, count 0 2006.161.07:51:49.71#ibcon#wrote, iclass 28, count 0 2006.161.07:51:49.71#ibcon#about to read 3, iclass 28, count 0 2006.161.07:51:49.73#ibcon#read 3, iclass 28, count 0 2006.161.07:51:49.73#ibcon#about to read 4, iclass 28, count 0 2006.161.07:51:49.73#ibcon#read 4, iclass 28, count 0 2006.161.07:51:49.73#ibcon#about to read 5, iclass 28, count 0 2006.161.07:51:49.73#ibcon#read 5, iclass 28, count 0 2006.161.07:51:49.73#ibcon#about to read 6, iclass 28, count 0 2006.161.07:51:49.73#ibcon#read 6, iclass 28, count 0 2006.161.07:51:49.73#ibcon#end of sib2, iclass 28, count 0 2006.161.07:51:49.73#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:51:49.73#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:51:49.73#ibcon#[25=USB\r\n] 2006.161.07:51:49.73#ibcon#*before write, iclass 28, count 0 2006.161.07:51:49.73#ibcon#enter sib2, iclass 28, count 0 2006.161.07:51:49.73#ibcon#flushed, iclass 28, count 0 2006.161.07:51:49.73#ibcon#about to write, iclass 28, count 0 2006.161.07:51:49.73#ibcon#wrote, iclass 28, count 0 2006.161.07:51:49.73#ibcon#about to read 3, iclass 28, count 0 2006.161.07:51:49.76#ibcon#read 3, iclass 28, count 0 2006.161.07:51:49.76#ibcon#about to read 4, iclass 28, count 0 2006.161.07:51:49.76#ibcon#read 4, iclass 28, count 0 2006.161.07:51:49.76#ibcon#about to read 5, iclass 28, count 0 2006.161.07:51:49.76#ibcon#read 5, iclass 28, count 0 2006.161.07:51:49.76#ibcon#about to read 6, iclass 28, count 0 2006.161.07:51:49.76#ibcon#read 6, iclass 28, count 0 2006.161.07:51:49.76#ibcon#end of sib2, iclass 28, count 0 2006.161.07:51:49.76#ibcon#*after write, iclass 28, count 0 2006.161.07:51:49.76#ibcon#*before return 0, iclass 28, count 0 2006.161.07:51:49.76#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:49.76#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:49.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:51:49.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:51:49.76$vc4f8/valo=2,572.99 2006.161.07:51:49.76#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:51:49.76#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:51:49.76#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:49.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:49.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:49.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:49.76#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:51:49.76#ibcon#first serial, iclass 30, count 0 2006.161.07:51:49.76#ibcon#enter sib2, iclass 30, count 0 2006.161.07:51:49.76#ibcon#flushed, iclass 30, count 0 2006.161.07:51:49.76#ibcon#about to write, iclass 30, count 0 2006.161.07:51:49.76#ibcon#wrote, iclass 30, count 0 2006.161.07:51:49.76#ibcon#about to read 3, iclass 30, count 0 2006.161.07:51:49.79#ibcon#read 3, iclass 30, count 0 2006.161.07:51:49.79#ibcon#about to read 4, iclass 30, count 0 2006.161.07:51:49.79#ibcon#read 4, iclass 30, count 0 2006.161.07:51:49.79#ibcon#about to read 5, iclass 30, count 0 2006.161.07:51:49.79#ibcon#read 5, iclass 30, count 0 2006.161.07:51:49.79#ibcon#about to read 6, iclass 30, count 0 2006.161.07:51:49.79#ibcon#read 6, iclass 30, count 0 2006.161.07:51:49.79#ibcon#end of sib2, iclass 30, count 0 2006.161.07:51:49.79#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:51:49.79#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:51:49.79#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:51:49.79#ibcon#*before write, iclass 30, count 0 2006.161.07:51:49.79#ibcon#enter sib2, iclass 30, count 0 2006.161.07:51:49.79#ibcon#flushed, iclass 30, count 0 2006.161.07:51:49.79#ibcon#about to write, iclass 30, count 0 2006.161.07:51:49.79#ibcon#wrote, iclass 30, count 0 2006.161.07:51:49.79#ibcon#about to read 3, iclass 30, count 0 2006.161.07:51:49.83#ibcon#read 3, iclass 30, count 0 2006.161.07:51:49.83#ibcon#about to read 4, iclass 30, count 0 2006.161.07:51:49.83#ibcon#read 4, iclass 30, count 0 2006.161.07:51:49.83#ibcon#about to read 5, iclass 30, count 0 2006.161.07:51:49.83#ibcon#read 5, iclass 30, count 0 2006.161.07:51:49.83#ibcon#about to read 6, iclass 30, count 0 2006.161.07:51:49.83#ibcon#read 6, iclass 30, count 0 2006.161.07:51:49.83#ibcon#end of sib2, iclass 30, count 0 2006.161.07:51:49.83#ibcon#*after write, iclass 30, count 0 2006.161.07:51:49.83#ibcon#*before return 0, iclass 30, count 0 2006.161.07:51:49.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:49.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:49.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:51:49.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:51:49.83$vc4f8/va=2,7 2006.161.07:51:49.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:51:49.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:51:49.83#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:49.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:49.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:49.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:49.88#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:51:49.88#ibcon#first serial, iclass 32, count 2 2006.161.07:51:49.88#ibcon#enter sib2, iclass 32, count 2 2006.161.07:51:49.88#ibcon#flushed, iclass 32, count 2 2006.161.07:51:49.88#ibcon#about to write, iclass 32, count 2 2006.161.07:51:49.88#ibcon#wrote, iclass 32, count 2 2006.161.07:51:49.88#ibcon#about to read 3, iclass 32, count 2 2006.161.07:51:49.90#ibcon#read 3, iclass 32, count 2 2006.161.07:51:49.90#ibcon#about to read 4, iclass 32, count 2 2006.161.07:51:49.90#ibcon#read 4, iclass 32, count 2 2006.161.07:51:49.90#ibcon#about to read 5, iclass 32, count 2 2006.161.07:51:49.90#ibcon#read 5, iclass 32, count 2 2006.161.07:51:49.90#ibcon#about to read 6, iclass 32, count 2 2006.161.07:51:49.90#ibcon#read 6, iclass 32, count 2 2006.161.07:51:49.90#ibcon#end of sib2, iclass 32, count 2 2006.161.07:51:49.90#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:51:49.90#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:51:49.90#ibcon#[25=AT02-07\r\n] 2006.161.07:51:49.90#ibcon#*before write, iclass 32, count 2 2006.161.07:51:49.90#ibcon#enter sib2, iclass 32, count 2 2006.161.07:51:49.90#ibcon#flushed, iclass 32, count 2 2006.161.07:51:49.90#ibcon#about to write, iclass 32, count 2 2006.161.07:51:49.90#ibcon#wrote, iclass 32, count 2 2006.161.07:51:49.90#ibcon#about to read 3, iclass 32, count 2 2006.161.07:51:49.93#ibcon#read 3, iclass 32, count 2 2006.161.07:51:49.93#ibcon#about to read 4, iclass 32, count 2 2006.161.07:51:49.93#ibcon#read 4, iclass 32, count 2 2006.161.07:51:49.93#ibcon#about to read 5, iclass 32, count 2 2006.161.07:51:49.93#ibcon#read 5, iclass 32, count 2 2006.161.07:51:49.93#ibcon#about to read 6, iclass 32, count 2 2006.161.07:51:49.93#ibcon#read 6, iclass 32, count 2 2006.161.07:51:49.93#ibcon#end of sib2, iclass 32, count 2 2006.161.07:51:49.93#ibcon#*after write, iclass 32, count 2 2006.161.07:51:49.93#ibcon#*before return 0, iclass 32, count 2 2006.161.07:51:49.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:49.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:49.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:51:49.93#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:49.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:50.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:50.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:50.05#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:51:50.05#ibcon#first serial, iclass 32, count 0 2006.161.07:51:50.05#ibcon#enter sib2, iclass 32, count 0 2006.161.07:51:50.05#ibcon#flushed, iclass 32, count 0 2006.161.07:51:50.05#ibcon#about to write, iclass 32, count 0 2006.161.07:51:50.05#ibcon#wrote, iclass 32, count 0 2006.161.07:51:50.05#ibcon#about to read 3, iclass 32, count 0 2006.161.07:51:50.09#ibcon#read 3, iclass 32, count 0 2006.161.07:51:50.09#ibcon#about to read 4, iclass 32, count 0 2006.161.07:51:50.09#ibcon#read 4, iclass 32, count 0 2006.161.07:51:50.09#ibcon#about to read 5, iclass 32, count 0 2006.161.07:51:50.09#ibcon#read 5, iclass 32, count 0 2006.161.07:51:50.09#ibcon#about to read 6, iclass 32, count 0 2006.161.07:51:50.09#ibcon#read 6, iclass 32, count 0 2006.161.07:51:50.09#ibcon#end of sib2, iclass 32, count 0 2006.161.07:51:50.09#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:51:50.09#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:51:50.09#ibcon#[25=USB\r\n] 2006.161.07:51:50.09#ibcon#*before write, iclass 32, count 0 2006.161.07:51:50.09#ibcon#enter sib2, iclass 32, count 0 2006.161.07:51:50.09#ibcon#flushed, iclass 32, count 0 2006.161.07:51:50.09#ibcon#about to write, iclass 32, count 0 2006.161.07:51:50.09#ibcon#wrote, iclass 32, count 0 2006.161.07:51:50.09#ibcon#about to read 3, iclass 32, count 0 2006.161.07:51:50.12#ibcon#read 3, iclass 32, count 0 2006.161.07:51:50.12#ibcon#about to read 4, iclass 32, count 0 2006.161.07:51:50.12#ibcon#read 4, iclass 32, count 0 2006.161.07:51:50.12#ibcon#about to read 5, iclass 32, count 0 2006.161.07:51:50.12#ibcon#read 5, iclass 32, count 0 2006.161.07:51:50.12#ibcon#about to read 6, iclass 32, count 0 2006.161.07:51:50.12#ibcon#read 6, iclass 32, count 0 2006.161.07:51:50.12#ibcon#end of sib2, iclass 32, count 0 2006.161.07:51:50.12#ibcon#*after write, iclass 32, count 0 2006.161.07:51:50.12#ibcon#*before return 0, iclass 32, count 0 2006.161.07:51:50.12#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:50.12#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:50.12#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:51:50.12#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:51:50.12$vc4f8/valo=3,672.99 2006.161.07:51:50.12#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.07:51:50.12#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.07:51:50.12#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:50.12#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:50.12#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:50.12#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:50.12#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:51:50.12#ibcon#first serial, iclass 34, count 0 2006.161.07:51:50.12#ibcon#enter sib2, iclass 34, count 0 2006.161.07:51:50.12#ibcon#flushed, iclass 34, count 0 2006.161.07:51:50.12#ibcon#about to write, iclass 34, count 0 2006.161.07:51:50.12#ibcon#wrote, iclass 34, count 0 2006.161.07:51:50.12#ibcon#about to read 3, iclass 34, count 0 2006.161.07:51:50.14#ibcon#read 3, iclass 34, count 0 2006.161.07:51:50.14#ibcon#about to read 4, iclass 34, count 0 2006.161.07:51:50.14#ibcon#read 4, iclass 34, count 0 2006.161.07:51:50.14#ibcon#about to read 5, iclass 34, count 0 2006.161.07:51:50.14#ibcon#read 5, iclass 34, count 0 2006.161.07:51:50.14#ibcon#about to read 6, iclass 34, count 0 2006.161.07:51:50.14#ibcon#read 6, iclass 34, count 0 2006.161.07:51:50.14#ibcon#end of sib2, iclass 34, count 0 2006.161.07:51:50.14#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:51:50.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:51:50.14#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:51:50.14#ibcon#*before write, iclass 34, count 0 2006.161.07:51:50.14#ibcon#enter sib2, iclass 34, count 0 2006.161.07:51:50.14#ibcon#flushed, iclass 34, count 0 2006.161.07:51:50.14#ibcon#about to write, iclass 34, count 0 2006.161.07:51:50.14#ibcon#wrote, iclass 34, count 0 2006.161.07:51:50.14#ibcon#about to read 3, iclass 34, count 0 2006.161.07:51:50.18#ibcon#read 3, iclass 34, count 0 2006.161.07:51:50.18#ibcon#about to read 4, iclass 34, count 0 2006.161.07:51:50.18#ibcon#read 4, iclass 34, count 0 2006.161.07:51:50.18#ibcon#about to read 5, iclass 34, count 0 2006.161.07:51:50.18#ibcon#read 5, iclass 34, count 0 2006.161.07:51:50.18#ibcon#about to read 6, iclass 34, count 0 2006.161.07:51:50.18#ibcon#read 6, iclass 34, count 0 2006.161.07:51:50.18#ibcon#end of sib2, iclass 34, count 0 2006.161.07:51:50.18#ibcon#*after write, iclass 34, count 0 2006.161.07:51:50.18#ibcon#*before return 0, iclass 34, count 0 2006.161.07:51:50.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:50.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:50.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:51:50.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:51:50.18$vc4f8/va=3,6 2006.161.07:51:50.18#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.07:51:50.18#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.07:51:50.18#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:50.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:50.24#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:50.24#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:50.24#ibcon#enter wrdev, iclass 36, count 2 2006.161.07:51:50.24#ibcon#first serial, iclass 36, count 2 2006.161.07:51:50.24#ibcon#enter sib2, iclass 36, count 2 2006.161.07:51:50.24#ibcon#flushed, iclass 36, count 2 2006.161.07:51:50.24#ibcon#about to write, iclass 36, count 2 2006.161.07:51:50.24#ibcon#wrote, iclass 36, count 2 2006.161.07:51:50.24#ibcon#about to read 3, iclass 36, count 2 2006.161.07:51:50.26#ibcon#read 3, iclass 36, count 2 2006.161.07:51:50.26#ibcon#about to read 4, iclass 36, count 2 2006.161.07:51:50.26#ibcon#read 4, iclass 36, count 2 2006.161.07:51:50.26#ibcon#about to read 5, iclass 36, count 2 2006.161.07:51:50.26#ibcon#read 5, iclass 36, count 2 2006.161.07:51:50.26#ibcon#about to read 6, iclass 36, count 2 2006.161.07:51:50.26#ibcon#read 6, iclass 36, count 2 2006.161.07:51:50.26#ibcon#end of sib2, iclass 36, count 2 2006.161.07:51:50.26#ibcon#*mode == 0, iclass 36, count 2 2006.161.07:51:50.26#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.07:51:50.26#ibcon#[25=AT03-06\r\n] 2006.161.07:51:50.26#ibcon#*before write, iclass 36, count 2 2006.161.07:51:50.26#ibcon#enter sib2, iclass 36, count 2 2006.161.07:51:50.26#ibcon#flushed, iclass 36, count 2 2006.161.07:51:50.26#ibcon#about to write, iclass 36, count 2 2006.161.07:51:50.26#ibcon#wrote, iclass 36, count 2 2006.161.07:51:50.26#ibcon#about to read 3, iclass 36, count 2 2006.161.07:51:50.29#ibcon#read 3, iclass 36, count 2 2006.161.07:51:50.29#ibcon#about to read 4, iclass 36, count 2 2006.161.07:51:50.29#ibcon#read 4, iclass 36, count 2 2006.161.07:51:50.29#ibcon#about to read 5, iclass 36, count 2 2006.161.07:51:50.29#ibcon#read 5, iclass 36, count 2 2006.161.07:51:50.29#ibcon#about to read 6, iclass 36, count 2 2006.161.07:51:50.29#ibcon#read 6, iclass 36, count 2 2006.161.07:51:50.29#ibcon#end of sib2, iclass 36, count 2 2006.161.07:51:50.29#ibcon#*after write, iclass 36, count 2 2006.161.07:51:50.29#ibcon#*before return 0, iclass 36, count 2 2006.161.07:51:50.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:50.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:50.29#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.07:51:50.29#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:50.29#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:50.41#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:50.41#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:50.41#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:51:50.41#ibcon#first serial, iclass 36, count 0 2006.161.07:51:50.41#ibcon#enter sib2, iclass 36, count 0 2006.161.07:51:50.41#ibcon#flushed, iclass 36, count 0 2006.161.07:51:50.41#ibcon#about to write, iclass 36, count 0 2006.161.07:51:50.41#ibcon#wrote, iclass 36, count 0 2006.161.07:51:50.41#ibcon#about to read 3, iclass 36, count 0 2006.161.07:51:50.43#ibcon#read 3, iclass 36, count 0 2006.161.07:51:50.43#ibcon#about to read 4, iclass 36, count 0 2006.161.07:51:50.43#ibcon#read 4, iclass 36, count 0 2006.161.07:51:50.43#ibcon#about to read 5, iclass 36, count 0 2006.161.07:51:50.43#ibcon#read 5, iclass 36, count 0 2006.161.07:51:50.43#ibcon#about to read 6, iclass 36, count 0 2006.161.07:51:50.43#ibcon#read 6, iclass 36, count 0 2006.161.07:51:50.43#ibcon#end of sib2, iclass 36, count 0 2006.161.07:51:50.43#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:51:50.43#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:51:50.43#ibcon#[25=USB\r\n] 2006.161.07:51:50.43#ibcon#*before write, iclass 36, count 0 2006.161.07:51:50.43#ibcon#enter sib2, iclass 36, count 0 2006.161.07:51:50.43#ibcon#flushed, iclass 36, count 0 2006.161.07:51:50.43#ibcon#about to write, iclass 36, count 0 2006.161.07:51:50.43#ibcon#wrote, iclass 36, count 0 2006.161.07:51:50.43#ibcon#about to read 3, iclass 36, count 0 2006.161.07:51:50.46#ibcon#read 3, iclass 36, count 0 2006.161.07:51:50.46#ibcon#about to read 4, iclass 36, count 0 2006.161.07:51:50.46#ibcon#read 4, iclass 36, count 0 2006.161.07:51:50.46#ibcon#about to read 5, iclass 36, count 0 2006.161.07:51:50.46#ibcon#read 5, iclass 36, count 0 2006.161.07:51:50.46#ibcon#about to read 6, iclass 36, count 0 2006.161.07:51:50.46#ibcon#read 6, iclass 36, count 0 2006.161.07:51:50.46#ibcon#end of sib2, iclass 36, count 0 2006.161.07:51:50.46#ibcon#*after write, iclass 36, count 0 2006.161.07:51:50.46#ibcon#*before return 0, iclass 36, count 0 2006.161.07:51:50.46#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:50.46#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:50.46#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:51:50.46#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:51:50.46$vc4f8/valo=4,832.99 2006.161.07:51:50.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.07:51:50.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.07:51:50.46#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:50.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:50.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:50.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:50.46#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:51:50.46#ibcon#first serial, iclass 38, count 0 2006.161.07:51:50.46#ibcon#enter sib2, iclass 38, count 0 2006.161.07:51:50.46#ibcon#flushed, iclass 38, count 0 2006.161.07:51:50.46#ibcon#about to write, iclass 38, count 0 2006.161.07:51:50.46#ibcon#wrote, iclass 38, count 0 2006.161.07:51:50.46#ibcon#about to read 3, iclass 38, count 0 2006.161.07:51:50.48#ibcon#read 3, iclass 38, count 0 2006.161.07:51:50.48#ibcon#about to read 4, iclass 38, count 0 2006.161.07:51:50.48#ibcon#read 4, iclass 38, count 0 2006.161.07:51:50.48#ibcon#about to read 5, iclass 38, count 0 2006.161.07:51:50.48#ibcon#read 5, iclass 38, count 0 2006.161.07:51:50.48#ibcon#about to read 6, iclass 38, count 0 2006.161.07:51:50.48#ibcon#read 6, iclass 38, count 0 2006.161.07:51:50.48#ibcon#end of sib2, iclass 38, count 0 2006.161.07:51:50.48#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:51:50.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:51:50.48#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:51:50.48#ibcon#*before write, iclass 38, count 0 2006.161.07:51:50.48#ibcon#enter sib2, iclass 38, count 0 2006.161.07:51:50.48#ibcon#flushed, iclass 38, count 0 2006.161.07:51:50.48#ibcon#about to write, iclass 38, count 0 2006.161.07:51:50.48#ibcon#wrote, iclass 38, count 0 2006.161.07:51:50.48#ibcon#about to read 3, iclass 38, count 0 2006.161.07:51:50.52#ibcon#read 3, iclass 38, count 0 2006.161.07:51:50.52#ibcon#about to read 4, iclass 38, count 0 2006.161.07:51:50.52#ibcon#read 4, iclass 38, count 0 2006.161.07:51:50.52#ibcon#about to read 5, iclass 38, count 0 2006.161.07:51:50.52#ibcon#read 5, iclass 38, count 0 2006.161.07:51:50.52#ibcon#about to read 6, iclass 38, count 0 2006.161.07:51:50.52#ibcon#read 6, iclass 38, count 0 2006.161.07:51:50.52#ibcon#end of sib2, iclass 38, count 0 2006.161.07:51:50.52#ibcon#*after write, iclass 38, count 0 2006.161.07:51:50.52#ibcon#*before return 0, iclass 38, count 0 2006.161.07:51:50.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:50.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:50.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:51:50.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:51:50.52$vc4f8/va=4,7 2006.161.07:51:50.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.07:51:50.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.07:51:50.52#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:50.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:50.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:50.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:50.58#ibcon#enter wrdev, iclass 40, count 2 2006.161.07:51:50.58#ibcon#first serial, iclass 40, count 2 2006.161.07:51:50.58#ibcon#enter sib2, iclass 40, count 2 2006.161.07:51:50.58#ibcon#flushed, iclass 40, count 2 2006.161.07:51:50.58#ibcon#about to write, iclass 40, count 2 2006.161.07:51:50.58#ibcon#wrote, iclass 40, count 2 2006.161.07:51:50.58#ibcon#about to read 3, iclass 40, count 2 2006.161.07:51:50.60#ibcon#read 3, iclass 40, count 2 2006.161.07:51:50.60#ibcon#about to read 4, iclass 40, count 2 2006.161.07:51:50.60#ibcon#read 4, iclass 40, count 2 2006.161.07:51:50.60#ibcon#about to read 5, iclass 40, count 2 2006.161.07:51:50.60#ibcon#read 5, iclass 40, count 2 2006.161.07:51:50.60#ibcon#about to read 6, iclass 40, count 2 2006.161.07:51:50.60#ibcon#read 6, iclass 40, count 2 2006.161.07:51:50.60#ibcon#end of sib2, iclass 40, count 2 2006.161.07:51:50.60#ibcon#*mode == 0, iclass 40, count 2 2006.161.07:51:50.60#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.07:51:50.60#ibcon#[25=AT04-07\r\n] 2006.161.07:51:50.60#ibcon#*before write, iclass 40, count 2 2006.161.07:51:50.60#ibcon#enter sib2, iclass 40, count 2 2006.161.07:51:50.60#ibcon#flushed, iclass 40, count 2 2006.161.07:51:50.60#ibcon#about to write, iclass 40, count 2 2006.161.07:51:50.60#ibcon#wrote, iclass 40, count 2 2006.161.07:51:50.60#ibcon#about to read 3, iclass 40, count 2 2006.161.07:51:50.63#ibcon#read 3, iclass 40, count 2 2006.161.07:51:50.63#ibcon#about to read 4, iclass 40, count 2 2006.161.07:51:50.63#ibcon#read 4, iclass 40, count 2 2006.161.07:51:50.63#ibcon#about to read 5, iclass 40, count 2 2006.161.07:51:50.63#ibcon#read 5, iclass 40, count 2 2006.161.07:51:50.63#ibcon#about to read 6, iclass 40, count 2 2006.161.07:51:50.63#ibcon#read 6, iclass 40, count 2 2006.161.07:51:50.63#ibcon#end of sib2, iclass 40, count 2 2006.161.07:51:50.63#ibcon#*after write, iclass 40, count 2 2006.161.07:51:50.63#ibcon#*before return 0, iclass 40, count 2 2006.161.07:51:50.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:50.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:50.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.07:51:50.63#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:50.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:50.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:50.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:50.75#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:51:50.75#ibcon#first serial, iclass 40, count 0 2006.161.07:51:50.75#ibcon#enter sib2, iclass 40, count 0 2006.161.07:51:50.75#ibcon#flushed, iclass 40, count 0 2006.161.07:51:50.75#ibcon#about to write, iclass 40, count 0 2006.161.07:51:50.75#ibcon#wrote, iclass 40, count 0 2006.161.07:51:50.75#ibcon#about to read 3, iclass 40, count 0 2006.161.07:51:50.77#ibcon#read 3, iclass 40, count 0 2006.161.07:51:50.77#ibcon#about to read 4, iclass 40, count 0 2006.161.07:51:50.77#ibcon#read 4, iclass 40, count 0 2006.161.07:51:50.77#ibcon#about to read 5, iclass 40, count 0 2006.161.07:51:50.77#ibcon#read 5, iclass 40, count 0 2006.161.07:51:50.77#ibcon#about to read 6, iclass 40, count 0 2006.161.07:51:50.77#ibcon#read 6, iclass 40, count 0 2006.161.07:51:50.77#ibcon#end of sib2, iclass 40, count 0 2006.161.07:51:50.77#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:51:50.77#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:51:50.77#ibcon#[25=USB\r\n] 2006.161.07:51:50.77#ibcon#*before write, iclass 40, count 0 2006.161.07:51:50.77#ibcon#enter sib2, iclass 40, count 0 2006.161.07:51:50.77#ibcon#flushed, iclass 40, count 0 2006.161.07:51:50.77#ibcon#about to write, iclass 40, count 0 2006.161.07:51:50.77#ibcon#wrote, iclass 40, count 0 2006.161.07:51:50.77#ibcon#about to read 3, iclass 40, count 0 2006.161.07:51:50.80#ibcon#read 3, iclass 40, count 0 2006.161.07:51:50.80#ibcon#about to read 4, iclass 40, count 0 2006.161.07:51:50.80#ibcon#read 4, iclass 40, count 0 2006.161.07:51:50.80#ibcon#about to read 5, iclass 40, count 0 2006.161.07:51:50.80#ibcon#read 5, iclass 40, count 0 2006.161.07:51:50.80#ibcon#about to read 6, iclass 40, count 0 2006.161.07:51:50.80#ibcon#read 6, iclass 40, count 0 2006.161.07:51:50.80#ibcon#end of sib2, iclass 40, count 0 2006.161.07:51:50.80#ibcon#*after write, iclass 40, count 0 2006.161.07:51:50.80#ibcon#*before return 0, iclass 40, count 0 2006.161.07:51:50.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:50.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:50.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:51:50.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:51:50.80$vc4f8/valo=5,652.99 2006.161.07:51:50.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.07:51:50.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.07:51:50.80#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:50.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:50.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:50.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:50.80#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:51:50.80#ibcon#first serial, iclass 4, count 0 2006.161.07:51:50.80#ibcon#enter sib2, iclass 4, count 0 2006.161.07:51:50.80#ibcon#flushed, iclass 4, count 0 2006.161.07:51:50.80#ibcon#about to write, iclass 4, count 0 2006.161.07:51:50.80#ibcon#wrote, iclass 4, count 0 2006.161.07:51:50.80#ibcon#about to read 3, iclass 4, count 0 2006.161.07:51:50.82#ibcon#read 3, iclass 4, count 0 2006.161.07:51:50.82#ibcon#about to read 4, iclass 4, count 0 2006.161.07:51:50.82#ibcon#read 4, iclass 4, count 0 2006.161.07:51:50.82#ibcon#about to read 5, iclass 4, count 0 2006.161.07:51:50.82#ibcon#read 5, iclass 4, count 0 2006.161.07:51:50.82#ibcon#about to read 6, iclass 4, count 0 2006.161.07:51:50.82#ibcon#read 6, iclass 4, count 0 2006.161.07:51:50.82#ibcon#end of sib2, iclass 4, count 0 2006.161.07:51:50.82#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:51:50.82#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:51:50.82#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:51:50.82#ibcon#*before write, iclass 4, count 0 2006.161.07:51:50.82#ibcon#enter sib2, iclass 4, count 0 2006.161.07:51:50.82#ibcon#flushed, iclass 4, count 0 2006.161.07:51:50.82#ibcon#about to write, iclass 4, count 0 2006.161.07:51:50.82#ibcon#wrote, iclass 4, count 0 2006.161.07:51:50.82#ibcon#about to read 3, iclass 4, count 0 2006.161.07:51:50.86#ibcon#read 3, iclass 4, count 0 2006.161.07:51:50.86#ibcon#about to read 4, iclass 4, count 0 2006.161.07:51:50.86#ibcon#read 4, iclass 4, count 0 2006.161.07:51:50.86#ibcon#about to read 5, iclass 4, count 0 2006.161.07:51:50.86#ibcon#read 5, iclass 4, count 0 2006.161.07:51:50.86#ibcon#about to read 6, iclass 4, count 0 2006.161.07:51:50.86#ibcon#read 6, iclass 4, count 0 2006.161.07:51:50.86#ibcon#end of sib2, iclass 4, count 0 2006.161.07:51:50.86#ibcon#*after write, iclass 4, count 0 2006.161.07:51:50.86#ibcon#*before return 0, iclass 4, count 0 2006.161.07:51:50.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:50.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:50.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:51:50.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:51:50.86$vc4f8/va=5,7 2006.161.07:51:50.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.07:51:50.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.07:51:50.86#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:50.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:50.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:50.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:50.92#ibcon#enter wrdev, iclass 6, count 2 2006.161.07:51:50.92#ibcon#first serial, iclass 6, count 2 2006.161.07:51:50.92#ibcon#enter sib2, iclass 6, count 2 2006.161.07:51:50.92#ibcon#flushed, iclass 6, count 2 2006.161.07:51:50.92#ibcon#about to write, iclass 6, count 2 2006.161.07:51:50.92#ibcon#wrote, iclass 6, count 2 2006.161.07:51:50.92#ibcon#about to read 3, iclass 6, count 2 2006.161.07:51:50.94#ibcon#read 3, iclass 6, count 2 2006.161.07:51:50.94#ibcon#about to read 4, iclass 6, count 2 2006.161.07:51:50.94#ibcon#read 4, iclass 6, count 2 2006.161.07:51:50.94#ibcon#about to read 5, iclass 6, count 2 2006.161.07:51:50.94#ibcon#read 5, iclass 6, count 2 2006.161.07:51:50.94#ibcon#about to read 6, iclass 6, count 2 2006.161.07:51:50.94#ibcon#read 6, iclass 6, count 2 2006.161.07:51:50.94#ibcon#end of sib2, iclass 6, count 2 2006.161.07:51:50.94#ibcon#*mode == 0, iclass 6, count 2 2006.161.07:51:50.94#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.07:51:50.94#ibcon#[25=AT05-07\r\n] 2006.161.07:51:50.94#ibcon#*before write, iclass 6, count 2 2006.161.07:51:50.94#ibcon#enter sib2, iclass 6, count 2 2006.161.07:51:50.94#ibcon#flushed, iclass 6, count 2 2006.161.07:51:50.94#ibcon#about to write, iclass 6, count 2 2006.161.07:51:50.94#ibcon#wrote, iclass 6, count 2 2006.161.07:51:50.94#ibcon#about to read 3, iclass 6, count 2 2006.161.07:51:50.97#ibcon#read 3, iclass 6, count 2 2006.161.07:51:50.97#ibcon#about to read 4, iclass 6, count 2 2006.161.07:51:50.97#ibcon#read 4, iclass 6, count 2 2006.161.07:51:50.97#ibcon#about to read 5, iclass 6, count 2 2006.161.07:51:50.97#ibcon#read 5, iclass 6, count 2 2006.161.07:51:50.97#ibcon#about to read 6, iclass 6, count 2 2006.161.07:51:50.97#ibcon#read 6, iclass 6, count 2 2006.161.07:51:50.97#ibcon#end of sib2, iclass 6, count 2 2006.161.07:51:50.97#ibcon#*after write, iclass 6, count 2 2006.161.07:51:50.97#ibcon#*before return 0, iclass 6, count 2 2006.161.07:51:50.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:50.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:50.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.07:51:50.97#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:50.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:51.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:51.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:51.09#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:51:51.09#ibcon#first serial, iclass 6, count 0 2006.161.07:51:51.09#ibcon#enter sib2, iclass 6, count 0 2006.161.07:51:51.09#ibcon#flushed, iclass 6, count 0 2006.161.07:51:51.09#ibcon#about to write, iclass 6, count 0 2006.161.07:51:51.09#ibcon#wrote, iclass 6, count 0 2006.161.07:51:51.09#ibcon#about to read 3, iclass 6, count 0 2006.161.07:51:51.12#ibcon#read 3, iclass 6, count 0 2006.161.07:51:51.12#ibcon#about to read 4, iclass 6, count 0 2006.161.07:51:51.12#ibcon#read 4, iclass 6, count 0 2006.161.07:51:51.12#ibcon#about to read 5, iclass 6, count 0 2006.161.07:51:51.12#ibcon#read 5, iclass 6, count 0 2006.161.07:51:51.12#ibcon#about to read 6, iclass 6, count 0 2006.161.07:51:51.12#ibcon#read 6, iclass 6, count 0 2006.161.07:51:51.12#ibcon#end of sib2, iclass 6, count 0 2006.161.07:51:51.12#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:51:51.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:51:51.12#ibcon#[25=USB\r\n] 2006.161.07:51:51.12#ibcon#*before write, iclass 6, count 0 2006.161.07:51:51.12#ibcon#enter sib2, iclass 6, count 0 2006.161.07:51:51.13#ibcon#flushed, iclass 6, count 0 2006.161.07:51:51.13#ibcon#about to write, iclass 6, count 0 2006.161.07:51:51.13#ibcon#wrote, iclass 6, count 0 2006.161.07:51:51.13#ibcon#about to read 3, iclass 6, count 0 2006.161.07:51:51.16#ibcon#read 3, iclass 6, count 0 2006.161.07:51:51.16#ibcon#about to read 4, iclass 6, count 0 2006.161.07:51:51.16#ibcon#read 4, iclass 6, count 0 2006.161.07:51:51.16#ibcon#about to read 5, iclass 6, count 0 2006.161.07:51:51.16#ibcon#read 5, iclass 6, count 0 2006.161.07:51:51.16#ibcon#about to read 6, iclass 6, count 0 2006.161.07:51:51.16#ibcon#read 6, iclass 6, count 0 2006.161.07:51:51.16#ibcon#end of sib2, iclass 6, count 0 2006.161.07:51:51.16#ibcon#*after write, iclass 6, count 0 2006.161.07:51:51.16#ibcon#*before return 0, iclass 6, count 0 2006.161.07:51:51.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:51.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:51.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:51:51.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:51:51.16$vc4f8/valo=6,772.99 2006.161.07:51:51.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:51:51.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:51:51.16#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:51.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:51.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:51.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:51.16#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:51:51.16#ibcon#first serial, iclass 10, count 0 2006.161.07:51:51.16#ibcon#enter sib2, iclass 10, count 0 2006.161.07:51:51.16#ibcon#flushed, iclass 10, count 0 2006.161.07:51:51.16#ibcon#about to write, iclass 10, count 0 2006.161.07:51:51.16#ibcon#wrote, iclass 10, count 0 2006.161.07:51:51.16#ibcon#about to read 3, iclass 10, count 0 2006.161.07:51:51.18#ibcon#read 3, iclass 10, count 0 2006.161.07:51:51.18#ibcon#about to read 4, iclass 10, count 0 2006.161.07:51:51.18#ibcon#read 4, iclass 10, count 0 2006.161.07:51:51.18#ibcon#about to read 5, iclass 10, count 0 2006.161.07:51:51.18#ibcon#read 5, iclass 10, count 0 2006.161.07:51:51.18#ibcon#about to read 6, iclass 10, count 0 2006.161.07:51:51.18#ibcon#read 6, iclass 10, count 0 2006.161.07:51:51.18#ibcon#end of sib2, iclass 10, count 0 2006.161.07:51:51.18#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:51:51.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:51:51.18#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:51:51.18#ibcon#*before write, iclass 10, count 0 2006.161.07:51:51.18#ibcon#enter sib2, iclass 10, count 0 2006.161.07:51:51.18#ibcon#flushed, iclass 10, count 0 2006.161.07:51:51.18#ibcon#about to write, iclass 10, count 0 2006.161.07:51:51.18#ibcon#wrote, iclass 10, count 0 2006.161.07:51:51.18#ibcon#about to read 3, iclass 10, count 0 2006.161.07:51:51.22#ibcon#read 3, iclass 10, count 0 2006.161.07:51:51.22#ibcon#about to read 4, iclass 10, count 0 2006.161.07:51:51.22#ibcon#read 4, iclass 10, count 0 2006.161.07:51:51.22#ibcon#about to read 5, iclass 10, count 0 2006.161.07:51:51.22#ibcon#read 5, iclass 10, count 0 2006.161.07:51:51.22#ibcon#about to read 6, iclass 10, count 0 2006.161.07:51:51.22#ibcon#read 6, iclass 10, count 0 2006.161.07:51:51.22#ibcon#end of sib2, iclass 10, count 0 2006.161.07:51:51.22#ibcon#*after write, iclass 10, count 0 2006.161.07:51:51.22#ibcon#*before return 0, iclass 10, count 0 2006.161.07:51:51.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:51.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:51.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:51:51.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:51:51.22$vc4f8/va=6,6 2006.161.07:51:51.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.07:51:51.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.07:51:51.22#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:51.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:51.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:51.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:51.28#ibcon#enter wrdev, iclass 12, count 2 2006.161.07:51:51.28#ibcon#first serial, iclass 12, count 2 2006.161.07:51:51.28#ibcon#enter sib2, iclass 12, count 2 2006.161.07:51:51.28#ibcon#flushed, iclass 12, count 2 2006.161.07:51:51.28#ibcon#about to write, iclass 12, count 2 2006.161.07:51:51.28#ibcon#wrote, iclass 12, count 2 2006.161.07:51:51.28#ibcon#about to read 3, iclass 12, count 2 2006.161.07:51:51.30#ibcon#read 3, iclass 12, count 2 2006.161.07:51:51.30#ibcon#about to read 4, iclass 12, count 2 2006.161.07:51:51.30#ibcon#read 4, iclass 12, count 2 2006.161.07:51:51.30#ibcon#about to read 5, iclass 12, count 2 2006.161.07:51:51.30#ibcon#read 5, iclass 12, count 2 2006.161.07:51:51.30#ibcon#about to read 6, iclass 12, count 2 2006.161.07:51:51.30#ibcon#read 6, iclass 12, count 2 2006.161.07:51:51.30#ibcon#end of sib2, iclass 12, count 2 2006.161.07:51:51.30#ibcon#*mode == 0, iclass 12, count 2 2006.161.07:51:51.30#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.07:51:51.30#ibcon#[25=AT06-06\r\n] 2006.161.07:51:51.30#ibcon#*before write, iclass 12, count 2 2006.161.07:51:51.30#ibcon#enter sib2, iclass 12, count 2 2006.161.07:51:51.30#ibcon#flushed, iclass 12, count 2 2006.161.07:51:51.30#ibcon#about to write, iclass 12, count 2 2006.161.07:51:51.30#ibcon#wrote, iclass 12, count 2 2006.161.07:51:51.30#ibcon#about to read 3, iclass 12, count 2 2006.161.07:51:51.33#ibcon#read 3, iclass 12, count 2 2006.161.07:51:51.33#ibcon#about to read 4, iclass 12, count 2 2006.161.07:51:51.33#ibcon#read 4, iclass 12, count 2 2006.161.07:51:51.33#ibcon#about to read 5, iclass 12, count 2 2006.161.07:51:51.33#ibcon#read 5, iclass 12, count 2 2006.161.07:51:51.33#ibcon#about to read 6, iclass 12, count 2 2006.161.07:51:51.33#ibcon#read 6, iclass 12, count 2 2006.161.07:51:51.33#ibcon#end of sib2, iclass 12, count 2 2006.161.07:51:51.33#ibcon#*after write, iclass 12, count 2 2006.161.07:51:51.33#ibcon#*before return 0, iclass 12, count 2 2006.161.07:51:51.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:51.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:51.33#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.07:51:51.33#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:51.33#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:51:51.45#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:51:51.45#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:51:51.45#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:51:51.45#ibcon#first serial, iclass 12, count 0 2006.161.07:51:51.45#ibcon#enter sib2, iclass 12, count 0 2006.161.07:51:51.45#ibcon#flushed, iclass 12, count 0 2006.161.07:51:51.45#ibcon#about to write, iclass 12, count 0 2006.161.07:51:51.45#ibcon#wrote, iclass 12, count 0 2006.161.07:51:51.45#ibcon#about to read 3, iclass 12, count 0 2006.161.07:51:51.47#ibcon#read 3, iclass 12, count 0 2006.161.07:51:51.47#ibcon#about to read 4, iclass 12, count 0 2006.161.07:51:51.47#ibcon#read 4, iclass 12, count 0 2006.161.07:51:51.47#ibcon#about to read 5, iclass 12, count 0 2006.161.07:51:51.47#ibcon#read 5, iclass 12, count 0 2006.161.07:51:51.47#ibcon#about to read 6, iclass 12, count 0 2006.161.07:51:51.47#ibcon#read 6, iclass 12, count 0 2006.161.07:51:51.47#ibcon#end of sib2, iclass 12, count 0 2006.161.07:51:51.47#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:51:51.47#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:51:51.47#ibcon#[25=USB\r\n] 2006.161.07:51:51.47#ibcon#*before write, iclass 12, count 0 2006.161.07:51:51.47#ibcon#enter sib2, iclass 12, count 0 2006.161.07:51:51.47#ibcon#flushed, iclass 12, count 0 2006.161.07:51:51.47#ibcon#about to write, iclass 12, count 0 2006.161.07:51:51.47#ibcon#wrote, iclass 12, count 0 2006.161.07:51:51.47#ibcon#about to read 3, iclass 12, count 0 2006.161.07:51:51.50#ibcon#read 3, iclass 12, count 0 2006.161.07:51:51.50#ibcon#about to read 4, iclass 12, count 0 2006.161.07:51:51.50#ibcon#read 4, iclass 12, count 0 2006.161.07:51:51.50#ibcon#about to read 5, iclass 12, count 0 2006.161.07:51:51.50#ibcon#read 5, iclass 12, count 0 2006.161.07:51:51.50#ibcon#about to read 6, iclass 12, count 0 2006.161.07:51:51.50#ibcon#read 6, iclass 12, count 0 2006.161.07:51:51.50#ibcon#end of sib2, iclass 12, count 0 2006.161.07:51:51.50#ibcon#*after write, iclass 12, count 0 2006.161.07:51:51.50#ibcon#*before return 0, iclass 12, count 0 2006.161.07:51:51.50#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:51:51.50#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.07:51:51.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:51:51.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:51:51.50$vc4f8/valo=7,832.99 2006.161.07:51:51.50#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.07:51:51.50#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.07:51:51.50#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:51.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:51:51.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:51:51.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:51:51.50#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:51:51.50#ibcon#first serial, iclass 14, count 0 2006.161.07:51:51.50#ibcon#enter sib2, iclass 14, count 0 2006.161.07:51:51.50#ibcon#flushed, iclass 14, count 0 2006.161.07:51:51.50#ibcon#about to write, iclass 14, count 0 2006.161.07:51:51.50#ibcon#wrote, iclass 14, count 0 2006.161.07:51:51.50#ibcon#about to read 3, iclass 14, count 0 2006.161.07:51:51.52#ibcon#read 3, iclass 14, count 0 2006.161.07:51:51.52#ibcon#about to read 4, iclass 14, count 0 2006.161.07:51:51.52#ibcon#read 4, iclass 14, count 0 2006.161.07:51:51.52#ibcon#about to read 5, iclass 14, count 0 2006.161.07:51:51.52#ibcon#read 5, iclass 14, count 0 2006.161.07:51:51.52#ibcon#about to read 6, iclass 14, count 0 2006.161.07:51:51.52#ibcon#read 6, iclass 14, count 0 2006.161.07:51:51.52#ibcon#end of sib2, iclass 14, count 0 2006.161.07:51:51.52#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:51:51.52#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:51:51.52#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:51:51.52#ibcon#*before write, iclass 14, count 0 2006.161.07:51:51.52#ibcon#enter sib2, iclass 14, count 0 2006.161.07:51:51.52#ibcon#flushed, iclass 14, count 0 2006.161.07:51:51.52#ibcon#about to write, iclass 14, count 0 2006.161.07:51:51.52#ibcon#wrote, iclass 14, count 0 2006.161.07:51:51.52#ibcon#about to read 3, iclass 14, count 0 2006.161.07:51:51.56#ibcon#read 3, iclass 14, count 0 2006.161.07:51:51.56#ibcon#about to read 4, iclass 14, count 0 2006.161.07:51:51.56#ibcon#read 4, iclass 14, count 0 2006.161.07:51:51.56#ibcon#about to read 5, iclass 14, count 0 2006.161.07:51:51.56#ibcon#read 5, iclass 14, count 0 2006.161.07:51:51.56#ibcon#about to read 6, iclass 14, count 0 2006.161.07:51:51.56#ibcon#read 6, iclass 14, count 0 2006.161.07:51:51.56#ibcon#end of sib2, iclass 14, count 0 2006.161.07:51:51.56#ibcon#*after write, iclass 14, count 0 2006.161.07:51:51.56#ibcon#*before return 0, iclass 14, count 0 2006.161.07:51:51.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:51:51.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.07:51:51.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:51:51.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:51:51.56$vc4f8/va=7,6 2006.161.07:51:51.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.07:51:51.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.07:51:51.56#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:51.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:51:51.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:51:51.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:51:51.62#ibcon#enter wrdev, iclass 16, count 2 2006.161.07:51:51.62#ibcon#first serial, iclass 16, count 2 2006.161.07:51:51.62#ibcon#enter sib2, iclass 16, count 2 2006.161.07:51:51.62#ibcon#flushed, iclass 16, count 2 2006.161.07:51:51.62#ibcon#about to write, iclass 16, count 2 2006.161.07:51:51.62#ibcon#wrote, iclass 16, count 2 2006.161.07:51:51.62#ibcon#about to read 3, iclass 16, count 2 2006.161.07:51:51.64#ibcon#read 3, iclass 16, count 2 2006.161.07:51:51.64#ibcon#about to read 4, iclass 16, count 2 2006.161.07:51:51.64#ibcon#read 4, iclass 16, count 2 2006.161.07:51:51.64#ibcon#about to read 5, iclass 16, count 2 2006.161.07:51:51.64#ibcon#read 5, iclass 16, count 2 2006.161.07:51:51.64#ibcon#about to read 6, iclass 16, count 2 2006.161.07:51:51.64#ibcon#read 6, iclass 16, count 2 2006.161.07:51:51.64#ibcon#end of sib2, iclass 16, count 2 2006.161.07:51:51.64#ibcon#*mode == 0, iclass 16, count 2 2006.161.07:51:51.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.07:51:51.64#ibcon#[25=AT07-06\r\n] 2006.161.07:51:51.64#ibcon#*before write, iclass 16, count 2 2006.161.07:51:51.64#ibcon#enter sib2, iclass 16, count 2 2006.161.07:51:51.64#ibcon#flushed, iclass 16, count 2 2006.161.07:51:51.64#ibcon#about to write, iclass 16, count 2 2006.161.07:51:51.64#ibcon#wrote, iclass 16, count 2 2006.161.07:51:51.64#ibcon#about to read 3, iclass 16, count 2 2006.161.07:51:51.67#ibcon#read 3, iclass 16, count 2 2006.161.07:51:51.67#ibcon#about to read 4, iclass 16, count 2 2006.161.07:51:51.67#ibcon#read 4, iclass 16, count 2 2006.161.07:51:51.67#ibcon#about to read 5, iclass 16, count 2 2006.161.07:51:51.67#ibcon#read 5, iclass 16, count 2 2006.161.07:51:51.67#ibcon#about to read 6, iclass 16, count 2 2006.161.07:51:51.67#ibcon#read 6, iclass 16, count 2 2006.161.07:51:51.67#ibcon#end of sib2, iclass 16, count 2 2006.161.07:51:51.67#ibcon#*after write, iclass 16, count 2 2006.161.07:51:51.67#ibcon#*before return 0, iclass 16, count 2 2006.161.07:51:51.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:51:51.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.07:51:51.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.07:51:51.67#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:51.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:51:51.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:51:51.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:51:51.79#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:51:51.79#ibcon#first serial, iclass 16, count 0 2006.161.07:51:51.79#ibcon#enter sib2, iclass 16, count 0 2006.161.07:51:51.79#ibcon#flushed, iclass 16, count 0 2006.161.07:51:51.79#ibcon#about to write, iclass 16, count 0 2006.161.07:51:51.79#ibcon#wrote, iclass 16, count 0 2006.161.07:51:51.79#ibcon#about to read 3, iclass 16, count 0 2006.161.07:51:51.81#ibcon#read 3, iclass 16, count 0 2006.161.07:51:51.81#ibcon#about to read 4, iclass 16, count 0 2006.161.07:51:51.81#ibcon#read 4, iclass 16, count 0 2006.161.07:51:51.81#ibcon#about to read 5, iclass 16, count 0 2006.161.07:51:51.81#ibcon#read 5, iclass 16, count 0 2006.161.07:51:51.81#ibcon#about to read 6, iclass 16, count 0 2006.161.07:51:51.81#ibcon#read 6, iclass 16, count 0 2006.161.07:51:51.81#ibcon#end of sib2, iclass 16, count 0 2006.161.07:51:51.81#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:51:51.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:51:51.81#ibcon#[25=USB\r\n] 2006.161.07:51:51.81#ibcon#*before write, iclass 16, count 0 2006.161.07:51:51.81#ibcon#enter sib2, iclass 16, count 0 2006.161.07:51:51.81#ibcon#flushed, iclass 16, count 0 2006.161.07:51:51.81#ibcon#about to write, iclass 16, count 0 2006.161.07:51:51.81#ibcon#wrote, iclass 16, count 0 2006.161.07:51:51.81#ibcon#about to read 3, iclass 16, count 0 2006.161.07:51:51.84#ibcon#read 3, iclass 16, count 0 2006.161.07:51:51.84#ibcon#about to read 4, iclass 16, count 0 2006.161.07:51:51.84#ibcon#read 4, iclass 16, count 0 2006.161.07:51:51.84#ibcon#about to read 5, iclass 16, count 0 2006.161.07:51:51.84#ibcon#read 5, iclass 16, count 0 2006.161.07:51:51.84#ibcon#about to read 6, iclass 16, count 0 2006.161.07:51:51.84#ibcon#read 6, iclass 16, count 0 2006.161.07:51:51.84#ibcon#end of sib2, iclass 16, count 0 2006.161.07:51:51.84#ibcon#*after write, iclass 16, count 0 2006.161.07:51:51.84#ibcon#*before return 0, iclass 16, count 0 2006.161.07:51:51.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:51:51.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.07:51:51.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:51:51.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:51:51.84$vc4f8/valo=8,852.99 2006.161.07:51:51.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.07:51:51.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.07:51:51.84#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:51.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:51:51.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:51:51.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:51:51.84#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:51:51.84#ibcon#first serial, iclass 18, count 0 2006.161.07:51:51.84#ibcon#enter sib2, iclass 18, count 0 2006.161.07:51:51.84#ibcon#flushed, iclass 18, count 0 2006.161.07:51:51.84#ibcon#about to write, iclass 18, count 0 2006.161.07:51:51.84#ibcon#wrote, iclass 18, count 0 2006.161.07:51:51.84#ibcon#about to read 3, iclass 18, count 0 2006.161.07:51:51.86#ibcon#read 3, iclass 18, count 0 2006.161.07:51:51.86#ibcon#about to read 4, iclass 18, count 0 2006.161.07:51:51.86#ibcon#read 4, iclass 18, count 0 2006.161.07:51:51.86#ibcon#about to read 5, iclass 18, count 0 2006.161.07:51:51.86#ibcon#read 5, iclass 18, count 0 2006.161.07:51:51.86#ibcon#about to read 6, iclass 18, count 0 2006.161.07:51:51.86#ibcon#read 6, iclass 18, count 0 2006.161.07:51:51.86#ibcon#end of sib2, iclass 18, count 0 2006.161.07:51:51.86#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:51:51.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:51:51.86#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:51:51.86#ibcon#*before write, iclass 18, count 0 2006.161.07:51:51.86#ibcon#enter sib2, iclass 18, count 0 2006.161.07:51:51.86#ibcon#flushed, iclass 18, count 0 2006.161.07:51:51.86#ibcon#about to write, iclass 18, count 0 2006.161.07:51:51.86#ibcon#wrote, iclass 18, count 0 2006.161.07:51:51.86#ibcon#about to read 3, iclass 18, count 0 2006.161.07:51:51.90#ibcon#read 3, iclass 18, count 0 2006.161.07:51:51.90#ibcon#about to read 4, iclass 18, count 0 2006.161.07:51:51.90#ibcon#read 4, iclass 18, count 0 2006.161.07:51:51.90#ibcon#about to read 5, iclass 18, count 0 2006.161.07:51:51.90#ibcon#read 5, iclass 18, count 0 2006.161.07:51:51.90#ibcon#about to read 6, iclass 18, count 0 2006.161.07:51:51.90#ibcon#read 6, iclass 18, count 0 2006.161.07:51:51.90#ibcon#end of sib2, iclass 18, count 0 2006.161.07:51:51.90#ibcon#*after write, iclass 18, count 0 2006.161.07:51:51.90#ibcon#*before return 0, iclass 18, count 0 2006.161.07:51:51.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:51:51.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.07:51:51.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:51:51.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:51:51.90$vc4f8/va=8,7 2006.161.07:51:51.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.07:51:51.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.07:51:51.90#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:51.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:51:51.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:51:51.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:51:51.96#ibcon#enter wrdev, iclass 20, count 2 2006.161.07:51:51.96#ibcon#first serial, iclass 20, count 2 2006.161.07:51:51.96#ibcon#enter sib2, iclass 20, count 2 2006.161.07:51:51.96#ibcon#flushed, iclass 20, count 2 2006.161.07:51:51.96#ibcon#about to write, iclass 20, count 2 2006.161.07:51:51.96#ibcon#wrote, iclass 20, count 2 2006.161.07:51:51.96#ibcon#about to read 3, iclass 20, count 2 2006.161.07:51:51.98#ibcon#read 3, iclass 20, count 2 2006.161.07:51:51.98#ibcon#about to read 4, iclass 20, count 2 2006.161.07:51:51.98#ibcon#read 4, iclass 20, count 2 2006.161.07:51:51.98#ibcon#about to read 5, iclass 20, count 2 2006.161.07:51:51.98#ibcon#read 5, iclass 20, count 2 2006.161.07:51:51.98#ibcon#about to read 6, iclass 20, count 2 2006.161.07:51:51.98#ibcon#read 6, iclass 20, count 2 2006.161.07:51:51.98#ibcon#end of sib2, iclass 20, count 2 2006.161.07:51:51.98#ibcon#*mode == 0, iclass 20, count 2 2006.161.07:51:51.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.07:51:51.98#ibcon#[25=AT08-07\r\n] 2006.161.07:51:51.98#ibcon#*before write, iclass 20, count 2 2006.161.07:51:51.98#ibcon#enter sib2, iclass 20, count 2 2006.161.07:51:51.98#ibcon#flushed, iclass 20, count 2 2006.161.07:51:51.98#ibcon#about to write, iclass 20, count 2 2006.161.07:51:51.98#ibcon#wrote, iclass 20, count 2 2006.161.07:51:51.98#ibcon#about to read 3, iclass 20, count 2 2006.161.07:51:52.01#ibcon#read 3, iclass 20, count 2 2006.161.07:51:52.01#ibcon#about to read 4, iclass 20, count 2 2006.161.07:51:52.01#ibcon#read 4, iclass 20, count 2 2006.161.07:51:52.01#ibcon#about to read 5, iclass 20, count 2 2006.161.07:51:52.01#ibcon#read 5, iclass 20, count 2 2006.161.07:51:52.01#ibcon#about to read 6, iclass 20, count 2 2006.161.07:51:52.01#ibcon#read 6, iclass 20, count 2 2006.161.07:51:52.01#ibcon#end of sib2, iclass 20, count 2 2006.161.07:51:52.01#ibcon#*after write, iclass 20, count 2 2006.161.07:51:52.01#ibcon#*before return 0, iclass 20, count 2 2006.161.07:51:52.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:51:52.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.07:51:52.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.07:51:52.01#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:52.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:51:52.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:51:52.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:51:52.13#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:51:52.13#ibcon#first serial, iclass 20, count 0 2006.161.07:51:52.13#ibcon#enter sib2, iclass 20, count 0 2006.161.07:51:52.13#ibcon#flushed, iclass 20, count 0 2006.161.07:51:52.13#ibcon#about to write, iclass 20, count 0 2006.161.07:51:52.13#ibcon#wrote, iclass 20, count 0 2006.161.07:51:52.13#ibcon#about to read 3, iclass 20, count 0 2006.161.07:51:52.15#ibcon#read 3, iclass 20, count 0 2006.161.07:51:52.15#ibcon#about to read 4, iclass 20, count 0 2006.161.07:51:52.15#ibcon#read 4, iclass 20, count 0 2006.161.07:51:52.15#ibcon#about to read 5, iclass 20, count 0 2006.161.07:51:52.15#ibcon#read 5, iclass 20, count 0 2006.161.07:51:52.15#ibcon#about to read 6, iclass 20, count 0 2006.161.07:51:52.15#ibcon#read 6, iclass 20, count 0 2006.161.07:51:52.15#ibcon#end of sib2, iclass 20, count 0 2006.161.07:51:52.15#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:51:52.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:51:52.15#ibcon#[25=USB\r\n] 2006.161.07:51:52.15#ibcon#*before write, iclass 20, count 0 2006.161.07:51:52.15#ibcon#enter sib2, iclass 20, count 0 2006.161.07:51:52.15#ibcon#flushed, iclass 20, count 0 2006.161.07:51:52.15#ibcon#about to write, iclass 20, count 0 2006.161.07:51:52.15#ibcon#wrote, iclass 20, count 0 2006.161.07:51:52.15#ibcon#about to read 3, iclass 20, count 0 2006.161.07:51:52.18#ibcon#read 3, iclass 20, count 0 2006.161.07:51:52.18#ibcon#about to read 4, iclass 20, count 0 2006.161.07:51:52.18#ibcon#read 4, iclass 20, count 0 2006.161.07:51:52.18#ibcon#about to read 5, iclass 20, count 0 2006.161.07:51:52.18#ibcon#read 5, iclass 20, count 0 2006.161.07:51:52.18#ibcon#about to read 6, iclass 20, count 0 2006.161.07:51:52.18#ibcon#read 6, iclass 20, count 0 2006.161.07:51:52.18#ibcon#end of sib2, iclass 20, count 0 2006.161.07:51:52.18#ibcon#*after write, iclass 20, count 0 2006.161.07:51:52.18#ibcon#*before return 0, iclass 20, count 0 2006.161.07:51:52.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:51:52.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.07:51:52.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:51:52.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:51:52.18$vc4f8/vblo=1,632.99 2006.161.07:51:52.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.07:51:52.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.07:51:52.18#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:52.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:51:52.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:51:52.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:51:52.18#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:51:52.18#ibcon#first serial, iclass 22, count 0 2006.161.07:51:52.18#ibcon#enter sib2, iclass 22, count 0 2006.161.07:51:52.18#ibcon#flushed, iclass 22, count 0 2006.161.07:51:52.18#ibcon#about to write, iclass 22, count 0 2006.161.07:51:52.18#ibcon#wrote, iclass 22, count 0 2006.161.07:51:52.18#ibcon#about to read 3, iclass 22, count 0 2006.161.07:51:52.20#ibcon#read 3, iclass 22, count 0 2006.161.07:51:52.20#ibcon#about to read 4, iclass 22, count 0 2006.161.07:51:52.20#ibcon#read 4, iclass 22, count 0 2006.161.07:51:52.20#ibcon#about to read 5, iclass 22, count 0 2006.161.07:51:52.20#ibcon#read 5, iclass 22, count 0 2006.161.07:51:52.20#ibcon#about to read 6, iclass 22, count 0 2006.161.07:51:52.20#ibcon#read 6, iclass 22, count 0 2006.161.07:51:52.20#ibcon#end of sib2, iclass 22, count 0 2006.161.07:51:52.20#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:51:52.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:51:52.20#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:51:52.20#ibcon#*before write, iclass 22, count 0 2006.161.07:51:52.20#ibcon#enter sib2, iclass 22, count 0 2006.161.07:51:52.20#ibcon#flushed, iclass 22, count 0 2006.161.07:51:52.20#ibcon#about to write, iclass 22, count 0 2006.161.07:51:52.20#ibcon#wrote, iclass 22, count 0 2006.161.07:51:52.20#ibcon#about to read 3, iclass 22, count 0 2006.161.07:51:52.24#ibcon#read 3, iclass 22, count 0 2006.161.07:51:52.24#ibcon#about to read 4, iclass 22, count 0 2006.161.07:51:52.24#ibcon#read 4, iclass 22, count 0 2006.161.07:51:52.24#ibcon#about to read 5, iclass 22, count 0 2006.161.07:51:52.24#ibcon#read 5, iclass 22, count 0 2006.161.07:51:52.24#ibcon#about to read 6, iclass 22, count 0 2006.161.07:51:52.24#ibcon#read 6, iclass 22, count 0 2006.161.07:51:52.24#ibcon#end of sib2, iclass 22, count 0 2006.161.07:51:52.24#ibcon#*after write, iclass 22, count 0 2006.161.07:51:52.24#ibcon#*before return 0, iclass 22, count 0 2006.161.07:51:52.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:51:52.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.07:51:52.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:51:52.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:51:52.24$vc4f8/vb=1,4 2006.161.07:51:52.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.07:51:52.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.07:51:52.24#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:52.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:51:52.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:51:52.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:51:52.24#ibcon#enter wrdev, iclass 24, count 2 2006.161.07:51:52.24#ibcon#first serial, iclass 24, count 2 2006.161.07:51:52.24#ibcon#enter sib2, iclass 24, count 2 2006.161.07:51:52.24#ibcon#flushed, iclass 24, count 2 2006.161.07:51:52.24#ibcon#about to write, iclass 24, count 2 2006.161.07:51:52.24#ibcon#wrote, iclass 24, count 2 2006.161.07:51:52.24#ibcon#about to read 3, iclass 24, count 2 2006.161.07:51:52.26#ibcon#read 3, iclass 24, count 2 2006.161.07:51:52.26#ibcon#about to read 4, iclass 24, count 2 2006.161.07:51:52.26#ibcon#read 4, iclass 24, count 2 2006.161.07:51:52.26#ibcon#about to read 5, iclass 24, count 2 2006.161.07:51:52.26#ibcon#read 5, iclass 24, count 2 2006.161.07:51:52.26#ibcon#about to read 6, iclass 24, count 2 2006.161.07:51:52.26#ibcon#read 6, iclass 24, count 2 2006.161.07:51:52.26#ibcon#end of sib2, iclass 24, count 2 2006.161.07:51:52.26#ibcon#*mode == 0, iclass 24, count 2 2006.161.07:51:52.26#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.07:51:52.26#ibcon#[27=AT01-04\r\n] 2006.161.07:51:52.26#ibcon#*before write, iclass 24, count 2 2006.161.07:51:52.26#ibcon#enter sib2, iclass 24, count 2 2006.161.07:51:52.26#ibcon#flushed, iclass 24, count 2 2006.161.07:51:52.26#ibcon#about to write, iclass 24, count 2 2006.161.07:51:52.26#ibcon#wrote, iclass 24, count 2 2006.161.07:51:52.26#ibcon#about to read 3, iclass 24, count 2 2006.161.07:51:52.29#ibcon#read 3, iclass 24, count 2 2006.161.07:51:52.29#ibcon#about to read 4, iclass 24, count 2 2006.161.07:51:52.29#ibcon#read 4, iclass 24, count 2 2006.161.07:51:52.29#ibcon#about to read 5, iclass 24, count 2 2006.161.07:51:52.29#ibcon#read 5, iclass 24, count 2 2006.161.07:51:52.29#ibcon#about to read 6, iclass 24, count 2 2006.161.07:51:52.29#ibcon#read 6, iclass 24, count 2 2006.161.07:51:52.29#ibcon#end of sib2, iclass 24, count 2 2006.161.07:51:52.29#ibcon#*after write, iclass 24, count 2 2006.161.07:51:52.29#ibcon#*before return 0, iclass 24, count 2 2006.161.07:51:52.29#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:51:52.29#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.07:51:52.29#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.07:51:52.29#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:52.29#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:51:52.41#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:51:52.41#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:51:52.41#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:51:52.41#ibcon#first serial, iclass 24, count 0 2006.161.07:51:52.41#ibcon#enter sib2, iclass 24, count 0 2006.161.07:51:52.41#ibcon#flushed, iclass 24, count 0 2006.161.07:51:52.41#ibcon#about to write, iclass 24, count 0 2006.161.07:51:52.41#ibcon#wrote, iclass 24, count 0 2006.161.07:51:52.41#ibcon#about to read 3, iclass 24, count 0 2006.161.07:51:52.43#ibcon#read 3, iclass 24, count 0 2006.161.07:51:52.43#ibcon#about to read 4, iclass 24, count 0 2006.161.07:51:52.43#ibcon#read 4, iclass 24, count 0 2006.161.07:51:52.43#ibcon#about to read 5, iclass 24, count 0 2006.161.07:51:52.43#ibcon#read 5, iclass 24, count 0 2006.161.07:51:52.43#ibcon#about to read 6, iclass 24, count 0 2006.161.07:51:52.43#ibcon#read 6, iclass 24, count 0 2006.161.07:51:52.43#ibcon#end of sib2, iclass 24, count 0 2006.161.07:51:52.43#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:51:52.43#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:51:52.43#ibcon#[27=USB\r\n] 2006.161.07:51:52.43#ibcon#*before write, iclass 24, count 0 2006.161.07:51:52.43#ibcon#enter sib2, iclass 24, count 0 2006.161.07:51:52.43#ibcon#flushed, iclass 24, count 0 2006.161.07:51:52.43#ibcon#about to write, iclass 24, count 0 2006.161.07:51:52.43#ibcon#wrote, iclass 24, count 0 2006.161.07:51:52.43#ibcon#about to read 3, iclass 24, count 0 2006.161.07:51:52.46#ibcon#read 3, iclass 24, count 0 2006.161.07:51:52.46#ibcon#about to read 4, iclass 24, count 0 2006.161.07:51:52.46#ibcon#read 4, iclass 24, count 0 2006.161.07:51:52.46#ibcon#about to read 5, iclass 24, count 0 2006.161.07:51:52.46#ibcon#read 5, iclass 24, count 0 2006.161.07:51:52.46#ibcon#about to read 6, iclass 24, count 0 2006.161.07:51:52.46#ibcon#read 6, iclass 24, count 0 2006.161.07:51:52.46#ibcon#end of sib2, iclass 24, count 0 2006.161.07:51:52.46#ibcon#*after write, iclass 24, count 0 2006.161.07:51:52.46#ibcon#*before return 0, iclass 24, count 0 2006.161.07:51:52.46#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:51:52.46#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.07:51:52.46#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:51:52.46#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:51:52.46$vc4f8/vblo=2,640.99 2006.161.07:51:52.46#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.07:51:52.46#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.07:51:52.46#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:52.46#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:52.46#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:52.46#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:52.46#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:51:52.46#ibcon#first serial, iclass 26, count 0 2006.161.07:51:52.46#ibcon#enter sib2, iclass 26, count 0 2006.161.07:51:52.46#ibcon#flushed, iclass 26, count 0 2006.161.07:51:52.46#ibcon#about to write, iclass 26, count 0 2006.161.07:51:52.46#ibcon#wrote, iclass 26, count 0 2006.161.07:51:52.46#ibcon#about to read 3, iclass 26, count 0 2006.161.07:51:52.49#ibcon#read 3, iclass 26, count 0 2006.161.07:51:52.49#ibcon#about to read 4, iclass 26, count 0 2006.161.07:51:52.49#ibcon#read 4, iclass 26, count 0 2006.161.07:51:52.49#ibcon#about to read 5, iclass 26, count 0 2006.161.07:51:52.49#ibcon#read 5, iclass 26, count 0 2006.161.07:51:52.49#ibcon#about to read 6, iclass 26, count 0 2006.161.07:51:52.49#ibcon#read 6, iclass 26, count 0 2006.161.07:51:52.49#ibcon#end of sib2, iclass 26, count 0 2006.161.07:51:52.49#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:51:52.49#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:51:52.49#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:51:52.49#ibcon#*before write, iclass 26, count 0 2006.161.07:51:52.49#ibcon#enter sib2, iclass 26, count 0 2006.161.07:51:52.49#ibcon#flushed, iclass 26, count 0 2006.161.07:51:52.49#ibcon#about to write, iclass 26, count 0 2006.161.07:51:52.49#ibcon#wrote, iclass 26, count 0 2006.161.07:51:52.49#ibcon#about to read 3, iclass 26, count 0 2006.161.07:51:52.53#ibcon#read 3, iclass 26, count 0 2006.161.07:51:52.53#ibcon#about to read 4, iclass 26, count 0 2006.161.07:51:52.53#ibcon#read 4, iclass 26, count 0 2006.161.07:51:52.53#ibcon#about to read 5, iclass 26, count 0 2006.161.07:51:52.53#ibcon#read 5, iclass 26, count 0 2006.161.07:51:52.53#ibcon#about to read 6, iclass 26, count 0 2006.161.07:51:52.53#ibcon#read 6, iclass 26, count 0 2006.161.07:51:52.53#ibcon#end of sib2, iclass 26, count 0 2006.161.07:51:52.53#ibcon#*after write, iclass 26, count 0 2006.161.07:51:52.53#ibcon#*before return 0, iclass 26, count 0 2006.161.07:51:52.53#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:52.53#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.07:51:52.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:51:52.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:51:52.53$vc4f8/vb=2,4 2006.161.07:51:52.53#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.07:51:52.53#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.07:51:52.53#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:52.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:52.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:52.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:52.58#ibcon#enter wrdev, iclass 28, count 2 2006.161.07:51:52.58#ibcon#first serial, iclass 28, count 2 2006.161.07:51:52.58#ibcon#enter sib2, iclass 28, count 2 2006.161.07:51:52.58#ibcon#flushed, iclass 28, count 2 2006.161.07:51:52.58#ibcon#about to write, iclass 28, count 2 2006.161.07:51:52.58#ibcon#wrote, iclass 28, count 2 2006.161.07:51:52.58#ibcon#about to read 3, iclass 28, count 2 2006.161.07:51:52.60#ibcon#read 3, iclass 28, count 2 2006.161.07:51:52.60#ibcon#about to read 4, iclass 28, count 2 2006.161.07:51:52.60#ibcon#read 4, iclass 28, count 2 2006.161.07:51:52.60#ibcon#about to read 5, iclass 28, count 2 2006.161.07:51:52.60#ibcon#read 5, iclass 28, count 2 2006.161.07:51:52.60#ibcon#about to read 6, iclass 28, count 2 2006.161.07:51:52.60#ibcon#read 6, iclass 28, count 2 2006.161.07:51:52.60#ibcon#end of sib2, iclass 28, count 2 2006.161.07:51:52.60#ibcon#*mode == 0, iclass 28, count 2 2006.161.07:51:52.60#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.07:51:52.60#ibcon#[27=AT02-04\r\n] 2006.161.07:51:52.60#ibcon#*before write, iclass 28, count 2 2006.161.07:51:52.60#ibcon#enter sib2, iclass 28, count 2 2006.161.07:51:52.60#ibcon#flushed, iclass 28, count 2 2006.161.07:51:52.60#ibcon#about to write, iclass 28, count 2 2006.161.07:51:52.60#ibcon#wrote, iclass 28, count 2 2006.161.07:51:52.60#ibcon#about to read 3, iclass 28, count 2 2006.161.07:51:52.63#ibcon#read 3, iclass 28, count 2 2006.161.07:51:52.63#ibcon#about to read 4, iclass 28, count 2 2006.161.07:51:52.63#ibcon#read 4, iclass 28, count 2 2006.161.07:51:52.63#ibcon#about to read 5, iclass 28, count 2 2006.161.07:51:52.63#ibcon#read 5, iclass 28, count 2 2006.161.07:51:52.63#ibcon#about to read 6, iclass 28, count 2 2006.161.07:51:52.63#ibcon#read 6, iclass 28, count 2 2006.161.07:51:52.63#ibcon#end of sib2, iclass 28, count 2 2006.161.07:51:52.63#ibcon#*after write, iclass 28, count 2 2006.161.07:51:52.63#ibcon#*before return 0, iclass 28, count 2 2006.161.07:51:52.63#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:52.63#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.07:51:52.63#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.07:51:52.63#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:52.63#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:52.75#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:52.75#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:52.75#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:51:52.75#ibcon#first serial, iclass 28, count 0 2006.161.07:51:52.75#ibcon#enter sib2, iclass 28, count 0 2006.161.07:51:52.75#ibcon#flushed, iclass 28, count 0 2006.161.07:51:52.75#ibcon#about to write, iclass 28, count 0 2006.161.07:51:52.75#ibcon#wrote, iclass 28, count 0 2006.161.07:51:52.75#ibcon#about to read 3, iclass 28, count 0 2006.161.07:51:52.77#ibcon#read 3, iclass 28, count 0 2006.161.07:51:52.77#ibcon#about to read 4, iclass 28, count 0 2006.161.07:51:52.77#ibcon#read 4, iclass 28, count 0 2006.161.07:51:52.77#ibcon#about to read 5, iclass 28, count 0 2006.161.07:51:52.77#ibcon#read 5, iclass 28, count 0 2006.161.07:51:52.77#ibcon#about to read 6, iclass 28, count 0 2006.161.07:51:52.77#ibcon#read 6, iclass 28, count 0 2006.161.07:51:52.77#ibcon#end of sib2, iclass 28, count 0 2006.161.07:51:52.77#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:51:52.77#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:51:52.77#ibcon#[27=USB\r\n] 2006.161.07:51:52.77#ibcon#*before write, iclass 28, count 0 2006.161.07:51:52.77#ibcon#enter sib2, iclass 28, count 0 2006.161.07:51:52.77#ibcon#flushed, iclass 28, count 0 2006.161.07:51:52.77#ibcon#about to write, iclass 28, count 0 2006.161.07:51:52.77#ibcon#wrote, iclass 28, count 0 2006.161.07:51:52.77#ibcon#about to read 3, iclass 28, count 0 2006.161.07:51:52.80#ibcon#read 3, iclass 28, count 0 2006.161.07:51:52.80#ibcon#about to read 4, iclass 28, count 0 2006.161.07:51:52.80#ibcon#read 4, iclass 28, count 0 2006.161.07:51:52.80#ibcon#about to read 5, iclass 28, count 0 2006.161.07:51:52.80#ibcon#read 5, iclass 28, count 0 2006.161.07:51:52.80#ibcon#about to read 6, iclass 28, count 0 2006.161.07:51:52.80#ibcon#read 6, iclass 28, count 0 2006.161.07:51:52.80#ibcon#end of sib2, iclass 28, count 0 2006.161.07:51:52.80#ibcon#*after write, iclass 28, count 0 2006.161.07:51:52.80#ibcon#*before return 0, iclass 28, count 0 2006.161.07:51:52.80#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:52.80#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.07:51:52.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:51:52.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:51:52.80$vc4f8/vblo=3,656.99 2006.161.07:51:52.80#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:51:52.80#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:51:52.80#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:52.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:52.80#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:52.80#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:52.80#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:51:52.80#ibcon#first serial, iclass 30, count 0 2006.161.07:51:52.80#ibcon#enter sib2, iclass 30, count 0 2006.161.07:51:52.80#ibcon#flushed, iclass 30, count 0 2006.161.07:51:52.80#ibcon#about to write, iclass 30, count 0 2006.161.07:51:52.80#ibcon#wrote, iclass 30, count 0 2006.161.07:51:52.80#ibcon#about to read 3, iclass 30, count 0 2006.161.07:51:52.82#ibcon#read 3, iclass 30, count 0 2006.161.07:51:52.82#ibcon#about to read 4, iclass 30, count 0 2006.161.07:51:52.82#ibcon#read 4, iclass 30, count 0 2006.161.07:51:52.82#ibcon#about to read 5, iclass 30, count 0 2006.161.07:51:52.82#ibcon#read 5, iclass 30, count 0 2006.161.07:51:52.82#ibcon#about to read 6, iclass 30, count 0 2006.161.07:51:52.82#ibcon#read 6, iclass 30, count 0 2006.161.07:51:52.82#ibcon#end of sib2, iclass 30, count 0 2006.161.07:51:52.82#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:51:52.82#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:51:52.82#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:51:52.82#ibcon#*before write, iclass 30, count 0 2006.161.07:51:52.82#ibcon#enter sib2, iclass 30, count 0 2006.161.07:51:52.82#ibcon#flushed, iclass 30, count 0 2006.161.07:51:52.82#ibcon#about to write, iclass 30, count 0 2006.161.07:51:52.82#ibcon#wrote, iclass 30, count 0 2006.161.07:51:52.82#ibcon#about to read 3, iclass 30, count 0 2006.161.07:51:52.86#ibcon#read 3, iclass 30, count 0 2006.161.07:51:52.86#ibcon#about to read 4, iclass 30, count 0 2006.161.07:51:52.86#ibcon#read 4, iclass 30, count 0 2006.161.07:51:52.86#ibcon#about to read 5, iclass 30, count 0 2006.161.07:51:52.86#ibcon#read 5, iclass 30, count 0 2006.161.07:51:52.86#ibcon#about to read 6, iclass 30, count 0 2006.161.07:51:52.86#ibcon#read 6, iclass 30, count 0 2006.161.07:51:52.86#ibcon#end of sib2, iclass 30, count 0 2006.161.07:51:52.86#ibcon#*after write, iclass 30, count 0 2006.161.07:51:52.86#ibcon#*before return 0, iclass 30, count 0 2006.161.07:51:52.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:52.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:51:52.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:51:52.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:51:52.86$vc4f8/vb=3,4 2006.161.07:51:52.86#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.07:51:52.86#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.07:51:52.86#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:52.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:52.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:52.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:52.92#ibcon#enter wrdev, iclass 32, count 2 2006.161.07:51:52.92#ibcon#first serial, iclass 32, count 2 2006.161.07:51:52.92#ibcon#enter sib2, iclass 32, count 2 2006.161.07:51:52.92#ibcon#flushed, iclass 32, count 2 2006.161.07:51:52.92#ibcon#about to write, iclass 32, count 2 2006.161.07:51:52.92#ibcon#wrote, iclass 32, count 2 2006.161.07:51:52.92#ibcon#about to read 3, iclass 32, count 2 2006.161.07:51:52.94#ibcon#read 3, iclass 32, count 2 2006.161.07:51:52.94#ibcon#about to read 4, iclass 32, count 2 2006.161.07:51:52.94#ibcon#read 4, iclass 32, count 2 2006.161.07:51:52.94#ibcon#about to read 5, iclass 32, count 2 2006.161.07:51:52.94#ibcon#read 5, iclass 32, count 2 2006.161.07:51:52.94#ibcon#about to read 6, iclass 32, count 2 2006.161.07:51:52.94#ibcon#read 6, iclass 32, count 2 2006.161.07:51:52.94#ibcon#end of sib2, iclass 32, count 2 2006.161.07:51:52.94#ibcon#*mode == 0, iclass 32, count 2 2006.161.07:51:52.94#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.07:51:52.94#ibcon#[27=AT03-04\r\n] 2006.161.07:51:52.94#ibcon#*before write, iclass 32, count 2 2006.161.07:51:52.94#ibcon#enter sib2, iclass 32, count 2 2006.161.07:51:52.94#ibcon#flushed, iclass 32, count 2 2006.161.07:51:52.94#ibcon#about to write, iclass 32, count 2 2006.161.07:51:52.94#ibcon#wrote, iclass 32, count 2 2006.161.07:51:52.94#ibcon#about to read 3, iclass 32, count 2 2006.161.07:51:52.97#ibcon#read 3, iclass 32, count 2 2006.161.07:51:52.97#ibcon#about to read 4, iclass 32, count 2 2006.161.07:51:52.97#ibcon#read 4, iclass 32, count 2 2006.161.07:51:52.97#ibcon#about to read 5, iclass 32, count 2 2006.161.07:51:52.97#ibcon#read 5, iclass 32, count 2 2006.161.07:51:52.97#ibcon#about to read 6, iclass 32, count 2 2006.161.07:51:52.97#ibcon#read 6, iclass 32, count 2 2006.161.07:51:52.97#ibcon#end of sib2, iclass 32, count 2 2006.161.07:51:52.97#ibcon#*after write, iclass 32, count 2 2006.161.07:51:52.97#ibcon#*before return 0, iclass 32, count 2 2006.161.07:51:52.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:52.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.07:51:52.97#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.07:51:52.97#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:52.97#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:53.09#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:53.09#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:53.09#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:51:53.09#ibcon#first serial, iclass 32, count 0 2006.161.07:51:53.09#ibcon#enter sib2, iclass 32, count 0 2006.161.07:51:53.09#ibcon#flushed, iclass 32, count 0 2006.161.07:51:53.09#ibcon#about to write, iclass 32, count 0 2006.161.07:51:53.09#ibcon#wrote, iclass 32, count 0 2006.161.07:51:53.09#ibcon#about to read 3, iclass 32, count 0 2006.161.07:51:53.11#ibcon#read 3, iclass 32, count 0 2006.161.07:51:53.11#ibcon#about to read 4, iclass 32, count 0 2006.161.07:51:53.11#ibcon#read 4, iclass 32, count 0 2006.161.07:51:53.11#ibcon#about to read 5, iclass 32, count 0 2006.161.07:51:53.11#ibcon#read 5, iclass 32, count 0 2006.161.07:51:53.11#ibcon#about to read 6, iclass 32, count 0 2006.161.07:51:53.11#ibcon#read 6, iclass 32, count 0 2006.161.07:51:53.11#ibcon#end of sib2, iclass 32, count 0 2006.161.07:51:53.11#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:51:53.11#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:51:53.11#ibcon#[27=USB\r\n] 2006.161.07:51:53.11#ibcon#*before write, iclass 32, count 0 2006.161.07:51:53.11#ibcon#enter sib2, iclass 32, count 0 2006.161.07:51:53.11#ibcon#flushed, iclass 32, count 0 2006.161.07:51:53.11#ibcon#about to write, iclass 32, count 0 2006.161.07:51:53.11#ibcon#wrote, iclass 32, count 0 2006.161.07:51:53.11#ibcon#about to read 3, iclass 32, count 0 2006.161.07:51:53.14#ibcon#read 3, iclass 32, count 0 2006.161.07:51:53.14#ibcon#about to read 4, iclass 32, count 0 2006.161.07:51:53.14#ibcon#read 4, iclass 32, count 0 2006.161.07:51:53.14#ibcon#about to read 5, iclass 32, count 0 2006.161.07:51:53.14#ibcon#read 5, iclass 32, count 0 2006.161.07:51:53.14#ibcon#about to read 6, iclass 32, count 0 2006.161.07:51:53.14#ibcon#read 6, iclass 32, count 0 2006.161.07:51:53.14#ibcon#end of sib2, iclass 32, count 0 2006.161.07:51:53.14#ibcon#*after write, iclass 32, count 0 2006.161.07:51:53.14#ibcon#*before return 0, iclass 32, count 0 2006.161.07:51:53.14#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:53.14#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.07:51:53.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:51:53.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:51:53.14$vc4f8/vblo=4,712.99 2006.161.07:51:53.14#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.07:51:53.14#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.07:51:53.14#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:53.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:53.14#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:53.14#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:53.14#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:51:53.14#ibcon#first serial, iclass 34, count 0 2006.161.07:51:53.14#ibcon#enter sib2, iclass 34, count 0 2006.161.07:51:53.14#ibcon#flushed, iclass 34, count 0 2006.161.07:51:53.14#ibcon#about to write, iclass 34, count 0 2006.161.07:51:53.14#ibcon#wrote, iclass 34, count 0 2006.161.07:51:53.14#ibcon#about to read 3, iclass 34, count 0 2006.161.07:51:53.16#ibcon#read 3, iclass 34, count 0 2006.161.07:51:53.16#ibcon#about to read 4, iclass 34, count 0 2006.161.07:51:53.16#ibcon#read 4, iclass 34, count 0 2006.161.07:51:53.16#ibcon#about to read 5, iclass 34, count 0 2006.161.07:51:53.16#ibcon#read 5, iclass 34, count 0 2006.161.07:51:53.16#ibcon#about to read 6, iclass 34, count 0 2006.161.07:51:53.16#ibcon#read 6, iclass 34, count 0 2006.161.07:51:53.16#ibcon#end of sib2, iclass 34, count 0 2006.161.07:51:53.16#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:51:53.16#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:51:53.16#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:51:53.16#ibcon#*before write, iclass 34, count 0 2006.161.07:51:53.16#ibcon#enter sib2, iclass 34, count 0 2006.161.07:51:53.16#ibcon#flushed, iclass 34, count 0 2006.161.07:51:53.16#ibcon#about to write, iclass 34, count 0 2006.161.07:51:53.16#ibcon#wrote, iclass 34, count 0 2006.161.07:51:53.16#ibcon#about to read 3, iclass 34, count 0 2006.161.07:51:53.20#ibcon#read 3, iclass 34, count 0 2006.161.07:51:53.20#ibcon#about to read 4, iclass 34, count 0 2006.161.07:51:53.20#ibcon#read 4, iclass 34, count 0 2006.161.07:51:53.20#ibcon#about to read 5, iclass 34, count 0 2006.161.07:51:53.20#ibcon#read 5, iclass 34, count 0 2006.161.07:51:53.20#ibcon#about to read 6, iclass 34, count 0 2006.161.07:51:53.20#ibcon#read 6, iclass 34, count 0 2006.161.07:51:53.20#ibcon#end of sib2, iclass 34, count 0 2006.161.07:51:53.20#ibcon#*after write, iclass 34, count 0 2006.161.07:51:53.20#ibcon#*before return 0, iclass 34, count 0 2006.161.07:51:53.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:53.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.07:51:53.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:51:53.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:51:53.20$vc4f8/vb=4,4 2006.161.07:51:53.20#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.07:51:53.20#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.07:51:53.20#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:53.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:53.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:53.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:53.26#ibcon#enter wrdev, iclass 36, count 2 2006.161.07:51:53.26#ibcon#first serial, iclass 36, count 2 2006.161.07:51:53.26#ibcon#enter sib2, iclass 36, count 2 2006.161.07:51:53.26#ibcon#flushed, iclass 36, count 2 2006.161.07:51:53.26#ibcon#about to write, iclass 36, count 2 2006.161.07:51:53.26#ibcon#wrote, iclass 36, count 2 2006.161.07:51:53.26#ibcon#about to read 3, iclass 36, count 2 2006.161.07:51:53.28#ibcon#read 3, iclass 36, count 2 2006.161.07:51:53.28#ibcon#about to read 4, iclass 36, count 2 2006.161.07:51:53.28#ibcon#read 4, iclass 36, count 2 2006.161.07:51:53.28#ibcon#about to read 5, iclass 36, count 2 2006.161.07:51:53.28#ibcon#read 5, iclass 36, count 2 2006.161.07:51:53.28#ibcon#about to read 6, iclass 36, count 2 2006.161.07:51:53.28#ibcon#read 6, iclass 36, count 2 2006.161.07:51:53.28#ibcon#end of sib2, iclass 36, count 2 2006.161.07:51:53.28#ibcon#*mode == 0, iclass 36, count 2 2006.161.07:51:53.28#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.07:51:53.28#ibcon#[27=AT04-04\r\n] 2006.161.07:51:53.28#ibcon#*before write, iclass 36, count 2 2006.161.07:51:53.28#ibcon#enter sib2, iclass 36, count 2 2006.161.07:51:53.28#ibcon#flushed, iclass 36, count 2 2006.161.07:51:53.28#ibcon#about to write, iclass 36, count 2 2006.161.07:51:53.28#ibcon#wrote, iclass 36, count 2 2006.161.07:51:53.28#ibcon#about to read 3, iclass 36, count 2 2006.161.07:51:53.31#ibcon#read 3, iclass 36, count 2 2006.161.07:51:53.31#ibcon#about to read 4, iclass 36, count 2 2006.161.07:51:53.31#ibcon#read 4, iclass 36, count 2 2006.161.07:51:53.31#ibcon#about to read 5, iclass 36, count 2 2006.161.07:51:53.31#ibcon#read 5, iclass 36, count 2 2006.161.07:51:53.31#ibcon#about to read 6, iclass 36, count 2 2006.161.07:51:53.31#ibcon#read 6, iclass 36, count 2 2006.161.07:51:53.31#ibcon#end of sib2, iclass 36, count 2 2006.161.07:51:53.31#ibcon#*after write, iclass 36, count 2 2006.161.07:51:53.31#ibcon#*before return 0, iclass 36, count 2 2006.161.07:51:53.31#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:53.31#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.07:51:53.31#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.07:51:53.31#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:53.31#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:53.43#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:53.43#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:53.43#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:51:53.43#ibcon#first serial, iclass 36, count 0 2006.161.07:51:53.43#ibcon#enter sib2, iclass 36, count 0 2006.161.07:51:53.43#ibcon#flushed, iclass 36, count 0 2006.161.07:51:53.43#ibcon#about to write, iclass 36, count 0 2006.161.07:51:53.43#ibcon#wrote, iclass 36, count 0 2006.161.07:51:53.43#ibcon#about to read 3, iclass 36, count 0 2006.161.07:51:53.45#ibcon#read 3, iclass 36, count 0 2006.161.07:51:53.45#ibcon#about to read 4, iclass 36, count 0 2006.161.07:51:53.45#ibcon#read 4, iclass 36, count 0 2006.161.07:51:53.45#ibcon#about to read 5, iclass 36, count 0 2006.161.07:51:53.45#ibcon#read 5, iclass 36, count 0 2006.161.07:51:53.45#ibcon#about to read 6, iclass 36, count 0 2006.161.07:51:53.45#ibcon#read 6, iclass 36, count 0 2006.161.07:51:53.45#ibcon#end of sib2, iclass 36, count 0 2006.161.07:51:53.45#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:51:53.45#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:51:53.45#ibcon#[27=USB\r\n] 2006.161.07:51:53.45#ibcon#*before write, iclass 36, count 0 2006.161.07:51:53.45#ibcon#enter sib2, iclass 36, count 0 2006.161.07:51:53.45#ibcon#flushed, iclass 36, count 0 2006.161.07:51:53.45#ibcon#about to write, iclass 36, count 0 2006.161.07:51:53.45#ibcon#wrote, iclass 36, count 0 2006.161.07:51:53.45#ibcon#about to read 3, iclass 36, count 0 2006.161.07:51:53.48#ibcon#read 3, iclass 36, count 0 2006.161.07:51:53.48#ibcon#about to read 4, iclass 36, count 0 2006.161.07:51:53.48#ibcon#read 4, iclass 36, count 0 2006.161.07:51:53.48#ibcon#about to read 5, iclass 36, count 0 2006.161.07:51:53.48#ibcon#read 5, iclass 36, count 0 2006.161.07:51:53.48#ibcon#about to read 6, iclass 36, count 0 2006.161.07:51:53.48#ibcon#read 6, iclass 36, count 0 2006.161.07:51:53.48#ibcon#end of sib2, iclass 36, count 0 2006.161.07:51:53.48#ibcon#*after write, iclass 36, count 0 2006.161.07:51:53.48#ibcon#*before return 0, iclass 36, count 0 2006.161.07:51:53.48#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:53.48#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.07:51:53.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:51:53.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:51:53.48$vc4f8/vblo=5,744.99 2006.161.07:51:53.48#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.07:51:53.48#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.07:51:53.48#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:53.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:53.48#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:53.48#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:53.48#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:51:53.48#ibcon#first serial, iclass 38, count 0 2006.161.07:51:53.48#ibcon#enter sib2, iclass 38, count 0 2006.161.07:51:53.48#ibcon#flushed, iclass 38, count 0 2006.161.07:51:53.48#ibcon#about to write, iclass 38, count 0 2006.161.07:51:53.48#ibcon#wrote, iclass 38, count 0 2006.161.07:51:53.48#ibcon#about to read 3, iclass 38, count 0 2006.161.07:51:53.50#ibcon#read 3, iclass 38, count 0 2006.161.07:51:53.50#ibcon#about to read 4, iclass 38, count 0 2006.161.07:51:53.50#ibcon#read 4, iclass 38, count 0 2006.161.07:51:53.50#ibcon#about to read 5, iclass 38, count 0 2006.161.07:51:53.50#ibcon#read 5, iclass 38, count 0 2006.161.07:51:53.50#ibcon#about to read 6, iclass 38, count 0 2006.161.07:51:53.50#ibcon#read 6, iclass 38, count 0 2006.161.07:51:53.50#ibcon#end of sib2, iclass 38, count 0 2006.161.07:51:53.50#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:51:53.50#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:51:53.50#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:51:53.50#ibcon#*before write, iclass 38, count 0 2006.161.07:51:53.50#ibcon#enter sib2, iclass 38, count 0 2006.161.07:51:53.50#ibcon#flushed, iclass 38, count 0 2006.161.07:51:53.50#ibcon#about to write, iclass 38, count 0 2006.161.07:51:53.50#ibcon#wrote, iclass 38, count 0 2006.161.07:51:53.50#ibcon#about to read 3, iclass 38, count 0 2006.161.07:51:53.54#ibcon#read 3, iclass 38, count 0 2006.161.07:51:53.54#ibcon#about to read 4, iclass 38, count 0 2006.161.07:51:53.54#ibcon#read 4, iclass 38, count 0 2006.161.07:51:53.54#ibcon#about to read 5, iclass 38, count 0 2006.161.07:51:53.54#ibcon#read 5, iclass 38, count 0 2006.161.07:51:53.54#ibcon#about to read 6, iclass 38, count 0 2006.161.07:51:53.54#ibcon#read 6, iclass 38, count 0 2006.161.07:51:53.54#ibcon#end of sib2, iclass 38, count 0 2006.161.07:51:53.54#ibcon#*after write, iclass 38, count 0 2006.161.07:51:53.54#ibcon#*before return 0, iclass 38, count 0 2006.161.07:51:53.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:53.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.07:51:53.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:51:53.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:51:53.54$vc4f8/vb=5,4 2006.161.07:51:53.54#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.07:51:53.54#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.07:51:53.54#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:53.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:53.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:53.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:53.60#ibcon#enter wrdev, iclass 40, count 2 2006.161.07:51:53.60#ibcon#first serial, iclass 40, count 2 2006.161.07:51:53.60#ibcon#enter sib2, iclass 40, count 2 2006.161.07:51:53.60#ibcon#flushed, iclass 40, count 2 2006.161.07:51:53.60#ibcon#about to write, iclass 40, count 2 2006.161.07:51:53.60#ibcon#wrote, iclass 40, count 2 2006.161.07:51:53.60#ibcon#about to read 3, iclass 40, count 2 2006.161.07:51:53.62#ibcon#read 3, iclass 40, count 2 2006.161.07:51:53.62#ibcon#about to read 4, iclass 40, count 2 2006.161.07:51:53.62#ibcon#read 4, iclass 40, count 2 2006.161.07:51:53.62#ibcon#about to read 5, iclass 40, count 2 2006.161.07:51:53.62#ibcon#read 5, iclass 40, count 2 2006.161.07:51:53.62#ibcon#about to read 6, iclass 40, count 2 2006.161.07:51:53.62#ibcon#read 6, iclass 40, count 2 2006.161.07:51:53.62#ibcon#end of sib2, iclass 40, count 2 2006.161.07:51:53.62#ibcon#*mode == 0, iclass 40, count 2 2006.161.07:51:53.62#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.07:51:53.62#ibcon#[27=AT05-04\r\n] 2006.161.07:51:53.62#ibcon#*before write, iclass 40, count 2 2006.161.07:51:53.62#ibcon#enter sib2, iclass 40, count 2 2006.161.07:51:53.62#ibcon#flushed, iclass 40, count 2 2006.161.07:51:53.62#ibcon#about to write, iclass 40, count 2 2006.161.07:51:53.62#ibcon#wrote, iclass 40, count 2 2006.161.07:51:53.62#ibcon#about to read 3, iclass 40, count 2 2006.161.07:51:53.65#ibcon#read 3, iclass 40, count 2 2006.161.07:51:53.65#ibcon#about to read 4, iclass 40, count 2 2006.161.07:51:53.65#ibcon#read 4, iclass 40, count 2 2006.161.07:51:53.65#ibcon#about to read 5, iclass 40, count 2 2006.161.07:51:53.65#ibcon#read 5, iclass 40, count 2 2006.161.07:51:53.65#ibcon#about to read 6, iclass 40, count 2 2006.161.07:51:53.65#ibcon#read 6, iclass 40, count 2 2006.161.07:51:53.65#ibcon#end of sib2, iclass 40, count 2 2006.161.07:51:53.65#ibcon#*after write, iclass 40, count 2 2006.161.07:51:53.65#ibcon#*before return 0, iclass 40, count 2 2006.161.07:51:53.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:53.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.07:51:53.65#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.07:51:53.65#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:53.65#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:53.77#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:53.77#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:53.77#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:51:53.77#ibcon#first serial, iclass 40, count 0 2006.161.07:51:53.77#ibcon#enter sib2, iclass 40, count 0 2006.161.07:51:53.77#ibcon#flushed, iclass 40, count 0 2006.161.07:51:53.77#ibcon#about to write, iclass 40, count 0 2006.161.07:51:53.77#ibcon#wrote, iclass 40, count 0 2006.161.07:51:53.77#ibcon#about to read 3, iclass 40, count 0 2006.161.07:51:53.79#ibcon#read 3, iclass 40, count 0 2006.161.07:51:53.79#ibcon#about to read 4, iclass 40, count 0 2006.161.07:51:53.79#ibcon#read 4, iclass 40, count 0 2006.161.07:51:53.79#ibcon#about to read 5, iclass 40, count 0 2006.161.07:51:53.79#ibcon#read 5, iclass 40, count 0 2006.161.07:51:53.79#ibcon#about to read 6, iclass 40, count 0 2006.161.07:51:53.79#ibcon#read 6, iclass 40, count 0 2006.161.07:51:53.79#ibcon#end of sib2, iclass 40, count 0 2006.161.07:51:53.79#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:51:53.79#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:51:53.79#ibcon#[27=USB\r\n] 2006.161.07:51:53.79#ibcon#*before write, iclass 40, count 0 2006.161.07:51:53.79#ibcon#enter sib2, iclass 40, count 0 2006.161.07:51:53.79#ibcon#flushed, iclass 40, count 0 2006.161.07:51:53.79#ibcon#about to write, iclass 40, count 0 2006.161.07:51:53.79#ibcon#wrote, iclass 40, count 0 2006.161.07:51:53.79#ibcon#about to read 3, iclass 40, count 0 2006.161.07:51:53.82#ibcon#read 3, iclass 40, count 0 2006.161.07:51:53.82#ibcon#about to read 4, iclass 40, count 0 2006.161.07:51:53.82#ibcon#read 4, iclass 40, count 0 2006.161.07:51:53.82#ibcon#about to read 5, iclass 40, count 0 2006.161.07:51:53.82#ibcon#read 5, iclass 40, count 0 2006.161.07:51:53.82#ibcon#about to read 6, iclass 40, count 0 2006.161.07:51:53.82#ibcon#read 6, iclass 40, count 0 2006.161.07:51:53.82#ibcon#end of sib2, iclass 40, count 0 2006.161.07:51:53.82#ibcon#*after write, iclass 40, count 0 2006.161.07:51:53.82#ibcon#*before return 0, iclass 40, count 0 2006.161.07:51:53.82#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:53.82#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.07:51:53.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:51:53.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:51:53.82$vc4f8/vblo=6,752.99 2006.161.07:51:53.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.07:51:53.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.07:51:53.82#ibcon#ireg 17 cls_cnt 0 2006.161.07:51:53.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:53.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:53.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:53.82#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:51:53.82#ibcon#first serial, iclass 4, count 0 2006.161.07:51:53.82#ibcon#enter sib2, iclass 4, count 0 2006.161.07:51:53.82#ibcon#flushed, iclass 4, count 0 2006.161.07:51:53.82#ibcon#about to write, iclass 4, count 0 2006.161.07:51:53.82#ibcon#wrote, iclass 4, count 0 2006.161.07:51:53.82#ibcon#about to read 3, iclass 4, count 0 2006.161.07:51:53.84#ibcon#read 3, iclass 4, count 0 2006.161.07:51:53.84#ibcon#about to read 4, iclass 4, count 0 2006.161.07:51:53.84#ibcon#read 4, iclass 4, count 0 2006.161.07:51:53.84#ibcon#about to read 5, iclass 4, count 0 2006.161.07:51:53.84#ibcon#read 5, iclass 4, count 0 2006.161.07:51:53.84#ibcon#about to read 6, iclass 4, count 0 2006.161.07:51:53.84#ibcon#read 6, iclass 4, count 0 2006.161.07:51:53.84#ibcon#end of sib2, iclass 4, count 0 2006.161.07:51:53.84#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:51:53.84#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:51:53.84#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:51:53.84#ibcon#*before write, iclass 4, count 0 2006.161.07:51:53.84#ibcon#enter sib2, iclass 4, count 0 2006.161.07:51:53.84#ibcon#flushed, iclass 4, count 0 2006.161.07:51:53.84#ibcon#about to write, iclass 4, count 0 2006.161.07:51:53.84#ibcon#wrote, iclass 4, count 0 2006.161.07:51:53.84#ibcon#about to read 3, iclass 4, count 0 2006.161.07:51:53.88#ibcon#read 3, iclass 4, count 0 2006.161.07:51:53.88#ibcon#about to read 4, iclass 4, count 0 2006.161.07:51:53.88#ibcon#read 4, iclass 4, count 0 2006.161.07:51:53.88#ibcon#about to read 5, iclass 4, count 0 2006.161.07:51:53.88#ibcon#read 5, iclass 4, count 0 2006.161.07:51:53.88#ibcon#about to read 6, iclass 4, count 0 2006.161.07:51:53.88#ibcon#read 6, iclass 4, count 0 2006.161.07:51:53.88#ibcon#end of sib2, iclass 4, count 0 2006.161.07:51:53.88#ibcon#*after write, iclass 4, count 0 2006.161.07:51:53.88#ibcon#*before return 0, iclass 4, count 0 2006.161.07:51:53.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:53.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.07:51:53.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:51:53.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:51:53.88$vc4f8/vb=6,4 2006.161.07:51:53.88#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.07:51:53.88#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.07:51:53.88#ibcon#ireg 11 cls_cnt 2 2006.161.07:51:53.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:53.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:53.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:53.94#ibcon#enter wrdev, iclass 6, count 2 2006.161.07:51:53.94#ibcon#first serial, iclass 6, count 2 2006.161.07:51:53.94#ibcon#enter sib2, iclass 6, count 2 2006.161.07:51:53.94#ibcon#flushed, iclass 6, count 2 2006.161.07:51:53.94#ibcon#about to write, iclass 6, count 2 2006.161.07:51:53.94#ibcon#wrote, iclass 6, count 2 2006.161.07:51:53.94#ibcon#about to read 3, iclass 6, count 2 2006.161.07:51:53.96#ibcon#read 3, iclass 6, count 2 2006.161.07:51:53.96#ibcon#about to read 4, iclass 6, count 2 2006.161.07:51:53.96#ibcon#read 4, iclass 6, count 2 2006.161.07:51:53.96#ibcon#about to read 5, iclass 6, count 2 2006.161.07:51:53.96#ibcon#read 5, iclass 6, count 2 2006.161.07:51:53.96#ibcon#about to read 6, iclass 6, count 2 2006.161.07:51:53.96#ibcon#read 6, iclass 6, count 2 2006.161.07:51:53.96#ibcon#end of sib2, iclass 6, count 2 2006.161.07:51:53.96#ibcon#*mode == 0, iclass 6, count 2 2006.161.07:51:53.96#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.07:51:53.96#ibcon#[27=AT06-04\r\n] 2006.161.07:51:53.96#ibcon#*before write, iclass 6, count 2 2006.161.07:51:53.96#ibcon#enter sib2, iclass 6, count 2 2006.161.07:51:53.96#ibcon#flushed, iclass 6, count 2 2006.161.07:51:53.96#ibcon#about to write, iclass 6, count 2 2006.161.07:51:53.96#ibcon#wrote, iclass 6, count 2 2006.161.07:51:53.96#ibcon#about to read 3, iclass 6, count 2 2006.161.07:51:53.99#ibcon#read 3, iclass 6, count 2 2006.161.07:51:53.99#ibcon#about to read 4, iclass 6, count 2 2006.161.07:51:53.99#ibcon#read 4, iclass 6, count 2 2006.161.07:51:53.99#ibcon#about to read 5, iclass 6, count 2 2006.161.07:51:53.99#ibcon#read 5, iclass 6, count 2 2006.161.07:51:53.99#ibcon#about to read 6, iclass 6, count 2 2006.161.07:51:53.99#ibcon#read 6, iclass 6, count 2 2006.161.07:51:53.99#ibcon#end of sib2, iclass 6, count 2 2006.161.07:51:53.99#ibcon#*after write, iclass 6, count 2 2006.161.07:51:53.99#ibcon#*before return 0, iclass 6, count 2 2006.161.07:51:53.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:53.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.07:51:53.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.07:51:53.99#ibcon#ireg 7 cls_cnt 0 2006.161.07:51:53.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:54.11#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:54.11#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:54.11#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:51:54.11#ibcon#first serial, iclass 6, count 0 2006.161.07:51:54.11#ibcon#enter sib2, iclass 6, count 0 2006.161.07:51:54.11#ibcon#flushed, iclass 6, count 0 2006.161.07:51:54.11#ibcon#about to write, iclass 6, count 0 2006.161.07:51:54.11#ibcon#wrote, iclass 6, count 0 2006.161.07:51:54.11#ibcon#about to read 3, iclass 6, count 0 2006.161.07:51:54.13#ibcon#read 3, iclass 6, count 0 2006.161.07:51:54.13#ibcon#about to read 4, iclass 6, count 0 2006.161.07:51:54.13#ibcon#read 4, iclass 6, count 0 2006.161.07:51:54.13#ibcon#about to read 5, iclass 6, count 0 2006.161.07:51:54.13#ibcon#read 5, iclass 6, count 0 2006.161.07:51:54.13#ibcon#about to read 6, iclass 6, count 0 2006.161.07:51:54.13#ibcon#read 6, iclass 6, count 0 2006.161.07:51:54.13#ibcon#end of sib2, iclass 6, count 0 2006.161.07:51:54.13#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:51:54.13#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:51:54.13#ibcon#[27=USB\r\n] 2006.161.07:51:54.13#ibcon#*before write, iclass 6, count 0 2006.161.07:51:54.13#ibcon#enter sib2, iclass 6, count 0 2006.161.07:51:54.13#ibcon#flushed, iclass 6, count 0 2006.161.07:51:54.13#ibcon#about to write, iclass 6, count 0 2006.161.07:51:54.13#ibcon#wrote, iclass 6, count 0 2006.161.07:51:54.13#ibcon#about to read 3, iclass 6, count 0 2006.161.07:51:54.16#ibcon#read 3, iclass 6, count 0 2006.161.07:51:54.16#ibcon#about to read 4, iclass 6, count 0 2006.161.07:51:54.16#ibcon#read 4, iclass 6, count 0 2006.161.07:51:54.16#ibcon#about to read 5, iclass 6, count 0 2006.161.07:51:54.16#ibcon#read 5, iclass 6, count 0 2006.161.07:51:54.16#ibcon#about to read 6, iclass 6, count 0 2006.161.07:51:54.16#ibcon#read 6, iclass 6, count 0 2006.161.07:51:54.16#ibcon#end of sib2, iclass 6, count 0 2006.161.07:51:54.16#ibcon#*after write, iclass 6, count 0 2006.161.07:51:54.16#ibcon#*before return 0, iclass 6, count 0 2006.161.07:51:54.16#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:54.16#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.07:51:54.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:51:54.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:51:54.16$vc4f8/vabw=wide 2006.161.07:51:54.16#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.07:51:54.16#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.07:51:54.16#ibcon#ireg 8 cls_cnt 0 2006.161.07:51:54.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:54.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:54.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:54.16#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:51:54.16#ibcon#first serial, iclass 10, count 0 2006.161.07:51:54.16#ibcon#enter sib2, iclass 10, count 0 2006.161.07:51:54.16#ibcon#flushed, iclass 10, count 0 2006.161.07:51:54.16#ibcon#about to write, iclass 10, count 0 2006.161.07:51:54.16#ibcon#wrote, iclass 10, count 0 2006.161.07:51:54.16#ibcon#about to read 3, iclass 10, count 0 2006.161.07:51:54.18#ibcon#read 3, iclass 10, count 0 2006.161.07:51:54.18#ibcon#about to read 4, iclass 10, count 0 2006.161.07:51:54.18#ibcon#read 4, iclass 10, count 0 2006.161.07:51:54.18#ibcon#about to read 5, iclass 10, count 0 2006.161.07:51:54.18#ibcon#read 5, iclass 10, count 0 2006.161.07:51:54.18#ibcon#about to read 6, iclass 10, count 0 2006.161.07:51:54.18#ibcon#read 6, iclass 10, count 0 2006.161.07:51:54.18#ibcon#end of sib2, iclass 10, count 0 2006.161.07:51:54.18#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:51:54.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:51:54.18#ibcon#[25=BW32\r\n] 2006.161.07:51:54.18#ibcon#*before write, iclass 10, count 0 2006.161.07:51:54.18#ibcon#enter sib2, iclass 10, count 0 2006.161.07:51:54.18#ibcon#flushed, iclass 10, count 0 2006.161.07:51:54.18#ibcon#about to write, iclass 10, count 0 2006.161.07:51:54.18#ibcon#wrote, iclass 10, count 0 2006.161.07:51:54.18#ibcon#about to read 3, iclass 10, count 0 2006.161.07:51:54.21#ibcon#read 3, iclass 10, count 0 2006.161.07:51:54.21#ibcon#about to read 4, iclass 10, count 0 2006.161.07:51:54.21#ibcon#read 4, iclass 10, count 0 2006.161.07:51:54.21#ibcon#about to read 5, iclass 10, count 0 2006.161.07:51:54.21#ibcon#read 5, iclass 10, count 0 2006.161.07:51:54.21#ibcon#about to read 6, iclass 10, count 0 2006.161.07:51:54.21#ibcon#read 6, iclass 10, count 0 2006.161.07:51:54.21#ibcon#end of sib2, iclass 10, count 0 2006.161.07:51:54.21#ibcon#*after write, iclass 10, count 0 2006.161.07:51:54.21#ibcon#*before return 0, iclass 10, count 0 2006.161.07:51:54.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:54.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.07:51:54.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:51:54.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:51:54.21$vc4f8/vbbw=wide 2006.161.07:51:54.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:51:54.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:51:54.21#ibcon#ireg 8 cls_cnt 0 2006.161.07:51:54.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:51:54.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:51:54.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:51:54.28#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:51:54.28#ibcon#first serial, iclass 12, count 0 2006.161.07:51:54.28#ibcon#enter sib2, iclass 12, count 0 2006.161.07:51:54.28#ibcon#flushed, iclass 12, count 0 2006.161.07:51:54.28#ibcon#about to write, iclass 12, count 0 2006.161.07:51:54.28#ibcon#wrote, iclass 12, count 0 2006.161.07:51:54.28#ibcon#about to read 3, iclass 12, count 0 2006.161.07:51:54.30#ibcon#read 3, iclass 12, count 0 2006.161.07:51:54.30#ibcon#about to read 4, iclass 12, count 0 2006.161.07:51:54.30#ibcon#read 4, iclass 12, count 0 2006.161.07:51:54.30#ibcon#about to read 5, iclass 12, count 0 2006.161.07:51:54.30#ibcon#read 5, iclass 12, count 0 2006.161.07:51:54.30#ibcon#about to read 6, iclass 12, count 0 2006.161.07:51:54.30#ibcon#read 6, iclass 12, count 0 2006.161.07:51:54.30#ibcon#end of sib2, iclass 12, count 0 2006.161.07:51:54.30#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:51:54.30#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:51:54.30#ibcon#[27=BW32\r\n] 2006.161.07:51:54.30#ibcon#*before write, iclass 12, count 0 2006.161.07:51:54.30#ibcon#enter sib2, iclass 12, count 0 2006.161.07:51:54.30#ibcon#flushed, iclass 12, count 0 2006.161.07:51:54.30#ibcon#about to write, iclass 12, count 0 2006.161.07:51:54.30#ibcon#wrote, iclass 12, count 0 2006.161.07:51:54.30#ibcon#about to read 3, iclass 12, count 0 2006.161.07:51:54.33#ibcon#read 3, iclass 12, count 0 2006.161.07:51:54.33#ibcon#about to read 4, iclass 12, count 0 2006.161.07:51:54.33#ibcon#read 4, iclass 12, count 0 2006.161.07:51:54.33#ibcon#about to read 5, iclass 12, count 0 2006.161.07:51:54.33#ibcon#read 5, iclass 12, count 0 2006.161.07:51:54.33#ibcon#about to read 6, iclass 12, count 0 2006.161.07:51:54.33#ibcon#read 6, iclass 12, count 0 2006.161.07:51:54.33#ibcon#end of sib2, iclass 12, count 0 2006.161.07:51:54.33#ibcon#*after write, iclass 12, count 0 2006.161.07:51:54.33#ibcon#*before return 0, iclass 12, count 0 2006.161.07:51:54.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:51:54.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:51:54.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:51:54.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:51:54.33$4f8m12a/ifd4f 2006.161.07:51:54.33$ifd4f/lo= 2006.161.07:51:54.33$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:51:54.33$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:51:54.33$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:51:54.33$ifd4f/patch= 2006.161.07:51:54.33$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:51:54.33$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:51:54.33$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:51:54.33$4f8m12a/"form=m,16.000,1:2 2006.161.07:51:54.33$4f8m12a/"tpicd 2006.161.07:51:54.33$4f8m12a/echo=off 2006.161.07:51:54.33$4f8m12a/xlog=off 2006.161.07:51:54.33:!2006.161.07:53:20 2006.161.07:52:05.14#trakl#Source acquired 2006.161.07:52:05.14#flagr#flagr/antenna,acquired 2006.161.07:53:20.00:preob 2006.161.07:53:21.14/onsource/TRACKING 2006.161.07:53:21.14:!2006.161.07:53:30 2006.161.07:53:30.00:data_valid=on 2006.161.07:53:30.00:midob 2006.161.07:53:30.14/onsource/TRACKING 2006.161.07:53:30.14/wx/24.04,1002.1,86 2006.161.07:53:30.29/cable/+6.5000E-03 2006.161.07:53:31.38/va/01,08,usb,yes,29,31 2006.161.07:53:31.38/va/02,07,usb,yes,29,31 2006.161.07:53:31.38/va/03,06,usb,yes,31,31 2006.161.07:53:31.38/va/04,07,usb,yes,30,32 2006.161.07:53:31.38/va/05,07,usb,yes,30,32 2006.161.07:53:31.38/va/06,06,usb,yes,29,29 2006.161.07:53:31.38/va/07,06,usb,yes,30,30 2006.161.07:53:31.38/va/08,07,usb,yes,28,28 2006.161.07:53:31.61/valo/01,532.99,yes,locked 2006.161.07:53:31.61/valo/02,572.99,yes,locked 2006.161.07:53:31.61/valo/03,672.99,yes,locked 2006.161.07:53:31.61/valo/04,832.99,yes,locked 2006.161.07:53:31.61/valo/05,652.99,yes,locked 2006.161.07:53:31.61/valo/06,772.99,yes,locked 2006.161.07:53:31.61/valo/07,832.99,yes,locked 2006.161.07:53:31.61/valo/08,852.99,yes,locked 2006.161.07:53:32.70/vb/01,04,usb,yes,29,28 2006.161.07:53:32.70/vb/02,04,usb,yes,31,32 2006.161.07:53:32.70/vb/03,04,usb,yes,27,31 2006.161.07:53:32.70/vb/04,04,usb,yes,28,28 2006.161.07:53:32.70/vb/05,04,usb,yes,27,31 2006.161.07:53:32.70/vb/06,04,usb,yes,28,31 2006.161.07:53:32.70/vb/07,04,usb,yes,30,30 2006.161.07:53:32.70/vb/08,04,usb,yes,27,31 2006.161.07:53:32.94/vblo/01,632.99,yes,locked 2006.161.07:53:32.94/vblo/02,640.99,yes,locked 2006.161.07:53:32.94/vblo/03,656.99,yes,locked 2006.161.07:53:32.94/vblo/04,712.99,yes,locked 2006.161.07:53:32.94/vblo/05,744.99,yes,locked 2006.161.07:53:32.94/vblo/06,752.99,yes,locked 2006.161.07:53:32.94/vblo/07,734.99,yes,locked 2006.161.07:53:32.94/vblo/08,744.99,yes,locked 2006.161.07:53:33.09/vabw/8 2006.161.07:53:33.24/vbbw/8 2006.161.07:53:33.33/xfe/off,on,14.7 2006.161.07:53:33.70/ifatt/23,28,28,28 2006.161.07:53:34.08/fmout-gps/S +4.45E-07 2006.161.07:53:34.12:!2006.161.07:54:30 2006.161.07:54:30.00:data_valid=off 2006.161.07:54:30.00:postob 2006.161.07:54:30.08/cable/+6.4994E-03 2006.161.07:54:30.08/wx/24.04,1002.1,86 2006.161.07:54:31.08/fmout-gps/S +4.46E-07 2006.161.07:54:31.08:scan_name=161-0757,k06161,60 2006.161.07:54:31.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.161.07:54:31.14#flagr#flagr/antenna,new-source 2006.161.07:54:32.14:checkk5 2006.161.07:54:32.76/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:54:33.17/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:54:33.60/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:54:34.03/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:54:34.44/chk_obsdata//k5ts1/T1610753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.07:54:34.82/chk_obsdata//k5ts2/T1610753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.07:54:35.21/chk_obsdata//k5ts3/T1610753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.07:54:35.67/chk_obsdata//k5ts4/T1610753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.07:54:36.68/k5log//k5ts1_log_newline 2006.161.07:54:37.49/k5log//k5ts2_log_newline 2006.161.07:54:38.23/k5log//k5ts3_log_newline 2006.161.07:54:39.02/k5log//k5ts4_log_newline 2006.161.07:54:39.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:54:39.09:4f8m12a=2 2006.161.07:54:39.09$4f8m12a/echo=on 2006.161.07:54:39.09$4f8m12a/pcalon 2006.161.07:54:39.09$pcalon/"no phase cal control is implemented here 2006.161.07:54:39.09$4f8m12a/"tpicd=stop 2006.161.07:54:39.09$4f8m12a/vc4f8 2006.161.07:54:39.09$vc4f8/valo=1,532.99 2006.161.07:54:39.09#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.07:54:39.09#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.07:54:39.09#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:39.09#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:39.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:39.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:39.09#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:54:39.09#ibcon#first serial, iclass 5, count 0 2006.161.07:54:39.09#ibcon#enter sib2, iclass 5, count 0 2006.161.07:54:39.09#ibcon#flushed, iclass 5, count 0 2006.161.07:54:39.09#ibcon#about to write, iclass 5, count 0 2006.161.07:54:39.09#ibcon#wrote, iclass 5, count 0 2006.161.07:54:39.09#ibcon#about to read 3, iclass 5, count 0 2006.161.07:54:39.11#ibcon#read 3, iclass 5, count 0 2006.161.07:54:39.11#ibcon#about to read 4, iclass 5, count 0 2006.161.07:54:39.11#ibcon#read 4, iclass 5, count 0 2006.161.07:54:39.11#ibcon#about to read 5, iclass 5, count 0 2006.161.07:54:39.11#ibcon#read 5, iclass 5, count 0 2006.161.07:54:39.11#ibcon#about to read 6, iclass 5, count 0 2006.161.07:54:39.11#ibcon#read 6, iclass 5, count 0 2006.161.07:54:39.11#ibcon#end of sib2, iclass 5, count 0 2006.161.07:54:39.11#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:54:39.11#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:54:39.11#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:54:39.11#ibcon#*before write, iclass 5, count 0 2006.161.07:54:39.11#ibcon#enter sib2, iclass 5, count 0 2006.161.07:54:39.11#ibcon#flushed, iclass 5, count 0 2006.161.07:54:39.11#ibcon#about to write, iclass 5, count 0 2006.161.07:54:39.11#ibcon#wrote, iclass 5, count 0 2006.161.07:54:39.11#ibcon#about to read 3, iclass 5, count 0 2006.161.07:54:39.16#ibcon#read 3, iclass 5, count 0 2006.161.07:54:39.16#ibcon#about to read 4, iclass 5, count 0 2006.161.07:54:39.16#ibcon#read 4, iclass 5, count 0 2006.161.07:54:39.16#ibcon#about to read 5, iclass 5, count 0 2006.161.07:54:39.16#ibcon#read 5, iclass 5, count 0 2006.161.07:54:39.16#ibcon#about to read 6, iclass 5, count 0 2006.161.07:54:39.16#ibcon#read 6, iclass 5, count 0 2006.161.07:54:39.16#ibcon#end of sib2, iclass 5, count 0 2006.161.07:54:39.16#ibcon#*after write, iclass 5, count 0 2006.161.07:54:39.16#ibcon#*before return 0, iclass 5, count 0 2006.161.07:54:39.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:39.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:39.16#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:54:39.16#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:54:39.16$vc4f8/va=1,8 2006.161.07:54:39.16#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.07:54:39.16#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.07:54:39.16#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:39.16#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:39.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:39.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:39.16#ibcon#enter wrdev, iclass 7, count 2 2006.161.07:54:39.16#ibcon#first serial, iclass 7, count 2 2006.161.07:54:39.16#ibcon#enter sib2, iclass 7, count 2 2006.161.07:54:39.16#ibcon#flushed, iclass 7, count 2 2006.161.07:54:39.16#ibcon#about to write, iclass 7, count 2 2006.161.07:54:39.16#ibcon#wrote, iclass 7, count 2 2006.161.07:54:39.16#ibcon#about to read 3, iclass 7, count 2 2006.161.07:54:39.18#ibcon#read 3, iclass 7, count 2 2006.161.07:54:39.18#ibcon#about to read 4, iclass 7, count 2 2006.161.07:54:39.18#ibcon#read 4, iclass 7, count 2 2006.161.07:54:39.18#ibcon#about to read 5, iclass 7, count 2 2006.161.07:54:39.18#ibcon#read 5, iclass 7, count 2 2006.161.07:54:39.18#ibcon#about to read 6, iclass 7, count 2 2006.161.07:54:39.18#ibcon#read 6, iclass 7, count 2 2006.161.07:54:39.18#ibcon#end of sib2, iclass 7, count 2 2006.161.07:54:39.18#ibcon#*mode == 0, iclass 7, count 2 2006.161.07:54:39.18#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.07:54:39.18#ibcon#[25=AT01-08\r\n] 2006.161.07:54:39.18#ibcon#*before write, iclass 7, count 2 2006.161.07:54:39.18#ibcon#enter sib2, iclass 7, count 2 2006.161.07:54:39.18#ibcon#flushed, iclass 7, count 2 2006.161.07:54:39.18#ibcon#about to write, iclass 7, count 2 2006.161.07:54:39.18#ibcon#wrote, iclass 7, count 2 2006.161.07:54:39.18#ibcon#about to read 3, iclass 7, count 2 2006.161.07:54:39.21#ibcon#read 3, iclass 7, count 2 2006.161.07:54:39.21#ibcon#about to read 4, iclass 7, count 2 2006.161.07:54:39.21#ibcon#read 4, iclass 7, count 2 2006.161.07:54:39.21#ibcon#about to read 5, iclass 7, count 2 2006.161.07:54:39.21#ibcon#read 5, iclass 7, count 2 2006.161.07:54:39.21#ibcon#about to read 6, iclass 7, count 2 2006.161.07:54:39.21#ibcon#read 6, iclass 7, count 2 2006.161.07:54:39.21#ibcon#end of sib2, iclass 7, count 2 2006.161.07:54:39.21#ibcon#*after write, iclass 7, count 2 2006.161.07:54:39.21#ibcon#*before return 0, iclass 7, count 2 2006.161.07:54:39.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:39.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:39.21#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.07:54:39.21#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:39.21#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:39.33#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:39.33#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:39.33#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:54:39.33#ibcon#first serial, iclass 7, count 0 2006.161.07:54:39.33#ibcon#enter sib2, iclass 7, count 0 2006.161.07:54:39.33#ibcon#flushed, iclass 7, count 0 2006.161.07:54:39.33#ibcon#about to write, iclass 7, count 0 2006.161.07:54:39.33#ibcon#wrote, iclass 7, count 0 2006.161.07:54:39.33#ibcon#about to read 3, iclass 7, count 0 2006.161.07:54:39.35#ibcon#read 3, iclass 7, count 0 2006.161.07:54:39.35#ibcon#about to read 4, iclass 7, count 0 2006.161.07:54:39.35#ibcon#read 4, iclass 7, count 0 2006.161.07:54:39.35#ibcon#about to read 5, iclass 7, count 0 2006.161.07:54:39.35#ibcon#read 5, iclass 7, count 0 2006.161.07:54:39.35#ibcon#about to read 6, iclass 7, count 0 2006.161.07:54:39.35#ibcon#read 6, iclass 7, count 0 2006.161.07:54:39.35#ibcon#end of sib2, iclass 7, count 0 2006.161.07:54:39.35#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:54:39.35#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:54:39.35#ibcon#[25=USB\r\n] 2006.161.07:54:39.35#ibcon#*before write, iclass 7, count 0 2006.161.07:54:39.35#ibcon#enter sib2, iclass 7, count 0 2006.161.07:54:39.35#ibcon#flushed, iclass 7, count 0 2006.161.07:54:39.35#ibcon#about to write, iclass 7, count 0 2006.161.07:54:39.35#ibcon#wrote, iclass 7, count 0 2006.161.07:54:39.35#ibcon#about to read 3, iclass 7, count 0 2006.161.07:54:39.38#ibcon#read 3, iclass 7, count 0 2006.161.07:54:39.38#ibcon#about to read 4, iclass 7, count 0 2006.161.07:54:39.38#ibcon#read 4, iclass 7, count 0 2006.161.07:54:39.38#ibcon#about to read 5, iclass 7, count 0 2006.161.07:54:39.38#ibcon#read 5, iclass 7, count 0 2006.161.07:54:39.38#ibcon#about to read 6, iclass 7, count 0 2006.161.07:54:39.38#ibcon#read 6, iclass 7, count 0 2006.161.07:54:39.38#ibcon#end of sib2, iclass 7, count 0 2006.161.07:54:39.38#ibcon#*after write, iclass 7, count 0 2006.161.07:54:39.38#ibcon#*before return 0, iclass 7, count 0 2006.161.07:54:39.38#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:39.38#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:39.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:54:39.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:54:39.38$vc4f8/valo=2,572.99 2006.161.07:54:39.38#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:54:39.38#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:54:39.38#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:39.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:39.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:39.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:39.38#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:54:39.38#ibcon#first serial, iclass 11, count 0 2006.161.07:54:39.38#ibcon#enter sib2, iclass 11, count 0 2006.161.07:54:39.38#ibcon#flushed, iclass 11, count 0 2006.161.07:54:39.38#ibcon#about to write, iclass 11, count 0 2006.161.07:54:39.38#ibcon#wrote, iclass 11, count 0 2006.161.07:54:39.38#ibcon#about to read 3, iclass 11, count 0 2006.161.07:54:39.40#ibcon#read 3, iclass 11, count 0 2006.161.07:54:39.40#ibcon#about to read 4, iclass 11, count 0 2006.161.07:54:39.40#ibcon#read 4, iclass 11, count 0 2006.161.07:54:39.40#ibcon#about to read 5, iclass 11, count 0 2006.161.07:54:39.40#ibcon#read 5, iclass 11, count 0 2006.161.07:54:39.40#ibcon#about to read 6, iclass 11, count 0 2006.161.07:54:39.40#ibcon#read 6, iclass 11, count 0 2006.161.07:54:39.40#ibcon#end of sib2, iclass 11, count 0 2006.161.07:54:39.40#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:54:39.40#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:54:39.40#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:54:39.40#ibcon#*before write, iclass 11, count 0 2006.161.07:54:39.40#ibcon#enter sib2, iclass 11, count 0 2006.161.07:54:39.40#ibcon#flushed, iclass 11, count 0 2006.161.07:54:39.40#ibcon#about to write, iclass 11, count 0 2006.161.07:54:39.40#ibcon#wrote, iclass 11, count 0 2006.161.07:54:39.40#ibcon#about to read 3, iclass 11, count 0 2006.161.07:54:39.44#ibcon#read 3, iclass 11, count 0 2006.161.07:54:39.44#ibcon#about to read 4, iclass 11, count 0 2006.161.07:54:39.44#ibcon#read 4, iclass 11, count 0 2006.161.07:54:39.44#ibcon#about to read 5, iclass 11, count 0 2006.161.07:54:39.44#ibcon#read 5, iclass 11, count 0 2006.161.07:54:39.44#ibcon#about to read 6, iclass 11, count 0 2006.161.07:54:39.44#ibcon#read 6, iclass 11, count 0 2006.161.07:54:39.44#ibcon#end of sib2, iclass 11, count 0 2006.161.07:54:39.44#ibcon#*after write, iclass 11, count 0 2006.161.07:54:39.44#ibcon#*before return 0, iclass 11, count 0 2006.161.07:54:39.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:39.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:39.44#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:54:39.44#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:54:39.44$vc4f8/va=2,7 2006.161.07:54:39.44#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:54:39.44#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:54:39.44#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:39.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:39.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:39.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:39.50#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:54:39.50#ibcon#first serial, iclass 13, count 2 2006.161.07:54:39.50#ibcon#enter sib2, iclass 13, count 2 2006.161.07:54:39.50#ibcon#flushed, iclass 13, count 2 2006.161.07:54:39.50#ibcon#about to write, iclass 13, count 2 2006.161.07:54:39.50#ibcon#wrote, iclass 13, count 2 2006.161.07:54:39.50#ibcon#about to read 3, iclass 13, count 2 2006.161.07:54:39.52#ibcon#read 3, iclass 13, count 2 2006.161.07:54:39.52#ibcon#about to read 4, iclass 13, count 2 2006.161.07:54:39.52#ibcon#read 4, iclass 13, count 2 2006.161.07:54:39.52#ibcon#about to read 5, iclass 13, count 2 2006.161.07:54:39.52#ibcon#read 5, iclass 13, count 2 2006.161.07:54:39.52#ibcon#about to read 6, iclass 13, count 2 2006.161.07:54:39.52#ibcon#read 6, iclass 13, count 2 2006.161.07:54:39.52#ibcon#end of sib2, iclass 13, count 2 2006.161.07:54:39.52#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:54:39.52#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:54:39.52#ibcon#[25=AT02-07\r\n] 2006.161.07:54:39.52#ibcon#*before write, iclass 13, count 2 2006.161.07:54:39.52#ibcon#enter sib2, iclass 13, count 2 2006.161.07:54:39.52#ibcon#flushed, iclass 13, count 2 2006.161.07:54:39.52#ibcon#about to write, iclass 13, count 2 2006.161.07:54:39.52#ibcon#wrote, iclass 13, count 2 2006.161.07:54:39.52#ibcon#about to read 3, iclass 13, count 2 2006.161.07:54:39.55#ibcon#read 3, iclass 13, count 2 2006.161.07:54:39.55#ibcon#about to read 4, iclass 13, count 2 2006.161.07:54:39.55#ibcon#read 4, iclass 13, count 2 2006.161.07:54:39.55#ibcon#about to read 5, iclass 13, count 2 2006.161.07:54:39.55#ibcon#read 5, iclass 13, count 2 2006.161.07:54:39.55#ibcon#about to read 6, iclass 13, count 2 2006.161.07:54:39.55#ibcon#read 6, iclass 13, count 2 2006.161.07:54:39.55#ibcon#end of sib2, iclass 13, count 2 2006.161.07:54:39.55#ibcon#*after write, iclass 13, count 2 2006.161.07:54:39.55#ibcon#*before return 0, iclass 13, count 2 2006.161.07:54:39.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:39.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:39.55#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:54:39.55#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:39.55#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:39.67#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:39.67#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:39.67#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:54:39.67#ibcon#first serial, iclass 13, count 0 2006.161.07:54:39.67#ibcon#enter sib2, iclass 13, count 0 2006.161.07:54:39.67#ibcon#flushed, iclass 13, count 0 2006.161.07:54:39.67#ibcon#about to write, iclass 13, count 0 2006.161.07:54:39.67#ibcon#wrote, iclass 13, count 0 2006.161.07:54:39.67#ibcon#about to read 3, iclass 13, count 0 2006.161.07:54:39.69#ibcon#read 3, iclass 13, count 0 2006.161.07:54:39.69#ibcon#about to read 4, iclass 13, count 0 2006.161.07:54:39.69#ibcon#read 4, iclass 13, count 0 2006.161.07:54:39.69#ibcon#about to read 5, iclass 13, count 0 2006.161.07:54:39.69#ibcon#read 5, iclass 13, count 0 2006.161.07:54:39.69#ibcon#about to read 6, iclass 13, count 0 2006.161.07:54:39.69#ibcon#read 6, iclass 13, count 0 2006.161.07:54:39.69#ibcon#end of sib2, iclass 13, count 0 2006.161.07:54:39.69#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:54:39.69#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:54:39.69#ibcon#[25=USB\r\n] 2006.161.07:54:39.69#ibcon#*before write, iclass 13, count 0 2006.161.07:54:39.69#ibcon#enter sib2, iclass 13, count 0 2006.161.07:54:39.69#ibcon#flushed, iclass 13, count 0 2006.161.07:54:39.69#ibcon#about to write, iclass 13, count 0 2006.161.07:54:39.69#ibcon#wrote, iclass 13, count 0 2006.161.07:54:39.69#ibcon#about to read 3, iclass 13, count 0 2006.161.07:54:39.72#ibcon#read 3, iclass 13, count 0 2006.161.07:54:39.72#ibcon#about to read 4, iclass 13, count 0 2006.161.07:54:39.72#ibcon#read 4, iclass 13, count 0 2006.161.07:54:39.72#ibcon#about to read 5, iclass 13, count 0 2006.161.07:54:39.72#ibcon#read 5, iclass 13, count 0 2006.161.07:54:39.72#ibcon#about to read 6, iclass 13, count 0 2006.161.07:54:39.72#ibcon#read 6, iclass 13, count 0 2006.161.07:54:39.72#ibcon#end of sib2, iclass 13, count 0 2006.161.07:54:39.72#ibcon#*after write, iclass 13, count 0 2006.161.07:54:39.72#ibcon#*before return 0, iclass 13, count 0 2006.161.07:54:39.72#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:39.72#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:39.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:54:39.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:54:39.72$vc4f8/valo=3,672.99 2006.161.07:54:39.72#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.07:54:39.72#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.07:54:39.72#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:39.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:39.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:39.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:39.72#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:54:39.72#ibcon#first serial, iclass 15, count 0 2006.161.07:54:39.72#ibcon#enter sib2, iclass 15, count 0 2006.161.07:54:39.72#ibcon#flushed, iclass 15, count 0 2006.161.07:54:39.72#ibcon#about to write, iclass 15, count 0 2006.161.07:54:39.72#ibcon#wrote, iclass 15, count 0 2006.161.07:54:39.72#ibcon#about to read 3, iclass 15, count 0 2006.161.07:54:39.74#ibcon#read 3, iclass 15, count 0 2006.161.07:54:39.74#ibcon#about to read 4, iclass 15, count 0 2006.161.07:54:39.74#ibcon#read 4, iclass 15, count 0 2006.161.07:54:39.74#ibcon#about to read 5, iclass 15, count 0 2006.161.07:54:39.74#ibcon#read 5, iclass 15, count 0 2006.161.07:54:39.74#ibcon#about to read 6, iclass 15, count 0 2006.161.07:54:39.74#ibcon#read 6, iclass 15, count 0 2006.161.07:54:39.74#ibcon#end of sib2, iclass 15, count 0 2006.161.07:54:39.74#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:54:39.74#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:54:39.74#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:54:39.74#ibcon#*before write, iclass 15, count 0 2006.161.07:54:39.74#ibcon#enter sib2, iclass 15, count 0 2006.161.07:54:39.74#ibcon#flushed, iclass 15, count 0 2006.161.07:54:39.74#ibcon#about to write, iclass 15, count 0 2006.161.07:54:39.74#ibcon#wrote, iclass 15, count 0 2006.161.07:54:39.74#ibcon#about to read 3, iclass 15, count 0 2006.161.07:54:39.78#ibcon#read 3, iclass 15, count 0 2006.161.07:54:39.78#ibcon#about to read 4, iclass 15, count 0 2006.161.07:54:39.78#ibcon#read 4, iclass 15, count 0 2006.161.07:54:39.78#ibcon#about to read 5, iclass 15, count 0 2006.161.07:54:39.78#ibcon#read 5, iclass 15, count 0 2006.161.07:54:39.78#ibcon#about to read 6, iclass 15, count 0 2006.161.07:54:39.78#ibcon#read 6, iclass 15, count 0 2006.161.07:54:39.78#ibcon#end of sib2, iclass 15, count 0 2006.161.07:54:39.78#ibcon#*after write, iclass 15, count 0 2006.161.07:54:39.78#ibcon#*before return 0, iclass 15, count 0 2006.161.07:54:39.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:39.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:39.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:54:39.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:54:39.78$vc4f8/va=3,6 2006.161.07:54:39.78#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.07:54:39.78#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.07:54:39.78#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:39.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:39.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:39.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:39.84#ibcon#enter wrdev, iclass 17, count 2 2006.161.07:54:39.84#ibcon#first serial, iclass 17, count 2 2006.161.07:54:39.84#ibcon#enter sib2, iclass 17, count 2 2006.161.07:54:39.84#ibcon#flushed, iclass 17, count 2 2006.161.07:54:39.84#ibcon#about to write, iclass 17, count 2 2006.161.07:54:39.84#ibcon#wrote, iclass 17, count 2 2006.161.07:54:39.84#ibcon#about to read 3, iclass 17, count 2 2006.161.07:54:39.86#ibcon#read 3, iclass 17, count 2 2006.161.07:54:39.86#ibcon#about to read 4, iclass 17, count 2 2006.161.07:54:39.86#ibcon#read 4, iclass 17, count 2 2006.161.07:54:39.86#ibcon#about to read 5, iclass 17, count 2 2006.161.07:54:39.86#ibcon#read 5, iclass 17, count 2 2006.161.07:54:39.86#ibcon#about to read 6, iclass 17, count 2 2006.161.07:54:39.86#ibcon#read 6, iclass 17, count 2 2006.161.07:54:39.86#ibcon#end of sib2, iclass 17, count 2 2006.161.07:54:39.86#ibcon#*mode == 0, iclass 17, count 2 2006.161.07:54:39.86#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.07:54:39.86#ibcon#[25=AT03-06\r\n] 2006.161.07:54:39.86#ibcon#*before write, iclass 17, count 2 2006.161.07:54:39.86#ibcon#enter sib2, iclass 17, count 2 2006.161.07:54:39.86#ibcon#flushed, iclass 17, count 2 2006.161.07:54:39.86#ibcon#about to write, iclass 17, count 2 2006.161.07:54:39.86#ibcon#wrote, iclass 17, count 2 2006.161.07:54:39.86#ibcon#about to read 3, iclass 17, count 2 2006.161.07:54:39.89#ibcon#read 3, iclass 17, count 2 2006.161.07:54:39.89#ibcon#about to read 4, iclass 17, count 2 2006.161.07:54:39.89#ibcon#read 4, iclass 17, count 2 2006.161.07:54:39.89#ibcon#about to read 5, iclass 17, count 2 2006.161.07:54:39.89#ibcon#read 5, iclass 17, count 2 2006.161.07:54:39.89#ibcon#about to read 6, iclass 17, count 2 2006.161.07:54:39.89#ibcon#read 6, iclass 17, count 2 2006.161.07:54:39.89#ibcon#end of sib2, iclass 17, count 2 2006.161.07:54:39.89#ibcon#*after write, iclass 17, count 2 2006.161.07:54:39.89#ibcon#*before return 0, iclass 17, count 2 2006.161.07:54:39.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:39.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:39.89#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.07:54:39.89#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:39.89#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:40.01#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:40.01#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:40.01#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:54:40.01#ibcon#first serial, iclass 17, count 0 2006.161.07:54:40.01#ibcon#enter sib2, iclass 17, count 0 2006.161.07:54:40.01#ibcon#flushed, iclass 17, count 0 2006.161.07:54:40.01#ibcon#about to write, iclass 17, count 0 2006.161.07:54:40.01#ibcon#wrote, iclass 17, count 0 2006.161.07:54:40.01#ibcon#about to read 3, iclass 17, count 0 2006.161.07:54:40.03#ibcon#read 3, iclass 17, count 0 2006.161.07:54:40.03#ibcon#about to read 4, iclass 17, count 0 2006.161.07:54:40.03#ibcon#read 4, iclass 17, count 0 2006.161.07:54:40.03#ibcon#about to read 5, iclass 17, count 0 2006.161.07:54:40.03#ibcon#read 5, iclass 17, count 0 2006.161.07:54:40.03#ibcon#about to read 6, iclass 17, count 0 2006.161.07:54:40.03#ibcon#read 6, iclass 17, count 0 2006.161.07:54:40.03#ibcon#end of sib2, iclass 17, count 0 2006.161.07:54:40.03#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:54:40.03#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:54:40.03#ibcon#[25=USB\r\n] 2006.161.07:54:40.03#ibcon#*before write, iclass 17, count 0 2006.161.07:54:40.03#ibcon#enter sib2, iclass 17, count 0 2006.161.07:54:40.03#ibcon#flushed, iclass 17, count 0 2006.161.07:54:40.03#ibcon#about to write, iclass 17, count 0 2006.161.07:54:40.03#ibcon#wrote, iclass 17, count 0 2006.161.07:54:40.03#ibcon#about to read 3, iclass 17, count 0 2006.161.07:54:40.06#ibcon#read 3, iclass 17, count 0 2006.161.07:54:40.06#ibcon#about to read 4, iclass 17, count 0 2006.161.07:54:40.06#ibcon#read 4, iclass 17, count 0 2006.161.07:54:40.06#ibcon#about to read 5, iclass 17, count 0 2006.161.07:54:40.06#ibcon#read 5, iclass 17, count 0 2006.161.07:54:40.06#ibcon#about to read 6, iclass 17, count 0 2006.161.07:54:40.06#ibcon#read 6, iclass 17, count 0 2006.161.07:54:40.06#ibcon#end of sib2, iclass 17, count 0 2006.161.07:54:40.06#ibcon#*after write, iclass 17, count 0 2006.161.07:54:40.06#ibcon#*before return 0, iclass 17, count 0 2006.161.07:54:40.06#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:40.06#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:40.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:54:40.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:54:40.06$vc4f8/valo=4,832.99 2006.161.07:54:40.06#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:54:40.06#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:54:40.06#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:40.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:40.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:40.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:40.06#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:54:40.06#ibcon#first serial, iclass 19, count 0 2006.161.07:54:40.06#ibcon#enter sib2, iclass 19, count 0 2006.161.07:54:40.06#ibcon#flushed, iclass 19, count 0 2006.161.07:54:40.06#ibcon#about to write, iclass 19, count 0 2006.161.07:54:40.06#ibcon#wrote, iclass 19, count 0 2006.161.07:54:40.06#ibcon#about to read 3, iclass 19, count 0 2006.161.07:54:40.08#ibcon#read 3, iclass 19, count 0 2006.161.07:54:40.08#ibcon#about to read 4, iclass 19, count 0 2006.161.07:54:40.08#ibcon#read 4, iclass 19, count 0 2006.161.07:54:40.08#ibcon#about to read 5, iclass 19, count 0 2006.161.07:54:40.08#ibcon#read 5, iclass 19, count 0 2006.161.07:54:40.08#ibcon#about to read 6, iclass 19, count 0 2006.161.07:54:40.08#ibcon#read 6, iclass 19, count 0 2006.161.07:54:40.08#ibcon#end of sib2, iclass 19, count 0 2006.161.07:54:40.08#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:54:40.08#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:54:40.08#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:54:40.08#ibcon#*before write, iclass 19, count 0 2006.161.07:54:40.08#ibcon#enter sib2, iclass 19, count 0 2006.161.07:54:40.08#ibcon#flushed, iclass 19, count 0 2006.161.07:54:40.08#ibcon#about to write, iclass 19, count 0 2006.161.07:54:40.08#ibcon#wrote, iclass 19, count 0 2006.161.07:54:40.08#ibcon#about to read 3, iclass 19, count 0 2006.161.07:54:40.12#ibcon#read 3, iclass 19, count 0 2006.161.07:54:40.12#ibcon#about to read 4, iclass 19, count 0 2006.161.07:54:40.12#ibcon#read 4, iclass 19, count 0 2006.161.07:54:40.12#ibcon#about to read 5, iclass 19, count 0 2006.161.07:54:40.12#ibcon#read 5, iclass 19, count 0 2006.161.07:54:40.12#ibcon#about to read 6, iclass 19, count 0 2006.161.07:54:40.12#ibcon#read 6, iclass 19, count 0 2006.161.07:54:40.12#ibcon#end of sib2, iclass 19, count 0 2006.161.07:54:40.12#ibcon#*after write, iclass 19, count 0 2006.161.07:54:40.12#ibcon#*before return 0, iclass 19, count 0 2006.161.07:54:40.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:40.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:40.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:54:40.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:54:40.12$vc4f8/va=4,7 2006.161.07:54:40.12#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:54:40.12#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:54:40.12#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:40.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:40.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:40.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:40.18#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:54:40.18#ibcon#first serial, iclass 21, count 2 2006.161.07:54:40.18#ibcon#enter sib2, iclass 21, count 2 2006.161.07:54:40.18#ibcon#flushed, iclass 21, count 2 2006.161.07:54:40.18#ibcon#about to write, iclass 21, count 2 2006.161.07:54:40.18#ibcon#wrote, iclass 21, count 2 2006.161.07:54:40.18#ibcon#about to read 3, iclass 21, count 2 2006.161.07:54:40.20#ibcon#read 3, iclass 21, count 2 2006.161.07:54:40.20#ibcon#about to read 4, iclass 21, count 2 2006.161.07:54:40.20#ibcon#read 4, iclass 21, count 2 2006.161.07:54:40.20#ibcon#about to read 5, iclass 21, count 2 2006.161.07:54:40.20#ibcon#read 5, iclass 21, count 2 2006.161.07:54:40.20#ibcon#about to read 6, iclass 21, count 2 2006.161.07:54:40.20#ibcon#read 6, iclass 21, count 2 2006.161.07:54:40.20#ibcon#end of sib2, iclass 21, count 2 2006.161.07:54:40.20#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:54:40.20#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:54:40.20#ibcon#[25=AT04-07\r\n] 2006.161.07:54:40.20#ibcon#*before write, iclass 21, count 2 2006.161.07:54:40.20#ibcon#enter sib2, iclass 21, count 2 2006.161.07:54:40.20#ibcon#flushed, iclass 21, count 2 2006.161.07:54:40.20#ibcon#about to write, iclass 21, count 2 2006.161.07:54:40.20#ibcon#wrote, iclass 21, count 2 2006.161.07:54:40.20#ibcon#about to read 3, iclass 21, count 2 2006.161.07:54:40.23#ibcon#read 3, iclass 21, count 2 2006.161.07:54:40.23#ibcon#about to read 4, iclass 21, count 2 2006.161.07:54:40.23#ibcon#read 4, iclass 21, count 2 2006.161.07:54:40.23#ibcon#about to read 5, iclass 21, count 2 2006.161.07:54:40.23#ibcon#read 5, iclass 21, count 2 2006.161.07:54:40.23#ibcon#about to read 6, iclass 21, count 2 2006.161.07:54:40.23#ibcon#read 6, iclass 21, count 2 2006.161.07:54:40.23#ibcon#end of sib2, iclass 21, count 2 2006.161.07:54:40.23#ibcon#*after write, iclass 21, count 2 2006.161.07:54:40.23#ibcon#*before return 0, iclass 21, count 2 2006.161.07:54:40.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:40.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:40.23#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:54:40.23#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:40.23#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:40.35#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:40.35#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:40.35#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:54:40.35#ibcon#first serial, iclass 21, count 0 2006.161.07:54:40.35#ibcon#enter sib2, iclass 21, count 0 2006.161.07:54:40.35#ibcon#flushed, iclass 21, count 0 2006.161.07:54:40.35#ibcon#about to write, iclass 21, count 0 2006.161.07:54:40.35#ibcon#wrote, iclass 21, count 0 2006.161.07:54:40.35#ibcon#about to read 3, iclass 21, count 0 2006.161.07:54:40.37#ibcon#read 3, iclass 21, count 0 2006.161.07:54:40.37#ibcon#about to read 4, iclass 21, count 0 2006.161.07:54:40.37#ibcon#read 4, iclass 21, count 0 2006.161.07:54:40.37#ibcon#about to read 5, iclass 21, count 0 2006.161.07:54:40.37#ibcon#read 5, iclass 21, count 0 2006.161.07:54:40.37#ibcon#about to read 6, iclass 21, count 0 2006.161.07:54:40.37#ibcon#read 6, iclass 21, count 0 2006.161.07:54:40.37#ibcon#end of sib2, iclass 21, count 0 2006.161.07:54:40.37#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:54:40.37#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:54:40.37#ibcon#[25=USB\r\n] 2006.161.07:54:40.37#ibcon#*before write, iclass 21, count 0 2006.161.07:54:40.37#ibcon#enter sib2, iclass 21, count 0 2006.161.07:54:40.37#ibcon#flushed, iclass 21, count 0 2006.161.07:54:40.37#ibcon#about to write, iclass 21, count 0 2006.161.07:54:40.37#ibcon#wrote, iclass 21, count 0 2006.161.07:54:40.37#ibcon#about to read 3, iclass 21, count 0 2006.161.07:54:40.40#ibcon#read 3, iclass 21, count 0 2006.161.07:54:40.40#ibcon#about to read 4, iclass 21, count 0 2006.161.07:54:40.40#ibcon#read 4, iclass 21, count 0 2006.161.07:54:40.40#ibcon#about to read 5, iclass 21, count 0 2006.161.07:54:40.40#ibcon#read 5, iclass 21, count 0 2006.161.07:54:40.40#ibcon#about to read 6, iclass 21, count 0 2006.161.07:54:40.40#ibcon#read 6, iclass 21, count 0 2006.161.07:54:40.40#ibcon#end of sib2, iclass 21, count 0 2006.161.07:54:40.40#ibcon#*after write, iclass 21, count 0 2006.161.07:54:40.40#ibcon#*before return 0, iclass 21, count 0 2006.161.07:54:40.40#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:40.40#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:40.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:54:40.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:54:40.40$vc4f8/valo=5,652.99 2006.161.07:54:40.40#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:54:40.40#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:54:40.40#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:40.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:40.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:40.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:40.40#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:54:40.40#ibcon#first serial, iclass 23, count 0 2006.161.07:54:40.40#ibcon#enter sib2, iclass 23, count 0 2006.161.07:54:40.40#ibcon#flushed, iclass 23, count 0 2006.161.07:54:40.40#ibcon#about to write, iclass 23, count 0 2006.161.07:54:40.40#ibcon#wrote, iclass 23, count 0 2006.161.07:54:40.40#ibcon#about to read 3, iclass 23, count 0 2006.161.07:54:40.42#ibcon#read 3, iclass 23, count 0 2006.161.07:54:40.42#ibcon#about to read 4, iclass 23, count 0 2006.161.07:54:40.42#ibcon#read 4, iclass 23, count 0 2006.161.07:54:40.42#ibcon#about to read 5, iclass 23, count 0 2006.161.07:54:40.42#ibcon#read 5, iclass 23, count 0 2006.161.07:54:40.42#ibcon#about to read 6, iclass 23, count 0 2006.161.07:54:40.42#ibcon#read 6, iclass 23, count 0 2006.161.07:54:40.42#ibcon#end of sib2, iclass 23, count 0 2006.161.07:54:40.42#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:54:40.42#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:54:40.42#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:54:40.42#ibcon#*before write, iclass 23, count 0 2006.161.07:54:40.42#ibcon#enter sib2, iclass 23, count 0 2006.161.07:54:40.42#ibcon#flushed, iclass 23, count 0 2006.161.07:54:40.42#ibcon#about to write, iclass 23, count 0 2006.161.07:54:40.42#ibcon#wrote, iclass 23, count 0 2006.161.07:54:40.42#ibcon#about to read 3, iclass 23, count 0 2006.161.07:54:40.46#ibcon#read 3, iclass 23, count 0 2006.161.07:54:40.46#ibcon#about to read 4, iclass 23, count 0 2006.161.07:54:40.46#ibcon#read 4, iclass 23, count 0 2006.161.07:54:40.46#ibcon#about to read 5, iclass 23, count 0 2006.161.07:54:40.46#ibcon#read 5, iclass 23, count 0 2006.161.07:54:40.46#ibcon#about to read 6, iclass 23, count 0 2006.161.07:54:40.46#ibcon#read 6, iclass 23, count 0 2006.161.07:54:40.46#ibcon#end of sib2, iclass 23, count 0 2006.161.07:54:40.46#ibcon#*after write, iclass 23, count 0 2006.161.07:54:40.46#ibcon#*before return 0, iclass 23, count 0 2006.161.07:54:40.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:40.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:40.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:54:40.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:54:40.46$vc4f8/va=5,7 2006.161.07:54:40.46#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:54:40.46#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:54:40.46#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:40.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:40.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:40.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:40.52#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:54:40.52#ibcon#first serial, iclass 25, count 2 2006.161.07:54:40.52#ibcon#enter sib2, iclass 25, count 2 2006.161.07:54:40.52#ibcon#flushed, iclass 25, count 2 2006.161.07:54:40.52#ibcon#about to write, iclass 25, count 2 2006.161.07:54:40.52#ibcon#wrote, iclass 25, count 2 2006.161.07:54:40.52#ibcon#about to read 3, iclass 25, count 2 2006.161.07:54:40.54#ibcon#read 3, iclass 25, count 2 2006.161.07:54:40.54#ibcon#about to read 4, iclass 25, count 2 2006.161.07:54:40.54#ibcon#read 4, iclass 25, count 2 2006.161.07:54:40.54#ibcon#about to read 5, iclass 25, count 2 2006.161.07:54:40.54#ibcon#read 5, iclass 25, count 2 2006.161.07:54:40.54#ibcon#about to read 6, iclass 25, count 2 2006.161.07:54:40.54#ibcon#read 6, iclass 25, count 2 2006.161.07:54:40.54#ibcon#end of sib2, iclass 25, count 2 2006.161.07:54:40.54#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:54:40.54#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:54:40.54#ibcon#[25=AT05-07\r\n] 2006.161.07:54:40.54#ibcon#*before write, iclass 25, count 2 2006.161.07:54:40.54#ibcon#enter sib2, iclass 25, count 2 2006.161.07:54:40.54#ibcon#flushed, iclass 25, count 2 2006.161.07:54:40.54#ibcon#about to write, iclass 25, count 2 2006.161.07:54:40.54#ibcon#wrote, iclass 25, count 2 2006.161.07:54:40.54#ibcon#about to read 3, iclass 25, count 2 2006.161.07:54:40.57#ibcon#read 3, iclass 25, count 2 2006.161.07:54:40.57#ibcon#about to read 4, iclass 25, count 2 2006.161.07:54:40.57#ibcon#read 4, iclass 25, count 2 2006.161.07:54:40.57#ibcon#about to read 5, iclass 25, count 2 2006.161.07:54:40.57#ibcon#read 5, iclass 25, count 2 2006.161.07:54:40.57#ibcon#about to read 6, iclass 25, count 2 2006.161.07:54:40.57#ibcon#read 6, iclass 25, count 2 2006.161.07:54:40.57#ibcon#end of sib2, iclass 25, count 2 2006.161.07:54:40.57#ibcon#*after write, iclass 25, count 2 2006.161.07:54:40.57#ibcon#*before return 0, iclass 25, count 2 2006.161.07:54:40.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:40.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:40.57#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:54:40.57#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:40.57#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:40.69#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:40.69#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:40.69#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:54:40.69#ibcon#first serial, iclass 25, count 0 2006.161.07:54:40.69#ibcon#enter sib2, iclass 25, count 0 2006.161.07:54:40.69#ibcon#flushed, iclass 25, count 0 2006.161.07:54:40.69#ibcon#about to write, iclass 25, count 0 2006.161.07:54:40.69#ibcon#wrote, iclass 25, count 0 2006.161.07:54:40.69#ibcon#about to read 3, iclass 25, count 0 2006.161.07:54:40.71#ibcon#read 3, iclass 25, count 0 2006.161.07:54:40.71#ibcon#about to read 4, iclass 25, count 0 2006.161.07:54:40.71#ibcon#read 4, iclass 25, count 0 2006.161.07:54:40.71#ibcon#about to read 5, iclass 25, count 0 2006.161.07:54:40.71#ibcon#read 5, iclass 25, count 0 2006.161.07:54:40.71#ibcon#about to read 6, iclass 25, count 0 2006.161.07:54:40.71#ibcon#read 6, iclass 25, count 0 2006.161.07:54:40.71#ibcon#end of sib2, iclass 25, count 0 2006.161.07:54:40.71#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:54:40.71#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:54:40.71#ibcon#[25=USB\r\n] 2006.161.07:54:40.71#ibcon#*before write, iclass 25, count 0 2006.161.07:54:40.71#ibcon#enter sib2, iclass 25, count 0 2006.161.07:54:40.71#ibcon#flushed, iclass 25, count 0 2006.161.07:54:40.71#ibcon#about to write, iclass 25, count 0 2006.161.07:54:40.71#ibcon#wrote, iclass 25, count 0 2006.161.07:54:40.71#ibcon#about to read 3, iclass 25, count 0 2006.161.07:54:40.74#ibcon#read 3, iclass 25, count 0 2006.161.07:54:40.74#ibcon#about to read 4, iclass 25, count 0 2006.161.07:54:40.74#ibcon#read 4, iclass 25, count 0 2006.161.07:54:40.74#ibcon#about to read 5, iclass 25, count 0 2006.161.07:54:40.74#ibcon#read 5, iclass 25, count 0 2006.161.07:54:40.74#ibcon#about to read 6, iclass 25, count 0 2006.161.07:54:40.74#ibcon#read 6, iclass 25, count 0 2006.161.07:54:40.74#ibcon#end of sib2, iclass 25, count 0 2006.161.07:54:40.74#ibcon#*after write, iclass 25, count 0 2006.161.07:54:40.74#ibcon#*before return 0, iclass 25, count 0 2006.161.07:54:40.74#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:40.74#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:40.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:54:40.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:54:40.74$vc4f8/valo=6,772.99 2006.161.07:54:40.74#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.07:54:40.74#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.07:54:40.74#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:40.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:40.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:40.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:40.74#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:54:40.74#ibcon#first serial, iclass 27, count 0 2006.161.07:54:40.74#ibcon#enter sib2, iclass 27, count 0 2006.161.07:54:40.74#ibcon#flushed, iclass 27, count 0 2006.161.07:54:40.74#ibcon#about to write, iclass 27, count 0 2006.161.07:54:40.74#ibcon#wrote, iclass 27, count 0 2006.161.07:54:40.74#ibcon#about to read 3, iclass 27, count 0 2006.161.07:54:40.76#ibcon#read 3, iclass 27, count 0 2006.161.07:54:40.76#ibcon#about to read 4, iclass 27, count 0 2006.161.07:54:40.76#ibcon#read 4, iclass 27, count 0 2006.161.07:54:40.76#ibcon#about to read 5, iclass 27, count 0 2006.161.07:54:40.76#ibcon#read 5, iclass 27, count 0 2006.161.07:54:40.76#ibcon#about to read 6, iclass 27, count 0 2006.161.07:54:40.76#ibcon#read 6, iclass 27, count 0 2006.161.07:54:40.76#ibcon#end of sib2, iclass 27, count 0 2006.161.07:54:40.76#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:54:40.76#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:54:40.76#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:54:40.76#ibcon#*before write, iclass 27, count 0 2006.161.07:54:40.76#ibcon#enter sib2, iclass 27, count 0 2006.161.07:54:40.76#ibcon#flushed, iclass 27, count 0 2006.161.07:54:40.76#ibcon#about to write, iclass 27, count 0 2006.161.07:54:40.76#ibcon#wrote, iclass 27, count 0 2006.161.07:54:40.76#ibcon#about to read 3, iclass 27, count 0 2006.161.07:54:40.80#ibcon#read 3, iclass 27, count 0 2006.161.07:54:40.80#ibcon#about to read 4, iclass 27, count 0 2006.161.07:54:40.80#ibcon#read 4, iclass 27, count 0 2006.161.07:54:40.80#ibcon#about to read 5, iclass 27, count 0 2006.161.07:54:40.80#ibcon#read 5, iclass 27, count 0 2006.161.07:54:40.80#ibcon#about to read 6, iclass 27, count 0 2006.161.07:54:40.80#ibcon#read 6, iclass 27, count 0 2006.161.07:54:40.80#ibcon#end of sib2, iclass 27, count 0 2006.161.07:54:40.80#ibcon#*after write, iclass 27, count 0 2006.161.07:54:40.80#ibcon#*before return 0, iclass 27, count 0 2006.161.07:54:40.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:40.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:40.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:54:40.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:54:40.80$vc4f8/va=6,6 2006.161.07:54:40.80#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.07:54:40.80#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.07:54:40.80#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:40.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:40.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:40.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:40.86#ibcon#enter wrdev, iclass 29, count 2 2006.161.07:54:40.86#ibcon#first serial, iclass 29, count 2 2006.161.07:54:40.86#ibcon#enter sib2, iclass 29, count 2 2006.161.07:54:40.86#ibcon#flushed, iclass 29, count 2 2006.161.07:54:40.86#ibcon#about to write, iclass 29, count 2 2006.161.07:54:40.86#ibcon#wrote, iclass 29, count 2 2006.161.07:54:40.86#ibcon#about to read 3, iclass 29, count 2 2006.161.07:54:40.88#ibcon#read 3, iclass 29, count 2 2006.161.07:54:40.88#ibcon#about to read 4, iclass 29, count 2 2006.161.07:54:40.88#ibcon#read 4, iclass 29, count 2 2006.161.07:54:40.88#ibcon#about to read 5, iclass 29, count 2 2006.161.07:54:40.88#ibcon#read 5, iclass 29, count 2 2006.161.07:54:40.88#ibcon#about to read 6, iclass 29, count 2 2006.161.07:54:40.88#ibcon#read 6, iclass 29, count 2 2006.161.07:54:40.88#ibcon#end of sib2, iclass 29, count 2 2006.161.07:54:40.88#ibcon#*mode == 0, iclass 29, count 2 2006.161.07:54:40.88#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.07:54:40.88#ibcon#[25=AT06-06\r\n] 2006.161.07:54:40.88#ibcon#*before write, iclass 29, count 2 2006.161.07:54:40.88#ibcon#enter sib2, iclass 29, count 2 2006.161.07:54:40.88#ibcon#flushed, iclass 29, count 2 2006.161.07:54:40.88#ibcon#about to write, iclass 29, count 2 2006.161.07:54:40.88#ibcon#wrote, iclass 29, count 2 2006.161.07:54:40.88#ibcon#about to read 3, iclass 29, count 2 2006.161.07:54:40.91#ibcon#read 3, iclass 29, count 2 2006.161.07:54:40.91#ibcon#about to read 4, iclass 29, count 2 2006.161.07:54:40.91#ibcon#read 4, iclass 29, count 2 2006.161.07:54:40.91#ibcon#about to read 5, iclass 29, count 2 2006.161.07:54:40.91#ibcon#read 5, iclass 29, count 2 2006.161.07:54:40.91#ibcon#about to read 6, iclass 29, count 2 2006.161.07:54:40.91#ibcon#read 6, iclass 29, count 2 2006.161.07:54:40.91#ibcon#end of sib2, iclass 29, count 2 2006.161.07:54:40.91#ibcon#*after write, iclass 29, count 2 2006.161.07:54:40.91#ibcon#*before return 0, iclass 29, count 2 2006.161.07:54:40.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:40.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:40.91#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.07:54:40.91#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:40.91#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:40.97#abcon#<5=/05 2.8 5.6 24.04 861002.1\r\n> 2006.161.07:54:40.99#abcon#{5=INTERFACE CLEAR} 2006.161.07:54:41.03#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:41.03#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:41.03#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:54:41.03#ibcon#first serial, iclass 29, count 0 2006.161.07:54:41.03#ibcon#enter sib2, iclass 29, count 0 2006.161.07:54:41.03#ibcon#flushed, iclass 29, count 0 2006.161.07:54:41.03#ibcon#about to write, iclass 29, count 0 2006.161.07:54:41.03#ibcon#wrote, iclass 29, count 0 2006.161.07:54:41.03#ibcon#about to read 3, iclass 29, count 0 2006.161.07:54:41.05#ibcon#read 3, iclass 29, count 0 2006.161.07:54:41.05#ibcon#about to read 4, iclass 29, count 0 2006.161.07:54:41.05#ibcon#read 4, iclass 29, count 0 2006.161.07:54:41.05#ibcon#about to read 5, iclass 29, count 0 2006.161.07:54:41.05#ibcon#read 5, iclass 29, count 0 2006.161.07:54:41.05#ibcon#about to read 6, iclass 29, count 0 2006.161.07:54:41.05#ibcon#read 6, iclass 29, count 0 2006.161.07:54:41.05#ibcon#end of sib2, iclass 29, count 0 2006.161.07:54:41.05#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:54:41.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:54:41.05#ibcon#[25=USB\r\n] 2006.161.07:54:41.05#ibcon#*before write, iclass 29, count 0 2006.161.07:54:41.05#ibcon#enter sib2, iclass 29, count 0 2006.161.07:54:41.05#ibcon#flushed, iclass 29, count 0 2006.161.07:54:41.05#ibcon#about to write, iclass 29, count 0 2006.161.07:54:41.05#ibcon#wrote, iclass 29, count 0 2006.161.07:54:41.05#ibcon#about to read 3, iclass 29, count 0 2006.161.07:54:41.05#abcon#[5=S1D000X0/0*\r\n] 2006.161.07:54:41.08#ibcon#read 3, iclass 29, count 0 2006.161.07:54:41.08#ibcon#about to read 4, iclass 29, count 0 2006.161.07:54:41.08#ibcon#read 4, iclass 29, count 0 2006.161.07:54:41.08#ibcon#about to read 5, iclass 29, count 0 2006.161.07:54:41.08#ibcon#read 5, iclass 29, count 0 2006.161.07:54:41.08#ibcon#about to read 6, iclass 29, count 0 2006.161.07:54:41.08#ibcon#read 6, iclass 29, count 0 2006.161.07:54:41.08#ibcon#end of sib2, iclass 29, count 0 2006.161.07:54:41.08#ibcon#*after write, iclass 29, count 0 2006.161.07:54:41.08#ibcon#*before return 0, iclass 29, count 0 2006.161.07:54:41.08#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:41.08#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:41.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:54:41.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:54:41.08$vc4f8/valo=7,832.99 2006.161.07:54:41.08#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.07:54:41.08#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.07:54:41.08#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:41.08#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:54:41.08#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:54:41.08#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:54:41.08#ibcon#enter wrdev, iclass 35, count 0 2006.161.07:54:41.08#ibcon#first serial, iclass 35, count 0 2006.161.07:54:41.08#ibcon#enter sib2, iclass 35, count 0 2006.161.07:54:41.08#ibcon#flushed, iclass 35, count 0 2006.161.07:54:41.08#ibcon#about to write, iclass 35, count 0 2006.161.07:54:41.08#ibcon#wrote, iclass 35, count 0 2006.161.07:54:41.08#ibcon#about to read 3, iclass 35, count 0 2006.161.07:54:41.10#ibcon#read 3, iclass 35, count 0 2006.161.07:54:41.10#ibcon#about to read 4, iclass 35, count 0 2006.161.07:54:41.10#ibcon#read 4, iclass 35, count 0 2006.161.07:54:41.10#ibcon#about to read 5, iclass 35, count 0 2006.161.07:54:41.10#ibcon#read 5, iclass 35, count 0 2006.161.07:54:41.10#ibcon#about to read 6, iclass 35, count 0 2006.161.07:54:41.10#ibcon#read 6, iclass 35, count 0 2006.161.07:54:41.10#ibcon#end of sib2, iclass 35, count 0 2006.161.07:54:41.10#ibcon#*mode == 0, iclass 35, count 0 2006.161.07:54:41.10#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.07:54:41.10#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:54:41.10#ibcon#*before write, iclass 35, count 0 2006.161.07:54:41.10#ibcon#enter sib2, iclass 35, count 0 2006.161.07:54:41.10#ibcon#flushed, iclass 35, count 0 2006.161.07:54:41.10#ibcon#about to write, iclass 35, count 0 2006.161.07:54:41.10#ibcon#wrote, iclass 35, count 0 2006.161.07:54:41.10#ibcon#about to read 3, iclass 35, count 0 2006.161.07:54:41.14#ibcon#read 3, iclass 35, count 0 2006.161.07:54:41.14#ibcon#about to read 4, iclass 35, count 0 2006.161.07:54:41.14#ibcon#read 4, iclass 35, count 0 2006.161.07:54:41.14#ibcon#about to read 5, iclass 35, count 0 2006.161.07:54:41.14#ibcon#read 5, iclass 35, count 0 2006.161.07:54:41.14#ibcon#about to read 6, iclass 35, count 0 2006.161.07:54:41.14#ibcon#read 6, iclass 35, count 0 2006.161.07:54:41.14#ibcon#end of sib2, iclass 35, count 0 2006.161.07:54:41.14#ibcon#*after write, iclass 35, count 0 2006.161.07:54:41.14#ibcon#*before return 0, iclass 35, count 0 2006.161.07:54:41.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:54:41.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.07:54:41.14#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.07:54:41.14#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.07:54:41.14$vc4f8/va=7,6 2006.161.07:54:41.14#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.07:54:41.14#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.07:54:41.14#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:41.14#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:54:41.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:54:41.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:54:41.20#ibcon#enter wrdev, iclass 37, count 2 2006.161.07:54:41.20#ibcon#first serial, iclass 37, count 2 2006.161.07:54:41.20#ibcon#enter sib2, iclass 37, count 2 2006.161.07:54:41.20#ibcon#flushed, iclass 37, count 2 2006.161.07:54:41.20#ibcon#about to write, iclass 37, count 2 2006.161.07:54:41.20#ibcon#wrote, iclass 37, count 2 2006.161.07:54:41.20#ibcon#about to read 3, iclass 37, count 2 2006.161.07:54:41.22#ibcon#read 3, iclass 37, count 2 2006.161.07:54:41.22#ibcon#about to read 4, iclass 37, count 2 2006.161.07:54:41.22#ibcon#read 4, iclass 37, count 2 2006.161.07:54:41.22#ibcon#about to read 5, iclass 37, count 2 2006.161.07:54:41.22#ibcon#read 5, iclass 37, count 2 2006.161.07:54:41.22#ibcon#about to read 6, iclass 37, count 2 2006.161.07:54:41.22#ibcon#read 6, iclass 37, count 2 2006.161.07:54:41.22#ibcon#end of sib2, iclass 37, count 2 2006.161.07:54:41.22#ibcon#*mode == 0, iclass 37, count 2 2006.161.07:54:41.22#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.07:54:41.22#ibcon#[25=AT07-06\r\n] 2006.161.07:54:41.22#ibcon#*before write, iclass 37, count 2 2006.161.07:54:41.22#ibcon#enter sib2, iclass 37, count 2 2006.161.07:54:41.22#ibcon#flushed, iclass 37, count 2 2006.161.07:54:41.22#ibcon#about to write, iclass 37, count 2 2006.161.07:54:41.22#ibcon#wrote, iclass 37, count 2 2006.161.07:54:41.22#ibcon#about to read 3, iclass 37, count 2 2006.161.07:54:41.25#ibcon#read 3, iclass 37, count 2 2006.161.07:54:41.25#ibcon#about to read 4, iclass 37, count 2 2006.161.07:54:41.25#ibcon#read 4, iclass 37, count 2 2006.161.07:54:41.25#ibcon#about to read 5, iclass 37, count 2 2006.161.07:54:41.25#ibcon#read 5, iclass 37, count 2 2006.161.07:54:41.25#ibcon#about to read 6, iclass 37, count 2 2006.161.07:54:41.25#ibcon#read 6, iclass 37, count 2 2006.161.07:54:41.25#ibcon#end of sib2, iclass 37, count 2 2006.161.07:54:41.25#ibcon#*after write, iclass 37, count 2 2006.161.07:54:41.25#ibcon#*before return 0, iclass 37, count 2 2006.161.07:54:41.25#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:54:41.25#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.07:54:41.25#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.07:54:41.25#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:41.25#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:54:41.37#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:54:41.37#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:54:41.37#ibcon#enter wrdev, iclass 37, count 0 2006.161.07:54:41.37#ibcon#first serial, iclass 37, count 0 2006.161.07:54:41.37#ibcon#enter sib2, iclass 37, count 0 2006.161.07:54:41.37#ibcon#flushed, iclass 37, count 0 2006.161.07:54:41.37#ibcon#about to write, iclass 37, count 0 2006.161.07:54:41.37#ibcon#wrote, iclass 37, count 0 2006.161.07:54:41.37#ibcon#about to read 3, iclass 37, count 0 2006.161.07:54:41.39#ibcon#read 3, iclass 37, count 0 2006.161.07:54:41.39#ibcon#about to read 4, iclass 37, count 0 2006.161.07:54:41.39#ibcon#read 4, iclass 37, count 0 2006.161.07:54:41.39#ibcon#about to read 5, iclass 37, count 0 2006.161.07:54:41.39#ibcon#read 5, iclass 37, count 0 2006.161.07:54:41.39#ibcon#about to read 6, iclass 37, count 0 2006.161.07:54:41.39#ibcon#read 6, iclass 37, count 0 2006.161.07:54:41.39#ibcon#end of sib2, iclass 37, count 0 2006.161.07:54:41.39#ibcon#*mode == 0, iclass 37, count 0 2006.161.07:54:41.39#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.07:54:41.39#ibcon#[25=USB\r\n] 2006.161.07:54:41.39#ibcon#*before write, iclass 37, count 0 2006.161.07:54:41.39#ibcon#enter sib2, iclass 37, count 0 2006.161.07:54:41.39#ibcon#flushed, iclass 37, count 0 2006.161.07:54:41.39#ibcon#about to write, iclass 37, count 0 2006.161.07:54:41.39#ibcon#wrote, iclass 37, count 0 2006.161.07:54:41.39#ibcon#about to read 3, iclass 37, count 0 2006.161.07:54:41.42#ibcon#read 3, iclass 37, count 0 2006.161.07:54:41.42#ibcon#about to read 4, iclass 37, count 0 2006.161.07:54:41.42#ibcon#read 4, iclass 37, count 0 2006.161.07:54:41.42#ibcon#about to read 5, iclass 37, count 0 2006.161.07:54:41.42#ibcon#read 5, iclass 37, count 0 2006.161.07:54:41.42#ibcon#about to read 6, iclass 37, count 0 2006.161.07:54:41.42#ibcon#read 6, iclass 37, count 0 2006.161.07:54:41.42#ibcon#end of sib2, iclass 37, count 0 2006.161.07:54:41.42#ibcon#*after write, iclass 37, count 0 2006.161.07:54:41.42#ibcon#*before return 0, iclass 37, count 0 2006.161.07:54:41.42#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:54:41.42#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.07:54:41.42#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.07:54:41.42#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.07:54:41.42$vc4f8/valo=8,852.99 2006.161.07:54:41.42#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.07:54:41.42#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.07:54:41.42#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:41.42#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:54:41.42#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:54:41.42#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:54:41.42#ibcon#enter wrdev, iclass 39, count 0 2006.161.07:54:41.42#ibcon#first serial, iclass 39, count 0 2006.161.07:54:41.42#ibcon#enter sib2, iclass 39, count 0 2006.161.07:54:41.42#ibcon#flushed, iclass 39, count 0 2006.161.07:54:41.42#ibcon#about to write, iclass 39, count 0 2006.161.07:54:41.42#ibcon#wrote, iclass 39, count 0 2006.161.07:54:41.42#ibcon#about to read 3, iclass 39, count 0 2006.161.07:54:41.44#ibcon#read 3, iclass 39, count 0 2006.161.07:54:41.44#ibcon#about to read 4, iclass 39, count 0 2006.161.07:54:41.44#ibcon#read 4, iclass 39, count 0 2006.161.07:54:41.44#ibcon#about to read 5, iclass 39, count 0 2006.161.07:54:41.44#ibcon#read 5, iclass 39, count 0 2006.161.07:54:41.44#ibcon#about to read 6, iclass 39, count 0 2006.161.07:54:41.44#ibcon#read 6, iclass 39, count 0 2006.161.07:54:41.44#ibcon#end of sib2, iclass 39, count 0 2006.161.07:54:41.44#ibcon#*mode == 0, iclass 39, count 0 2006.161.07:54:41.44#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.07:54:41.44#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:54:41.44#ibcon#*before write, iclass 39, count 0 2006.161.07:54:41.44#ibcon#enter sib2, iclass 39, count 0 2006.161.07:54:41.44#ibcon#flushed, iclass 39, count 0 2006.161.07:54:41.44#ibcon#about to write, iclass 39, count 0 2006.161.07:54:41.44#ibcon#wrote, iclass 39, count 0 2006.161.07:54:41.44#ibcon#about to read 3, iclass 39, count 0 2006.161.07:54:41.48#ibcon#read 3, iclass 39, count 0 2006.161.07:54:41.48#ibcon#about to read 4, iclass 39, count 0 2006.161.07:54:41.48#ibcon#read 4, iclass 39, count 0 2006.161.07:54:41.48#ibcon#about to read 5, iclass 39, count 0 2006.161.07:54:41.48#ibcon#read 5, iclass 39, count 0 2006.161.07:54:41.48#ibcon#about to read 6, iclass 39, count 0 2006.161.07:54:41.48#ibcon#read 6, iclass 39, count 0 2006.161.07:54:41.48#ibcon#end of sib2, iclass 39, count 0 2006.161.07:54:41.48#ibcon#*after write, iclass 39, count 0 2006.161.07:54:41.48#ibcon#*before return 0, iclass 39, count 0 2006.161.07:54:41.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:54:41.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.07:54:41.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.07:54:41.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.07:54:41.48$vc4f8/va=8,7 2006.161.07:54:41.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.07:54:41.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.07:54:41.48#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:41.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:54:41.54#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:54:41.54#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:54:41.54#ibcon#enter wrdev, iclass 3, count 2 2006.161.07:54:41.54#ibcon#first serial, iclass 3, count 2 2006.161.07:54:41.54#ibcon#enter sib2, iclass 3, count 2 2006.161.07:54:41.54#ibcon#flushed, iclass 3, count 2 2006.161.07:54:41.54#ibcon#about to write, iclass 3, count 2 2006.161.07:54:41.54#ibcon#wrote, iclass 3, count 2 2006.161.07:54:41.54#ibcon#about to read 3, iclass 3, count 2 2006.161.07:54:41.56#ibcon#read 3, iclass 3, count 2 2006.161.07:54:41.56#ibcon#about to read 4, iclass 3, count 2 2006.161.07:54:41.56#ibcon#read 4, iclass 3, count 2 2006.161.07:54:41.56#ibcon#about to read 5, iclass 3, count 2 2006.161.07:54:41.56#ibcon#read 5, iclass 3, count 2 2006.161.07:54:41.56#ibcon#about to read 6, iclass 3, count 2 2006.161.07:54:41.56#ibcon#read 6, iclass 3, count 2 2006.161.07:54:41.56#ibcon#end of sib2, iclass 3, count 2 2006.161.07:54:41.56#ibcon#*mode == 0, iclass 3, count 2 2006.161.07:54:41.56#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.07:54:41.56#ibcon#[25=AT08-07\r\n] 2006.161.07:54:41.56#ibcon#*before write, iclass 3, count 2 2006.161.07:54:41.56#ibcon#enter sib2, iclass 3, count 2 2006.161.07:54:41.56#ibcon#flushed, iclass 3, count 2 2006.161.07:54:41.56#ibcon#about to write, iclass 3, count 2 2006.161.07:54:41.56#ibcon#wrote, iclass 3, count 2 2006.161.07:54:41.56#ibcon#about to read 3, iclass 3, count 2 2006.161.07:54:41.59#ibcon#read 3, iclass 3, count 2 2006.161.07:54:41.59#ibcon#about to read 4, iclass 3, count 2 2006.161.07:54:41.59#ibcon#read 4, iclass 3, count 2 2006.161.07:54:41.59#ibcon#about to read 5, iclass 3, count 2 2006.161.07:54:41.59#ibcon#read 5, iclass 3, count 2 2006.161.07:54:41.59#ibcon#about to read 6, iclass 3, count 2 2006.161.07:54:41.59#ibcon#read 6, iclass 3, count 2 2006.161.07:54:41.59#ibcon#end of sib2, iclass 3, count 2 2006.161.07:54:41.59#ibcon#*after write, iclass 3, count 2 2006.161.07:54:41.59#ibcon#*before return 0, iclass 3, count 2 2006.161.07:54:41.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:54:41.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.07:54:41.59#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.07:54:41.59#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:41.59#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:54:41.71#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:54:41.71#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:54:41.71#ibcon#enter wrdev, iclass 3, count 0 2006.161.07:54:41.71#ibcon#first serial, iclass 3, count 0 2006.161.07:54:41.71#ibcon#enter sib2, iclass 3, count 0 2006.161.07:54:41.71#ibcon#flushed, iclass 3, count 0 2006.161.07:54:41.71#ibcon#about to write, iclass 3, count 0 2006.161.07:54:41.71#ibcon#wrote, iclass 3, count 0 2006.161.07:54:41.71#ibcon#about to read 3, iclass 3, count 0 2006.161.07:54:41.73#ibcon#read 3, iclass 3, count 0 2006.161.07:54:41.73#ibcon#about to read 4, iclass 3, count 0 2006.161.07:54:41.73#ibcon#read 4, iclass 3, count 0 2006.161.07:54:41.73#ibcon#about to read 5, iclass 3, count 0 2006.161.07:54:41.73#ibcon#read 5, iclass 3, count 0 2006.161.07:54:41.73#ibcon#about to read 6, iclass 3, count 0 2006.161.07:54:41.73#ibcon#read 6, iclass 3, count 0 2006.161.07:54:41.73#ibcon#end of sib2, iclass 3, count 0 2006.161.07:54:41.73#ibcon#*mode == 0, iclass 3, count 0 2006.161.07:54:41.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.07:54:41.73#ibcon#[25=USB\r\n] 2006.161.07:54:41.73#ibcon#*before write, iclass 3, count 0 2006.161.07:54:41.73#ibcon#enter sib2, iclass 3, count 0 2006.161.07:54:41.73#ibcon#flushed, iclass 3, count 0 2006.161.07:54:41.73#ibcon#about to write, iclass 3, count 0 2006.161.07:54:41.73#ibcon#wrote, iclass 3, count 0 2006.161.07:54:41.73#ibcon#about to read 3, iclass 3, count 0 2006.161.07:54:41.76#ibcon#read 3, iclass 3, count 0 2006.161.07:54:41.76#ibcon#about to read 4, iclass 3, count 0 2006.161.07:54:41.76#ibcon#read 4, iclass 3, count 0 2006.161.07:54:41.76#ibcon#about to read 5, iclass 3, count 0 2006.161.07:54:41.76#ibcon#read 5, iclass 3, count 0 2006.161.07:54:41.76#ibcon#about to read 6, iclass 3, count 0 2006.161.07:54:41.76#ibcon#read 6, iclass 3, count 0 2006.161.07:54:41.76#ibcon#end of sib2, iclass 3, count 0 2006.161.07:54:41.76#ibcon#*after write, iclass 3, count 0 2006.161.07:54:41.76#ibcon#*before return 0, iclass 3, count 0 2006.161.07:54:41.76#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:54:41.76#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.07:54:41.76#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.07:54:41.76#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.07:54:41.76$vc4f8/vblo=1,632.99 2006.161.07:54:41.76#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.07:54:41.76#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.07:54:41.76#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:41.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:41.76#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:41.76#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:41.76#ibcon#enter wrdev, iclass 5, count 0 2006.161.07:54:41.76#ibcon#first serial, iclass 5, count 0 2006.161.07:54:41.76#ibcon#enter sib2, iclass 5, count 0 2006.161.07:54:41.76#ibcon#flushed, iclass 5, count 0 2006.161.07:54:41.76#ibcon#about to write, iclass 5, count 0 2006.161.07:54:41.76#ibcon#wrote, iclass 5, count 0 2006.161.07:54:41.76#ibcon#about to read 3, iclass 5, count 0 2006.161.07:54:41.78#ibcon#read 3, iclass 5, count 0 2006.161.07:54:41.78#ibcon#about to read 4, iclass 5, count 0 2006.161.07:54:41.78#ibcon#read 4, iclass 5, count 0 2006.161.07:54:41.78#ibcon#about to read 5, iclass 5, count 0 2006.161.07:54:41.78#ibcon#read 5, iclass 5, count 0 2006.161.07:54:41.78#ibcon#about to read 6, iclass 5, count 0 2006.161.07:54:41.78#ibcon#read 6, iclass 5, count 0 2006.161.07:54:41.78#ibcon#end of sib2, iclass 5, count 0 2006.161.07:54:41.78#ibcon#*mode == 0, iclass 5, count 0 2006.161.07:54:41.78#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.07:54:41.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:54:41.78#ibcon#*before write, iclass 5, count 0 2006.161.07:54:41.78#ibcon#enter sib2, iclass 5, count 0 2006.161.07:54:41.78#ibcon#flushed, iclass 5, count 0 2006.161.07:54:41.78#ibcon#about to write, iclass 5, count 0 2006.161.07:54:41.78#ibcon#wrote, iclass 5, count 0 2006.161.07:54:41.78#ibcon#about to read 3, iclass 5, count 0 2006.161.07:54:41.82#ibcon#read 3, iclass 5, count 0 2006.161.07:54:41.82#ibcon#about to read 4, iclass 5, count 0 2006.161.07:54:41.82#ibcon#read 4, iclass 5, count 0 2006.161.07:54:41.82#ibcon#about to read 5, iclass 5, count 0 2006.161.07:54:41.82#ibcon#read 5, iclass 5, count 0 2006.161.07:54:41.82#ibcon#about to read 6, iclass 5, count 0 2006.161.07:54:41.82#ibcon#read 6, iclass 5, count 0 2006.161.07:54:41.82#ibcon#end of sib2, iclass 5, count 0 2006.161.07:54:41.82#ibcon#*after write, iclass 5, count 0 2006.161.07:54:41.82#ibcon#*before return 0, iclass 5, count 0 2006.161.07:54:41.82#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:41.82#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.07:54:41.82#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.07:54:41.82#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.07:54:41.82$vc4f8/vb=1,4 2006.161.07:54:41.82#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.07:54:41.82#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.07:54:41.82#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:41.82#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:41.82#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:41.82#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:41.82#ibcon#enter wrdev, iclass 7, count 2 2006.161.07:54:41.82#ibcon#first serial, iclass 7, count 2 2006.161.07:54:41.82#ibcon#enter sib2, iclass 7, count 2 2006.161.07:54:41.82#ibcon#flushed, iclass 7, count 2 2006.161.07:54:41.82#ibcon#about to write, iclass 7, count 2 2006.161.07:54:41.82#ibcon#wrote, iclass 7, count 2 2006.161.07:54:41.82#ibcon#about to read 3, iclass 7, count 2 2006.161.07:54:41.84#ibcon#read 3, iclass 7, count 2 2006.161.07:54:41.84#ibcon#about to read 4, iclass 7, count 2 2006.161.07:54:41.84#ibcon#read 4, iclass 7, count 2 2006.161.07:54:41.84#ibcon#about to read 5, iclass 7, count 2 2006.161.07:54:41.84#ibcon#read 5, iclass 7, count 2 2006.161.07:54:41.84#ibcon#about to read 6, iclass 7, count 2 2006.161.07:54:41.84#ibcon#read 6, iclass 7, count 2 2006.161.07:54:41.84#ibcon#end of sib2, iclass 7, count 2 2006.161.07:54:41.84#ibcon#*mode == 0, iclass 7, count 2 2006.161.07:54:41.84#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.07:54:41.84#ibcon#[27=AT01-04\r\n] 2006.161.07:54:41.84#ibcon#*before write, iclass 7, count 2 2006.161.07:54:41.84#ibcon#enter sib2, iclass 7, count 2 2006.161.07:54:41.84#ibcon#flushed, iclass 7, count 2 2006.161.07:54:41.84#ibcon#about to write, iclass 7, count 2 2006.161.07:54:41.84#ibcon#wrote, iclass 7, count 2 2006.161.07:54:41.84#ibcon#about to read 3, iclass 7, count 2 2006.161.07:54:41.87#ibcon#read 3, iclass 7, count 2 2006.161.07:54:41.87#ibcon#about to read 4, iclass 7, count 2 2006.161.07:54:41.87#ibcon#read 4, iclass 7, count 2 2006.161.07:54:41.87#ibcon#about to read 5, iclass 7, count 2 2006.161.07:54:41.87#ibcon#read 5, iclass 7, count 2 2006.161.07:54:41.87#ibcon#about to read 6, iclass 7, count 2 2006.161.07:54:41.87#ibcon#read 6, iclass 7, count 2 2006.161.07:54:41.87#ibcon#end of sib2, iclass 7, count 2 2006.161.07:54:41.87#ibcon#*after write, iclass 7, count 2 2006.161.07:54:41.87#ibcon#*before return 0, iclass 7, count 2 2006.161.07:54:41.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:41.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.07:54:41.87#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.07:54:41.87#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:41.87#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:41.99#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:41.99#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:41.99#ibcon#enter wrdev, iclass 7, count 0 2006.161.07:54:41.99#ibcon#first serial, iclass 7, count 0 2006.161.07:54:41.99#ibcon#enter sib2, iclass 7, count 0 2006.161.07:54:41.99#ibcon#flushed, iclass 7, count 0 2006.161.07:54:41.99#ibcon#about to write, iclass 7, count 0 2006.161.07:54:41.99#ibcon#wrote, iclass 7, count 0 2006.161.07:54:41.99#ibcon#about to read 3, iclass 7, count 0 2006.161.07:54:42.01#ibcon#read 3, iclass 7, count 0 2006.161.07:54:42.01#ibcon#about to read 4, iclass 7, count 0 2006.161.07:54:42.01#ibcon#read 4, iclass 7, count 0 2006.161.07:54:42.01#ibcon#about to read 5, iclass 7, count 0 2006.161.07:54:42.01#ibcon#read 5, iclass 7, count 0 2006.161.07:54:42.01#ibcon#about to read 6, iclass 7, count 0 2006.161.07:54:42.01#ibcon#read 6, iclass 7, count 0 2006.161.07:54:42.01#ibcon#end of sib2, iclass 7, count 0 2006.161.07:54:42.01#ibcon#*mode == 0, iclass 7, count 0 2006.161.07:54:42.01#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.07:54:42.01#ibcon#[27=USB\r\n] 2006.161.07:54:42.01#ibcon#*before write, iclass 7, count 0 2006.161.07:54:42.01#ibcon#enter sib2, iclass 7, count 0 2006.161.07:54:42.01#ibcon#flushed, iclass 7, count 0 2006.161.07:54:42.01#ibcon#about to write, iclass 7, count 0 2006.161.07:54:42.01#ibcon#wrote, iclass 7, count 0 2006.161.07:54:42.01#ibcon#about to read 3, iclass 7, count 0 2006.161.07:54:42.04#ibcon#read 3, iclass 7, count 0 2006.161.07:54:42.04#ibcon#about to read 4, iclass 7, count 0 2006.161.07:54:42.04#ibcon#read 4, iclass 7, count 0 2006.161.07:54:42.04#ibcon#about to read 5, iclass 7, count 0 2006.161.07:54:42.04#ibcon#read 5, iclass 7, count 0 2006.161.07:54:42.04#ibcon#about to read 6, iclass 7, count 0 2006.161.07:54:42.04#ibcon#read 6, iclass 7, count 0 2006.161.07:54:42.04#ibcon#end of sib2, iclass 7, count 0 2006.161.07:54:42.04#ibcon#*after write, iclass 7, count 0 2006.161.07:54:42.04#ibcon#*before return 0, iclass 7, count 0 2006.161.07:54:42.04#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:42.04#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.07:54:42.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.07:54:42.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.07:54:42.04$vc4f8/vblo=2,640.99 2006.161.07:54:42.04#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.07:54:42.04#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.07:54:42.04#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:42.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:42.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:42.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:42.04#ibcon#enter wrdev, iclass 11, count 0 2006.161.07:54:42.04#ibcon#first serial, iclass 11, count 0 2006.161.07:54:42.04#ibcon#enter sib2, iclass 11, count 0 2006.161.07:54:42.04#ibcon#flushed, iclass 11, count 0 2006.161.07:54:42.04#ibcon#about to write, iclass 11, count 0 2006.161.07:54:42.04#ibcon#wrote, iclass 11, count 0 2006.161.07:54:42.04#ibcon#about to read 3, iclass 11, count 0 2006.161.07:54:42.06#ibcon#read 3, iclass 11, count 0 2006.161.07:54:42.06#ibcon#about to read 4, iclass 11, count 0 2006.161.07:54:42.06#ibcon#read 4, iclass 11, count 0 2006.161.07:54:42.06#ibcon#about to read 5, iclass 11, count 0 2006.161.07:54:42.06#ibcon#read 5, iclass 11, count 0 2006.161.07:54:42.06#ibcon#about to read 6, iclass 11, count 0 2006.161.07:54:42.06#ibcon#read 6, iclass 11, count 0 2006.161.07:54:42.06#ibcon#end of sib2, iclass 11, count 0 2006.161.07:54:42.06#ibcon#*mode == 0, iclass 11, count 0 2006.161.07:54:42.06#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.07:54:42.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:54:42.06#ibcon#*before write, iclass 11, count 0 2006.161.07:54:42.06#ibcon#enter sib2, iclass 11, count 0 2006.161.07:54:42.06#ibcon#flushed, iclass 11, count 0 2006.161.07:54:42.06#ibcon#about to write, iclass 11, count 0 2006.161.07:54:42.06#ibcon#wrote, iclass 11, count 0 2006.161.07:54:42.06#ibcon#about to read 3, iclass 11, count 0 2006.161.07:54:42.10#ibcon#read 3, iclass 11, count 0 2006.161.07:54:42.10#ibcon#about to read 4, iclass 11, count 0 2006.161.07:54:42.10#ibcon#read 4, iclass 11, count 0 2006.161.07:54:42.10#ibcon#about to read 5, iclass 11, count 0 2006.161.07:54:42.10#ibcon#read 5, iclass 11, count 0 2006.161.07:54:42.10#ibcon#about to read 6, iclass 11, count 0 2006.161.07:54:42.10#ibcon#read 6, iclass 11, count 0 2006.161.07:54:42.10#ibcon#end of sib2, iclass 11, count 0 2006.161.07:54:42.10#ibcon#*after write, iclass 11, count 0 2006.161.07:54:42.10#ibcon#*before return 0, iclass 11, count 0 2006.161.07:54:42.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:42.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.07:54:42.10#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.07:54:42.10#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.07:54:42.10$vc4f8/vb=2,4 2006.161.07:54:42.10#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.07:54:42.10#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.07:54:42.10#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:42.10#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:42.16#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:42.16#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:42.16#ibcon#enter wrdev, iclass 13, count 2 2006.161.07:54:42.16#ibcon#first serial, iclass 13, count 2 2006.161.07:54:42.16#ibcon#enter sib2, iclass 13, count 2 2006.161.07:54:42.16#ibcon#flushed, iclass 13, count 2 2006.161.07:54:42.16#ibcon#about to write, iclass 13, count 2 2006.161.07:54:42.16#ibcon#wrote, iclass 13, count 2 2006.161.07:54:42.16#ibcon#about to read 3, iclass 13, count 2 2006.161.07:54:42.18#ibcon#read 3, iclass 13, count 2 2006.161.07:54:42.18#ibcon#about to read 4, iclass 13, count 2 2006.161.07:54:42.18#ibcon#read 4, iclass 13, count 2 2006.161.07:54:42.18#ibcon#about to read 5, iclass 13, count 2 2006.161.07:54:42.18#ibcon#read 5, iclass 13, count 2 2006.161.07:54:42.18#ibcon#about to read 6, iclass 13, count 2 2006.161.07:54:42.18#ibcon#read 6, iclass 13, count 2 2006.161.07:54:42.18#ibcon#end of sib2, iclass 13, count 2 2006.161.07:54:42.18#ibcon#*mode == 0, iclass 13, count 2 2006.161.07:54:42.18#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.07:54:42.18#ibcon#[27=AT02-04\r\n] 2006.161.07:54:42.18#ibcon#*before write, iclass 13, count 2 2006.161.07:54:42.18#ibcon#enter sib2, iclass 13, count 2 2006.161.07:54:42.18#ibcon#flushed, iclass 13, count 2 2006.161.07:54:42.18#ibcon#about to write, iclass 13, count 2 2006.161.07:54:42.18#ibcon#wrote, iclass 13, count 2 2006.161.07:54:42.18#ibcon#about to read 3, iclass 13, count 2 2006.161.07:54:42.21#ibcon#read 3, iclass 13, count 2 2006.161.07:54:42.21#ibcon#about to read 4, iclass 13, count 2 2006.161.07:54:42.21#ibcon#read 4, iclass 13, count 2 2006.161.07:54:42.21#ibcon#about to read 5, iclass 13, count 2 2006.161.07:54:42.21#ibcon#read 5, iclass 13, count 2 2006.161.07:54:42.21#ibcon#about to read 6, iclass 13, count 2 2006.161.07:54:42.21#ibcon#read 6, iclass 13, count 2 2006.161.07:54:42.21#ibcon#end of sib2, iclass 13, count 2 2006.161.07:54:42.21#ibcon#*after write, iclass 13, count 2 2006.161.07:54:42.21#ibcon#*before return 0, iclass 13, count 2 2006.161.07:54:42.21#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:42.21#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.07:54:42.21#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.07:54:42.21#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:42.21#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:42.33#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:42.33#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:42.33#ibcon#enter wrdev, iclass 13, count 0 2006.161.07:54:42.33#ibcon#first serial, iclass 13, count 0 2006.161.07:54:42.33#ibcon#enter sib2, iclass 13, count 0 2006.161.07:54:42.33#ibcon#flushed, iclass 13, count 0 2006.161.07:54:42.33#ibcon#about to write, iclass 13, count 0 2006.161.07:54:42.33#ibcon#wrote, iclass 13, count 0 2006.161.07:54:42.33#ibcon#about to read 3, iclass 13, count 0 2006.161.07:54:42.35#ibcon#read 3, iclass 13, count 0 2006.161.07:54:42.35#ibcon#about to read 4, iclass 13, count 0 2006.161.07:54:42.35#ibcon#read 4, iclass 13, count 0 2006.161.07:54:42.35#ibcon#about to read 5, iclass 13, count 0 2006.161.07:54:42.35#ibcon#read 5, iclass 13, count 0 2006.161.07:54:42.35#ibcon#about to read 6, iclass 13, count 0 2006.161.07:54:42.35#ibcon#read 6, iclass 13, count 0 2006.161.07:54:42.35#ibcon#end of sib2, iclass 13, count 0 2006.161.07:54:42.35#ibcon#*mode == 0, iclass 13, count 0 2006.161.07:54:42.35#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.07:54:42.35#ibcon#[27=USB\r\n] 2006.161.07:54:42.35#ibcon#*before write, iclass 13, count 0 2006.161.07:54:42.35#ibcon#enter sib2, iclass 13, count 0 2006.161.07:54:42.35#ibcon#flushed, iclass 13, count 0 2006.161.07:54:42.35#ibcon#about to write, iclass 13, count 0 2006.161.07:54:42.35#ibcon#wrote, iclass 13, count 0 2006.161.07:54:42.35#ibcon#about to read 3, iclass 13, count 0 2006.161.07:54:42.38#ibcon#read 3, iclass 13, count 0 2006.161.07:54:42.38#ibcon#about to read 4, iclass 13, count 0 2006.161.07:54:42.38#ibcon#read 4, iclass 13, count 0 2006.161.07:54:42.38#ibcon#about to read 5, iclass 13, count 0 2006.161.07:54:42.38#ibcon#read 5, iclass 13, count 0 2006.161.07:54:42.38#ibcon#about to read 6, iclass 13, count 0 2006.161.07:54:42.38#ibcon#read 6, iclass 13, count 0 2006.161.07:54:42.38#ibcon#end of sib2, iclass 13, count 0 2006.161.07:54:42.38#ibcon#*after write, iclass 13, count 0 2006.161.07:54:42.38#ibcon#*before return 0, iclass 13, count 0 2006.161.07:54:42.38#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:42.38#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.07:54:42.38#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.07:54:42.38#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.07:54:42.38$vc4f8/vblo=3,656.99 2006.161.07:54:42.38#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.07:54:42.38#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.07:54:42.38#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:42.38#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:42.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:42.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:42.38#ibcon#enter wrdev, iclass 15, count 0 2006.161.07:54:42.38#ibcon#first serial, iclass 15, count 0 2006.161.07:54:42.38#ibcon#enter sib2, iclass 15, count 0 2006.161.07:54:42.38#ibcon#flushed, iclass 15, count 0 2006.161.07:54:42.38#ibcon#about to write, iclass 15, count 0 2006.161.07:54:42.38#ibcon#wrote, iclass 15, count 0 2006.161.07:54:42.38#ibcon#about to read 3, iclass 15, count 0 2006.161.07:54:42.40#ibcon#read 3, iclass 15, count 0 2006.161.07:54:42.40#ibcon#about to read 4, iclass 15, count 0 2006.161.07:54:42.40#ibcon#read 4, iclass 15, count 0 2006.161.07:54:42.40#ibcon#about to read 5, iclass 15, count 0 2006.161.07:54:42.40#ibcon#read 5, iclass 15, count 0 2006.161.07:54:42.40#ibcon#about to read 6, iclass 15, count 0 2006.161.07:54:42.40#ibcon#read 6, iclass 15, count 0 2006.161.07:54:42.40#ibcon#end of sib2, iclass 15, count 0 2006.161.07:54:42.40#ibcon#*mode == 0, iclass 15, count 0 2006.161.07:54:42.40#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.07:54:42.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:54:42.40#ibcon#*before write, iclass 15, count 0 2006.161.07:54:42.40#ibcon#enter sib2, iclass 15, count 0 2006.161.07:54:42.40#ibcon#flushed, iclass 15, count 0 2006.161.07:54:42.40#ibcon#about to write, iclass 15, count 0 2006.161.07:54:42.40#ibcon#wrote, iclass 15, count 0 2006.161.07:54:42.40#ibcon#about to read 3, iclass 15, count 0 2006.161.07:54:42.44#ibcon#read 3, iclass 15, count 0 2006.161.07:54:42.44#ibcon#about to read 4, iclass 15, count 0 2006.161.07:54:42.44#ibcon#read 4, iclass 15, count 0 2006.161.07:54:42.44#ibcon#about to read 5, iclass 15, count 0 2006.161.07:54:42.44#ibcon#read 5, iclass 15, count 0 2006.161.07:54:42.44#ibcon#about to read 6, iclass 15, count 0 2006.161.07:54:42.44#ibcon#read 6, iclass 15, count 0 2006.161.07:54:42.44#ibcon#end of sib2, iclass 15, count 0 2006.161.07:54:42.44#ibcon#*after write, iclass 15, count 0 2006.161.07:54:42.44#ibcon#*before return 0, iclass 15, count 0 2006.161.07:54:42.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:42.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.07:54:42.44#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.07:54:42.44#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.07:54:42.44$vc4f8/vb=3,4 2006.161.07:54:42.44#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.07:54:42.44#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.07:54:42.44#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:42.44#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:42.50#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:42.50#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:42.50#ibcon#enter wrdev, iclass 17, count 2 2006.161.07:54:42.50#ibcon#first serial, iclass 17, count 2 2006.161.07:54:42.50#ibcon#enter sib2, iclass 17, count 2 2006.161.07:54:42.50#ibcon#flushed, iclass 17, count 2 2006.161.07:54:42.50#ibcon#about to write, iclass 17, count 2 2006.161.07:54:42.50#ibcon#wrote, iclass 17, count 2 2006.161.07:54:42.50#ibcon#about to read 3, iclass 17, count 2 2006.161.07:54:42.52#ibcon#read 3, iclass 17, count 2 2006.161.07:54:42.52#ibcon#about to read 4, iclass 17, count 2 2006.161.07:54:42.52#ibcon#read 4, iclass 17, count 2 2006.161.07:54:42.52#ibcon#about to read 5, iclass 17, count 2 2006.161.07:54:42.52#ibcon#read 5, iclass 17, count 2 2006.161.07:54:42.52#ibcon#about to read 6, iclass 17, count 2 2006.161.07:54:42.52#ibcon#read 6, iclass 17, count 2 2006.161.07:54:42.52#ibcon#end of sib2, iclass 17, count 2 2006.161.07:54:42.52#ibcon#*mode == 0, iclass 17, count 2 2006.161.07:54:42.52#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.07:54:42.52#ibcon#[27=AT03-04\r\n] 2006.161.07:54:42.52#ibcon#*before write, iclass 17, count 2 2006.161.07:54:42.52#ibcon#enter sib2, iclass 17, count 2 2006.161.07:54:42.52#ibcon#flushed, iclass 17, count 2 2006.161.07:54:42.52#ibcon#about to write, iclass 17, count 2 2006.161.07:54:42.52#ibcon#wrote, iclass 17, count 2 2006.161.07:54:42.52#ibcon#about to read 3, iclass 17, count 2 2006.161.07:54:42.55#ibcon#read 3, iclass 17, count 2 2006.161.07:54:42.55#ibcon#about to read 4, iclass 17, count 2 2006.161.07:54:42.55#ibcon#read 4, iclass 17, count 2 2006.161.07:54:42.55#ibcon#about to read 5, iclass 17, count 2 2006.161.07:54:42.55#ibcon#read 5, iclass 17, count 2 2006.161.07:54:42.55#ibcon#about to read 6, iclass 17, count 2 2006.161.07:54:42.55#ibcon#read 6, iclass 17, count 2 2006.161.07:54:42.55#ibcon#end of sib2, iclass 17, count 2 2006.161.07:54:42.55#ibcon#*after write, iclass 17, count 2 2006.161.07:54:42.55#ibcon#*before return 0, iclass 17, count 2 2006.161.07:54:42.55#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:42.55#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.07:54:42.55#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.07:54:42.55#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:42.55#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:42.67#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:42.67#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:42.67#ibcon#enter wrdev, iclass 17, count 0 2006.161.07:54:42.67#ibcon#first serial, iclass 17, count 0 2006.161.07:54:42.67#ibcon#enter sib2, iclass 17, count 0 2006.161.07:54:42.67#ibcon#flushed, iclass 17, count 0 2006.161.07:54:42.67#ibcon#about to write, iclass 17, count 0 2006.161.07:54:42.67#ibcon#wrote, iclass 17, count 0 2006.161.07:54:42.67#ibcon#about to read 3, iclass 17, count 0 2006.161.07:54:42.69#ibcon#read 3, iclass 17, count 0 2006.161.07:54:42.69#ibcon#about to read 4, iclass 17, count 0 2006.161.07:54:42.69#ibcon#read 4, iclass 17, count 0 2006.161.07:54:42.69#ibcon#about to read 5, iclass 17, count 0 2006.161.07:54:42.69#ibcon#read 5, iclass 17, count 0 2006.161.07:54:42.69#ibcon#about to read 6, iclass 17, count 0 2006.161.07:54:42.69#ibcon#read 6, iclass 17, count 0 2006.161.07:54:42.69#ibcon#end of sib2, iclass 17, count 0 2006.161.07:54:42.69#ibcon#*mode == 0, iclass 17, count 0 2006.161.07:54:42.69#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.07:54:42.69#ibcon#[27=USB\r\n] 2006.161.07:54:42.69#ibcon#*before write, iclass 17, count 0 2006.161.07:54:42.69#ibcon#enter sib2, iclass 17, count 0 2006.161.07:54:42.69#ibcon#flushed, iclass 17, count 0 2006.161.07:54:42.69#ibcon#about to write, iclass 17, count 0 2006.161.07:54:42.69#ibcon#wrote, iclass 17, count 0 2006.161.07:54:42.69#ibcon#about to read 3, iclass 17, count 0 2006.161.07:54:42.72#ibcon#read 3, iclass 17, count 0 2006.161.07:54:42.72#ibcon#about to read 4, iclass 17, count 0 2006.161.07:54:42.72#ibcon#read 4, iclass 17, count 0 2006.161.07:54:42.72#ibcon#about to read 5, iclass 17, count 0 2006.161.07:54:42.72#ibcon#read 5, iclass 17, count 0 2006.161.07:54:42.72#ibcon#about to read 6, iclass 17, count 0 2006.161.07:54:42.72#ibcon#read 6, iclass 17, count 0 2006.161.07:54:42.72#ibcon#end of sib2, iclass 17, count 0 2006.161.07:54:42.72#ibcon#*after write, iclass 17, count 0 2006.161.07:54:42.72#ibcon#*before return 0, iclass 17, count 0 2006.161.07:54:42.72#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:42.72#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.07:54:42.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.07:54:42.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.07:54:42.72$vc4f8/vblo=4,712.99 2006.161.07:54:42.72#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.07:54:42.72#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.07:54:42.72#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:42.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:42.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:42.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:42.72#ibcon#enter wrdev, iclass 19, count 0 2006.161.07:54:42.72#ibcon#first serial, iclass 19, count 0 2006.161.07:54:42.72#ibcon#enter sib2, iclass 19, count 0 2006.161.07:54:42.72#ibcon#flushed, iclass 19, count 0 2006.161.07:54:42.72#ibcon#about to write, iclass 19, count 0 2006.161.07:54:42.72#ibcon#wrote, iclass 19, count 0 2006.161.07:54:42.72#ibcon#about to read 3, iclass 19, count 0 2006.161.07:54:42.74#ibcon#read 3, iclass 19, count 0 2006.161.07:54:42.74#ibcon#about to read 4, iclass 19, count 0 2006.161.07:54:42.74#ibcon#read 4, iclass 19, count 0 2006.161.07:54:42.74#ibcon#about to read 5, iclass 19, count 0 2006.161.07:54:42.74#ibcon#read 5, iclass 19, count 0 2006.161.07:54:42.74#ibcon#about to read 6, iclass 19, count 0 2006.161.07:54:42.74#ibcon#read 6, iclass 19, count 0 2006.161.07:54:42.74#ibcon#end of sib2, iclass 19, count 0 2006.161.07:54:42.74#ibcon#*mode == 0, iclass 19, count 0 2006.161.07:54:42.74#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.07:54:42.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:54:42.74#ibcon#*before write, iclass 19, count 0 2006.161.07:54:42.74#ibcon#enter sib2, iclass 19, count 0 2006.161.07:54:42.74#ibcon#flushed, iclass 19, count 0 2006.161.07:54:42.74#ibcon#about to write, iclass 19, count 0 2006.161.07:54:42.74#ibcon#wrote, iclass 19, count 0 2006.161.07:54:42.74#ibcon#about to read 3, iclass 19, count 0 2006.161.07:54:42.78#ibcon#read 3, iclass 19, count 0 2006.161.07:54:42.78#ibcon#about to read 4, iclass 19, count 0 2006.161.07:54:42.78#ibcon#read 4, iclass 19, count 0 2006.161.07:54:42.78#ibcon#about to read 5, iclass 19, count 0 2006.161.07:54:42.78#ibcon#read 5, iclass 19, count 0 2006.161.07:54:42.78#ibcon#about to read 6, iclass 19, count 0 2006.161.07:54:42.78#ibcon#read 6, iclass 19, count 0 2006.161.07:54:42.78#ibcon#end of sib2, iclass 19, count 0 2006.161.07:54:42.78#ibcon#*after write, iclass 19, count 0 2006.161.07:54:42.78#ibcon#*before return 0, iclass 19, count 0 2006.161.07:54:42.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:42.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.07:54:42.78#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.07:54:42.78#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.07:54:42.78$vc4f8/vb=4,4 2006.161.07:54:42.78#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.07:54:42.78#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.07:54:42.78#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:42.78#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:42.84#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:42.84#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:42.84#ibcon#enter wrdev, iclass 21, count 2 2006.161.07:54:42.84#ibcon#first serial, iclass 21, count 2 2006.161.07:54:42.84#ibcon#enter sib2, iclass 21, count 2 2006.161.07:54:42.84#ibcon#flushed, iclass 21, count 2 2006.161.07:54:42.84#ibcon#about to write, iclass 21, count 2 2006.161.07:54:42.84#ibcon#wrote, iclass 21, count 2 2006.161.07:54:42.84#ibcon#about to read 3, iclass 21, count 2 2006.161.07:54:42.86#ibcon#read 3, iclass 21, count 2 2006.161.07:54:42.86#ibcon#about to read 4, iclass 21, count 2 2006.161.07:54:42.86#ibcon#read 4, iclass 21, count 2 2006.161.07:54:42.86#ibcon#about to read 5, iclass 21, count 2 2006.161.07:54:42.86#ibcon#read 5, iclass 21, count 2 2006.161.07:54:42.86#ibcon#about to read 6, iclass 21, count 2 2006.161.07:54:42.86#ibcon#read 6, iclass 21, count 2 2006.161.07:54:42.86#ibcon#end of sib2, iclass 21, count 2 2006.161.07:54:42.86#ibcon#*mode == 0, iclass 21, count 2 2006.161.07:54:42.86#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.07:54:42.86#ibcon#[27=AT04-04\r\n] 2006.161.07:54:42.86#ibcon#*before write, iclass 21, count 2 2006.161.07:54:42.86#ibcon#enter sib2, iclass 21, count 2 2006.161.07:54:42.86#ibcon#flushed, iclass 21, count 2 2006.161.07:54:42.86#ibcon#about to write, iclass 21, count 2 2006.161.07:54:42.86#ibcon#wrote, iclass 21, count 2 2006.161.07:54:42.86#ibcon#about to read 3, iclass 21, count 2 2006.161.07:54:42.89#ibcon#read 3, iclass 21, count 2 2006.161.07:54:42.89#ibcon#about to read 4, iclass 21, count 2 2006.161.07:54:42.89#ibcon#read 4, iclass 21, count 2 2006.161.07:54:42.89#ibcon#about to read 5, iclass 21, count 2 2006.161.07:54:42.89#ibcon#read 5, iclass 21, count 2 2006.161.07:54:42.89#ibcon#about to read 6, iclass 21, count 2 2006.161.07:54:42.89#ibcon#read 6, iclass 21, count 2 2006.161.07:54:42.89#ibcon#end of sib2, iclass 21, count 2 2006.161.07:54:42.89#ibcon#*after write, iclass 21, count 2 2006.161.07:54:42.89#ibcon#*before return 0, iclass 21, count 2 2006.161.07:54:42.89#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:42.89#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.07:54:42.89#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.07:54:42.89#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:42.89#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:43.01#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:43.01#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:43.01#ibcon#enter wrdev, iclass 21, count 0 2006.161.07:54:43.01#ibcon#first serial, iclass 21, count 0 2006.161.07:54:43.01#ibcon#enter sib2, iclass 21, count 0 2006.161.07:54:43.01#ibcon#flushed, iclass 21, count 0 2006.161.07:54:43.01#ibcon#about to write, iclass 21, count 0 2006.161.07:54:43.01#ibcon#wrote, iclass 21, count 0 2006.161.07:54:43.01#ibcon#about to read 3, iclass 21, count 0 2006.161.07:54:43.03#ibcon#read 3, iclass 21, count 0 2006.161.07:54:43.03#ibcon#about to read 4, iclass 21, count 0 2006.161.07:54:43.03#ibcon#read 4, iclass 21, count 0 2006.161.07:54:43.03#ibcon#about to read 5, iclass 21, count 0 2006.161.07:54:43.03#ibcon#read 5, iclass 21, count 0 2006.161.07:54:43.03#ibcon#about to read 6, iclass 21, count 0 2006.161.07:54:43.03#ibcon#read 6, iclass 21, count 0 2006.161.07:54:43.03#ibcon#end of sib2, iclass 21, count 0 2006.161.07:54:43.03#ibcon#*mode == 0, iclass 21, count 0 2006.161.07:54:43.03#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.07:54:43.03#ibcon#[27=USB\r\n] 2006.161.07:54:43.03#ibcon#*before write, iclass 21, count 0 2006.161.07:54:43.03#ibcon#enter sib2, iclass 21, count 0 2006.161.07:54:43.03#ibcon#flushed, iclass 21, count 0 2006.161.07:54:43.03#ibcon#about to write, iclass 21, count 0 2006.161.07:54:43.03#ibcon#wrote, iclass 21, count 0 2006.161.07:54:43.03#ibcon#about to read 3, iclass 21, count 0 2006.161.07:54:43.06#ibcon#read 3, iclass 21, count 0 2006.161.07:54:43.06#ibcon#about to read 4, iclass 21, count 0 2006.161.07:54:43.06#ibcon#read 4, iclass 21, count 0 2006.161.07:54:43.06#ibcon#about to read 5, iclass 21, count 0 2006.161.07:54:43.06#ibcon#read 5, iclass 21, count 0 2006.161.07:54:43.06#ibcon#about to read 6, iclass 21, count 0 2006.161.07:54:43.06#ibcon#read 6, iclass 21, count 0 2006.161.07:54:43.06#ibcon#end of sib2, iclass 21, count 0 2006.161.07:54:43.06#ibcon#*after write, iclass 21, count 0 2006.161.07:54:43.06#ibcon#*before return 0, iclass 21, count 0 2006.161.07:54:43.06#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:43.06#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.07:54:43.06#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.07:54:43.06#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.07:54:43.06$vc4f8/vblo=5,744.99 2006.161.07:54:43.06#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.07:54:43.06#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.07:54:43.06#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:43.06#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:43.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:43.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:43.06#ibcon#enter wrdev, iclass 23, count 0 2006.161.07:54:43.06#ibcon#first serial, iclass 23, count 0 2006.161.07:54:43.06#ibcon#enter sib2, iclass 23, count 0 2006.161.07:54:43.06#ibcon#flushed, iclass 23, count 0 2006.161.07:54:43.06#ibcon#about to write, iclass 23, count 0 2006.161.07:54:43.06#ibcon#wrote, iclass 23, count 0 2006.161.07:54:43.06#ibcon#about to read 3, iclass 23, count 0 2006.161.07:54:43.08#ibcon#read 3, iclass 23, count 0 2006.161.07:54:43.08#ibcon#about to read 4, iclass 23, count 0 2006.161.07:54:43.08#ibcon#read 4, iclass 23, count 0 2006.161.07:54:43.08#ibcon#about to read 5, iclass 23, count 0 2006.161.07:54:43.08#ibcon#read 5, iclass 23, count 0 2006.161.07:54:43.08#ibcon#about to read 6, iclass 23, count 0 2006.161.07:54:43.08#ibcon#read 6, iclass 23, count 0 2006.161.07:54:43.08#ibcon#end of sib2, iclass 23, count 0 2006.161.07:54:43.08#ibcon#*mode == 0, iclass 23, count 0 2006.161.07:54:43.08#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.07:54:43.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:54:43.08#ibcon#*before write, iclass 23, count 0 2006.161.07:54:43.08#ibcon#enter sib2, iclass 23, count 0 2006.161.07:54:43.08#ibcon#flushed, iclass 23, count 0 2006.161.07:54:43.08#ibcon#about to write, iclass 23, count 0 2006.161.07:54:43.08#ibcon#wrote, iclass 23, count 0 2006.161.07:54:43.08#ibcon#about to read 3, iclass 23, count 0 2006.161.07:54:43.12#ibcon#read 3, iclass 23, count 0 2006.161.07:54:43.12#ibcon#about to read 4, iclass 23, count 0 2006.161.07:54:43.12#ibcon#read 4, iclass 23, count 0 2006.161.07:54:43.12#ibcon#about to read 5, iclass 23, count 0 2006.161.07:54:43.12#ibcon#read 5, iclass 23, count 0 2006.161.07:54:43.12#ibcon#about to read 6, iclass 23, count 0 2006.161.07:54:43.12#ibcon#read 6, iclass 23, count 0 2006.161.07:54:43.12#ibcon#end of sib2, iclass 23, count 0 2006.161.07:54:43.12#ibcon#*after write, iclass 23, count 0 2006.161.07:54:43.12#ibcon#*before return 0, iclass 23, count 0 2006.161.07:54:43.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:43.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.07:54:43.12#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.07:54:43.12#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.07:54:43.12$vc4f8/vb=5,4 2006.161.07:54:43.12#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.07:54:43.12#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.07:54:43.12#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:43.12#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:43.18#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:43.18#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:43.18#ibcon#enter wrdev, iclass 25, count 2 2006.161.07:54:43.18#ibcon#first serial, iclass 25, count 2 2006.161.07:54:43.18#ibcon#enter sib2, iclass 25, count 2 2006.161.07:54:43.18#ibcon#flushed, iclass 25, count 2 2006.161.07:54:43.18#ibcon#about to write, iclass 25, count 2 2006.161.07:54:43.18#ibcon#wrote, iclass 25, count 2 2006.161.07:54:43.18#ibcon#about to read 3, iclass 25, count 2 2006.161.07:54:43.20#ibcon#read 3, iclass 25, count 2 2006.161.07:54:43.20#ibcon#about to read 4, iclass 25, count 2 2006.161.07:54:43.20#ibcon#read 4, iclass 25, count 2 2006.161.07:54:43.20#ibcon#about to read 5, iclass 25, count 2 2006.161.07:54:43.20#ibcon#read 5, iclass 25, count 2 2006.161.07:54:43.20#ibcon#about to read 6, iclass 25, count 2 2006.161.07:54:43.20#ibcon#read 6, iclass 25, count 2 2006.161.07:54:43.20#ibcon#end of sib2, iclass 25, count 2 2006.161.07:54:43.20#ibcon#*mode == 0, iclass 25, count 2 2006.161.07:54:43.20#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.07:54:43.20#ibcon#[27=AT05-04\r\n] 2006.161.07:54:43.20#ibcon#*before write, iclass 25, count 2 2006.161.07:54:43.20#ibcon#enter sib2, iclass 25, count 2 2006.161.07:54:43.20#ibcon#flushed, iclass 25, count 2 2006.161.07:54:43.20#ibcon#about to write, iclass 25, count 2 2006.161.07:54:43.20#ibcon#wrote, iclass 25, count 2 2006.161.07:54:43.20#ibcon#about to read 3, iclass 25, count 2 2006.161.07:54:43.23#ibcon#read 3, iclass 25, count 2 2006.161.07:54:43.23#ibcon#about to read 4, iclass 25, count 2 2006.161.07:54:43.23#ibcon#read 4, iclass 25, count 2 2006.161.07:54:43.23#ibcon#about to read 5, iclass 25, count 2 2006.161.07:54:43.23#ibcon#read 5, iclass 25, count 2 2006.161.07:54:43.23#ibcon#about to read 6, iclass 25, count 2 2006.161.07:54:43.23#ibcon#read 6, iclass 25, count 2 2006.161.07:54:43.23#ibcon#end of sib2, iclass 25, count 2 2006.161.07:54:43.23#ibcon#*after write, iclass 25, count 2 2006.161.07:54:43.23#ibcon#*before return 0, iclass 25, count 2 2006.161.07:54:43.23#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:43.23#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.07:54:43.23#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.07:54:43.23#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:43.23#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:43.35#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:43.35#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:43.35#ibcon#enter wrdev, iclass 25, count 0 2006.161.07:54:43.35#ibcon#first serial, iclass 25, count 0 2006.161.07:54:43.35#ibcon#enter sib2, iclass 25, count 0 2006.161.07:54:43.35#ibcon#flushed, iclass 25, count 0 2006.161.07:54:43.35#ibcon#about to write, iclass 25, count 0 2006.161.07:54:43.35#ibcon#wrote, iclass 25, count 0 2006.161.07:54:43.35#ibcon#about to read 3, iclass 25, count 0 2006.161.07:54:43.37#ibcon#read 3, iclass 25, count 0 2006.161.07:54:43.37#ibcon#about to read 4, iclass 25, count 0 2006.161.07:54:43.37#ibcon#read 4, iclass 25, count 0 2006.161.07:54:43.37#ibcon#about to read 5, iclass 25, count 0 2006.161.07:54:43.37#ibcon#read 5, iclass 25, count 0 2006.161.07:54:43.37#ibcon#about to read 6, iclass 25, count 0 2006.161.07:54:43.37#ibcon#read 6, iclass 25, count 0 2006.161.07:54:43.37#ibcon#end of sib2, iclass 25, count 0 2006.161.07:54:43.37#ibcon#*mode == 0, iclass 25, count 0 2006.161.07:54:43.37#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.07:54:43.37#ibcon#[27=USB\r\n] 2006.161.07:54:43.37#ibcon#*before write, iclass 25, count 0 2006.161.07:54:43.37#ibcon#enter sib2, iclass 25, count 0 2006.161.07:54:43.37#ibcon#flushed, iclass 25, count 0 2006.161.07:54:43.37#ibcon#about to write, iclass 25, count 0 2006.161.07:54:43.37#ibcon#wrote, iclass 25, count 0 2006.161.07:54:43.37#ibcon#about to read 3, iclass 25, count 0 2006.161.07:54:43.40#ibcon#read 3, iclass 25, count 0 2006.161.07:54:43.40#ibcon#about to read 4, iclass 25, count 0 2006.161.07:54:43.40#ibcon#read 4, iclass 25, count 0 2006.161.07:54:43.40#ibcon#about to read 5, iclass 25, count 0 2006.161.07:54:43.40#ibcon#read 5, iclass 25, count 0 2006.161.07:54:43.40#ibcon#about to read 6, iclass 25, count 0 2006.161.07:54:43.40#ibcon#read 6, iclass 25, count 0 2006.161.07:54:43.40#ibcon#end of sib2, iclass 25, count 0 2006.161.07:54:43.40#ibcon#*after write, iclass 25, count 0 2006.161.07:54:43.40#ibcon#*before return 0, iclass 25, count 0 2006.161.07:54:43.40#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:43.40#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.07:54:43.40#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.07:54:43.40#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.07:54:43.40$vc4f8/vblo=6,752.99 2006.161.07:54:43.40#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.07:54:43.40#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.07:54:43.40#ibcon#ireg 17 cls_cnt 0 2006.161.07:54:43.40#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:43.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:43.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:43.40#ibcon#enter wrdev, iclass 27, count 0 2006.161.07:54:43.40#ibcon#first serial, iclass 27, count 0 2006.161.07:54:43.40#ibcon#enter sib2, iclass 27, count 0 2006.161.07:54:43.40#ibcon#flushed, iclass 27, count 0 2006.161.07:54:43.40#ibcon#about to write, iclass 27, count 0 2006.161.07:54:43.40#ibcon#wrote, iclass 27, count 0 2006.161.07:54:43.40#ibcon#about to read 3, iclass 27, count 0 2006.161.07:54:43.42#ibcon#read 3, iclass 27, count 0 2006.161.07:54:43.42#ibcon#about to read 4, iclass 27, count 0 2006.161.07:54:43.42#ibcon#read 4, iclass 27, count 0 2006.161.07:54:43.42#ibcon#about to read 5, iclass 27, count 0 2006.161.07:54:43.42#ibcon#read 5, iclass 27, count 0 2006.161.07:54:43.42#ibcon#about to read 6, iclass 27, count 0 2006.161.07:54:43.42#ibcon#read 6, iclass 27, count 0 2006.161.07:54:43.42#ibcon#end of sib2, iclass 27, count 0 2006.161.07:54:43.42#ibcon#*mode == 0, iclass 27, count 0 2006.161.07:54:43.42#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.07:54:43.42#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:54:43.42#ibcon#*before write, iclass 27, count 0 2006.161.07:54:43.42#ibcon#enter sib2, iclass 27, count 0 2006.161.07:54:43.42#ibcon#flushed, iclass 27, count 0 2006.161.07:54:43.42#ibcon#about to write, iclass 27, count 0 2006.161.07:54:43.42#ibcon#wrote, iclass 27, count 0 2006.161.07:54:43.42#ibcon#about to read 3, iclass 27, count 0 2006.161.07:54:43.46#ibcon#read 3, iclass 27, count 0 2006.161.07:54:43.46#ibcon#about to read 4, iclass 27, count 0 2006.161.07:54:43.46#ibcon#read 4, iclass 27, count 0 2006.161.07:54:43.46#ibcon#about to read 5, iclass 27, count 0 2006.161.07:54:43.46#ibcon#read 5, iclass 27, count 0 2006.161.07:54:43.46#ibcon#about to read 6, iclass 27, count 0 2006.161.07:54:43.46#ibcon#read 6, iclass 27, count 0 2006.161.07:54:43.46#ibcon#end of sib2, iclass 27, count 0 2006.161.07:54:43.46#ibcon#*after write, iclass 27, count 0 2006.161.07:54:43.46#ibcon#*before return 0, iclass 27, count 0 2006.161.07:54:43.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:43.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.07:54:43.46#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.07:54:43.46#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.07:54:43.46$vc4f8/vb=6,4 2006.161.07:54:43.46#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.07:54:43.46#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.07:54:43.46#ibcon#ireg 11 cls_cnt 2 2006.161.07:54:43.46#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:43.52#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:43.52#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:43.52#ibcon#enter wrdev, iclass 29, count 2 2006.161.07:54:43.52#ibcon#first serial, iclass 29, count 2 2006.161.07:54:43.52#ibcon#enter sib2, iclass 29, count 2 2006.161.07:54:43.52#ibcon#flushed, iclass 29, count 2 2006.161.07:54:43.52#ibcon#about to write, iclass 29, count 2 2006.161.07:54:43.52#ibcon#wrote, iclass 29, count 2 2006.161.07:54:43.52#ibcon#about to read 3, iclass 29, count 2 2006.161.07:54:43.54#ibcon#read 3, iclass 29, count 2 2006.161.07:54:43.54#ibcon#about to read 4, iclass 29, count 2 2006.161.07:54:43.54#ibcon#read 4, iclass 29, count 2 2006.161.07:54:43.54#ibcon#about to read 5, iclass 29, count 2 2006.161.07:54:43.54#ibcon#read 5, iclass 29, count 2 2006.161.07:54:43.54#ibcon#about to read 6, iclass 29, count 2 2006.161.07:54:43.54#ibcon#read 6, iclass 29, count 2 2006.161.07:54:43.54#ibcon#end of sib2, iclass 29, count 2 2006.161.07:54:43.54#ibcon#*mode == 0, iclass 29, count 2 2006.161.07:54:43.54#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.07:54:43.54#ibcon#[27=AT06-04\r\n] 2006.161.07:54:43.54#ibcon#*before write, iclass 29, count 2 2006.161.07:54:43.54#ibcon#enter sib2, iclass 29, count 2 2006.161.07:54:43.54#ibcon#flushed, iclass 29, count 2 2006.161.07:54:43.54#ibcon#about to write, iclass 29, count 2 2006.161.07:54:43.54#ibcon#wrote, iclass 29, count 2 2006.161.07:54:43.54#ibcon#about to read 3, iclass 29, count 2 2006.161.07:54:43.57#ibcon#read 3, iclass 29, count 2 2006.161.07:54:43.57#ibcon#about to read 4, iclass 29, count 2 2006.161.07:54:43.57#ibcon#read 4, iclass 29, count 2 2006.161.07:54:43.57#ibcon#about to read 5, iclass 29, count 2 2006.161.07:54:43.57#ibcon#read 5, iclass 29, count 2 2006.161.07:54:43.57#ibcon#about to read 6, iclass 29, count 2 2006.161.07:54:43.57#ibcon#read 6, iclass 29, count 2 2006.161.07:54:43.57#ibcon#end of sib2, iclass 29, count 2 2006.161.07:54:43.57#ibcon#*after write, iclass 29, count 2 2006.161.07:54:43.57#ibcon#*before return 0, iclass 29, count 2 2006.161.07:54:43.57#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:43.57#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.07:54:43.57#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.07:54:43.57#ibcon#ireg 7 cls_cnt 0 2006.161.07:54:43.57#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:43.69#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:43.69#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:43.69#ibcon#enter wrdev, iclass 29, count 0 2006.161.07:54:43.69#ibcon#first serial, iclass 29, count 0 2006.161.07:54:43.69#ibcon#enter sib2, iclass 29, count 0 2006.161.07:54:43.69#ibcon#flushed, iclass 29, count 0 2006.161.07:54:43.69#ibcon#about to write, iclass 29, count 0 2006.161.07:54:43.69#ibcon#wrote, iclass 29, count 0 2006.161.07:54:43.69#ibcon#about to read 3, iclass 29, count 0 2006.161.07:54:43.71#ibcon#read 3, iclass 29, count 0 2006.161.07:54:43.71#ibcon#about to read 4, iclass 29, count 0 2006.161.07:54:43.71#ibcon#read 4, iclass 29, count 0 2006.161.07:54:43.71#ibcon#about to read 5, iclass 29, count 0 2006.161.07:54:43.71#ibcon#read 5, iclass 29, count 0 2006.161.07:54:43.71#ibcon#about to read 6, iclass 29, count 0 2006.161.07:54:43.71#ibcon#read 6, iclass 29, count 0 2006.161.07:54:43.71#ibcon#end of sib2, iclass 29, count 0 2006.161.07:54:43.71#ibcon#*mode == 0, iclass 29, count 0 2006.161.07:54:43.71#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.07:54:43.71#ibcon#[27=USB\r\n] 2006.161.07:54:43.71#ibcon#*before write, iclass 29, count 0 2006.161.07:54:43.71#ibcon#enter sib2, iclass 29, count 0 2006.161.07:54:43.71#ibcon#flushed, iclass 29, count 0 2006.161.07:54:43.71#ibcon#about to write, iclass 29, count 0 2006.161.07:54:43.71#ibcon#wrote, iclass 29, count 0 2006.161.07:54:43.71#ibcon#about to read 3, iclass 29, count 0 2006.161.07:54:43.74#ibcon#read 3, iclass 29, count 0 2006.161.07:54:43.74#ibcon#about to read 4, iclass 29, count 0 2006.161.07:54:43.74#ibcon#read 4, iclass 29, count 0 2006.161.07:54:43.74#ibcon#about to read 5, iclass 29, count 0 2006.161.07:54:43.74#ibcon#read 5, iclass 29, count 0 2006.161.07:54:43.74#ibcon#about to read 6, iclass 29, count 0 2006.161.07:54:43.74#ibcon#read 6, iclass 29, count 0 2006.161.07:54:43.74#ibcon#end of sib2, iclass 29, count 0 2006.161.07:54:43.74#ibcon#*after write, iclass 29, count 0 2006.161.07:54:43.74#ibcon#*before return 0, iclass 29, count 0 2006.161.07:54:43.74#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:43.74#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.07:54:43.74#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.07:54:43.74#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.07:54:43.74$vc4f8/vabw=wide 2006.161.07:54:43.74#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.07:54:43.74#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.07:54:43.74#ibcon#ireg 8 cls_cnt 0 2006.161.07:54:43.74#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:54:43.74#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:54:43.74#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:54:43.74#ibcon#enter wrdev, iclass 31, count 0 2006.161.07:54:43.74#ibcon#first serial, iclass 31, count 0 2006.161.07:54:43.74#ibcon#enter sib2, iclass 31, count 0 2006.161.07:54:43.74#ibcon#flushed, iclass 31, count 0 2006.161.07:54:43.74#ibcon#about to write, iclass 31, count 0 2006.161.07:54:43.74#ibcon#wrote, iclass 31, count 0 2006.161.07:54:43.74#ibcon#about to read 3, iclass 31, count 0 2006.161.07:54:43.76#ibcon#read 3, iclass 31, count 0 2006.161.07:54:43.76#ibcon#about to read 4, iclass 31, count 0 2006.161.07:54:43.76#ibcon#read 4, iclass 31, count 0 2006.161.07:54:43.76#ibcon#about to read 5, iclass 31, count 0 2006.161.07:54:43.76#ibcon#read 5, iclass 31, count 0 2006.161.07:54:43.76#ibcon#about to read 6, iclass 31, count 0 2006.161.07:54:43.76#ibcon#read 6, iclass 31, count 0 2006.161.07:54:43.76#ibcon#end of sib2, iclass 31, count 0 2006.161.07:54:43.76#ibcon#*mode == 0, iclass 31, count 0 2006.161.07:54:43.76#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.07:54:43.76#ibcon#[25=BW32\r\n] 2006.161.07:54:43.76#ibcon#*before write, iclass 31, count 0 2006.161.07:54:43.76#ibcon#enter sib2, iclass 31, count 0 2006.161.07:54:43.76#ibcon#flushed, iclass 31, count 0 2006.161.07:54:43.76#ibcon#about to write, iclass 31, count 0 2006.161.07:54:43.76#ibcon#wrote, iclass 31, count 0 2006.161.07:54:43.76#ibcon#about to read 3, iclass 31, count 0 2006.161.07:54:43.79#ibcon#read 3, iclass 31, count 0 2006.161.07:54:43.79#ibcon#about to read 4, iclass 31, count 0 2006.161.07:54:43.79#ibcon#read 4, iclass 31, count 0 2006.161.07:54:43.79#ibcon#about to read 5, iclass 31, count 0 2006.161.07:54:43.79#ibcon#read 5, iclass 31, count 0 2006.161.07:54:43.79#ibcon#about to read 6, iclass 31, count 0 2006.161.07:54:43.79#ibcon#read 6, iclass 31, count 0 2006.161.07:54:43.79#ibcon#end of sib2, iclass 31, count 0 2006.161.07:54:43.79#ibcon#*after write, iclass 31, count 0 2006.161.07:54:43.79#ibcon#*before return 0, iclass 31, count 0 2006.161.07:54:43.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:54:43.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.07:54:43.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.07:54:43.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.07:54:43.79$vc4f8/vbbw=wide 2006.161.07:54:43.79#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.07:54:43.79#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.07:54:43.79#ibcon#ireg 8 cls_cnt 0 2006.161.07:54:43.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:54:43.86#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:54:43.86#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:54:43.86#ibcon#enter wrdev, iclass 33, count 0 2006.161.07:54:43.86#ibcon#first serial, iclass 33, count 0 2006.161.07:54:43.86#ibcon#enter sib2, iclass 33, count 0 2006.161.07:54:43.86#ibcon#flushed, iclass 33, count 0 2006.161.07:54:43.86#ibcon#about to write, iclass 33, count 0 2006.161.07:54:43.86#ibcon#wrote, iclass 33, count 0 2006.161.07:54:43.86#ibcon#about to read 3, iclass 33, count 0 2006.161.07:54:43.88#ibcon#read 3, iclass 33, count 0 2006.161.07:54:43.88#ibcon#about to read 4, iclass 33, count 0 2006.161.07:54:43.88#ibcon#read 4, iclass 33, count 0 2006.161.07:54:43.88#ibcon#about to read 5, iclass 33, count 0 2006.161.07:54:43.88#ibcon#read 5, iclass 33, count 0 2006.161.07:54:43.88#ibcon#about to read 6, iclass 33, count 0 2006.161.07:54:43.88#ibcon#read 6, iclass 33, count 0 2006.161.07:54:43.88#ibcon#end of sib2, iclass 33, count 0 2006.161.07:54:43.88#ibcon#*mode == 0, iclass 33, count 0 2006.161.07:54:43.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.07:54:43.88#ibcon#[27=BW32\r\n] 2006.161.07:54:43.88#ibcon#*before write, iclass 33, count 0 2006.161.07:54:43.88#ibcon#enter sib2, iclass 33, count 0 2006.161.07:54:43.88#ibcon#flushed, iclass 33, count 0 2006.161.07:54:43.88#ibcon#about to write, iclass 33, count 0 2006.161.07:54:43.88#ibcon#wrote, iclass 33, count 0 2006.161.07:54:43.88#ibcon#about to read 3, iclass 33, count 0 2006.161.07:54:43.91#ibcon#read 3, iclass 33, count 0 2006.161.07:54:43.91#ibcon#about to read 4, iclass 33, count 0 2006.161.07:54:43.91#ibcon#read 4, iclass 33, count 0 2006.161.07:54:43.91#ibcon#about to read 5, iclass 33, count 0 2006.161.07:54:43.91#ibcon#read 5, iclass 33, count 0 2006.161.07:54:43.91#ibcon#about to read 6, iclass 33, count 0 2006.161.07:54:43.91#ibcon#read 6, iclass 33, count 0 2006.161.07:54:43.91#ibcon#end of sib2, iclass 33, count 0 2006.161.07:54:43.91#ibcon#*after write, iclass 33, count 0 2006.161.07:54:43.91#ibcon#*before return 0, iclass 33, count 0 2006.161.07:54:43.91#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:54:43.91#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.07:54:43.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.07:54:43.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.07:54:43.91$4f8m12a/ifd4f 2006.161.07:54:43.91$ifd4f/lo= 2006.161.07:54:43.91$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:54:43.91$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:54:43.91$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:54:43.91$ifd4f/patch= 2006.161.07:54:43.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:54:43.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:54:43.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:54:43.91$4f8m12a/"form=m,16.000,1:2 2006.161.07:54:43.91$4f8m12a/"tpicd 2006.161.07:54:43.91$4f8m12a/echo=off 2006.161.07:54:43.91$4f8m12a/xlog=off 2006.161.07:54:43.91:!2006.161.07:56:50 2006.161.07:54:53.14#trakl#Source acquired 2006.161.07:54:55.14#flagr#flagr/antenna,acquired 2006.161.07:56:50.00:preob 2006.161.07:56:50.13/onsource/TRACKING 2006.161.07:56:50.13:!2006.161.07:57:00 2006.161.07:57:00.00:data_valid=on 2006.161.07:57:00.00:midob 2006.161.07:57:01.13/onsource/TRACKING 2006.161.07:57:01.13/wx/24.04,1002.0,86 2006.161.07:57:01.26/cable/+6.4985E-03 2006.161.07:57:02.35/va/01,08,usb,yes,29,30 2006.161.07:57:02.35/va/02,07,usb,yes,29,30 2006.161.07:57:02.35/va/03,06,usb,yes,30,31 2006.161.07:57:02.35/va/04,07,usb,yes,30,32 2006.161.07:57:02.35/va/05,07,usb,yes,30,31 2006.161.07:57:02.35/va/06,06,usb,yes,29,28 2006.161.07:57:02.35/va/07,06,usb,yes,29,29 2006.161.07:57:02.35/va/08,07,usb,yes,27,27 2006.161.07:57:02.58/valo/01,532.99,yes,locked 2006.161.07:57:02.58/valo/02,572.99,yes,locked 2006.161.07:57:02.58/valo/03,672.99,yes,locked 2006.161.07:57:02.58/valo/04,832.99,yes,locked 2006.161.07:57:02.58/valo/05,652.99,yes,locked 2006.161.07:57:02.58/valo/06,772.99,yes,locked 2006.161.07:57:02.58/valo/07,832.99,yes,locked 2006.161.07:57:02.58/valo/08,852.99,yes,locked 2006.161.07:57:03.67/vb/01,04,usb,yes,29,28 2006.161.07:57:03.67/vb/02,04,usb,yes,31,32 2006.161.07:57:03.67/vb/03,04,usb,yes,27,31 2006.161.07:57:03.67/vb/04,04,usb,yes,28,28 2006.161.07:57:03.67/vb/05,04,usb,yes,27,30 2006.161.07:57:03.67/vb/06,04,usb,yes,28,30 2006.161.07:57:03.67/vb/07,04,usb,yes,29,29 2006.161.07:57:03.67/vb/08,04,usb,yes,27,30 2006.161.07:57:03.91/vblo/01,632.99,yes,locked 2006.161.07:57:03.91/vblo/02,640.99,yes,locked 2006.161.07:57:03.91/vblo/03,656.99,yes,locked 2006.161.07:57:03.91/vblo/04,712.99,yes,locked 2006.161.07:57:03.91/vblo/05,744.99,yes,locked 2006.161.07:57:03.91/vblo/06,752.99,yes,locked 2006.161.07:57:03.91/vblo/07,734.99,yes,locked 2006.161.07:57:03.91/vblo/08,744.99,yes,locked 2006.161.07:57:04.06/vabw/8 2006.161.07:57:04.21/vbbw/8 2006.161.07:57:04.30/xfe/off,on,14.7 2006.161.07:57:04.68/ifatt/23,28,28,28 2006.161.07:57:05.08/fmout-gps/S +4.48E-07 2006.161.07:57:05.12:!2006.161.07:58:00 2006.161.07:58:00.00:data_valid=off 2006.161.07:58:00.00:postob 2006.161.07:58:00.14/cable/+6.4987E-03 2006.161.07:58:00.14/wx/24.04,1002.1,86 2006.161.07:58:01.08/fmout-gps/S +4.48E-07 2006.161.07:58:01.08:scan_name=161-0759,k06161,60 2006.161.07:58:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.161.07:58:01.13#flagr#flagr/antenna,new-source 2006.161.07:58:02.14:checkk5 2006.161.07:58:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.07:58:03.00/chk_autoobs//k5ts2/ autoobs is running! 2006.161.07:58:03.43/chk_autoobs//k5ts3/ autoobs is running! 2006.161.07:58:03.88/chk_autoobs//k5ts4/ autoobs is running! 2006.161.07:58:04.30/chk_obsdata//k5ts1/T1610757??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:58:04.70/chk_obsdata//k5ts2/T1610757??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:58:05.12/chk_obsdata//k5ts3/T1610757??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:58:05.55/chk_obsdata//k5ts4/T1610757??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.07:58:06.35/k5log//k5ts1_log_newline 2006.161.07:58:07.19/k5log//k5ts2_log_newline 2006.161.07:58:07.95/k5log//k5ts3_log_newline 2006.161.07:58:08.67/k5log//k5ts4_log_newline 2006.161.07:58:08.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.07:58:08.69:4f8m12a=2 2006.161.07:58:08.69$4f8m12a/echo=on 2006.161.07:58:08.69$4f8m12a/pcalon 2006.161.07:58:08.69$pcalon/"no phase cal control is implemented here 2006.161.07:58:08.69$4f8m12a/"tpicd=stop 2006.161.07:58:08.69$4f8m12a/vc4f8 2006.161.07:58:08.69$vc4f8/valo=1,532.99 2006.161.07:58:08.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:58:08.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:58:08.70#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:08.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:08.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:08.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:08.70#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:58:08.70#ibcon#first serial, iclass 6, count 0 2006.161.07:58:08.70#ibcon#enter sib2, iclass 6, count 0 2006.161.07:58:08.70#ibcon#flushed, iclass 6, count 0 2006.161.07:58:08.70#ibcon#about to write, iclass 6, count 0 2006.161.07:58:08.70#ibcon#wrote, iclass 6, count 0 2006.161.07:58:08.70#ibcon#about to read 3, iclass 6, count 0 2006.161.07:58:08.74#ibcon#read 3, iclass 6, count 0 2006.161.07:58:08.74#ibcon#about to read 4, iclass 6, count 0 2006.161.07:58:08.74#ibcon#read 4, iclass 6, count 0 2006.161.07:58:08.74#ibcon#about to read 5, iclass 6, count 0 2006.161.07:58:08.74#ibcon#read 5, iclass 6, count 0 2006.161.07:58:08.74#ibcon#about to read 6, iclass 6, count 0 2006.161.07:58:08.74#ibcon#read 6, iclass 6, count 0 2006.161.07:58:08.74#ibcon#end of sib2, iclass 6, count 0 2006.161.07:58:08.74#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:58:08.74#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:58:08.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.07:58:08.74#ibcon#*before write, iclass 6, count 0 2006.161.07:58:08.74#ibcon#enter sib2, iclass 6, count 0 2006.161.07:58:08.74#ibcon#flushed, iclass 6, count 0 2006.161.07:58:08.74#ibcon#about to write, iclass 6, count 0 2006.161.07:58:08.74#ibcon#wrote, iclass 6, count 0 2006.161.07:58:08.74#ibcon#about to read 3, iclass 6, count 0 2006.161.07:58:08.79#ibcon#read 3, iclass 6, count 0 2006.161.07:58:08.79#ibcon#about to read 4, iclass 6, count 0 2006.161.07:58:08.79#ibcon#read 4, iclass 6, count 0 2006.161.07:58:08.79#ibcon#about to read 5, iclass 6, count 0 2006.161.07:58:08.79#ibcon#read 5, iclass 6, count 0 2006.161.07:58:08.79#ibcon#about to read 6, iclass 6, count 0 2006.161.07:58:08.79#ibcon#read 6, iclass 6, count 0 2006.161.07:58:08.79#ibcon#end of sib2, iclass 6, count 0 2006.161.07:58:08.79#ibcon#*after write, iclass 6, count 0 2006.161.07:58:08.79#ibcon#*before return 0, iclass 6, count 0 2006.161.07:58:08.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:08.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:08.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:58:08.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:58:08.79$vc4f8/va=1,8 2006.161.07:58:08.79#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:58:08.79#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:58:08.79#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:08.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:08.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:08.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:08.79#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:58:08.79#ibcon#first serial, iclass 10, count 2 2006.161.07:58:08.79#ibcon#enter sib2, iclass 10, count 2 2006.161.07:58:08.79#ibcon#flushed, iclass 10, count 2 2006.161.07:58:08.79#ibcon#about to write, iclass 10, count 2 2006.161.07:58:08.79#ibcon#wrote, iclass 10, count 2 2006.161.07:58:08.79#ibcon#about to read 3, iclass 10, count 2 2006.161.07:58:08.81#ibcon#read 3, iclass 10, count 2 2006.161.07:58:08.81#ibcon#about to read 4, iclass 10, count 2 2006.161.07:58:08.81#ibcon#read 4, iclass 10, count 2 2006.161.07:58:08.81#ibcon#about to read 5, iclass 10, count 2 2006.161.07:58:08.81#ibcon#read 5, iclass 10, count 2 2006.161.07:58:08.81#ibcon#about to read 6, iclass 10, count 2 2006.161.07:58:08.81#ibcon#read 6, iclass 10, count 2 2006.161.07:58:08.81#ibcon#end of sib2, iclass 10, count 2 2006.161.07:58:08.81#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:58:08.81#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:58:08.81#ibcon#[25=AT01-08\r\n] 2006.161.07:58:08.81#ibcon#*before write, iclass 10, count 2 2006.161.07:58:08.81#ibcon#enter sib2, iclass 10, count 2 2006.161.07:58:08.81#ibcon#flushed, iclass 10, count 2 2006.161.07:58:08.81#ibcon#about to write, iclass 10, count 2 2006.161.07:58:08.81#ibcon#wrote, iclass 10, count 2 2006.161.07:58:08.81#ibcon#about to read 3, iclass 10, count 2 2006.161.07:58:08.84#ibcon#read 3, iclass 10, count 2 2006.161.07:58:08.84#ibcon#about to read 4, iclass 10, count 2 2006.161.07:58:08.84#ibcon#read 4, iclass 10, count 2 2006.161.07:58:08.84#ibcon#about to read 5, iclass 10, count 2 2006.161.07:58:08.84#ibcon#read 5, iclass 10, count 2 2006.161.07:58:08.84#ibcon#about to read 6, iclass 10, count 2 2006.161.07:58:08.84#ibcon#read 6, iclass 10, count 2 2006.161.07:58:08.84#ibcon#end of sib2, iclass 10, count 2 2006.161.07:58:08.84#ibcon#*after write, iclass 10, count 2 2006.161.07:58:08.84#ibcon#*before return 0, iclass 10, count 2 2006.161.07:58:08.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:08.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:08.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:58:08.84#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:08.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:08.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:08.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:08.96#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:58:08.96#ibcon#first serial, iclass 10, count 0 2006.161.07:58:08.96#ibcon#enter sib2, iclass 10, count 0 2006.161.07:58:08.96#ibcon#flushed, iclass 10, count 0 2006.161.07:58:08.96#ibcon#about to write, iclass 10, count 0 2006.161.07:58:08.96#ibcon#wrote, iclass 10, count 0 2006.161.07:58:08.96#ibcon#about to read 3, iclass 10, count 0 2006.161.07:58:08.98#ibcon#read 3, iclass 10, count 0 2006.161.07:58:08.98#ibcon#about to read 4, iclass 10, count 0 2006.161.07:58:08.98#ibcon#read 4, iclass 10, count 0 2006.161.07:58:08.98#ibcon#about to read 5, iclass 10, count 0 2006.161.07:58:08.98#ibcon#read 5, iclass 10, count 0 2006.161.07:58:08.98#ibcon#about to read 6, iclass 10, count 0 2006.161.07:58:08.98#ibcon#read 6, iclass 10, count 0 2006.161.07:58:08.98#ibcon#end of sib2, iclass 10, count 0 2006.161.07:58:08.98#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:58:08.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:58:08.98#ibcon#[25=USB\r\n] 2006.161.07:58:08.98#ibcon#*before write, iclass 10, count 0 2006.161.07:58:08.98#ibcon#enter sib2, iclass 10, count 0 2006.161.07:58:08.98#ibcon#flushed, iclass 10, count 0 2006.161.07:58:08.98#ibcon#about to write, iclass 10, count 0 2006.161.07:58:08.98#ibcon#wrote, iclass 10, count 0 2006.161.07:58:08.98#ibcon#about to read 3, iclass 10, count 0 2006.161.07:58:09.01#ibcon#read 3, iclass 10, count 0 2006.161.07:58:09.01#ibcon#about to read 4, iclass 10, count 0 2006.161.07:58:09.01#ibcon#read 4, iclass 10, count 0 2006.161.07:58:09.01#ibcon#about to read 5, iclass 10, count 0 2006.161.07:58:09.01#ibcon#read 5, iclass 10, count 0 2006.161.07:58:09.01#ibcon#about to read 6, iclass 10, count 0 2006.161.07:58:09.01#ibcon#read 6, iclass 10, count 0 2006.161.07:58:09.01#ibcon#end of sib2, iclass 10, count 0 2006.161.07:58:09.01#ibcon#*after write, iclass 10, count 0 2006.161.07:58:09.01#ibcon#*before return 0, iclass 10, count 0 2006.161.07:58:09.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:09.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:09.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:58:09.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:58:09.01$vc4f8/valo=2,572.99 2006.161.07:58:09.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:58:09.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:58:09.01#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:09.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:09.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:09.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:09.01#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:58:09.01#ibcon#first serial, iclass 12, count 0 2006.161.07:58:09.01#ibcon#enter sib2, iclass 12, count 0 2006.161.07:58:09.01#ibcon#flushed, iclass 12, count 0 2006.161.07:58:09.01#ibcon#about to write, iclass 12, count 0 2006.161.07:58:09.01#ibcon#wrote, iclass 12, count 0 2006.161.07:58:09.01#ibcon#about to read 3, iclass 12, count 0 2006.161.07:58:09.03#ibcon#read 3, iclass 12, count 0 2006.161.07:58:09.03#ibcon#about to read 4, iclass 12, count 0 2006.161.07:58:09.03#ibcon#read 4, iclass 12, count 0 2006.161.07:58:09.03#ibcon#about to read 5, iclass 12, count 0 2006.161.07:58:09.03#ibcon#read 5, iclass 12, count 0 2006.161.07:58:09.03#ibcon#about to read 6, iclass 12, count 0 2006.161.07:58:09.03#ibcon#read 6, iclass 12, count 0 2006.161.07:58:09.03#ibcon#end of sib2, iclass 12, count 0 2006.161.07:58:09.03#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:58:09.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:58:09.03#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.07:58:09.03#ibcon#*before write, iclass 12, count 0 2006.161.07:58:09.03#ibcon#enter sib2, iclass 12, count 0 2006.161.07:58:09.03#ibcon#flushed, iclass 12, count 0 2006.161.07:58:09.03#ibcon#about to write, iclass 12, count 0 2006.161.07:58:09.03#ibcon#wrote, iclass 12, count 0 2006.161.07:58:09.03#ibcon#about to read 3, iclass 12, count 0 2006.161.07:58:09.07#ibcon#read 3, iclass 12, count 0 2006.161.07:58:09.07#ibcon#about to read 4, iclass 12, count 0 2006.161.07:58:09.07#ibcon#read 4, iclass 12, count 0 2006.161.07:58:09.07#ibcon#about to read 5, iclass 12, count 0 2006.161.07:58:09.07#ibcon#read 5, iclass 12, count 0 2006.161.07:58:09.07#ibcon#about to read 6, iclass 12, count 0 2006.161.07:58:09.07#ibcon#read 6, iclass 12, count 0 2006.161.07:58:09.07#ibcon#end of sib2, iclass 12, count 0 2006.161.07:58:09.07#ibcon#*after write, iclass 12, count 0 2006.161.07:58:09.07#ibcon#*before return 0, iclass 12, count 0 2006.161.07:58:09.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:09.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:09.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:58:09.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:58:09.07$vc4f8/va=2,7 2006.161.07:58:09.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:58:09.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:58:09.07#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:09.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:09.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:09.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:09.13#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:58:09.13#ibcon#first serial, iclass 14, count 2 2006.161.07:58:09.13#ibcon#enter sib2, iclass 14, count 2 2006.161.07:58:09.13#ibcon#flushed, iclass 14, count 2 2006.161.07:58:09.13#ibcon#about to write, iclass 14, count 2 2006.161.07:58:09.13#ibcon#wrote, iclass 14, count 2 2006.161.07:58:09.13#ibcon#about to read 3, iclass 14, count 2 2006.161.07:58:09.15#ibcon#read 3, iclass 14, count 2 2006.161.07:58:09.15#ibcon#about to read 4, iclass 14, count 2 2006.161.07:58:09.15#ibcon#read 4, iclass 14, count 2 2006.161.07:58:09.15#ibcon#about to read 5, iclass 14, count 2 2006.161.07:58:09.15#ibcon#read 5, iclass 14, count 2 2006.161.07:58:09.15#ibcon#about to read 6, iclass 14, count 2 2006.161.07:58:09.15#ibcon#read 6, iclass 14, count 2 2006.161.07:58:09.15#ibcon#end of sib2, iclass 14, count 2 2006.161.07:58:09.15#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:58:09.15#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:58:09.15#ibcon#[25=AT02-07\r\n] 2006.161.07:58:09.15#ibcon#*before write, iclass 14, count 2 2006.161.07:58:09.15#ibcon#enter sib2, iclass 14, count 2 2006.161.07:58:09.15#ibcon#flushed, iclass 14, count 2 2006.161.07:58:09.15#ibcon#about to write, iclass 14, count 2 2006.161.07:58:09.15#ibcon#wrote, iclass 14, count 2 2006.161.07:58:09.15#ibcon#about to read 3, iclass 14, count 2 2006.161.07:58:09.18#ibcon#read 3, iclass 14, count 2 2006.161.07:58:09.18#ibcon#about to read 4, iclass 14, count 2 2006.161.07:58:09.18#ibcon#read 4, iclass 14, count 2 2006.161.07:58:09.18#ibcon#about to read 5, iclass 14, count 2 2006.161.07:58:09.18#ibcon#read 5, iclass 14, count 2 2006.161.07:58:09.18#ibcon#about to read 6, iclass 14, count 2 2006.161.07:58:09.18#ibcon#read 6, iclass 14, count 2 2006.161.07:58:09.18#ibcon#end of sib2, iclass 14, count 2 2006.161.07:58:09.18#ibcon#*after write, iclass 14, count 2 2006.161.07:58:09.18#ibcon#*before return 0, iclass 14, count 2 2006.161.07:58:09.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:09.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:09.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:58:09.18#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:09.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:09.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:09.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:09.30#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:58:09.30#ibcon#first serial, iclass 14, count 0 2006.161.07:58:09.30#ibcon#enter sib2, iclass 14, count 0 2006.161.07:58:09.30#ibcon#flushed, iclass 14, count 0 2006.161.07:58:09.30#ibcon#about to write, iclass 14, count 0 2006.161.07:58:09.30#ibcon#wrote, iclass 14, count 0 2006.161.07:58:09.30#ibcon#about to read 3, iclass 14, count 0 2006.161.07:58:09.32#ibcon#read 3, iclass 14, count 0 2006.161.07:58:09.32#ibcon#about to read 4, iclass 14, count 0 2006.161.07:58:09.32#ibcon#read 4, iclass 14, count 0 2006.161.07:58:09.32#ibcon#about to read 5, iclass 14, count 0 2006.161.07:58:09.32#ibcon#read 5, iclass 14, count 0 2006.161.07:58:09.32#ibcon#about to read 6, iclass 14, count 0 2006.161.07:58:09.32#ibcon#read 6, iclass 14, count 0 2006.161.07:58:09.32#ibcon#end of sib2, iclass 14, count 0 2006.161.07:58:09.32#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:58:09.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:58:09.32#ibcon#[25=USB\r\n] 2006.161.07:58:09.32#ibcon#*before write, iclass 14, count 0 2006.161.07:58:09.32#ibcon#enter sib2, iclass 14, count 0 2006.161.07:58:09.32#ibcon#flushed, iclass 14, count 0 2006.161.07:58:09.32#ibcon#about to write, iclass 14, count 0 2006.161.07:58:09.32#ibcon#wrote, iclass 14, count 0 2006.161.07:58:09.32#ibcon#about to read 3, iclass 14, count 0 2006.161.07:58:09.35#ibcon#read 3, iclass 14, count 0 2006.161.07:58:09.35#ibcon#about to read 4, iclass 14, count 0 2006.161.07:58:09.35#ibcon#read 4, iclass 14, count 0 2006.161.07:58:09.35#ibcon#about to read 5, iclass 14, count 0 2006.161.07:58:09.35#ibcon#read 5, iclass 14, count 0 2006.161.07:58:09.35#ibcon#about to read 6, iclass 14, count 0 2006.161.07:58:09.35#ibcon#read 6, iclass 14, count 0 2006.161.07:58:09.35#ibcon#end of sib2, iclass 14, count 0 2006.161.07:58:09.35#ibcon#*after write, iclass 14, count 0 2006.161.07:58:09.35#ibcon#*before return 0, iclass 14, count 0 2006.161.07:58:09.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:09.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:09.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:58:09.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:58:09.35$vc4f8/valo=3,672.99 2006.161.07:58:09.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:58:09.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:58:09.35#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:09.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:09.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:09.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:09.35#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:58:09.35#ibcon#first serial, iclass 16, count 0 2006.161.07:58:09.35#ibcon#enter sib2, iclass 16, count 0 2006.161.07:58:09.35#ibcon#flushed, iclass 16, count 0 2006.161.07:58:09.35#ibcon#about to write, iclass 16, count 0 2006.161.07:58:09.35#ibcon#wrote, iclass 16, count 0 2006.161.07:58:09.35#ibcon#about to read 3, iclass 16, count 0 2006.161.07:58:09.37#ibcon#read 3, iclass 16, count 0 2006.161.07:58:09.37#ibcon#about to read 4, iclass 16, count 0 2006.161.07:58:09.37#ibcon#read 4, iclass 16, count 0 2006.161.07:58:09.37#ibcon#about to read 5, iclass 16, count 0 2006.161.07:58:09.37#ibcon#read 5, iclass 16, count 0 2006.161.07:58:09.37#ibcon#about to read 6, iclass 16, count 0 2006.161.07:58:09.37#ibcon#read 6, iclass 16, count 0 2006.161.07:58:09.37#ibcon#end of sib2, iclass 16, count 0 2006.161.07:58:09.37#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:58:09.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:58:09.37#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.07:58:09.37#ibcon#*before write, iclass 16, count 0 2006.161.07:58:09.37#ibcon#enter sib2, iclass 16, count 0 2006.161.07:58:09.37#ibcon#flushed, iclass 16, count 0 2006.161.07:58:09.37#ibcon#about to write, iclass 16, count 0 2006.161.07:58:09.37#ibcon#wrote, iclass 16, count 0 2006.161.07:58:09.37#ibcon#about to read 3, iclass 16, count 0 2006.161.07:58:09.41#ibcon#read 3, iclass 16, count 0 2006.161.07:58:09.41#ibcon#about to read 4, iclass 16, count 0 2006.161.07:58:09.41#ibcon#read 4, iclass 16, count 0 2006.161.07:58:09.41#ibcon#about to read 5, iclass 16, count 0 2006.161.07:58:09.41#ibcon#read 5, iclass 16, count 0 2006.161.07:58:09.41#ibcon#about to read 6, iclass 16, count 0 2006.161.07:58:09.41#ibcon#read 6, iclass 16, count 0 2006.161.07:58:09.41#ibcon#end of sib2, iclass 16, count 0 2006.161.07:58:09.41#ibcon#*after write, iclass 16, count 0 2006.161.07:58:09.41#ibcon#*before return 0, iclass 16, count 0 2006.161.07:58:09.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:09.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:09.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:58:09.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:58:09.41$vc4f8/va=3,6 2006.161.07:58:09.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:58:09.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:58:09.41#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:09.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:09.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:09.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:09.47#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:58:09.47#ibcon#first serial, iclass 18, count 2 2006.161.07:58:09.47#ibcon#enter sib2, iclass 18, count 2 2006.161.07:58:09.47#ibcon#flushed, iclass 18, count 2 2006.161.07:58:09.47#ibcon#about to write, iclass 18, count 2 2006.161.07:58:09.47#ibcon#wrote, iclass 18, count 2 2006.161.07:58:09.47#ibcon#about to read 3, iclass 18, count 2 2006.161.07:58:09.49#ibcon#read 3, iclass 18, count 2 2006.161.07:58:09.49#ibcon#about to read 4, iclass 18, count 2 2006.161.07:58:09.49#ibcon#read 4, iclass 18, count 2 2006.161.07:58:09.49#ibcon#about to read 5, iclass 18, count 2 2006.161.07:58:09.49#ibcon#read 5, iclass 18, count 2 2006.161.07:58:09.49#ibcon#about to read 6, iclass 18, count 2 2006.161.07:58:09.49#ibcon#read 6, iclass 18, count 2 2006.161.07:58:09.49#ibcon#end of sib2, iclass 18, count 2 2006.161.07:58:09.49#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:58:09.49#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:58:09.49#ibcon#[25=AT03-06\r\n] 2006.161.07:58:09.49#ibcon#*before write, iclass 18, count 2 2006.161.07:58:09.49#ibcon#enter sib2, iclass 18, count 2 2006.161.07:58:09.49#ibcon#flushed, iclass 18, count 2 2006.161.07:58:09.49#ibcon#about to write, iclass 18, count 2 2006.161.07:58:09.49#ibcon#wrote, iclass 18, count 2 2006.161.07:58:09.49#ibcon#about to read 3, iclass 18, count 2 2006.161.07:58:09.52#ibcon#read 3, iclass 18, count 2 2006.161.07:58:09.52#ibcon#about to read 4, iclass 18, count 2 2006.161.07:58:09.52#ibcon#read 4, iclass 18, count 2 2006.161.07:58:09.52#ibcon#about to read 5, iclass 18, count 2 2006.161.07:58:09.52#ibcon#read 5, iclass 18, count 2 2006.161.07:58:09.52#ibcon#about to read 6, iclass 18, count 2 2006.161.07:58:09.52#ibcon#read 6, iclass 18, count 2 2006.161.07:58:09.52#ibcon#end of sib2, iclass 18, count 2 2006.161.07:58:09.52#ibcon#*after write, iclass 18, count 2 2006.161.07:58:09.52#ibcon#*before return 0, iclass 18, count 2 2006.161.07:58:09.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:09.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:09.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:58:09.52#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:09.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:09.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:09.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:09.64#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:58:09.64#ibcon#first serial, iclass 18, count 0 2006.161.07:58:09.64#ibcon#enter sib2, iclass 18, count 0 2006.161.07:58:09.64#ibcon#flushed, iclass 18, count 0 2006.161.07:58:09.64#ibcon#about to write, iclass 18, count 0 2006.161.07:58:09.64#ibcon#wrote, iclass 18, count 0 2006.161.07:58:09.64#ibcon#about to read 3, iclass 18, count 0 2006.161.07:58:09.66#ibcon#read 3, iclass 18, count 0 2006.161.07:58:09.66#ibcon#about to read 4, iclass 18, count 0 2006.161.07:58:09.66#ibcon#read 4, iclass 18, count 0 2006.161.07:58:09.66#ibcon#about to read 5, iclass 18, count 0 2006.161.07:58:09.66#ibcon#read 5, iclass 18, count 0 2006.161.07:58:09.66#ibcon#about to read 6, iclass 18, count 0 2006.161.07:58:09.66#ibcon#read 6, iclass 18, count 0 2006.161.07:58:09.66#ibcon#end of sib2, iclass 18, count 0 2006.161.07:58:09.66#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:58:09.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:58:09.66#ibcon#[25=USB\r\n] 2006.161.07:58:09.66#ibcon#*before write, iclass 18, count 0 2006.161.07:58:09.66#ibcon#enter sib2, iclass 18, count 0 2006.161.07:58:09.66#ibcon#flushed, iclass 18, count 0 2006.161.07:58:09.66#ibcon#about to write, iclass 18, count 0 2006.161.07:58:09.66#ibcon#wrote, iclass 18, count 0 2006.161.07:58:09.66#ibcon#about to read 3, iclass 18, count 0 2006.161.07:58:09.69#ibcon#read 3, iclass 18, count 0 2006.161.07:58:09.69#ibcon#about to read 4, iclass 18, count 0 2006.161.07:58:09.69#ibcon#read 4, iclass 18, count 0 2006.161.07:58:09.69#ibcon#about to read 5, iclass 18, count 0 2006.161.07:58:09.69#ibcon#read 5, iclass 18, count 0 2006.161.07:58:09.69#ibcon#about to read 6, iclass 18, count 0 2006.161.07:58:09.69#ibcon#read 6, iclass 18, count 0 2006.161.07:58:09.69#ibcon#end of sib2, iclass 18, count 0 2006.161.07:58:09.69#ibcon#*after write, iclass 18, count 0 2006.161.07:58:09.69#ibcon#*before return 0, iclass 18, count 0 2006.161.07:58:09.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:09.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:09.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:58:09.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:58:09.69$vc4f8/valo=4,832.99 2006.161.07:58:09.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:58:09.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:58:09.69#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:09.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:09.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:09.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:09.69#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:58:09.69#ibcon#first serial, iclass 20, count 0 2006.161.07:58:09.69#ibcon#enter sib2, iclass 20, count 0 2006.161.07:58:09.69#ibcon#flushed, iclass 20, count 0 2006.161.07:58:09.69#ibcon#about to write, iclass 20, count 0 2006.161.07:58:09.69#ibcon#wrote, iclass 20, count 0 2006.161.07:58:09.69#ibcon#about to read 3, iclass 20, count 0 2006.161.07:58:09.71#ibcon#read 3, iclass 20, count 0 2006.161.07:58:09.71#ibcon#about to read 4, iclass 20, count 0 2006.161.07:58:09.71#ibcon#read 4, iclass 20, count 0 2006.161.07:58:09.71#ibcon#about to read 5, iclass 20, count 0 2006.161.07:58:09.71#ibcon#read 5, iclass 20, count 0 2006.161.07:58:09.71#ibcon#about to read 6, iclass 20, count 0 2006.161.07:58:09.71#ibcon#read 6, iclass 20, count 0 2006.161.07:58:09.71#ibcon#end of sib2, iclass 20, count 0 2006.161.07:58:09.71#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:58:09.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:58:09.71#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.07:58:09.71#ibcon#*before write, iclass 20, count 0 2006.161.07:58:09.71#ibcon#enter sib2, iclass 20, count 0 2006.161.07:58:09.71#ibcon#flushed, iclass 20, count 0 2006.161.07:58:09.71#ibcon#about to write, iclass 20, count 0 2006.161.07:58:09.71#ibcon#wrote, iclass 20, count 0 2006.161.07:58:09.71#ibcon#about to read 3, iclass 20, count 0 2006.161.07:58:09.75#ibcon#read 3, iclass 20, count 0 2006.161.07:58:09.75#ibcon#about to read 4, iclass 20, count 0 2006.161.07:58:09.75#ibcon#read 4, iclass 20, count 0 2006.161.07:58:09.75#ibcon#about to read 5, iclass 20, count 0 2006.161.07:58:09.75#ibcon#read 5, iclass 20, count 0 2006.161.07:58:09.75#ibcon#about to read 6, iclass 20, count 0 2006.161.07:58:09.75#ibcon#read 6, iclass 20, count 0 2006.161.07:58:09.75#ibcon#end of sib2, iclass 20, count 0 2006.161.07:58:09.75#ibcon#*after write, iclass 20, count 0 2006.161.07:58:09.75#ibcon#*before return 0, iclass 20, count 0 2006.161.07:58:09.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:09.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:09.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:58:09.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:58:09.75$vc4f8/va=4,7 2006.161.07:58:09.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:58:09.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:58:09.75#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:09.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:09.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:09.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:09.81#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:58:09.81#ibcon#first serial, iclass 22, count 2 2006.161.07:58:09.81#ibcon#enter sib2, iclass 22, count 2 2006.161.07:58:09.81#ibcon#flushed, iclass 22, count 2 2006.161.07:58:09.81#ibcon#about to write, iclass 22, count 2 2006.161.07:58:09.81#ibcon#wrote, iclass 22, count 2 2006.161.07:58:09.81#ibcon#about to read 3, iclass 22, count 2 2006.161.07:58:09.83#ibcon#read 3, iclass 22, count 2 2006.161.07:58:09.83#ibcon#about to read 4, iclass 22, count 2 2006.161.07:58:09.83#ibcon#read 4, iclass 22, count 2 2006.161.07:58:09.83#ibcon#about to read 5, iclass 22, count 2 2006.161.07:58:09.83#ibcon#read 5, iclass 22, count 2 2006.161.07:58:09.83#ibcon#about to read 6, iclass 22, count 2 2006.161.07:58:09.83#ibcon#read 6, iclass 22, count 2 2006.161.07:58:09.83#ibcon#end of sib2, iclass 22, count 2 2006.161.07:58:09.83#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:58:09.83#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:58:09.83#ibcon#[25=AT04-07\r\n] 2006.161.07:58:09.83#ibcon#*before write, iclass 22, count 2 2006.161.07:58:09.83#ibcon#enter sib2, iclass 22, count 2 2006.161.07:58:09.83#ibcon#flushed, iclass 22, count 2 2006.161.07:58:09.83#ibcon#about to write, iclass 22, count 2 2006.161.07:58:09.83#ibcon#wrote, iclass 22, count 2 2006.161.07:58:09.83#ibcon#about to read 3, iclass 22, count 2 2006.161.07:58:09.86#ibcon#read 3, iclass 22, count 2 2006.161.07:58:09.86#ibcon#about to read 4, iclass 22, count 2 2006.161.07:58:09.86#ibcon#read 4, iclass 22, count 2 2006.161.07:58:09.86#ibcon#about to read 5, iclass 22, count 2 2006.161.07:58:09.86#ibcon#read 5, iclass 22, count 2 2006.161.07:58:09.86#ibcon#about to read 6, iclass 22, count 2 2006.161.07:58:09.86#ibcon#read 6, iclass 22, count 2 2006.161.07:58:09.86#ibcon#end of sib2, iclass 22, count 2 2006.161.07:58:09.86#ibcon#*after write, iclass 22, count 2 2006.161.07:58:09.86#ibcon#*before return 0, iclass 22, count 2 2006.161.07:58:09.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:09.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:09.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:58:09.86#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:09.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:09.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:09.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:09.98#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:58:09.98#ibcon#first serial, iclass 22, count 0 2006.161.07:58:09.98#ibcon#enter sib2, iclass 22, count 0 2006.161.07:58:09.98#ibcon#flushed, iclass 22, count 0 2006.161.07:58:09.98#ibcon#about to write, iclass 22, count 0 2006.161.07:58:09.98#ibcon#wrote, iclass 22, count 0 2006.161.07:58:09.98#ibcon#about to read 3, iclass 22, count 0 2006.161.07:58:10.00#ibcon#read 3, iclass 22, count 0 2006.161.07:58:10.00#ibcon#about to read 4, iclass 22, count 0 2006.161.07:58:10.00#ibcon#read 4, iclass 22, count 0 2006.161.07:58:10.00#ibcon#about to read 5, iclass 22, count 0 2006.161.07:58:10.00#ibcon#read 5, iclass 22, count 0 2006.161.07:58:10.00#ibcon#about to read 6, iclass 22, count 0 2006.161.07:58:10.00#ibcon#read 6, iclass 22, count 0 2006.161.07:58:10.00#ibcon#end of sib2, iclass 22, count 0 2006.161.07:58:10.00#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:58:10.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:58:10.00#ibcon#[25=USB\r\n] 2006.161.07:58:10.00#ibcon#*before write, iclass 22, count 0 2006.161.07:58:10.00#ibcon#enter sib2, iclass 22, count 0 2006.161.07:58:10.00#ibcon#flushed, iclass 22, count 0 2006.161.07:58:10.00#ibcon#about to write, iclass 22, count 0 2006.161.07:58:10.00#ibcon#wrote, iclass 22, count 0 2006.161.07:58:10.00#ibcon#about to read 3, iclass 22, count 0 2006.161.07:58:10.03#ibcon#read 3, iclass 22, count 0 2006.161.07:58:10.03#ibcon#about to read 4, iclass 22, count 0 2006.161.07:58:10.03#ibcon#read 4, iclass 22, count 0 2006.161.07:58:10.03#ibcon#about to read 5, iclass 22, count 0 2006.161.07:58:10.03#ibcon#read 5, iclass 22, count 0 2006.161.07:58:10.03#ibcon#about to read 6, iclass 22, count 0 2006.161.07:58:10.03#ibcon#read 6, iclass 22, count 0 2006.161.07:58:10.03#ibcon#end of sib2, iclass 22, count 0 2006.161.07:58:10.03#ibcon#*after write, iclass 22, count 0 2006.161.07:58:10.03#ibcon#*before return 0, iclass 22, count 0 2006.161.07:58:10.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:10.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:10.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:58:10.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:58:10.03$vc4f8/valo=5,652.99 2006.161.07:58:10.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:58:10.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:58:10.03#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:10.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:10.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:10.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:10.03#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:58:10.03#ibcon#first serial, iclass 24, count 0 2006.161.07:58:10.03#ibcon#enter sib2, iclass 24, count 0 2006.161.07:58:10.03#ibcon#flushed, iclass 24, count 0 2006.161.07:58:10.03#ibcon#about to write, iclass 24, count 0 2006.161.07:58:10.03#ibcon#wrote, iclass 24, count 0 2006.161.07:58:10.03#ibcon#about to read 3, iclass 24, count 0 2006.161.07:58:10.05#ibcon#read 3, iclass 24, count 0 2006.161.07:58:10.05#ibcon#about to read 4, iclass 24, count 0 2006.161.07:58:10.05#ibcon#read 4, iclass 24, count 0 2006.161.07:58:10.05#ibcon#about to read 5, iclass 24, count 0 2006.161.07:58:10.05#ibcon#read 5, iclass 24, count 0 2006.161.07:58:10.05#ibcon#about to read 6, iclass 24, count 0 2006.161.07:58:10.05#ibcon#read 6, iclass 24, count 0 2006.161.07:58:10.05#ibcon#end of sib2, iclass 24, count 0 2006.161.07:58:10.05#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:58:10.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:58:10.05#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.07:58:10.05#ibcon#*before write, iclass 24, count 0 2006.161.07:58:10.05#ibcon#enter sib2, iclass 24, count 0 2006.161.07:58:10.05#ibcon#flushed, iclass 24, count 0 2006.161.07:58:10.05#ibcon#about to write, iclass 24, count 0 2006.161.07:58:10.05#ibcon#wrote, iclass 24, count 0 2006.161.07:58:10.05#ibcon#about to read 3, iclass 24, count 0 2006.161.07:58:10.09#ibcon#read 3, iclass 24, count 0 2006.161.07:58:10.09#ibcon#about to read 4, iclass 24, count 0 2006.161.07:58:10.09#ibcon#read 4, iclass 24, count 0 2006.161.07:58:10.09#ibcon#about to read 5, iclass 24, count 0 2006.161.07:58:10.09#ibcon#read 5, iclass 24, count 0 2006.161.07:58:10.09#ibcon#about to read 6, iclass 24, count 0 2006.161.07:58:10.09#ibcon#read 6, iclass 24, count 0 2006.161.07:58:10.09#ibcon#end of sib2, iclass 24, count 0 2006.161.07:58:10.09#ibcon#*after write, iclass 24, count 0 2006.161.07:58:10.09#ibcon#*before return 0, iclass 24, count 0 2006.161.07:58:10.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:10.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:10.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:58:10.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:58:10.09$vc4f8/va=5,7 2006.161.07:58:10.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:58:10.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:58:10.09#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:10.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:10.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:10.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:10.15#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:58:10.15#ibcon#first serial, iclass 26, count 2 2006.161.07:58:10.15#ibcon#enter sib2, iclass 26, count 2 2006.161.07:58:10.15#ibcon#flushed, iclass 26, count 2 2006.161.07:58:10.15#ibcon#about to write, iclass 26, count 2 2006.161.07:58:10.15#ibcon#wrote, iclass 26, count 2 2006.161.07:58:10.15#ibcon#about to read 3, iclass 26, count 2 2006.161.07:58:10.17#ibcon#read 3, iclass 26, count 2 2006.161.07:58:10.17#ibcon#about to read 4, iclass 26, count 2 2006.161.07:58:10.17#ibcon#read 4, iclass 26, count 2 2006.161.07:58:10.17#ibcon#about to read 5, iclass 26, count 2 2006.161.07:58:10.17#ibcon#read 5, iclass 26, count 2 2006.161.07:58:10.17#ibcon#about to read 6, iclass 26, count 2 2006.161.07:58:10.17#ibcon#read 6, iclass 26, count 2 2006.161.07:58:10.17#ibcon#end of sib2, iclass 26, count 2 2006.161.07:58:10.17#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:58:10.17#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:58:10.17#ibcon#[25=AT05-07\r\n] 2006.161.07:58:10.17#ibcon#*before write, iclass 26, count 2 2006.161.07:58:10.17#ibcon#enter sib2, iclass 26, count 2 2006.161.07:58:10.17#ibcon#flushed, iclass 26, count 2 2006.161.07:58:10.17#ibcon#about to write, iclass 26, count 2 2006.161.07:58:10.17#ibcon#wrote, iclass 26, count 2 2006.161.07:58:10.17#ibcon#about to read 3, iclass 26, count 2 2006.161.07:58:10.20#ibcon#read 3, iclass 26, count 2 2006.161.07:58:10.20#ibcon#about to read 4, iclass 26, count 2 2006.161.07:58:10.20#ibcon#read 4, iclass 26, count 2 2006.161.07:58:10.20#ibcon#about to read 5, iclass 26, count 2 2006.161.07:58:10.20#ibcon#read 5, iclass 26, count 2 2006.161.07:58:10.20#ibcon#about to read 6, iclass 26, count 2 2006.161.07:58:10.20#ibcon#read 6, iclass 26, count 2 2006.161.07:58:10.20#ibcon#end of sib2, iclass 26, count 2 2006.161.07:58:10.20#ibcon#*after write, iclass 26, count 2 2006.161.07:58:10.20#ibcon#*before return 0, iclass 26, count 2 2006.161.07:58:10.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:10.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:10.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:58:10.20#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:10.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:10.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:10.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:10.32#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:58:10.32#ibcon#first serial, iclass 26, count 0 2006.161.07:58:10.32#ibcon#enter sib2, iclass 26, count 0 2006.161.07:58:10.32#ibcon#flushed, iclass 26, count 0 2006.161.07:58:10.32#ibcon#about to write, iclass 26, count 0 2006.161.07:58:10.32#ibcon#wrote, iclass 26, count 0 2006.161.07:58:10.32#ibcon#about to read 3, iclass 26, count 0 2006.161.07:58:10.34#ibcon#read 3, iclass 26, count 0 2006.161.07:58:10.34#ibcon#about to read 4, iclass 26, count 0 2006.161.07:58:10.34#ibcon#read 4, iclass 26, count 0 2006.161.07:58:10.34#ibcon#about to read 5, iclass 26, count 0 2006.161.07:58:10.34#ibcon#read 5, iclass 26, count 0 2006.161.07:58:10.34#ibcon#about to read 6, iclass 26, count 0 2006.161.07:58:10.34#ibcon#read 6, iclass 26, count 0 2006.161.07:58:10.34#ibcon#end of sib2, iclass 26, count 0 2006.161.07:58:10.34#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:58:10.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:58:10.34#ibcon#[25=USB\r\n] 2006.161.07:58:10.34#ibcon#*before write, iclass 26, count 0 2006.161.07:58:10.34#ibcon#enter sib2, iclass 26, count 0 2006.161.07:58:10.34#ibcon#flushed, iclass 26, count 0 2006.161.07:58:10.34#ibcon#about to write, iclass 26, count 0 2006.161.07:58:10.34#ibcon#wrote, iclass 26, count 0 2006.161.07:58:10.34#ibcon#about to read 3, iclass 26, count 0 2006.161.07:58:10.37#ibcon#read 3, iclass 26, count 0 2006.161.07:58:10.37#ibcon#about to read 4, iclass 26, count 0 2006.161.07:58:10.37#ibcon#read 4, iclass 26, count 0 2006.161.07:58:10.37#ibcon#about to read 5, iclass 26, count 0 2006.161.07:58:10.37#ibcon#read 5, iclass 26, count 0 2006.161.07:58:10.37#ibcon#about to read 6, iclass 26, count 0 2006.161.07:58:10.37#ibcon#read 6, iclass 26, count 0 2006.161.07:58:10.37#ibcon#end of sib2, iclass 26, count 0 2006.161.07:58:10.37#ibcon#*after write, iclass 26, count 0 2006.161.07:58:10.37#ibcon#*before return 0, iclass 26, count 0 2006.161.07:58:10.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:10.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:10.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:58:10.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:58:10.37$vc4f8/valo=6,772.99 2006.161.07:58:10.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:58:10.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:58:10.37#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:10.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:10.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:10.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:10.37#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:58:10.37#ibcon#first serial, iclass 28, count 0 2006.161.07:58:10.37#ibcon#enter sib2, iclass 28, count 0 2006.161.07:58:10.37#ibcon#flushed, iclass 28, count 0 2006.161.07:58:10.37#ibcon#about to write, iclass 28, count 0 2006.161.07:58:10.37#ibcon#wrote, iclass 28, count 0 2006.161.07:58:10.37#ibcon#about to read 3, iclass 28, count 0 2006.161.07:58:10.39#ibcon#read 3, iclass 28, count 0 2006.161.07:58:10.39#ibcon#about to read 4, iclass 28, count 0 2006.161.07:58:10.39#ibcon#read 4, iclass 28, count 0 2006.161.07:58:10.39#ibcon#about to read 5, iclass 28, count 0 2006.161.07:58:10.39#ibcon#read 5, iclass 28, count 0 2006.161.07:58:10.39#ibcon#about to read 6, iclass 28, count 0 2006.161.07:58:10.39#ibcon#read 6, iclass 28, count 0 2006.161.07:58:10.39#ibcon#end of sib2, iclass 28, count 0 2006.161.07:58:10.39#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:58:10.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:58:10.39#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.07:58:10.39#ibcon#*before write, iclass 28, count 0 2006.161.07:58:10.39#ibcon#enter sib2, iclass 28, count 0 2006.161.07:58:10.39#ibcon#flushed, iclass 28, count 0 2006.161.07:58:10.39#ibcon#about to write, iclass 28, count 0 2006.161.07:58:10.39#ibcon#wrote, iclass 28, count 0 2006.161.07:58:10.39#ibcon#about to read 3, iclass 28, count 0 2006.161.07:58:10.43#ibcon#read 3, iclass 28, count 0 2006.161.07:58:10.43#ibcon#about to read 4, iclass 28, count 0 2006.161.07:58:10.43#ibcon#read 4, iclass 28, count 0 2006.161.07:58:10.43#ibcon#about to read 5, iclass 28, count 0 2006.161.07:58:10.43#ibcon#read 5, iclass 28, count 0 2006.161.07:58:10.43#ibcon#about to read 6, iclass 28, count 0 2006.161.07:58:10.43#ibcon#read 6, iclass 28, count 0 2006.161.07:58:10.43#ibcon#end of sib2, iclass 28, count 0 2006.161.07:58:10.43#ibcon#*after write, iclass 28, count 0 2006.161.07:58:10.43#ibcon#*before return 0, iclass 28, count 0 2006.161.07:58:10.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:10.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:10.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:58:10.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:58:10.43$vc4f8/va=6,6 2006.161.07:58:10.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.07:58:10.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.07:58:10.43#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:10.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:10.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:10.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:10.49#ibcon#enter wrdev, iclass 30, count 2 2006.161.07:58:10.49#ibcon#first serial, iclass 30, count 2 2006.161.07:58:10.49#ibcon#enter sib2, iclass 30, count 2 2006.161.07:58:10.49#ibcon#flushed, iclass 30, count 2 2006.161.07:58:10.49#ibcon#about to write, iclass 30, count 2 2006.161.07:58:10.49#ibcon#wrote, iclass 30, count 2 2006.161.07:58:10.49#ibcon#about to read 3, iclass 30, count 2 2006.161.07:58:10.51#ibcon#read 3, iclass 30, count 2 2006.161.07:58:10.51#ibcon#about to read 4, iclass 30, count 2 2006.161.07:58:10.51#ibcon#read 4, iclass 30, count 2 2006.161.07:58:10.51#ibcon#about to read 5, iclass 30, count 2 2006.161.07:58:10.51#ibcon#read 5, iclass 30, count 2 2006.161.07:58:10.51#ibcon#about to read 6, iclass 30, count 2 2006.161.07:58:10.51#ibcon#read 6, iclass 30, count 2 2006.161.07:58:10.51#ibcon#end of sib2, iclass 30, count 2 2006.161.07:58:10.51#ibcon#*mode == 0, iclass 30, count 2 2006.161.07:58:10.51#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.07:58:10.51#ibcon#[25=AT06-06\r\n] 2006.161.07:58:10.51#ibcon#*before write, iclass 30, count 2 2006.161.07:58:10.51#ibcon#enter sib2, iclass 30, count 2 2006.161.07:58:10.51#ibcon#flushed, iclass 30, count 2 2006.161.07:58:10.51#ibcon#about to write, iclass 30, count 2 2006.161.07:58:10.51#ibcon#wrote, iclass 30, count 2 2006.161.07:58:10.51#ibcon#about to read 3, iclass 30, count 2 2006.161.07:58:10.54#ibcon#read 3, iclass 30, count 2 2006.161.07:58:10.54#ibcon#about to read 4, iclass 30, count 2 2006.161.07:58:10.54#ibcon#read 4, iclass 30, count 2 2006.161.07:58:10.54#ibcon#about to read 5, iclass 30, count 2 2006.161.07:58:10.54#ibcon#read 5, iclass 30, count 2 2006.161.07:58:10.54#ibcon#about to read 6, iclass 30, count 2 2006.161.07:58:10.54#ibcon#read 6, iclass 30, count 2 2006.161.07:58:10.54#ibcon#end of sib2, iclass 30, count 2 2006.161.07:58:10.54#ibcon#*after write, iclass 30, count 2 2006.161.07:58:10.54#ibcon#*before return 0, iclass 30, count 2 2006.161.07:58:10.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:10.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:10.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.07:58:10.54#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:10.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:58:10.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:58:10.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:58:10.66#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:58:10.66#ibcon#first serial, iclass 30, count 0 2006.161.07:58:10.66#ibcon#enter sib2, iclass 30, count 0 2006.161.07:58:10.66#ibcon#flushed, iclass 30, count 0 2006.161.07:58:10.66#ibcon#about to write, iclass 30, count 0 2006.161.07:58:10.66#ibcon#wrote, iclass 30, count 0 2006.161.07:58:10.66#ibcon#about to read 3, iclass 30, count 0 2006.161.07:58:10.68#ibcon#read 3, iclass 30, count 0 2006.161.07:58:10.68#ibcon#about to read 4, iclass 30, count 0 2006.161.07:58:10.68#ibcon#read 4, iclass 30, count 0 2006.161.07:58:10.68#ibcon#about to read 5, iclass 30, count 0 2006.161.07:58:10.68#ibcon#read 5, iclass 30, count 0 2006.161.07:58:10.68#ibcon#about to read 6, iclass 30, count 0 2006.161.07:58:10.68#ibcon#read 6, iclass 30, count 0 2006.161.07:58:10.68#ibcon#end of sib2, iclass 30, count 0 2006.161.07:58:10.68#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:58:10.68#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:58:10.68#ibcon#[25=USB\r\n] 2006.161.07:58:10.68#ibcon#*before write, iclass 30, count 0 2006.161.07:58:10.68#ibcon#enter sib2, iclass 30, count 0 2006.161.07:58:10.68#ibcon#flushed, iclass 30, count 0 2006.161.07:58:10.68#ibcon#about to write, iclass 30, count 0 2006.161.07:58:10.68#ibcon#wrote, iclass 30, count 0 2006.161.07:58:10.68#ibcon#about to read 3, iclass 30, count 0 2006.161.07:58:10.71#ibcon#read 3, iclass 30, count 0 2006.161.07:58:10.71#ibcon#about to read 4, iclass 30, count 0 2006.161.07:58:10.71#ibcon#read 4, iclass 30, count 0 2006.161.07:58:10.71#ibcon#about to read 5, iclass 30, count 0 2006.161.07:58:10.71#ibcon#read 5, iclass 30, count 0 2006.161.07:58:10.71#ibcon#about to read 6, iclass 30, count 0 2006.161.07:58:10.71#ibcon#read 6, iclass 30, count 0 2006.161.07:58:10.71#ibcon#end of sib2, iclass 30, count 0 2006.161.07:58:10.71#ibcon#*after write, iclass 30, count 0 2006.161.07:58:10.71#ibcon#*before return 0, iclass 30, count 0 2006.161.07:58:10.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:58:10.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.07:58:10.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:58:10.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:58:10.71$vc4f8/valo=7,832.99 2006.161.07:58:10.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.07:58:10.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.07:58:10.71#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:10.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:58:10.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:58:10.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:58:10.71#ibcon#enter wrdev, iclass 32, count 0 2006.161.07:58:10.71#ibcon#first serial, iclass 32, count 0 2006.161.07:58:10.71#ibcon#enter sib2, iclass 32, count 0 2006.161.07:58:10.71#ibcon#flushed, iclass 32, count 0 2006.161.07:58:10.71#ibcon#about to write, iclass 32, count 0 2006.161.07:58:10.71#ibcon#wrote, iclass 32, count 0 2006.161.07:58:10.71#ibcon#about to read 3, iclass 32, count 0 2006.161.07:58:10.73#ibcon#read 3, iclass 32, count 0 2006.161.07:58:10.73#ibcon#about to read 4, iclass 32, count 0 2006.161.07:58:10.73#ibcon#read 4, iclass 32, count 0 2006.161.07:58:10.73#ibcon#about to read 5, iclass 32, count 0 2006.161.07:58:10.73#ibcon#read 5, iclass 32, count 0 2006.161.07:58:10.73#ibcon#about to read 6, iclass 32, count 0 2006.161.07:58:10.73#ibcon#read 6, iclass 32, count 0 2006.161.07:58:10.73#ibcon#end of sib2, iclass 32, count 0 2006.161.07:58:10.73#ibcon#*mode == 0, iclass 32, count 0 2006.161.07:58:10.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.07:58:10.73#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.07:58:10.73#ibcon#*before write, iclass 32, count 0 2006.161.07:58:10.73#ibcon#enter sib2, iclass 32, count 0 2006.161.07:58:10.73#ibcon#flushed, iclass 32, count 0 2006.161.07:58:10.73#ibcon#about to write, iclass 32, count 0 2006.161.07:58:10.73#ibcon#wrote, iclass 32, count 0 2006.161.07:58:10.73#ibcon#about to read 3, iclass 32, count 0 2006.161.07:58:10.77#ibcon#read 3, iclass 32, count 0 2006.161.07:58:10.77#ibcon#about to read 4, iclass 32, count 0 2006.161.07:58:10.77#ibcon#read 4, iclass 32, count 0 2006.161.07:58:10.77#ibcon#about to read 5, iclass 32, count 0 2006.161.07:58:10.77#ibcon#read 5, iclass 32, count 0 2006.161.07:58:10.77#ibcon#about to read 6, iclass 32, count 0 2006.161.07:58:10.77#ibcon#read 6, iclass 32, count 0 2006.161.07:58:10.77#ibcon#end of sib2, iclass 32, count 0 2006.161.07:58:10.77#ibcon#*after write, iclass 32, count 0 2006.161.07:58:10.77#ibcon#*before return 0, iclass 32, count 0 2006.161.07:58:10.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:58:10.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.07:58:10.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.07:58:10.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.07:58:10.77$vc4f8/va=7,6 2006.161.07:58:10.77#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.07:58:10.77#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.07:58:10.77#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:10.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:58:10.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:58:10.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:58:10.83#ibcon#enter wrdev, iclass 34, count 2 2006.161.07:58:10.83#ibcon#first serial, iclass 34, count 2 2006.161.07:58:10.83#ibcon#enter sib2, iclass 34, count 2 2006.161.07:58:10.83#ibcon#flushed, iclass 34, count 2 2006.161.07:58:10.83#ibcon#about to write, iclass 34, count 2 2006.161.07:58:10.83#ibcon#wrote, iclass 34, count 2 2006.161.07:58:10.83#ibcon#about to read 3, iclass 34, count 2 2006.161.07:58:10.85#ibcon#read 3, iclass 34, count 2 2006.161.07:58:10.85#ibcon#about to read 4, iclass 34, count 2 2006.161.07:58:10.85#ibcon#read 4, iclass 34, count 2 2006.161.07:58:10.85#ibcon#about to read 5, iclass 34, count 2 2006.161.07:58:10.85#ibcon#read 5, iclass 34, count 2 2006.161.07:58:10.85#ibcon#about to read 6, iclass 34, count 2 2006.161.07:58:10.85#ibcon#read 6, iclass 34, count 2 2006.161.07:58:10.85#ibcon#end of sib2, iclass 34, count 2 2006.161.07:58:10.85#ibcon#*mode == 0, iclass 34, count 2 2006.161.07:58:10.85#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.07:58:10.85#ibcon#[25=AT07-06\r\n] 2006.161.07:58:10.85#ibcon#*before write, iclass 34, count 2 2006.161.07:58:10.85#ibcon#enter sib2, iclass 34, count 2 2006.161.07:58:10.85#ibcon#flushed, iclass 34, count 2 2006.161.07:58:10.85#ibcon#about to write, iclass 34, count 2 2006.161.07:58:10.85#ibcon#wrote, iclass 34, count 2 2006.161.07:58:10.85#ibcon#about to read 3, iclass 34, count 2 2006.161.07:58:10.88#ibcon#read 3, iclass 34, count 2 2006.161.07:58:10.88#ibcon#about to read 4, iclass 34, count 2 2006.161.07:58:10.88#ibcon#read 4, iclass 34, count 2 2006.161.07:58:10.88#ibcon#about to read 5, iclass 34, count 2 2006.161.07:58:10.88#ibcon#read 5, iclass 34, count 2 2006.161.07:58:10.88#ibcon#about to read 6, iclass 34, count 2 2006.161.07:58:10.88#ibcon#read 6, iclass 34, count 2 2006.161.07:58:10.88#ibcon#end of sib2, iclass 34, count 2 2006.161.07:58:10.88#ibcon#*after write, iclass 34, count 2 2006.161.07:58:10.88#ibcon#*before return 0, iclass 34, count 2 2006.161.07:58:10.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:58:10.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.07:58:10.88#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.07:58:10.88#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:10.88#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:58:11.00#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:58:11.00#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:58:11.00#ibcon#enter wrdev, iclass 34, count 0 2006.161.07:58:11.00#ibcon#first serial, iclass 34, count 0 2006.161.07:58:11.00#ibcon#enter sib2, iclass 34, count 0 2006.161.07:58:11.00#ibcon#flushed, iclass 34, count 0 2006.161.07:58:11.00#ibcon#about to write, iclass 34, count 0 2006.161.07:58:11.00#ibcon#wrote, iclass 34, count 0 2006.161.07:58:11.00#ibcon#about to read 3, iclass 34, count 0 2006.161.07:58:11.02#ibcon#read 3, iclass 34, count 0 2006.161.07:58:11.02#ibcon#about to read 4, iclass 34, count 0 2006.161.07:58:11.02#ibcon#read 4, iclass 34, count 0 2006.161.07:58:11.02#ibcon#about to read 5, iclass 34, count 0 2006.161.07:58:11.02#ibcon#read 5, iclass 34, count 0 2006.161.07:58:11.02#ibcon#about to read 6, iclass 34, count 0 2006.161.07:58:11.02#ibcon#read 6, iclass 34, count 0 2006.161.07:58:11.02#ibcon#end of sib2, iclass 34, count 0 2006.161.07:58:11.02#ibcon#*mode == 0, iclass 34, count 0 2006.161.07:58:11.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.07:58:11.02#ibcon#[25=USB\r\n] 2006.161.07:58:11.02#ibcon#*before write, iclass 34, count 0 2006.161.07:58:11.02#ibcon#enter sib2, iclass 34, count 0 2006.161.07:58:11.02#ibcon#flushed, iclass 34, count 0 2006.161.07:58:11.02#ibcon#about to write, iclass 34, count 0 2006.161.07:58:11.02#ibcon#wrote, iclass 34, count 0 2006.161.07:58:11.02#ibcon#about to read 3, iclass 34, count 0 2006.161.07:58:11.05#ibcon#read 3, iclass 34, count 0 2006.161.07:58:11.05#ibcon#about to read 4, iclass 34, count 0 2006.161.07:58:11.05#ibcon#read 4, iclass 34, count 0 2006.161.07:58:11.05#ibcon#about to read 5, iclass 34, count 0 2006.161.07:58:11.05#ibcon#read 5, iclass 34, count 0 2006.161.07:58:11.05#ibcon#about to read 6, iclass 34, count 0 2006.161.07:58:11.05#ibcon#read 6, iclass 34, count 0 2006.161.07:58:11.05#ibcon#end of sib2, iclass 34, count 0 2006.161.07:58:11.05#ibcon#*after write, iclass 34, count 0 2006.161.07:58:11.05#ibcon#*before return 0, iclass 34, count 0 2006.161.07:58:11.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:58:11.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.07:58:11.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.07:58:11.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.07:58:11.05$vc4f8/valo=8,852.99 2006.161.07:58:11.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.07:58:11.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.07:58:11.05#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:11.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:58:11.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:58:11.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:58:11.05#ibcon#enter wrdev, iclass 36, count 0 2006.161.07:58:11.05#ibcon#first serial, iclass 36, count 0 2006.161.07:58:11.05#ibcon#enter sib2, iclass 36, count 0 2006.161.07:58:11.05#ibcon#flushed, iclass 36, count 0 2006.161.07:58:11.05#ibcon#about to write, iclass 36, count 0 2006.161.07:58:11.05#ibcon#wrote, iclass 36, count 0 2006.161.07:58:11.05#ibcon#about to read 3, iclass 36, count 0 2006.161.07:58:11.07#ibcon#read 3, iclass 36, count 0 2006.161.07:58:11.07#ibcon#about to read 4, iclass 36, count 0 2006.161.07:58:11.07#ibcon#read 4, iclass 36, count 0 2006.161.07:58:11.07#ibcon#about to read 5, iclass 36, count 0 2006.161.07:58:11.07#ibcon#read 5, iclass 36, count 0 2006.161.07:58:11.07#ibcon#about to read 6, iclass 36, count 0 2006.161.07:58:11.07#ibcon#read 6, iclass 36, count 0 2006.161.07:58:11.07#ibcon#end of sib2, iclass 36, count 0 2006.161.07:58:11.07#ibcon#*mode == 0, iclass 36, count 0 2006.161.07:58:11.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.07:58:11.07#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.07:58:11.07#ibcon#*before write, iclass 36, count 0 2006.161.07:58:11.07#ibcon#enter sib2, iclass 36, count 0 2006.161.07:58:11.07#ibcon#flushed, iclass 36, count 0 2006.161.07:58:11.07#ibcon#about to write, iclass 36, count 0 2006.161.07:58:11.07#ibcon#wrote, iclass 36, count 0 2006.161.07:58:11.07#ibcon#about to read 3, iclass 36, count 0 2006.161.07:58:11.11#ibcon#read 3, iclass 36, count 0 2006.161.07:58:11.11#ibcon#about to read 4, iclass 36, count 0 2006.161.07:58:11.11#ibcon#read 4, iclass 36, count 0 2006.161.07:58:11.11#ibcon#about to read 5, iclass 36, count 0 2006.161.07:58:11.11#ibcon#read 5, iclass 36, count 0 2006.161.07:58:11.11#ibcon#about to read 6, iclass 36, count 0 2006.161.07:58:11.11#ibcon#read 6, iclass 36, count 0 2006.161.07:58:11.11#ibcon#end of sib2, iclass 36, count 0 2006.161.07:58:11.11#ibcon#*after write, iclass 36, count 0 2006.161.07:58:11.11#ibcon#*before return 0, iclass 36, count 0 2006.161.07:58:11.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:58:11.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.07:58:11.11#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.07:58:11.11#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.07:58:11.11$vc4f8/va=8,7 2006.161.07:58:11.11#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.07:58:11.11#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.07:58:11.11#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:11.11#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:58:11.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:58:11.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:58:11.17#ibcon#enter wrdev, iclass 38, count 2 2006.161.07:58:11.17#ibcon#first serial, iclass 38, count 2 2006.161.07:58:11.17#ibcon#enter sib2, iclass 38, count 2 2006.161.07:58:11.17#ibcon#flushed, iclass 38, count 2 2006.161.07:58:11.17#ibcon#about to write, iclass 38, count 2 2006.161.07:58:11.17#ibcon#wrote, iclass 38, count 2 2006.161.07:58:11.17#ibcon#about to read 3, iclass 38, count 2 2006.161.07:58:11.19#ibcon#read 3, iclass 38, count 2 2006.161.07:58:11.19#ibcon#about to read 4, iclass 38, count 2 2006.161.07:58:11.19#ibcon#read 4, iclass 38, count 2 2006.161.07:58:11.19#ibcon#about to read 5, iclass 38, count 2 2006.161.07:58:11.19#ibcon#read 5, iclass 38, count 2 2006.161.07:58:11.19#ibcon#about to read 6, iclass 38, count 2 2006.161.07:58:11.19#ibcon#read 6, iclass 38, count 2 2006.161.07:58:11.19#ibcon#end of sib2, iclass 38, count 2 2006.161.07:58:11.19#ibcon#*mode == 0, iclass 38, count 2 2006.161.07:58:11.19#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.07:58:11.19#ibcon#[25=AT08-07\r\n] 2006.161.07:58:11.19#ibcon#*before write, iclass 38, count 2 2006.161.07:58:11.19#ibcon#enter sib2, iclass 38, count 2 2006.161.07:58:11.19#ibcon#flushed, iclass 38, count 2 2006.161.07:58:11.19#ibcon#about to write, iclass 38, count 2 2006.161.07:58:11.19#ibcon#wrote, iclass 38, count 2 2006.161.07:58:11.19#ibcon#about to read 3, iclass 38, count 2 2006.161.07:58:11.22#ibcon#read 3, iclass 38, count 2 2006.161.07:58:11.22#ibcon#about to read 4, iclass 38, count 2 2006.161.07:58:11.22#ibcon#read 4, iclass 38, count 2 2006.161.07:58:11.22#ibcon#about to read 5, iclass 38, count 2 2006.161.07:58:11.22#ibcon#read 5, iclass 38, count 2 2006.161.07:58:11.22#ibcon#about to read 6, iclass 38, count 2 2006.161.07:58:11.22#ibcon#read 6, iclass 38, count 2 2006.161.07:58:11.22#ibcon#end of sib2, iclass 38, count 2 2006.161.07:58:11.22#ibcon#*after write, iclass 38, count 2 2006.161.07:58:11.22#ibcon#*before return 0, iclass 38, count 2 2006.161.07:58:11.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:58:11.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.07:58:11.22#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.07:58:11.22#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:11.22#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:58:11.34#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:58:11.34#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:58:11.34#ibcon#enter wrdev, iclass 38, count 0 2006.161.07:58:11.34#ibcon#first serial, iclass 38, count 0 2006.161.07:58:11.34#ibcon#enter sib2, iclass 38, count 0 2006.161.07:58:11.34#ibcon#flushed, iclass 38, count 0 2006.161.07:58:11.34#ibcon#about to write, iclass 38, count 0 2006.161.07:58:11.34#ibcon#wrote, iclass 38, count 0 2006.161.07:58:11.34#ibcon#about to read 3, iclass 38, count 0 2006.161.07:58:11.36#ibcon#read 3, iclass 38, count 0 2006.161.07:58:11.36#ibcon#about to read 4, iclass 38, count 0 2006.161.07:58:11.36#ibcon#read 4, iclass 38, count 0 2006.161.07:58:11.36#ibcon#about to read 5, iclass 38, count 0 2006.161.07:58:11.36#ibcon#read 5, iclass 38, count 0 2006.161.07:58:11.36#ibcon#about to read 6, iclass 38, count 0 2006.161.07:58:11.36#ibcon#read 6, iclass 38, count 0 2006.161.07:58:11.36#ibcon#end of sib2, iclass 38, count 0 2006.161.07:58:11.36#ibcon#*mode == 0, iclass 38, count 0 2006.161.07:58:11.36#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.07:58:11.36#ibcon#[25=USB\r\n] 2006.161.07:58:11.36#ibcon#*before write, iclass 38, count 0 2006.161.07:58:11.36#ibcon#enter sib2, iclass 38, count 0 2006.161.07:58:11.36#ibcon#flushed, iclass 38, count 0 2006.161.07:58:11.36#ibcon#about to write, iclass 38, count 0 2006.161.07:58:11.36#ibcon#wrote, iclass 38, count 0 2006.161.07:58:11.36#ibcon#about to read 3, iclass 38, count 0 2006.161.07:58:11.39#ibcon#read 3, iclass 38, count 0 2006.161.07:58:11.39#ibcon#about to read 4, iclass 38, count 0 2006.161.07:58:11.39#ibcon#read 4, iclass 38, count 0 2006.161.07:58:11.39#ibcon#about to read 5, iclass 38, count 0 2006.161.07:58:11.39#ibcon#read 5, iclass 38, count 0 2006.161.07:58:11.39#ibcon#about to read 6, iclass 38, count 0 2006.161.07:58:11.39#ibcon#read 6, iclass 38, count 0 2006.161.07:58:11.39#ibcon#end of sib2, iclass 38, count 0 2006.161.07:58:11.39#ibcon#*after write, iclass 38, count 0 2006.161.07:58:11.39#ibcon#*before return 0, iclass 38, count 0 2006.161.07:58:11.39#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:58:11.39#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.07:58:11.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.07:58:11.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.07:58:11.39$vc4f8/vblo=1,632.99 2006.161.07:58:11.39#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.07:58:11.39#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.07:58:11.39#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:11.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:58:11.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:58:11.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:58:11.39#ibcon#enter wrdev, iclass 40, count 0 2006.161.07:58:11.39#ibcon#first serial, iclass 40, count 0 2006.161.07:58:11.39#ibcon#enter sib2, iclass 40, count 0 2006.161.07:58:11.39#ibcon#flushed, iclass 40, count 0 2006.161.07:58:11.39#ibcon#about to write, iclass 40, count 0 2006.161.07:58:11.39#ibcon#wrote, iclass 40, count 0 2006.161.07:58:11.39#ibcon#about to read 3, iclass 40, count 0 2006.161.07:58:11.41#ibcon#read 3, iclass 40, count 0 2006.161.07:58:11.41#ibcon#about to read 4, iclass 40, count 0 2006.161.07:58:11.41#ibcon#read 4, iclass 40, count 0 2006.161.07:58:11.41#ibcon#about to read 5, iclass 40, count 0 2006.161.07:58:11.41#ibcon#read 5, iclass 40, count 0 2006.161.07:58:11.41#ibcon#about to read 6, iclass 40, count 0 2006.161.07:58:11.41#ibcon#read 6, iclass 40, count 0 2006.161.07:58:11.41#ibcon#end of sib2, iclass 40, count 0 2006.161.07:58:11.41#ibcon#*mode == 0, iclass 40, count 0 2006.161.07:58:11.41#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.07:58:11.41#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.07:58:11.41#ibcon#*before write, iclass 40, count 0 2006.161.07:58:11.41#ibcon#enter sib2, iclass 40, count 0 2006.161.07:58:11.41#ibcon#flushed, iclass 40, count 0 2006.161.07:58:11.41#ibcon#about to write, iclass 40, count 0 2006.161.07:58:11.41#ibcon#wrote, iclass 40, count 0 2006.161.07:58:11.41#ibcon#about to read 3, iclass 40, count 0 2006.161.07:58:11.45#ibcon#read 3, iclass 40, count 0 2006.161.07:58:11.45#ibcon#about to read 4, iclass 40, count 0 2006.161.07:58:11.45#ibcon#read 4, iclass 40, count 0 2006.161.07:58:11.45#ibcon#about to read 5, iclass 40, count 0 2006.161.07:58:11.45#ibcon#read 5, iclass 40, count 0 2006.161.07:58:11.45#ibcon#about to read 6, iclass 40, count 0 2006.161.07:58:11.45#ibcon#read 6, iclass 40, count 0 2006.161.07:58:11.45#ibcon#end of sib2, iclass 40, count 0 2006.161.07:58:11.45#ibcon#*after write, iclass 40, count 0 2006.161.07:58:11.45#ibcon#*before return 0, iclass 40, count 0 2006.161.07:58:11.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:58:11.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.07:58:11.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.07:58:11.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.07:58:11.45$vc4f8/vb=1,4 2006.161.07:58:11.45#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.07:58:11.45#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.07:58:11.45#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:11.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:58:11.45#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:58:11.45#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:58:11.45#ibcon#enter wrdev, iclass 4, count 2 2006.161.07:58:11.45#ibcon#first serial, iclass 4, count 2 2006.161.07:58:11.45#ibcon#enter sib2, iclass 4, count 2 2006.161.07:58:11.45#ibcon#flushed, iclass 4, count 2 2006.161.07:58:11.45#ibcon#about to write, iclass 4, count 2 2006.161.07:58:11.45#ibcon#wrote, iclass 4, count 2 2006.161.07:58:11.45#ibcon#about to read 3, iclass 4, count 2 2006.161.07:58:11.47#ibcon#read 3, iclass 4, count 2 2006.161.07:58:11.47#ibcon#about to read 4, iclass 4, count 2 2006.161.07:58:11.47#ibcon#read 4, iclass 4, count 2 2006.161.07:58:11.47#ibcon#about to read 5, iclass 4, count 2 2006.161.07:58:11.47#ibcon#read 5, iclass 4, count 2 2006.161.07:58:11.47#ibcon#about to read 6, iclass 4, count 2 2006.161.07:58:11.47#ibcon#read 6, iclass 4, count 2 2006.161.07:58:11.47#ibcon#end of sib2, iclass 4, count 2 2006.161.07:58:11.47#ibcon#*mode == 0, iclass 4, count 2 2006.161.07:58:11.47#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.07:58:11.47#ibcon#[27=AT01-04\r\n] 2006.161.07:58:11.47#ibcon#*before write, iclass 4, count 2 2006.161.07:58:11.47#ibcon#enter sib2, iclass 4, count 2 2006.161.07:58:11.47#ibcon#flushed, iclass 4, count 2 2006.161.07:58:11.47#ibcon#about to write, iclass 4, count 2 2006.161.07:58:11.47#ibcon#wrote, iclass 4, count 2 2006.161.07:58:11.47#ibcon#about to read 3, iclass 4, count 2 2006.161.07:58:11.50#ibcon#read 3, iclass 4, count 2 2006.161.07:58:11.50#ibcon#about to read 4, iclass 4, count 2 2006.161.07:58:11.50#ibcon#read 4, iclass 4, count 2 2006.161.07:58:11.50#ibcon#about to read 5, iclass 4, count 2 2006.161.07:58:11.50#ibcon#read 5, iclass 4, count 2 2006.161.07:58:11.50#ibcon#about to read 6, iclass 4, count 2 2006.161.07:58:11.50#ibcon#read 6, iclass 4, count 2 2006.161.07:58:11.50#ibcon#end of sib2, iclass 4, count 2 2006.161.07:58:11.50#ibcon#*after write, iclass 4, count 2 2006.161.07:58:11.50#ibcon#*before return 0, iclass 4, count 2 2006.161.07:58:11.50#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:58:11.50#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.07:58:11.50#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.07:58:11.50#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:11.50#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:58:11.62#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:58:11.62#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:58:11.62#ibcon#enter wrdev, iclass 4, count 0 2006.161.07:58:11.62#ibcon#first serial, iclass 4, count 0 2006.161.07:58:11.62#ibcon#enter sib2, iclass 4, count 0 2006.161.07:58:11.62#ibcon#flushed, iclass 4, count 0 2006.161.07:58:11.62#ibcon#about to write, iclass 4, count 0 2006.161.07:58:11.62#ibcon#wrote, iclass 4, count 0 2006.161.07:58:11.62#ibcon#about to read 3, iclass 4, count 0 2006.161.07:58:11.64#ibcon#read 3, iclass 4, count 0 2006.161.07:58:11.64#ibcon#about to read 4, iclass 4, count 0 2006.161.07:58:11.64#ibcon#read 4, iclass 4, count 0 2006.161.07:58:11.64#ibcon#about to read 5, iclass 4, count 0 2006.161.07:58:11.64#ibcon#read 5, iclass 4, count 0 2006.161.07:58:11.64#ibcon#about to read 6, iclass 4, count 0 2006.161.07:58:11.64#ibcon#read 6, iclass 4, count 0 2006.161.07:58:11.64#ibcon#end of sib2, iclass 4, count 0 2006.161.07:58:11.64#ibcon#*mode == 0, iclass 4, count 0 2006.161.07:58:11.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.07:58:11.64#ibcon#[27=USB\r\n] 2006.161.07:58:11.64#ibcon#*before write, iclass 4, count 0 2006.161.07:58:11.64#ibcon#enter sib2, iclass 4, count 0 2006.161.07:58:11.64#ibcon#flushed, iclass 4, count 0 2006.161.07:58:11.64#ibcon#about to write, iclass 4, count 0 2006.161.07:58:11.64#ibcon#wrote, iclass 4, count 0 2006.161.07:58:11.64#ibcon#about to read 3, iclass 4, count 0 2006.161.07:58:11.67#ibcon#read 3, iclass 4, count 0 2006.161.07:58:11.67#ibcon#about to read 4, iclass 4, count 0 2006.161.07:58:11.67#ibcon#read 4, iclass 4, count 0 2006.161.07:58:11.67#ibcon#about to read 5, iclass 4, count 0 2006.161.07:58:11.67#ibcon#read 5, iclass 4, count 0 2006.161.07:58:11.67#ibcon#about to read 6, iclass 4, count 0 2006.161.07:58:11.67#ibcon#read 6, iclass 4, count 0 2006.161.07:58:11.67#ibcon#end of sib2, iclass 4, count 0 2006.161.07:58:11.67#ibcon#*after write, iclass 4, count 0 2006.161.07:58:11.67#ibcon#*before return 0, iclass 4, count 0 2006.161.07:58:11.67#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:58:11.67#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.07:58:11.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.07:58:11.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.07:58:11.67$vc4f8/vblo=2,640.99 2006.161.07:58:11.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.07:58:11.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.07:58:11.67#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:11.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:11.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:11.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:11.67#ibcon#enter wrdev, iclass 6, count 0 2006.161.07:58:11.67#ibcon#first serial, iclass 6, count 0 2006.161.07:58:11.67#ibcon#enter sib2, iclass 6, count 0 2006.161.07:58:11.67#ibcon#flushed, iclass 6, count 0 2006.161.07:58:11.67#ibcon#about to write, iclass 6, count 0 2006.161.07:58:11.67#ibcon#wrote, iclass 6, count 0 2006.161.07:58:11.67#ibcon#about to read 3, iclass 6, count 0 2006.161.07:58:11.69#ibcon#read 3, iclass 6, count 0 2006.161.07:58:11.69#ibcon#about to read 4, iclass 6, count 0 2006.161.07:58:11.69#ibcon#read 4, iclass 6, count 0 2006.161.07:58:11.69#ibcon#about to read 5, iclass 6, count 0 2006.161.07:58:11.69#ibcon#read 5, iclass 6, count 0 2006.161.07:58:11.69#ibcon#about to read 6, iclass 6, count 0 2006.161.07:58:11.69#ibcon#read 6, iclass 6, count 0 2006.161.07:58:11.69#ibcon#end of sib2, iclass 6, count 0 2006.161.07:58:11.69#ibcon#*mode == 0, iclass 6, count 0 2006.161.07:58:11.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.07:58:11.69#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.07:58:11.69#ibcon#*before write, iclass 6, count 0 2006.161.07:58:11.69#ibcon#enter sib2, iclass 6, count 0 2006.161.07:58:11.69#ibcon#flushed, iclass 6, count 0 2006.161.07:58:11.69#ibcon#about to write, iclass 6, count 0 2006.161.07:58:11.69#ibcon#wrote, iclass 6, count 0 2006.161.07:58:11.69#ibcon#about to read 3, iclass 6, count 0 2006.161.07:58:11.73#ibcon#read 3, iclass 6, count 0 2006.161.07:58:11.73#ibcon#about to read 4, iclass 6, count 0 2006.161.07:58:11.73#ibcon#read 4, iclass 6, count 0 2006.161.07:58:11.73#ibcon#about to read 5, iclass 6, count 0 2006.161.07:58:11.73#ibcon#read 5, iclass 6, count 0 2006.161.07:58:11.73#ibcon#about to read 6, iclass 6, count 0 2006.161.07:58:11.73#ibcon#read 6, iclass 6, count 0 2006.161.07:58:11.73#ibcon#end of sib2, iclass 6, count 0 2006.161.07:58:11.73#ibcon#*after write, iclass 6, count 0 2006.161.07:58:11.73#ibcon#*before return 0, iclass 6, count 0 2006.161.07:58:11.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:11.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.07:58:11.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.07:58:11.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.07:58:11.73$vc4f8/vb=2,4 2006.161.07:58:11.73#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.07:58:11.73#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.07:58:11.73#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:11.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:11.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:11.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:11.79#ibcon#enter wrdev, iclass 10, count 2 2006.161.07:58:11.79#ibcon#first serial, iclass 10, count 2 2006.161.07:58:11.79#ibcon#enter sib2, iclass 10, count 2 2006.161.07:58:11.79#ibcon#flushed, iclass 10, count 2 2006.161.07:58:11.79#ibcon#about to write, iclass 10, count 2 2006.161.07:58:11.79#ibcon#wrote, iclass 10, count 2 2006.161.07:58:11.79#ibcon#about to read 3, iclass 10, count 2 2006.161.07:58:11.81#ibcon#read 3, iclass 10, count 2 2006.161.07:58:11.81#ibcon#about to read 4, iclass 10, count 2 2006.161.07:58:11.81#ibcon#read 4, iclass 10, count 2 2006.161.07:58:11.81#ibcon#about to read 5, iclass 10, count 2 2006.161.07:58:11.81#ibcon#read 5, iclass 10, count 2 2006.161.07:58:11.81#ibcon#about to read 6, iclass 10, count 2 2006.161.07:58:11.81#ibcon#read 6, iclass 10, count 2 2006.161.07:58:11.81#ibcon#end of sib2, iclass 10, count 2 2006.161.07:58:11.81#ibcon#*mode == 0, iclass 10, count 2 2006.161.07:58:11.81#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.07:58:11.81#ibcon#[27=AT02-04\r\n] 2006.161.07:58:11.81#ibcon#*before write, iclass 10, count 2 2006.161.07:58:11.81#ibcon#enter sib2, iclass 10, count 2 2006.161.07:58:11.81#ibcon#flushed, iclass 10, count 2 2006.161.07:58:11.81#ibcon#about to write, iclass 10, count 2 2006.161.07:58:11.81#ibcon#wrote, iclass 10, count 2 2006.161.07:58:11.81#ibcon#about to read 3, iclass 10, count 2 2006.161.07:58:11.84#ibcon#read 3, iclass 10, count 2 2006.161.07:58:11.84#ibcon#about to read 4, iclass 10, count 2 2006.161.07:58:11.84#ibcon#read 4, iclass 10, count 2 2006.161.07:58:11.84#ibcon#about to read 5, iclass 10, count 2 2006.161.07:58:11.84#ibcon#read 5, iclass 10, count 2 2006.161.07:58:11.84#ibcon#about to read 6, iclass 10, count 2 2006.161.07:58:11.84#ibcon#read 6, iclass 10, count 2 2006.161.07:58:11.84#ibcon#end of sib2, iclass 10, count 2 2006.161.07:58:11.84#ibcon#*after write, iclass 10, count 2 2006.161.07:58:11.84#ibcon#*before return 0, iclass 10, count 2 2006.161.07:58:11.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:11.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.07:58:11.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.07:58:11.84#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:11.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:11.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:11.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:11.96#ibcon#enter wrdev, iclass 10, count 0 2006.161.07:58:11.96#ibcon#first serial, iclass 10, count 0 2006.161.07:58:11.96#ibcon#enter sib2, iclass 10, count 0 2006.161.07:58:11.96#ibcon#flushed, iclass 10, count 0 2006.161.07:58:11.96#ibcon#about to write, iclass 10, count 0 2006.161.07:58:11.96#ibcon#wrote, iclass 10, count 0 2006.161.07:58:11.96#ibcon#about to read 3, iclass 10, count 0 2006.161.07:58:11.98#ibcon#read 3, iclass 10, count 0 2006.161.07:58:11.98#ibcon#about to read 4, iclass 10, count 0 2006.161.07:58:11.98#ibcon#read 4, iclass 10, count 0 2006.161.07:58:11.98#ibcon#about to read 5, iclass 10, count 0 2006.161.07:58:11.98#ibcon#read 5, iclass 10, count 0 2006.161.07:58:11.98#ibcon#about to read 6, iclass 10, count 0 2006.161.07:58:11.98#ibcon#read 6, iclass 10, count 0 2006.161.07:58:11.98#ibcon#end of sib2, iclass 10, count 0 2006.161.07:58:11.98#ibcon#*mode == 0, iclass 10, count 0 2006.161.07:58:11.98#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.07:58:11.98#ibcon#[27=USB\r\n] 2006.161.07:58:11.98#ibcon#*before write, iclass 10, count 0 2006.161.07:58:11.98#ibcon#enter sib2, iclass 10, count 0 2006.161.07:58:11.98#ibcon#flushed, iclass 10, count 0 2006.161.07:58:11.98#ibcon#about to write, iclass 10, count 0 2006.161.07:58:11.98#ibcon#wrote, iclass 10, count 0 2006.161.07:58:11.98#ibcon#about to read 3, iclass 10, count 0 2006.161.07:58:12.01#ibcon#read 3, iclass 10, count 0 2006.161.07:58:12.01#ibcon#about to read 4, iclass 10, count 0 2006.161.07:58:12.01#ibcon#read 4, iclass 10, count 0 2006.161.07:58:12.01#ibcon#about to read 5, iclass 10, count 0 2006.161.07:58:12.01#ibcon#read 5, iclass 10, count 0 2006.161.07:58:12.01#ibcon#about to read 6, iclass 10, count 0 2006.161.07:58:12.01#ibcon#read 6, iclass 10, count 0 2006.161.07:58:12.01#ibcon#end of sib2, iclass 10, count 0 2006.161.07:58:12.01#ibcon#*after write, iclass 10, count 0 2006.161.07:58:12.01#ibcon#*before return 0, iclass 10, count 0 2006.161.07:58:12.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:12.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.07:58:12.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.07:58:12.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.07:58:12.01$vc4f8/vblo=3,656.99 2006.161.07:58:12.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.07:58:12.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.07:58:12.01#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:12.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:12.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:12.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:12.01#ibcon#enter wrdev, iclass 12, count 0 2006.161.07:58:12.01#ibcon#first serial, iclass 12, count 0 2006.161.07:58:12.01#ibcon#enter sib2, iclass 12, count 0 2006.161.07:58:12.01#ibcon#flushed, iclass 12, count 0 2006.161.07:58:12.01#ibcon#about to write, iclass 12, count 0 2006.161.07:58:12.01#ibcon#wrote, iclass 12, count 0 2006.161.07:58:12.01#ibcon#about to read 3, iclass 12, count 0 2006.161.07:58:12.03#ibcon#read 3, iclass 12, count 0 2006.161.07:58:12.03#ibcon#about to read 4, iclass 12, count 0 2006.161.07:58:12.03#ibcon#read 4, iclass 12, count 0 2006.161.07:58:12.03#ibcon#about to read 5, iclass 12, count 0 2006.161.07:58:12.03#ibcon#read 5, iclass 12, count 0 2006.161.07:58:12.03#ibcon#about to read 6, iclass 12, count 0 2006.161.07:58:12.03#ibcon#read 6, iclass 12, count 0 2006.161.07:58:12.03#ibcon#end of sib2, iclass 12, count 0 2006.161.07:58:12.03#ibcon#*mode == 0, iclass 12, count 0 2006.161.07:58:12.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.07:58:12.03#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.07:58:12.03#ibcon#*before write, iclass 12, count 0 2006.161.07:58:12.03#ibcon#enter sib2, iclass 12, count 0 2006.161.07:58:12.03#ibcon#flushed, iclass 12, count 0 2006.161.07:58:12.03#ibcon#about to write, iclass 12, count 0 2006.161.07:58:12.03#ibcon#wrote, iclass 12, count 0 2006.161.07:58:12.03#ibcon#about to read 3, iclass 12, count 0 2006.161.07:58:12.07#ibcon#read 3, iclass 12, count 0 2006.161.07:58:12.07#ibcon#about to read 4, iclass 12, count 0 2006.161.07:58:12.07#ibcon#read 4, iclass 12, count 0 2006.161.07:58:12.07#ibcon#about to read 5, iclass 12, count 0 2006.161.07:58:12.07#ibcon#read 5, iclass 12, count 0 2006.161.07:58:12.07#ibcon#about to read 6, iclass 12, count 0 2006.161.07:58:12.07#ibcon#read 6, iclass 12, count 0 2006.161.07:58:12.07#ibcon#end of sib2, iclass 12, count 0 2006.161.07:58:12.07#ibcon#*after write, iclass 12, count 0 2006.161.07:58:12.07#ibcon#*before return 0, iclass 12, count 0 2006.161.07:58:12.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:12.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.07:58:12.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.07:58:12.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.07:58:12.07$vc4f8/vb=3,4 2006.161.07:58:12.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.07:58:12.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.07:58:12.07#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:12.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:12.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:12.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:12.13#ibcon#enter wrdev, iclass 14, count 2 2006.161.07:58:12.13#ibcon#first serial, iclass 14, count 2 2006.161.07:58:12.13#ibcon#enter sib2, iclass 14, count 2 2006.161.07:58:12.13#ibcon#flushed, iclass 14, count 2 2006.161.07:58:12.13#ibcon#about to write, iclass 14, count 2 2006.161.07:58:12.13#ibcon#wrote, iclass 14, count 2 2006.161.07:58:12.13#ibcon#about to read 3, iclass 14, count 2 2006.161.07:58:12.15#ibcon#read 3, iclass 14, count 2 2006.161.07:58:12.15#ibcon#about to read 4, iclass 14, count 2 2006.161.07:58:12.15#ibcon#read 4, iclass 14, count 2 2006.161.07:58:12.15#ibcon#about to read 5, iclass 14, count 2 2006.161.07:58:12.15#ibcon#read 5, iclass 14, count 2 2006.161.07:58:12.15#ibcon#about to read 6, iclass 14, count 2 2006.161.07:58:12.15#ibcon#read 6, iclass 14, count 2 2006.161.07:58:12.15#ibcon#end of sib2, iclass 14, count 2 2006.161.07:58:12.15#ibcon#*mode == 0, iclass 14, count 2 2006.161.07:58:12.15#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.07:58:12.15#ibcon#[27=AT03-04\r\n] 2006.161.07:58:12.15#ibcon#*before write, iclass 14, count 2 2006.161.07:58:12.15#ibcon#enter sib2, iclass 14, count 2 2006.161.07:58:12.15#ibcon#flushed, iclass 14, count 2 2006.161.07:58:12.15#ibcon#about to write, iclass 14, count 2 2006.161.07:58:12.15#ibcon#wrote, iclass 14, count 2 2006.161.07:58:12.15#ibcon#about to read 3, iclass 14, count 2 2006.161.07:58:12.18#ibcon#read 3, iclass 14, count 2 2006.161.07:58:12.18#ibcon#about to read 4, iclass 14, count 2 2006.161.07:58:12.18#ibcon#read 4, iclass 14, count 2 2006.161.07:58:12.18#ibcon#about to read 5, iclass 14, count 2 2006.161.07:58:12.18#ibcon#read 5, iclass 14, count 2 2006.161.07:58:12.18#ibcon#about to read 6, iclass 14, count 2 2006.161.07:58:12.18#ibcon#read 6, iclass 14, count 2 2006.161.07:58:12.18#ibcon#end of sib2, iclass 14, count 2 2006.161.07:58:12.18#ibcon#*after write, iclass 14, count 2 2006.161.07:58:12.18#ibcon#*before return 0, iclass 14, count 2 2006.161.07:58:12.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:12.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.07:58:12.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.07:58:12.18#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:12.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:12.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:12.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:12.30#ibcon#enter wrdev, iclass 14, count 0 2006.161.07:58:12.30#ibcon#first serial, iclass 14, count 0 2006.161.07:58:12.30#ibcon#enter sib2, iclass 14, count 0 2006.161.07:58:12.30#ibcon#flushed, iclass 14, count 0 2006.161.07:58:12.30#ibcon#about to write, iclass 14, count 0 2006.161.07:58:12.30#ibcon#wrote, iclass 14, count 0 2006.161.07:58:12.30#ibcon#about to read 3, iclass 14, count 0 2006.161.07:58:12.32#ibcon#read 3, iclass 14, count 0 2006.161.07:58:12.32#ibcon#about to read 4, iclass 14, count 0 2006.161.07:58:12.32#ibcon#read 4, iclass 14, count 0 2006.161.07:58:12.32#ibcon#about to read 5, iclass 14, count 0 2006.161.07:58:12.32#ibcon#read 5, iclass 14, count 0 2006.161.07:58:12.32#ibcon#about to read 6, iclass 14, count 0 2006.161.07:58:12.32#ibcon#read 6, iclass 14, count 0 2006.161.07:58:12.32#ibcon#end of sib2, iclass 14, count 0 2006.161.07:58:12.32#ibcon#*mode == 0, iclass 14, count 0 2006.161.07:58:12.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.07:58:12.32#ibcon#[27=USB\r\n] 2006.161.07:58:12.32#ibcon#*before write, iclass 14, count 0 2006.161.07:58:12.32#ibcon#enter sib2, iclass 14, count 0 2006.161.07:58:12.32#ibcon#flushed, iclass 14, count 0 2006.161.07:58:12.32#ibcon#about to write, iclass 14, count 0 2006.161.07:58:12.32#ibcon#wrote, iclass 14, count 0 2006.161.07:58:12.32#ibcon#about to read 3, iclass 14, count 0 2006.161.07:58:12.35#ibcon#read 3, iclass 14, count 0 2006.161.07:58:12.35#ibcon#about to read 4, iclass 14, count 0 2006.161.07:58:12.35#ibcon#read 4, iclass 14, count 0 2006.161.07:58:12.35#ibcon#about to read 5, iclass 14, count 0 2006.161.07:58:12.35#ibcon#read 5, iclass 14, count 0 2006.161.07:58:12.35#ibcon#about to read 6, iclass 14, count 0 2006.161.07:58:12.35#ibcon#read 6, iclass 14, count 0 2006.161.07:58:12.35#ibcon#end of sib2, iclass 14, count 0 2006.161.07:58:12.35#ibcon#*after write, iclass 14, count 0 2006.161.07:58:12.35#ibcon#*before return 0, iclass 14, count 0 2006.161.07:58:12.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:12.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.07:58:12.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.07:58:12.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.07:58:12.35$vc4f8/vblo=4,712.99 2006.161.07:58:12.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.07:58:12.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.07:58:12.35#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:12.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:12.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:12.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:12.35#ibcon#enter wrdev, iclass 16, count 0 2006.161.07:58:12.35#ibcon#first serial, iclass 16, count 0 2006.161.07:58:12.35#ibcon#enter sib2, iclass 16, count 0 2006.161.07:58:12.35#ibcon#flushed, iclass 16, count 0 2006.161.07:58:12.35#ibcon#about to write, iclass 16, count 0 2006.161.07:58:12.35#ibcon#wrote, iclass 16, count 0 2006.161.07:58:12.35#ibcon#about to read 3, iclass 16, count 0 2006.161.07:58:12.37#ibcon#read 3, iclass 16, count 0 2006.161.07:58:12.37#ibcon#about to read 4, iclass 16, count 0 2006.161.07:58:12.37#ibcon#read 4, iclass 16, count 0 2006.161.07:58:12.37#ibcon#about to read 5, iclass 16, count 0 2006.161.07:58:12.37#ibcon#read 5, iclass 16, count 0 2006.161.07:58:12.37#ibcon#about to read 6, iclass 16, count 0 2006.161.07:58:12.37#ibcon#read 6, iclass 16, count 0 2006.161.07:58:12.37#ibcon#end of sib2, iclass 16, count 0 2006.161.07:58:12.37#ibcon#*mode == 0, iclass 16, count 0 2006.161.07:58:12.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.07:58:12.37#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.07:58:12.37#ibcon#*before write, iclass 16, count 0 2006.161.07:58:12.37#ibcon#enter sib2, iclass 16, count 0 2006.161.07:58:12.37#ibcon#flushed, iclass 16, count 0 2006.161.07:58:12.37#ibcon#about to write, iclass 16, count 0 2006.161.07:58:12.37#ibcon#wrote, iclass 16, count 0 2006.161.07:58:12.37#ibcon#about to read 3, iclass 16, count 0 2006.161.07:58:12.41#ibcon#read 3, iclass 16, count 0 2006.161.07:58:12.41#ibcon#about to read 4, iclass 16, count 0 2006.161.07:58:12.41#ibcon#read 4, iclass 16, count 0 2006.161.07:58:12.41#ibcon#about to read 5, iclass 16, count 0 2006.161.07:58:12.41#ibcon#read 5, iclass 16, count 0 2006.161.07:58:12.41#ibcon#about to read 6, iclass 16, count 0 2006.161.07:58:12.41#ibcon#read 6, iclass 16, count 0 2006.161.07:58:12.41#ibcon#end of sib2, iclass 16, count 0 2006.161.07:58:12.41#ibcon#*after write, iclass 16, count 0 2006.161.07:58:12.41#ibcon#*before return 0, iclass 16, count 0 2006.161.07:58:12.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:12.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.07:58:12.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.07:58:12.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.07:58:12.41$vc4f8/vb=4,4 2006.161.07:58:12.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.07:58:12.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.07:58:12.41#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:12.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:12.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:12.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:12.47#ibcon#enter wrdev, iclass 18, count 2 2006.161.07:58:12.47#ibcon#first serial, iclass 18, count 2 2006.161.07:58:12.47#ibcon#enter sib2, iclass 18, count 2 2006.161.07:58:12.47#ibcon#flushed, iclass 18, count 2 2006.161.07:58:12.47#ibcon#about to write, iclass 18, count 2 2006.161.07:58:12.47#ibcon#wrote, iclass 18, count 2 2006.161.07:58:12.47#ibcon#about to read 3, iclass 18, count 2 2006.161.07:58:12.49#ibcon#read 3, iclass 18, count 2 2006.161.07:58:12.49#ibcon#about to read 4, iclass 18, count 2 2006.161.07:58:12.49#ibcon#read 4, iclass 18, count 2 2006.161.07:58:12.49#ibcon#about to read 5, iclass 18, count 2 2006.161.07:58:12.49#ibcon#read 5, iclass 18, count 2 2006.161.07:58:12.49#ibcon#about to read 6, iclass 18, count 2 2006.161.07:58:12.49#ibcon#read 6, iclass 18, count 2 2006.161.07:58:12.49#ibcon#end of sib2, iclass 18, count 2 2006.161.07:58:12.49#ibcon#*mode == 0, iclass 18, count 2 2006.161.07:58:12.49#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.07:58:12.49#ibcon#[27=AT04-04\r\n] 2006.161.07:58:12.49#ibcon#*before write, iclass 18, count 2 2006.161.07:58:12.49#ibcon#enter sib2, iclass 18, count 2 2006.161.07:58:12.49#ibcon#flushed, iclass 18, count 2 2006.161.07:58:12.49#ibcon#about to write, iclass 18, count 2 2006.161.07:58:12.49#ibcon#wrote, iclass 18, count 2 2006.161.07:58:12.49#ibcon#about to read 3, iclass 18, count 2 2006.161.07:58:12.52#ibcon#read 3, iclass 18, count 2 2006.161.07:58:12.52#ibcon#about to read 4, iclass 18, count 2 2006.161.07:58:12.52#ibcon#read 4, iclass 18, count 2 2006.161.07:58:12.52#ibcon#about to read 5, iclass 18, count 2 2006.161.07:58:12.52#ibcon#read 5, iclass 18, count 2 2006.161.07:58:12.52#ibcon#about to read 6, iclass 18, count 2 2006.161.07:58:12.52#ibcon#read 6, iclass 18, count 2 2006.161.07:58:12.52#ibcon#end of sib2, iclass 18, count 2 2006.161.07:58:12.52#ibcon#*after write, iclass 18, count 2 2006.161.07:58:12.52#ibcon#*before return 0, iclass 18, count 2 2006.161.07:58:12.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:12.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.07:58:12.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.07:58:12.52#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:12.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:12.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:12.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:12.64#ibcon#enter wrdev, iclass 18, count 0 2006.161.07:58:12.64#ibcon#first serial, iclass 18, count 0 2006.161.07:58:12.64#ibcon#enter sib2, iclass 18, count 0 2006.161.07:58:12.64#ibcon#flushed, iclass 18, count 0 2006.161.07:58:12.64#ibcon#about to write, iclass 18, count 0 2006.161.07:58:12.64#ibcon#wrote, iclass 18, count 0 2006.161.07:58:12.64#ibcon#about to read 3, iclass 18, count 0 2006.161.07:58:12.66#ibcon#read 3, iclass 18, count 0 2006.161.07:58:12.66#ibcon#about to read 4, iclass 18, count 0 2006.161.07:58:12.66#ibcon#read 4, iclass 18, count 0 2006.161.07:58:12.66#ibcon#about to read 5, iclass 18, count 0 2006.161.07:58:12.66#ibcon#read 5, iclass 18, count 0 2006.161.07:58:12.66#ibcon#about to read 6, iclass 18, count 0 2006.161.07:58:12.66#ibcon#read 6, iclass 18, count 0 2006.161.07:58:12.66#ibcon#end of sib2, iclass 18, count 0 2006.161.07:58:12.66#ibcon#*mode == 0, iclass 18, count 0 2006.161.07:58:12.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.07:58:12.66#ibcon#[27=USB\r\n] 2006.161.07:58:12.66#ibcon#*before write, iclass 18, count 0 2006.161.07:58:12.66#ibcon#enter sib2, iclass 18, count 0 2006.161.07:58:12.66#ibcon#flushed, iclass 18, count 0 2006.161.07:58:12.66#ibcon#about to write, iclass 18, count 0 2006.161.07:58:12.66#ibcon#wrote, iclass 18, count 0 2006.161.07:58:12.66#ibcon#about to read 3, iclass 18, count 0 2006.161.07:58:12.69#ibcon#read 3, iclass 18, count 0 2006.161.07:58:12.69#ibcon#about to read 4, iclass 18, count 0 2006.161.07:58:12.69#ibcon#read 4, iclass 18, count 0 2006.161.07:58:12.69#ibcon#about to read 5, iclass 18, count 0 2006.161.07:58:12.69#ibcon#read 5, iclass 18, count 0 2006.161.07:58:12.69#ibcon#about to read 6, iclass 18, count 0 2006.161.07:58:12.69#ibcon#read 6, iclass 18, count 0 2006.161.07:58:12.69#ibcon#end of sib2, iclass 18, count 0 2006.161.07:58:12.69#ibcon#*after write, iclass 18, count 0 2006.161.07:58:12.69#ibcon#*before return 0, iclass 18, count 0 2006.161.07:58:12.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:12.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.07:58:12.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.07:58:12.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.07:58:12.69$vc4f8/vblo=5,744.99 2006.161.07:58:12.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.07:58:12.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.07:58:12.69#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:12.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:12.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:12.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:12.69#ibcon#enter wrdev, iclass 20, count 0 2006.161.07:58:12.69#ibcon#first serial, iclass 20, count 0 2006.161.07:58:12.69#ibcon#enter sib2, iclass 20, count 0 2006.161.07:58:12.69#ibcon#flushed, iclass 20, count 0 2006.161.07:58:12.69#ibcon#about to write, iclass 20, count 0 2006.161.07:58:12.69#ibcon#wrote, iclass 20, count 0 2006.161.07:58:12.69#ibcon#about to read 3, iclass 20, count 0 2006.161.07:58:12.71#ibcon#read 3, iclass 20, count 0 2006.161.07:58:12.71#ibcon#about to read 4, iclass 20, count 0 2006.161.07:58:12.71#ibcon#read 4, iclass 20, count 0 2006.161.07:58:12.71#ibcon#about to read 5, iclass 20, count 0 2006.161.07:58:12.71#ibcon#read 5, iclass 20, count 0 2006.161.07:58:12.71#ibcon#about to read 6, iclass 20, count 0 2006.161.07:58:12.71#ibcon#read 6, iclass 20, count 0 2006.161.07:58:12.71#ibcon#end of sib2, iclass 20, count 0 2006.161.07:58:12.71#ibcon#*mode == 0, iclass 20, count 0 2006.161.07:58:12.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.07:58:12.71#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.07:58:12.71#ibcon#*before write, iclass 20, count 0 2006.161.07:58:12.71#ibcon#enter sib2, iclass 20, count 0 2006.161.07:58:12.71#ibcon#flushed, iclass 20, count 0 2006.161.07:58:12.71#ibcon#about to write, iclass 20, count 0 2006.161.07:58:12.71#ibcon#wrote, iclass 20, count 0 2006.161.07:58:12.71#ibcon#about to read 3, iclass 20, count 0 2006.161.07:58:12.75#ibcon#read 3, iclass 20, count 0 2006.161.07:58:12.75#ibcon#about to read 4, iclass 20, count 0 2006.161.07:58:12.75#ibcon#read 4, iclass 20, count 0 2006.161.07:58:12.75#ibcon#about to read 5, iclass 20, count 0 2006.161.07:58:12.75#ibcon#read 5, iclass 20, count 0 2006.161.07:58:12.75#ibcon#about to read 6, iclass 20, count 0 2006.161.07:58:12.75#ibcon#read 6, iclass 20, count 0 2006.161.07:58:12.75#ibcon#end of sib2, iclass 20, count 0 2006.161.07:58:12.75#ibcon#*after write, iclass 20, count 0 2006.161.07:58:12.75#ibcon#*before return 0, iclass 20, count 0 2006.161.07:58:12.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:12.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.07:58:12.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.07:58:12.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.07:58:12.75$vc4f8/vb=5,4 2006.161.07:58:12.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.07:58:12.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.07:58:12.75#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:12.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:12.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:12.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:12.81#ibcon#enter wrdev, iclass 22, count 2 2006.161.07:58:12.81#ibcon#first serial, iclass 22, count 2 2006.161.07:58:12.81#ibcon#enter sib2, iclass 22, count 2 2006.161.07:58:12.81#ibcon#flushed, iclass 22, count 2 2006.161.07:58:12.81#ibcon#about to write, iclass 22, count 2 2006.161.07:58:12.81#ibcon#wrote, iclass 22, count 2 2006.161.07:58:12.81#ibcon#about to read 3, iclass 22, count 2 2006.161.07:58:12.83#ibcon#read 3, iclass 22, count 2 2006.161.07:58:12.83#ibcon#about to read 4, iclass 22, count 2 2006.161.07:58:12.83#ibcon#read 4, iclass 22, count 2 2006.161.07:58:12.83#ibcon#about to read 5, iclass 22, count 2 2006.161.07:58:12.83#ibcon#read 5, iclass 22, count 2 2006.161.07:58:12.83#ibcon#about to read 6, iclass 22, count 2 2006.161.07:58:12.83#ibcon#read 6, iclass 22, count 2 2006.161.07:58:12.83#ibcon#end of sib2, iclass 22, count 2 2006.161.07:58:12.83#ibcon#*mode == 0, iclass 22, count 2 2006.161.07:58:12.83#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.07:58:12.83#ibcon#[27=AT05-04\r\n] 2006.161.07:58:12.83#ibcon#*before write, iclass 22, count 2 2006.161.07:58:12.83#ibcon#enter sib2, iclass 22, count 2 2006.161.07:58:12.83#ibcon#flushed, iclass 22, count 2 2006.161.07:58:12.83#ibcon#about to write, iclass 22, count 2 2006.161.07:58:12.83#ibcon#wrote, iclass 22, count 2 2006.161.07:58:12.83#ibcon#about to read 3, iclass 22, count 2 2006.161.07:58:12.86#ibcon#read 3, iclass 22, count 2 2006.161.07:58:12.86#ibcon#about to read 4, iclass 22, count 2 2006.161.07:58:12.86#ibcon#read 4, iclass 22, count 2 2006.161.07:58:12.86#ibcon#about to read 5, iclass 22, count 2 2006.161.07:58:12.86#ibcon#read 5, iclass 22, count 2 2006.161.07:58:12.86#ibcon#about to read 6, iclass 22, count 2 2006.161.07:58:12.86#ibcon#read 6, iclass 22, count 2 2006.161.07:58:12.86#ibcon#end of sib2, iclass 22, count 2 2006.161.07:58:12.86#ibcon#*after write, iclass 22, count 2 2006.161.07:58:12.86#ibcon#*before return 0, iclass 22, count 2 2006.161.07:58:12.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:12.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.07:58:12.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.07:58:12.86#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:12.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:12.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:12.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:12.98#ibcon#enter wrdev, iclass 22, count 0 2006.161.07:58:12.98#ibcon#first serial, iclass 22, count 0 2006.161.07:58:12.98#ibcon#enter sib2, iclass 22, count 0 2006.161.07:58:12.98#ibcon#flushed, iclass 22, count 0 2006.161.07:58:12.98#ibcon#about to write, iclass 22, count 0 2006.161.07:58:12.98#ibcon#wrote, iclass 22, count 0 2006.161.07:58:12.98#ibcon#about to read 3, iclass 22, count 0 2006.161.07:58:13.00#ibcon#read 3, iclass 22, count 0 2006.161.07:58:13.00#ibcon#about to read 4, iclass 22, count 0 2006.161.07:58:13.00#ibcon#read 4, iclass 22, count 0 2006.161.07:58:13.00#ibcon#about to read 5, iclass 22, count 0 2006.161.07:58:13.00#ibcon#read 5, iclass 22, count 0 2006.161.07:58:13.00#ibcon#about to read 6, iclass 22, count 0 2006.161.07:58:13.00#ibcon#read 6, iclass 22, count 0 2006.161.07:58:13.00#ibcon#end of sib2, iclass 22, count 0 2006.161.07:58:13.00#ibcon#*mode == 0, iclass 22, count 0 2006.161.07:58:13.00#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.07:58:13.00#ibcon#[27=USB\r\n] 2006.161.07:58:13.00#ibcon#*before write, iclass 22, count 0 2006.161.07:58:13.00#ibcon#enter sib2, iclass 22, count 0 2006.161.07:58:13.00#ibcon#flushed, iclass 22, count 0 2006.161.07:58:13.00#ibcon#about to write, iclass 22, count 0 2006.161.07:58:13.00#ibcon#wrote, iclass 22, count 0 2006.161.07:58:13.00#ibcon#about to read 3, iclass 22, count 0 2006.161.07:58:13.03#ibcon#read 3, iclass 22, count 0 2006.161.07:58:13.03#ibcon#about to read 4, iclass 22, count 0 2006.161.07:58:13.03#ibcon#read 4, iclass 22, count 0 2006.161.07:58:13.03#ibcon#about to read 5, iclass 22, count 0 2006.161.07:58:13.03#ibcon#read 5, iclass 22, count 0 2006.161.07:58:13.03#ibcon#about to read 6, iclass 22, count 0 2006.161.07:58:13.03#ibcon#read 6, iclass 22, count 0 2006.161.07:58:13.03#ibcon#end of sib2, iclass 22, count 0 2006.161.07:58:13.03#ibcon#*after write, iclass 22, count 0 2006.161.07:58:13.03#ibcon#*before return 0, iclass 22, count 0 2006.161.07:58:13.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:13.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.07:58:13.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.07:58:13.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.07:58:13.03$vc4f8/vblo=6,752.99 2006.161.07:58:13.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.07:58:13.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.07:58:13.03#ibcon#ireg 17 cls_cnt 0 2006.161.07:58:13.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:13.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:13.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:13.03#ibcon#enter wrdev, iclass 24, count 0 2006.161.07:58:13.03#ibcon#first serial, iclass 24, count 0 2006.161.07:58:13.03#ibcon#enter sib2, iclass 24, count 0 2006.161.07:58:13.03#ibcon#flushed, iclass 24, count 0 2006.161.07:58:13.03#ibcon#about to write, iclass 24, count 0 2006.161.07:58:13.03#ibcon#wrote, iclass 24, count 0 2006.161.07:58:13.03#ibcon#about to read 3, iclass 24, count 0 2006.161.07:58:13.05#ibcon#read 3, iclass 24, count 0 2006.161.07:58:13.05#ibcon#about to read 4, iclass 24, count 0 2006.161.07:58:13.05#ibcon#read 4, iclass 24, count 0 2006.161.07:58:13.05#ibcon#about to read 5, iclass 24, count 0 2006.161.07:58:13.05#ibcon#read 5, iclass 24, count 0 2006.161.07:58:13.05#ibcon#about to read 6, iclass 24, count 0 2006.161.07:58:13.05#ibcon#read 6, iclass 24, count 0 2006.161.07:58:13.05#ibcon#end of sib2, iclass 24, count 0 2006.161.07:58:13.05#ibcon#*mode == 0, iclass 24, count 0 2006.161.07:58:13.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.07:58:13.05#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.07:58:13.05#ibcon#*before write, iclass 24, count 0 2006.161.07:58:13.05#ibcon#enter sib2, iclass 24, count 0 2006.161.07:58:13.05#ibcon#flushed, iclass 24, count 0 2006.161.07:58:13.05#ibcon#about to write, iclass 24, count 0 2006.161.07:58:13.05#ibcon#wrote, iclass 24, count 0 2006.161.07:58:13.05#ibcon#about to read 3, iclass 24, count 0 2006.161.07:58:13.09#ibcon#read 3, iclass 24, count 0 2006.161.07:58:13.09#ibcon#about to read 4, iclass 24, count 0 2006.161.07:58:13.09#ibcon#read 4, iclass 24, count 0 2006.161.07:58:13.09#ibcon#about to read 5, iclass 24, count 0 2006.161.07:58:13.09#ibcon#read 5, iclass 24, count 0 2006.161.07:58:13.09#ibcon#about to read 6, iclass 24, count 0 2006.161.07:58:13.09#ibcon#read 6, iclass 24, count 0 2006.161.07:58:13.09#ibcon#end of sib2, iclass 24, count 0 2006.161.07:58:13.09#ibcon#*after write, iclass 24, count 0 2006.161.07:58:13.09#ibcon#*before return 0, iclass 24, count 0 2006.161.07:58:13.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:13.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.07:58:13.09#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.07:58:13.09#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.07:58:13.09$vc4f8/vb=6,4 2006.161.07:58:13.09#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.07:58:13.09#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.07:58:13.09#ibcon#ireg 11 cls_cnt 2 2006.161.07:58:13.09#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:13.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:13.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:13.15#ibcon#enter wrdev, iclass 26, count 2 2006.161.07:58:13.15#ibcon#first serial, iclass 26, count 2 2006.161.07:58:13.15#ibcon#enter sib2, iclass 26, count 2 2006.161.07:58:13.15#ibcon#flushed, iclass 26, count 2 2006.161.07:58:13.15#ibcon#about to write, iclass 26, count 2 2006.161.07:58:13.15#ibcon#wrote, iclass 26, count 2 2006.161.07:58:13.15#ibcon#about to read 3, iclass 26, count 2 2006.161.07:58:13.17#ibcon#read 3, iclass 26, count 2 2006.161.07:58:13.17#ibcon#about to read 4, iclass 26, count 2 2006.161.07:58:13.17#ibcon#read 4, iclass 26, count 2 2006.161.07:58:13.17#ibcon#about to read 5, iclass 26, count 2 2006.161.07:58:13.17#ibcon#read 5, iclass 26, count 2 2006.161.07:58:13.17#ibcon#about to read 6, iclass 26, count 2 2006.161.07:58:13.17#ibcon#read 6, iclass 26, count 2 2006.161.07:58:13.17#ibcon#end of sib2, iclass 26, count 2 2006.161.07:58:13.17#ibcon#*mode == 0, iclass 26, count 2 2006.161.07:58:13.17#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.07:58:13.17#ibcon#[27=AT06-04\r\n] 2006.161.07:58:13.17#ibcon#*before write, iclass 26, count 2 2006.161.07:58:13.17#ibcon#enter sib2, iclass 26, count 2 2006.161.07:58:13.17#ibcon#flushed, iclass 26, count 2 2006.161.07:58:13.17#ibcon#about to write, iclass 26, count 2 2006.161.07:58:13.17#ibcon#wrote, iclass 26, count 2 2006.161.07:58:13.17#ibcon#about to read 3, iclass 26, count 2 2006.161.07:58:13.20#ibcon#read 3, iclass 26, count 2 2006.161.07:58:13.20#ibcon#about to read 4, iclass 26, count 2 2006.161.07:58:13.20#ibcon#read 4, iclass 26, count 2 2006.161.07:58:13.20#ibcon#about to read 5, iclass 26, count 2 2006.161.07:58:13.20#ibcon#read 5, iclass 26, count 2 2006.161.07:58:13.20#ibcon#about to read 6, iclass 26, count 2 2006.161.07:58:13.20#ibcon#read 6, iclass 26, count 2 2006.161.07:58:13.20#ibcon#end of sib2, iclass 26, count 2 2006.161.07:58:13.20#ibcon#*after write, iclass 26, count 2 2006.161.07:58:13.20#ibcon#*before return 0, iclass 26, count 2 2006.161.07:58:13.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:13.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.07:58:13.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.07:58:13.20#ibcon#ireg 7 cls_cnt 0 2006.161.07:58:13.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:13.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:13.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:13.32#ibcon#enter wrdev, iclass 26, count 0 2006.161.07:58:13.32#ibcon#first serial, iclass 26, count 0 2006.161.07:58:13.32#ibcon#enter sib2, iclass 26, count 0 2006.161.07:58:13.32#ibcon#flushed, iclass 26, count 0 2006.161.07:58:13.32#ibcon#about to write, iclass 26, count 0 2006.161.07:58:13.32#ibcon#wrote, iclass 26, count 0 2006.161.07:58:13.32#ibcon#about to read 3, iclass 26, count 0 2006.161.07:58:13.34#ibcon#read 3, iclass 26, count 0 2006.161.07:58:13.34#ibcon#about to read 4, iclass 26, count 0 2006.161.07:58:13.34#ibcon#read 4, iclass 26, count 0 2006.161.07:58:13.34#ibcon#about to read 5, iclass 26, count 0 2006.161.07:58:13.34#ibcon#read 5, iclass 26, count 0 2006.161.07:58:13.34#ibcon#about to read 6, iclass 26, count 0 2006.161.07:58:13.34#ibcon#read 6, iclass 26, count 0 2006.161.07:58:13.34#ibcon#end of sib2, iclass 26, count 0 2006.161.07:58:13.34#ibcon#*mode == 0, iclass 26, count 0 2006.161.07:58:13.34#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.07:58:13.34#ibcon#[27=USB\r\n] 2006.161.07:58:13.34#ibcon#*before write, iclass 26, count 0 2006.161.07:58:13.34#ibcon#enter sib2, iclass 26, count 0 2006.161.07:58:13.34#ibcon#flushed, iclass 26, count 0 2006.161.07:58:13.34#ibcon#about to write, iclass 26, count 0 2006.161.07:58:13.34#ibcon#wrote, iclass 26, count 0 2006.161.07:58:13.34#ibcon#about to read 3, iclass 26, count 0 2006.161.07:58:13.37#ibcon#read 3, iclass 26, count 0 2006.161.07:58:13.37#ibcon#about to read 4, iclass 26, count 0 2006.161.07:58:13.37#ibcon#read 4, iclass 26, count 0 2006.161.07:58:13.37#ibcon#about to read 5, iclass 26, count 0 2006.161.07:58:13.37#ibcon#read 5, iclass 26, count 0 2006.161.07:58:13.37#ibcon#about to read 6, iclass 26, count 0 2006.161.07:58:13.37#ibcon#read 6, iclass 26, count 0 2006.161.07:58:13.37#ibcon#end of sib2, iclass 26, count 0 2006.161.07:58:13.37#ibcon#*after write, iclass 26, count 0 2006.161.07:58:13.37#ibcon#*before return 0, iclass 26, count 0 2006.161.07:58:13.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:13.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.07:58:13.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.07:58:13.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.07:58:13.37$vc4f8/vabw=wide 2006.161.07:58:13.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.07:58:13.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.07:58:13.37#ibcon#ireg 8 cls_cnt 0 2006.161.07:58:13.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:13.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:13.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:13.37#ibcon#enter wrdev, iclass 28, count 0 2006.161.07:58:13.37#ibcon#first serial, iclass 28, count 0 2006.161.07:58:13.37#ibcon#enter sib2, iclass 28, count 0 2006.161.07:58:13.37#ibcon#flushed, iclass 28, count 0 2006.161.07:58:13.37#ibcon#about to write, iclass 28, count 0 2006.161.07:58:13.37#ibcon#wrote, iclass 28, count 0 2006.161.07:58:13.37#ibcon#about to read 3, iclass 28, count 0 2006.161.07:58:13.39#ibcon#read 3, iclass 28, count 0 2006.161.07:58:13.39#ibcon#about to read 4, iclass 28, count 0 2006.161.07:58:13.39#ibcon#read 4, iclass 28, count 0 2006.161.07:58:13.39#ibcon#about to read 5, iclass 28, count 0 2006.161.07:58:13.39#ibcon#read 5, iclass 28, count 0 2006.161.07:58:13.39#ibcon#about to read 6, iclass 28, count 0 2006.161.07:58:13.39#ibcon#read 6, iclass 28, count 0 2006.161.07:58:13.39#ibcon#end of sib2, iclass 28, count 0 2006.161.07:58:13.39#ibcon#*mode == 0, iclass 28, count 0 2006.161.07:58:13.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.07:58:13.39#ibcon#[25=BW32\r\n] 2006.161.07:58:13.39#ibcon#*before write, iclass 28, count 0 2006.161.07:58:13.39#ibcon#enter sib2, iclass 28, count 0 2006.161.07:58:13.39#ibcon#flushed, iclass 28, count 0 2006.161.07:58:13.39#ibcon#about to write, iclass 28, count 0 2006.161.07:58:13.39#ibcon#wrote, iclass 28, count 0 2006.161.07:58:13.39#ibcon#about to read 3, iclass 28, count 0 2006.161.07:58:13.42#ibcon#read 3, iclass 28, count 0 2006.161.07:58:13.42#ibcon#about to read 4, iclass 28, count 0 2006.161.07:58:13.42#ibcon#read 4, iclass 28, count 0 2006.161.07:58:13.42#ibcon#about to read 5, iclass 28, count 0 2006.161.07:58:13.42#ibcon#read 5, iclass 28, count 0 2006.161.07:58:13.42#ibcon#about to read 6, iclass 28, count 0 2006.161.07:58:13.42#ibcon#read 6, iclass 28, count 0 2006.161.07:58:13.42#ibcon#end of sib2, iclass 28, count 0 2006.161.07:58:13.42#ibcon#*after write, iclass 28, count 0 2006.161.07:58:13.42#ibcon#*before return 0, iclass 28, count 0 2006.161.07:58:13.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:13.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.07:58:13.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.07:58:13.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.07:58:13.42$vc4f8/vbbw=wide 2006.161.07:58:13.42#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.07:58:13.42#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.07:58:13.42#ibcon#ireg 8 cls_cnt 0 2006.161.07:58:13.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:58:13.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:58:13.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:58:13.49#ibcon#enter wrdev, iclass 30, count 0 2006.161.07:58:13.49#ibcon#first serial, iclass 30, count 0 2006.161.07:58:13.49#ibcon#enter sib2, iclass 30, count 0 2006.161.07:58:13.49#ibcon#flushed, iclass 30, count 0 2006.161.07:58:13.49#ibcon#about to write, iclass 30, count 0 2006.161.07:58:13.49#ibcon#wrote, iclass 30, count 0 2006.161.07:58:13.49#ibcon#about to read 3, iclass 30, count 0 2006.161.07:58:13.51#ibcon#read 3, iclass 30, count 0 2006.161.07:58:13.51#ibcon#about to read 4, iclass 30, count 0 2006.161.07:58:13.51#ibcon#read 4, iclass 30, count 0 2006.161.07:58:13.51#ibcon#about to read 5, iclass 30, count 0 2006.161.07:58:13.51#ibcon#read 5, iclass 30, count 0 2006.161.07:58:13.51#ibcon#about to read 6, iclass 30, count 0 2006.161.07:58:13.51#ibcon#read 6, iclass 30, count 0 2006.161.07:58:13.51#ibcon#end of sib2, iclass 30, count 0 2006.161.07:58:13.51#ibcon#*mode == 0, iclass 30, count 0 2006.161.07:58:13.51#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.07:58:13.51#ibcon#[27=BW32\r\n] 2006.161.07:58:13.51#ibcon#*before write, iclass 30, count 0 2006.161.07:58:13.51#ibcon#enter sib2, iclass 30, count 0 2006.161.07:58:13.51#ibcon#flushed, iclass 30, count 0 2006.161.07:58:13.51#ibcon#about to write, iclass 30, count 0 2006.161.07:58:13.51#ibcon#wrote, iclass 30, count 0 2006.161.07:58:13.51#ibcon#about to read 3, iclass 30, count 0 2006.161.07:58:13.54#ibcon#read 3, iclass 30, count 0 2006.161.07:58:13.54#ibcon#about to read 4, iclass 30, count 0 2006.161.07:58:13.54#ibcon#read 4, iclass 30, count 0 2006.161.07:58:13.54#ibcon#about to read 5, iclass 30, count 0 2006.161.07:58:13.54#ibcon#read 5, iclass 30, count 0 2006.161.07:58:13.54#ibcon#about to read 6, iclass 30, count 0 2006.161.07:58:13.54#ibcon#read 6, iclass 30, count 0 2006.161.07:58:13.54#ibcon#end of sib2, iclass 30, count 0 2006.161.07:58:13.54#ibcon#*after write, iclass 30, count 0 2006.161.07:58:13.54#ibcon#*before return 0, iclass 30, count 0 2006.161.07:58:13.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:58:13.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.07:58:13.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.07:58:13.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.07:58:13.54$4f8m12a/ifd4f 2006.161.07:58:13.54$ifd4f/lo= 2006.161.07:58:13.54$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.07:58:13.54$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.07:58:13.54$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.07:58:13.54$ifd4f/patch= 2006.161.07:58:13.54$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.07:58:13.54$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.07:58:13.54$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.07:58:13.54$4f8m12a/"form=m,16.000,1:2 2006.161.07:58:13.54$4f8m12a/"tpicd 2006.161.07:58:13.54$4f8m12a/echo=off 2006.161.07:58:13.54$4f8m12a/xlog=off 2006.161.07:58:13.54:!2006.161.07:58:50 2006.161.07:58:32.14#trakl#Source acquired 2006.161.07:58:34.14#flagr#flagr/antenna,acquired 2006.161.07:58:50.00:preob 2006.161.07:58:50.14/onsource/TRACKING 2006.161.07:58:50.14:!2006.161.07:59:00 2006.161.07:59:00.00:data_valid=on 2006.161.07:59:00.00:midob 2006.161.07:59:01.14/onsource/TRACKING 2006.161.07:59:01.14/wx/24.03,1002.2,86 2006.161.07:59:01.20/cable/+6.4993E-03 2006.161.07:59:02.29/va/01,08,usb,yes,31,33 2006.161.07:59:02.29/va/02,07,usb,yes,31,32 2006.161.07:59:02.29/va/03,06,usb,yes,33,33 2006.161.07:59:02.29/va/04,07,usb,yes,32,34 2006.161.07:59:02.29/va/05,07,usb,yes,32,34 2006.161.07:59:02.29/va/06,06,usb,yes,32,31 2006.161.07:59:02.29/va/07,06,usb,yes,32,32 2006.161.07:59:02.29/va/08,07,usb,yes,30,30 2006.161.07:59:02.52/valo/01,532.99,yes,locked 2006.161.07:59:02.52/valo/02,572.99,yes,locked 2006.161.07:59:02.52/valo/03,672.99,yes,locked 2006.161.07:59:02.52/valo/04,832.99,yes,locked 2006.161.07:59:02.52/valo/05,652.99,yes,locked 2006.161.07:59:02.52/valo/06,772.99,yes,locked 2006.161.07:59:02.52/valo/07,832.99,yes,locked 2006.161.07:59:02.52/valo/08,852.99,yes,locked 2006.161.07:59:03.61/vb/01,04,usb,yes,30,28 2006.161.07:59:03.61/vb/02,04,usb,yes,32,33 2006.161.07:59:03.61/vb/03,04,usb,yes,28,32 2006.161.07:59:03.61/vb/04,04,usb,yes,29,29 2006.161.07:59:03.61/vb/05,04,usb,yes,27,31 2006.161.07:59:03.61/vb/06,04,usb,yes,29,31 2006.161.07:59:03.61/vb/07,04,usb,yes,31,30 2006.161.07:59:03.61/vb/08,04,usb,yes,28,31 2006.161.07:59:03.84/vblo/01,632.99,yes,locked 2006.161.07:59:03.84/vblo/02,640.99,yes,locked 2006.161.07:59:03.84/vblo/03,656.99,yes,locked 2006.161.07:59:03.84/vblo/04,712.99,yes,locked 2006.161.07:59:03.84/vblo/05,744.99,yes,locked 2006.161.07:59:03.84/vblo/06,752.99,yes,locked 2006.161.07:59:03.84/vblo/07,734.99,yes,locked 2006.161.07:59:03.84/vblo/08,744.99,yes,locked 2006.161.07:59:03.99/vabw/8 2006.161.07:59:04.14/vbbw/8 2006.161.07:59:04.23/xfe/off,on,15.0 2006.161.07:59:04.62/ifatt/23,28,28,28 2006.161.07:59:05.08/fmout-gps/S +4.49E-07 2006.161.07:59:05.12:!2006.161.08:00:00 2006.161.08:00:00.02:data_valid=off 2006.161.08:00:00.02:postob 2006.161.08:00:00.18/cable/+6.4972E-03 2006.161.08:00:00.18/wx/24.03,1002.2,85 2006.161.08:00:01.08/fmout-gps/S +4.49E-07 2006.161.08:00:01.08:scan_name=161-0801,k06161,60 2006.161.08:00:01.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.161.08:00:01.15#flagr#flagr/antenna,new-source 2006.161.08:00:02.15:checkk5 2006.161.08:00:02.59/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:00:03.07/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:00:03.48/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:00:03.92/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:00:04.33/chk_obsdata//k5ts1/T1610759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:00:05.00/chk_obsdata//k5ts2/T1610759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:00:05.40/chk_obsdata//k5ts3/T1610759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:00:05.85/chk_obsdata//k5ts4/T1610759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:00:06.88/k5log//k5ts1_log_newline 2006.161.08:00:07.64/k5log//k5ts2_log_newline 2006.161.08:00:08.49/k5log//k5ts3_log_newline 2006.161.08:00:09.27/k5log//k5ts4_log_newline 2006.161.08:00:09.29/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:00:09.29:4f8m12a=2 2006.161.08:00:09.29$4f8m12a/echo=on 2006.161.08:00:09.29$4f8m12a/pcalon 2006.161.08:00:09.29$pcalon/"no phase cal control is implemented here 2006.161.08:00:09.29$4f8m12a/"tpicd=stop 2006.161.08:00:09.29$4f8m12a/vc4f8 2006.161.08:00:09.29$vc4f8/valo=1,532.99 2006.161.08:00:09.30#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:00:09.30#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:00:09.30#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:09.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:09.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:09.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:09.30#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:00:09.30#ibcon#first serial, iclass 7, count 0 2006.161.08:00:09.30#ibcon#enter sib2, iclass 7, count 0 2006.161.08:00:09.30#ibcon#flushed, iclass 7, count 0 2006.161.08:00:09.30#ibcon#about to write, iclass 7, count 0 2006.161.08:00:09.30#ibcon#wrote, iclass 7, count 0 2006.161.08:00:09.30#ibcon#about to read 3, iclass 7, count 0 2006.161.08:00:09.34#ibcon#read 3, iclass 7, count 0 2006.161.08:00:09.34#ibcon#about to read 4, iclass 7, count 0 2006.161.08:00:09.34#ibcon#read 4, iclass 7, count 0 2006.161.08:00:09.34#ibcon#about to read 5, iclass 7, count 0 2006.161.08:00:09.34#ibcon#read 5, iclass 7, count 0 2006.161.08:00:09.34#ibcon#about to read 6, iclass 7, count 0 2006.161.08:00:09.34#ibcon#read 6, iclass 7, count 0 2006.161.08:00:09.34#ibcon#end of sib2, iclass 7, count 0 2006.161.08:00:09.34#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:00:09.34#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:00:09.34#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:00:09.34#ibcon#*before write, iclass 7, count 0 2006.161.08:00:09.34#ibcon#enter sib2, iclass 7, count 0 2006.161.08:00:09.34#ibcon#flushed, iclass 7, count 0 2006.161.08:00:09.34#ibcon#about to write, iclass 7, count 0 2006.161.08:00:09.34#ibcon#wrote, iclass 7, count 0 2006.161.08:00:09.34#ibcon#about to read 3, iclass 7, count 0 2006.161.08:00:09.38#ibcon#read 3, iclass 7, count 0 2006.161.08:00:09.38#ibcon#about to read 4, iclass 7, count 0 2006.161.08:00:09.38#ibcon#read 4, iclass 7, count 0 2006.161.08:00:09.38#ibcon#about to read 5, iclass 7, count 0 2006.161.08:00:09.38#ibcon#read 5, iclass 7, count 0 2006.161.08:00:09.38#ibcon#about to read 6, iclass 7, count 0 2006.161.08:00:09.38#ibcon#read 6, iclass 7, count 0 2006.161.08:00:09.38#ibcon#end of sib2, iclass 7, count 0 2006.161.08:00:09.38#ibcon#*after write, iclass 7, count 0 2006.161.08:00:09.38#ibcon#*before return 0, iclass 7, count 0 2006.161.08:00:09.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:09.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:09.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:00:09.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:00:09.39$vc4f8/va=1,8 2006.161.08:00:09.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:00:09.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:00:09.39#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:09.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:09.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:09.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:09.39#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:00:09.39#ibcon#first serial, iclass 11, count 2 2006.161.08:00:09.39#ibcon#enter sib2, iclass 11, count 2 2006.161.08:00:09.39#ibcon#flushed, iclass 11, count 2 2006.161.08:00:09.39#ibcon#about to write, iclass 11, count 2 2006.161.08:00:09.39#ibcon#wrote, iclass 11, count 2 2006.161.08:00:09.39#ibcon#about to read 3, iclass 11, count 2 2006.161.08:00:09.41#ibcon#read 3, iclass 11, count 2 2006.161.08:00:09.41#ibcon#about to read 4, iclass 11, count 2 2006.161.08:00:09.41#ibcon#read 4, iclass 11, count 2 2006.161.08:00:09.41#ibcon#about to read 5, iclass 11, count 2 2006.161.08:00:09.41#ibcon#read 5, iclass 11, count 2 2006.161.08:00:09.41#ibcon#about to read 6, iclass 11, count 2 2006.161.08:00:09.41#ibcon#read 6, iclass 11, count 2 2006.161.08:00:09.41#ibcon#end of sib2, iclass 11, count 2 2006.161.08:00:09.41#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:00:09.41#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:00:09.41#ibcon#[25=AT01-08\r\n] 2006.161.08:00:09.41#ibcon#*before write, iclass 11, count 2 2006.161.08:00:09.41#ibcon#enter sib2, iclass 11, count 2 2006.161.08:00:09.41#ibcon#flushed, iclass 11, count 2 2006.161.08:00:09.41#ibcon#about to write, iclass 11, count 2 2006.161.08:00:09.41#ibcon#wrote, iclass 11, count 2 2006.161.08:00:09.41#ibcon#about to read 3, iclass 11, count 2 2006.161.08:00:09.43#ibcon#read 3, iclass 11, count 2 2006.161.08:00:09.43#ibcon#about to read 4, iclass 11, count 2 2006.161.08:00:09.43#ibcon#read 4, iclass 11, count 2 2006.161.08:00:09.43#ibcon#about to read 5, iclass 11, count 2 2006.161.08:00:09.43#ibcon#read 5, iclass 11, count 2 2006.161.08:00:09.43#ibcon#about to read 6, iclass 11, count 2 2006.161.08:00:09.43#ibcon#read 6, iclass 11, count 2 2006.161.08:00:09.43#ibcon#end of sib2, iclass 11, count 2 2006.161.08:00:09.44#ibcon#*after write, iclass 11, count 2 2006.161.08:00:09.44#ibcon#*before return 0, iclass 11, count 2 2006.161.08:00:09.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:09.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:09.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:00:09.44#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:09.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:09.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:09.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:09.55#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:00:09.55#ibcon#first serial, iclass 11, count 0 2006.161.08:00:09.55#ibcon#enter sib2, iclass 11, count 0 2006.161.08:00:09.55#ibcon#flushed, iclass 11, count 0 2006.161.08:00:09.55#ibcon#about to write, iclass 11, count 0 2006.161.08:00:09.55#ibcon#wrote, iclass 11, count 0 2006.161.08:00:09.55#ibcon#about to read 3, iclass 11, count 0 2006.161.08:00:09.57#ibcon#read 3, iclass 11, count 0 2006.161.08:00:09.57#ibcon#about to read 4, iclass 11, count 0 2006.161.08:00:09.57#ibcon#read 4, iclass 11, count 0 2006.161.08:00:09.57#ibcon#about to read 5, iclass 11, count 0 2006.161.08:00:09.57#ibcon#read 5, iclass 11, count 0 2006.161.08:00:09.57#ibcon#about to read 6, iclass 11, count 0 2006.161.08:00:09.57#ibcon#read 6, iclass 11, count 0 2006.161.08:00:09.57#ibcon#end of sib2, iclass 11, count 0 2006.161.08:00:09.57#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:00:09.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:00:09.57#ibcon#[25=USB\r\n] 2006.161.08:00:09.58#ibcon#*before write, iclass 11, count 0 2006.161.08:00:09.58#ibcon#enter sib2, iclass 11, count 0 2006.161.08:00:09.58#ibcon#flushed, iclass 11, count 0 2006.161.08:00:09.58#ibcon#about to write, iclass 11, count 0 2006.161.08:00:09.58#ibcon#wrote, iclass 11, count 0 2006.161.08:00:09.58#ibcon#about to read 3, iclass 11, count 0 2006.161.08:00:09.60#ibcon#read 3, iclass 11, count 0 2006.161.08:00:09.60#ibcon#about to read 4, iclass 11, count 0 2006.161.08:00:09.60#ibcon#read 4, iclass 11, count 0 2006.161.08:00:09.60#ibcon#about to read 5, iclass 11, count 0 2006.161.08:00:09.60#ibcon#read 5, iclass 11, count 0 2006.161.08:00:09.60#ibcon#about to read 6, iclass 11, count 0 2006.161.08:00:09.60#ibcon#read 6, iclass 11, count 0 2006.161.08:00:09.60#ibcon#end of sib2, iclass 11, count 0 2006.161.08:00:09.60#ibcon#*after write, iclass 11, count 0 2006.161.08:00:09.60#ibcon#*before return 0, iclass 11, count 0 2006.161.08:00:09.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:09.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:09.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:00:09.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:00:09.61$vc4f8/valo=2,572.99 2006.161.08:00:09.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:00:09.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:00:09.61#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:09.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:09.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:09.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:09.61#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:00:09.61#ibcon#first serial, iclass 13, count 0 2006.161.08:00:09.61#ibcon#enter sib2, iclass 13, count 0 2006.161.08:00:09.61#ibcon#flushed, iclass 13, count 0 2006.161.08:00:09.61#ibcon#about to write, iclass 13, count 0 2006.161.08:00:09.61#ibcon#wrote, iclass 13, count 0 2006.161.08:00:09.61#ibcon#about to read 3, iclass 13, count 0 2006.161.08:00:09.62#ibcon#read 3, iclass 13, count 0 2006.161.08:00:09.62#ibcon#about to read 4, iclass 13, count 0 2006.161.08:00:09.62#ibcon#read 4, iclass 13, count 0 2006.161.08:00:09.62#ibcon#about to read 5, iclass 13, count 0 2006.161.08:00:09.62#ibcon#read 5, iclass 13, count 0 2006.161.08:00:09.62#ibcon#about to read 6, iclass 13, count 0 2006.161.08:00:09.62#ibcon#read 6, iclass 13, count 0 2006.161.08:00:09.62#ibcon#end of sib2, iclass 13, count 0 2006.161.08:00:09.63#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:00:09.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:00:09.63#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:00:09.63#ibcon#*before write, iclass 13, count 0 2006.161.08:00:09.63#ibcon#enter sib2, iclass 13, count 0 2006.161.08:00:09.63#ibcon#flushed, iclass 13, count 0 2006.161.08:00:09.63#ibcon#about to write, iclass 13, count 0 2006.161.08:00:09.63#ibcon#wrote, iclass 13, count 0 2006.161.08:00:09.63#ibcon#about to read 3, iclass 13, count 0 2006.161.08:00:09.67#ibcon#read 3, iclass 13, count 0 2006.161.08:00:09.67#ibcon#about to read 4, iclass 13, count 0 2006.161.08:00:09.67#ibcon#read 4, iclass 13, count 0 2006.161.08:00:09.67#ibcon#about to read 5, iclass 13, count 0 2006.161.08:00:09.67#ibcon#read 5, iclass 13, count 0 2006.161.08:00:09.67#ibcon#about to read 6, iclass 13, count 0 2006.161.08:00:09.67#ibcon#read 6, iclass 13, count 0 2006.161.08:00:09.67#ibcon#end of sib2, iclass 13, count 0 2006.161.08:00:09.67#ibcon#*after write, iclass 13, count 0 2006.161.08:00:09.67#ibcon#*before return 0, iclass 13, count 0 2006.161.08:00:09.67#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:09.67#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:09.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:00:09.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:00:09.67$vc4f8/va=2,7 2006.161.08:00:09.67#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:00:09.67#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:00:09.67#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:09.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:09.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:09.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:09.72#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:00:09.72#ibcon#first serial, iclass 15, count 2 2006.161.08:00:09.72#ibcon#enter sib2, iclass 15, count 2 2006.161.08:00:09.72#ibcon#flushed, iclass 15, count 2 2006.161.08:00:09.72#ibcon#about to write, iclass 15, count 2 2006.161.08:00:09.72#ibcon#wrote, iclass 15, count 2 2006.161.08:00:09.72#ibcon#about to read 3, iclass 15, count 2 2006.161.08:00:09.75#ibcon#read 3, iclass 15, count 2 2006.161.08:00:09.75#ibcon#about to read 4, iclass 15, count 2 2006.161.08:00:09.75#ibcon#read 4, iclass 15, count 2 2006.161.08:00:09.75#ibcon#about to read 5, iclass 15, count 2 2006.161.08:00:09.75#ibcon#read 5, iclass 15, count 2 2006.161.08:00:09.75#ibcon#about to read 6, iclass 15, count 2 2006.161.08:00:09.75#ibcon#read 6, iclass 15, count 2 2006.161.08:00:09.75#ibcon#end of sib2, iclass 15, count 2 2006.161.08:00:09.75#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:00:09.75#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:00:09.75#ibcon#[25=AT02-07\r\n] 2006.161.08:00:09.75#ibcon#*before write, iclass 15, count 2 2006.161.08:00:09.75#ibcon#enter sib2, iclass 15, count 2 2006.161.08:00:09.75#ibcon#flushed, iclass 15, count 2 2006.161.08:00:09.75#ibcon#about to write, iclass 15, count 2 2006.161.08:00:09.75#ibcon#wrote, iclass 15, count 2 2006.161.08:00:09.75#ibcon#about to read 3, iclass 15, count 2 2006.161.08:00:09.78#ibcon#read 3, iclass 15, count 2 2006.161.08:00:09.78#ibcon#about to read 4, iclass 15, count 2 2006.161.08:00:09.78#ibcon#read 4, iclass 15, count 2 2006.161.08:00:09.78#ibcon#about to read 5, iclass 15, count 2 2006.161.08:00:09.78#ibcon#read 5, iclass 15, count 2 2006.161.08:00:09.78#ibcon#about to read 6, iclass 15, count 2 2006.161.08:00:09.78#ibcon#read 6, iclass 15, count 2 2006.161.08:00:09.79#ibcon#end of sib2, iclass 15, count 2 2006.161.08:00:09.79#ibcon#*after write, iclass 15, count 2 2006.161.08:00:09.79#ibcon#*before return 0, iclass 15, count 2 2006.161.08:00:09.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:09.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:09.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:00:09.79#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:09.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:09.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:09.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:09.90#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:00:09.90#ibcon#first serial, iclass 15, count 0 2006.161.08:00:09.90#ibcon#enter sib2, iclass 15, count 0 2006.161.08:00:09.90#ibcon#flushed, iclass 15, count 0 2006.161.08:00:09.90#ibcon#about to write, iclass 15, count 0 2006.161.08:00:09.90#ibcon#wrote, iclass 15, count 0 2006.161.08:00:09.90#ibcon#about to read 3, iclass 15, count 0 2006.161.08:00:09.92#ibcon#read 3, iclass 15, count 0 2006.161.08:00:09.92#ibcon#about to read 4, iclass 15, count 0 2006.161.08:00:09.92#ibcon#read 4, iclass 15, count 0 2006.161.08:00:09.92#ibcon#about to read 5, iclass 15, count 0 2006.161.08:00:09.92#ibcon#read 5, iclass 15, count 0 2006.161.08:00:09.92#ibcon#about to read 6, iclass 15, count 0 2006.161.08:00:09.92#ibcon#read 6, iclass 15, count 0 2006.161.08:00:09.92#ibcon#end of sib2, iclass 15, count 0 2006.161.08:00:09.92#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:00:09.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:00:09.92#ibcon#[25=USB\r\n] 2006.161.08:00:09.93#ibcon#*before write, iclass 15, count 0 2006.161.08:00:09.93#ibcon#enter sib2, iclass 15, count 0 2006.161.08:00:09.93#ibcon#flushed, iclass 15, count 0 2006.161.08:00:09.93#ibcon#about to write, iclass 15, count 0 2006.161.08:00:09.93#ibcon#wrote, iclass 15, count 0 2006.161.08:00:09.93#ibcon#about to read 3, iclass 15, count 0 2006.161.08:00:09.95#ibcon#read 3, iclass 15, count 0 2006.161.08:00:09.95#ibcon#about to read 4, iclass 15, count 0 2006.161.08:00:09.95#ibcon#read 4, iclass 15, count 0 2006.161.08:00:09.95#ibcon#about to read 5, iclass 15, count 0 2006.161.08:00:09.95#ibcon#read 5, iclass 15, count 0 2006.161.08:00:09.95#ibcon#about to read 6, iclass 15, count 0 2006.161.08:00:09.95#ibcon#read 6, iclass 15, count 0 2006.161.08:00:09.95#ibcon#end of sib2, iclass 15, count 0 2006.161.08:00:09.95#ibcon#*after write, iclass 15, count 0 2006.161.08:00:09.95#ibcon#*before return 0, iclass 15, count 0 2006.161.08:00:09.96#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:09.96#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:09.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:00:09.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:00:09.96$vc4f8/valo=3,672.99 2006.161.08:00:09.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:00:09.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:00:09.96#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:09.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:09.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:09.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:09.96#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:00:09.96#ibcon#first serial, iclass 17, count 0 2006.161.08:00:09.96#ibcon#enter sib2, iclass 17, count 0 2006.161.08:00:09.96#ibcon#flushed, iclass 17, count 0 2006.161.08:00:09.96#ibcon#about to write, iclass 17, count 0 2006.161.08:00:09.96#ibcon#wrote, iclass 17, count 0 2006.161.08:00:09.96#ibcon#about to read 3, iclass 17, count 0 2006.161.08:00:09.97#ibcon#read 3, iclass 17, count 0 2006.161.08:00:09.97#ibcon#about to read 4, iclass 17, count 0 2006.161.08:00:09.97#ibcon#read 4, iclass 17, count 0 2006.161.08:00:09.97#ibcon#about to read 5, iclass 17, count 0 2006.161.08:00:09.97#ibcon#read 5, iclass 17, count 0 2006.161.08:00:09.97#ibcon#about to read 6, iclass 17, count 0 2006.161.08:00:09.97#ibcon#read 6, iclass 17, count 0 2006.161.08:00:09.98#ibcon#end of sib2, iclass 17, count 0 2006.161.08:00:09.98#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:00:09.98#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:00:09.98#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:00:09.98#ibcon#*before write, iclass 17, count 0 2006.161.08:00:09.98#ibcon#enter sib2, iclass 17, count 0 2006.161.08:00:09.98#ibcon#flushed, iclass 17, count 0 2006.161.08:00:09.98#ibcon#about to write, iclass 17, count 0 2006.161.08:00:09.98#ibcon#wrote, iclass 17, count 0 2006.161.08:00:09.98#ibcon#about to read 3, iclass 17, count 0 2006.161.08:00:10.02#ibcon#read 3, iclass 17, count 0 2006.161.08:00:10.02#ibcon#about to read 4, iclass 17, count 0 2006.161.08:00:10.02#ibcon#read 4, iclass 17, count 0 2006.161.08:00:10.02#ibcon#about to read 5, iclass 17, count 0 2006.161.08:00:10.02#ibcon#read 5, iclass 17, count 0 2006.161.08:00:10.02#ibcon#about to read 6, iclass 17, count 0 2006.161.08:00:10.02#ibcon#read 6, iclass 17, count 0 2006.161.08:00:10.02#ibcon#end of sib2, iclass 17, count 0 2006.161.08:00:10.02#ibcon#*after write, iclass 17, count 0 2006.161.08:00:10.02#ibcon#*before return 0, iclass 17, count 0 2006.161.08:00:10.02#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:10.02#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:10.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:00:10.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:00:10.02$vc4f8/va=3,6 2006.161.08:00:10.02#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:00:10.02#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:00:10.02#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:10.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:10.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:10.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:10.07#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:00:10.07#ibcon#first serial, iclass 19, count 2 2006.161.08:00:10.07#ibcon#enter sib2, iclass 19, count 2 2006.161.08:00:10.07#ibcon#flushed, iclass 19, count 2 2006.161.08:00:10.07#ibcon#about to write, iclass 19, count 2 2006.161.08:00:10.07#ibcon#wrote, iclass 19, count 2 2006.161.08:00:10.07#ibcon#about to read 3, iclass 19, count 2 2006.161.08:00:10.09#ibcon#read 3, iclass 19, count 2 2006.161.08:00:10.09#ibcon#about to read 4, iclass 19, count 2 2006.161.08:00:10.09#ibcon#read 4, iclass 19, count 2 2006.161.08:00:10.10#ibcon#about to read 5, iclass 19, count 2 2006.161.08:00:10.10#ibcon#read 5, iclass 19, count 2 2006.161.08:00:10.10#ibcon#about to read 6, iclass 19, count 2 2006.161.08:00:10.10#ibcon#read 6, iclass 19, count 2 2006.161.08:00:10.10#ibcon#end of sib2, iclass 19, count 2 2006.161.08:00:10.10#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:00:10.10#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:00:10.10#ibcon#[25=AT03-06\r\n] 2006.161.08:00:10.10#ibcon#*before write, iclass 19, count 2 2006.161.08:00:10.10#ibcon#enter sib2, iclass 19, count 2 2006.161.08:00:10.10#ibcon#flushed, iclass 19, count 2 2006.161.08:00:10.10#ibcon#about to write, iclass 19, count 2 2006.161.08:00:10.10#ibcon#wrote, iclass 19, count 2 2006.161.08:00:10.10#ibcon#about to read 3, iclass 19, count 2 2006.161.08:00:10.12#ibcon#read 3, iclass 19, count 2 2006.161.08:00:10.12#ibcon#about to read 4, iclass 19, count 2 2006.161.08:00:10.12#ibcon#read 4, iclass 19, count 2 2006.161.08:00:10.12#ibcon#about to read 5, iclass 19, count 2 2006.161.08:00:10.12#ibcon#read 5, iclass 19, count 2 2006.161.08:00:10.12#ibcon#about to read 6, iclass 19, count 2 2006.161.08:00:10.12#ibcon#read 6, iclass 19, count 2 2006.161.08:00:10.12#ibcon#end of sib2, iclass 19, count 2 2006.161.08:00:10.12#ibcon#*after write, iclass 19, count 2 2006.161.08:00:10.12#ibcon#*before return 0, iclass 19, count 2 2006.161.08:00:10.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:10.13#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:10.13#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:00:10.13#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:10.13#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:10.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:10.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:10.24#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:00:10.24#ibcon#first serial, iclass 19, count 0 2006.161.08:00:10.24#ibcon#enter sib2, iclass 19, count 0 2006.161.08:00:10.24#ibcon#flushed, iclass 19, count 0 2006.161.08:00:10.24#ibcon#about to write, iclass 19, count 0 2006.161.08:00:10.24#ibcon#wrote, iclass 19, count 0 2006.161.08:00:10.24#ibcon#about to read 3, iclass 19, count 0 2006.161.08:00:10.26#ibcon#read 3, iclass 19, count 0 2006.161.08:00:10.26#ibcon#about to read 4, iclass 19, count 0 2006.161.08:00:10.26#ibcon#read 4, iclass 19, count 0 2006.161.08:00:10.26#ibcon#about to read 5, iclass 19, count 0 2006.161.08:00:10.26#ibcon#read 5, iclass 19, count 0 2006.161.08:00:10.26#ibcon#about to read 6, iclass 19, count 0 2006.161.08:00:10.26#ibcon#read 6, iclass 19, count 0 2006.161.08:00:10.26#ibcon#end of sib2, iclass 19, count 0 2006.161.08:00:10.26#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:00:10.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:00:10.26#ibcon#[25=USB\r\n] 2006.161.08:00:10.27#ibcon#*before write, iclass 19, count 0 2006.161.08:00:10.27#ibcon#enter sib2, iclass 19, count 0 2006.161.08:00:10.27#ibcon#flushed, iclass 19, count 0 2006.161.08:00:10.27#ibcon#about to write, iclass 19, count 0 2006.161.08:00:10.27#ibcon#wrote, iclass 19, count 0 2006.161.08:00:10.27#ibcon#about to read 3, iclass 19, count 0 2006.161.08:00:10.29#ibcon#read 3, iclass 19, count 0 2006.161.08:00:10.29#ibcon#about to read 4, iclass 19, count 0 2006.161.08:00:10.29#ibcon#read 4, iclass 19, count 0 2006.161.08:00:10.29#ibcon#about to read 5, iclass 19, count 0 2006.161.08:00:10.29#ibcon#read 5, iclass 19, count 0 2006.161.08:00:10.29#ibcon#about to read 6, iclass 19, count 0 2006.161.08:00:10.29#ibcon#read 6, iclass 19, count 0 2006.161.08:00:10.29#ibcon#end of sib2, iclass 19, count 0 2006.161.08:00:10.29#ibcon#*after write, iclass 19, count 0 2006.161.08:00:10.29#ibcon#*before return 0, iclass 19, count 0 2006.161.08:00:10.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:10.30#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:10.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:00:10.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:00:10.30$vc4f8/valo=4,832.99 2006.161.08:00:10.30#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:00:10.30#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:00:10.30#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:10.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:10.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:10.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:10.30#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:00:10.30#ibcon#first serial, iclass 21, count 0 2006.161.08:00:10.30#ibcon#enter sib2, iclass 21, count 0 2006.161.08:00:10.30#ibcon#flushed, iclass 21, count 0 2006.161.08:00:10.30#ibcon#about to write, iclass 21, count 0 2006.161.08:00:10.30#ibcon#wrote, iclass 21, count 0 2006.161.08:00:10.30#ibcon#about to read 3, iclass 21, count 0 2006.161.08:00:10.31#ibcon#read 3, iclass 21, count 0 2006.161.08:00:10.31#ibcon#about to read 4, iclass 21, count 0 2006.161.08:00:10.31#ibcon#read 4, iclass 21, count 0 2006.161.08:00:10.31#ibcon#about to read 5, iclass 21, count 0 2006.161.08:00:10.31#ibcon#read 5, iclass 21, count 0 2006.161.08:00:10.31#ibcon#about to read 6, iclass 21, count 0 2006.161.08:00:10.31#ibcon#read 6, iclass 21, count 0 2006.161.08:00:10.31#ibcon#end of sib2, iclass 21, count 0 2006.161.08:00:10.31#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:00:10.31#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:00:10.31#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:00:10.31#ibcon#*before write, iclass 21, count 0 2006.161.08:00:10.32#ibcon#enter sib2, iclass 21, count 0 2006.161.08:00:10.32#ibcon#flushed, iclass 21, count 0 2006.161.08:00:10.32#ibcon#about to write, iclass 21, count 0 2006.161.08:00:10.32#ibcon#wrote, iclass 21, count 0 2006.161.08:00:10.32#ibcon#about to read 3, iclass 21, count 0 2006.161.08:00:10.35#ibcon#read 3, iclass 21, count 0 2006.161.08:00:10.35#ibcon#about to read 4, iclass 21, count 0 2006.161.08:00:10.35#ibcon#read 4, iclass 21, count 0 2006.161.08:00:10.35#ibcon#about to read 5, iclass 21, count 0 2006.161.08:00:10.35#ibcon#read 5, iclass 21, count 0 2006.161.08:00:10.35#ibcon#about to read 6, iclass 21, count 0 2006.161.08:00:10.35#ibcon#read 6, iclass 21, count 0 2006.161.08:00:10.35#ibcon#end of sib2, iclass 21, count 0 2006.161.08:00:10.35#ibcon#*after write, iclass 21, count 0 2006.161.08:00:10.35#ibcon#*before return 0, iclass 21, count 0 2006.161.08:00:10.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:10.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:10.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:00:10.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:00:10.36$vc4f8/va=4,7 2006.161.08:00:10.36#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:00:10.36#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:00:10.36#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:10.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:10.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:10.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:10.41#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:00:10.41#ibcon#first serial, iclass 23, count 2 2006.161.08:00:10.41#ibcon#enter sib2, iclass 23, count 2 2006.161.08:00:10.41#ibcon#flushed, iclass 23, count 2 2006.161.08:00:10.41#ibcon#about to write, iclass 23, count 2 2006.161.08:00:10.41#ibcon#wrote, iclass 23, count 2 2006.161.08:00:10.41#ibcon#about to read 3, iclass 23, count 2 2006.161.08:00:10.43#ibcon#read 3, iclass 23, count 2 2006.161.08:00:10.43#ibcon#about to read 4, iclass 23, count 2 2006.161.08:00:10.43#ibcon#read 4, iclass 23, count 2 2006.161.08:00:10.43#ibcon#about to read 5, iclass 23, count 2 2006.161.08:00:10.43#ibcon#read 5, iclass 23, count 2 2006.161.08:00:10.43#ibcon#about to read 6, iclass 23, count 2 2006.161.08:00:10.43#ibcon#read 6, iclass 23, count 2 2006.161.08:00:10.43#ibcon#end of sib2, iclass 23, count 2 2006.161.08:00:10.43#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:00:10.43#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:00:10.44#ibcon#[25=AT04-07\r\n] 2006.161.08:00:10.44#ibcon#*before write, iclass 23, count 2 2006.161.08:00:10.44#ibcon#enter sib2, iclass 23, count 2 2006.161.08:00:10.44#ibcon#flushed, iclass 23, count 2 2006.161.08:00:10.44#ibcon#about to write, iclass 23, count 2 2006.161.08:00:10.44#ibcon#wrote, iclass 23, count 2 2006.161.08:00:10.44#ibcon#about to read 3, iclass 23, count 2 2006.161.08:00:10.46#ibcon#read 3, iclass 23, count 2 2006.161.08:00:10.46#ibcon#about to read 4, iclass 23, count 2 2006.161.08:00:10.46#ibcon#read 4, iclass 23, count 2 2006.161.08:00:10.46#ibcon#about to read 5, iclass 23, count 2 2006.161.08:00:10.46#ibcon#read 5, iclass 23, count 2 2006.161.08:00:10.46#ibcon#about to read 6, iclass 23, count 2 2006.161.08:00:10.46#ibcon#read 6, iclass 23, count 2 2006.161.08:00:10.46#ibcon#end of sib2, iclass 23, count 2 2006.161.08:00:10.46#ibcon#*after write, iclass 23, count 2 2006.161.08:00:10.46#ibcon#*before return 0, iclass 23, count 2 2006.161.08:00:10.47#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:10.47#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:10.47#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:00:10.47#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:10.47#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:10.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:10.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:10.58#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:00:10.58#ibcon#first serial, iclass 23, count 0 2006.161.08:00:10.58#ibcon#enter sib2, iclass 23, count 0 2006.161.08:00:10.58#ibcon#flushed, iclass 23, count 0 2006.161.08:00:10.58#ibcon#about to write, iclass 23, count 0 2006.161.08:00:10.58#ibcon#wrote, iclass 23, count 0 2006.161.08:00:10.58#ibcon#about to read 3, iclass 23, count 0 2006.161.08:00:10.60#ibcon#read 3, iclass 23, count 0 2006.161.08:00:10.60#ibcon#about to read 4, iclass 23, count 0 2006.161.08:00:10.60#ibcon#read 4, iclass 23, count 0 2006.161.08:00:10.60#ibcon#about to read 5, iclass 23, count 0 2006.161.08:00:10.60#ibcon#read 5, iclass 23, count 0 2006.161.08:00:10.60#ibcon#about to read 6, iclass 23, count 0 2006.161.08:00:10.60#ibcon#read 6, iclass 23, count 0 2006.161.08:00:10.60#ibcon#end of sib2, iclass 23, count 0 2006.161.08:00:10.60#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:00:10.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:00:10.60#ibcon#[25=USB\r\n] 2006.161.08:00:10.61#ibcon#*before write, iclass 23, count 0 2006.161.08:00:10.61#ibcon#enter sib2, iclass 23, count 0 2006.161.08:00:10.61#ibcon#flushed, iclass 23, count 0 2006.161.08:00:10.61#ibcon#about to write, iclass 23, count 0 2006.161.08:00:10.61#ibcon#wrote, iclass 23, count 0 2006.161.08:00:10.61#ibcon#about to read 3, iclass 23, count 0 2006.161.08:00:10.63#ibcon#read 3, iclass 23, count 0 2006.161.08:00:10.63#ibcon#about to read 4, iclass 23, count 0 2006.161.08:00:10.63#ibcon#read 4, iclass 23, count 0 2006.161.08:00:10.63#ibcon#about to read 5, iclass 23, count 0 2006.161.08:00:10.63#ibcon#read 5, iclass 23, count 0 2006.161.08:00:10.63#ibcon#about to read 6, iclass 23, count 0 2006.161.08:00:10.63#ibcon#read 6, iclass 23, count 0 2006.161.08:00:10.63#ibcon#end of sib2, iclass 23, count 0 2006.161.08:00:10.63#ibcon#*after write, iclass 23, count 0 2006.161.08:00:10.63#ibcon#*before return 0, iclass 23, count 0 2006.161.08:00:10.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:10.64#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:10.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:00:10.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:00:10.64$vc4f8/valo=5,652.99 2006.161.08:00:10.64#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:00:10.64#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:00:10.64#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:10.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:10.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:10.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:10.64#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:00:10.64#ibcon#first serial, iclass 25, count 0 2006.161.08:00:10.64#ibcon#enter sib2, iclass 25, count 0 2006.161.08:00:10.64#ibcon#flushed, iclass 25, count 0 2006.161.08:00:10.64#ibcon#about to write, iclass 25, count 0 2006.161.08:00:10.64#ibcon#wrote, iclass 25, count 0 2006.161.08:00:10.64#ibcon#about to read 3, iclass 25, count 0 2006.161.08:00:10.65#ibcon#read 3, iclass 25, count 0 2006.161.08:00:10.65#ibcon#about to read 4, iclass 25, count 0 2006.161.08:00:10.65#ibcon#read 4, iclass 25, count 0 2006.161.08:00:10.65#ibcon#about to read 5, iclass 25, count 0 2006.161.08:00:10.65#ibcon#read 5, iclass 25, count 0 2006.161.08:00:10.65#ibcon#about to read 6, iclass 25, count 0 2006.161.08:00:10.65#ibcon#read 6, iclass 25, count 0 2006.161.08:00:10.65#ibcon#end of sib2, iclass 25, count 0 2006.161.08:00:10.65#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:00:10.65#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:00:10.65#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:00:10.66#ibcon#*before write, iclass 25, count 0 2006.161.08:00:10.66#ibcon#enter sib2, iclass 25, count 0 2006.161.08:00:10.66#ibcon#flushed, iclass 25, count 0 2006.161.08:00:10.66#ibcon#about to write, iclass 25, count 0 2006.161.08:00:10.66#ibcon#wrote, iclass 25, count 0 2006.161.08:00:10.66#ibcon#about to read 3, iclass 25, count 0 2006.161.08:00:10.69#ibcon#read 3, iclass 25, count 0 2006.161.08:00:10.69#ibcon#about to read 4, iclass 25, count 0 2006.161.08:00:10.69#ibcon#read 4, iclass 25, count 0 2006.161.08:00:10.69#ibcon#about to read 5, iclass 25, count 0 2006.161.08:00:10.69#ibcon#read 5, iclass 25, count 0 2006.161.08:00:10.69#ibcon#about to read 6, iclass 25, count 0 2006.161.08:00:10.69#ibcon#read 6, iclass 25, count 0 2006.161.08:00:10.69#ibcon#end of sib2, iclass 25, count 0 2006.161.08:00:10.69#ibcon#*after write, iclass 25, count 0 2006.161.08:00:10.69#ibcon#*before return 0, iclass 25, count 0 2006.161.08:00:10.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:10.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:10.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:00:10.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:00:10.70$vc4f8/va=5,7 2006.161.08:00:10.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:00:10.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:00:10.70#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:10.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:10.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:10.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:10.75#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:00:10.75#ibcon#first serial, iclass 27, count 2 2006.161.08:00:10.75#ibcon#enter sib2, iclass 27, count 2 2006.161.08:00:10.75#ibcon#flushed, iclass 27, count 2 2006.161.08:00:10.75#ibcon#about to write, iclass 27, count 2 2006.161.08:00:10.75#ibcon#wrote, iclass 27, count 2 2006.161.08:00:10.75#ibcon#about to read 3, iclass 27, count 2 2006.161.08:00:10.77#ibcon#read 3, iclass 27, count 2 2006.161.08:00:10.77#ibcon#about to read 4, iclass 27, count 2 2006.161.08:00:10.77#ibcon#read 4, iclass 27, count 2 2006.161.08:00:10.77#ibcon#about to read 5, iclass 27, count 2 2006.161.08:00:10.77#ibcon#read 5, iclass 27, count 2 2006.161.08:00:10.77#ibcon#about to read 6, iclass 27, count 2 2006.161.08:00:10.77#ibcon#read 6, iclass 27, count 2 2006.161.08:00:10.77#ibcon#end of sib2, iclass 27, count 2 2006.161.08:00:10.77#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:00:10.77#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:00:10.78#ibcon#[25=AT05-07\r\n] 2006.161.08:00:10.78#ibcon#*before write, iclass 27, count 2 2006.161.08:00:10.78#ibcon#enter sib2, iclass 27, count 2 2006.161.08:00:10.78#ibcon#flushed, iclass 27, count 2 2006.161.08:00:10.78#ibcon#about to write, iclass 27, count 2 2006.161.08:00:10.78#ibcon#wrote, iclass 27, count 2 2006.161.08:00:10.78#ibcon#about to read 3, iclass 27, count 2 2006.161.08:00:10.80#ibcon#read 3, iclass 27, count 2 2006.161.08:00:10.80#ibcon#about to read 4, iclass 27, count 2 2006.161.08:00:10.80#ibcon#read 4, iclass 27, count 2 2006.161.08:00:10.80#ibcon#about to read 5, iclass 27, count 2 2006.161.08:00:10.80#ibcon#read 5, iclass 27, count 2 2006.161.08:00:10.80#ibcon#about to read 6, iclass 27, count 2 2006.161.08:00:10.80#ibcon#read 6, iclass 27, count 2 2006.161.08:00:10.80#ibcon#end of sib2, iclass 27, count 2 2006.161.08:00:10.80#ibcon#*after write, iclass 27, count 2 2006.161.08:00:10.80#ibcon#*before return 0, iclass 27, count 2 2006.161.08:00:10.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:10.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:10.81#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:00:10.81#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:10.81#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:10.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:10.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:10.92#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:00:10.92#ibcon#first serial, iclass 27, count 0 2006.161.08:00:10.92#ibcon#enter sib2, iclass 27, count 0 2006.161.08:00:10.92#ibcon#flushed, iclass 27, count 0 2006.161.08:00:10.92#ibcon#about to write, iclass 27, count 0 2006.161.08:00:10.92#ibcon#wrote, iclass 27, count 0 2006.161.08:00:10.92#ibcon#about to read 3, iclass 27, count 0 2006.161.08:00:10.94#ibcon#read 3, iclass 27, count 0 2006.161.08:00:10.94#ibcon#about to read 4, iclass 27, count 0 2006.161.08:00:10.94#ibcon#read 4, iclass 27, count 0 2006.161.08:00:10.94#ibcon#about to read 5, iclass 27, count 0 2006.161.08:00:10.94#ibcon#read 5, iclass 27, count 0 2006.161.08:00:10.94#ibcon#about to read 6, iclass 27, count 0 2006.161.08:00:10.94#ibcon#read 6, iclass 27, count 0 2006.161.08:00:10.94#ibcon#end of sib2, iclass 27, count 0 2006.161.08:00:10.94#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:00:10.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:00:10.94#ibcon#[25=USB\r\n] 2006.161.08:00:10.95#ibcon#*before write, iclass 27, count 0 2006.161.08:00:10.95#ibcon#enter sib2, iclass 27, count 0 2006.161.08:00:10.95#ibcon#flushed, iclass 27, count 0 2006.161.08:00:10.95#ibcon#about to write, iclass 27, count 0 2006.161.08:00:10.95#ibcon#wrote, iclass 27, count 0 2006.161.08:00:10.95#ibcon#about to read 3, iclass 27, count 0 2006.161.08:00:10.97#ibcon#read 3, iclass 27, count 0 2006.161.08:00:10.97#ibcon#about to read 4, iclass 27, count 0 2006.161.08:00:10.97#ibcon#read 4, iclass 27, count 0 2006.161.08:00:10.97#ibcon#about to read 5, iclass 27, count 0 2006.161.08:00:10.97#ibcon#read 5, iclass 27, count 0 2006.161.08:00:10.97#ibcon#about to read 6, iclass 27, count 0 2006.161.08:00:10.97#ibcon#read 6, iclass 27, count 0 2006.161.08:00:10.97#ibcon#end of sib2, iclass 27, count 0 2006.161.08:00:10.97#ibcon#*after write, iclass 27, count 0 2006.161.08:00:10.97#ibcon#*before return 0, iclass 27, count 0 2006.161.08:00:10.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:10.98#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:10.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:00:10.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:00:10.98$vc4f8/valo=6,772.99 2006.161.08:00:10.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:00:10.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:00:10.98#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:10.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:10.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:10.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:10.98#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:00:10.98#ibcon#first serial, iclass 29, count 0 2006.161.08:00:10.98#ibcon#enter sib2, iclass 29, count 0 2006.161.08:00:10.98#ibcon#flushed, iclass 29, count 0 2006.161.08:00:10.98#ibcon#about to write, iclass 29, count 0 2006.161.08:00:10.98#ibcon#wrote, iclass 29, count 0 2006.161.08:00:10.98#ibcon#about to read 3, iclass 29, count 0 2006.161.08:00:10.99#ibcon#read 3, iclass 29, count 0 2006.161.08:00:10.99#ibcon#about to read 4, iclass 29, count 0 2006.161.08:00:10.99#ibcon#read 4, iclass 29, count 0 2006.161.08:00:10.99#ibcon#about to read 5, iclass 29, count 0 2006.161.08:00:10.99#ibcon#read 5, iclass 29, count 0 2006.161.08:00:10.99#ibcon#about to read 6, iclass 29, count 0 2006.161.08:00:10.99#ibcon#read 6, iclass 29, count 0 2006.161.08:00:10.99#ibcon#end of sib2, iclass 29, count 0 2006.161.08:00:10.99#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:00:10.99#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:00:11.00#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:00:11.00#ibcon#*before write, iclass 29, count 0 2006.161.08:00:11.00#ibcon#enter sib2, iclass 29, count 0 2006.161.08:00:11.00#ibcon#flushed, iclass 29, count 0 2006.161.08:00:11.00#ibcon#about to write, iclass 29, count 0 2006.161.08:00:11.00#ibcon#wrote, iclass 29, count 0 2006.161.08:00:11.00#ibcon#about to read 3, iclass 29, count 0 2006.161.08:00:11.03#ibcon#read 3, iclass 29, count 0 2006.161.08:00:11.03#ibcon#about to read 4, iclass 29, count 0 2006.161.08:00:11.03#ibcon#read 4, iclass 29, count 0 2006.161.08:00:11.03#ibcon#about to read 5, iclass 29, count 0 2006.161.08:00:11.03#ibcon#read 5, iclass 29, count 0 2006.161.08:00:11.03#ibcon#about to read 6, iclass 29, count 0 2006.161.08:00:11.03#ibcon#read 6, iclass 29, count 0 2006.161.08:00:11.03#ibcon#end of sib2, iclass 29, count 0 2006.161.08:00:11.03#ibcon#*after write, iclass 29, count 0 2006.161.08:00:11.03#ibcon#*before return 0, iclass 29, count 0 2006.161.08:00:11.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:11.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:11.04#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:00:11.04#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:00:11.04$vc4f8/va=6,6 2006.161.08:00:11.04#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.08:00:11.04#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.08:00:11.04#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:11.04#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:11.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:11.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:11.09#ibcon#enter wrdev, iclass 31, count 2 2006.161.08:00:11.09#ibcon#first serial, iclass 31, count 2 2006.161.08:00:11.09#ibcon#enter sib2, iclass 31, count 2 2006.161.08:00:11.09#ibcon#flushed, iclass 31, count 2 2006.161.08:00:11.09#ibcon#about to write, iclass 31, count 2 2006.161.08:00:11.09#ibcon#wrote, iclass 31, count 2 2006.161.08:00:11.09#ibcon#about to read 3, iclass 31, count 2 2006.161.08:00:11.11#ibcon#read 3, iclass 31, count 2 2006.161.08:00:11.11#ibcon#about to read 4, iclass 31, count 2 2006.161.08:00:11.11#ibcon#read 4, iclass 31, count 2 2006.161.08:00:11.11#ibcon#about to read 5, iclass 31, count 2 2006.161.08:00:11.11#ibcon#read 5, iclass 31, count 2 2006.161.08:00:11.11#ibcon#about to read 6, iclass 31, count 2 2006.161.08:00:11.11#ibcon#read 6, iclass 31, count 2 2006.161.08:00:11.11#ibcon#end of sib2, iclass 31, count 2 2006.161.08:00:11.11#ibcon#*mode == 0, iclass 31, count 2 2006.161.08:00:11.11#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.08:00:11.11#ibcon#[25=AT06-06\r\n] 2006.161.08:00:11.11#ibcon#*before write, iclass 31, count 2 2006.161.08:00:11.12#ibcon#enter sib2, iclass 31, count 2 2006.161.08:00:11.12#ibcon#flushed, iclass 31, count 2 2006.161.08:00:11.12#ibcon#about to write, iclass 31, count 2 2006.161.08:00:11.12#ibcon#wrote, iclass 31, count 2 2006.161.08:00:11.12#ibcon#about to read 3, iclass 31, count 2 2006.161.08:00:11.15#ibcon#read 3, iclass 31, count 2 2006.161.08:00:11.15#ibcon#about to read 4, iclass 31, count 2 2006.161.08:00:11.15#ibcon#read 4, iclass 31, count 2 2006.161.08:00:11.15#ibcon#about to read 5, iclass 31, count 2 2006.161.08:00:11.15#ibcon#read 5, iclass 31, count 2 2006.161.08:00:11.15#ibcon#about to read 6, iclass 31, count 2 2006.161.08:00:11.15#ibcon#read 6, iclass 31, count 2 2006.161.08:00:11.15#ibcon#end of sib2, iclass 31, count 2 2006.161.08:00:11.15#ibcon#*after write, iclass 31, count 2 2006.161.08:00:11.15#ibcon#*before return 0, iclass 31, count 2 2006.161.08:00:11.15#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:11.15#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:11.15#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.08:00:11.15#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:11.15#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:00:11.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:00:11.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:00:11.26#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:00:11.26#ibcon#first serial, iclass 31, count 0 2006.161.08:00:11.26#ibcon#enter sib2, iclass 31, count 0 2006.161.08:00:11.26#ibcon#flushed, iclass 31, count 0 2006.161.08:00:11.26#ibcon#about to write, iclass 31, count 0 2006.161.08:00:11.26#ibcon#wrote, iclass 31, count 0 2006.161.08:00:11.26#ibcon#about to read 3, iclass 31, count 0 2006.161.08:00:11.28#ibcon#read 3, iclass 31, count 0 2006.161.08:00:11.28#ibcon#about to read 4, iclass 31, count 0 2006.161.08:00:11.28#ibcon#read 4, iclass 31, count 0 2006.161.08:00:11.28#ibcon#about to read 5, iclass 31, count 0 2006.161.08:00:11.28#ibcon#read 5, iclass 31, count 0 2006.161.08:00:11.28#ibcon#about to read 6, iclass 31, count 0 2006.161.08:00:11.28#ibcon#read 6, iclass 31, count 0 2006.161.08:00:11.28#ibcon#end of sib2, iclass 31, count 0 2006.161.08:00:11.28#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:00:11.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:00:11.28#ibcon#[25=USB\r\n] 2006.161.08:00:11.29#ibcon#*before write, iclass 31, count 0 2006.161.08:00:11.29#ibcon#enter sib2, iclass 31, count 0 2006.161.08:00:11.29#ibcon#flushed, iclass 31, count 0 2006.161.08:00:11.29#ibcon#about to write, iclass 31, count 0 2006.161.08:00:11.29#ibcon#wrote, iclass 31, count 0 2006.161.08:00:11.29#ibcon#about to read 3, iclass 31, count 0 2006.161.08:00:11.31#ibcon#read 3, iclass 31, count 0 2006.161.08:00:11.31#ibcon#about to read 4, iclass 31, count 0 2006.161.08:00:11.31#ibcon#read 4, iclass 31, count 0 2006.161.08:00:11.31#ibcon#about to read 5, iclass 31, count 0 2006.161.08:00:11.31#ibcon#read 5, iclass 31, count 0 2006.161.08:00:11.31#ibcon#about to read 6, iclass 31, count 0 2006.161.08:00:11.31#ibcon#read 6, iclass 31, count 0 2006.161.08:00:11.31#ibcon#end of sib2, iclass 31, count 0 2006.161.08:00:11.31#ibcon#*after write, iclass 31, count 0 2006.161.08:00:11.31#ibcon#*before return 0, iclass 31, count 0 2006.161.08:00:11.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:00:11.32#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:00:11.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:00:11.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:00:11.32$vc4f8/valo=7,832.99 2006.161.08:00:11.32#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.08:00:11.32#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.08:00:11.32#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:11.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:00:11.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:00:11.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:00:11.32#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:00:11.32#ibcon#first serial, iclass 33, count 0 2006.161.08:00:11.32#ibcon#enter sib2, iclass 33, count 0 2006.161.08:00:11.32#ibcon#flushed, iclass 33, count 0 2006.161.08:00:11.32#ibcon#about to write, iclass 33, count 0 2006.161.08:00:11.32#ibcon#wrote, iclass 33, count 0 2006.161.08:00:11.32#ibcon#about to read 3, iclass 33, count 0 2006.161.08:00:11.33#ibcon#read 3, iclass 33, count 0 2006.161.08:00:11.33#ibcon#about to read 4, iclass 33, count 0 2006.161.08:00:11.33#ibcon#read 4, iclass 33, count 0 2006.161.08:00:11.33#ibcon#about to read 5, iclass 33, count 0 2006.161.08:00:11.33#ibcon#read 5, iclass 33, count 0 2006.161.08:00:11.33#ibcon#about to read 6, iclass 33, count 0 2006.161.08:00:11.33#ibcon#read 6, iclass 33, count 0 2006.161.08:00:11.33#ibcon#end of sib2, iclass 33, count 0 2006.161.08:00:11.33#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:00:11.33#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:00:11.33#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:00:11.33#ibcon#*before write, iclass 33, count 0 2006.161.08:00:11.34#ibcon#enter sib2, iclass 33, count 0 2006.161.08:00:11.34#ibcon#flushed, iclass 33, count 0 2006.161.08:00:11.34#ibcon#about to write, iclass 33, count 0 2006.161.08:00:11.34#ibcon#wrote, iclass 33, count 0 2006.161.08:00:11.34#ibcon#about to read 3, iclass 33, count 0 2006.161.08:00:11.37#ibcon#read 3, iclass 33, count 0 2006.161.08:00:11.37#ibcon#about to read 4, iclass 33, count 0 2006.161.08:00:11.37#ibcon#read 4, iclass 33, count 0 2006.161.08:00:11.37#ibcon#about to read 5, iclass 33, count 0 2006.161.08:00:11.37#ibcon#read 5, iclass 33, count 0 2006.161.08:00:11.37#ibcon#about to read 6, iclass 33, count 0 2006.161.08:00:11.37#ibcon#read 6, iclass 33, count 0 2006.161.08:00:11.37#ibcon#end of sib2, iclass 33, count 0 2006.161.08:00:11.37#ibcon#*after write, iclass 33, count 0 2006.161.08:00:11.37#ibcon#*before return 0, iclass 33, count 0 2006.161.08:00:11.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:00:11.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:00:11.38#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:00:11.38#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:00:11.38$vc4f8/va=7,6 2006.161.08:00:11.38#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.08:00:11.38#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.08:00:11.38#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:11.38#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:00:11.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:00:11.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:00:11.43#ibcon#enter wrdev, iclass 35, count 2 2006.161.08:00:11.43#ibcon#first serial, iclass 35, count 2 2006.161.08:00:11.43#ibcon#enter sib2, iclass 35, count 2 2006.161.08:00:11.43#ibcon#flushed, iclass 35, count 2 2006.161.08:00:11.43#ibcon#about to write, iclass 35, count 2 2006.161.08:00:11.43#ibcon#wrote, iclass 35, count 2 2006.161.08:00:11.43#ibcon#about to read 3, iclass 35, count 2 2006.161.08:00:11.45#ibcon#read 3, iclass 35, count 2 2006.161.08:00:11.45#ibcon#about to read 4, iclass 35, count 2 2006.161.08:00:11.45#ibcon#read 4, iclass 35, count 2 2006.161.08:00:11.45#ibcon#about to read 5, iclass 35, count 2 2006.161.08:00:11.45#ibcon#read 5, iclass 35, count 2 2006.161.08:00:11.45#ibcon#about to read 6, iclass 35, count 2 2006.161.08:00:11.45#ibcon#read 6, iclass 35, count 2 2006.161.08:00:11.45#ibcon#end of sib2, iclass 35, count 2 2006.161.08:00:11.45#ibcon#*mode == 0, iclass 35, count 2 2006.161.08:00:11.45#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.08:00:11.45#ibcon#[25=AT07-06\r\n] 2006.161.08:00:11.45#ibcon#*before write, iclass 35, count 2 2006.161.08:00:11.46#ibcon#enter sib2, iclass 35, count 2 2006.161.08:00:11.46#ibcon#flushed, iclass 35, count 2 2006.161.08:00:11.46#ibcon#about to write, iclass 35, count 2 2006.161.08:00:11.46#ibcon#wrote, iclass 35, count 2 2006.161.08:00:11.46#ibcon#about to read 3, iclass 35, count 2 2006.161.08:00:11.48#ibcon#read 3, iclass 35, count 2 2006.161.08:00:11.48#ibcon#about to read 4, iclass 35, count 2 2006.161.08:00:11.48#ibcon#read 4, iclass 35, count 2 2006.161.08:00:11.48#ibcon#about to read 5, iclass 35, count 2 2006.161.08:00:11.48#ibcon#read 5, iclass 35, count 2 2006.161.08:00:11.48#ibcon#about to read 6, iclass 35, count 2 2006.161.08:00:11.48#ibcon#read 6, iclass 35, count 2 2006.161.08:00:11.48#ibcon#end of sib2, iclass 35, count 2 2006.161.08:00:11.48#ibcon#*after write, iclass 35, count 2 2006.161.08:00:11.48#ibcon#*before return 0, iclass 35, count 2 2006.161.08:00:11.49#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:00:11.49#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:00:11.49#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.08:00:11.49#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:11.49#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:00:11.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:00:11.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:00:11.60#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:00:11.60#ibcon#first serial, iclass 35, count 0 2006.161.08:00:11.60#ibcon#enter sib2, iclass 35, count 0 2006.161.08:00:11.60#ibcon#flushed, iclass 35, count 0 2006.161.08:00:11.60#ibcon#about to write, iclass 35, count 0 2006.161.08:00:11.60#ibcon#wrote, iclass 35, count 0 2006.161.08:00:11.60#ibcon#about to read 3, iclass 35, count 0 2006.161.08:00:11.62#ibcon#read 3, iclass 35, count 0 2006.161.08:00:11.62#ibcon#about to read 4, iclass 35, count 0 2006.161.08:00:11.62#ibcon#read 4, iclass 35, count 0 2006.161.08:00:11.62#ibcon#about to read 5, iclass 35, count 0 2006.161.08:00:11.62#ibcon#read 5, iclass 35, count 0 2006.161.08:00:11.62#ibcon#about to read 6, iclass 35, count 0 2006.161.08:00:11.62#ibcon#read 6, iclass 35, count 0 2006.161.08:00:11.62#ibcon#end of sib2, iclass 35, count 0 2006.161.08:00:11.62#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:00:11.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:00:11.62#ibcon#[25=USB\r\n] 2006.161.08:00:11.63#ibcon#*before write, iclass 35, count 0 2006.161.08:00:11.63#ibcon#enter sib2, iclass 35, count 0 2006.161.08:00:11.63#ibcon#flushed, iclass 35, count 0 2006.161.08:00:11.63#ibcon#about to write, iclass 35, count 0 2006.161.08:00:11.63#ibcon#wrote, iclass 35, count 0 2006.161.08:00:11.63#ibcon#about to read 3, iclass 35, count 0 2006.161.08:00:11.65#ibcon#read 3, iclass 35, count 0 2006.161.08:00:11.65#ibcon#about to read 4, iclass 35, count 0 2006.161.08:00:11.65#ibcon#read 4, iclass 35, count 0 2006.161.08:00:11.65#ibcon#about to read 5, iclass 35, count 0 2006.161.08:00:11.65#ibcon#read 5, iclass 35, count 0 2006.161.08:00:11.65#ibcon#about to read 6, iclass 35, count 0 2006.161.08:00:11.65#ibcon#read 6, iclass 35, count 0 2006.161.08:00:11.65#ibcon#end of sib2, iclass 35, count 0 2006.161.08:00:11.65#ibcon#*after write, iclass 35, count 0 2006.161.08:00:11.65#ibcon#*before return 0, iclass 35, count 0 2006.161.08:00:11.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:00:11.66#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:00:11.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:00:11.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:00:11.66$vc4f8/valo=8,852.99 2006.161.08:00:11.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:00:11.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:00:11.66#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:11.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:00:11.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:00:11.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:00:11.66#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:00:11.66#ibcon#first serial, iclass 37, count 0 2006.161.08:00:11.66#ibcon#enter sib2, iclass 37, count 0 2006.161.08:00:11.66#ibcon#flushed, iclass 37, count 0 2006.161.08:00:11.66#ibcon#about to write, iclass 37, count 0 2006.161.08:00:11.66#ibcon#wrote, iclass 37, count 0 2006.161.08:00:11.66#ibcon#about to read 3, iclass 37, count 0 2006.161.08:00:11.67#ibcon#read 3, iclass 37, count 0 2006.161.08:00:11.67#ibcon#about to read 4, iclass 37, count 0 2006.161.08:00:11.67#ibcon#read 4, iclass 37, count 0 2006.161.08:00:11.67#ibcon#about to read 5, iclass 37, count 0 2006.161.08:00:11.67#ibcon#read 5, iclass 37, count 0 2006.161.08:00:11.67#ibcon#about to read 6, iclass 37, count 0 2006.161.08:00:11.67#ibcon#read 6, iclass 37, count 0 2006.161.08:00:11.67#ibcon#end of sib2, iclass 37, count 0 2006.161.08:00:11.67#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:00:11.67#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:00:11.67#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:00:11.67#ibcon#*before write, iclass 37, count 0 2006.161.08:00:11.68#ibcon#enter sib2, iclass 37, count 0 2006.161.08:00:11.68#ibcon#flushed, iclass 37, count 0 2006.161.08:00:11.68#ibcon#about to write, iclass 37, count 0 2006.161.08:00:11.68#ibcon#wrote, iclass 37, count 0 2006.161.08:00:11.68#ibcon#about to read 3, iclass 37, count 0 2006.161.08:00:11.71#ibcon#read 3, iclass 37, count 0 2006.161.08:00:11.71#ibcon#about to read 4, iclass 37, count 0 2006.161.08:00:11.71#ibcon#read 4, iclass 37, count 0 2006.161.08:00:11.71#ibcon#about to read 5, iclass 37, count 0 2006.161.08:00:11.71#ibcon#read 5, iclass 37, count 0 2006.161.08:00:11.71#ibcon#about to read 6, iclass 37, count 0 2006.161.08:00:11.71#ibcon#read 6, iclass 37, count 0 2006.161.08:00:11.71#ibcon#end of sib2, iclass 37, count 0 2006.161.08:00:11.71#ibcon#*after write, iclass 37, count 0 2006.161.08:00:11.71#ibcon#*before return 0, iclass 37, count 0 2006.161.08:00:11.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:00:11.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:00:11.72#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:00:11.72#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:00:11.72$vc4f8/va=8,7 2006.161.08:00:11.72#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:00:11.72#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:00:11.72#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:11.72#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:00:11.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:00:11.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:00:11.77#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:00:11.77#ibcon#first serial, iclass 39, count 2 2006.161.08:00:11.77#ibcon#enter sib2, iclass 39, count 2 2006.161.08:00:11.77#ibcon#flushed, iclass 39, count 2 2006.161.08:00:11.77#ibcon#about to write, iclass 39, count 2 2006.161.08:00:11.77#ibcon#wrote, iclass 39, count 2 2006.161.08:00:11.77#ibcon#about to read 3, iclass 39, count 2 2006.161.08:00:11.79#ibcon#read 3, iclass 39, count 2 2006.161.08:00:11.79#ibcon#about to read 4, iclass 39, count 2 2006.161.08:00:11.79#ibcon#read 4, iclass 39, count 2 2006.161.08:00:11.79#ibcon#about to read 5, iclass 39, count 2 2006.161.08:00:11.79#ibcon#read 5, iclass 39, count 2 2006.161.08:00:11.79#ibcon#about to read 6, iclass 39, count 2 2006.161.08:00:11.79#ibcon#read 6, iclass 39, count 2 2006.161.08:00:11.79#ibcon#end of sib2, iclass 39, count 2 2006.161.08:00:11.79#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:00:11.79#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:00:11.79#ibcon#[25=AT08-07\r\n] 2006.161.08:00:11.79#ibcon#*before write, iclass 39, count 2 2006.161.08:00:11.80#ibcon#enter sib2, iclass 39, count 2 2006.161.08:00:11.80#ibcon#flushed, iclass 39, count 2 2006.161.08:00:11.80#ibcon#about to write, iclass 39, count 2 2006.161.08:00:11.80#ibcon#wrote, iclass 39, count 2 2006.161.08:00:11.80#ibcon#about to read 3, iclass 39, count 2 2006.161.08:00:11.82#ibcon#read 3, iclass 39, count 2 2006.161.08:00:11.82#ibcon#about to read 4, iclass 39, count 2 2006.161.08:00:11.82#ibcon#read 4, iclass 39, count 2 2006.161.08:00:11.82#ibcon#about to read 5, iclass 39, count 2 2006.161.08:00:11.82#ibcon#read 5, iclass 39, count 2 2006.161.08:00:11.82#ibcon#about to read 6, iclass 39, count 2 2006.161.08:00:11.82#ibcon#read 6, iclass 39, count 2 2006.161.08:00:11.82#ibcon#end of sib2, iclass 39, count 2 2006.161.08:00:11.82#ibcon#*after write, iclass 39, count 2 2006.161.08:00:11.82#ibcon#*before return 0, iclass 39, count 2 2006.161.08:00:11.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:00:11.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:00:11.83#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:00:11.83#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:11.83#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:00:11.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:00:11.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:00:11.94#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:00:11.94#ibcon#first serial, iclass 39, count 0 2006.161.08:00:11.94#ibcon#enter sib2, iclass 39, count 0 2006.161.08:00:11.94#ibcon#flushed, iclass 39, count 0 2006.161.08:00:11.94#ibcon#about to write, iclass 39, count 0 2006.161.08:00:11.94#ibcon#wrote, iclass 39, count 0 2006.161.08:00:11.94#ibcon#about to read 3, iclass 39, count 0 2006.161.08:00:11.96#ibcon#read 3, iclass 39, count 0 2006.161.08:00:11.96#ibcon#about to read 4, iclass 39, count 0 2006.161.08:00:11.96#ibcon#read 4, iclass 39, count 0 2006.161.08:00:11.96#ibcon#about to read 5, iclass 39, count 0 2006.161.08:00:11.96#ibcon#read 5, iclass 39, count 0 2006.161.08:00:11.96#ibcon#about to read 6, iclass 39, count 0 2006.161.08:00:11.96#ibcon#read 6, iclass 39, count 0 2006.161.08:00:11.96#ibcon#end of sib2, iclass 39, count 0 2006.161.08:00:11.96#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:00:11.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:00:11.96#ibcon#[25=USB\r\n] 2006.161.08:00:11.96#ibcon#*before write, iclass 39, count 0 2006.161.08:00:11.97#ibcon#enter sib2, iclass 39, count 0 2006.161.08:00:11.97#ibcon#flushed, iclass 39, count 0 2006.161.08:00:11.97#ibcon#about to write, iclass 39, count 0 2006.161.08:00:11.97#ibcon#wrote, iclass 39, count 0 2006.161.08:00:11.97#ibcon#about to read 3, iclass 39, count 0 2006.161.08:00:11.99#ibcon#read 3, iclass 39, count 0 2006.161.08:00:11.99#ibcon#about to read 4, iclass 39, count 0 2006.161.08:00:11.99#ibcon#read 4, iclass 39, count 0 2006.161.08:00:11.99#ibcon#about to read 5, iclass 39, count 0 2006.161.08:00:11.99#ibcon#read 5, iclass 39, count 0 2006.161.08:00:11.99#ibcon#about to read 6, iclass 39, count 0 2006.161.08:00:11.99#ibcon#read 6, iclass 39, count 0 2006.161.08:00:11.99#ibcon#end of sib2, iclass 39, count 0 2006.161.08:00:11.99#ibcon#*after write, iclass 39, count 0 2006.161.08:00:11.99#ibcon#*before return 0, iclass 39, count 0 2006.161.08:00:11.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:00:12.00#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:00:12.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:00:12.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:00:12.00$vc4f8/vblo=1,632.99 2006.161.08:00:12.00#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:00:12.00#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:00:12.00#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:12.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:00:12.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:00:12.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:00:12.00#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:00:12.00#ibcon#first serial, iclass 3, count 0 2006.161.08:00:12.00#ibcon#enter sib2, iclass 3, count 0 2006.161.08:00:12.00#ibcon#flushed, iclass 3, count 0 2006.161.08:00:12.00#ibcon#about to write, iclass 3, count 0 2006.161.08:00:12.00#ibcon#wrote, iclass 3, count 0 2006.161.08:00:12.00#ibcon#about to read 3, iclass 3, count 0 2006.161.08:00:12.01#ibcon#read 3, iclass 3, count 0 2006.161.08:00:12.01#ibcon#about to read 4, iclass 3, count 0 2006.161.08:00:12.01#ibcon#read 4, iclass 3, count 0 2006.161.08:00:12.01#ibcon#about to read 5, iclass 3, count 0 2006.161.08:00:12.01#ibcon#read 5, iclass 3, count 0 2006.161.08:00:12.01#ibcon#about to read 6, iclass 3, count 0 2006.161.08:00:12.01#ibcon#read 6, iclass 3, count 0 2006.161.08:00:12.01#ibcon#end of sib2, iclass 3, count 0 2006.161.08:00:12.01#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:00:12.01#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:00:12.01#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:00:12.02#ibcon#*before write, iclass 3, count 0 2006.161.08:00:12.02#ibcon#enter sib2, iclass 3, count 0 2006.161.08:00:12.02#ibcon#flushed, iclass 3, count 0 2006.161.08:00:12.02#ibcon#about to write, iclass 3, count 0 2006.161.08:00:12.02#ibcon#wrote, iclass 3, count 0 2006.161.08:00:12.02#ibcon#about to read 3, iclass 3, count 0 2006.161.08:00:12.05#ibcon#read 3, iclass 3, count 0 2006.161.08:00:12.05#ibcon#about to read 4, iclass 3, count 0 2006.161.08:00:12.05#ibcon#read 4, iclass 3, count 0 2006.161.08:00:12.05#ibcon#about to read 5, iclass 3, count 0 2006.161.08:00:12.05#ibcon#read 5, iclass 3, count 0 2006.161.08:00:12.05#ibcon#about to read 6, iclass 3, count 0 2006.161.08:00:12.05#ibcon#read 6, iclass 3, count 0 2006.161.08:00:12.05#ibcon#end of sib2, iclass 3, count 0 2006.161.08:00:12.05#ibcon#*after write, iclass 3, count 0 2006.161.08:00:12.05#ibcon#*before return 0, iclass 3, count 0 2006.161.08:00:12.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:00:12.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:00:12.06#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:00:12.06#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:00:12.06$vc4f8/vb=1,4 2006.161.08:00:12.06#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:00:12.06#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:00:12.06#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:12.06#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:00:12.06#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:00:12.06#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:00:12.06#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:00:12.06#ibcon#first serial, iclass 5, count 2 2006.161.08:00:12.06#ibcon#enter sib2, iclass 5, count 2 2006.161.08:00:12.06#ibcon#flushed, iclass 5, count 2 2006.161.08:00:12.06#ibcon#about to write, iclass 5, count 2 2006.161.08:00:12.06#ibcon#wrote, iclass 5, count 2 2006.161.08:00:12.06#ibcon#about to read 3, iclass 5, count 2 2006.161.08:00:12.07#ibcon#read 3, iclass 5, count 2 2006.161.08:00:12.07#ibcon#about to read 4, iclass 5, count 2 2006.161.08:00:12.07#ibcon#read 4, iclass 5, count 2 2006.161.08:00:12.07#ibcon#about to read 5, iclass 5, count 2 2006.161.08:00:12.07#ibcon#read 5, iclass 5, count 2 2006.161.08:00:12.07#ibcon#about to read 6, iclass 5, count 2 2006.161.08:00:12.07#ibcon#read 6, iclass 5, count 2 2006.161.08:00:12.07#ibcon#end of sib2, iclass 5, count 2 2006.161.08:00:12.07#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:00:12.08#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:00:12.08#ibcon#[27=AT01-04\r\n] 2006.161.08:00:12.08#ibcon#*before write, iclass 5, count 2 2006.161.08:00:12.08#ibcon#enter sib2, iclass 5, count 2 2006.161.08:00:12.08#ibcon#flushed, iclass 5, count 2 2006.161.08:00:12.08#ibcon#about to write, iclass 5, count 2 2006.161.08:00:12.08#ibcon#wrote, iclass 5, count 2 2006.161.08:00:12.08#ibcon#about to read 3, iclass 5, count 2 2006.161.08:00:12.10#ibcon#read 3, iclass 5, count 2 2006.161.08:00:12.10#ibcon#about to read 4, iclass 5, count 2 2006.161.08:00:12.10#ibcon#read 4, iclass 5, count 2 2006.161.08:00:12.10#ibcon#about to read 5, iclass 5, count 2 2006.161.08:00:12.10#ibcon#read 5, iclass 5, count 2 2006.161.08:00:12.10#ibcon#about to read 6, iclass 5, count 2 2006.161.08:00:12.10#ibcon#read 6, iclass 5, count 2 2006.161.08:00:12.10#ibcon#end of sib2, iclass 5, count 2 2006.161.08:00:12.10#ibcon#*after write, iclass 5, count 2 2006.161.08:00:12.10#ibcon#*before return 0, iclass 5, count 2 2006.161.08:00:12.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:00:12.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:00:12.11#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:00:12.11#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:12.11#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:00:12.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:00:12.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:00:12.22#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:00:12.22#ibcon#first serial, iclass 5, count 0 2006.161.08:00:12.22#ibcon#enter sib2, iclass 5, count 0 2006.161.08:00:12.22#ibcon#flushed, iclass 5, count 0 2006.161.08:00:12.22#ibcon#about to write, iclass 5, count 0 2006.161.08:00:12.22#ibcon#wrote, iclass 5, count 0 2006.161.08:00:12.22#ibcon#about to read 3, iclass 5, count 0 2006.161.08:00:12.24#ibcon#read 3, iclass 5, count 0 2006.161.08:00:12.24#ibcon#about to read 4, iclass 5, count 0 2006.161.08:00:12.24#ibcon#read 4, iclass 5, count 0 2006.161.08:00:12.24#ibcon#about to read 5, iclass 5, count 0 2006.161.08:00:12.24#ibcon#read 5, iclass 5, count 0 2006.161.08:00:12.24#ibcon#about to read 6, iclass 5, count 0 2006.161.08:00:12.24#ibcon#read 6, iclass 5, count 0 2006.161.08:00:12.24#ibcon#end of sib2, iclass 5, count 0 2006.161.08:00:12.24#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:00:12.24#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:00:12.25#ibcon#[27=USB\r\n] 2006.161.08:00:12.25#ibcon#*before write, iclass 5, count 0 2006.161.08:00:12.25#ibcon#enter sib2, iclass 5, count 0 2006.161.08:00:12.25#ibcon#flushed, iclass 5, count 0 2006.161.08:00:12.25#ibcon#about to write, iclass 5, count 0 2006.161.08:00:12.25#ibcon#wrote, iclass 5, count 0 2006.161.08:00:12.25#ibcon#about to read 3, iclass 5, count 0 2006.161.08:00:12.27#ibcon#read 3, iclass 5, count 0 2006.161.08:00:12.27#ibcon#about to read 4, iclass 5, count 0 2006.161.08:00:12.27#ibcon#read 4, iclass 5, count 0 2006.161.08:00:12.27#ibcon#about to read 5, iclass 5, count 0 2006.161.08:00:12.27#ibcon#read 5, iclass 5, count 0 2006.161.08:00:12.27#ibcon#about to read 6, iclass 5, count 0 2006.161.08:00:12.27#ibcon#read 6, iclass 5, count 0 2006.161.08:00:12.28#ibcon#end of sib2, iclass 5, count 0 2006.161.08:00:12.28#ibcon#*after write, iclass 5, count 0 2006.161.08:00:12.28#ibcon#*before return 0, iclass 5, count 0 2006.161.08:00:12.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:00:12.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:00:12.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:00:12.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:00:12.28$vc4f8/vblo=2,640.99 2006.161.08:00:12.28#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:00:12.28#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:00:12.28#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:12.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:12.28#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:12.28#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:12.28#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:00:12.28#ibcon#first serial, iclass 7, count 0 2006.161.08:00:12.28#ibcon#enter sib2, iclass 7, count 0 2006.161.08:00:12.28#ibcon#flushed, iclass 7, count 0 2006.161.08:00:12.28#ibcon#about to write, iclass 7, count 0 2006.161.08:00:12.28#ibcon#wrote, iclass 7, count 0 2006.161.08:00:12.28#ibcon#about to read 3, iclass 7, count 0 2006.161.08:00:12.29#ibcon#read 3, iclass 7, count 0 2006.161.08:00:12.29#ibcon#about to read 4, iclass 7, count 0 2006.161.08:00:12.29#ibcon#read 4, iclass 7, count 0 2006.161.08:00:12.29#ibcon#about to read 5, iclass 7, count 0 2006.161.08:00:12.29#ibcon#read 5, iclass 7, count 0 2006.161.08:00:12.29#ibcon#about to read 6, iclass 7, count 0 2006.161.08:00:12.29#ibcon#read 6, iclass 7, count 0 2006.161.08:00:12.29#ibcon#end of sib2, iclass 7, count 0 2006.161.08:00:12.29#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:00:12.29#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:00:12.29#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:00:12.30#ibcon#*before write, iclass 7, count 0 2006.161.08:00:12.30#ibcon#enter sib2, iclass 7, count 0 2006.161.08:00:12.30#ibcon#flushed, iclass 7, count 0 2006.161.08:00:12.30#ibcon#about to write, iclass 7, count 0 2006.161.08:00:12.30#ibcon#wrote, iclass 7, count 0 2006.161.08:00:12.30#ibcon#about to read 3, iclass 7, count 0 2006.161.08:00:12.33#ibcon#read 3, iclass 7, count 0 2006.161.08:00:12.33#ibcon#about to read 4, iclass 7, count 0 2006.161.08:00:12.33#ibcon#read 4, iclass 7, count 0 2006.161.08:00:12.33#ibcon#about to read 5, iclass 7, count 0 2006.161.08:00:12.33#ibcon#read 5, iclass 7, count 0 2006.161.08:00:12.33#ibcon#about to read 6, iclass 7, count 0 2006.161.08:00:12.33#ibcon#read 6, iclass 7, count 0 2006.161.08:00:12.33#ibcon#end of sib2, iclass 7, count 0 2006.161.08:00:12.33#ibcon#*after write, iclass 7, count 0 2006.161.08:00:12.33#ibcon#*before return 0, iclass 7, count 0 2006.161.08:00:12.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:12.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:00:12.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:00:12.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:00:12.34$vc4f8/vb=2,4 2006.161.08:00:12.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:00:12.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:00:12.34#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:12.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:12.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:12.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:12.39#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:00:12.39#ibcon#first serial, iclass 11, count 2 2006.161.08:00:12.39#ibcon#enter sib2, iclass 11, count 2 2006.161.08:00:12.39#ibcon#flushed, iclass 11, count 2 2006.161.08:00:12.39#ibcon#about to write, iclass 11, count 2 2006.161.08:00:12.39#ibcon#wrote, iclass 11, count 2 2006.161.08:00:12.39#ibcon#about to read 3, iclass 11, count 2 2006.161.08:00:12.41#ibcon#read 3, iclass 11, count 2 2006.161.08:00:12.41#ibcon#about to read 4, iclass 11, count 2 2006.161.08:00:12.41#ibcon#read 4, iclass 11, count 2 2006.161.08:00:12.41#ibcon#about to read 5, iclass 11, count 2 2006.161.08:00:12.41#ibcon#read 5, iclass 11, count 2 2006.161.08:00:12.41#ibcon#about to read 6, iclass 11, count 2 2006.161.08:00:12.41#ibcon#read 6, iclass 11, count 2 2006.161.08:00:12.41#ibcon#end of sib2, iclass 11, count 2 2006.161.08:00:12.41#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:00:12.41#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:00:12.41#ibcon#[27=AT02-04\r\n] 2006.161.08:00:12.41#ibcon#*before write, iclass 11, count 2 2006.161.08:00:12.42#ibcon#enter sib2, iclass 11, count 2 2006.161.08:00:12.42#ibcon#flushed, iclass 11, count 2 2006.161.08:00:12.42#ibcon#about to write, iclass 11, count 2 2006.161.08:00:12.42#ibcon#wrote, iclass 11, count 2 2006.161.08:00:12.42#ibcon#about to read 3, iclass 11, count 2 2006.161.08:00:12.44#ibcon#read 3, iclass 11, count 2 2006.161.08:00:12.44#ibcon#about to read 4, iclass 11, count 2 2006.161.08:00:12.44#ibcon#read 4, iclass 11, count 2 2006.161.08:00:12.44#ibcon#about to read 5, iclass 11, count 2 2006.161.08:00:12.44#ibcon#read 5, iclass 11, count 2 2006.161.08:00:12.44#ibcon#about to read 6, iclass 11, count 2 2006.161.08:00:12.44#ibcon#read 6, iclass 11, count 2 2006.161.08:00:12.44#ibcon#end of sib2, iclass 11, count 2 2006.161.08:00:12.44#ibcon#*after write, iclass 11, count 2 2006.161.08:00:12.44#ibcon#*before return 0, iclass 11, count 2 2006.161.08:00:12.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:12.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:00:12.45#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:00:12.45#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:12.45#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:12.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:12.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:12.56#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:00:12.56#ibcon#first serial, iclass 11, count 0 2006.161.08:00:12.56#ibcon#enter sib2, iclass 11, count 0 2006.161.08:00:12.56#ibcon#flushed, iclass 11, count 0 2006.161.08:00:12.56#ibcon#about to write, iclass 11, count 0 2006.161.08:00:12.56#ibcon#wrote, iclass 11, count 0 2006.161.08:00:12.56#ibcon#about to read 3, iclass 11, count 0 2006.161.08:00:12.58#ibcon#read 3, iclass 11, count 0 2006.161.08:00:12.58#ibcon#about to read 4, iclass 11, count 0 2006.161.08:00:12.58#ibcon#read 4, iclass 11, count 0 2006.161.08:00:12.58#ibcon#about to read 5, iclass 11, count 0 2006.161.08:00:12.58#ibcon#read 5, iclass 11, count 0 2006.161.08:00:12.58#ibcon#about to read 6, iclass 11, count 0 2006.161.08:00:12.58#ibcon#read 6, iclass 11, count 0 2006.161.08:00:12.58#ibcon#end of sib2, iclass 11, count 0 2006.161.08:00:12.58#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:00:12.59#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:00:12.59#ibcon#[27=USB\r\n] 2006.161.08:00:12.59#ibcon#*before write, iclass 11, count 0 2006.161.08:00:12.59#ibcon#enter sib2, iclass 11, count 0 2006.161.08:00:12.59#ibcon#flushed, iclass 11, count 0 2006.161.08:00:12.59#ibcon#about to write, iclass 11, count 0 2006.161.08:00:12.59#ibcon#wrote, iclass 11, count 0 2006.161.08:00:12.59#ibcon#about to read 3, iclass 11, count 0 2006.161.08:00:12.61#ibcon#read 3, iclass 11, count 0 2006.161.08:00:12.61#ibcon#about to read 4, iclass 11, count 0 2006.161.08:00:12.61#ibcon#read 4, iclass 11, count 0 2006.161.08:00:12.61#ibcon#about to read 5, iclass 11, count 0 2006.161.08:00:12.61#ibcon#read 5, iclass 11, count 0 2006.161.08:00:12.61#ibcon#about to read 6, iclass 11, count 0 2006.161.08:00:12.61#ibcon#read 6, iclass 11, count 0 2006.161.08:00:12.61#ibcon#end of sib2, iclass 11, count 0 2006.161.08:00:12.61#ibcon#*after write, iclass 11, count 0 2006.161.08:00:12.61#ibcon#*before return 0, iclass 11, count 0 2006.161.08:00:12.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:12.62#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:00:12.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:00:12.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:00:12.62$vc4f8/vblo=3,656.99 2006.161.08:00:12.62#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:00:12.62#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:00:12.62#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:12.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:12.62#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:12.62#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:12.62#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:00:12.62#ibcon#first serial, iclass 13, count 0 2006.161.08:00:12.62#ibcon#enter sib2, iclass 13, count 0 2006.161.08:00:12.62#ibcon#flushed, iclass 13, count 0 2006.161.08:00:12.62#ibcon#about to write, iclass 13, count 0 2006.161.08:00:12.62#ibcon#wrote, iclass 13, count 0 2006.161.08:00:12.62#ibcon#about to read 3, iclass 13, count 0 2006.161.08:00:12.63#ibcon#read 3, iclass 13, count 0 2006.161.08:00:12.63#ibcon#about to read 4, iclass 13, count 0 2006.161.08:00:12.63#ibcon#read 4, iclass 13, count 0 2006.161.08:00:12.63#ibcon#about to read 5, iclass 13, count 0 2006.161.08:00:12.63#ibcon#read 5, iclass 13, count 0 2006.161.08:00:12.63#ibcon#about to read 6, iclass 13, count 0 2006.161.08:00:12.63#ibcon#read 6, iclass 13, count 0 2006.161.08:00:12.63#ibcon#end of sib2, iclass 13, count 0 2006.161.08:00:12.63#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:00:12.63#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:00:12.63#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:00:12.63#ibcon#*before write, iclass 13, count 0 2006.161.08:00:12.64#ibcon#enter sib2, iclass 13, count 0 2006.161.08:00:12.64#ibcon#flushed, iclass 13, count 0 2006.161.08:00:12.64#ibcon#about to write, iclass 13, count 0 2006.161.08:00:12.64#ibcon#wrote, iclass 13, count 0 2006.161.08:00:12.64#ibcon#about to read 3, iclass 13, count 0 2006.161.08:00:12.67#ibcon#read 3, iclass 13, count 0 2006.161.08:00:12.67#ibcon#about to read 4, iclass 13, count 0 2006.161.08:00:12.67#ibcon#read 4, iclass 13, count 0 2006.161.08:00:12.67#ibcon#about to read 5, iclass 13, count 0 2006.161.08:00:12.67#ibcon#read 5, iclass 13, count 0 2006.161.08:00:12.67#ibcon#about to read 6, iclass 13, count 0 2006.161.08:00:12.67#ibcon#read 6, iclass 13, count 0 2006.161.08:00:12.68#ibcon#end of sib2, iclass 13, count 0 2006.161.08:00:12.68#ibcon#*after write, iclass 13, count 0 2006.161.08:00:12.68#ibcon#*before return 0, iclass 13, count 0 2006.161.08:00:12.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:12.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:00:12.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:00:12.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:00:12.68$vc4f8/vb=3,4 2006.161.08:00:12.68#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:00:12.68#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:00:12.68#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:12.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:12.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:12.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:12.73#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:00:12.73#ibcon#first serial, iclass 15, count 2 2006.161.08:00:12.73#ibcon#enter sib2, iclass 15, count 2 2006.161.08:00:12.73#ibcon#flushed, iclass 15, count 2 2006.161.08:00:12.73#ibcon#about to write, iclass 15, count 2 2006.161.08:00:12.73#ibcon#wrote, iclass 15, count 2 2006.161.08:00:12.73#ibcon#about to read 3, iclass 15, count 2 2006.161.08:00:12.75#ibcon#read 3, iclass 15, count 2 2006.161.08:00:12.75#ibcon#about to read 4, iclass 15, count 2 2006.161.08:00:12.75#ibcon#read 4, iclass 15, count 2 2006.161.08:00:12.75#ibcon#about to read 5, iclass 15, count 2 2006.161.08:00:12.75#ibcon#read 5, iclass 15, count 2 2006.161.08:00:12.75#ibcon#about to read 6, iclass 15, count 2 2006.161.08:00:12.75#ibcon#read 6, iclass 15, count 2 2006.161.08:00:12.75#ibcon#end of sib2, iclass 15, count 2 2006.161.08:00:12.75#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:00:12.75#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:00:12.75#ibcon#[27=AT03-04\r\n] 2006.161.08:00:12.75#ibcon#*before write, iclass 15, count 2 2006.161.08:00:12.76#ibcon#enter sib2, iclass 15, count 2 2006.161.08:00:12.76#ibcon#flushed, iclass 15, count 2 2006.161.08:00:12.76#ibcon#about to write, iclass 15, count 2 2006.161.08:00:12.76#ibcon#wrote, iclass 15, count 2 2006.161.08:00:12.76#ibcon#about to read 3, iclass 15, count 2 2006.161.08:00:12.78#ibcon#read 3, iclass 15, count 2 2006.161.08:00:12.78#ibcon#about to read 4, iclass 15, count 2 2006.161.08:00:12.78#ibcon#read 4, iclass 15, count 2 2006.161.08:00:12.78#ibcon#about to read 5, iclass 15, count 2 2006.161.08:00:12.78#ibcon#read 5, iclass 15, count 2 2006.161.08:00:12.78#ibcon#about to read 6, iclass 15, count 2 2006.161.08:00:12.78#ibcon#read 6, iclass 15, count 2 2006.161.08:00:12.78#ibcon#end of sib2, iclass 15, count 2 2006.161.08:00:12.78#ibcon#*after write, iclass 15, count 2 2006.161.08:00:12.78#ibcon#*before return 0, iclass 15, count 2 2006.161.08:00:12.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:12.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:00:12.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:00:12.79#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:12.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:12.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:12.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:12.89#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:00:12.89#ibcon#first serial, iclass 15, count 0 2006.161.08:00:12.89#ibcon#enter sib2, iclass 15, count 0 2006.161.08:00:12.89#ibcon#flushed, iclass 15, count 0 2006.161.08:00:12.89#ibcon#about to write, iclass 15, count 0 2006.161.08:00:12.89#ibcon#wrote, iclass 15, count 0 2006.161.08:00:12.89#ibcon#about to read 3, iclass 15, count 0 2006.161.08:00:12.91#ibcon#read 3, iclass 15, count 0 2006.161.08:00:12.91#ibcon#about to read 4, iclass 15, count 0 2006.161.08:00:12.91#ibcon#read 4, iclass 15, count 0 2006.161.08:00:12.91#ibcon#about to read 5, iclass 15, count 0 2006.161.08:00:12.91#ibcon#read 5, iclass 15, count 0 2006.161.08:00:12.91#ibcon#about to read 6, iclass 15, count 0 2006.161.08:00:12.91#ibcon#read 6, iclass 15, count 0 2006.161.08:00:12.91#ibcon#end of sib2, iclass 15, count 0 2006.161.08:00:12.91#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:00:12.92#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:00:12.92#ibcon#[27=USB\r\n] 2006.161.08:00:12.92#ibcon#*before write, iclass 15, count 0 2006.161.08:00:12.92#ibcon#enter sib2, iclass 15, count 0 2006.161.08:00:12.92#ibcon#flushed, iclass 15, count 0 2006.161.08:00:12.92#ibcon#about to write, iclass 15, count 0 2006.161.08:00:12.92#ibcon#wrote, iclass 15, count 0 2006.161.08:00:12.92#ibcon#about to read 3, iclass 15, count 0 2006.161.08:00:12.94#ibcon#read 3, iclass 15, count 0 2006.161.08:00:12.94#ibcon#about to read 4, iclass 15, count 0 2006.161.08:00:12.94#ibcon#read 4, iclass 15, count 0 2006.161.08:00:12.94#ibcon#about to read 5, iclass 15, count 0 2006.161.08:00:12.94#ibcon#read 5, iclass 15, count 0 2006.161.08:00:12.94#ibcon#about to read 6, iclass 15, count 0 2006.161.08:00:12.94#ibcon#read 6, iclass 15, count 0 2006.161.08:00:12.94#ibcon#end of sib2, iclass 15, count 0 2006.161.08:00:12.94#ibcon#*after write, iclass 15, count 0 2006.161.08:00:12.94#ibcon#*before return 0, iclass 15, count 0 2006.161.08:00:12.94#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:12.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:00:12.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:00:12.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:00:12.95$vc4f8/vblo=4,712.99 2006.161.08:00:12.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:00:12.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:00:12.95#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:12.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:12.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:12.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:12.95#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:00:12.95#ibcon#first serial, iclass 17, count 0 2006.161.08:00:12.95#ibcon#enter sib2, iclass 17, count 0 2006.161.08:00:12.95#ibcon#flushed, iclass 17, count 0 2006.161.08:00:12.95#ibcon#about to write, iclass 17, count 0 2006.161.08:00:12.95#ibcon#wrote, iclass 17, count 0 2006.161.08:00:12.95#ibcon#about to read 3, iclass 17, count 0 2006.161.08:00:12.96#ibcon#read 3, iclass 17, count 0 2006.161.08:00:12.96#ibcon#about to read 4, iclass 17, count 0 2006.161.08:00:12.96#ibcon#read 4, iclass 17, count 0 2006.161.08:00:12.96#ibcon#about to read 5, iclass 17, count 0 2006.161.08:00:12.96#ibcon#read 5, iclass 17, count 0 2006.161.08:00:12.96#ibcon#about to read 6, iclass 17, count 0 2006.161.08:00:12.96#ibcon#read 6, iclass 17, count 0 2006.161.08:00:12.96#ibcon#end of sib2, iclass 17, count 0 2006.161.08:00:12.96#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:00:12.96#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:00:12.96#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:00:12.96#ibcon#*before write, iclass 17, count 0 2006.161.08:00:12.97#ibcon#enter sib2, iclass 17, count 0 2006.161.08:00:12.97#ibcon#flushed, iclass 17, count 0 2006.161.08:00:12.97#ibcon#about to write, iclass 17, count 0 2006.161.08:00:12.97#ibcon#wrote, iclass 17, count 0 2006.161.08:00:12.97#ibcon#about to read 3, iclass 17, count 0 2006.161.08:00:13.00#ibcon#read 3, iclass 17, count 0 2006.161.08:00:13.00#ibcon#about to read 4, iclass 17, count 0 2006.161.08:00:13.00#ibcon#read 4, iclass 17, count 0 2006.161.08:00:13.00#ibcon#about to read 5, iclass 17, count 0 2006.161.08:00:13.00#ibcon#read 5, iclass 17, count 0 2006.161.08:00:13.00#ibcon#about to read 6, iclass 17, count 0 2006.161.08:00:13.00#ibcon#read 6, iclass 17, count 0 2006.161.08:00:13.00#ibcon#end of sib2, iclass 17, count 0 2006.161.08:00:13.00#ibcon#*after write, iclass 17, count 0 2006.161.08:00:13.00#ibcon#*before return 0, iclass 17, count 0 2006.161.08:00:13.00#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:13.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:00:13.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:00:13.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:00:13.01$vc4f8/vb=4,4 2006.161.08:00:13.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:00:13.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:00:13.01#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:13.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:13.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:13.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:13.06#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:00:13.06#ibcon#first serial, iclass 19, count 2 2006.161.08:00:13.06#ibcon#enter sib2, iclass 19, count 2 2006.161.08:00:13.06#ibcon#flushed, iclass 19, count 2 2006.161.08:00:13.06#ibcon#about to write, iclass 19, count 2 2006.161.08:00:13.06#ibcon#wrote, iclass 19, count 2 2006.161.08:00:13.06#ibcon#about to read 3, iclass 19, count 2 2006.161.08:00:13.08#ibcon#read 3, iclass 19, count 2 2006.161.08:00:13.08#ibcon#about to read 4, iclass 19, count 2 2006.161.08:00:13.08#ibcon#read 4, iclass 19, count 2 2006.161.08:00:13.08#ibcon#about to read 5, iclass 19, count 2 2006.161.08:00:13.08#ibcon#read 5, iclass 19, count 2 2006.161.08:00:13.08#ibcon#about to read 6, iclass 19, count 2 2006.161.08:00:13.08#ibcon#read 6, iclass 19, count 2 2006.161.08:00:13.08#ibcon#end of sib2, iclass 19, count 2 2006.161.08:00:13.08#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:00:13.08#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:00:13.08#ibcon#[27=AT04-04\r\n] 2006.161.08:00:13.08#ibcon#*before write, iclass 19, count 2 2006.161.08:00:13.08#ibcon#enter sib2, iclass 19, count 2 2006.161.08:00:13.09#ibcon#flushed, iclass 19, count 2 2006.161.08:00:13.09#ibcon#about to write, iclass 19, count 2 2006.161.08:00:13.09#ibcon#wrote, iclass 19, count 2 2006.161.08:00:13.09#ibcon#about to read 3, iclass 19, count 2 2006.161.08:00:13.11#ibcon#read 3, iclass 19, count 2 2006.161.08:00:13.11#ibcon#about to read 4, iclass 19, count 2 2006.161.08:00:13.11#ibcon#read 4, iclass 19, count 2 2006.161.08:00:13.11#ibcon#about to read 5, iclass 19, count 2 2006.161.08:00:13.11#ibcon#read 5, iclass 19, count 2 2006.161.08:00:13.11#ibcon#about to read 6, iclass 19, count 2 2006.161.08:00:13.11#ibcon#read 6, iclass 19, count 2 2006.161.08:00:13.11#ibcon#end of sib2, iclass 19, count 2 2006.161.08:00:13.11#ibcon#*after write, iclass 19, count 2 2006.161.08:00:13.11#ibcon#*before return 0, iclass 19, count 2 2006.161.08:00:13.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:13.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:00:13.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:00:13.12#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:13.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:13.23#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:13.23#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:13.23#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:00:13.23#ibcon#first serial, iclass 19, count 0 2006.161.08:00:13.23#ibcon#enter sib2, iclass 19, count 0 2006.161.08:00:13.23#ibcon#flushed, iclass 19, count 0 2006.161.08:00:13.23#ibcon#about to write, iclass 19, count 0 2006.161.08:00:13.23#ibcon#wrote, iclass 19, count 0 2006.161.08:00:13.23#ibcon#about to read 3, iclass 19, count 0 2006.161.08:00:13.25#ibcon#read 3, iclass 19, count 0 2006.161.08:00:13.25#ibcon#about to read 4, iclass 19, count 0 2006.161.08:00:13.25#ibcon#read 4, iclass 19, count 0 2006.161.08:00:13.25#ibcon#about to read 5, iclass 19, count 0 2006.161.08:00:13.25#ibcon#read 5, iclass 19, count 0 2006.161.08:00:13.25#ibcon#about to read 6, iclass 19, count 0 2006.161.08:00:13.25#ibcon#read 6, iclass 19, count 0 2006.161.08:00:13.25#ibcon#end of sib2, iclass 19, count 0 2006.161.08:00:13.25#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:00:13.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:00:13.25#ibcon#[27=USB\r\n] 2006.161.08:00:13.25#ibcon#*before write, iclass 19, count 0 2006.161.08:00:13.26#ibcon#enter sib2, iclass 19, count 0 2006.161.08:00:13.26#ibcon#flushed, iclass 19, count 0 2006.161.08:00:13.26#ibcon#about to write, iclass 19, count 0 2006.161.08:00:13.26#ibcon#wrote, iclass 19, count 0 2006.161.08:00:13.26#ibcon#about to read 3, iclass 19, count 0 2006.161.08:00:13.28#ibcon#read 3, iclass 19, count 0 2006.161.08:00:13.28#ibcon#about to read 4, iclass 19, count 0 2006.161.08:00:13.28#ibcon#read 4, iclass 19, count 0 2006.161.08:00:13.28#ibcon#about to read 5, iclass 19, count 0 2006.161.08:00:13.28#ibcon#read 5, iclass 19, count 0 2006.161.08:00:13.28#ibcon#about to read 6, iclass 19, count 0 2006.161.08:00:13.28#ibcon#read 6, iclass 19, count 0 2006.161.08:00:13.28#ibcon#end of sib2, iclass 19, count 0 2006.161.08:00:13.28#ibcon#*after write, iclass 19, count 0 2006.161.08:00:13.28#ibcon#*before return 0, iclass 19, count 0 2006.161.08:00:13.28#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:13.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:00:13.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:00:13.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:00:13.29$vc4f8/vblo=5,744.99 2006.161.08:00:13.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:00:13.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:00:13.29#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:13.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:13.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:13.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:13.29#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:00:13.29#ibcon#first serial, iclass 21, count 0 2006.161.08:00:13.29#ibcon#enter sib2, iclass 21, count 0 2006.161.08:00:13.29#ibcon#flushed, iclass 21, count 0 2006.161.08:00:13.29#ibcon#about to write, iclass 21, count 0 2006.161.08:00:13.29#ibcon#wrote, iclass 21, count 0 2006.161.08:00:13.29#ibcon#about to read 3, iclass 21, count 0 2006.161.08:00:13.30#ibcon#read 3, iclass 21, count 0 2006.161.08:00:13.30#ibcon#about to read 4, iclass 21, count 0 2006.161.08:00:13.30#ibcon#read 4, iclass 21, count 0 2006.161.08:00:13.30#ibcon#about to read 5, iclass 21, count 0 2006.161.08:00:13.30#ibcon#read 5, iclass 21, count 0 2006.161.08:00:13.30#ibcon#about to read 6, iclass 21, count 0 2006.161.08:00:13.30#ibcon#read 6, iclass 21, count 0 2006.161.08:00:13.30#ibcon#end of sib2, iclass 21, count 0 2006.161.08:00:13.30#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:00:13.30#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:00:13.30#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:00:13.30#ibcon#*before write, iclass 21, count 0 2006.161.08:00:13.30#ibcon#enter sib2, iclass 21, count 0 2006.161.08:00:13.31#ibcon#flushed, iclass 21, count 0 2006.161.08:00:13.31#ibcon#about to write, iclass 21, count 0 2006.161.08:00:13.31#ibcon#wrote, iclass 21, count 0 2006.161.08:00:13.31#ibcon#about to read 3, iclass 21, count 0 2006.161.08:00:13.34#ibcon#read 3, iclass 21, count 0 2006.161.08:00:13.34#ibcon#about to read 4, iclass 21, count 0 2006.161.08:00:13.34#ibcon#read 4, iclass 21, count 0 2006.161.08:00:13.34#ibcon#about to read 5, iclass 21, count 0 2006.161.08:00:13.34#ibcon#read 5, iclass 21, count 0 2006.161.08:00:13.34#ibcon#about to read 6, iclass 21, count 0 2006.161.08:00:13.34#ibcon#read 6, iclass 21, count 0 2006.161.08:00:13.34#ibcon#end of sib2, iclass 21, count 0 2006.161.08:00:13.34#ibcon#*after write, iclass 21, count 0 2006.161.08:00:13.34#ibcon#*before return 0, iclass 21, count 0 2006.161.08:00:13.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:13.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:00:13.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:00:13.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:00:13.35$vc4f8/vb=5,4 2006.161.08:00:13.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:00:13.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:00:13.35#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:13.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:13.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:13.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:13.40#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:00:13.40#ibcon#first serial, iclass 23, count 2 2006.161.08:00:13.40#ibcon#enter sib2, iclass 23, count 2 2006.161.08:00:13.40#ibcon#flushed, iclass 23, count 2 2006.161.08:00:13.40#ibcon#about to write, iclass 23, count 2 2006.161.08:00:13.40#ibcon#wrote, iclass 23, count 2 2006.161.08:00:13.40#ibcon#about to read 3, iclass 23, count 2 2006.161.08:00:13.42#ibcon#read 3, iclass 23, count 2 2006.161.08:00:13.42#ibcon#about to read 4, iclass 23, count 2 2006.161.08:00:13.42#ibcon#read 4, iclass 23, count 2 2006.161.08:00:13.42#ibcon#about to read 5, iclass 23, count 2 2006.161.08:00:13.42#ibcon#read 5, iclass 23, count 2 2006.161.08:00:13.42#ibcon#about to read 6, iclass 23, count 2 2006.161.08:00:13.42#ibcon#read 6, iclass 23, count 2 2006.161.08:00:13.42#ibcon#end of sib2, iclass 23, count 2 2006.161.08:00:13.42#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:00:13.42#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:00:13.42#ibcon#[27=AT05-04\r\n] 2006.161.08:00:13.42#ibcon#*before write, iclass 23, count 2 2006.161.08:00:13.42#ibcon#enter sib2, iclass 23, count 2 2006.161.08:00:13.43#ibcon#flushed, iclass 23, count 2 2006.161.08:00:13.43#ibcon#about to write, iclass 23, count 2 2006.161.08:00:13.43#ibcon#wrote, iclass 23, count 2 2006.161.08:00:13.43#ibcon#about to read 3, iclass 23, count 2 2006.161.08:00:13.45#ibcon#read 3, iclass 23, count 2 2006.161.08:00:13.45#ibcon#about to read 4, iclass 23, count 2 2006.161.08:00:13.45#ibcon#read 4, iclass 23, count 2 2006.161.08:00:13.45#ibcon#about to read 5, iclass 23, count 2 2006.161.08:00:13.45#ibcon#read 5, iclass 23, count 2 2006.161.08:00:13.45#ibcon#about to read 6, iclass 23, count 2 2006.161.08:00:13.45#ibcon#read 6, iclass 23, count 2 2006.161.08:00:13.45#ibcon#end of sib2, iclass 23, count 2 2006.161.08:00:13.45#ibcon#*after write, iclass 23, count 2 2006.161.08:00:13.45#ibcon#*before return 0, iclass 23, count 2 2006.161.08:00:13.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:13.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:00:13.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:00:13.46#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:13.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:13.57#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:13.57#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:13.57#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:00:13.57#ibcon#first serial, iclass 23, count 0 2006.161.08:00:13.57#ibcon#enter sib2, iclass 23, count 0 2006.161.08:00:13.57#ibcon#flushed, iclass 23, count 0 2006.161.08:00:13.57#ibcon#about to write, iclass 23, count 0 2006.161.08:00:13.57#ibcon#wrote, iclass 23, count 0 2006.161.08:00:13.57#ibcon#about to read 3, iclass 23, count 0 2006.161.08:00:13.59#ibcon#read 3, iclass 23, count 0 2006.161.08:00:13.59#ibcon#about to read 4, iclass 23, count 0 2006.161.08:00:13.59#ibcon#read 4, iclass 23, count 0 2006.161.08:00:13.59#ibcon#about to read 5, iclass 23, count 0 2006.161.08:00:13.59#ibcon#read 5, iclass 23, count 0 2006.161.08:00:13.59#ibcon#about to read 6, iclass 23, count 0 2006.161.08:00:13.59#ibcon#read 6, iclass 23, count 0 2006.161.08:00:13.59#ibcon#end of sib2, iclass 23, count 0 2006.161.08:00:13.59#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:00:13.59#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:00:13.59#ibcon#[27=USB\r\n] 2006.161.08:00:13.59#ibcon#*before write, iclass 23, count 0 2006.161.08:00:13.60#ibcon#enter sib2, iclass 23, count 0 2006.161.08:00:13.60#ibcon#flushed, iclass 23, count 0 2006.161.08:00:13.60#ibcon#about to write, iclass 23, count 0 2006.161.08:00:13.60#ibcon#wrote, iclass 23, count 0 2006.161.08:00:13.60#ibcon#about to read 3, iclass 23, count 0 2006.161.08:00:13.62#ibcon#read 3, iclass 23, count 0 2006.161.08:00:13.62#ibcon#about to read 4, iclass 23, count 0 2006.161.08:00:13.62#ibcon#read 4, iclass 23, count 0 2006.161.08:00:13.62#ibcon#about to read 5, iclass 23, count 0 2006.161.08:00:13.62#ibcon#read 5, iclass 23, count 0 2006.161.08:00:13.62#ibcon#about to read 6, iclass 23, count 0 2006.161.08:00:13.62#ibcon#read 6, iclass 23, count 0 2006.161.08:00:13.62#ibcon#end of sib2, iclass 23, count 0 2006.161.08:00:13.62#ibcon#*after write, iclass 23, count 0 2006.161.08:00:13.62#ibcon#*before return 0, iclass 23, count 0 2006.161.08:00:13.62#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:13.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:00:13.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:00:13.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:00:13.63$vc4f8/vblo=6,752.99 2006.161.08:00:13.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:00:13.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:00:13.63#ibcon#ireg 17 cls_cnt 0 2006.161.08:00:13.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:13.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:13.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:13.63#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:00:13.63#ibcon#first serial, iclass 25, count 0 2006.161.08:00:13.63#ibcon#enter sib2, iclass 25, count 0 2006.161.08:00:13.63#ibcon#flushed, iclass 25, count 0 2006.161.08:00:13.63#ibcon#about to write, iclass 25, count 0 2006.161.08:00:13.63#ibcon#wrote, iclass 25, count 0 2006.161.08:00:13.63#ibcon#about to read 3, iclass 25, count 0 2006.161.08:00:13.64#ibcon#read 3, iclass 25, count 0 2006.161.08:00:13.64#ibcon#about to read 4, iclass 25, count 0 2006.161.08:00:13.64#ibcon#read 4, iclass 25, count 0 2006.161.08:00:13.64#ibcon#about to read 5, iclass 25, count 0 2006.161.08:00:13.64#ibcon#read 5, iclass 25, count 0 2006.161.08:00:13.64#ibcon#about to read 6, iclass 25, count 0 2006.161.08:00:13.64#ibcon#read 6, iclass 25, count 0 2006.161.08:00:13.64#ibcon#end of sib2, iclass 25, count 0 2006.161.08:00:13.64#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:00:13.64#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:00:13.64#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:00:13.64#ibcon#*before write, iclass 25, count 0 2006.161.08:00:13.65#ibcon#enter sib2, iclass 25, count 0 2006.161.08:00:13.65#ibcon#flushed, iclass 25, count 0 2006.161.08:00:13.65#ibcon#about to write, iclass 25, count 0 2006.161.08:00:13.65#ibcon#wrote, iclass 25, count 0 2006.161.08:00:13.65#ibcon#about to read 3, iclass 25, count 0 2006.161.08:00:13.68#ibcon#read 3, iclass 25, count 0 2006.161.08:00:13.68#ibcon#about to read 4, iclass 25, count 0 2006.161.08:00:13.68#ibcon#read 4, iclass 25, count 0 2006.161.08:00:13.68#ibcon#about to read 5, iclass 25, count 0 2006.161.08:00:13.68#ibcon#read 5, iclass 25, count 0 2006.161.08:00:13.68#ibcon#about to read 6, iclass 25, count 0 2006.161.08:00:13.68#ibcon#read 6, iclass 25, count 0 2006.161.08:00:13.68#ibcon#end of sib2, iclass 25, count 0 2006.161.08:00:13.68#ibcon#*after write, iclass 25, count 0 2006.161.08:00:13.68#ibcon#*before return 0, iclass 25, count 0 2006.161.08:00:13.68#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:13.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:00:13.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:00:13.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:00:13.69$vc4f8/vb=6,4 2006.161.08:00:13.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:00:13.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:00:13.69#ibcon#ireg 11 cls_cnt 2 2006.161.08:00:13.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:13.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:13.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:13.74#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:00:13.74#ibcon#first serial, iclass 27, count 2 2006.161.08:00:13.74#ibcon#enter sib2, iclass 27, count 2 2006.161.08:00:13.74#ibcon#flushed, iclass 27, count 2 2006.161.08:00:13.74#ibcon#about to write, iclass 27, count 2 2006.161.08:00:13.74#ibcon#wrote, iclass 27, count 2 2006.161.08:00:13.74#ibcon#about to read 3, iclass 27, count 2 2006.161.08:00:13.76#ibcon#read 3, iclass 27, count 2 2006.161.08:00:13.76#ibcon#about to read 4, iclass 27, count 2 2006.161.08:00:13.76#ibcon#read 4, iclass 27, count 2 2006.161.08:00:13.76#ibcon#about to read 5, iclass 27, count 2 2006.161.08:00:13.76#ibcon#read 5, iclass 27, count 2 2006.161.08:00:13.76#ibcon#about to read 6, iclass 27, count 2 2006.161.08:00:13.76#ibcon#read 6, iclass 27, count 2 2006.161.08:00:13.76#ibcon#end of sib2, iclass 27, count 2 2006.161.08:00:13.76#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:00:13.76#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:00:13.76#ibcon#[27=AT06-04\r\n] 2006.161.08:00:13.76#ibcon#*before write, iclass 27, count 2 2006.161.08:00:13.77#ibcon#enter sib2, iclass 27, count 2 2006.161.08:00:13.77#ibcon#flushed, iclass 27, count 2 2006.161.08:00:13.77#ibcon#about to write, iclass 27, count 2 2006.161.08:00:13.77#ibcon#wrote, iclass 27, count 2 2006.161.08:00:13.77#ibcon#about to read 3, iclass 27, count 2 2006.161.08:00:13.79#ibcon#read 3, iclass 27, count 2 2006.161.08:00:13.79#ibcon#about to read 4, iclass 27, count 2 2006.161.08:00:13.79#ibcon#read 4, iclass 27, count 2 2006.161.08:00:13.79#ibcon#about to read 5, iclass 27, count 2 2006.161.08:00:13.79#ibcon#read 5, iclass 27, count 2 2006.161.08:00:13.79#ibcon#about to read 6, iclass 27, count 2 2006.161.08:00:13.79#ibcon#read 6, iclass 27, count 2 2006.161.08:00:13.79#ibcon#end of sib2, iclass 27, count 2 2006.161.08:00:13.79#ibcon#*after write, iclass 27, count 2 2006.161.08:00:13.79#ibcon#*before return 0, iclass 27, count 2 2006.161.08:00:13.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:13.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:00:13.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:00:13.80#ibcon#ireg 7 cls_cnt 0 2006.161.08:00:13.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:13.91#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:13.91#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:13.91#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:00:13.91#ibcon#first serial, iclass 27, count 0 2006.161.08:00:13.91#ibcon#enter sib2, iclass 27, count 0 2006.161.08:00:13.91#ibcon#flushed, iclass 27, count 0 2006.161.08:00:13.91#ibcon#about to write, iclass 27, count 0 2006.161.08:00:13.91#ibcon#wrote, iclass 27, count 0 2006.161.08:00:13.91#ibcon#about to read 3, iclass 27, count 0 2006.161.08:00:13.93#ibcon#read 3, iclass 27, count 0 2006.161.08:00:13.93#ibcon#about to read 4, iclass 27, count 0 2006.161.08:00:13.93#ibcon#read 4, iclass 27, count 0 2006.161.08:00:13.93#ibcon#about to read 5, iclass 27, count 0 2006.161.08:00:13.93#ibcon#read 5, iclass 27, count 0 2006.161.08:00:13.93#ibcon#about to read 6, iclass 27, count 0 2006.161.08:00:13.93#ibcon#read 6, iclass 27, count 0 2006.161.08:00:13.93#ibcon#end of sib2, iclass 27, count 0 2006.161.08:00:13.93#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:00:13.93#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:00:13.93#ibcon#[27=USB\r\n] 2006.161.08:00:13.93#ibcon#*before write, iclass 27, count 0 2006.161.08:00:13.94#ibcon#enter sib2, iclass 27, count 0 2006.161.08:00:13.94#ibcon#flushed, iclass 27, count 0 2006.161.08:00:13.94#ibcon#about to write, iclass 27, count 0 2006.161.08:00:13.94#ibcon#wrote, iclass 27, count 0 2006.161.08:00:13.94#ibcon#about to read 3, iclass 27, count 0 2006.161.08:00:13.96#ibcon#read 3, iclass 27, count 0 2006.161.08:00:13.96#ibcon#about to read 4, iclass 27, count 0 2006.161.08:00:13.96#ibcon#read 4, iclass 27, count 0 2006.161.08:00:13.96#ibcon#about to read 5, iclass 27, count 0 2006.161.08:00:13.96#ibcon#read 5, iclass 27, count 0 2006.161.08:00:13.96#ibcon#about to read 6, iclass 27, count 0 2006.161.08:00:13.96#ibcon#read 6, iclass 27, count 0 2006.161.08:00:13.96#ibcon#end of sib2, iclass 27, count 0 2006.161.08:00:13.96#ibcon#*after write, iclass 27, count 0 2006.161.08:00:13.96#ibcon#*before return 0, iclass 27, count 0 2006.161.08:00:13.96#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:13.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:00:13.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:00:13.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:00:13.97$vc4f8/vabw=wide 2006.161.08:00:13.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:00:13.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:00:13.97#ibcon#ireg 8 cls_cnt 0 2006.161.08:00:13.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:13.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:13.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:13.97#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:00:13.97#ibcon#first serial, iclass 29, count 0 2006.161.08:00:13.97#ibcon#enter sib2, iclass 29, count 0 2006.161.08:00:13.97#ibcon#flushed, iclass 29, count 0 2006.161.08:00:13.97#ibcon#about to write, iclass 29, count 0 2006.161.08:00:13.97#ibcon#wrote, iclass 29, count 0 2006.161.08:00:13.97#ibcon#about to read 3, iclass 29, count 0 2006.161.08:00:13.98#ibcon#read 3, iclass 29, count 0 2006.161.08:00:13.98#ibcon#about to read 4, iclass 29, count 0 2006.161.08:00:13.98#ibcon#read 4, iclass 29, count 0 2006.161.08:00:13.98#ibcon#about to read 5, iclass 29, count 0 2006.161.08:00:13.98#ibcon#read 5, iclass 29, count 0 2006.161.08:00:13.98#ibcon#about to read 6, iclass 29, count 0 2006.161.08:00:13.98#ibcon#read 6, iclass 29, count 0 2006.161.08:00:13.98#ibcon#end of sib2, iclass 29, count 0 2006.161.08:00:13.98#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:00:13.98#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:00:13.98#ibcon#[25=BW32\r\n] 2006.161.08:00:13.98#ibcon#*before write, iclass 29, count 0 2006.161.08:00:13.99#ibcon#enter sib2, iclass 29, count 0 2006.161.08:00:13.99#ibcon#flushed, iclass 29, count 0 2006.161.08:00:13.99#ibcon#about to write, iclass 29, count 0 2006.161.08:00:13.99#ibcon#wrote, iclass 29, count 0 2006.161.08:00:13.99#ibcon#about to read 3, iclass 29, count 0 2006.161.08:00:14.01#ibcon#read 3, iclass 29, count 0 2006.161.08:00:14.01#ibcon#about to read 4, iclass 29, count 0 2006.161.08:00:14.01#ibcon#read 4, iclass 29, count 0 2006.161.08:00:14.01#ibcon#about to read 5, iclass 29, count 0 2006.161.08:00:14.01#ibcon#read 5, iclass 29, count 0 2006.161.08:00:14.01#ibcon#about to read 6, iclass 29, count 0 2006.161.08:00:14.01#ibcon#read 6, iclass 29, count 0 2006.161.08:00:14.01#ibcon#end of sib2, iclass 29, count 0 2006.161.08:00:14.01#ibcon#*after write, iclass 29, count 0 2006.161.08:00:14.01#ibcon#*before return 0, iclass 29, count 0 2006.161.08:00:14.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:14.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:00:14.02#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:00:14.02#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:00:14.02$vc4f8/vbbw=wide 2006.161.08:00:14.02#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:00:14.02#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:00:14.02#ibcon#ireg 8 cls_cnt 0 2006.161.08:00:14.02#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:00:14.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:00:14.08#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:00:14.08#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:00:14.08#ibcon#first serial, iclass 31, count 0 2006.161.08:00:14.08#ibcon#enter sib2, iclass 31, count 0 2006.161.08:00:14.08#ibcon#flushed, iclass 31, count 0 2006.161.08:00:14.08#ibcon#about to write, iclass 31, count 0 2006.161.08:00:14.08#ibcon#wrote, iclass 31, count 0 2006.161.08:00:14.08#ibcon#about to read 3, iclass 31, count 0 2006.161.08:00:14.10#ibcon#read 3, iclass 31, count 0 2006.161.08:00:14.10#ibcon#about to read 4, iclass 31, count 0 2006.161.08:00:14.10#ibcon#read 4, iclass 31, count 0 2006.161.08:00:14.10#ibcon#about to read 5, iclass 31, count 0 2006.161.08:00:14.10#ibcon#read 5, iclass 31, count 0 2006.161.08:00:14.10#ibcon#about to read 6, iclass 31, count 0 2006.161.08:00:14.10#ibcon#read 6, iclass 31, count 0 2006.161.08:00:14.10#ibcon#end of sib2, iclass 31, count 0 2006.161.08:00:14.10#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:00:14.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:00:14.10#ibcon#[27=BW32\r\n] 2006.161.08:00:14.10#ibcon#*before write, iclass 31, count 0 2006.161.08:00:14.10#ibcon#enter sib2, iclass 31, count 0 2006.161.08:00:14.11#ibcon#flushed, iclass 31, count 0 2006.161.08:00:14.11#ibcon#about to write, iclass 31, count 0 2006.161.08:00:14.11#ibcon#wrote, iclass 31, count 0 2006.161.08:00:14.11#ibcon#about to read 3, iclass 31, count 0 2006.161.08:00:14.13#ibcon#read 3, iclass 31, count 0 2006.161.08:00:14.13#ibcon#about to read 4, iclass 31, count 0 2006.161.08:00:14.13#ibcon#read 4, iclass 31, count 0 2006.161.08:00:14.13#ibcon#about to read 5, iclass 31, count 0 2006.161.08:00:14.13#ibcon#read 5, iclass 31, count 0 2006.161.08:00:14.13#ibcon#about to read 6, iclass 31, count 0 2006.161.08:00:14.13#ibcon#read 6, iclass 31, count 0 2006.161.08:00:14.13#ibcon#end of sib2, iclass 31, count 0 2006.161.08:00:14.13#ibcon#*after write, iclass 31, count 0 2006.161.08:00:14.13#ibcon#*before return 0, iclass 31, count 0 2006.161.08:00:14.13#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:00:14.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:00:14.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:00:14.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:00:14.14$4f8m12a/ifd4f 2006.161.08:00:14.14$ifd4f/lo= 2006.161.08:00:14.14$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:00:14.14$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:00:14.14$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:00:14.14$ifd4f/patch= 2006.161.08:00:14.14$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:00:14.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:00:14.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:00:14.14$4f8m12a/"form=m,16.000,1:2 2006.161.08:00:14.14$4f8m12a/"tpicd 2006.161.08:00:14.14$4f8m12a/echo=off 2006.161.08:00:14.14$4f8m12a/xlog=off 2006.161.08:00:14.14:!2006.161.08:01:20 2006.161.08:00:58.14#trakl#Source acquired 2006.161.08:00:58.15#flagr#flagr/antenna,acquired 2006.161.08:01:20.02:preob 2006.161.08:01:21.15/onsource/TRACKING 2006.161.08:01:21.15:!2006.161.08:01:30 2006.161.08:01:30.02:data_valid=on 2006.161.08:01:30.02:midob 2006.161.08:01:31.15/onsource/TRACKING 2006.161.08:01:31.15/wx/24.02,1002.2,86 2006.161.08:01:31.24/cable/+6.4983E-03 2006.161.08:01:32.33/va/01,08,usb,yes,28,30 2006.161.08:01:32.33/va/02,07,usb,yes,29,30 2006.161.08:01:32.33/va/03,06,usb,yes,30,30 2006.161.08:01:32.33/va/04,07,usb,yes,29,32 2006.161.08:01:32.33/va/05,07,usb,yes,29,31 2006.161.08:01:32.33/va/06,06,usb,yes,28,28 2006.161.08:01:32.33/va/07,06,usb,yes,29,29 2006.161.08:01:32.33/va/08,07,usb,yes,27,27 2006.161.08:01:32.56/valo/01,532.99,yes,locked 2006.161.08:01:32.56/valo/02,572.99,yes,locked 2006.161.08:01:32.56/valo/03,672.99,yes,locked 2006.161.08:01:32.56/valo/04,832.99,yes,locked 2006.161.08:01:32.56/valo/05,652.99,yes,locked 2006.161.08:01:32.56/valo/06,772.99,yes,locked 2006.161.08:01:32.56/valo/07,832.99,yes,locked 2006.161.08:01:32.56/valo/08,852.99,yes,locked 2006.161.08:01:33.65/vb/01,04,usb,yes,29,27 2006.161.08:01:33.65/vb/02,04,usb,yes,30,32 2006.161.08:01:33.65/vb/03,04,usb,yes,27,31 2006.161.08:01:33.65/vb/04,04,usb,yes,28,28 2006.161.08:01:33.65/vb/05,04,usb,yes,26,30 2006.161.08:01:33.65/vb/06,04,usb,yes,27,30 2006.161.08:01:33.65/vb/07,04,usb,yes,29,29 2006.161.08:01:33.65/vb/08,04,usb,yes,27,30 2006.161.08:01:33.88/vblo/01,632.99,yes,locked 2006.161.08:01:33.88/vblo/02,640.99,yes,locked 2006.161.08:01:33.88/vblo/03,656.99,yes,locked 2006.161.08:01:33.88/vblo/04,712.99,yes,locked 2006.161.08:01:33.88/vblo/05,744.99,yes,locked 2006.161.08:01:33.88/vblo/06,752.99,yes,locked 2006.161.08:01:33.88/vblo/07,734.99,yes,locked 2006.161.08:01:33.88/vblo/08,744.99,yes,locked 2006.161.08:01:34.03/vabw/8 2006.161.08:01:34.18/vbbw/8 2006.161.08:01:34.31/xfe/off,on,14.2 2006.161.08:01:34.69/ifatt/23,28,28,28 2006.161.08:01:35.07/fmout-gps/S +4.49E-07 2006.161.08:01:35.12:!2006.161.08:02:30 2006.161.08:02:30.01:data_valid=off 2006.161.08:02:30.02:postob 2006.161.08:02:30.13/cable/+6.5008E-03 2006.161.08:02:30.14/wx/24.02,1002.2,86 2006.161.08:02:31.08/fmout-gps/S +4.49E-07 2006.161.08:02:31.09:scan_name=161-0803,k06161,60 2006.161.08:02:31.09:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.161.08:02:32.14#flagr#flagr/antenna,new-source 2006.161.08:02:32.15:checkk5 2006.161.08:02:32.61/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:02:33.04/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:02:33.45/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:02:33.87/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:02:34.49/chk_obsdata//k5ts1/T1610801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:02:34.92/chk_obsdata//k5ts2/T1610801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:02:35.34/chk_obsdata//k5ts3/T1610801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:02:35.81/chk_obsdata//k5ts4/T1610801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:02:36.72/k5log//k5ts1_log_newline 2006.161.08:02:37.53/k5log//k5ts2_log_newline 2006.161.08:02:38.52/k5log//k5ts3_log_newline 2006.161.08:02:39.33/k5log//k5ts4_log_newline 2006.161.08:02:39.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:02:39.35:4f8m12a=2 2006.161.08:02:39.36$4f8m12a/echo=on 2006.161.08:02:39.36$4f8m12a/pcalon 2006.161.08:02:39.36$pcalon/"no phase cal control is implemented here 2006.161.08:02:39.36$4f8m12a/"tpicd=stop 2006.161.08:02:39.36$4f8m12a/vc4f8 2006.161.08:02:39.36$vc4f8/valo=1,532.99 2006.161.08:02:39.36#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:02:39.36#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:02:39.36#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:39.36#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:39.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:39.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:39.36#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:02:39.36#ibcon#first serial, iclass 22, count 0 2006.161.08:02:39.36#ibcon#enter sib2, iclass 22, count 0 2006.161.08:02:39.36#ibcon#flushed, iclass 22, count 0 2006.161.08:02:39.36#ibcon#about to write, iclass 22, count 0 2006.161.08:02:39.36#ibcon#wrote, iclass 22, count 0 2006.161.08:02:39.36#ibcon#about to read 3, iclass 22, count 0 2006.161.08:02:39.40#ibcon#read 3, iclass 22, count 0 2006.161.08:02:39.40#ibcon#about to read 4, iclass 22, count 0 2006.161.08:02:39.40#ibcon#read 4, iclass 22, count 0 2006.161.08:02:39.40#ibcon#about to read 5, iclass 22, count 0 2006.161.08:02:39.40#ibcon#read 5, iclass 22, count 0 2006.161.08:02:39.40#ibcon#about to read 6, iclass 22, count 0 2006.161.08:02:39.40#ibcon#read 6, iclass 22, count 0 2006.161.08:02:39.40#ibcon#end of sib2, iclass 22, count 0 2006.161.08:02:39.40#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:02:39.40#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:02:39.40#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:02:39.40#ibcon#*before write, iclass 22, count 0 2006.161.08:02:39.40#ibcon#enter sib2, iclass 22, count 0 2006.161.08:02:39.40#ibcon#flushed, iclass 22, count 0 2006.161.08:02:39.40#ibcon#about to write, iclass 22, count 0 2006.161.08:02:39.40#ibcon#wrote, iclass 22, count 0 2006.161.08:02:39.40#ibcon#about to read 3, iclass 22, count 0 2006.161.08:02:39.44#ibcon#read 3, iclass 22, count 0 2006.161.08:02:39.44#ibcon#about to read 4, iclass 22, count 0 2006.161.08:02:39.44#ibcon#read 4, iclass 22, count 0 2006.161.08:02:39.44#ibcon#about to read 5, iclass 22, count 0 2006.161.08:02:39.44#ibcon#read 5, iclass 22, count 0 2006.161.08:02:39.44#ibcon#about to read 6, iclass 22, count 0 2006.161.08:02:39.44#ibcon#read 6, iclass 22, count 0 2006.161.08:02:39.44#ibcon#end of sib2, iclass 22, count 0 2006.161.08:02:39.44#ibcon#*after write, iclass 22, count 0 2006.161.08:02:39.44#ibcon#*before return 0, iclass 22, count 0 2006.161.08:02:39.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:39.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:39.44#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:02:39.44#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:02:39.44$vc4f8/va=1,8 2006.161.08:02:39.44#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:02:39.44#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:02:39.44#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:39.44#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:39.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:39.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:39.44#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:02:39.44#ibcon#first serial, iclass 24, count 2 2006.161.08:02:39.44#ibcon#enter sib2, iclass 24, count 2 2006.161.08:02:39.44#ibcon#flushed, iclass 24, count 2 2006.161.08:02:39.44#ibcon#about to write, iclass 24, count 2 2006.161.08:02:39.44#ibcon#wrote, iclass 24, count 2 2006.161.08:02:39.44#ibcon#about to read 3, iclass 24, count 2 2006.161.08:02:39.46#ibcon#read 3, iclass 24, count 2 2006.161.08:02:39.46#ibcon#about to read 4, iclass 24, count 2 2006.161.08:02:39.46#ibcon#read 4, iclass 24, count 2 2006.161.08:02:39.46#ibcon#about to read 5, iclass 24, count 2 2006.161.08:02:39.46#ibcon#read 5, iclass 24, count 2 2006.161.08:02:39.46#ibcon#about to read 6, iclass 24, count 2 2006.161.08:02:39.46#ibcon#read 6, iclass 24, count 2 2006.161.08:02:39.46#ibcon#end of sib2, iclass 24, count 2 2006.161.08:02:39.46#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:02:39.46#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:02:39.46#ibcon#[25=AT01-08\r\n] 2006.161.08:02:39.46#ibcon#*before write, iclass 24, count 2 2006.161.08:02:39.46#ibcon#enter sib2, iclass 24, count 2 2006.161.08:02:39.46#ibcon#flushed, iclass 24, count 2 2006.161.08:02:39.46#ibcon#about to write, iclass 24, count 2 2006.161.08:02:39.46#ibcon#wrote, iclass 24, count 2 2006.161.08:02:39.46#ibcon#about to read 3, iclass 24, count 2 2006.161.08:02:39.49#ibcon#read 3, iclass 24, count 2 2006.161.08:02:39.49#ibcon#about to read 4, iclass 24, count 2 2006.161.08:02:39.49#ibcon#read 4, iclass 24, count 2 2006.161.08:02:39.50#ibcon#about to read 5, iclass 24, count 2 2006.161.08:02:39.50#ibcon#read 5, iclass 24, count 2 2006.161.08:02:39.50#ibcon#about to read 6, iclass 24, count 2 2006.161.08:02:39.50#ibcon#read 6, iclass 24, count 2 2006.161.08:02:39.50#ibcon#end of sib2, iclass 24, count 2 2006.161.08:02:39.50#ibcon#*after write, iclass 24, count 2 2006.161.08:02:39.50#ibcon#*before return 0, iclass 24, count 2 2006.161.08:02:39.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:39.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:39.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:02:39.50#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:39.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:39.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:39.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:39.62#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:02:39.62#ibcon#first serial, iclass 24, count 0 2006.161.08:02:39.62#ibcon#enter sib2, iclass 24, count 0 2006.161.08:02:39.62#ibcon#flushed, iclass 24, count 0 2006.161.08:02:39.62#ibcon#about to write, iclass 24, count 0 2006.161.08:02:39.62#ibcon#wrote, iclass 24, count 0 2006.161.08:02:39.62#ibcon#about to read 3, iclass 24, count 0 2006.161.08:02:39.63#ibcon#read 3, iclass 24, count 0 2006.161.08:02:39.63#ibcon#about to read 4, iclass 24, count 0 2006.161.08:02:39.63#ibcon#read 4, iclass 24, count 0 2006.161.08:02:39.63#ibcon#about to read 5, iclass 24, count 0 2006.161.08:02:39.63#ibcon#read 5, iclass 24, count 0 2006.161.08:02:39.63#ibcon#about to read 6, iclass 24, count 0 2006.161.08:02:39.63#ibcon#read 6, iclass 24, count 0 2006.161.08:02:39.63#ibcon#end of sib2, iclass 24, count 0 2006.161.08:02:39.63#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:02:39.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:02:39.63#ibcon#[25=USB\r\n] 2006.161.08:02:39.63#ibcon#*before write, iclass 24, count 0 2006.161.08:02:39.63#ibcon#enter sib2, iclass 24, count 0 2006.161.08:02:39.63#ibcon#flushed, iclass 24, count 0 2006.161.08:02:39.63#ibcon#about to write, iclass 24, count 0 2006.161.08:02:39.63#ibcon#wrote, iclass 24, count 0 2006.161.08:02:39.63#ibcon#about to read 3, iclass 24, count 0 2006.161.08:02:39.66#ibcon#read 3, iclass 24, count 0 2006.161.08:02:39.66#ibcon#about to read 4, iclass 24, count 0 2006.161.08:02:39.66#ibcon#read 4, iclass 24, count 0 2006.161.08:02:39.66#ibcon#about to read 5, iclass 24, count 0 2006.161.08:02:39.66#ibcon#read 5, iclass 24, count 0 2006.161.08:02:39.66#ibcon#about to read 6, iclass 24, count 0 2006.161.08:02:39.66#ibcon#read 6, iclass 24, count 0 2006.161.08:02:39.66#ibcon#end of sib2, iclass 24, count 0 2006.161.08:02:39.66#ibcon#*after write, iclass 24, count 0 2006.161.08:02:39.66#ibcon#*before return 0, iclass 24, count 0 2006.161.08:02:39.66#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:39.66#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:39.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:02:39.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:02:39.66$vc4f8/valo=2,572.99 2006.161.08:02:39.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:02:39.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:02:39.66#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:39.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:39.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:39.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:39.66#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:02:39.66#ibcon#first serial, iclass 26, count 0 2006.161.08:02:39.66#ibcon#enter sib2, iclass 26, count 0 2006.161.08:02:39.66#ibcon#flushed, iclass 26, count 0 2006.161.08:02:39.66#ibcon#about to write, iclass 26, count 0 2006.161.08:02:39.66#ibcon#wrote, iclass 26, count 0 2006.161.08:02:39.66#ibcon#about to read 3, iclass 26, count 0 2006.161.08:02:39.69#ibcon#read 3, iclass 26, count 0 2006.161.08:02:39.69#ibcon#about to read 4, iclass 26, count 0 2006.161.08:02:39.69#ibcon#read 4, iclass 26, count 0 2006.161.08:02:39.69#ibcon#about to read 5, iclass 26, count 0 2006.161.08:02:39.69#ibcon#read 5, iclass 26, count 0 2006.161.08:02:39.69#ibcon#about to read 6, iclass 26, count 0 2006.161.08:02:39.69#ibcon#read 6, iclass 26, count 0 2006.161.08:02:39.69#ibcon#end of sib2, iclass 26, count 0 2006.161.08:02:39.69#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:02:39.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:02:39.69#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:02:39.69#ibcon#*before write, iclass 26, count 0 2006.161.08:02:39.69#ibcon#enter sib2, iclass 26, count 0 2006.161.08:02:39.69#ibcon#flushed, iclass 26, count 0 2006.161.08:02:39.69#ibcon#about to write, iclass 26, count 0 2006.161.08:02:39.69#ibcon#wrote, iclass 26, count 0 2006.161.08:02:39.69#ibcon#about to read 3, iclass 26, count 0 2006.161.08:02:39.73#ibcon#read 3, iclass 26, count 0 2006.161.08:02:39.73#ibcon#about to read 4, iclass 26, count 0 2006.161.08:02:39.73#ibcon#read 4, iclass 26, count 0 2006.161.08:02:39.73#ibcon#about to read 5, iclass 26, count 0 2006.161.08:02:39.73#ibcon#read 5, iclass 26, count 0 2006.161.08:02:39.73#ibcon#about to read 6, iclass 26, count 0 2006.161.08:02:39.73#ibcon#read 6, iclass 26, count 0 2006.161.08:02:39.73#ibcon#end of sib2, iclass 26, count 0 2006.161.08:02:39.73#ibcon#*after write, iclass 26, count 0 2006.161.08:02:39.73#ibcon#*before return 0, iclass 26, count 0 2006.161.08:02:39.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:39.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:39.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:02:39.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:02:39.73$vc4f8/va=2,7 2006.161.08:02:39.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:02:39.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:02:39.73#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:39.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:39.79#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:39.79#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:39.79#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:02:39.79#ibcon#first serial, iclass 28, count 2 2006.161.08:02:39.79#ibcon#enter sib2, iclass 28, count 2 2006.161.08:02:39.79#ibcon#flushed, iclass 28, count 2 2006.161.08:02:39.79#ibcon#about to write, iclass 28, count 2 2006.161.08:02:39.79#ibcon#wrote, iclass 28, count 2 2006.161.08:02:39.79#ibcon#about to read 3, iclass 28, count 2 2006.161.08:02:39.80#ibcon#read 3, iclass 28, count 2 2006.161.08:02:39.80#ibcon#about to read 4, iclass 28, count 2 2006.161.08:02:39.80#ibcon#read 4, iclass 28, count 2 2006.161.08:02:39.80#ibcon#about to read 5, iclass 28, count 2 2006.161.08:02:39.80#ibcon#read 5, iclass 28, count 2 2006.161.08:02:39.80#ibcon#about to read 6, iclass 28, count 2 2006.161.08:02:39.80#ibcon#read 6, iclass 28, count 2 2006.161.08:02:39.80#ibcon#end of sib2, iclass 28, count 2 2006.161.08:02:39.80#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:02:39.80#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:02:39.80#ibcon#[25=AT02-07\r\n] 2006.161.08:02:39.80#ibcon#*before write, iclass 28, count 2 2006.161.08:02:39.80#ibcon#enter sib2, iclass 28, count 2 2006.161.08:02:39.80#ibcon#flushed, iclass 28, count 2 2006.161.08:02:39.80#ibcon#about to write, iclass 28, count 2 2006.161.08:02:39.80#ibcon#wrote, iclass 28, count 2 2006.161.08:02:39.80#ibcon#about to read 3, iclass 28, count 2 2006.161.08:02:39.83#ibcon#read 3, iclass 28, count 2 2006.161.08:02:39.83#ibcon#about to read 4, iclass 28, count 2 2006.161.08:02:39.83#ibcon#read 4, iclass 28, count 2 2006.161.08:02:39.83#ibcon#about to read 5, iclass 28, count 2 2006.161.08:02:39.83#ibcon#read 5, iclass 28, count 2 2006.161.08:02:39.83#ibcon#about to read 6, iclass 28, count 2 2006.161.08:02:39.83#ibcon#read 6, iclass 28, count 2 2006.161.08:02:39.83#ibcon#end of sib2, iclass 28, count 2 2006.161.08:02:39.83#ibcon#*after write, iclass 28, count 2 2006.161.08:02:39.83#ibcon#*before return 0, iclass 28, count 2 2006.161.08:02:39.83#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:39.83#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:39.83#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:02:39.83#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:39.83#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:39.95#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:39.95#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:39.95#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:02:39.95#ibcon#first serial, iclass 28, count 0 2006.161.08:02:39.95#ibcon#enter sib2, iclass 28, count 0 2006.161.08:02:39.95#ibcon#flushed, iclass 28, count 0 2006.161.08:02:39.95#ibcon#about to write, iclass 28, count 0 2006.161.08:02:39.95#ibcon#wrote, iclass 28, count 0 2006.161.08:02:39.95#ibcon#about to read 3, iclass 28, count 0 2006.161.08:02:39.97#ibcon#read 3, iclass 28, count 0 2006.161.08:02:39.97#ibcon#about to read 4, iclass 28, count 0 2006.161.08:02:39.97#ibcon#read 4, iclass 28, count 0 2006.161.08:02:39.97#ibcon#about to read 5, iclass 28, count 0 2006.161.08:02:39.97#ibcon#read 5, iclass 28, count 0 2006.161.08:02:39.97#ibcon#about to read 6, iclass 28, count 0 2006.161.08:02:39.97#ibcon#read 6, iclass 28, count 0 2006.161.08:02:39.97#ibcon#end of sib2, iclass 28, count 0 2006.161.08:02:39.97#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:02:39.97#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:02:39.97#ibcon#[25=USB\r\n] 2006.161.08:02:39.97#ibcon#*before write, iclass 28, count 0 2006.161.08:02:39.97#ibcon#enter sib2, iclass 28, count 0 2006.161.08:02:39.97#ibcon#flushed, iclass 28, count 0 2006.161.08:02:39.97#ibcon#about to write, iclass 28, count 0 2006.161.08:02:39.97#ibcon#wrote, iclass 28, count 0 2006.161.08:02:39.97#ibcon#about to read 3, iclass 28, count 0 2006.161.08:02:40.00#ibcon#read 3, iclass 28, count 0 2006.161.08:02:40.00#ibcon#about to read 4, iclass 28, count 0 2006.161.08:02:40.00#ibcon#read 4, iclass 28, count 0 2006.161.08:02:40.00#ibcon#about to read 5, iclass 28, count 0 2006.161.08:02:40.00#ibcon#read 5, iclass 28, count 0 2006.161.08:02:40.00#ibcon#about to read 6, iclass 28, count 0 2006.161.08:02:40.00#ibcon#read 6, iclass 28, count 0 2006.161.08:02:40.00#ibcon#end of sib2, iclass 28, count 0 2006.161.08:02:40.00#ibcon#*after write, iclass 28, count 0 2006.161.08:02:40.00#ibcon#*before return 0, iclass 28, count 0 2006.161.08:02:40.00#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:40.00#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:40.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:02:40.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:02:40.00$vc4f8/valo=3,672.99 2006.161.08:02:40.00#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:02:40.00#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:02:40.00#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:40.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:40.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:40.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:40.00#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:02:40.00#ibcon#first serial, iclass 30, count 0 2006.161.08:02:40.00#ibcon#enter sib2, iclass 30, count 0 2006.161.08:02:40.00#ibcon#flushed, iclass 30, count 0 2006.161.08:02:40.00#ibcon#about to write, iclass 30, count 0 2006.161.08:02:40.00#ibcon#wrote, iclass 30, count 0 2006.161.08:02:40.00#ibcon#about to read 3, iclass 30, count 0 2006.161.08:02:40.02#ibcon#read 3, iclass 30, count 0 2006.161.08:02:40.02#ibcon#about to read 4, iclass 30, count 0 2006.161.08:02:40.02#ibcon#read 4, iclass 30, count 0 2006.161.08:02:40.02#ibcon#about to read 5, iclass 30, count 0 2006.161.08:02:40.02#ibcon#read 5, iclass 30, count 0 2006.161.08:02:40.02#ibcon#about to read 6, iclass 30, count 0 2006.161.08:02:40.02#ibcon#read 6, iclass 30, count 0 2006.161.08:02:40.02#ibcon#end of sib2, iclass 30, count 0 2006.161.08:02:40.02#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:02:40.02#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:02:40.02#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:02:40.02#ibcon#*before write, iclass 30, count 0 2006.161.08:02:40.02#ibcon#enter sib2, iclass 30, count 0 2006.161.08:02:40.02#ibcon#flushed, iclass 30, count 0 2006.161.08:02:40.02#ibcon#about to write, iclass 30, count 0 2006.161.08:02:40.02#ibcon#wrote, iclass 30, count 0 2006.161.08:02:40.02#ibcon#about to read 3, iclass 30, count 0 2006.161.08:02:40.06#ibcon#read 3, iclass 30, count 0 2006.161.08:02:40.06#ibcon#about to read 4, iclass 30, count 0 2006.161.08:02:40.06#ibcon#read 4, iclass 30, count 0 2006.161.08:02:40.06#ibcon#about to read 5, iclass 30, count 0 2006.161.08:02:40.06#ibcon#read 5, iclass 30, count 0 2006.161.08:02:40.06#ibcon#about to read 6, iclass 30, count 0 2006.161.08:02:40.06#ibcon#read 6, iclass 30, count 0 2006.161.08:02:40.06#ibcon#end of sib2, iclass 30, count 0 2006.161.08:02:40.06#ibcon#*after write, iclass 30, count 0 2006.161.08:02:40.06#ibcon#*before return 0, iclass 30, count 0 2006.161.08:02:40.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:40.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:40.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:02:40.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:02:40.06$vc4f8/va=3,6 2006.161.08:02:40.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:02:40.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:02:40.06#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:40.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:40.13#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:40.13#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:40.13#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:02:40.13#ibcon#first serial, iclass 32, count 2 2006.161.08:02:40.13#ibcon#enter sib2, iclass 32, count 2 2006.161.08:02:40.13#ibcon#flushed, iclass 32, count 2 2006.161.08:02:40.13#ibcon#about to write, iclass 32, count 2 2006.161.08:02:40.13#ibcon#wrote, iclass 32, count 2 2006.161.08:02:40.13#ibcon#about to read 3, iclass 32, count 2 2006.161.08:02:40.15#ibcon#read 3, iclass 32, count 2 2006.161.08:02:40.15#ibcon#about to read 4, iclass 32, count 2 2006.161.08:02:40.15#ibcon#read 4, iclass 32, count 2 2006.161.08:02:40.15#ibcon#about to read 5, iclass 32, count 2 2006.161.08:02:40.15#ibcon#read 5, iclass 32, count 2 2006.161.08:02:40.15#ibcon#about to read 6, iclass 32, count 2 2006.161.08:02:40.15#ibcon#read 6, iclass 32, count 2 2006.161.08:02:40.15#ibcon#end of sib2, iclass 32, count 2 2006.161.08:02:40.15#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:02:40.15#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:02:40.15#ibcon#[25=AT03-06\r\n] 2006.161.08:02:40.15#ibcon#*before write, iclass 32, count 2 2006.161.08:02:40.15#ibcon#enter sib2, iclass 32, count 2 2006.161.08:02:40.15#ibcon#flushed, iclass 32, count 2 2006.161.08:02:40.15#ibcon#about to write, iclass 32, count 2 2006.161.08:02:40.15#ibcon#wrote, iclass 32, count 2 2006.161.08:02:40.15#ibcon#about to read 3, iclass 32, count 2 2006.161.08:02:40.17#ibcon#read 3, iclass 32, count 2 2006.161.08:02:40.17#ibcon#about to read 4, iclass 32, count 2 2006.161.08:02:40.17#ibcon#read 4, iclass 32, count 2 2006.161.08:02:40.17#ibcon#about to read 5, iclass 32, count 2 2006.161.08:02:40.17#ibcon#read 5, iclass 32, count 2 2006.161.08:02:40.17#ibcon#about to read 6, iclass 32, count 2 2006.161.08:02:40.17#ibcon#read 6, iclass 32, count 2 2006.161.08:02:40.17#ibcon#end of sib2, iclass 32, count 2 2006.161.08:02:40.17#ibcon#*after write, iclass 32, count 2 2006.161.08:02:40.17#ibcon#*before return 0, iclass 32, count 2 2006.161.08:02:40.17#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:40.17#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:40.17#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:02:40.17#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:40.17#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:40.29#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:40.29#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:40.29#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:02:40.29#ibcon#first serial, iclass 32, count 0 2006.161.08:02:40.29#ibcon#enter sib2, iclass 32, count 0 2006.161.08:02:40.29#ibcon#flushed, iclass 32, count 0 2006.161.08:02:40.29#ibcon#about to write, iclass 32, count 0 2006.161.08:02:40.29#ibcon#wrote, iclass 32, count 0 2006.161.08:02:40.29#ibcon#about to read 3, iclass 32, count 0 2006.161.08:02:40.31#ibcon#read 3, iclass 32, count 0 2006.161.08:02:40.31#ibcon#about to read 4, iclass 32, count 0 2006.161.08:02:40.31#ibcon#read 4, iclass 32, count 0 2006.161.08:02:40.31#ibcon#about to read 5, iclass 32, count 0 2006.161.08:02:40.31#ibcon#read 5, iclass 32, count 0 2006.161.08:02:40.31#ibcon#about to read 6, iclass 32, count 0 2006.161.08:02:40.31#ibcon#read 6, iclass 32, count 0 2006.161.08:02:40.31#ibcon#end of sib2, iclass 32, count 0 2006.161.08:02:40.31#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:02:40.31#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:02:40.31#ibcon#[25=USB\r\n] 2006.161.08:02:40.31#ibcon#*before write, iclass 32, count 0 2006.161.08:02:40.31#ibcon#enter sib2, iclass 32, count 0 2006.161.08:02:40.31#ibcon#flushed, iclass 32, count 0 2006.161.08:02:40.31#ibcon#about to write, iclass 32, count 0 2006.161.08:02:40.31#ibcon#wrote, iclass 32, count 0 2006.161.08:02:40.31#ibcon#about to read 3, iclass 32, count 0 2006.161.08:02:40.34#ibcon#read 3, iclass 32, count 0 2006.161.08:02:40.34#ibcon#about to read 4, iclass 32, count 0 2006.161.08:02:40.34#ibcon#read 4, iclass 32, count 0 2006.161.08:02:40.34#ibcon#about to read 5, iclass 32, count 0 2006.161.08:02:40.34#ibcon#read 5, iclass 32, count 0 2006.161.08:02:40.34#ibcon#about to read 6, iclass 32, count 0 2006.161.08:02:40.34#ibcon#read 6, iclass 32, count 0 2006.161.08:02:40.34#ibcon#end of sib2, iclass 32, count 0 2006.161.08:02:40.34#ibcon#*after write, iclass 32, count 0 2006.161.08:02:40.34#ibcon#*before return 0, iclass 32, count 0 2006.161.08:02:40.34#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:40.34#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:40.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:02:40.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:02:40.34$vc4f8/valo=4,832.99 2006.161.08:02:40.34#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:02:40.34#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:02:40.34#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:40.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:40.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:40.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:40.34#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:02:40.34#ibcon#first serial, iclass 34, count 0 2006.161.08:02:40.34#ibcon#enter sib2, iclass 34, count 0 2006.161.08:02:40.34#ibcon#flushed, iclass 34, count 0 2006.161.08:02:40.34#ibcon#about to write, iclass 34, count 0 2006.161.08:02:40.34#ibcon#wrote, iclass 34, count 0 2006.161.08:02:40.34#ibcon#about to read 3, iclass 34, count 0 2006.161.08:02:40.36#ibcon#read 3, iclass 34, count 0 2006.161.08:02:40.36#ibcon#about to read 4, iclass 34, count 0 2006.161.08:02:40.36#ibcon#read 4, iclass 34, count 0 2006.161.08:02:40.36#ibcon#about to read 5, iclass 34, count 0 2006.161.08:02:40.36#ibcon#read 5, iclass 34, count 0 2006.161.08:02:40.36#ibcon#about to read 6, iclass 34, count 0 2006.161.08:02:40.36#ibcon#read 6, iclass 34, count 0 2006.161.08:02:40.36#ibcon#end of sib2, iclass 34, count 0 2006.161.08:02:40.36#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:02:40.36#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:02:40.36#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:02:40.36#ibcon#*before write, iclass 34, count 0 2006.161.08:02:40.36#ibcon#enter sib2, iclass 34, count 0 2006.161.08:02:40.36#ibcon#flushed, iclass 34, count 0 2006.161.08:02:40.36#ibcon#about to write, iclass 34, count 0 2006.161.08:02:40.36#ibcon#wrote, iclass 34, count 0 2006.161.08:02:40.36#ibcon#about to read 3, iclass 34, count 0 2006.161.08:02:40.40#ibcon#read 3, iclass 34, count 0 2006.161.08:02:40.40#ibcon#about to read 4, iclass 34, count 0 2006.161.08:02:40.40#ibcon#read 4, iclass 34, count 0 2006.161.08:02:40.40#ibcon#about to read 5, iclass 34, count 0 2006.161.08:02:40.40#ibcon#read 5, iclass 34, count 0 2006.161.08:02:40.40#ibcon#about to read 6, iclass 34, count 0 2006.161.08:02:40.40#ibcon#read 6, iclass 34, count 0 2006.161.08:02:40.40#ibcon#end of sib2, iclass 34, count 0 2006.161.08:02:40.40#ibcon#*after write, iclass 34, count 0 2006.161.08:02:40.40#ibcon#*before return 0, iclass 34, count 0 2006.161.08:02:40.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:40.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:40.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:02:40.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:02:40.40$vc4f8/va=4,7 2006.161.08:02:40.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:02:40.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:02:40.40#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:40.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:40.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:40.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:40.46#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:02:40.46#ibcon#first serial, iclass 36, count 2 2006.161.08:02:40.46#ibcon#enter sib2, iclass 36, count 2 2006.161.08:02:40.46#ibcon#flushed, iclass 36, count 2 2006.161.08:02:40.46#ibcon#about to write, iclass 36, count 2 2006.161.08:02:40.46#ibcon#wrote, iclass 36, count 2 2006.161.08:02:40.46#ibcon#about to read 3, iclass 36, count 2 2006.161.08:02:40.48#ibcon#read 3, iclass 36, count 2 2006.161.08:02:40.48#ibcon#about to read 4, iclass 36, count 2 2006.161.08:02:40.48#ibcon#read 4, iclass 36, count 2 2006.161.08:02:40.48#ibcon#about to read 5, iclass 36, count 2 2006.161.08:02:40.48#ibcon#read 5, iclass 36, count 2 2006.161.08:02:40.48#ibcon#about to read 6, iclass 36, count 2 2006.161.08:02:40.48#ibcon#read 6, iclass 36, count 2 2006.161.08:02:40.48#ibcon#end of sib2, iclass 36, count 2 2006.161.08:02:40.48#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:02:40.48#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:02:40.48#ibcon#[25=AT04-07\r\n] 2006.161.08:02:40.48#ibcon#*before write, iclass 36, count 2 2006.161.08:02:40.48#ibcon#enter sib2, iclass 36, count 2 2006.161.08:02:40.48#ibcon#flushed, iclass 36, count 2 2006.161.08:02:40.48#ibcon#about to write, iclass 36, count 2 2006.161.08:02:40.48#ibcon#wrote, iclass 36, count 2 2006.161.08:02:40.48#ibcon#about to read 3, iclass 36, count 2 2006.161.08:02:40.51#ibcon#read 3, iclass 36, count 2 2006.161.08:02:40.51#ibcon#about to read 4, iclass 36, count 2 2006.161.08:02:40.51#ibcon#read 4, iclass 36, count 2 2006.161.08:02:40.51#ibcon#about to read 5, iclass 36, count 2 2006.161.08:02:40.51#ibcon#read 5, iclass 36, count 2 2006.161.08:02:40.51#ibcon#about to read 6, iclass 36, count 2 2006.161.08:02:40.51#ibcon#read 6, iclass 36, count 2 2006.161.08:02:40.51#ibcon#end of sib2, iclass 36, count 2 2006.161.08:02:40.51#ibcon#*after write, iclass 36, count 2 2006.161.08:02:40.51#ibcon#*before return 0, iclass 36, count 2 2006.161.08:02:40.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:40.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:40.51#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:02:40.51#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:40.51#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:40.63#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:40.63#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:40.63#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:02:40.63#ibcon#first serial, iclass 36, count 0 2006.161.08:02:40.63#ibcon#enter sib2, iclass 36, count 0 2006.161.08:02:40.63#ibcon#flushed, iclass 36, count 0 2006.161.08:02:40.63#ibcon#about to write, iclass 36, count 0 2006.161.08:02:40.63#ibcon#wrote, iclass 36, count 0 2006.161.08:02:40.63#ibcon#about to read 3, iclass 36, count 0 2006.161.08:02:40.65#ibcon#read 3, iclass 36, count 0 2006.161.08:02:40.65#ibcon#about to read 4, iclass 36, count 0 2006.161.08:02:40.65#ibcon#read 4, iclass 36, count 0 2006.161.08:02:40.65#ibcon#about to read 5, iclass 36, count 0 2006.161.08:02:40.65#ibcon#read 5, iclass 36, count 0 2006.161.08:02:40.65#ibcon#about to read 6, iclass 36, count 0 2006.161.08:02:40.65#ibcon#read 6, iclass 36, count 0 2006.161.08:02:40.65#ibcon#end of sib2, iclass 36, count 0 2006.161.08:02:40.65#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:02:40.65#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:02:40.65#ibcon#[25=USB\r\n] 2006.161.08:02:40.65#ibcon#*before write, iclass 36, count 0 2006.161.08:02:40.65#ibcon#enter sib2, iclass 36, count 0 2006.161.08:02:40.65#ibcon#flushed, iclass 36, count 0 2006.161.08:02:40.65#ibcon#about to write, iclass 36, count 0 2006.161.08:02:40.65#ibcon#wrote, iclass 36, count 0 2006.161.08:02:40.65#ibcon#about to read 3, iclass 36, count 0 2006.161.08:02:40.68#ibcon#read 3, iclass 36, count 0 2006.161.08:02:40.68#ibcon#about to read 4, iclass 36, count 0 2006.161.08:02:40.68#ibcon#read 4, iclass 36, count 0 2006.161.08:02:40.68#ibcon#about to read 5, iclass 36, count 0 2006.161.08:02:40.68#ibcon#read 5, iclass 36, count 0 2006.161.08:02:40.68#ibcon#about to read 6, iclass 36, count 0 2006.161.08:02:40.68#ibcon#read 6, iclass 36, count 0 2006.161.08:02:40.68#ibcon#end of sib2, iclass 36, count 0 2006.161.08:02:40.68#ibcon#*after write, iclass 36, count 0 2006.161.08:02:40.68#ibcon#*before return 0, iclass 36, count 0 2006.161.08:02:40.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:40.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:40.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:02:40.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:02:40.68$vc4f8/valo=5,652.99 2006.161.08:02:40.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:02:40.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:02:40.68#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:40.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:40.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:40.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:40.68#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:02:40.68#ibcon#first serial, iclass 38, count 0 2006.161.08:02:40.68#ibcon#enter sib2, iclass 38, count 0 2006.161.08:02:40.68#ibcon#flushed, iclass 38, count 0 2006.161.08:02:40.68#ibcon#about to write, iclass 38, count 0 2006.161.08:02:40.68#ibcon#wrote, iclass 38, count 0 2006.161.08:02:40.68#ibcon#about to read 3, iclass 38, count 0 2006.161.08:02:40.70#ibcon#read 3, iclass 38, count 0 2006.161.08:02:40.70#ibcon#about to read 4, iclass 38, count 0 2006.161.08:02:40.70#ibcon#read 4, iclass 38, count 0 2006.161.08:02:40.70#ibcon#about to read 5, iclass 38, count 0 2006.161.08:02:40.70#ibcon#read 5, iclass 38, count 0 2006.161.08:02:40.70#ibcon#about to read 6, iclass 38, count 0 2006.161.08:02:40.70#ibcon#read 6, iclass 38, count 0 2006.161.08:02:40.70#ibcon#end of sib2, iclass 38, count 0 2006.161.08:02:40.70#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:02:40.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:02:40.70#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:02:40.70#ibcon#*before write, iclass 38, count 0 2006.161.08:02:40.70#ibcon#enter sib2, iclass 38, count 0 2006.161.08:02:40.70#ibcon#flushed, iclass 38, count 0 2006.161.08:02:40.70#ibcon#about to write, iclass 38, count 0 2006.161.08:02:40.70#ibcon#wrote, iclass 38, count 0 2006.161.08:02:40.70#ibcon#about to read 3, iclass 38, count 0 2006.161.08:02:40.74#ibcon#read 3, iclass 38, count 0 2006.161.08:02:40.74#ibcon#about to read 4, iclass 38, count 0 2006.161.08:02:40.74#ibcon#read 4, iclass 38, count 0 2006.161.08:02:40.74#ibcon#about to read 5, iclass 38, count 0 2006.161.08:02:40.74#ibcon#read 5, iclass 38, count 0 2006.161.08:02:40.74#ibcon#about to read 6, iclass 38, count 0 2006.161.08:02:40.74#ibcon#read 6, iclass 38, count 0 2006.161.08:02:40.74#ibcon#end of sib2, iclass 38, count 0 2006.161.08:02:40.74#ibcon#*after write, iclass 38, count 0 2006.161.08:02:40.74#ibcon#*before return 0, iclass 38, count 0 2006.161.08:02:40.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:40.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:40.74#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:02:40.74#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:02:40.74$vc4f8/va=5,7 2006.161.08:02:40.74#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:02:40.74#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:02:40.74#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:40.74#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:40.81#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:40.81#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:40.81#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:02:40.81#ibcon#first serial, iclass 40, count 2 2006.161.08:02:40.81#ibcon#enter sib2, iclass 40, count 2 2006.161.08:02:40.81#ibcon#flushed, iclass 40, count 2 2006.161.08:02:40.81#ibcon#about to write, iclass 40, count 2 2006.161.08:02:40.81#ibcon#wrote, iclass 40, count 2 2006.161.08:02:40.81#ibcon#about to read 3, iclass 40, count 2 2006.161.08:02:40.83#ibcon#read 3, iclass 40, count 2 2006.161.08:02:40.83#ibcon#about to read 4, iclass 40, count 2 2006.161.08:02:40.83#ibcon#read 4, iclass 40, count 2 2006.161.08:02:40.83#ibcon#about to read 5, iclass 40, count 2 2006.161.08:02:40.83#ibcon#read 5, iclass 40, count 2 2006.161.08:02:40.83#ibcon#about to read 6, iclass 40, count 2 2006.161.08:02:40.83#ibcon#read 6, iclass 40, count 2 2006.161.08:02:40.83#ibcon#end of sib2, iclass 40, count 2 2006.161.08:02:40.83#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:02:40.83#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:02:40.83#ibcon#[25=AT05-07\r\n] 2006.161.08:02:40.83#ibcon#*before write, iclass 40, count 2 2006.161.08:02:40.83#ibcon#enter sib2, iclass 40, count 2 2006.161.08:02:40.83#ibcon#flushed, iclass 40, count 2 2006.161.08:02:40.83#ibcon#about to write, iclass 40, count 2 2006.161.08:02:40.83#ibcon#wrote, iclass 40, count 2 2006.161.08:02:40.83#ibcon#about to read 3, iclass 40, count 2 2006.161.08:02:40.85#ibcon#read 3, iclass 40, count 2 2006.161.08:02:40.85#ibcon#about to read 4, iclass 40, count 2 2006.161.08:02:40.85#ibcon#read 4, iclass 40, count 2 2006.161.08:02:40.85#ibcon#about to read 5, iclass 40, count 2 2006.161.08:02:40.85#ibcon#read 5, iclass 40, count 2 2006.161.08:02:40.85#ibcon#about to read 6, iclass 40, count 2 2006.161.08:02:40.85#ibcon#read 6, iclass 40, count 2 2006.161.08:02:40.85#ibcon#end of sib2, iclass 40, count 2 2006.161.08:02:40.85#ibcon#*after write, iclass 40, count 2 2006.161.08:02:40.85#ibcon#*before return 0, iclass 40, count 2 2006.161.08:02:40.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:40.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:40.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:02:40.85#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:40.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:40.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:40.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:40.97#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:02:40.97#ibcon#first serial, iclass 40, count 0 2006.161.08:02:40.97#ibcon#enter sib2, iclass 40, count 0 2006.161.08:02:40.97#ibcon#flushed, iclass 40, count 0 2006.161.08:02:40.97#ibcon#about to write, iclass 40, count 0 2006.161.08:02:40.97#ibcon#wrote, iclass 40, count 0 2006.161.08:02:40.97#ibcon#about to read 3, iclass 40, count 0 2006.161.08:02:40.99#ibcon#read 3, iclass 40, count 0 2006.161.08:02:40.99#ibcon#about to read 4, iclass 40, count 0 2006.161.08:02:40.99#ibcon#read 4, iclass 40, count 0 2006.161.08:02:40.99#ibcon#about to read 5, iclass 40, count 0 2006.161.08:02:40.99#ibcon#read 5, iclass 40, count 0 2006.161.08:02:40.99#ibcon#about to read 6, iclass 40, count 0 2006.161.08:02:40.99#ibcon#read 6, iclass 40, count 0 2006.161.08:02:40.99#ibcon#end of sib2, iclass 40, count 0 2006.161.08:02:40.99#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:02:40.99#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:02:40.99#ibcon#[25=USB\r\n] 2006.161.08:02:40.99#ibcon#*before write, iclass 40, count 0 2006.161.08:02:40.99#ibcon#enter sib2, iclass 40, count 0 2006.161.08:02:40.99#ibcon#flushed, iclass 40, count 0 2006.161.08:02:40.99#ibcon#about to write, iclass 40, count 0 2006.161.08:02:40.99#ibcon#wrote, iclass 40, count 0 2006.161.08:02:40.99#ibcon#about to read 3, iclass 40, count 0 2006.161.08:02:41.02#ibcon#read 3, iclass 40, count 0 2006.161.08:02:41.02#ibcon#about to read 4, iclass 40, count 0 2006.161.08:02:41.02#ibcon#read 4, iclass 40, count 0 2006.161.08:02:41.02#ibcon#about to read 5, iclass 40, count 0 2006.161.08:02:41.02#ibcon#read 5, iclass 40, count 0 2006.161.08:02:41.02#ibcon#about to read 6, iclass 40, count 0 2006.161.08:02:41.02#ibcon#read 6, iclass 40, count 0 2006.161.08:02:41.02#ibcon#end of sib2, iclass 40, count 0 2006.161.08:02:41.02#ibcon#*after write, iclass 40, count 0 2006.161.08:02:41.02#ibcon#*before return 0, iclass 40, count 0 2006.161.08:02:41.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:41.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:41.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:02:41.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:02:41.02$vc4f8/valo=6,772.99 2006.161.08:02:41.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:02:41.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:02:41.02#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:41.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:41.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:41.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:41.02#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:02:41.02#ibcon#first serial, iclass 4, count 0 2006.161.08:02:41.02#ibcon#enter sib2, iclass 4, count 0 2006.161.08:02:41.02#ibcon#flushed, iclass 4, count 0 2006.161.08:02:41.02#ibcon#about to write, iclass 4, count 0 2006.161.08:02:41.02#ibcon#wrote, iclass 4, count 0 2006.161.08:02:41.03#ibcon#about to read 3, iclass 4, count 0 2006.161.08:02:41.04#ibcon#read 3, iclass 4, count 0 2006.161.08:02:41.04#ibcon#about to read 4, iclass 4, count 0 2006.161.08:02:41.04#ibcon#read 4, iclass 4, count 0 2006.161.08:02:41.04#ibcon#about to read 5, iclass 4, count 0 2006.161.08:02:41.04#ibcon#read 5, iclass 4, count 0 2006.161.08:02:41.04#ibcon#about to read 6, iclass 4, count 0 2006.161.08:02:41.04#ibcon#read 6, iclass 4, count 0 2006.161.08:02:41.04#ibcon#end of sib2, iclass 4, count 0 2006.161.08:02:41.04#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:02:41.04#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:02:41.04#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:02:41.04#ibcon#*before write, iclass 4, count 0 2006.161.08:02:41.04#ibcon#enter sib2, iclass 4, count 0 2006.161.08:02:41.04#ibcon#flushed, iclass 4, count 0 2006.161.08:02:41.04#ibcon#about to write, iclass 4, count 0 2006.161.08:02:41.04#ibcon#wrote, iclass 4, count 0 2006.161.08:02:41.04#ibcon#about to read 3, iclass 4, count 0 2006.161.08:02:41.08#ibcon#read 3, iclass 4, count 0 2006.161.08:02:41.08#ibcon#about to read 4, iclass 4, count 0 2006.161.08:02:41.08#ibcon#read 4, iclass 4, count 0 2006.161.08:02:41.08#ibcon#about to read 5, iclass 4, count 0 2006.161.08:02:41.08#ibcon#read 5, iclass 4, count 0 2006.161.08:02:41.08#ibcon#about to read 6, iclass 4, count 0 2006.161.08:02:41.08#ibcon#read 6, iclass 4, count 0 2006.161.08:02:41.08#ibcon#end of sib2, iclass 4, count 0 2006.161.08:02:41.08#ibcon#*after write, iclass 4, count 0 2006.161.08:02:41.08#ibcon#*before return 0, iclass 4, count 0 2006.161.08:02:41.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:41.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:41.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:02:41.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:02:41.08$vc4f8/va=6,6 2006.161.08:02:41.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:02:41.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:02:41.08#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:41.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:41.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:41.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:41.14#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:02:41.14#ibcon#first serial, iclass 6, count 2 2006.161.08:02:41.14#ibcon#enter sib2, iclass 6, count 2 2006.161.08:02:41.14#ibcon#flushed, iclass 6, count 2 2006.161.08:02:41.14#ibcon#about to write, iclass 6, count 2 2006.161.08:02:41.14#ibcon#wrote, iclass 6, count 2 2006.161.08:02:41.14#ibcon#about to read 3, iclass 6, count 2 2006.161.08:02:41.17#ibcon#read 3, iclass 6, count 2 2006.161.08:02:41.17#ibcon#about to read 4, iclass 6, count 2 2006.161.08:02:41.17#ibcon#read 4, iclass 6, count 2 2006.161.08:02:41.17#ibcon#about to read 5, iclass 6, count 2 2006.161.08:02:41.17#ibcon#read 5, iclass 6, count 2 2006.161.08:02:41.17#ibcon#about to read 6, iclass 6, count 2 2006.161.08:02:41.17#ibcon#read 6, iclass 6, count 2 2006.161.08:02:41.17#ibcon#end of sib2, iclass 6, count 2 2006.161.08:02:41.17#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:02:41.17#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:02:41.17#ibcon#[25=AT06-06\r\n] 2006.161.08:02:41.17#ibcon#*before write, iclass 6, count 2 2006.161.08:02:41.17#ibcon#enter sib2, iclass 6, count 2 2006.161.08:02:41.17#ibcon#flushed, iclass 6, count 2 2006.161.08:02:41.17#ibcon#about to write, iclass 6, count 2 2006.161.08:02:41.17#ibcon#wrote, iclass 6, count 2 2006.161.08:02:41.17#ibcon#about to read 3, iclass 6, count 2 2006.161.08:02:41.19#ibcon#read 3, iclass 6, count 2 2006.161.08:02:41.19#ibcon#about to read 4, iclass 6, count 2 2006.161.08:02:41.19#ibcon#read 4, iclass 6, count 2 2006.161.08:02:41.19#ibcon#about to read 5, iclass 6, count 2 2006.161.08:02:41.19#ibcon#read 5, iclass 6, count 2 2006.161.08:02:41.19#ibcon#about to read 6, iclass 6, count 2 2006.161.08:02:41.19#ibcon#read 6, iclass 6, count 2 2006.161.08:02:41.19#ibcon#end of sib2, iclass 6, count 2 2006.161.08:02:41.19#ibcon#*after write, iclass 6, count 2 2006.161.08:02:41.19#ibcon#*before return 0, iclass 6, count 2 2006.161.08:02:41.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:41.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:41.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:02:41.19#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:41.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:02:41.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:02:41.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:02:41.31#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:02:41.31#ibcon#first serial, iclass 6, count 0 2006.161.08:02:41.31#ibcon#enter sib2, iclass 6, count 0 2006.161.08:02:41.31#ibcon#flushed, iclass 6, count 0 2006.161.08:02:41.31#ibcon#about to write, iclass 6, count 0 2006.161.08:02:41.31#ibcon#wrote, iclass 6, count 0 2006.161.08:02:41.31#ibcon#about to read 3, iclass 6, count 0 2006.161.08:02:41.33#ibcon#read 3, iclass 6, count 0 2006.161.08:02:41.33#ibcon#about to read 4, iclass 6, count 0 2006.161.08:02:41.33#ibcon#read 4, iclass 6, count 0 2006.161.08:02:41.33#ibcon#about to read 5, iclass 6, count 0 2006.161.08:02:41.33#ibcon#read 5, iclass 6, count 0 2006.161.08:02:41.33#ibcon#about to read 6, iclass 6, count 0 2006.161.08:02:41.33#ibcon#read 6, iclass 6, count 0 2006.161.08:02:41.33#ibcon#end of sib2, iclass 6, count 0 2006.161.08:02:41.33#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:02:41.33#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:02:41.33#ibcon#[25=USB\r\n] 2006.161.08:02:41.33#ibcon#*before write, iclass 6, count 0 2006.161.08:02:41.33#ibcon#enter sib2, iclass 6, count 0 2006.161.08:02:41.33#ibcon#flushed, iclass 6, count 0 2006.161.08:02:41.33#ibcon#about to write, iclass 6, count 0 2006.161.08:02:41.33#ibcon#wrote, iclass 6, count 0 2006.161.08:02:41.33#ibcon#about to read 3, iclass 6, count 0 2006.161.08:02:41.36#ibcon#read 3, iclass 6, count 0 2006.161.08:02:41.36#ibcon#about to read 4, iclass 6, count 0 2006.161.08:02:41.36#ibcon#read 4, iclass 6, count 0 2006.161.08:02:41.36#ibcon#about to read 5, iclass 6, count 0 2006.161.08:02:41.36#ibcon#read 5, iclass 6, count 0 2006.161.08:02:41.36#ibcon#about to read 6, iclass 6, count 0 2006.161.08:02:41.36#ibcon#read 6, iclass 6, count 0 2006.161.08:02:41.36#ibcon#end of sib2, iclass 6, count 0 2006.161.08:02:41.36#ibcon#*after write, iclass 6, count 0 2006.161.08:02:41.36#ibcon#*before return 0, iclass 6, count 0 2006.161.08:02:41.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:02:41.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:02:41.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:02:41.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:02:41.36$vc4f8/valo=7,832.99 2006.161.08:02:41.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:02:41.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:02:41.36#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:41.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:02:41.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:02:41.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:02:41.36#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:02:41.36#ibcon#first serial, iclass 10, count 0 2006.161.08:02:41.36#ibcon#enter sib2, iclass 10, count 0 2006.161.08:02:41.36#ibcon#flushed, iclass 10, count 0 2006.161.08:02:41.36#ibcon#about to write, iclass 10, count 0 2006.161.08:02:41.36#ibcon#wrote, iclass 10, count 0 2006.161.08:02:41.36#ibcon#about to read 3, iclass 10, count 0 2006.161.08:02:41.38#ibcon#read 3, iclass 10, count 0 2006.161.08:02:41.38#ibcon#about to read 4, iclass 10, count 0 2006.161.08:02:41.38#ibcon#read 4, iclass 10, count 0 2006.161.08:02:41.38#ibcon#about to read 5, iclass 10, count 0 2006.161.08:02:41.38#ibcon#read 5, iclass 10, count 0 2006.161.08:02:41.38#ibcon#about to read 6, iclass 10, count 0 2006.161.08:02:41.38#ibcon#read 6, iclass 10, count 0 2006.161.08:02:41.38#ibcon#end of sib2, iclass 10, count 0 2006.161.08:02:41.38#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:02:41.38#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:02:41.38#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:02:41.38#ibcon#*before write, iclass 10, count 0 2006.161.08:02:41.38#ibcon#enter sib2, iclass 10, count 0 2006.161.08:02:41.38#ibcon#flushed, iclass 10, count 0 2006.161.08:02:41.38#ibcon#about to write, iclass 10, count 0 2006.161.08:02:41.38#ibcon#wrote, iclass 10, count 0 2006.161.08:02:41.38#ibcon#about to read 3, iclass 10, count 0 2006.161.08:02:41.42#ibcon#read 3, iclass 10, count 0 2006.161.08:02:41.42#ibcon#about to read 4, iclass 10, count 0 2006.161.08:02:41.42#ibcon#read 4, iclass 10, count 0 2006.161.08:02:41.42#ibcon#about to read 5, iclass 10, count 0 2006.161.08:02:41.42#ibcon#read 5, iclass 10, count 0 2006.161.08:02:41.42#ibcon#about to read 6, iclass 10, count 0 2006.161.08:02:41.42#ibcon#read 6, iclass 10, count 0 2006.161.08:02:41.42#ibcon#end of sib2, iclass 10, count 0 2006.161.08:02:41.42#ibcon#*after write, iclass 10, count 0 2006.161.08:02:41.42#ibcon#*before return 0, iclass 10, count 0 2006.161.08:02:41.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:02:41.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:02:41.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:02:41.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:02:41.42$vc4f8/va=7,6 2006.161.08:02:41.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.08:02:41.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.08:02:41.42#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:41.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:02:41.49#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:02:41.49#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:02:41.49#ibcon#enter wrdev, iclass 12, count 2 2006.161.08:02:41.49#ibcon#first serial, iclass 12, count 2 2006.161.08:02:41.49#ibcon#enter sib2, iclass 12, count 2 2006.161.08:02:41.49#ibcon#flushed, iclass 12, count 2 2006.161.08:02:41.49#ibcon#about to write, iclass 12, count 2 2006.161.08:02:41.49#ibcon#wrote, iclass 12, count 2 2006.161.08:02:41.49#ibcon#about to read 3, iclass 12, count 2 2006.161.08:02:41.51#ibcon#read 3, iclass 12, count 2 2006.161.08:02:41.51#ibcon#about to read 4, iclass 12, count 2 2006.161.08:02:41.51#ibcon#read 4, iclass 12, count 2 2006.161.08:02:41.51#ibcon#about to read 5, iclass 12, count 2 2006.161.08:02:41.51#ibcon#read 5, iclass 12, count 2 2006.161.08:02:41.51#ibcon#about to read 6, iclass 12, count 2 2006.161.08:02:41.51#ibcon#read 6, iclass 12, count 2 2006.161.08:02:41.51#ibcon#end of sib2, iclass 12, count 2 2006.161.08:02:41.51#ibcon#*mode == 0, iclass 12, count 2 2006.161.08:02:41.51#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.08:02:41.51#ibcon#[25=AT07-06\r\n] 2006.161.08:02:41.51#ibcon#*before write, iclass 12, count 2 2006.161.08:02:41.51#ibcon#enter sib2, iclass 12, count 2 2006.161.08:02:41.51#ibcon#flushed, iclass 12, count 2 2006.161.08:02:41.51#ibcon#about to write, iclass 12, count 2 2006.161.08:02:41.51#ibcon#wrote, iclass 12, count 2 2006.161.08:02:41.51#ibcon#about to read 3, iclass 12, count 2 2006.161.08:02:41.53#ibcon#read 3, iclass 12, count 2 2006.161.08:02:41.53#ibcon#about to read 4, iclass 12, count 2 2006.161.08:02:41.53#ibcon#read 4, iclass 12, count 2 2006.161.08:02:41.53#ibcon#about to read 5, iclass 12, count 2 2006.161.08:02:41.53#ibcon#read 5, iclass 12, count 2 2006.161.08:02:41.53#ibcon#about to read 6, iclass 12, count 2 2006.161.08:02:41.53#ibcon#read 6, iclass 12, count 2 2006.161.08:02:41.53#ibcon#end of sib2, iclass 12, count 2 2006.161.08:02:41.53#ibcon#*after write, iclass 12, count 2 2006.161.08:02:41.53#ibcon#*before return 0, iclass 12, count 2 2006.161.08:02:41.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:02:41.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:02:41.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.08:02:41.53#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:41.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:02:41.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:02:41.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:02:41.65#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:02:41.65#ibcon#first serial, iclass 12, count 0 2006.161.08:02:41.65#ibcon#enter sib2, iclass 12, count 0 2006.161.08:02:41.65#ibcon#flushed, iclass 12, count 0 2006.161.08:02:41.65#ibcon#about to write, iclass 12, count 0 2006.161.08:02:41.65#ibcon#wrote, iclass 12, count 0 2006.161.08:02:41.65#ibcon#about to read 3, iclass 12, count 0 2006.161.08:02:41.67#ibcon#read 3, iclass 12, count 0 2006.161.08:02:41.67#ibcon#about to read 4, iclass 12, count 0 2006.161.08:02:41.67#ibcon#read 4, iclass 12, count 0 2006.161.08:02:41.67#ibcon#about to read 5, iclass 12, count 0 2006.161.08:02:41.67#ibcon#read 5, iclass 12, count 0 2006.161.08:02:41.67#ibcon#about to read 6, iclass 12, count 0 2006.161.08:02:41.67#ibcon#read 6, iclass 12, count 0 2006.161.08:02:41.67#ibcon#end of sib2, iclass 12, count 0 2006.161.08:02:41.67#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:02:41.67#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:02:41.67#ibcon#[25=USB\r\n] 2006.161.08:02:41.67#ibcon#*before write, iclass 12, count 0 2006.161.08:02:41.67#ibcon#enter sib2, iclass 12, count 0 2006.161.08:02:41.67#ibcon#flushed, iclass 12, count 0 2006.161.08:02:41.67#ibcon#about to write, iclass 12, count 0 2006.161.08:02:41.67#ibcon#wrote, iclass 12, count 0 2006.161.08:02:41.67#ibcon#about to read 3, iclass 12, count 0 2006.161.08:02:41.70#ibcon#read 3, iclass 12, count 0 2006.161.08:02:41.70#ibcon#about to read 4, iclass 12, count 0 2006.161.08:02:41.70#ibcon#read 4, iclass 12, count 0 2006.161.08:02:41.70#ibcon#about to read 5, iclass 12, count 0 2006.161.08:02:41.70#ibcon#read 5, iclass 12, count 0 2006.161.08:02:41.70#ibcon#about to read 6, iclass 12, count 0 2006.161.08:02:41.70#ibcon#read 6, iclass 12, count 0 2006.161.08:02:41.70#ibcon#end of sib2, iclass 12, count 0 2006.161.08:02:41.70#ibcon#*after write, iclass 12, count 0 2006.161.08:02:41.70#ibcon#*before return 0, iclass 12, count 0 2006.161.08:02:41.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:02:41.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:02:41.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:02:41.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:02:41.70$vc4f8/valo=8,852.99 2006.161.08:02:41.70#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:02:41.70#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:02:41.70#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:41.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:02:41.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:02:41.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:02:41.70#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:02:41.70#ibcon#first serial, iclass 14, count 0 2006.161.08:02:41.70#ibcon#enter sib2, iclass 14, count 0 2006.161.08:02:41.70#ibcon#flushed, iclass 14, count 0 2006.161.08:02:41.70#ibcon#about to write, iclass 14, count 0 2006.161.08:02:41.70#ibcon#wrote, iclass 14, count 0 2006.161.08:02:41.70#ibcon#about to read 3, iclass 14, count 0 2006.161.08:02:41.72#ibcon#read 3, iclass 14, count 0 2006.161.08:02:41.72#ibcon#about to read 4, iclass 14, count 0 2006.161.08:02:41.72#ibcon#read 4, iclass 14, count 0 2006.161.08:02:41.72#ibcon#about to read 5, iclass 14, count 0 2006.161.08:02:41.72#ibcon#read 5, iclass 14, count 0 2006.161.08:02:41.72#ibcon#about to read 6, iclass 14, count 0 2006.161.08:02:41.72#ibcon#read 6, iclass 14, count 0 2006.161.08:02:41.72#ibcon#end of sib2, iclass 14, count 0 2006.161.08:02:41.72#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:02:41.72#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:02:41.72#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:02:41.72#ibcon#*before write, iclass 14, count 0 2006.161.08:02:41.72#ibcon#enter sib2, iclass 14, count 0 2006.161.08:02:41.72#ibcon#flushed, iclass 14, count 0 2006.161.08:02:41.72#ibcon#about to write, iclass 14, count 0 2006.161.08:02:41.72#ibcon#wrote, iclass 14, count 0 2006.161.08:02:41.72#ibcon#about to read 3, iclass 14, count 0 2006.161.08:02:41.76#ibcon#read 3, iclass 14, count 0 2006.161.08:02:41.76#ibcon#about to read 4, iclass 14, count 0 2006.161.08:02:41.76#ibcon#read 4, iclass 14, count 0 2006.161.08:02:41.76#ibcon#about to read 5, iclass 14, count 0 2006.161.08:02:41.76#ibcon#read 5, iclass 14, count 0 2006.161.08:02:41.76#ibcon#about to read 6, iclass 14, count 0 2006.161.08:02:41.76#ibcon#read 6, iclass 14, count 0 2006.161.08:02:41.76#ibcon#end of sib2, iclass 14, count 0 2006.161.08:02:41.76#ibcon#*after write, iclass 14, count 0 2006.161.08:02:41.76#ibcon#*before return 0, iclass 14, count 0 2006.161.08:02:41.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:02:41.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:02:41.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:02:41.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:02:41.76$vc4f8/va=8,7 2006.161.08:02:41.76#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.08:02:41.76#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.08:02:41.76#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:41.76#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:02:41.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:02:41.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:02:41.83#ibcon#enter wrdev, iclass 16, count 2 2006.161.08:02:41.83#ibcon#first serial, iclass 16, count 2 2006.161.08:02:41.83#ibcon#enter sib2, iclass 16, count 2 2006.161.08:02:41.83#ibcon#flushed, iclass 16, count 2 2006.161.08:02:41.83#ibcon#about to write, iclass 16, count 2 2006.161.08:02:41.83#ibcon#wrote, iclass 16, count 2 2006.161.08:02:41.83#ibcon#about to read 3, iclass 16, count 2 2006.161.08:02:41.85#ibcon#read 3, iclass 16, count 2 2006.161.08:02:41.85#ibcon#about to read 4, iclass 16, count 2 2006.161.08:02:41.85#ibcon#read 4, iclass 16, count 2 2006.161.08:02:41.85#ibcon#about to read 5, iclass 16, count 2 2006.161.08:02:41.85#ibcon#read 5, iclass 16, count 2 2006.161.08:02:41.85#ibcon#about to read 6, iclass 16, count 2 2006.161.08:02:41.85#ibcon#read 6, iclass 16, count 2 2006.161.08:02:41.85#ibcon#end of sib2, iclass 16, count 2 2006.161.08:02:41.85#ibcon#*mode == 0, iclass 16, count 2 2006.161.08:02:41.85#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.08:02:41.85#ibcon#[25=AT08-07\r\n] 2006.161.08:02:41.85#ibcon#*before write, iclass 16, count 2 2006.161.08:02:41.85#ibcon#enter sib2, iclass 16, count 2 2006.161.08:02:41.85#ibcon#flushed, iclass 16, count 2 2006.161.08:02:41.85#ibcon#about to write, iclass 16, count 2 2006.161.08:02:41.85#ibcon#wrote, iclass 16, count 2 2006.161.08:02:41.85#ibcon#about to read 3, iclass 16, count 2 2006.161.08:02:41.87#ibcon#read 3, iclass 16, count 2 2006.161.08:02:41.87#ibcon#about to read 4, iclass 16, count 2 2006.161.08:02:41.87#ibcon#read 4, iclass 16, count 2 2006.161.08:02:41.87#ibcon#about to read 5, iclass 16, count 2 2006.161.08:02:41.87#ibcon#read 5, iclass 16, count 2 2006.161.08:02:41.87#ibcon#about to read 6, iclass 16, count 2 2006.161.08:02:41.87#ibcon#read 6, iclass 16, count 2 2006.161.08:02:41.87#ibcon#end of sib2, iclass 16, count 2 2006.161.08:02:41.87#ibcon#*after write, iclass 16, count 2 2006.161.08:02:41.87#ibcon#*before return 0, iclass 16, count 2 2006.161.08:02:41.87#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:02:41.87#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:02:41.87#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.08:02:41.87#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:41.87#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:02:41.99#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:02:41.99#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:02:41.99#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:02:41.99#ibcon#first serial, iclass 16, count 0 2006.161.08:02:41.99#ibcon#enter sib2, iclass 16, count 0 2006.161.08:02:41.99#ibcon#flushed, iclass 16, count 0 2006.161.08:02:41.99#ibcon#about to write, iclass 16, count 0 2006.161.08:02:41.99#ibcon#wrote, iclass 16, count 0 2006.161.08:02:41.99#ibcon#about to read 3, iclass 16, count 0 2006.161.08:02:42.01#ibcon#read 3, iclass 16, count 0 2006.161.08:02:42.01#ibcon#about to read 4, iclass 16, count 0 2006.161.08:02:42.01#ibcon#read 4, iclass 16, count 0 2006.161.08:02:42.01#ibcon#about to read 5, iclass 16, count 0 2006.161.08:02:42.01#ibcon#read 5, iclass 16, count 0 2006.161.08:02:42.01#ibcon#about to read 6, iclass 16, count 0 2006.161.08:02:42.01#ibcon#read 6, iclass 16, count 0 2006.161.08:02:42.01#ibcon#end of sib2, iclass 16, count 0 2006.161.08:02:42.01#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:02:42.01#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:02:42.01#ibcon#[25=USB\r\n] 2006.161.08:02:42.01#ibcon#*before write, iclass 16, count 0 2006.161.08:02:42.01#ibcon#enter sib2, iclass 16, count 0 2006.161.08:02:42.01#ibcon#flushed, iclass 16, count 0 2006.161.08:02:42.01#ibcon#about to write, iclass 16, count 0 2006.161.08:02:42.01#ibcon#wrote, iclass 16, count 0 2006.161.08:02:42.01#ibcon#about to read 3, iclass 16, count 0 2006.161.08:02:42.04#ibcon#read 3, iclass 16, count 0 2006.161.08:02:42.04#ibcon#about to read 4, iclass 16, count 0 2006.161.08:02:42.04#ibcon#read 4, iclass 16, count 0 2006.161.08:02:42.04#ibcon#about to read 5, iclass 16, count 0 2006.161.08:02:42.04#ibcon#read 5, iclass 16, count 0 2006.161.08:02:42.04#ibcon#about to read 6, iclass 16, count 0 2006.161.08:02:42.04#ibcon#read 6, iclass 16, count 0 2006.161.08:02:42.04#ibcon#end of sib2, iclass 16, count 0 2006.161.08:02:42.04#ibcon#*after write, iclass 16, count 0 2006.161.08:02:42.04#ibcon#*before return 0, iclass 16, count 0 2006.161.08:02:42.04#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:02:42.04#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:02:42.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:02:42.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:02:42.04$vc4f8/vblo=1,632.99 2006.161.08:02:42.04#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.08:02:42.04#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.08:02:42.04#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:42.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:02:42.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:02:42.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:02:42.04#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:02:42.04#ibcon#first serial, iclass 18, count 0 2006.161.08:02:42.04#ibcon#enter sib2, iclass 18, count 0 2006.161.08:02:42.04#ibcon#flushed, iclass 18, count 0 2006.161.08:02:42.04#ibcon#about to write, iclass 18, count 0 2006.161.08:02:42.04#ibcon#wrote, iclass 18, count 0 2006.161.08:02:42.04#ibcon#about to read 3, iclass 18, count 0 2006.161.08:02:42.06#ibcon#read 3, iclass 18, count 0 2006.161.08:02:42.06#ibcon#about to read 4, iclass 18, count 0 2006.161.08:02:42.06#ibcon#read 4, iclass 18, count 0 2006.161.08:02:42.06#ibcon#about to read 5, iclass 18, count 0 2006.161.08:02:42.06#ibcon#read 5, iclass 18, count 0 2006.161.08:02:42.06#ibcon#about to read 6, iclass 18, count 0 2006.161.08:02:42.06#ibcon#read 6, iclass 18, count 0 2006.161.08:02:42.06#ibcon#end of sib2, iclass 18, count 0 2006.161.08:02:42.06#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:02:42.06#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:02:42.06#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:02:42.06#ibcon#*before write, iclass 18, count 0 2006.161.08:02:42.06#ibcon#enter sib2, iclass 18, count 0 2006.161.08:02:42.06#ibcon#flushed, iclass 18, count 0 2006.161.08:02:42.06#ibcon#about to write, iclass 18, count 0 2006.161.08:02:42.06#ibcon#wrote, iclass 18, count 0 2006.161.08:02:42.06#ibcon#about to read 3, iclass 18, count 0 2006.161.08:02:42.10#ibcon#read 3, iclass 18, count 0 2006.161.08:02:42.10#ibcon#about to read 4, iclass 18, count 0 2006.161.08:02:42.10#ibcon#read 4, iclass 18, count 0 2006.161.08:02:42.10#ibcon#about to read 5, iclass 18, count 0 2006.161.08:02:42.10#ibcon#read 5, iclass 18, count 0 2006.161.08:02:42.10#ibcon#about to read 6, iclass 18, count 0 2006.161.08:02:42.10#ibcon#read 6, iclass 18, count 0 2006.161.08:02:42.10#ibcon#end of sib2, iclass 18, count 0 2006.161.08:02:42.10#ibcon#*after write, iclass 18, count 0 2006.161.08:02:42.10#ibcon#*before return 0, iclass 18, count 0 2006.161.08:02:42.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:02:42.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:02:42.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:02:42.10#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:02:42.10$vc4f8/vb=1,4 2006.161.08:02:42.10#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.08:02:42.10#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.08:02:42.10#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:42.10#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:02:42.10#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:02:42.10#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:02:42.10#ibcon#enter wrdev, iclass 20, count 2 2006.161.08:02:42.10#ibcon#first serial, iclass 20, count 2 2006.161.08:02:42.10#ibcon#enter sib2, iclass 20, count 2 2006.161.08:02:42.10#ibcon#flushed, iclass 20, count 2 2006.161.08:02:42.10#ibcon#about to write, iclass 20, count 2 2006.161.08:02:42.10#ibcon#wrote, iclass 20, count 2 2006.161.08:02:42.10#ibcon#about to read 3, iclass 20, count 2 2006.161.08:02:42.12#ibcon#read 3, iclass 20, count 2 2006.161.08:02:42.12#ibcon#about to read 4, iclass 20, count 2 2006.161.08:02:42.12#ibcon#read 4, iclass 20, count 2 2006.161.08:02:42.12#ibcon#about to read 5, iclass 20, count 2 2006.161.08:02:42.12#ibcon#read 5, iclass 20, count 2 2006.161.08:02:42.12#ibcon#about to read 6, iclass 20, count 2 2006.161.08:02:42.12#ibcon#read 6, iclass 20, count 2 2006.161.08:02:42.12#ibcon#end of sib2, iclass 20, count 2 2006.161.08:02:42.12#ibcon#*mode == 0, iclass 20, count 2 2006.161.08:02:42.12#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.08:02:42.12#ibcon#[27=AT01-04\r\n] 2006.161.08:02:42.12#ibcon#*before write, iclass 20, count 2 2006.161.08:02:42.12#ibcon#enter sib2, iclass 20, count 2 2006.161.08:02:42.12#ibcon#flushed, iclass 20, count 2 2006.161.08:02:42.12#ibcon#about to write, iclass 20, count 2 2006.161.08:02:42.12#ibcon#wrote, iclass 20, count 2 2006.161.08:02:42.12#ibcon#about to read 3, iclass 20, count 2 2006.161.08:02:42.15#ibcon#read 3, iclass 20, count 2 2006.161.08:02:42.16#ibcon#about to read 4, iclass 20, count 2 2006.161.08:02:42.16#ibcon#read 4, iclass 20, count 2 2006.161.08:02:42.16#ibcon#about to read 5, iclass 20, count 2 2006.161.08:02:42.16#ibcon#read 5, iclass 20, count 2 2006.161.08:02:42.16#ibcon#about to read 6, iclass 20, count 2 2006.161.08:02:42.16#ibcon#read 6, iclass 20, count 2 2006.161.08:02:42.16#ibcon#end of sib2, iclass 20, count 2 2006.161.08:02:42.16#ibcon#*after write, iclass 20, count 2 2006.161.08:02:42.16#ibcon#*before return 0, iclass 20, count 2 2006.161.08:02:42.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:02:42.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:02:42.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.08:02:42.16#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:42.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:02:42.27#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:02:42.27#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:02:42.27#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:02:42.27#ibcon#first serial, iclass 20, count 0 2006.161.08:02:42.27#ibcon#enter sib2, iclass 20, count 0 2006.161.08:02:42.27#ibcon#flushed, iclass 20, count 0 2006.161.08:02:42.27#ibcon#about to write, iclass 20, count 0 2006.161.08:02:42.27#ibcon#wrote, iclass 20, count 0 2006.161.08:02:42.27#ibcon#about to read 3, iclass 20, count 0 2006.161.08:02:42.29#ibcon#read 3, iclass 20, count 0 2006.161.08:02:42.29#ibcon#about to read 4, iclass 20, count 0 2006.161.08:02:42.29#ibcon#read 4, iclass 20, count 0 2006.161.08:02:42.29#ibcon#about to read 5, iclass 20, count 0 2006.161.08:02:42.29#ibcon#read 5, iclass 20, count 0 2006.161.08:02:42.29#ibcon#about to read 6, iclass 20, count 0 2006.161.08:02:42.29#ibcon#read 6, iclass 20, count 0 2006.161.08:02:42.29#ibcon#end of sib2, iclass 20, count 0 2006.161.08:02:42.29#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:02:42.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:02:42.29#ibcon#[27=USB\r\n] 2006.161.08:02:42.29#ibcon#*before write, iclass 20, count 0 2006.161.08:02:42.29#ibcon#enter sib2, iclass 20, count 0 2006.161.08:02:42.29#ibcon#flushed, iclass 20, count 0 2006.161.08:02:42.29#ibcon#about to write, iclass 20, count 0 2006.161.08:02:42.29#ibcon#wrote, iclass 20, count 0 2006.161.08:02:42.29#ibcon#about to read 3, iclass 20, count 0 2006.161.08:02:42.32#ibcon#read 3, iclass 20, count 0 2006.161.08:02:42.32#ibcon#about to read 4, iclass 20, count 0 2006.161.08:02:42.32#ibcon#read 4, iclass 20, count 0 2006.161.08:02:42.32#ibcon#about to read 5, iclass 20, count 0 2006.161.08:02:42.32#ibcon#read 5, iclass 20, count 0 2006.161.08:02:42.32#ibcon#about to read 6, iclass 20, count 0 2006.161.08:02:42.32#ibcon#read 6, iclass 20, count 0 2006.161.08:02:42.32#ibcon#end of sib2, iclass 20, count 0 2006.161.08:02:42.32#ibcon#*after write, iclass 20, count 0 2006.161.08:02:42.32#ibcon#*before return 0, iclass 20, count 0 2006.161.08:02:42.32#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:02:42.32#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:02:42.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:02:42.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:02:42.32$vc4f8/vblo=2,640.99 2006.161.08:02:42.32#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:02:42.32#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:02:42.32#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:42.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:42.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:42.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:42.32#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:02:42.32#ibcon#first serial, iclass 22, count 0 2006.161.08:02:42.32#ibcon#enter sib2, iclass 22, count 0 2006.161.08:02:42.32#ibcon#flushed, iclass 22, count 0 2006.161.08:02:42.32#ibcon#about to write, iclass 22, count 0 2006.161.08:02:42.32#ibcon#wrote, iclass 22, count 0 2006.161.08:02:42.32#ibcon#about to read 3, iclass 22, count 0 2006.161.08:02:42.34#ibcon#read 3, iclass 22, count 0 2006.161.08:02:42.34#ibcon#about to read 4, iclass 22, count 0 2006.161.08:02:42.34#ibcon#read 4, iclass 22, count 0 2006.161.08:02:42.34#ibcon#about to read 5, iclass 22, count 0 2006.161.08:02:42.34#ibcon#read 5, iclass 22, count 0 2006.161.08:02:42.34#ibcon#about to read 6, iclass 22, count 0 2006.161.08:02:42.34#ibcon#read 6, iclass 22, count 0 2006.161.08:02:42.34#ibcon#end of sib2, iclass 22, count 0 2006.161.08:02:42.34#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:02:42.34#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:02:42.34#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:02:42.34#ibcon#*before write, iclass 22, count 0 2006.161.08:02:42.34#ibcon#enter sib2, iclass 22, count 0 2006.161.08:02:42.34#ibcon#flushed, iclass 22, count 0 2006.161.08:02:42.34#ibcon#about to write, iclass 22, count 0 2006.161.08:02:42.34#ibcon#wrote, iclass 22, count 0 2006.161.08:02:42.34#ibcon#about to read 3, iclass 22, count 0 2006.161.08:02:42.38#ibcon#read 3, iclass 22, count 0 2006.161.08:02:42.38#ibcon#about to read 4, iclass 22, count 0 2006.161.08:02:42.38#ibcon#read 4, iclass 22, count 0 2006.161.08:02:42.38#ibcon#about to read 5, iclass 22, count 0 2006.161.08:02:42.38#ibcon#read 5, iclass 22, count 0 2006.161.08:02:42.38#ibcon#about to read 6, iclass 22, count 0 2006.161.08:02:42.38#ibcon#read 6, iclass 22, count 0 2006.161.08:02:42.38#ibcon#end of sib2, iclass 22, count 0 2006.161.08:02:42.38#ibcon#*after write, iclass 22, count 0 2006.161.08:02:42.38#ibcon#*before return 0, iclass 22, count 0 2006.161.08:02:42.38#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:42.38#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:02:42.38#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:02:42.38#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:02:42.38$vc4f8/vb=2,4 2006.161.08:02:42.38#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:02:42.38#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:02:42.38#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:42.38#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:42.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:42.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:42.44#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:02:42.44#ibcon#first serial, iclass 24, count 2 2006.161.08:02:42.44#ibcon#enter sib2, iclass 24, count 2 2006.161.08:02:42.44#ibcon#flushed, iclass 24, count 2 2006.161.08:02:42.44#ibcon#about to write, iclass 24, count 2 2006.161.08:02:42.44#ibcon#wrote, iclass 24, count 2 2006.161.08:02:42.44#ibcon#about to read 3, iclass 24, count 2 2006.161.08:02:42.47#ibcon#read 3, iclass 24, count 2 2006.161.08:02:42.47#ibcon#about to read 4, iclass 24, count 2 2006.161.08:02:42.47#ibcon#read 4, iclass 24, count 2 2006.161.08:02:42.47#ibcon#about to read 5, iclass 24, count 2 2006.161.08:02:42.47#ibcon#read 5, iclass 24, count 2 2006.161.08:02:42.47#ibcon#about to read 6, iclass 24, count 2 2006.161.08:02:42.47#ibcon#read 6, iclass 24, count 2 2006.161.08:02:42.47#ibcon#end of sib2, iclass 24, count 2 2006.161.08:02:42.47#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:02:42.47#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:02:42.47#ibcon#[27=AT02-04\r\n] 2006.161.08:02:42.47#ibcon#*before write, iclass 24, count 2 2006.161.08:02:42.47#ibcon#enter sib2, iclass 24, count 2 2006.161.08:02:42.47#ibcon#flushed, iclass 24, count 2 2006.161.08:02:42.47#ibcon#about to write, iclass 24, count 2 2006.161.08:02:42.47#ibcon#wrote, iclass 24, count 2 2006.161.08:02:42.47#ibcon#about to read 3, iclass 24, count 2 2006.161.08:02:42.50#ibcon#read 3, iclass 24, count 2 2006.161.08:02:42.50#ibcon#about to read 4, iclass 24, count 2 2006.161.08:02:42.50#ibcon#read 4, iclass 24, count 2 2006.161.08:02:42.50#ibcon#about to read 5, iclass 24, count 2 2006.161.08:02:42.50#ibcon#read 5, iclass 24, count 2 2006.161.08:02:42.50#ibcon#about to read 6, iclass 24, count 2 2006.161.08:02:42.50#ibcon#read 6, iclass 24, count 2 2006.161.08:02:42.50#ibcon#end of sib2, iclass 24, count 2 2006.161.08:02:42.50#ibcon#*after write, iclass 24, count 2 2006.161.08:02:42.50#ibcon#*before return 0, iclass 24, count 2 2006.161.08:02:42.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:42.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:02:42.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:02:42.50#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:42.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:42.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:42.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:42.62#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:02:42.62#ibcon#first serial, iclass 24, count 0 2006.161.08:02:42.62#ibcon#enter sib2, iclass 24, count 0 2006.161.08:02:42.62#ibcon#flushed, iclass 24, count 0 2006.161.08:02:42.62#ibcon#about to write, iclass 24, count 0 2006.161.08:02:42.62#ibcon#wrote, iclass 24, count 0 2006.161.08:02:42.62#ibcon#about to read 3, iclass 24, count 0 2006.161.08:02:42.64#ibcon#read 3, iclass 24, count 0 2006.161.08:02:42.64#ibcon#about to read 4, iclass 24, count 0 2006.161.08:02:42.64#ibcon#read 4, iclass 24, count 0 2006.161.08:02:42.64#ibcon#about to read 5, iclass 24, count 0 2006.161.08:02:42.64#ibcon#read 5, iclass 24, count 0 2006.161.08:02:42.64#ibcon#about to read 6, iclass 24, count 0 2006.161.08:02:42.64#ibcon#read 6, iclass 24, count 0 2006.161.08:02:42.64#ibcon#end of sib2, iclass 24, count 0 2006.161.08:02:42.64#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:02:42.64#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:02:42.64#ibcon#[27=USB\r\n] 2006.161.08:02:42.64#ibcon#*before write, iclass 24, count 0 2006.161.08:02:42.64#ibcon#enter sib2, iclass 24, count 0 2006.161.08:02:42.64#ibcon#flushed, iclass 24, count 0 2006.161.08:02:42.64#ibcon#about to write, iclass 24, count 0 2006.161.08:02:42.64#ibcon#wrote, iclass 24, count 0 2006.161.08:02:42.64#ibcon#about to read 3, iclass 24, count 0 2006.161.08:02:42.67#ibcon#read 3, iclass 24, count 0 2006.161.08:02:42.67#ibcon#about to read 4, iclass 24, count 0 2006.161.08:02:42.67#ibcon#read 4, iclass 24, count 0 2006.161.08:02:42.67#ibcon#about to read 5, iclass 24, count 0 2006.161.08:02:42.67#ibcon#read 5, iclass 24, count 0 2006.161.08:02:42.67#ibcon#about to read 6, iclass 24, count 0 2006.161.08:02:42.67#ibcon#read 6, iclass 24, count 0 2006.161.08:02:42.67#ibcon#end of sib2, iclass 24, count 0 2006.161.08:02:42.67#ibcon#*after write, iclass 24, count 0 2006.161.08:02:42.67#ibcon#*before return 0, iclass 24, count 0 2006.161.08:02:42.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:42.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:02:42.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:02:42.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:02:42.67$vc4f8/vblo=3,656.99 2006.161.08:02:42.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:02:42.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:02:42.67#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:42.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:42.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:42.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:42.67#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:02:42.67#ibcon#first serial, iclass 26, count 0 2006.161.08:02:42.67#ibcon#enter sib2, iclass 26, count 0 2006.161.08:02:42.67#ibcon#flushed, iclass 26, count 0 2006.161.08:02:42.67#ibcon#about to write, iclass 26, count 0 2006.161.08:02:42.67#ibcon#wrote, iclass 26, count 0 2006.161.08:02:42.67#ibcon#about to read 3, iclass 26, count 0 2006.161.08:02:42.69#ibcon#read 3, iclass 26, count 0 2006.161.08:02:42.69#ibcon#about to read 4, iclass 26, count 0 2006.161.08:02:42.69#ibcon#read 4, iclass 26, count 0 2006.161.08:02:42.69#ibcon#about to read 5, iclass 26, count 0 2006.161.08:02:42.69#ibcon#read 5, iclass 26, count 0 2006.161.08:02:42.69#ibcon#about to read 6, iclass 26, count 0 2006.161.08:02:42.69#ibcon#read 6, iclass 26, count 0 2006.161.08:02:42.69#ibcon#end of sib2, iclass 26, count 0 2006.161.08:02:42.69#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:02:42.69#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:02:42.69#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:02:42.69#ibcon#*before write, iclass 26, count 0 2006.161.08:02:42.69#ibcon#enter sib2, iclass 26, count 0 2006.161.08:02:42.69#ibcon#flushed, iclass 26, count 0 2006.161.08:02:42.69#ibcon#about to write, iclass 26, count 0 2006.161.08:02:42.69#ibcon#wrote, iclass 26, count 0 2006.161.08:02:42.69#ibcon#about to read 3, iclass 26, count 0 2006.161.08:02:42.73#ibcon#read 3, iclass 26, count 0 2006.161.08:02:42.73#ibcon#about to read 4, iclass 26, count 0 2006.161.08:02:42.73#ibcon#read 4, iclass 26, count 0 2006.161.08:02:42.73#ibcon#about to read 5, iclass 26, count 0 2006.161.08:02:42.73#ibcon#read 5, iclass 26, count 0 2006.161.08:02:42.73#ibcon#about to read 6, iclass 26, count 0 2006.161.08:02:42.73#ibcon#read 6, iclass 26, count 0 2006.161.08:02:42.73#ibcon#end of sib2, iclass 26, count 0 2006.161.08:02:42.73#ibcon#*after write, iclass 26, count 0 2006.161.08:02:42.73#ibcon#*before return 0, iclass 26, count 0 2006.161.08:02:42.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:42.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:02:42.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:02:42.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:02:42.73$vc4f8/vb=3,4 2006.161.08:02:42.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:02:42.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:02:42.73#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:42.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:42.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:42.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:42.80#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:02:42.80#ibcon#first serial, iclass 28, count 2 2006.161.08:02:42.80#ibcon#enter sib2, iclass 28, count 2 2006.161.08:02:42.80#ibcon#flushed, iclass 28, count 2 2006.161.08:02:42.80#ibcon#about to write, iclass 28, count 2 2006.161.08:02:42.80#ibcon#wrote, iclass 28, count 2 2006.161.08:02:42.80#ibcon#about to read 3, iclass 28, count 2 2006.161.08:02:42.81#ibcon#read 3, iclass 28, count 2 2006.161.08:02:42.81#ibcon#about to read 4, iclass 28, count 2 2006.161.08:02:42.81#ibcon#read 4, iclass 28, count 2 2006.161.08:02:42.81#ibcon#about to read 5, iclass 28, count 2 2006.161.08:02:42.81#ibcon#read 5, iclass 28, count 2 2006.161.08:02:42.81#ibcon#about to read 6, iclass 28, count 2 2006.161.08:02:42.81#ibcon#read 6, iclass 28, count 2 2006.161.08:02:42.81#ibcon#end of sib2, iclass 28, count 2 2006.161.08:02:42.81#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:02:42.81#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:02:42.81#ibcon#[27=AT03-04\r\n] 2006.161.08:02:42.81#ibcon#*before write, iclass 28, count 2 2006.161.08:02:42.81#ibcon#enter sib2, iclass 28, count 2 2006.161.08:02:42.81#ibcon#flushed, iclass 28, count 2 2006.161.08:02:42.81#ibcon#about to write, iclass 28, count 2 2006.161.08:02:42.81#ibcon#wrote, iclass 28, count 2 2006.161.08:02:42.81#ibcon#about to read 3, iclass 28, count 2 2006.161.08:02:42.84#ibcon#read 3, iclass 28, count 2 2006.161.08:02:42.84#ibcon#about to read 4, iclass 28, count 2 2006.161.08:02:42.84#ibcon#read 4, iclass 28, count 2 2006.161.08:02:42.84#ibcon#about to read 5, iclass 28, count 2 2006.161.08:02:42.84#ibcon#read 5, iclass 28, count 2 2006.161.08:02:42.84#ibcon#about to read 6, iclass 28, count 2 2006.161.08:02:42.84#ibcon#read 6, iclass 28, count 2 2006.161.08:02:42.84#ibcon#end of sib2, iclass 28, count 2 2006.161.08:02:42.84#ibcon#*after write, iclass 28, count 2 2006.161.08:02:42.84#ibcon#*before return 0, iclass 28, count 2 2006.161.08:02:42.84#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:42.84#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:02:42.84#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:02:42.84#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:42.84#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:42.96#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:42.96#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:42.96#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:02:42.96#ibcon#first serial, iclass 28, count 0 2006.161.08:02:42.96#ibcon#enter sib2, iclass 28, count 0 2006.161.08:02:42.96#ibcon#flushed, iclass 28, count 0 2006.161.08:02:42.96#ibcon#about to write, iclass 28, count 0 2006.161.08:02:42.96#ibcon#wrote, iclass 28, count 0 2006.161.08:02:42.96#ibcon#about to read 3, iclass 28, count 0 2006.161.08:02:42.98#ibcon#read 3, iclass 28, count 0 2006.161.08:02:42.98#ibcon#about to read 4, iclass 28, count 0 2006.161.08:02:42.98#ibcon#read 4, iclass 28, count 0 2006.161.08:02:42.98#ibcon#about to read 5, iclass 28, count 0 2006.161.08:02:42.98#ibcon#read 5, iclass 28, count 0 2006.161.08:02:42.98#ibcon#about to read 6, iclass 28, count 0 2006.161.08:02:42.98#ibcon#read 6, iclass 28, count 0 2006.161.08:02:42.98#ibcon#end of sib2, iclass 28, count 0 2006.161.08:02:42.98#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:02:42.98#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:02:42.98#ibcon#[27=USB\r\n] 2006.161.08:02:42.98#ibcon#*before write, iclass 28, count 0 2006.161.08:02:42.98#ibcon#enter sib2, iclass 28, count 0 2006.161.08:02:42.98#ibcon#flushed, iclass 28, count 0 2006.161.08:02:42.98#ibcon#about to write, iclass 28, count 0 2006.161.08:02:42.98#ibcon#wrote, iclass 28, count 0 2006.161.08:02:42.98#ibcon#about to read 3, iclass 28, count 0 2006.161.08:02:43.01#ibcon#read 3, iclass 28, count 0 2006.161.08:02:43.01#ibcon#about to read 4, iclass 28, count 0 2006.161.08:02:43.01#ibcon#read 4, iclass 28, count 0 2006.161.08:02:43.01#ibcon#about to read 5, iclass 28, count 0 2006.161.08:02:43.01#ibcon#read 5, iclass 28, count 0 2006.161.08:02:43.01#ibcon#about to read 6, iclass 28, count 0 2006.161.08:02:43.01#ibcon#read 6, iclass 28, count 0 2006.161.08:02:43.01#ibcon#end of sib2, iclass 28, count 0 2006.161.08:02:43.01#ibcon#*after write, iclass 28, count 0 2006.161.08:02:43.01#ibcon#*before return 0, iclass 28, count 0 2006.161.08:02:43.01#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:43.01#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:02:43.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:02:43.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:02:43.01$vc4f8/vblo=4,712.99 2006.161.08:02:43.01#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:02:43.01#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:02:43.01#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:43.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:43.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:43.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:43.01#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:02:43.01#ibcon#first serial, iclass 30, count 0 2006.161.08:02:43.01#ibcon#enter sib2, iclass 30, count 0 2006.161.08:02:43.01#ibcon#flushed, iclass 30, count 0 2006.161.08:02:43.01#ibcon#about to write, iclass 30, count 0 2006.161.08:02:43.01#ibcon#wrote, iclass 30, count 0 2006.161.08:02:43.01#ibcon#about to read 3, iclass 30, count 0 2006.161.08:02:43.03#ibcon#read 3, iclass 30, count 0 2006.161.08:02:43.03#ibcon#about to read 4, iclass 30, count 0 2006.161.08:02:43.03#ibcon#read 4, iclass 30, count 0 2006.161.08:02:43.03#ibcon#about to read 5, iclass 30, count 0 2006.161.08:02:43.03#ibcon#read 5, iclass 30, count 0 2006.161.08:02:43.03#ibcon#about to read 6, iclass 30, count 0 2006.161.08:02:43.03#ibcon#read 6, iclass 30, count 0 2006.161.08:02:43.03#ibcon#end of sib2, iclass 30, count 0 2006.161.08:02:43.03#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:02:43.03#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:02:43.03#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:02:43.03#ibcon#*before write, iclass 30, count 0 2006.161.08:02:43.03#ibcon#enter sib2, iclass 30, count 0 2006.161.08:02:43.03#ibcon#flushed, iclass 30, count 0 2006.161.08:02:43.03#ibcon#about to write, iclass 30, count 0 2006.161.08:02:43.03#ibcon#wrote, iclass 30, count 0 2006.161.08:02:43.03#ibcon#about to read 3, iclass 30, count 0 2006.161.08:02:43.07#ibcon#read 3, iclass 30, count 0 2006.161.08:02:43.07#ibcon#about to read 4, iclass 30, count 0 2006.161.08:02:43.07#ibcon#read 4, iclass 30, count 0 2006.161.08:02:43.07#ibcon#about to read 5, iclass 30, count 0 2006.161.08:02:43.07#ibcon#read 5, iclass 30, count 0 2006.161.08:02:43.07#ibcon#about to read 6, iclass 30, count 0 2006.161.08:02:43.07#ibcon#read 6, iclass 30, count 0 2006.161.08:02:43.07#ibcon#end of sib2, iclass 30, count 0 2006.161.08:02:43.07#ibcon#*after write, iclass 30, count 0 2006.161.08:02:43.07#ibcon#*before return 0, iclass 30, count 0 2006.161.08:02:43.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:43.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:02:43.07#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:02:43.07#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:02:43.07$vc4f8/vb=4,4 2006.161.08:02:43.07#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:02:43.07#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:02:43.07#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:43.07#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:43.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:43.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:43.14#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:02:43.14#ibcon#first serial, iclass 32, count 2 2006.161.08:02:43.14#ibcon#enter sib2, iclass 32, count 2 2006.161.08:02:43.14#ibcon#flushed, iclass 32, count 2 2006.161.08:02:43.14#ibcon#about to write, iclass 32, count 2 2006.161.08:02:43.14#ibcon#wrote, iclass 32, count 2 2006.161.08:02:43.14#ibcon#about to read 3, iclass 32, count 2 2006.161.08:02:43.16#ibcon#read 3, iclass 32, count 2 2006.161.08:02:43.16#ibcon#about to read 4, iclass 32, count 2 2006.161.08:02:43.16#ibcon#read 4, iclass 32, count 2 2006.161.08:02:43.16#ibcon#about to read 5, iclass 32, count 2 2006.161.08:02:43.16#ibcon#read 5, iclass 32, count 2 2006.161.08:02:43.16#ibcon#about to read 6, iclass 32, count 2 2006.161.08:02:43.16#ibcon#read 6, iclass 32, count 2 2006.161.08:02:43.16#ibcon#end of sib2, iclass 32, count 2 2006.161.08:02:43.16#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:02:43.16#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:02:43.16#ibcon#[27=AT04-04\r\n] 2006.161.08:02:43.16#ibcon#*before write, iclass 32, count 2 2006.161.08:02:43.16#ibcon#enter sib2, iclass 32, count 2 2006.161.08:02:43.16#ibcon#flushed, iclass 32, count 2 2006.161.08:02:43.16#ibcon#about to write, iclass 32, count 2 2006.161.08:02:43.16#ibcon#wrote, iclass 32, count 2 2006.161.08:02:43.16#ibcon#about to read 3, iclass 32, count 2 2006.161.08:02:43.18#ibcon#read 3, iclass 32, count 2 2006.161.08:02:43.18#ibcon#about to read 4, iclass 32, count 2 2006.161.08:02:43.18#ibcon#read 4, iclass 32, count 2 2006.161.08:02:43.18#ibcon#about to read 5, iclass 32, count 2 2006.161.08:02:43.18#ibcon#read 5, iclass 32, count 2 2006.161.08:02:43.18#ibcon#about to read 6, iclass 32, count 2 2006.161.08:02:43.18#ibcon#read 6, iclass 32, count 2 2006.161.08:02:43.18#ibcon#end of sib2, iclass 32, count 2 2006.161.08:02:43.18#ibcon#*after write, iclass 32, count 2 2006.161.08:02:43.18#ibcon#*before return 0, iclass 32, count 2 2006.161.08:02:43.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:43.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:02:43.18#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:02:43.18#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:43.18#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:43.30#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:43.30#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:43.30#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:02:43.30#ibcon#first serial, iclass 32, count 0 2006.161.08:02:43.30#ibcon#enter sib2, iclass 32, count 0 2006.161.08:02:43.30#ibcon#flushed, iclass 32, count 0 2006.161.08:02:43.30#ibcon#about to write, iclass 32, count 0 2006.161.08:02:43.30#ibcon#wrote, iclass 32, count 0 2006.161.08:02:43.30#ibcon#about to read 3, iclass 32, count 0 2006.161.08:02:43.32#ibcon#read 3, iclass 32, count 0 2006.161.08:02:43.32#ibcon#about to read 4, iclass 32, count 0 2006.161.08:02:43.32#ibcon#read 4, iclass 32, count 0 2006.161.08:02:43.32#ibcon#about to read 5, iclass 32, count 0 2006.161.08:02:43.32#ibcon#read 5, iclass 32, count 0 2006.161.08:02:43.32#ibcon#about to read 6, iclass 32, count 0 2006.161.08:02:43.32#ibcon#read 6, iclass 32, count 0 2006.161.08:02:43.32#ibcon#end of sib2, iclass 32, count 0 2006.161.08:02:43.32#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:02:43.32#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:02:43.32#ibcon#[27=USB\r\n] 2006.161.08:02:43.32#ibcon#*before write, iclass 32, count 0 2006.161.08:02:43.32#ibcon#enter sib2, iclass 32, count 0 2006.161.08:02:43.32#ibcon#flushed, iclass 32, count 0 2006.161.08:02:43.32#ibcon#about to write, iclass 32, count 0 2006.161.08:02:43.32#ibcon#wrote, iclass 32, count 0 2006.161.08:02:43.32#ibcon#about to read 3, iclass 32, count 0 2006.161.08:02:43.35#ibcon#read 3, iclass 32, count 0 2006.161.08:02:43.35#ibcon#about to read 4, iclass 32, count 0 2006.161.08:02:43.35#ibcon#read 4, iclass 32, count 0 2006.161.08:02:43.35#ibcon#about to read 5, iclass 32, count 0 2006.161.08:02:43.35#ibcon#read 5, iclass 32, count 0 2006.161.08:02:43.35#ibcon#about to read 6, iclass 32, count 0 2006.161.08:02:43.35#ibcon#read 6, iclass 32, count 0 2006.161.08:02:43.35#ibcon#end of sib2, iclass 32, count 0 2006.161.08:02:43.35#ibcon#*after write, iclass 32, count 0 2006.161.08:02:43.35#ibcon#*before return 0, iclass 32, count 0 2006.161.08:02:43.35#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:43.35#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:02:43.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:02:43.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:02:43.35$vc4f8/vblo=5,744.99 2006.161.08:02:43.35#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:02:43.35#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:02:43.35#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:43.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:43.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:43.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:43.35#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:02:43.35#ibcon#first serial, iclass 34, count 0 2006.161.08:02:43.35#ibcon#enter sib2, iclass 34, count 0 2006.161.08:02:43.35#ibcon#flushed, iclass 34, count 0 2006.161.08:02:43.35#ibcon#about to write, iclass 34, count 0 2006.161.08:02:43.35#ibcon#wrote, iclass 34, count 0 2006.161.08:02:43.35#ibcon#about to read 3, iclass 34, count 0 2006.161.08:02:43.37#ibcon#read 3, iclass 34, count 0 2006.161.08:02:43.37#ibcon#about to read 4, iclass 34, count 0 2006.161.08:02:43.37#ibcon#read 4, iclass 34, count 0 2006.161.08:02:43.37#ibcon#about to read 5, iclass 34, count 0 2006.161.08:02:43.37#ibcon#read 5, iclass 34, count 0 2006.161.08:02:43.37#ibcon#about to read 6, iclass 34, count 0 2006.161.08:02:43.37#ibcon#read 6, iclass 34, count 0 2006.161.08:02:43.37#ibcon#end of sib2, iclass 34, count 0 2006.161.08:02:43.37#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:02:43.37#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:02:43.37#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:02:43.37#ibcon#*before write, iclass 34, count 0 2006.161.08:02:43.37#ibcon#enter sib2, iclass 34, count 0 2006.161.08:02:43.37#ibcon#flushed, iclass 34, count 0 2006.161.08:02:43.37#ibcon#about to write, iclass 34, count 0 2006.161.08:02:43.37#ibcon#wrote, iclass 34, count 0 2006.161.08:02:43.37#ibcon#about to read 3, iclass 34, count 0 2006.161.08:02:43.41#ibcon#read 3, iclass 34, count 0 2006.161.08:02:43.41#ibcon#about to read 4, iclass 34, count 0 2006.161.08:02:43.41#ibcon#read 4, iclass 34, count 0 2006.161.08:02:43.41#ibcon#about to read 5, iclass 34, count 0 2006.161.08:02:43.41#ibcon#read 5, iclass 34, count 0 2006.161.08:02:43.41#ibcon#about to read 6, iclass 34, count 0 2006.161.08:02:43.41#ibcon#read 6, iclass 34, count 0 2006.161.08:02:43.41#ibcon#end of sib2, iclass 34, count 0 2006.161.08:02:43.41#ibcon#*after write, iclass 34, count 0 2006.161.08:02:43.41#ibcon#*before return 0, iclass 34, count 0 2006.161.08:02:43.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:43.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:02:43.41#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:02:43.41#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:02:43.41$vc4f8/vb=5,4 2006.161.08:02:43.41#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:02:43.41#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:02:43.41#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:43.41#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:43.47#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:43.47#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:43.47#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:02:43.47#ibcon#first serial, iclass 36, count 2 2006.161.08:02:43.47#ibcon#enter sib2, iclass 36, count 2 2006.161.08:02:43.47#ibcon#flushed, iclass 36, count 2 2006.161.08:02:43.47#ibcon#about to write, iclass 36, count 2 2006.161.08:02:43.47#ibcon#wrote, iclass 36, count 2 2006.161.08:02:43.47#ibcon#about to read 3, iclass 36, count 2 2006.161.08:02:43.50#ibcon#read 3, iclass 36, count 2 2006.161.08:02:43.50#ibcon#about to read 4, iclass 36, count 2 2006.161.08:02:43.50#ibcon#read 4, iclass 36, count 2 2006.161.08:02:43.50#ibcon#about to read 5, iclass 36, count 2 2006.161.08:02:43.50#ibcon#read 5, iclass 36, count 2 2006.161.08:02:43.50#ibcon#about to read 6, iclass 36, count 2 2006.161.08:02:43.50#ibcon#read 6, iclass 36, count 2 2006.161.08:02:43.50#ibcon#end of sib2, iclass 36, count 2 2006.161.08:02:43.50#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:02:43.50#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:02:43.50#ibcon#[27=AT05-04\r\n] 2006.161.08:02:43.50#ibcon#*before write, iclass 36, count 2 2006.161.08:02:43.50#ibcon#enter sib2, iclass 36, count 2 2006.161.08:02:43.50#ibcon#flushed, iclass 36, count 2 2006.161.08:02:43.50#ibcon#about to write, iclass 36, count 2 2006.161.08:02:43.50#ibcon#wrote, iclass 36, count 2 2006.161.08:02:43.50#ibcon#about to read 3, iclass 36, count 2 2006.161.08:02:43.52#ibcon#read 3, iclass 36, count 2 2006.161.08:02:43.52#ibcon#about to read 4, iclass 36, count 2 2006.161.08:02:43.52#ibcon#read 4, iclass 36, count 2 2006.161.08:02:43.52#ibcon#about to read 5, iclass 36, count 2 2006.161.08:02:43.52#ibcon#read 5, iclass 36, count 2 2006.161.08:02:43.52#ibcon#about to read 6, iclass 36, count 2 2006.161.08:02:43.52#ibcon#read 6, iclass 36, count 2 2006.161.08:02:43.52#ibcon#end of sib2, iclass 36, count 2 2006.161.08:02:43.52#ibcon#*after write, iclass 36, count 2 2006.161.08:02:43.52#ibcon#*before return 0, iclass 36, count 2 2006.161.08:02:43.52#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:43.52#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:02:43.52#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:02:43.52#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:43.52#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:43.64#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:43.64#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:43.64#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:02:43.64#ibcon#first serial, iclass 36, count 0 2006.161.08:02:43.64#ibcon#enter sib2, iclass 36, count 0 2006.161.08:02:43.64#ibcon#flushed, iclass 36, count 0 2006.161.08:02:43.64#ibcon#about to write, iclass 36, count 0 2006.161.08:02:43.64#ibcon#wrote, iclass 36, count 0 2006.161.08:02:43.64#ibcon#about to read 3, iclass 36, count 0 2006.161.08:02:43.66#ibcon#read 3, iclass 36, count 0 2006.161.08:02:43.66#ibcon#about to read 4, iclass 36, count 0 2006.161.08:02:43.66#ibcon#read 4, iclass 36, count 0 2006.161.08:02:43.66#ibcon#about to read 5, iclass 36, count 0 2006.161.08:02:43.66#ibcon#read 5, iclass 36, count 0 2006.161.08:02:43.66#ibcon#about to read 6, iclass 36, count 0 2006.161.08:02:43.66#ibcon#read 6, iclass 36, count 0 2006.161.08:02:43.66#ibcon#end of sib2, iclass 36, count 0 2006.161.08:02:43.66#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:02:43.66#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:02:43.66#ibcon#[27=USB\r\n] 2006.161.08:02:43.66#ibcon#*before write, iclass 36, count 0 2006.161.08:02:43.66#ibcon#enter sib2, iclass 36, count 0 2006.161.08:02:43.66#ibcon#flushed, iclass 36, count 0 2006.161.08:02:43.66#ibcon#about to write, iclass 36, count 0 2006.161.08:02:43.66#ibcon#wrote, iclass 36, count 0 2006.161.08:02:43.66#ibcon#about to read 3, iclass 36, count 0 2006.161.08:02:43.69#ibcon#read 3, iclass 36, count 0 2006.161.08:02:43.69#ibcon#about to read 4, iclass 36, count 0 2006.161.08:02:43.69#ibcon#read 4, iclass 36, count 0 2006.161.08:02:43.69#ibcon#about to read 5, iclass 36, count 0 2006.161.08:02:43.69#ibcon#read 5, iclass 36, count 0 2006.161.08:02:43.69#ibcon#about to read 6, iclass 36, count 0 2006.161.08:02:43.69#ibcon#read 6, iclass 36, count 0 2006.161.08:02:43.69#ibcon#end of sib2, iclass 36, count 0 2006.161.08:02:43.69#ibcon#*after write, iclass 36, count 0 2006.161.08:02:43.69#ibcon#*before return 0, iclass 36, count 0 2006.161.08:02:43.69#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:43.69#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:02:43.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:02:43.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:02:43.69$vc4f8/vblo=6,752.99 2006.161.08:02:43.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:02:43.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:02:43.69#ibcon#ireg 17 cls_cnt 0 2006.161.08:02:43.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:43.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:43.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:43.69#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:02:43.69#ibcon#first serial, iclass 38, count 0 2006.161.08:02:43.69#ibcon#enter sib2, iclass 38, count 0 2006.161.08:02:43.69#ibcon#flushed, iclass 38, count 0 2006.161.08:02:43.69#ibcon#about to write, iclass 38, count 0 2006.161.08:02:43.69#ibcon#wrote, iclass 38, count 0 2006.161.08:02:43.69#ibcon#about to read 3, iclass 38, count 0 2006.161.08:02:43.71#ibcon#read 3, iclass 38, count 0 2006.161.08:02:43.71#ibcon#about to read 4, iclass 38, count 0 2006.161.08:02:43.71#ibcon#read 4, iclass 38, count 0 2006.161.08:02:43.71#ibcon#about to read 5, iclass 38, count 0 2006.161.08:02:43.71#ibcon#read 5, iclass 38, count 0 2006.161.08:02:43.71#ibcon#about to read 6, iclass 38, count 0 2006.161.08:02:43.71#ibcon#read 6, iclass 38, count 0 2006.161.08:02:43.71#ibcon#end of sib2, iclass 38, count 0 2006.161.08:02:43.71#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:02:43.71#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:02:43.71#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:02:43.71#ibcon#*before write, iclass 38, count 0 2006.161.08:02:43.71#ibcon#enter sib2, iclass 38, count 0 2006.161.08:02:43.71#ibcon#flushed, iclass 38, count 0 2006.161.08:02:43.71#ibcon#about to write, iclass 38, count 0 2006.161.08:02:43.71#ibcon#wrote, iclass 38, count 0 2006.161.08:02:43.71#ibcon#about to read 3, iclass 38, count 0 2006.161.08:02:43.75#ibcon#read 3, iclass 38, count 0 2006.161.08:02:43.75#ibcon#about to read 4, iclass 38, count 0 2006.161.08:02:43.75#ibcon#read 4, iclass 38, count 0 2006.161.08:02:43.75#ibcon#about to read 5, iclass 38, count 0 2006.161.08:02:43.75#ibcon#read 5, iclass 38, count 0 2006.161.08:02:43.75#ibcon#about to read 6, iclass 38, count 0 2006.161.08:02:43.75#ibcon#read 6, iclass 38, count 0 2006.161.08:02:43.75#ibcon#end of sib2, iclass 38, count 0 2006.161.08:02:43.75#ibcon#*after write, iclass 38, count 0 2006.161.08:02:43.75#ibcon#*before return 0, iclass 38, count 0 2006.161.08:02:43.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:43.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:02:43.75#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:02:43.75#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:02:43.75$vc4f8/vb=6,4 2006.161.08:02:43.75#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:02:43.75#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:02:43.75#ibcon#ireg 11 cls_cnt 2 2006.161.08:02:43.75#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:43.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:43.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:43.82#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:02:43.82#ibcon#first serial, iclass 40, count 2 2006.161.08:02:43.82#ibcon#enter sib2, iclass 40, count 2 2006.161.08:02:43.82#ibcon#flushed, iclass 40, count 2 2006.161.08:02:43.82#ibcon#about to write, iclass 40, count 2 2006.161.08:02:43.82#ibcon#wrote, iclass 40, count 2 2006.161.08:02:43.82#ibcon#about to read 3, iclass 40, count 2 2006.161.08:02:43.84#ibcon#read 3, iclass 40, count 2 2006.161.08:02:43.84#ibcon#about to read 4, iclass 40, count 2 2006.161.08:02:43.84#ibcon#read 4, iclass 40, count 2 2006.161.08:02:43.84#ibcon#about to read 5, iclass 40, count 2 2006.161.08:02:43.84#ibcon#read 5, iclass 40, count 2 2006.161.08:02:43.84#ibcon#about to read 6, iclass 40, count 2 2006.161.08:02:43.84#ibcon#read 6, iclass 40, count 2 2006.161.08:02:43.84#ibcon#end of sib2, iclass 40, count 2 2006.161.08:02:43.84#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:02:43.84#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:02:43.84#ibcon#[27=AT06-04\r\n] 2006.161.08:02:43.84#ibcon#*before write, iclass 40, count 2 2006.161.08:02:43.84#ibcon#enter sib2, iclass 40, count 2 2006.161.08:02:43.84#ibcon#flushed, iclass 40, count 2 2006.161.08:02:43.84#ibcon#about to write, iclass 40, count 2 2006.161.08:02:43.84#ibcon#wrote, iclass 40, count 2 2006.161.08:02:43.84#ibcon#about to read 3, iclass 40, count 2 2006.161.08:02:43.86#ibcon#read 3, iclass 40, count 2 2006.161.08:02:43.86#ibcon#about to read 4, iclass 40, count 2 2006.161.08:02:43.86#ibcon#read 4, iclass 40, count 2 2006.161.08:02:43.86#ibcon#about to read 5, iclass 40, count 2 2006.161.08:02:43.86#ibcon#read 5, iclass 40, count 2 2006.161.08:02:43.86#ibcon#about to read 6, iclass 40, count 2 2006.161.08:02:43.86#ibcon#read 6, iclass 40, count 2 2006.161.08:02:43.86#ibcon#end of sib2, iclass 40, count 2 2006.161.08:02:43.86#ibcon#*after write, iclass 40, count 2 2006.161.08:02:43.86#ibcon#*before return 0, iclass 40, count 2 2006.161.08:02:43.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:43.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:02:43.86#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:02:43.86#ibcon#ireg 7 cls_cnt 0 2006.161.08:02:43.86#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:43.98#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:43.98#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:43.98#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:02:43.98#ibcon#first serial, iclass 40, count 0 2006.161.08:02:43.98#ibcon#enter sib2, iclass 40, count 0 2006.161.08:02:43.98#ibcon#flushed, iclass 40, count 0 2006.161.08:02:43.98#ibcon#about to write, iclass 40, count 0 2006.161.08:02:43.98#ibcon#wrote, iclass 40, count 0 2006.161.08:02:43.98#ibcon#about to read 3, iclass 40, count 0 2006.161.08:02:44.00#ibcon#read 3, iclass 40, count 0 2006.161.08:02:44.00#ibcon#about to read 4, iclass 40, count 0 2006.161.08:02:44.00#ibcon#read 4, iclass 40, count 0 2006.161.08:02:44.00#ibcon#about to read 5, iclass 40, count 0 2006.161.08:02:44.00#ibcon#read 5, iclass 40, count 0 2006.161.08:02:44.00#ibcon#about to read 6, iclass 40, count 0 2006.161.08:02:44.00#ibcon#read 6, iclass 40, count 0 2006.161.08:02:44.00#ibcon#end of sib2, iclass 40, count 0 2006.161.08:02:44.00#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:02:44.00#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:02:44.00#ibcon#[27=USB\r\n] 2006.161.08:02:44.00#ibcon#*before write, iclass 40, count 0 2006.161.08:02:44.00#ibcon#enter sib2, iclass 40, count 0 2006.161.08:02:44.00#ibcon#flushed, iclass 40, count 0 2006.161.08:02:44.00#ibcon#about to write, iclass 40, count 0 2006.161.08:02:44.00#ibcon#wrote, iclass 40, count 0 2006.161.08:02:44.00#ibcon#about to read 3, iclass 40, count 0 2006.161.08:02:44.03#ibcon#read 3, iclass 40, count 0 2006.161.08:02:44.03#ibcon#about to read 4, iclass 40, count 0 2006.161.08:02:44.03#ibcon#read 4, iclass 40, count 0 2006.161.08:02:44.03#ibcon#about to read 5, iclass 40, count 0 2006.161.08:02:44.03#ibcon#read 5, iclass 40, count 0 2006.161.08:02:44.03#ibcon#about to read 6, iclass 40, count 0 2006.161.08:02:44.03#ibcon#read 6, iclass 40, count 0 2006.161.08:02:44.03#ibcon#end of sib2, iclass 40, count 0 2006.161.08:02:44.03#ibcon#*after write, iclass 40, count 0 2006.161.08:02:44.03#ibcon#*before return 0, iclass 40, count 0 2006.161.08:02:44.03#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:44.03#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:02:44.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:02:44.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:02:44.03$vc4f8/vabw=wide 2006.161.08:02:44.03#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:02:44.03#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:02:44.03#ibcon#ireg 8 cls_cnt 0 2006.161.08:02:44.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:44.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:44.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:44.03#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:02:44.03#ibcon#first serial, iclass 4, count 0 2006.161.08:02:44.03#ibcon#enter sib2, iclass 4, count 0 2006.161.08:02:44.03#ibcon#flushed, iclass 4, count 0 2006.161.08:02:44.03#ibcon#about to write, iclass 4, count 0 2006.161.08:02:44.03#ibcon#wrote, iclass 4, count 0 2006.161.08:02:44.03#ibcon#about to read 3, iclass 4, count 0 2006.161.08:02:44.05#ibcon#read 3, iclass 4, count 0 2006.161.08:02:44.05#ibcon#about to read 4, iclass 4, count 0 2006.161.08:02:44.05#ibcon#read 4, iclass 4, count 0 2006.161.08:02:44.05#ibcon#about to read 5, iclass 4, count 0 2006.161.08:02:44.05#ibcon#read 5, iclass 4, count 0 2006.161.08:02:44.05#ibcon#about to read 6, iclass 4, count 0 2006.161.08:02:44.05#ibcon#read 6, iclass 4, count 0 2006.161.08:02:44.05#ibcon#end of sib2, iclass 4, count 0 2006.161.08:02:44.05#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:02:44.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:02:44.05#ibcon#[25=BW32\r\n] 2006.161.08:02:44.05#ibcon#*before write, iclass 4, count 0 2006.161.08:02:44.05#ibcon#enter sib2, iclass 4, count 0 2006.161.08:02:44.05#ibcon#flushed, iclass 4, count 0 2006.161.08:02:44.05#ibcon#about to write, iclass 4, count 0 2006.161.08:02:44.05#ibcon#wrote, iclass 4, count 0 2006.161.08:02:44.05#ibcon#about to read 3, iclass 4, count 0 2006.161.08:02:44.08#ibcon#read 3, iclass 4, count 0 2006.161.08:02:44.08#ibcon#about to read 4, iclass 4, count 0 2006.161.08:02:44.08#ibcon#read 4, iclass 4, count 0 2006.161.08:02:44.08#ibcon#about to read 5, iclass 4, count 0 2006.161.08:02:44.08#ibcon#read 5, iclass 4, count 0 2006.161.08:02:44.08#ibcon#about to read 6, iclass 4, count 0 2006.161.08:02:44.08#ibcon#read 6, iclass 4, count 0 2006.161.08:02:44.08#ibcon#end of sib2, iclass 4, count 0 2006.161.08:02:44.08#ibcon#*after write, iclass 4, count 0 2006.161.08:02:44.08#ibcon#*before return 0, iclass 4, count 0 2006.161.08:02:44.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:44.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:02:44.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:02:44.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:02:44.08$vc4f8/vbbw=wide 2006.161.08:02:44.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:02:44.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:02:44.08#ibcon#ireg 8 cls_cnt 0 2006.161.08:02:44.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:02:44.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:02:44.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:02:44.16#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:02:44.16#ibcon#first serial, iclass 6, count 0 2006.161.08:02:44.16#ibcon#enter sib2, iclass 6, count 0 2006.161.08:02:44.16#ibcon#flushed, iclass 6, count 0 2006.161.08:02:44.16#ibcon#about to write, iclass 6, count 0 2006.161.08:02:44.16#ibcon#wrote, iclass 6, count 0 2006.161.08:02:44.16#ibcon#about to read 3, iclass 6, count 0 2006.161.08:02:44.18#ibcon#read 3, iclass 6, count 0 2006.161.08:02:44.18#ibcon#about to read 4, iclass 6, count 0 2006.161.08:02:44.18#ibcon#read 4, iclass 6, count 0 2006.161.08:02:44.18#ibcon#about to read 5, iclass 6, count 0 2006.161.08:02:44.18#ibcon#read 5, iclass 6, count 0 2006.161.08:02:44.18#ibcon#about to read 6, iclass 6, count 0 2006.161.08:02:44.18#ibcon#read 6, iclass 6, count 0 2006.161.08:02:44.18#ibcon#end of sib2, iclass 6, count 0 2006.161.08:02:44.18#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:02:44.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:02:44.18#ibcon#[27=BW32\r\n] 2006.161.08:02:44.18#ibcon#*before write, iclass 6, count 0 2006.161.08:02:44.18#ibcon#enter sib2, iclass 6, count 0 2006.161.08:02:44.18#ibcon#flushed, iclass 6, count 0 2006.161.08:02:44.18#ibcon#about to write, iclass 6, count 0 2006.161.08:02:44.18#ibcon#wrote, iclass 6, count 0 2006.161.08:02:44.18#ibcon#about to read 3, iclass 6, count 0 2006.161.08:02:44.20#ibcon#read 3, iclass 6, count 0 2006.161.08:02:44.20#ibcon#about to read 4, iclass 6, count 0 2006.161.08:02:44.20#ibcon#read 4, iclass 6, count 0 2006.161.08:02:44.20#ibcon#about to read 5, iclass 6, count 0 2006.161.08:02:44.20#ibcon#read 5, iclass 6, count 0 2006.161.08:02:44.20#ibcon#about to read 6, iclass 6, count 0 2006.161.08:02:44.20#ibcon#read 6, iclass 6, count 0 2006.161.08:02:44.20#ibcon#end of sib2, iclass 6, count 0 2006.161.08:02:44.20#ibcon#*after write, iclass 6, count 0 2006.161.08:02:44.20#ibcon#*before return 0, iclass 6, count 0 2006.161.08:02:44.20#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:02:44.20#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:02:44.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:02:44.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:02:44.20$4f8m12a/ifd4f 2006.161.08:02:44.20$ifd4f/lo= 2006.161.08:02:44.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:02:44.21$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:02:44.21$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:02:44.21$ifd4f/patch= 2006.161.08:02:44.21$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:02:44.21$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:02:44.21$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:02:44.21$4f8m12a/"form=m,16.000,1:2 2006.161.08:02:44.21$4f8m12a/"tpicd 2006.161.08:02:44.21$4f8m12a/echo=off 2006.161.08:02:44.21$4f8m12a/xlog=off 2006.161.08:02:44.21:!2006.161.08:03:10 2006.161.08:02:47.14#trakl#Source acquired 2006.161.08:02:49.14#flagr#flagr/antenna,acquired 2006.161.08:03:10.01:preob 2006.161.08:03:11.14/onsource/TRACKING 2006.161.08:03:11.14:!2006.161.08:03:20 2006.161.08:03:20.00:data_valid=on 2006.161.08:03:20.00:midob 2006.161.08:03:20.14/onsource/TRACKING 2006.161.08:03:20.14/wx/24.02,1002.2,86 2006.161.08:03:20.36/cable/+6.4997E-03 2006.161.08:03:21.45/va/01,08,usb,yes,28,30 2006.161.08:03:21.45/va/02,07,usb,yes,28,30 2006.161.08:03:21.45/va/03,06,usb,yes,30,30 2006.161.08:03:21.45/va/04,07,usb,yes,29,31 2006.161.08:03:21.45/va/05,07,usb,yes,29,30 2006.161.08:03:21.45/va/06,06,usb,yes,28,28 2006.161.08:03:21.45/va/07,06,usb,yes,28,28 2006.161.08:03:21.45/va/08,07,usb,yes,27,26 2006.161.08:03:21.68/valo/01,532.99,yes,locked 2006.161.08:03:21.68/valo/02,572.99,yes,locked 2006.161.08:03:21.68/valo/03,672.99,yes,locked 2006.161.08:03:21.68/valo/04,832.99,yes,locked 2006.161.08:03:21.68/valo/05,652.99,yes,locked 2006.161.08:03:21.68/valo/06,772.99,yes,locked 2006.161.08:03:21.68/valo/07,832.99,yes,locked 2006.161.08:03:21.68/valo/08,852.99,yes,locked 2006.161.08:03:22.77/vb/01,04,usb,yes,29,27 2006.161.08:03:22.77/vb/02,04,usb,yes,30,32 2006.161.08:03:22.77/vb/03,04,usb,yes,27,30 2006.161.08:03:22.77/vb/04,04,usb,yes,28,28 2006.161.08:03:22.77/vb/05,04,usb,yes,26,30 2006.161.08:03:22.77/vb/06,04,usb,yes,27,30 2006.161.08:03:22.77/vb/07,04,usb,yes,29,29 2006.161.08:03:22.77/vb/08,04,usb,yes,27,30 2006.161.08:03:23.01/vblo/01,632.99,yes,locked 2006.161.08:03:23.01/vblo/02,640.99,yes,locked 2006.161.08:03:23.01/vblo/03,656.99,yes,locked 2006.161.08:03:23.01/vblo/04,712.99,yes,locked 2006.161.08:03:23.01/vblo/05,744.99,yes,locked 2006.161.08:03:23.01/vblo/06,752.99,yes,locked 2006.161.08:03:23.01/vblo/07,734.99,yes,locked 2006.161.08:03:23.01/vblo/08,744.99,yes,locked 2006.161.08:03:23.16/vabw/8 2006.161.08:03:23.31/vbbw/8 2006.161.08:03:23.40/xfe/off,on,14.5 2006.161.08:03:23.77/ifatt/23,28,28,28 2006.161.08:03:24.08/fmout-gps/S +4.49E-07 2006.161.08:03:24.16:!2006.161.08:04:20 2006.161.08:04:20.01:data_valid=off 2006.161.08:04:20.02:postob 2006.161.08:04:20.15/cable/+6.5005E-03 2006.161.08:04:20.16/wx/24.02,1002.2,86 2006.161.08:04:21.07/fmout-gps/S +4.50E-07 2006.161.08:04:21.08:scan_name=161-0805,k06161,60 2006.161.08:04:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.161.08:04:21.14#flagr#flagr/antenna,new-source 2006.161.08:04:22.14:checkk5 2006.161.08:04:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:04:22.94/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:04:23.33/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:04:23.84/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:04:24.26/chk_obsdata//k5ts1/T1610803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:04:24.66/chk_obsdata//k5ts2/T1610803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:04:25.05/chk_obsdata//k5ts3/T1610803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:04:25.57/chk_obsdata//k5ts4/T1610803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:04:26.76/k5log//k5ts1_log_newline 2006.161.08:04:27.60/k5log//k5ts2_log_newline 2006.161.08:04:28.39/k5log//k5ts3_log_newline 2006.161.08:04:29.22/k5log//k5ts4_log_newline 2006.161.08:04:29.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:04:29.25:4f8m12a=2 2006.161.08:04:29.25$4f8m12a/echo=on 2006.161.08:04:29.25$4f8m12a/pcalon 2006.161.08:04:29.25$pcalon/"no phase cal control is implemented here 2006.161.08:04:29.25$4f8m12a/"tpicd=stop 2006.161.08:04:29.25$4f8m12a/vc4f8 2006.161.08:04:29.25$vc4f8/valo=1,532.99 2006.161.08:04:29.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.08:04:29.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.08:04:29.25#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:29.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:29.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:29.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:29.25#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:04:29.25#ibcon#first serial, iclass 15, count 0 2006.161.08:04:29.25#ibcon#enter sib2, iclass 15, count 0 2006.161.08:04:29.25#ibcon#flushed, iclass 15, count 0 2006.161.08:04:29.25#ibcon#about to write, iclass 15, count 0 2006.161.08:04:29.25#ibcon#wrote, iclass 15, count 0 2006.161.08:04:29.25#ibcon#about to read 3, iclass 15, count 0 2006.161.08:04:29.30#ibcon#read 3, iclass 15, count 0 2006.161.08:04:29.30#ibcon#about to read 4, iclass 15, count 0 2006.161.08:04:29.30#ibcon#read 4, iclass 15, count 0 2006.161.08:04:29.30#ibcon#about to read 5, iclass 15, count 0 2006.161.08:04:29.30#ibcon#read 5, iclass 15, count 0 2006.161.08:04:29.30#ibcon#about to read 6, iclass 15, count 0 2006.161.08:04:29.30#ibcon#read 6, iclass 15, count 0 2006.161.08:04:29.30#ibcon#end of sib2, iclass 15, count 0 2006.161.08:04:29.30#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:04:29.30#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:04:29.30#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:04:29.30#ibcon#*before write, iclass 15, count 0 2006.161.08:04:29.30#ibcon#enter sib2, iclass 15, count 0 2006.161.08:04:29.30#ibcon#flushed, iclass 15, count 0 2006.161.08:04:29.30#ibcon#about to write, iclass 15, count 0 2006.161.08:04:29.30#ibcon#wrote, iclass 15, count 0 2006.161.08:04:29.30#ibcon#about to read 3, iclass 15, count 0 2006.161.08:04:29.34#ibcon#read 3, iclass 15, count 0 2006.161.08:04:29.34#ibcon#about to read 4, iclass 15, count 0 2006.161.08:04:29.34#ibcon#read 4, iclass 15, count 0 2006.161.08:04:29.34#ibcon#about to read 5, iclass 15, count 0 2006.161.08:04:29.34#ibcon#read 5, iclass 15, count 0 2006.161.08:04:29.34#ibcon#about to read 6, iclass 15, count 0 2006.161.08:04:29.34#ibcon#read 6, iclass 15, count 0 2006.161.08:04:29.34#ibcon#end of sib2, iclass 15, count 0 2006.161.08:04:29.34#ibcon#*after write, iclass 15, count 0 2006.161.08:04:29.34#ibcon#*before return 0, iclass 15, count 0 2006.161.08:04:29.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:29.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:29.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:04:29.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:04:29.34$vc4f8/va=1,8 2006.161.08:04:29.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.08:04:29.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.08:04:29.34#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:29.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:29.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:29.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:29.34#ibcon#enter wrdev, iclass 17, count 2 2006.161.08:04:29.34#ibcon#first serial, iclass 17, count 2 2006.161.08:04:29.34#ibcon#enter sib2, iclass 17, count 2 2006.161.08:04:29.34#ibcon#flushed, iclass 17, count 2 2006.161.08:04:29.34#ibcon#about to write, iclass 17, count 2 2006.161.08:04:29.34#ibcon#wrote, iclass 17, count 2 2006.161.08:04:29.34#ibcon#about to read 3, iclass 17, count 2 2006.161.08:04:29.37#ibcon#read 3, iclass 17, count 2 2006.161.08:04:29.37#ibcon#about to read 4, iclass 17, count 2 2006.161.08:04:29.37#ibcon#read 4, iclass 17, count 2 2006.161.08:04:29.37#ibcon#about to read 5, iclass 17, count 2 2006.161.08:04:29.37#ibcon#read 5, iclass 17, count 2 2006.161.08:04:29.37#ibcon#about to read 6, iclass 17, count 2 2006.161.08:04:29.37#ibcon#read 6, iclass 17, count 2 2006.161.08:04:29.37#ibcon#end of sib2, iclass 17, count 2 2006.161.08:04:29.37#ibcon#*mode == 0, iclass 17, count 2 2006.161.08:04:29.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.08:04:29.37#ibcon#[25=AT01-08\r\n] 2006.161.08:04:29.37#ibcon#*before write, iclass 17, count 2 2006.161.08:04:29.37#ibcon#enter sib2, iclass 17, count 2 2006.161.08:04:29.37#ibcon#flushed, iclass 17, count 2 2006.161.08:04:29.37#ibcon#about to write, iclass 17, count 2 2006.161.08:04:29.37#ibcon#wrote, iclass 17, count 2 2006.161.08:04:29.37#ibcon#about to read 3, iclass 17, count 2 2006.161.08:04:29.41#ibcon#read 3, iclass 17, count 2 2006.161.08:04:29.41#ibcon#about to read 4, iclass 17, count 2 2006.161.08:04:29.41#ibcon#read 4, iclass 17, count 2 2006.161.08:04:29.41#ibcon#about to read 5, iclass 17, count 2 2006.161.08:04:29.41#ibcon#read 5, iclass 17, count 2 2006.161.08:04:29.41#ibcon#about to read 6, iclass 17, count 2 2006.161.08:04:29.41#ibcon#read 6, iclass 17, count 2 2006.161.08:04:29.41#ibcon#end of sib2, iclass 17, count 2 2006.161.08:04:29.41#ibcon#*after write, iclass 17, count 2 2006.161.08:04:29.41#ibcon#*before return 0, iclass 17, count 2 2006.161.08:04:29.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:29.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:29.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.08:04:29.41#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:29.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:29.52#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:29.52#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:29.52#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:04:29.52#ibcon#first serial, iclass 17, count 0 2006.161.08:04:29.52#ibcon#enter sib2, iclass 17, count 0 2006.161.08:04:29.52#ibcon#flushed, iclass 17, count 0 2006.161.08:04:29.52#ibcon#about to write, iclass 17, count 0 2006.161.08:04:29.52#ibcon#wrote, iclass 17, count 0 2006.161.08:04:29.52#ibcon#about to read 3, iclass 17, count 0 2006.161.08:04:29.54#ibcon#read 3, iclass 17, count 0 2006.161.08:04:29.54#ibcon#about to read 4, iclass 17, count 0 2006.161.08:04:29.54#ibcon#read 4, iclass 17, count 0 2006.161.08:04:29.54#ibcon#about to read 5, iclass 17, count 0 2006.161.08:04:29.54#ibcon#read 5, iclass 17, count 0 2006.161.08:04:29.54#ibcon#about to read 6, iclass 17, count 0 2006.161.08:04:29.54#ibcon#read 6, iclass 17, count 0 2006.161.08:04:29.54#ibcon#end of sib2, iclass 17, count 0 2006.161.08:04:29.54#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:04:29.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:04:29.54#ibcon#[25=USB\r\n] 2006.161.08:04:29.54#ibcon#*before write, iclass 17, count 0 2006.161.08:04:29.54#ibcon#enter sib2, iclass 17, count 0 2006.161.08:04:29.54#ibcon#flushed, iclass 17, count 0 2006.161.08:04:29.54#ibcon#about to write, iclass 17, count 0 2006.161.08:04:29.54#ibcon#wrote, iclass 17, count 0 2006.161.08:04:29.54#ibcon#about to read 3, iclass 17, count 0 2006.161.08:04:29.57#ibcon#read 3, iclass 17, count 0 2006.161.08:04:29.57#ibcon#about to read 4, iclass 17, count 0 2006.161.08:04:29.57#ibcon#read 4, iclass 17, count 0 2006.161.08:04:29.57#ibcon#about to read 5, iclass 17, count 0 2006.161.08:04:29.57#ibcon#read 5, iclass 17, count 0 2006.161.08:04:29.57#ibcon#about to read 6, iclass 17, count 0 2006.161.08:04:29.57#ibcon#read 6, iclass 17, count 0 2006.161.08:04:29.57#ibcon#end of sib2, iclass 17, count 0 2006.161.08:04:29.57#ibcon#*after write, iclass 17, count 0 2006.161.08:04:29.57#ibcon#*before return 0, iclass 17, count 0 2006.161.08:04:29.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:29.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:29.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:04:29.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:04:29.57$vc4f8/valo=2,572.99 2006.161.08:04:29.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:04:29.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:04:29.57#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:29.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:29.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:29.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:29.57#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:04:29.57#ibcon#first serial, iclass 19, count 0 2006.161.08:04:29.57#ibcon#enter sib2, iclass 19, count 0 2006.161.08:04:29.57#ibcon#flushed, iclass 19, count 0 2006.161.08:04:29.57#ibcon#about to write, iclass 19, count 0 2006.161.08:04:29.57#ibcon#wrote, iclass 19, count 0 2006.161.08:04:29.57#ibcon#about to read 3, iclass 19, count 0 2006.161.08:04:29.59#ibcon#read 3, iclass 19, count 0 2006.161.08:04:29.59#ibcon#about to read 4, iclass 19, count 0 2006.161.08:04:29.59#ibcon#read 4, iclass 19, count 0 2006.161.08:04:29.59#ibcon#about to read 5, iclass 19, count 0 2006.161.08:04:29.59#ibcon#read 5, iclass 19, count 0 2006.161.08:04:29.59#ibcon#about to read 6, iclass 19, count 0 2006.161.08:04:29.59#ibcon#read 6, iclass 19, count 0 2006.161.08:04:29.59#ibcon#end of sib2, iclass 19, count 0 2006.161.08:04:29.59#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:04:29.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:04:29.59#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:04:29.59#ibcon#*before write, iclass 19, count 0 2006.161.08:04:29.59#ibcon#enter sib2, iclass 19, count 0 2006.161.08:04:29.59#ibcon#flushed, iclass 19, count 0 2006.161.08:04:29.59#ibcon#about to write, iclass 19, count 0 2006.161.08:04:29.59#ibcon#wrote, iclass 19, count 0 2006.161.08:04:29.59#ibcon#about to read 3, iclass 19, count 0 2006.161.08:04:29.63#ibcon#read 3, iclass 19, count 0 2006.161.08:04:29.63#ibcon#about to read 4, iclass 19, count 0 2006.161.08:04:29.63#ibcon#read 4, iclass 19, count 0 2006.161.08:04:29.63#ibcon#about to read 5, iclass 19, count 0 2006.161.08:04:29.63#ibcon#read 5, iclass 19, count 0 2006.161.08:04:29.63#ibcon#about to read 6, iclass 19, count 0 2006.161.08:04:29.63#ibcon#read 6, iclass 19, count 0 2006.161.08:04:29.63#ibcon#end of sib2, iclass 19, count 0 2006.161.08:04:29.63#ibcon#*after write, iclass 19, count 0 2006.161.08:04:29.63#ibcon#*before return 0, iclass 19, count 0 2006.161.08:04:29.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:29.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:29.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:04:29.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:04:29.63$vc4f8/va=2,7 2006.161.08:04:29.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:04:29.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:04:29.63#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:29.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:29.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:29.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:29.69#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:04:29.69#ibcon#first serial, iclass 21, count 2 2006.161.08:04:29.69#ibcon#enter sib2, iclass 21, count 2 2006.161.08:04:29.69#ibcon#flushed, iclass 21, count 2 2006.161.08:04:29.69#ibcon#about to write, iclass 21, count 2 2006.161.08:04:29.69#ibcon#wrote, iclass 21, count 2 2006.161.08:04:29.69#ibcon#about to read 3, iclass 21, count 2 2006.161.08:04:29.72#ibcon#read 3, iclass 21, count 2 2006.161.08:04:29.72#ibcon#about to read 4, iclass 21, count 2 2006.161.08:04:29.72#ibcon#read 4, iclass 21, count 2 2006.161.08:04:29.72#ibcon#about to read 5, iclass 21, count 2 2006.161.08:04:29.72#ibcon#read 5, iclass 21, count 2 2006.161.08:04:29.72#ibcon#about to read 6, iclass 21, count 2 2006.161.08:04:29.72#ibcon#read 6, iclass 21, count 2 2006.161.08:04:29.72#ibcon#end of sib2, iclass 21, count 2 2006.161.08:04:29.72#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:04:29.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:04:29.72#ibcon#[25=AT02-07\r\n] 2006.161.08:04:29.72#ibcon#*before write, iclass 21, count 2 2006.161.08:04:29.72#ibcon#enter sib2, iclass 21, count 2 2006.161.08:04:29.72#ibcon#flushed, iclass 21, count 2 2006.161.08:04:29.72#ibcon#about to write, iclass 21, count 2 2006.161.08:04:29.72#ibcon#wrote, iclass 21, count 2 2006.161.08:04:29.72#ibcon#about to read 3, iclass 21, count 2 2006.161.08:04:29.75#ibcon#read 3, iclass 21, count 2 2006.161.08:04:29.75#ibcon#about to read 4, iclass 21, count 2 2006.161.08:04:29.75#ibcon#read 4, iclass 21, count 2 2006.161.08:04:29.75#ibcon#about to read 5, iclass 21, count 2 2006.161.08:04:29.75#ibcon#read 5, iclass 21, count 2 2006.161.08:04:29.75#ibcon#about to read 6, iclass 21, count 2 2006.161.08:04:29.75#ibcon#read 6, iclass 21, count 2 2006.161.08:04:29.75#ibcon#end of sib2, iclass 21, count 2 2006.161.08:04:29.75#ibcon#*after write, iclass 21, count 2 2006.161.08:04:29.75#ibcon#*before return 0, iclass 21, count 2 2006.161.08:04:29.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:29.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:29.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:04:29.75#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:29.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:29.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:29.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:29.87#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:04:29.87#ibcon#first serial, iclass 21, count 0 2006.161.08:04:29.87#ibcon#enter sib2, iclass 21, count 0 2006.161.08:04:29.87#ibcon#flushed, iclass 21, count 0 2006.161.08:04:29.87#ibcon#about to write, iclass 21, count 0 2006.161.08:04:29.87#ibcon#wrote, iclass 21, count 0 2006.161.08:04:29.87#ibcon#about to read 3, iclass 21, count 0 2006.161.08:04:29.89#ibcon#read 3, iclass 21, count 0 2006.161.08:04:29.89#ibcon#about to read 4, iclass 21, count 0 2006.161.08:04:29.89#ibcon#read 4, iclass 21, count 0 2006.161.08:04:29.89#ibcon#about to read 5, iclass 21, count 0 2006.161.08:04:29.89#ibcon#read 5, iclass 21, count 0 2006.161.08:04:29.89#ibcon#about to read 6, iclass 21, count 0 2006.161.08:04:29.89#ibcon#read 6, iclass 21, count 0 2006.161.08:04:29.89#ibcon#end of sib2, iclass 21, count 0 2006.161.08:04:29.89#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:04:29.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:04:29.89#ibcon#[25=USB\r\n] 2006.161.08:04:29.89#ibcon#*before write, iclass 21, count 0 2006.161.08:04:29.89#ibcon#enter sib2, iclass 21, count 0 2006.161.08:04:29.89#ibcon#flushed, iclass 21, count 0 2006.161.08:04:29.89#ibcon#about to write, iclass 21, count 0 2006.161.08:04:29.89#ibcon#wrote, iclass 21, count 0 2006.161.08:04:29.89#ibcon#about to read 3, iclass 21, count 0 2006.161.08:04:29.92#ibcon#read 3, iclass 21, count 0 2006.161.08:04:29.92#ibcon#about to read 4, iclass 21, count 0 2006.161.08:04:29.92#ibcon#read 4, iclass 21, count 0 2006.161.08:04:29.92#ibcon#about to read 5, iclass 21, count 0 2006.161.08:04:29.92#ibcon#read 5, iclass 21, count 0 2006.161.08:04:29.92#ibcon#about to read 6, iclass 21, count 0 2006.161.08:04:29.92#ibcon#read 6, iclass 21, count 0 2006.161.08:04:29.92#ibcon#end of sib2, iclass 21, count 0 2006.161.08:04:29.92#ibcon#*after write, iclass 21, count 0 2006.161.08:04:29.92#ibcon#*before return 0, iclass 21, count 0 2006.161.08:04:29.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:29.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:29.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:04:29.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:04:29.92$vc4f8/valo=3,672.99 2006.161.08:04:29.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:04:29.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:04:29.92#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:29.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:29.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:29.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:29.92#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:04:29.92#ibcon#first serial, iclass 23, count 0 2006.161.08:04:29.92#ibcon#enter sib2, iclass 23, count 0 2006.161.08:04:29.92#ibcon#flushed, iclass 23, count 0 2006.161.08:04:29.92#ibcon#about to write, iclass 23, count 0 2006.161.08:04:29.92#ibcon#wrote, iclass 23, count 0 2006.161.08:04:29.92#ibcon#about to read 3, iclass 23, count 0 2006.161.08:04:29.94#ibcon#read 3, iclass 23, count 0 2006.161.08:04:29.94#ibcon#about to read 4, iclass 23, count 0 2006.161.08:04:29.94#ibcon#read 4, iclass 23, count 0 2006.161.08:04:29.94#ibcon#about to read 5, iclass 23, count 0 2006.161.08:04:29.94#ibcon#read 5, iclass 23, count 0 2006.161.08:04:29.94#ibcon#about to read 6, iclass 23, count 0 2006.161.08:04:29.94#ibcon#read 6, iclass 23, count 0 2006.161.08:04:29.94#ibcon#end of sib2, iclass 23, count 0 2006.161.08:04:29.94#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:04:29.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:04:29.94#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:04:29.94#ibcon#*before write, iclass 23, count 0 2006.161.08:04:29.94#ibcon#enter sib2, iclass 23, count 0 2006.161.08:04:29.94#ibcon#flushed, iclass 23, count 0 2006.161.08:04:29.94#ibcon#about to write, iclass 23, count 0 2006.161.08:04:29.94#ibcon#wrote, iclass 23, count 0 2006.161.08:04:29.94#ibcon#about to read 3, iclass 23, count 0 2006.161.08:04:29.98#ibcon#read 3, iclass 23, count 0 2006.161.08:04:29.98#ibcon#about to read 4, iclass 23, count 0 2006.161.08:04:29.98#ibcon#read 4, iclass 23, count 0 2006.161.08:04:29.98#ibcon#about to read 5, iclass 23, count 0 2006.161.08:04:29.98#ibcon#read 5, iclass 23, count 0 2006.161.08:04:29.98#ibcon#about to read 6, iclass 23, count 0 2006.161.08:04:29.98#ibcon#read 6, iclass 23, count 0 2006.161.08:04:29.98#ibcon#end of sib2, iclass 23, count 0 2006.161.08:04:29.98#ibcon#*after write, iclass 23, count 0 2006.161.08:04:29.98#ibcon#*before return 0, iclass 23, count 0 2006.161.08:04:29.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:29.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:29.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:04:29.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:04:29.98$vc4f8/va=3,6 2006.161.08:04:29.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.08:04:29.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.08:04:29.98#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:29.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:30.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:30.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:30.04#ibcon#enter wrdev, iclass 25, count 2 2006.161.08:04:30.04#ibcon#first serial, iclass 25, count 2 2006.161.08:04:30.04#ibcon#enter sib2, iclass 25, count 2 2006.161.08:04:30.04#ibcon#flushed, iclass 25, count 2 2006.161.08:04:30.04#ibcon#about to write, iclass 25, count 2 2006.161.08:04:30.04#ibcon#wrote, iclass 25, count 2 2006.161.08:04:30.04#ibcon#about to read 3, iclass 25, count 2 2006.161.08:04:30.06#ibcon#read 3, iclass 25, count 2 2006.161.08:04:30.06#ibcon#about to read 4, iclass 25, count 2 2006.161.08:04:30.06#ibcon#read 4, iclass 25, count 2 2006.161.08:04:30.06#ibcon#about to read 5, iclass 25, count 2 2006.161.08:04:30.06#ibcon#read 5, iclass 25, count 2 2006.161.08:04:30.06#ibcon#about to read 6, iclass 25, count 2 2006.161.08:04:30.06#ibcon#read 6, iclass 25, count 2 2006.161.08:04:30.06#ibcon#end of sib2, iclass 25, count 2 2006.161.08:04:30.06#ibcon#*mode == 0, iclass 25, count 2 2006.161.08:04:30.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.08:04:30.06#ibcon#[25=AT03-06\r\n] 2006.161.08:04:30.06#ibcon#*before write, iclass 25, count 2 2006.161.08:04:30.06#ibcon#enter sib2, iclass 25, count 2 2006.161.08:04:30.06#ibcon#flushed, iclass 25, count 2 2006.161.08:04:30.06#ibcon#about to write, iclass 25, count 2 2006.161.08:04:30.06#ibcon#wrote, iclass 25, count 2 2006.161.08:04:30.06#ibcon#about to read 3, iclass 25, count 2 2006.161.08:04:30.09#ibcon#read 3, iclass 25, count 2 2006.161.08:04:30.09#ibcon#about to read 4, iclass 25, count 2 2006.161.08:04:30.09#ibcon#read 4, iclass 25, count 2 2006.161.08:04:30.09#ibcon#about to read 5, iclass 25, count 2 2006.161.08:04:30.09#ibcon#read 5, iclass 25, count 2 2006.161.08:04:30.09#ibcon#about to read 6, iclass 25, count 2 2006.161.08:04:30.09#ibcon#read 6, iclass 25, count 2 2006.161.08:04:30.09#ibcon#end of sib2, iclass 25, count 2 2006.161.08:04:30.09#ibcon#*after write, iclass 25, count 2 2006.161.08:04:30.09#ibcon#*before return 0, iclass 25, count 2 2006.161.08:04:30.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:30.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:30.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.08:04:30.09#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:30.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:30.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:30.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:30.21#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:04:30.21#ibcon#first serial, iclass 25, count 0 2006.161.08:04:30.21#ibcon#enter sib2, iclass 25, count 0 2006.161.08:04:30.21#ibcon#flushed, iclass 25, count 0 2006.161.08:04:30.21#ibcon#about to write, iclass 25, count 0 2006.161.08:04:30.21#ibcon#wrote, iclass 25, count 0 2006.161.08:04:30.21#ibcon#about to read 3, iclass 25, count 0 2006.161.08:04:30.23#ibcon#read 3, iclass 25, count 0 2006.161.08:04:30.23#ibcon#about to read 4, iclass 25, count 0 2006.161.08:04:30.23#ibcon#read 4, iclass 25, count 0 2006.161.08:04:30.23#ibcon#about to read 5, iclass 25, count 0 2006.161.08:04:30.23#ibcon#read 5, iclass 25, count 0 2006.161.08:04:30.23#ibcon#about to read 6, iclass 25, count 0 2006.161.08:04:30.23#ibcon#read 6, iclass 25, count 0 2006.161.08:04:30.23#ibcon#end of sib2, iclass 25, count 0 2006.161.08:04:30.23#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:04:30.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:04:30.23#ibcon#[25=USB\r\n] 2006.161.08:04:30.23#ibcon#*before write, iclass 25, count 0 2006.161.08:04:30.23#ibcon#enter sib2, iclass 25, count 0 2006.161.08:04:30.23#ibcon#flushed, iclass 25, count 0 2006.161.08:04:30.23#ibcon#about to write, iclass 25, count 0 2006.161.08:04:30.23#ibcon#wrote, iclass 25, count 0 2006.161.08:04:30.23#ibcon#about to read 3, iclass 25, count 0 2006.161.08:04:30.26#ibcon#read 3, iclass 25, count 0 2006.161.08:04:30.26#ibcon#about to read 4, iclass 25, count 0 2006.161.08:04:30.26#ibcon#read 4, iclass 25, count 0 2006.161.08:04:30.26#ibcon#about to read 5, iclass 25, count 0 2006.161.08:04:30.26#ibcon#read 5, iclass 25, count 0 2006.161.08:04:30.26#ibcon#about to read 6, iclass 25, count 0 2006.161.08:04:30.26#ibcon#read 6, iclass 25, count 0 2006.161.08:04:30.26#ibcon#end of sib2, iclass 25, count 0 2006.161.08:04:30.26#ibcon#*after write, iclass 25, count 0 2006.161.08:04:30.26#ibcon#*before return 0, iclass 25, count 0 2006.161.08:04:30.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:30.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:30.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:04:30.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:04:30.26$vc4f8/valo=4,832.99 2006.161.08:04:30.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.08:04:30.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.08:04:30.26#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:30.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:30.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:30.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:30.26#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:04:30.26#ibcon#first serial, iclass 27, count 0 2006.161.08:04:30.26#ibcon#enter sib2, iclass 27, count 0 2006.161.08:04:30.26#ibcon#flushed, iclass 27, count 0 2006.161.08:04:30.26#ibcon#about to write, iclass 27, count 0 2006.161.08:04:30.26#ibcon#wrote, iclass 27, count 0 2006.161.08:04:30.26#ibcon#about to read 3, iclass 27, count 0 2006.161.08:04:30.28#ibcon#read 3, iclass 27, count 0 2006.161.08:04:30.28#ibcon#about to read 4, iclass 27, count 0 2006.161.08:04:30.28#ibcon#read 4, iclass 27, count 0 2006.161.08:04:30.28#ibcon#about to read 5, iclass 27, count 0 2006.161.08:04:30.28#ibcon#read 5, iclass 27, count 0 2006.161.08:04:30.28#ibcon#about to read 6, iclass 27, count 0 2006.161.08:04:30.28#ibcon#read 6, iclass 27, count 0 2006.161.08:04:30.28#ibcon#end of sib2, iclass 27, count 0 2006.161.08:04:30.28#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:04:30.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:04:30.28#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:04:30.28#ibcon#*before write, iclass 27, count 0 2006.161.08:04:30.28#ibcon#enter sib2, iclass 27, count 0 2006.161.08:04:30.28#ibcon#flushed, iclass 27, count 0 2006.161.08:04:30.28#ibcon#about to write, iclass 27, count 0 2006.161.08:04:30.28#ibcon#wrote, iclass 27, count 0 2006.161.08:04:30.28#ibcon#about to read 3, iclass 27, count 0 2006.161.08:04:30.32#ibcon#read 3, iclass 27, count 0 2006.161.08:04:30.32#ibcon#about to read 4, iclass 27, count 0 2006.161.08:04:30.32#ibcon#read 4, iclass 27, count 0 2006.161.08:04:30.32#ibcon#about to read 5, iclass 27, count 0 2006.161.08:04:30.32#ibcon#read 5, iclass 27, count 0 2006.161.08:04:30.32#ibcon#about to read 6, iclass 27, count 0 2006.161.08:04:30.32#ibcon#read 6, iclass 27, count 0 2006.161.08:04:30.32#ibcon#end of sib2, iclass 27, count 0 2006.161.08:04:30.32#ibcon#*after write, iclass 27, count 0 2006.161.08:04:30.32#ibcon#*before return 0, iclass 27, count 0 2006.161.08:04:30.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:30.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:30.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:04:30.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:04:30.32$vc4f8/va=4,7 2006.161.08:04:30.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.08:04:30.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.08:04:30.32#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:30.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:30.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:30.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:30.38#ibcon#enter wrdev, iclass 29, count 2 2006.161.08:04:30.38#ibcon#first serial, iclass 29, count 2 2006.161.08:04:30.38#ibcon#enter sib2, iclass 29, count 2 2006.161.08:04:30.38#ibcon#flushed, iclass 29, count 2 2006.161.08:04:30.38#ibcon#about to write, iclass 29, count 2 2006.161.08:04:30.38#ibcon#wrote, iclass 29, count 2 2006.161.08:04:30.38#ibcon#about to read 3, iclass 29, count 2 2006.161.08:04:30.40#ibcon#read 3, iclass 29, count 2 2006.161.08:04:30.40#ibcon#about to read 4, iclass 29, count 2 2006.161.08:04:30.40#ibcon#read 4, iclass 29, count 2 2006.161.08:04:30.40#ibcon#about to read 5, iclass 29, count 2 2006.161.08:04:30.40#ibcon#read 5, iclass 29, count 2 2006.161.08:04:30.40#ibcon#about to read 6, iclass 29, count 2 2006.161.08:04:30.40#ibcon#read 6, iclass 29, count 2 2006.161.08:04:30.40#ibcon#end of sib2, iclass 29, count 2 2006.161.08:04:30.40#ibcon#*mode == 0, iclass 29, count 2 2006.161.08:04:30.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.08:04:30.40#ibcon#[25=AT04-07\r\n] 2006.161.08:04:30.40#ibcon#*before write, iclass 29, count 2 2006.161.08:04:30.40#ibcon#enter sib2, iclass 29, count 2 2006.161.08:04:30.40#ibcon#flushed, iclass 29, count 2 2006.161.08:04:30.40#ibcon#about to write, iclass 29, count 2 2006.161.08:04:30.40#ibcon#wrote, iclass 29, count 2 2006.161.08:04:30.40#ibcon#about to read 3, iclass 29, count 2 2006.161.08:04:30.43#ibcon#read 3, iclass 29, count 2 2006.161.08:04:30.43#ibcon#about to read 4, iclass 29, count 2 2006.161.08:04:30.43#ibcon#read 4, iclass 29, count 2 2006.161.08:04:30.43#ibcon#about to read 5, iclass 29, count 2 2006.161.08:04:30.43#ibcon#read 5, iclass 29, count 2 2006.161.08:04:30.43#ibcon#about to read 6, iclass 29, count 2 2006.161.08:04:30.43#ibcon#read 6, iclass 29, count 2 2006.161.08:04:30.43#ibcon#end of sib2, iclass 29, count 2 2006.161.08:04:30.43#ibcon#*after write, iclass 29, count 2 2006.161.08:04:30.43#ibcon#*before return 0, iclass 29, count 2 2006.161.08:04:30.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:30.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:30.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.08:04:30.43#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:30.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:30.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:30.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:30.55#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:04:30.55#ibcon#first serial, iclass 29, count 0 2006.161.08:04:30.55#ibcon#enter sib2, iclass 29, count 0 2006.161.08:04:30.55#ibcon#flushed, iclass 29, count 0 2006.161.08:04:30.55#ibcon#about to write, iclass 29, count 0 2006.161.08:04:30.55#ibcon#wrote, iclass 29, count 0 2006.161.08:04:30.55#ibcon#about to read 3, iclass 29, count 0 2006.161.08:04:30.57#ibcon#read 3, iclass 29, count 0 2006.161.08:04:30.57#ibcon#about to read 4, iclass 29, count 0 2006.161.08:04:30.57#ibcon#read 4, iclass 29, count 0 2006.161.08:04:30.57#ibcon#about to read 5, iclass 29, count 0 2006.161.08:04:30.57#ibcon#read 5, iclass 29, count 0 2006.161.08:04:30.57#ibcon#about to read 6, iclass 29, count 0 2006.161.08:04:30.57#ibcon#read 6, iclass 29, count 0 2006.161.08:04:30.57#ibcon#end of sib2, iclass 29, count 0 2006.161.08:04:30.57#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:04:30.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:04:30.57#ibcon#[25=USB\r\n] 2006.161.08:04:30.57#ibcon#*before write, iclass 29, count 0 2006.161.08:04:30.57#ibcon#enter sib2, iclass 29, count 0 2006.161.08:04:30.57#ibcon#flushed, iclass 29, count 0 2006.161.08:04:30.57#ibcon#about to write, iclass 29, count 0 2006.161.08:04:30.57#ibcon#wrote, iclass 29, count 0 2006.161.08:04:30.57#ibcon#about to read 3, iclass 29, count 0 2006.161.08:04:30.60#ibcon#read 3, iclass 29, count 0 2006.161.08:04:30.60#ibcon#about to read 4, iclass 29, count 0 2006.161.08:04:30.60#ibcon#read 4, iclass 29, count 0 2006.161.08:04:30.60#ibcon#about to read 5, iclass 29, count 0 2006.161.08:04:30.60#ibcon#read 5, iclass 29, count 0 2006.161.08:04:30.60#ibcon#about to read 6, iclass 29, count 0 2006.161.08:04:30.60#ibcon#read 6, iclass 29, count 0 2006.161.08:04:30.60#ibcon#end of sib2, iclass 29, count 0 2006.161.08:04:30.60#ibcon#*after write, iclass 29, count 0 2006.161.08:04:30.60#ibcon#*before return 0, iclass 29, count 0 2006.161.08:04:30.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:30.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:30.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:04:30.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:04:30.60$vc4f8/valo=5,652.99 2006.161.08:04:30.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:04:30.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:04:30.60#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:30.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:30.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:30.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:30.60#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:04:30.60#ibcon#first serial, iclass 31, count 0 2006.161.08:04:30.60#ibcon#enter sib2, iclass 31, count 0 2006.161.08:04:30.60#ibcon#flushed, iclass 31, count 0 2006.161.08:04:30.60#ibcon#about to write, iclass 31, count 0 2006.161.08:04:30.60#ibcon#wrote, iclass 31, count 0 2006.161.08:04:30.60#ibcon#about to read 3, iclass 31, count 0 2006.161.08:04:30.62#ibcon#read 3, iclass 31, count 0 2006.161.08:04:30.62#ibcon#about to read 4, iclass 31, count 0 2006.161.08:04:30.62#ibcon#read 4, iclass 31, count 0 2006.161.08:04:30.62#ibcon#about to read 5, iclass 31, count 0 2006.161.08:04:30.62#ibcon#read 5, iclass 31, count 0 2006.161.08:04:30.62#ibcon#about to read 6, iclass 31, count 0 2006.161.08:04:30.62#ibcon#read 6, iclass 31, count 0 2006.161.08:04:30.62#ibcon#end of sib2, iclass 31, count 0 2006.161.08:04:30.62#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:04:30.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:04:30.62#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:04:30.62#ibcon#*before write, iclass 31, count 0 2006.161.08:04:30.62#ibcon#enter sib2, iclass 31, count 0 2006.161.08:04:30.62#ibcon#flushed, iclass 31, count 0 2006.161.08:04:30.62#ibcon#about to write, iclass 31, count 0 2006.161.08:04:30.62#ibcon#wrote, iclass 31, count 0 2006.161.08:04:30.62#ibcon#about to read 3, iclass 31, count 0 2006.161.08:04:30.66#ibcon#read 3, iclass 31, count 0 2006.161.08:04:30.66#ibcon#about to read 4, iclass 31, count 0 2006.161.08:04:30.66#ibcon#read 4, iclass 31, count 0 2006.161.08:04:30.66#ibcon#about to read 5, iclass 31, count 0 2006.161.08:04:30.66#ibcon#read 5, iclass 31, count 0 2006.161.08:04:30.66#ibcon#about to read 6, iclass 31, count 0 2006.161.08:04:30.66#ibcon#read 6, iclass 31, count 0 2006.161.08:04:30.66#ibcon#end of sib2, iclass 31, count 0 2006.161.08:04:30.66#ibcon#*after write, iclass 31, count 0 2006.161.08:04:30.66#ibcon#*before return 0, iclass 31, count 0 2006.161.08:04:30.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:30.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:30.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:04:30.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:04:30.66$vc4f8/va=5,7 2006.161.08:04:30.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.08:04:30.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.08:04:30.66#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:30.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:30.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:30.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:30.72#ibcon#enter wrdev, iclass 33, count 2 2006.161.08:04:30.72#ibcon#first serial, iclass 33, count 2 2006.161.08:04:30.72#ibcon#enter sib2, iclass 33, count 2 2006.161.08:04:30.72#ibcon#flushed, iclass 33, count 2 2006.161.08:04:30.72#ibcon#about to write, iclass 33, count 2 2006.161.08:04:30.72#ibcon#wrote, iclass 33, count 2 2006.161.08:04:30.72#ibcon#about to read 3, iclass 33, count 2 2006.161.08:04:30.74#ibcon#read 3, iclass 33, count 2 2006.161.08:04:30.74#ibcon#about to read 4, iclass 33, count 2 2006.161.08:04:30.74#ibcon#read 4, iclass 33, count 2 2006.161.08:04:30.74#ibcon#about to read 5, iclass 33, count 2 2006.161.08:04:30.74#ibcon#read 5, iclass 33, count 2 2006.161.08:04:30.74#ibcon#about to read 6, iclass 33, count 2 2006.161.08:04:30.74#ibcon#read 6, iclass 33, count 2 2006.161.08:04:30.74#ibcon#end of sib2, iclass 33, count 2 2006.161.08:04:30.74#ibcon#*mode == 0, iclass 33, count 2 2006.161.08:04:30.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.08:04:30.74#ibcon#[25=AT05-07\r\n] 2006.161.08:04:30.74#ibcon#*before write, iclass 33, count 2 2006.161.08:04:30.74#ibcon#enter sib2, iclass 33, count 2 2006.161.08:04:30.74#ibcon#flushed, iclass 33, count 2 2006.161.08:04:30.74#ibcon#about to write, iclass 33, count 2 2006.161.08:04:30.74#ibcon#wrote, iclass 33, count 2 2006.161.08:04:30.74#ibcon#about to read 3, iclass 33, count 2 2006.161.08:04:30.77#ibcon#read 3, iclass 33, count 2 2006.161.08:04:30.77#ibcon#about to read 4, iclass 33, count 2 2006.161.08:04:30.77#ibcon#read 4, iclass 33, count 2 2006.161.08:04:30.77#ibcon#about to read 5, iclass 33, count 2 2006.161.08:04:30.77#ibcon#read 5, iclass 33, count 2 2006.161.08:04:30.77#ibcon#about to read 6, iclass 33, count 2 2006.161.08:04:30.77#ibcon#read 6, iclass 33, count 2 2006.161.08:04:30.77#ibcon#end of sib2, iclass 33, count 2 2006.161.08:04:30.77#ibcon#*after write, iclass 33, count 2 2006.161.08:04:30.77#ibcon#*before return 0, iclass 33, count 2 2006.161.08:04:30.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:30.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:30.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.08:04:30.77#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:30.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:30.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:30.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:30.89#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:04:30.89#ibcon#first serial, iclass 33, count 0 2006.161.08:04:30.89#ibcon#enter sib2, iclass 33, count 0 2006.161.08:04:30.89#ibcon#flushed, iclass 33, count 0 2006.161.08:04:30.89#ibcon#about to write, iclass 33, count 0 2006.161.08:04:30.89#ibcon#wrote, iclass 33, count 0 2006.161.08:04:30.89#ibcon#about to read 3, iclass 33, count 0 2006.161.08:04:30.91#ibcon#read 3, iclass 33, count 0 2006.161.08:04:30.91#ibcon#about to read 4, iclass 33, count 0 2006.161.08:04:30.91#ibcon#read 4, iclass 33, count 0 2006.161.08:04:30.91#ibcon#about to read 5, iclass 33, count 0 2006.161.08:04:30.91#ibcon#read 5, iclass 33, count 0 2006.161.08:04:30.91#ibcon#about to read 6, iclass 33, count 0 2006.161.08:04:30.91#ibcon#read 6, iclass 33, count 0 2006.161.08:04:30.91#ibcon#end of sib2, iclass 33, count 0 2006.161.08:04:30.91#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:04:30.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:04:30.91#ibcon#[25=USB\r\n] 2006.161.08:04:30.91#ibcon#*before write, iclass 33, count 0 2006.161.08:04:30.91#ibcon#enter sib2, iclass 33, count 0 2006.161.08:04:30.91#ibcon#flushed, iclass 33, count 0 2006.161.08:04:30.91#ibcon#about to write, iclass 33, count 0 2006.161.08:04:30.91#ibcon#wrote, iclass 33, count 0 2006.161.08:04:30.91#ibcon#about to read 3, iclass 33, count 0 2006.161.08:04:30.94#ibcon#read 3, iclass 33, count 0 2006.161.08:04:30.94#ibcon#about to read 4, iclass 33, count 0 2006.161.08:04:30.94#ibcon#read 4, iclass 33, count 0 2006.161.08:04:30.94#ibcon#about to read 5, iclass 33, count 0 2006.161.08:04:30.94#ibcon#read 5, iclass 33, count 0 2006.161.08:04:30.94#ibcon#about to read 6, iclass 33, count 0 2006.161.08:04:30.94#ibcon#read 6, iclass 33, count 0 2006.161.08:04:30.94#ibcon#end of sib2, iclass 33, count 0 2006.161.08:04:30.94#ibcon#*after write, iclass 33, count 0 2006.161.08:04:30.94#ibcon#*before return 0, iclass 33, count 0 2006.161.08:04:30.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:30.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:30.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:04:30.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:04:30.94$vc4f8/valo=6,772.99 2006.161.08:04:30.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:04:30.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:04:30.94#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:30.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:04:30.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:04:30.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:04:30.94#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:04:30.94#ibcon#first serial, iclass 36, count 0 2006.161.08:04:30.94#ibcon#enter sib2, iclass 36, count 0 2006.161.08:04:30.94#ibcon#flushed, iclass 36, count 0 2006.161.08:04:30.94#ibcon#about to write, iclass 36, count 0 2006.161.08:04:30.94#ibcon#wrote, iclass 36, count 0 2006.161.08:04:30.94#ibcon#about to read 3, iclass 36, count 0 2006.161.08:04:30.96#ibcon#read 3, iclass 36, count 0 2006.161.08:04:30.96#ibcon#about to read 4, iclass 36, count 0 2006.161.08:04:30.96#ibcon#read 4, iclass 36, count 0 2006.161.08:04:30.96#ibcon#about to read 5, iclass 36, count 0 2006.161.08:04:30.96#ibcon#read 5, iclass 36, count 0 2006.161.08:04:30.96#ibcon#about to read 6, iclass 36, count 0 2006.161.08:04:30.96#ibcon#read 6, iclass 36, count 0 2006.161.08:04:30.96#ibcon#end of sib2, iclass 36, count 0 2006.161.08:04:30.96#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:04:30.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:04:30.96#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:04:30.96#ibcon#*before write, iclass 36, count 0 2006.161.08:04:30.96#ibcon#enter sib2, iclass 36, count 0 2006.161.08:04:30.96#ibcon#flushed, iclass 36, count 0 2006.161.08:04:30.96#ibcon#about to write, iclass 36, count 0 2006.161.08:04:30.96#ibcon#wrote, iclass 36, count 0 2006.161.08:04:30.96#ibcon#about to read 3, iclass 36, count 0 2006.161.08:04:30.97#abcon#<5=/05 3.0 5.8 24.02 861002.2\r\n> 2006.161.08:04:30.99#abcon#{5=INTERFACE CLEAR} 2006.161.08:04:31.00#ibcon#read 3, iclass 36, count 0 2006.161.08:04:31.00#ibcon#about to read 4, iclass 36, count 0 2006.161.08:04:31.00#ibcon#read 4, iclass 36, count 0 2006.161.08:04:31.00#ibcon#about to read 5, iclass 36, count 0 2006.161.08:04:31.00#ibcon#read 5, iclass 36, count 0 2006.161.08:04:31.00#ibcon#about to read 6, iclass 36, count 0 2006.161.08:04:31.00#ibcon#read 6, iclass 36, count 0 2006.161.08:04:31.00#ibcon#end of sib2, iclass 36, count 0 2006.161.08:04:31.00#ibcon#*after write, iclass 36, count 0 2006.161.08:04:31.00#ibcon#*before return 0, iclass 36, count 0 2006.161.08:04:31.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:04:31.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:04:31.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:04:31.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:04:31.00$vc4f8/va=6,6 2006.161.08:04:31.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:04:31.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:04:31.00#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:31.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:04:31.05#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:04:31.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:04:31.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:04:31.06#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:04:31.06#ibcon#first serial, iclass 40, count 2 2006.161.08:04:31.06#ibcon#enter sib2, iclass 40, count 2 2006.161.08:04:31.06#ibcon#flushed, iclass 40, count 2 2006.161.08:04:31.06#ibcon#about to write, iclass 40, count 2 2006.161.08:04:31.06#ibcon#wrote, iclass 40, count 2 2006.161.08:04:31.06#ibcon#about to read 3, iclass 40, count 2 2006.161.08:04:31.08#ibcon#read 3, iclass 40, count 2 2006.161.08:04:31.08#ibcon#about to read 4, iclass 40, count 2 2006.161.08:04:31.08#ibcon#read 4, iclass 40, count 2 2006.161.08:04:31.08#ibcon#about to read 5, iclass 40, count 2 2006.161.08:04:31.08#ibcon#read 5, iclass 40, count 2 2006.161.08:04:31.08#ibcon#about to read 6, iclass 40, count 2 2006.161.08:04:31.08#ibcon#read 6, iclass 40, count 2 2006.161.08:04:31.08#ibcon#end of sib2, iclass 40, count 2 2006.161.08:04:31.08#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:04:31.08#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:04:31.08#ibcon#[25=AT06-06\r\n] 2006.161.08:04:31.08#ibcon#*before write, iclass 40, count 2 2006.161.08:04:31.08#ibcon#enter sib2, iclass 40, count 2 2006.161.08:04:31.08#ibcon#flushed, iclass 40, count 2 2006.161.08:04:31.08#ibcon#about to write, iclass 40, count 2 2006.161.08:04:31.08#ibcon#wrote, iclass 40, count 2 2006.161.08:04:31.08#ibcon#about to read 3, iclass 40, count 2 2006.161.08:04:31.11#ibcon#read 3, iclass 40, count 2 2006.161.08:04:31.11#ibcon#about to read 4, iclass 40, count 2 2006.161.08:04:31.11#ibcon#read 4, iclass 40, count 2 2006.161.08:04:31.11#ibcon#about to read 5, iclass 40, count 2 2006.161.08:04:31.11#ibcon#read 5, iclass 40, count 2 2006.161.08:04:31.11#ibcon#about to read 6, iclass 40, count 2 2006.161.08:04:31.11#ibcon#read 6, iclass 40, count 2 2006.161.08:04:31.11#ibcon#end of sib2, iclass 40, count 2 2006.161.08:04:31.11#ibcon#*after write, iclass 40, count 2 2006.161.08:04:31.11#ibcon#*before return 0, iclass 40, count 2 2006.161.08:04:31.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:04:31.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:04:31.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:04:31.11#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:31.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:04:31.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:04:31.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:04:31.23#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:04:31.23#ibcon#first serial, iclass 40, count 0 2006.161.08:04:31.23#ibcon#enter sib2, iclass 40, count 0 2006.161.08:04:31.23#ibcon#flushed, iclass 40, count 0 2006.161.08:04:31.23#ibcon#about to write, iclass 40, count 0 2006.161.08:04:31.23#ibcon#wrote, iclass 40, count 0 2006.161.08:04:31.23#ibcon#about to read 3, iclass 40, count 0 2006.161.08:04:31.25#ibcon#read 3, iclass 40, count 0 2006.161.08:04:31.25#ibcon#about to read 4, iclass 40, count 0 2006.161.08:04:31.25#ibcon#read 4, iclass 40, count 0 2006.161.08:04:31.25#ibcon#about to read 5, iclass 40, count 0 2006.161.08:04:31.25#ibcon#read 5, iclass 40, count 0 2006.161.08:04:31.25#ibcon#about to read 6, iclass 40, count 0 2006.161.08:04:31.25#ibcon#read 6, iclass 40, count 0 2006.161.08:04:31.25#ibcon#end of sib2, iclass 40, count 0 2006.161.08:04:31.25#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:04:31.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:04:31.25#ibcon#[25=USB\r\n] 2006.161.08:04:31.25#ibcon#*before write, iclass 40, count 0 2006.161.08:04:31.25#ibcon#enter sib2, iclass 40, count 0 2006.161.08:04:31.25#ibcon#flushed, iclass 40, count 0 2006.161.08:04:31.25#ibcon#about to write, iclass 40, count 0 2006.161.08:04:31.25#ibcon#wrote, iclass 40, count 0 2006.161.08:04:31.25#ibcon#about to read 3, iclass 40, count 0 2006.161.08:04:31.28#ibcon#read 3, iclass 40, count 0 2006.161.08:04:31.28#ibcon#about to read 4, iclass 40, count 0 2006.161.08:04:31.28#ibcon#read 4, iclass 40, count 0 2006.161.08:04:31.28#ibcon#about to read 5, iclass 40, count 0 2006.161.08:04:31.28#ibcon#read 5, iclass 40, count 0 2006.161.08:04:31.28#ibcon#about to read 6, iclass 40, count 0 2006.161.08:04:31.28#ibcon#read 6, iclass 40, count 0 2006.161.08:04:31.28#ibcon#end of sib2, iclass 40, count 0 2006.161.08:04:31.28#ibcon#*after write, iclass 40, count 0 2006.161.08:04:31.28#ibcon#*before return 0, iclass 40, count 0 2006.161.08:04:31.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:04:31.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:04:31.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:04:31.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:04:31.28$vc4f8/valo=7,832.99 2006.161.08:04:31.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.08:04:31.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.08:04:31.28#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:31.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:04:31.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:04:31.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:04:31.28#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:04:31.28#ibcon#first serial, iclass 5, count 0 2006.161.08:04:31.28#ibcon#enter sib2, iclass 5, count 0 2006.161.08:04:31.28#ibcon#flushed, iclass 5, count 0 2006.161.08:04:31.28#ibcon#about to write, iclass 5, count 0 2006.161.08:04:31.28#ibcon#wrote, iclass 5, count 0 2006.161.08:04:31.28#ibcon#about to read 3, iclass 5, count 0 2006.161.08:04:31.30#ibcon#read 3, iclass 5, count 0 2006.161.08:04:31.30#ibcon#about to read 4, iclass 5, count 0 2006.161.08:04:31.30#ibcon#read 4, iclass 5, count 0 2006.161.08:04:31.30#ibcon#about to read 5, iclass 5, count 0 2006.161.08:04:31.30#ibcon#read 5, iclass 5, count 0 2006.161.08:04:31.30#ibcon#about to read 6, iclass 5, count 0 2006.161.08:04:31.30#ibcon#read 6, iclass 5, count 0 2006.161.08:04:31.30#ibcon#end of sib2, iclass 5, count 0 2006.161.08:04:31.30#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:04:31.30#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:04:31.30#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:04:31.30#ibcon#*before write, iclass 5, count 0 2006.161.08:04:31.30#ibcon#enter sib2, iclass 5, count 0 2006.161.08:04:31.30#ibcon#flushed, iclass 5, count 0 2006.161.08:04:31.30#ibcon#about to write, iclass 5, count 0 2006.161.08:04:31.30#ibcon#wrote, iclass 5, count 0 2006.161.08:04:31.30#ibcon#about to read 3, iclass 5, count 0 2006.161.08:04:31.34#ibcon#read 3, iclass 5, count 0 2006.161.08:04:31.34#ibcon#about to read 4, iclass 5, count 0 2006.161.08:04:31.34#ibcon#read 4, iclass 5, count 0 2006.161.08:04:31.34#ibcon#about to read 5, iclass 5, count 0 2006.161.08:04:31.34#ibcon#read 5, iclass 5, count 0 2006.161.08:04:31.34#ibcon#about to read 6, iclass 5, count 0 2006.161.08:04:31.34#ibcon#read 6, iclass 5, count 0 2006.161.08:04:31.34#ibcon#end of sib2, iclass 5, count 0 2006.161.08:04:31.34#ibcon#*after write, iclass 5, count 0 2006.161.08:04:31.34#ibcon#*before return 0, iclass 5, count 0 2006.161.08:04:31.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:04:31.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:04:31.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:04:31.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:04:31.34$vc4f8/va=7,6 2006.161.08:04:31.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.08:04:31.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.08:04:31.34#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:31.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:04:31.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:04:31.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:04:31.40#ibcon#enter wrdev, iclass 7, count 2 2006.161.08:04:31.40#ibcon#first serial, iclass 7, count 2 2006.161.08:04:31.40#ibcon#enter sib2, iclass 7, count 2 2006.161.08:04:31.40#ibcon#flushed, iclass 7, count 2 2006.161.08:04:31.40#ibcon#about to write, iclass 7, count 2 2006.161.08:04:31.40#ibcon#wrote, iclass 7, count 2 2006.161.08:04:31.40#ibcon#about to read 3, iclass 7, count 2 2006.161.08:04:31.42#ibcon#read 3, iclass 7, count 2 2006.161.08:04:31.42#ibcon#about to read 4, iclass 7, count 2 2006.161.08:04:31.42#ibcon#read 4, iclass 7, count 2 2006.161.08:04:31.42#ibcon#about to read 5, iclass 7, count 2 2006.161.08:04:31.42#ibcon#read 5, iclass 7, count 2 2006.161.08:04:31.42#ibcon#about to read 6, iclass 7, count 2 2006.161.08:04:31.42#ibcon#read 6, iclass 7, count 2 2006.161.08:04:31.42#ibcon#end of sib2, iclass 7, count 2 2006.161.08:04:31.42#ibcon#*mode == 0, iclass 7, count 2 2006.161.08:04:31.42#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.08:04:31.42#ibcon#[25=AT07-06\r\n] 2006.161.08:04:31.42#ibcon#*before write, iclass 7, count 2 2006.161.08:04:31.42#ibcon#enter sib2, iclass 7, count 2 2006.161.08:04:31.42#ibcon#flushed, iclass 7, count 2 2006.161.08:04:31.42#ibcon#about to write, iclass 7, count 2 2006.161.08:04:31.42#ibcon#wrote, iclass 7, count 2 2006.161.08:04:31.42#ibcon#about to read 3, iclass 7, count 2 2006.161.08:04:31.45#ibcon#read 3, iclass 7, count 2 2006.161.08:04:31.45#ibcon#about to read 4, iclass 7, count 2 2006.161.08:04:31.45#ibcon#read 4, iclass 7, count 2 2006.161.08:04:31.45#ibcon#about to read 5, iclass 7, count 2 2006.161.08:04:31.45#ibcon#read 5, iclass 7, count 2 2006.161.08:04:31.45#ibcon#about to read 6, iclass 7, count 2 2006.161.08:04:31.45#ibcon#read 6, iclass 7, count 2 2006.161.08:04:31.45#ibcon#end of sib2, iclass 7, count 2 2006.161.08:04:31.45#ibcon#*after write, iclass 7, count 2 2006.161.08:04:31.45#ibcon#*before return 0, iclass 7, count 2 2006.161.08:04:31.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:04:31.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:04:31.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.08:04:31.45#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:31.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:04:31.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:04:31.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:04:31.57#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:04:31.57#ibcon#first serial, iclass 7, count 0 2006.161.08:04:31.57#ibcon#enter sib2, iclass 7, count 0 2006.161.08:04:31.57#ibcon#flushed, iclass 7, count 0 2006.161.08:04:31.57#ibcon#about to write, iclass 7, count 0 2006.161.08:04:31.57#ibcon#wrote, iclass 7, count 0 2006.161.08:04:31.57#ibcon#about to read 3, iclass 7, count 0 2006.161.08:04:31.59#ibcon#read 3, iclass 7, count 0 2006.161.08:04:31.59#ibcon#about to read 4, iclass 7, count 0 2006.161.08:04:31.59#ibcon#read 4, iclass 7, count 0 2006.161.08:04:31.59#ibcon#about to read 5, iclass 7, count 0 2006.161.08:04:31.59#ibcon#read 5, iclass 7, count 0 2006.161.08:04:31.59#ibcon#about to read 6, iclass 7, count 0 2006.161.08:04:31.59#ibcon#read 6, iclass 7, count 0 2006.161.08:04:31.59#ibcon#end of sib2, iclass 7, count 0 2006.161.08:04:31.59#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:04:31.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:04:31.59#ibcon#[25=USB\r\n] 2006.161.08:04:31.59#ibcon#*before write, iclass 7, count 0 2006.161.08:04:31.59#ibcon#enter sib2, iclass 7, count 0 2006.161.08:04:31.59#ibcon#flushed, iclass 7, count 0 2006.161.08:04:31.59#ibcon#about to write, iclass 7, count 0 2006.161.08:04:31.59#ibcon#wrote, iclass 7, count 0 2006.161.08:04:31.59#ibcon#about to read 3, iclass 7, count 0 2006.161.08:04:31.62#ibcon#read 3, iclass 7, count 0 2006.161.08:04:31.62#ibcon#about to read 4, iclass 7, count 0 2006.161.08:04:31.62#ibcon#read 4, iclass 7, count 0 2006.161.08:04:31.62#ibcon#about to read 5, iclass 7, count 0 2006.161.08:04:31.62#ibcon#read 5, iclass 7, count 0 2006.161.08:04:31.62#ibcon#about to read 6, iclass 7, count 0 2006.161.08:04:31.62#ibcon#read 6, iclass 7, count 0 2006.161.08:04:31.62#ibcon#end of sib2, iclass 7, count 0 2006.161.08:04:31.62#ibcon#*after write, iclass 7, count 0 2006.161.08:04:31.62#ibcon#*before return 0, iclass 7, count 0 2006.161.08:04:31.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:04:31.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:04:31.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:04:31.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:04:31.62$vc4f8/valo=8,852.99 2006.161.08:04:31.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.08:04:31.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.08:04:31.62#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:31.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:04:31.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:04:31.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:04:31.62#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:04:31.62#ibcon#first serial, iclass 11, count 0 2006.161.08:04:31.62#ibcon#enter sib2, iclass 11, count 0 2006.161.08:04:31.62#ibcon#flushed, iclass 11, count 0 2006.161.08:04:31.62#ibcon#about to write, iclass 11, count 0 2006.161.08:04:31.62#ibcon#wrote, iclass 11, count 0 2006.161.08:04:31.62#ibcon#about to read 3, iclass 11, count 0 2006.161.08:04:31.64#ibcon#read 3, iclass 11, count 0 2006.161.08:04:31.64#ibcon#about to read 4, iclass 11, count 0 2006.161.08:04:31.64#ibcon#read 4, iclass 11, count 0 2006.161.08:04:31.64#ibcon#about to read 5, iclass 11, count 0 2006.161.08:04:31.64#ibcon#read 5, iclass 11, count 0 2006.161.08:04:31.64#ibcon#about to read 6, iclass 11, count 0 2006.161.08:04:31.64#ibcon#read 6, iclass 11, count 0 2006.161.08:04:31.64#ibcon#end of sib2, iclass 11, count 0 2006.161.08:04:31.64#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:04:31.64#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:04:31.64#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:04:31.64#ibcon#*before write, iclass 11, count 0 2006.161.08:04:31.64#ibcon#enter sib2, iclass 11, count 0 2006.161.08:04:31.64#ibcon#flushed, iclass 11, count 0 2006.161.08:04:31.64#ibcon#about to write, iclass 11, count 0 2006.161.08:04:31.64#ibcon#wrote, iclass 11, count 0 2006.161.08:04:31.64#ibcon#about to read 3, iclass 11, count 0 2006.161.08:04:31.68#ibcon#read 3, iclass 11, count 0 2006.161.08:04:31.68#ibcon#about to read 4, iclass 11, count 0 2006.161.08:04:31.68#ibcon#read 4, iclass 11, count 0 2006.161.08:04:31.68#ibcon#about to read 5, iclass 11, count 0 2006.161.08:04:31.68#ibcon#read 5, iclass 11, count 0 2006.161.08:04:31.68#ibcon#about to read 6, iclass 11, count 0 2006.161.08:04:31.68#ibcon#read 6, iclass 11, count 0 2006.161.08:04:31.68#ibcon#end of sib2, iclass 11, count 0 2006.161.08:04:31.68#ibcon#*after write, iclass 11, count 0 2006.161.08:04:31.68#ibcon#*before return 0, iclass 11, count 0 2006.161.08:04:31.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:04:31.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:04:31.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:04:31.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:04:31.68$vc4f8/va=8,7 2006.161.08:04:31.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.08:04:31.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.08:04:31.68#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:31.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:04:31.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:04:31.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:04:31.74#ibcon#enter wrdev, iclass 13, count 2 2006.161.08:04:31.74#ibcon#first serial, iclass 13, count 2 2006.161.08:04:31.74#ibcon#enter sib2, iclass 13, count 2 2006.161.08:04:31.74#ibcon#flushed, iclass 13, count 2 2006.161.08:04:31.74#ibcon#about to write, iclass 13, count 2 2006.161.08:04:31.74#ibcon#wrote, iclass 13, count 2 2006.161.08:04:31.74#ibcon#about to read 3, iclass 13, count 2 2006.161.08:04:31.76#ibcon#read 3, iclass 13, count 2 2006.161.08:04:31.76#ibcon#about to read 4, iclass 13, count 2 2006.161.08:04:31.76#ibcon#read 4, iclass 13, count 2 2006.161.08:04:31.76#ibcon#about to read 5, iclass 13, count 2 2006.161.08:04:31.76#ibcon#read 5, iclass 13, count 2 2006.161.08:04:31.76#ibcon#about to read 6, iclass 13, count 2 2006.161.08:04:31.76#ibcon#read 6, iclass 13, count 2 2006.161.08:04:31.76#ibcon#end of sib2, iclass 13, count 2 2006.161.08:04:31.76#ibcon#*mode == 0, iclass 13, count 2 2006.161.08:04:31.76#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.08:04:31.76#ibcon#[25=AT08-07\r\n] 2006.161.08:04:31.76#ibcon#*before write, iclass 13, count 2 2006.161.08:04:31.76#ibcon#enter sib2, iclass 13, count 2 2006.161.08:04:31.76#ibcon#flushed, iclass 13, count 2 2006.161.08:04:31.76#ibcon#about to write, iclass 13, count 2 2006.161.08:04:31.76#ibcon#wrote, iclass 13, count 2 2006.161.08:04:31.76#ibcon#about to read 3, iclass 13, count 2 2006.161.08:04:31.79#ibcon#read 3, iclass 13, count 2 2006.161.08:04:31.79#ibcon#about to read 4, iclass 13, count 2 2006.161.08:04:31.79#ibcon#read 4, iclass 13, count 2 2006.161.08:04:31.79#ibcon#about to read 5, iclass 13, count 2 2006.161.08:04:31.79#ibcon#read 5, iclass 13, count 2 2006.161.08:04:31.79#ibcon#about to read 6, iclass 13, count 2 2006.161.08:04:31.79#ibcon#read 6, iclass 13, count 2 2006.161.08:04:31.79#ibcon#end of sib2, iclass 13, count 2 2006.161.08:04:31.79#ibcon#*after write, iclass 13, count 2 2006.161.08:04:31.79#ibcon#*before return 0, iclass 13, count 2 2006.161.08:04:31.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:04:31.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:04:31.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.08:04:31.79#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:31.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:04:31.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:04:31.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:04:31.91#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:04:31.91#ibcon#first serial, iclass 13, count 0 2006.161.08:04:31.91#ibcon#enter sib2, iclass 13, count 0 2006.161.08:04:31.91#ibcon#flushed, iclass 13, count 0 2006.161.08:04:31.91#ibcon#about to write, iclass 13, count 0 2006.161.08:04:31.91#ibcon#wrote, iclass 13, count 0 2006.161.08:04:31.91#ibcon#about to read 3, iclass 13, count 0 2006.161.08:04:31.93#ibcon#read 3, iclass 13, count 0 2006.161.08:04:31.93#ibcon#about to read 4, iclass 13, count 0 2006.161.08:04:31.93#ibcon#read 4, iclass 13, count 0 2006.161.08:04:31.93#ibcon#about to read 5, iclass 13, count 0 2006.161.08:04:31.93#ibcon#read 5, iclass 13, count 0 2006.161.08:04:31.93#ibcon#about to read 6, iclass 13, count 0 2006.161.08:04:31.93#ibcon#read 6, iclass 13, count 0 2006.161.08:04:31.93#ibcon#end of sib2, iclass 13, count 0 2006.161.08:04:31.93#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:04:31.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:04:31.93#ibcon#[25=USB\r\n] 2006.161.08:04:31.93#ibcon#*before write, iclass 13, count 0 2006.161.08:04:31.93#ibcon#enter sib2, iclass 13, count 0 2006.161.08:04:31.93#ibcon#flushed, iclass 13, count 0 2006.161.08:04:31.93#ibcon#about to write, iclass 13, count 0 2006.161.08:04:31.93#ibcon#wrote, iclass 13, count 0 2006.161.08:04:31.93#ibcon#about to read 3, iclass 13, count 0 2006.161.08:04:31.96#ibcon#read 3, iclass 13, count 0 2006.161.08:04:31.96#ibcon#about to read 4, iclass 13, count 0 2006.161.08:04:31.96#ibcon#read 4, iclass 13, count 0 2006.161.08:04:31.96#ibcon#about to read 5, iclass 13, count 0 2006.161.08:04:31.96#ibcon#read 5, iclass 13, count 0 2006.161.08:04:31.96#ibcon#about to read 6, iclass 13, count 0 2006.161.08:04:31.96#ibcon#read 6, iclass 13, count 0 2006.161.08:04:31.96#ibcon#end of sib2, iclass 13, count 0 2006.161.08:04:31.96#ibcon#*after write, iclass 13, count 0 2006.161.08:04:31.96#ibcon#*before return 0, iclass 13, count 0 2006.161.08:04:31.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:04:31.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:04:31.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:04:31.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:04:31.96$vc4f8/vblo=1,632.99 2006.161.08:04:31.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.08:04:31.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.08:04:31.96#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:31.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:31.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:31.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:31.96#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:04:31.96#ibcon#first serial, iclass 15, count 0 2006.161.08:04:31.96#ibcon#enter sib2, iclass 15, count 0 2006.161.08:04:31.96#ibcon#flushed, iclass 15, count 0 2006.161.08:04:31.96#ibcon#about to write, iclass 15, count 0 2006.161.08:04:31.96#ibcon#wrote, iclass 15, count 0 2006.161.08:04:31.96#ibcon#about to read 3, iclass 15, count 0 2006.161.08:04:31.98#ibcon#read 3, iclass 15, count 0 2006.161.08:04:31.98#ibcon#about to read 4, iclass 15, count 0 2006.161.08:04:31.98#ibcon#read 4, iclass 15, count 0 2006.161.08:04:31.98#ibcon#about to read 5, iclass 15, count 0 2006.161.08:04:31.98#ibcon#read 5, iclass 15, count 0 2006.161.08:04:31.98#ibcon#about to read 6, iclass 15, count 0 2006.161.08:04:31.98#ibcon#read 6, iclass 15, count 0 2006.161.08:04:31.98#ibcon#end of sib2, iclass 15, count 0 2006.161.08:04:31.98#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:04:31.98#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:04:31.98#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:04:31.98#ibcon#*before write, iclass 15, count 0 2006.161.08:04:31.98#ibcon#enter sib2, iclass 15, count 0 2006.161.08:04:31.98#ibcon#flushed, iclass 15, count 0 2006.161.08:04:31.98#ibcon#about to write, iclass 15, count 0 2006.161.08:04:31.98#ibcon#wrote, iclass 15, count 0 2006.161.08:04:31.98#ibcon#about to read 3, iclass 15, count 0 2006.161.08:04:32.02#ibcon#read 3, iclass 15, count 0 2006.161.08:04:32.02#ibcon#about to read 4, iclass 15, count 0 2006.161.08:04:32.02#ibcon#read 4, iclass 15, count 0 2006.161.08:04:32.02#ibcon#about to read 5, iclass 15, count 0 2006.161.08:04:32.02#ibcon#read 5, iclass 15, count 0 2006.161.08:04:32.02#ibcon#about to read 6, iclass 15, count 0 2006.161.08:04:32.02#ibcon#read 6, iclass 15, count 0 2006.161.08:04:32.02#ibcon#end of sib2, iclass 15, count 0 2006.161.08:04:32.02#ibcon#*after write, iclass 15, count 0 2006.161.08:04:32.02#ibcon#*before return 0, iclass 15, count 0 2006.161.08:04:32.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:32.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:04:32.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:04:32.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:04:32.02$vc4f8/vb=1,4 2006.161.08:04:32.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.08:04:32.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.08:04:32.02#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:32.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:32.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:32.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:32.02#ibcon#enter wrdev, iclass 17, count 2 2006.161.08:04:32.02#ibcon#first serial, iclass 17, count 2 2006.161.08:04:32.02#ibcon#enter sib2, iclass 17, count 2 2006.161.08:04:32.02#ibcon#flushed, iclass 17, count 2 2006.161.08:04:32.02#ibcon#about to write, iclass 17, count 2 2006.161.08:04:32.02#ibcon#wrote, iclass 17, count 2 2006.161.08:04:32.02#ibcon#about to read 3, iclass 17, count 2 2006.161.08:04:32.04#ibcon#read 3, iclass 17, count 2 2006.161.08:04:32.04#ibcon#about to read 4, iclass 17, count 2 2006.161.08:04:32.04#ibcon#read 4, iclass 17, count 2 2006.161.08:04:32.04#ibcon#about to read 5, iclass 17, count 2 2006.161.08:04:32.04#ibcon#read 5, iclass 17, count 2 2006.161.08:04:32.04#ibcon#about to read 6, iclass 17, count 2 2006.161.08:04:32.04#ibcon#read 6, iclass 17, count 2 2006.161.08:04:32.04#ibcon#end of sib2, iclass 17, count 2 2006.161.08:04:32.04#ibcon#*mode == 0, iclass 17, count 2 2006.161.08:04:32.04#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.08:04:32.04#ibcon#[27=AT01-04\r\n] 2006.161.08:04:32.04#ibcon#*before write, iclass 17, count 2 2006.161.08:04:32.04#ibcon#enter sib2, iclass 17, count 2 2006.161.08:04:32.04#ibcon#flushed, iclass 17, count 2 2006.161.08:04:32.04#ibcon#about to write, iclass 17, count 2 2006.161.08:04:32.04#ibcon#wrote, iclass 17, count 2 2006.161.08:04:32.04#ibcon#about to read 3, iclass 17, count 2 2006.161.08:04:32.07#ibcon#read 3, iclass 17, count 2 2006.161.08:04:32.07#ibcon#about to read 4, iclass 17, count 2 2006.161.08:04:32.07#ibcon#read 4, iclass 17, count 2 2006.161.08:04:32.07#ibcon#about to read 5, iclass 17, count 2 2006.161.08:04:32.07#ibcon#read 5, iclass 17, count 2 2006.161.08:04:32.07#ibcon#about to read 6, iclass 17, count 2 2006.161.08:04:32.07#ibcon#read 6, iclass 17, count 2 2006.161.08:04:32.07#ibcon#end of sib2, iclass 17, count 2 2006.161.08:04:32.07#ibcon#*after write, iclass 17, count 2 2006.161.08:04:32.07#ibcon#*before return 0, iclass 17, count 2 2006.161.08:04:32.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:32.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:04:32.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.08:04:32.07#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:32.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:32.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:32.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:32.19#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:04:32.19#ibcon#first serial, iclass 17, count 0 2006.161.08:04:32.19#ibcon#enter sib2, iclass 17, count 0 2006.161.08:04:32.19#ibcon#flushed, iclass 17, count 0 2006.161.08:04:32.19#ibcon#about to write, iclass 17, count 0 2006.161.08:04:32.19#ibcon#wrote, iclass 17, count 0 2006.161.08:04:32.19#ibcon#about to read 3, iclass 17, count 0 2006.161.08:04:32.21#ibcon#read 3, iclass 17, count 0 2006.161.08:04:32.21#ibcon#about to read 4, iclass 17, count 0 2006.161.08:04:32.21#ibcon#read 4, iclass 17, count 0 2006.161.08:04:32.21#ibcon#about to read 5, iclass 17, count 0 2006.161.08:04:32.21#ibcon#read 5, iclass 17, count 0 2006.161.08:04:32.21#ibcon#about to read 6, iclass 17, count 0 2006.161.08:04:32.21#ibcon#read 6, iclass 17, count 0 2006.161.08:04:32.21#ibcon#end of sib2, iclass 17, count 0 2006.161.08:04:32.21#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:04:32.21#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:04:32.21#ibcon#[27=USB\r\n] 2006.161.08:04:32.21#ibcon#*before write, iclass 17, count 0 2006.161.08:04:32.21#ibcon#enter sib2, iclass 17, count 0 2006.161.08:04:32.21#ibcon#flushed, iclass 17, count 0 2006.161.08:04:32.21#ibcon#about to write, iclass 17, count 0 2006.161.08:04:32.21#ibcon#wrote, iclass 17, count 0 2006.161.08:04:32.21#ibcon#about to read 3, iclass 17, count 0 2006.161.08:04:32.24#ibcon#read 3, iclass 17, count 0 2006.161.08:04:32.24#ibcon#about to read 4, iclass 17, count 0 2006.161.08:04:32.24#ibcon#read 4, iclass 17, count 0 2006.161.08:04:32.24#ibcon#about to read 5, iclass 17, count 0 2006.161.08:04:32.24#ibcon#read 5, iclass 17, count 0 2006.161.08:04:32.24#ibcon#about to read 6, iclass 17, count 0 2006.161.08:04:32.24#ibcon#read 6, iclass 17, count 0 2006.161.08:04:32.24#ibcon#end of sib2, iclass 17, count 0 2006.161.08:04:32.24#ibcon#*after write, iclass 17, count 0 2006.161.08:04:32.24#ibcon#*before return 0, iclass 17, count 0 2006.161.08:04:32.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:32.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:04:32.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:04:32.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:04:32.24$vc4f8/vblo=2,640.99 2006.161.08:04:32.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:04:32.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:04:32.24#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:32.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:32.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:32.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:32.24#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:04:32.24#ibcon#first serial, iclass 19, count 0 2006.161.08:04:32.24#ibcon#enter sib2, iclass 19, count 0 2006.161.08:04:32.24#ibcon#flushed, iclass 19, count 0 2006.161.08:04:32.24#ibcon#about to write, iclass 19, count 0 2006.161.08:04:32.24#ibcon#wrote, iclass 19, count 0 2006.161.08:04:32.24#ibcon#about to read 3, iclass 19, count 0 2006.161.08:04:32.26#ibcon#read 3, iclass 19, count 0 2006.161.08:04:32.26#ibcon#about to read 4, iclass 19, count 0 2006.161.08:04:32.26#ibcon#read 4, iclass 19, count 0 2006.161.08:04:32.26#ibcon#about to read 5, iclass 19, count 0 2006.161.08:04:32.26#ibcon#read 5, iclass 19, count 0 2006.161.08:04:32.26#ibcon#about to read 6, iclass 19, count 0 2006.161.08:04:32.26#ibcon#read 6, iclass 19, count 0 2006.161.08:04:32.26#ibcon#end of sib2, iclass 19, count 0 2006.161.08:04:32.26#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:04:32.26#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:04:32.26#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:04:32.26#ibcon#*before write, iclass 19, count 0 2006.161.08:04:32.26#ibcon#enter sib2, iclass 19, count 0 2006.161.08:04:32.26#ibcon#flushed, iclass 19, count 0 2006.161.08:04:32.26#ibcon#about to write, iclass 19, count 0 2006.161.08:04:32.26#ibcon#wrote, iclass 19, count 0 2006.161.08:04:32.26#ibcon#about to read 3, iclass 19, count 0 2006.161.08:04:32.30#ibcon#read 3, iclass 19, count 0 2006.161.08:04:32.30#ibcon#about to read 4, iclass 19, count 0 2006.161.08:04:32.30#ibcon#read 4, iclass 19, count 0 2006.161.08:04:32.30#ibcon#about to read 5, iclass 19, count 0 2006.161.08:04:32.30#ibcon#read 5, iclass 19, count 0 2006.161.08:04:32.30#ibcon#about to read 6, iclass 19, count 0 2006.161.08:04:32.30#ibcon#read 6, iclass 19, count 0 2006.161.08:04:32.30#ibcon#end of sib2, iclass 19, count 0 2006.161.08:04:32.30#ibcon#*after write, iclass 19, count 0 2006.161.08:04:32.30#ibcon#*before return 0, iclass 19, count 0 2006.161.08:04:32.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:32.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:04:32.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:04:32.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:04:32.30$vc4f8/vb=2,4 2006.161.08:04:32.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:04:32.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:04:32.30#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:32.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:32.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:32.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:32.36#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:04:32.36#ibcon#first serial, iclass 21, count 2 2006.161.08:04:32.36#ibcon#enter sib2, iclass 21, count 2 2006.161.08:04:32.36#ibcon#flushed, iclass 21, count 2 2006.161.08:04:32.36#ibcon#about to write, iclass 21, count 2 2006.161.08:04:32.36#ibcon#wrote, iclass 21, count 2 2006.161.08:04:32.36#ibcon#about to read 3, iclass 21, count 2 2006.161.08:04:32.38#ibcon#read 3, iclass 21, count 2 2006.161.08:04:32.38#ibcon#about to read 4, iclass 21, count 2 2006.161.08:04:32.38#ibcon#read 4, iclass 21, count 2 2006.161.08:04:32.38#ibcon#about to read 5, iclass 21, count 2 2006.161.08:04:32.38#ibcon#read 5, iclass 21, count 2 2006.161.08:04:32.38#ibcon#about to read 6, iclass 21, count 2 2006.161.08:04:32.38#ibcon#read 6, iclass 21, count 2 2006.161.08:04:32.38#ibcon#end of sib2, iclass 21, count 2 2006.161.08:04:32.38#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:04:32.38#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:04:32.38#ibcon#[27=AT02-04\r\n] 2006.161.08:04:32.38#ibcon#*before write, iclass 21, count 2 2006.161.08:04:32.38#ibcon#enter sib2, iclass 21, count 2 2006.161.08:04:32.38#ibcon#flushed, iclass 21, count 2 2006.161.08:04:32.38#ibcon#about to write, iclass 21, count 2 2006.161.08:04:32.38#ibcon#wrote, iclass 21, count 2 2006.161.08:04:32.38#ibcon#about to read 3, iclass 21, count 2 2006.161.08:04:32.41#ibcon#read 3, iclass 21, count 2 2006.161.08:04:32.41#ibcon#about to read 4, iclass 21, count 2 2006.161.08:04:32.41#ibcon#read 4, iclass 21, count 2 2006.161.08:04:32.41#ibcon#about to read 5, iclass 21, count 2 2006.161.08:04:32.41#ibcon#read 5, iclass 21, count 2 2006.161.08:04:32.41#ibcon#about to read 6, iclass 21, count 2 2006.161.08:04:32.41#ibcon#read 6, iclass 21, count 2 2006.161.08:04:32.41#ibcon#end of sib2, iclass 21, count 2 2006.161.08:04:32.41#ibcon#*after write, iclass 21, count 2 2006.161.08:04:32.41#ibcon#*before return 0, iclass 21, count 2 2006.161.08:04:32.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:32.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:04:32.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:04:32.41#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:32.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:32.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:32.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:32.53#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:04:32.53#ibcon#first serial, iclass 21, count 0 2006.161.08:04:32.53#ibcon#enter sib2, iclass 21, count 0 2006.161.08:04:32.53#ibcon#flushed, iclass 21, count 0 2006.161.08:04:32.53#ibcon#about to write, iclass 21, count 0 2006.161.08:04:32.53#ibcon#wrote, iclass 21, count 0 2006.161.08:04:32.53#ibcon#about to read 3, iclass 21, count 0 2006.161.08:04:32.55#ibcon#read 3, iclass 21, count 0 2006.161.08:04:32.55#ibcon#about to read 4, iclass 21, count 0 2006.161.08:04:32.55#ibcon#read 4, iclass 21, count 0 2006.161.08:04:32.55#ibcon#about to read 5, iclass 21, count 0 2006.161.08:04:32.55#ibcon#read 5, iclass 21, count 0 2006.161.08:04:32.55#ibcon#about to read 6, iclass 21, count 0 2006.161.08:04:32.55#ibcon#read 6, iclass 21, count 0 2006.161.08:04:32.55#ibcon#end of sib2, iclass 21, count 0 2006.161.08:04:32.55#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:04:32.55#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:04:32.55#ibcon#[27=USB\r\n] 2006.161.08:04:32.55#ibcon#*before write, iclass 21, count 0 2006.161.08:04:32.55#ibcon#enter sib2, iclass 21, count 0 2006.161.08:04:32.55#ibcon#flushed, iclass 21, count 0 2006.161.08:04:32.55#ibcon#about to write, iclass 21, count 0 2006.161.08:04:32.55#ibcon#wrote, iclass 21, count 0 2006.161.08:04:32.55#ibcon#about to read 3, iclass 21, count 0 2006.161.08:04:32.58#ibcon#read 3, iclass 21, count 0 2006.161.08:04:32.58#ibcon#about to read 4, iclass 21, count 0 2006.161.08:04:32.58#ibcon#read 4, iclass 21, count 0 2006.161.08:04:32.58#ibcon#about to read 5, iclass 21, count 0 2006.161.08:04:32.58#ibcon#read 5, iclass 21, count 0 2006.161.08:04:32.58#ibcon#about to read 6, iclass 21, count 0 2006.161.08:04:32.58#ibcon#read 6, iclass 21, count 0 2006.161.08:04:32.58#ibcon#end of sib2, iclass 21, count 0 2006.161.08:04:32.58#ibcon#*after write, iclass 21, count 0 2006.161.08:04:32.58#ibcon#*before return 0, iclass 21, count 0 2006.161.08:04:32.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:32.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:04:32.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:04:32.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:04:32.58$vc4f8/vblo=3,656.99 2006.161.08:04:32.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:04:32.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:04:32.58#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:32.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:32.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:32.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:32.58#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:04:32.58#ibcon#first serial, iclass 23, count 0 2006.161.08:04:32.58#ibcon#enter sib2, iclass 23, count 0 2006.161.08:04:32.58#ibcon#flushed, iclass 23, count 0 2006.161.08:04:32.58#ibcon#about to write, iclass 23, count 0 2006.161.08:04:32.58#ibcon#wrote, iclass 23, count 0 2006.161.08:04:32.58#ibcon#about to read 3, iclass 23, count 0 2006.161.08:04:32.60#ibcon#read 3, iclass 23, count 0 2006.161.08:04:32.60#ibcon#about to read 4, iclass 23, count 0 2006.161.08:04:32.60#ibcon#read 4, iclass 23, count 0 2006.161.08:04:32.60#ibcon#about to read 5, iclass 23, count 0 2006.161.08:04:32.60#ibcon#read 5, iclass 23, count 0 2006.161.08:04:32.60#ibcon#about to read 6, iclass 23, count 0 2006.161.08:04:32.60#ibcon#read 6, iclass 23, count 0 2006.161.08:04:32.60#ibcon#end of sib2, iclass 23, count 0 2006.161.08:04:32.60#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:04:32.60#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:04:32.60#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:04:32.60#ibcon#*before write, iclass 23, count 0 2006.161.08:04:32.60#ibcon#enter sib2, iclass 23, count 0 2006.161.08:04:32.60#ibcon#flushed, iclass 23, count 0 2006.161.08:04:32.60#ibcon#about to write, iclass 23, count 0 2006.161.08:04:32.60#ibcon#wrote, iclass 23, count 0 2006.161.08:04:32.60#ibcon#about to read 3, iclass 23, count 0 2006.161.08:04:32.64#ibcon#read 3, iclass 23, count 0 2006.161.08:04:32.64#ibcon#about to read 4, iclass 23, count 0 2006.161.08:04:32.64#ibcon#read 4, iclass 23, count 0 2006.161.08:04:32.64#ibcon#about to read 5, iclass 23, count 0 2006.161.08:04:32.64#ibcon#read 5, iclass 23, count 0 2006.161.08:04:32.64#ibcon#about to read 6, iclass 23, count 0 2006.161.08:04:32.64#ibcon#read 6, iclass 23, count 0 2006.161.08:04:32.64#ibcon#end of sib2, iclass 23, count 0 2006.161.08:04:32.64#ibcon#*after write, iclass 23, count 0 2006.161.08:04:32.64#ibcon#*before return 0, iclass 23, count 0 2006.161.08:04:32.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:32.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:04:32.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:04:32.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:04:32.64$vc4f8/vb=3,4 2006.161.08:04:32.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.08:04:32.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.08:04:32.64#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:32.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:32.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:32.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:32.70#ibcon#enter wrdev, iclass 25, count 2 2006.161.08:04:32.70#ibcon#first serial, iclass 25, count 2 2006.161.08:04:32.70#ibcon#enter sib2, iclass 25, count 2 2006.161.08:04:32.70#ibcon#flushed, iclass 25, count 2 2006.161.08:04:32.70#ibcon#about to write, iclass 25, count 2 2006.161.08:04:32.70#ibcon#wrote, iclass 25, count 2 2006.161.08:04:32.70#ibcon#about to read 3, iclass 25, count 2 2006.161.08:04:32.72#ibcon#read 3, iclass 25, count 2 2006.161.08:04:32.72#ibcon#about to read 4, iclass 25, count 2 2006.161.08:04:32.72#ibcon#read 4, iclass 25, count 2 2006.161.08:04:32.72#ibcon#about to read 5, iclass 25, count 2 2006.161.08:04:32.72#ibcon#read 5, iclass 25, count 2 2006.161.08:04:32.72#ibcon#about to read 6, iclass 25, count 2 2006.161.08:04:32.72#ibcon#read 6, iclass 25, count 2 2006.161.08:04:32.72#ibcon#end of sib2, iclass 25, count 2 2006.161.08:04:32.72#ibcon#*mode == 0, iclass 25, count 2 2006.161.08:04:32.72#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.08:04:32.72#ibcon#[27=AT03-04\r\n] 2006.161.08:04:32.72#ibcon#*before write, iclass 25, count 2 2006.161.08:04:32.72#ibcon#enter sib2, iclass 25, count 2 2006.161.08:04:32.72#ibcon#flushed, iclass 25, count 2 2006.161.08:04:32.72#ibcon#about to write, iclass 25, count 2 2006.161.08:04:32.72#ibcon#wrote, iclass 25, count 2 2006.161.08:04:32.72#ibcon#about to read 3, iclass 25, count 2 2006.161.08:04:32.75#ibcon#read 3, iclass 25, count 2 2006.161.08:04:32.75#ibcon#about to read 4, iclass 25, count 2 2006.161.08:04:32.75#ibcon#read 4, iclass 25, count 2 2006.161.08:04:32.75#ibcon#about to read 5, iclass 25, count 2 2006.161.08:04:32.75#ibcon#read 5, iclass 25, count 2 2006.161.08:04:32.75#ibcon#about to read 6, iclass 25, count 2 2006.161.08:04:32.75#ibcon#read 6, iclass 25, count 2 2006.161.08:04:32.75#ibcon#end of sib2, iclass 25, count 2 2006.161.08:04:32.75#ibcon#*after write, iclass 25, count 2 2006.161.08:04:32.75#ibcon#*before return 0, iclass 25, count 2 2006.161.08:04:32.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:32.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:04:32.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.08:04:32.75#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:32.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:32.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:32.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:32.87#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:04:32.87#ibcon#first serial, iclass 25, count 0 2006.161.08:04:32.87#ibcon#enter sib2, iclass 25, count 0 2006.161.08:04:32.87#ibcon#flushed, iclass 25, count 0 2006.161.08:04:32.87#ibcon#about to write, iclass 25, count 0 2006.161.08:04:32.87#ibcon#wrote, iclass 25, count 0 2006.161.08:04:32.87#ibcon#about to read 3, iclass 25, count 0 2006.161.08:04:32.89#ibcon#read 3, iclass 25, count 0 2006.161.08:04:32.89#ibcon#about to read 4, iclass 25, count 0 2006.161.08:04:32.89#ibcon#read 4, iclass 25, count 0 2006.161.08:04:32.89#ibcon#about to read 5, iclass 25, count 0 2006.161.08:04:32.89#ibcon#read 5, iclass 25, count 0 2006.161.08:04:32.89#ibcon#about to read 6, iclass 25, count 0 2006.161.08:04:32.89#ibcon#read 6, iclass 25, count 0 2006.161.08:04:32.89#ibcon#end of sib2, iclass 25, count 0 2006.161.08:04:32.89#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:04:32.89#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:04:32.89#ibcon#[27=USB\r\n] 2006.161.08:04:32.89#ibcon#*before write, iclass 25, count 0 2006.161.08:04:32.89#ibcon#enter sib2, iclass 25, count 0 2006.161.08:04:32.89#ibcon#flushed, iclass 25, count 0 2006.161.08:04:32.89#ibcon#about to write, iclass 25, count 0 2006.161.08:04:32.89#ibcon#wrote, iclass 25, count 0 2006.161.08:04:32.89#ibcon#about to read 3, iclass 25, count 0 2006.161.08:04:32.92#ibcon#read 3, iclass 25, count 0 2006.161.08:04:32.92#ibcon#about to read 4, iclass 25, count 0 2006.161.08:04:32.92#ibcon#read 4, iclass 25, count 0 2006.161.08:04:32.92#ibcon#about to read 5, iclass 25, count 0 2006.161.08:04:32.92#ibcon#read 5, iclass 25, count 0 2006.161.08:04:32.92#ibcon#about to read 6, iclass 25, count 0 2006.161.08:04:32.92#ibcon#read 6, iclass 25, count 0 2006.161.08:04:32.92#ibcon#end of sib2, iclass 25, count 0 2006.161.08:04:32.92#ibcon#*after write, iclass 25, count 0 2006.161.08:04:32.92#ibcon#*before return 0, iclass 25, count 0 2006.161.08:04:32.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:32.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:04:32.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:04:32.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:04:32.92$vc4f8/vblo=4,712.99 2006.161.08:04:32.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.08:04:32.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.08:04:32.92#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:32.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:32.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:32.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:32.92#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:04:32.92#ibcon#first serial, iclass 27, count 0 2006.161.08:04:32.92#ibcon#enter sib2, iclass 27, count 0 2006.161.08:04:32.92#ibcon#flushed, iclass 27, count 0 2006.161.08:04:32.92#ibcon#about to write, iclass 27, count 0 2006.161.08:04:32.92#ibcon#wrote, iclass 27, count 0 2006.161.08:04:32.92#ibcon#about to read 3, iclass 27, count 0 2006.161.08:04:32.94#ibcon#read 3, iclass 27, count 0 2006.161.08:04:32.94#ibcon#about to read 4, iclass 27, count 0 2006.161.08:04:32.94#ibcon#read 4, iclass 27, count 0 2006.161.08:04:32.94#ibcon#about to read 5, iclass 27, count 0 2006.161.08:04:32.94#ibcon#read 5, iclass 27, count 0 2006.161.08:04:32.94#ibcon#about to read 6, iclass 27, count 0 2006.161.08:04:32.94#ibcon#read 6, iclass 27, count 0 2006.161.08:04:32.94#ibcon#end of sib2, iclass 27, count 0 2006.161.08:04:32.94#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:04:32.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:04:32.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:04:32.94#ibcon#*before write, iclass 27, count 0 2006.161.08:04:32.94#ibcon#enter sib2, iclass 27, count 0 2006.161.08:04:32.94#ibcon#flushed, iclass 27, count 0 2006.161.08:04:32.94#ibcon#about to write, iclass 27, count 0 2006.161.08:04:32.94#ibcon#wrote, iclass 27, count 0 2006.161.08:04:32.94#ibcon#about to read 3, iclass 27, count 0 2006.161.08:04:32.98#ibcon#read 3, iclass 27, count 0 2006.161.08:04:32.98#ibcon#about to read 4, iclass 27, count 0 2006.161.08:04:32.98#ibcon#read 4, iclass 27, count 0 2006.161.08:04:32.98#ibcon#about to read 5, iclass 27, count 0 2006.161.08:04:32.98#ibcon#read 5, iclass 27, count 0 2006.161.08:04:32.98#ibcon#about to read 6, iclass 27, count 0 2006.161.08:04:32.98#ibcon#read 6, iclass 27, count 0 2006.161.08:04:32.98#ibcon#end of sib2, iclass 27, count 0 2006.161.08:04:32.98#ibcon#*after write, iclass 27, count 0 2006.161.08:04:32.98#ibcon#*before return 0, iclass 27, count 0 2006.161.08:04:32.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:32.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:04:32.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:04:32.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:04:32.98$vc4f8/vb=4,4 2006.161.08:04:32.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.08:04:32.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.08:04:32.98#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:32.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:33.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:33.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:33.04#ibcon#enter wrdev, iclass 29, count 2 2006.161.08:04:33.04#ibcon#first serial, iclass 29, count 2 2006.161.08:04:33.04#ibcon#enter sib2, iclass 29, count 2 2006.161.08:04:33.04#ibcon#flushed, iclass 29, count 2 2006.161.08:04:33.04#ibcon#about to write, iclass 29, count 2 2006.161.08:04:33.04#ibcon#wrote, iclass 29, count 2 2006.161.08:04:33.04#ibcon#about to read 3, iclass 29, count 2 2006.161.08:04:33.06#ibcon#read 3, iclass 29, count 2 2006.161.08:04:33.06#ibcon#about to read 4, iclass 29, count 2 2006.161.08:04:33.06#ibcon#read 4, iclass 29, count 2 2006.161.08:04:33.06#ibcon#about to read 5, iclass 29, count 2 2006.161.08:04:33.06#ibcon#read 5, iclass 29, count 2 2006.161.08:04:33.06#ibcon#about to read 6, iclass 29, count 2 2006.161.08:04:33.06#ibcon#read 6, iclass 29, count 2 2006.161.08:04:33.06#ibcon#end of sib2, iclass 29, count 2 2006.161.08:04:33.06#ibcon#*mode == 0, iclass 29, count 2 2006.161.08:04:33.06#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.08:04:33.06#ibcon#[27=AT04-04\r\n] 2006.161.08:04:33.06#ibcon#*before write, iclass 29, count 2 2006.161.08:04:33.06#ibcon#enter sib2, iclass 29, count 2 2006.161.08:04:33.06#ibcon#flushed, iclass 29, count 2 2006.161.08:04:33.06#ibcon#about to write, iclass 29, count 2 2006.161.08:04:33.06#ibcon#wrote, iclass 29, count 2 2006.161.08:04:33.06#ibcon#about to read 3, iclass 29, count 2 2006.161.08:04:33.09#ibcon#read 3, iclass 29, count 2 2006.161.08:04:33.09#ibcon#about to read 4, iclass 29, count 2 2006.161.08:04:33.09#ibcon#read 4, iclass 29, count 2 2006.161.08:04:33.09#ibcon#about to read 5, iclass 29, count 2 2006.161.08:04:33.09#ibcon#read 5, iclass 29, count 2 2006.161.08:04:33.09#ibcon#about to read 6, iclass 29, count 2 2006.161.08:04:33.09#ibcon#read 6, iclass 29, count 2 2006.161.08:04:33.09#ibcon#end of sib2, iclass 29, count 2 2006.161.08:04:33.09#ibcon#*after write, iclass 29, count 2 2006.161.08:04:33.09#ibcon#*before return 0, iclass 29, count 2 2006.161.08:04:33.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:33.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:04:33.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.08:04:33.09#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:33.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:33.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:33.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:33.21#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:04:33.21#ibcon#first serial, iclass 29, count 0 2006.161.08:04:33.21#ibcon#enter sib2, iclass 29, count 0 2006.161.08:04:33.21#ibcon#flushed, iclass 29, count 0 2006.161.08:04:33.21#ibcon#about to write, iclass 29, count 0 2006.161.08:04:33.21#ibcon#wrote, iclass 29, count 0 2006.161.08:04:33.21#ibcon#about to read 3, iclass 29, count 0 2006.161.08:04:33.23#ibcon#read 3, iclass 29, count 0 2006.161.08:04:33.23#ibcon#about to read 4, iclass 29, count 0 2006.161.08:04:33.23#ibcon#read 4, iclass 29, count 0 2006.161.08:04:33.23#ibcon#about to read 5, iclass 29, count 0 2006.161.08:04:33.23#ibcon#read 5, iclass 29, count 0 2006.161.08:04:33.23#ibcon#about to read 6, iclass 29, count 0 2006.161.08:04:33.23#ibcon#read 6, iclass 29, count 0 2006.161.08:04:33.23#ibcon#end of sib2, iclass 29, count 0 2006.161.08:04:33.23#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:04:33.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:04:33.23#ibcon#[27=USB\r\n] 2006.161.08:04:33.23#ibcon#*before write, iclass 29, count 0 2006.161.08:04:33.23#ibcon#enter sib2, iclass 29, count 0 2006.161.08:04:33.23#ibcon#flushed, iclass 29, count 0 2006.161.08:04:33.23#ibcon#about to write, iclass 29, count 0 2006.161.08:04:33.23#ibcon#wrote, iclass 29, count 0 2006.161.08:04:33.23#ibcon#about to read 3, iclass 29, count 0 2006.161.08:04:33.26#ibcon#read 3, iclass 29, count 0 2006.161.08:04:33.26#ibcon#about to read 4, iclass 29, count 0 2006.161.08:04:33.26#ibcon#read 4, iclass 29, count 0 2006.161.08:04:33.26#ibcon#about to read 5, iclass 29, count 0 2006.161.08:04:33.26#ibcon#read 5, iclass 29, count 0 2006.161.08:04:33.26#ibcon#about to read 6, iclass 29, count 0 2006.161.08:04:33.26#ibcon#read 6, iclass 29, count 0 2006.161.08:04:33.26#ibcon#end of sib2, iclass 29, count 0 2006.161.08:04:33.26#ibcon#*after write, iclass 29, count 0 2006.161.08:04:33.26#ibcon#*before return 0, iclass 29, count 0 2006.161.08:04:33.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:33.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:04:33.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:04:33.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:04:33.26$vc4f8/vblo=5,744.99 2006.161.08:04:33.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:04:33.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:04:33.26#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:33.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:33.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:33.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:33.26#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:04:33.26#ibcon#first serial, iclass 31, count 0 2006.161.08:04:33.26#ibcon#enter sib2, iclass 31, count 0 2006.161.08:04:33.26#ibcon#flushed, iclass 31, count 0 2006.161.08:04:33.26#ibcon#about to write, iclass 31, count 0 2006.161.08:04:33.26#ibcon#wrote, iclass 31, count 0 2006.161.08:04:33.26#ibcon#about to read 3, iclass 31, count 0 2006.161.08:04:33.28#ibcon#read 3, iclass 31, count 0 2006.161.08:04:33.28#ibcon#about to read 4, iclass 31, count 0 2006.161.08:04:33.28#ibcon#read 4, iclass 31, count 0 2006.161.08:04:33.28#ibcon#about to read 5, iclass 31, count 0 2006.161.08:04:33.28#ibcon#read 5, iclass 31, count 0 2006.161.08:04:33.28#ibcon#about to read 6, iclass 31, count 0 2006.161.08:04:33.28#ibcon#read 6, iclass 31, count 0 2006.161.08:04:33.28#ibcon#end of sib2, iclass 31, count 0 2006.161.08:04:33.28#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:04:33.28#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:04:33.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:04:33.28#ibcon#*before write, iclass 31, count 0 2006.161.08:04:33.28#ibcon#enter sib2, iclass 31, count 0 2006.161.08:04:33.28#ibcon#flushed, iclass 31, count 0 2006.161.08:04:33.28#ibcon#about to write, iclass 31, count 0 2006.161.08:04:33.28#ibcon#wrote, iclass 31, count 0 2006.161.08:04:33.28#ibcon#about to read 3, iclass 31, count 0 2006.161.08:04:33.32#ibcon#read 3, iclass 31, count 0 2006.161.08:04:33.32#ibcon#about to read 4, iclass 31, count 0 2006.161.08:04:33.32#ibcon#read 4, iclass 31, count 0 2006.161.08:04:33.32#ibcon#about to read 5, iclass 31, count 0 2006.161.08:04:33.32#ibcon#read 5, iclass 31, count 0 2006.161.08:04:33.32#ibcon#about to read 6, iclass 31, count 0 2006.161.08:04:33.32#ibcon#read 6, iclass 31, count 0 2006.161.08:04:33.32#ibcon#end of sib2, iclass 31, count 0 2006.161.08:04:33.32#ibcon#*after write, iclass 31, count 0 2006.161.08:04:33.32#ibcon#*before return 0, iclass 31, count 0 2006.161.08:04:33.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:33.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:04:33.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:04:33.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:04:33.32$vc4f8/vb=5,4 2006.161.08:04:33.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.08:04:33.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.08:04:33.32#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:33.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:33.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:33.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:33.38#ibcon#enter wrdev, iclass 33, count 2 2006.161.08:04:33.38#ibcon#first serial, iclass 33, count 2 2006.161.08:04:33.38#ibcon#enter sib2, iclass 33, count 2 2006.161.08:04:33.38#ibcon#flushed, iclass 33, count 2 2006.161.08:04:33.38#ibcon#about to write, iclass 33, count 2 2006.161.08:04:33.38#ibcon#wrote, iclass 33, count 2 2006.161.08:04:33.38#ibcon#about to read 3, iclass 33, count 2 2006.161.08:04:33.40#ibcon#read 3, iclass 33, count 2 2006.161.08:04:33.40#ibcon#about to read 4, iclass 33, count 2 2006.161.08:04:33.40#ibcon#read 4, iclass 33, count 2 2006.161.08:04:33.40#ibcon#about to read 5, iclass 33, count 2 2006.161.08:04:33.40#ibcon#read 5, iclass 33, count 2 2006.161.08:04:33.40#ibcon#about to read 6, iclass 33, count 2 2006.161.08:04:33.40#ibcon#read 6, iclass 33, count 2 2006.161.08:04:33.40#ibcon#end of sib2, iclass 33, count 2 2006.161.08:04:33.40#ibcon#*mode == 0, iclass 33, count 2 2006.161.08:04:33.40#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.08:04:33.40#ibcon#[27=AT05-04\r\n] 2006.161.08:04:33.40#ibcon#*before write, iclass 33, count 2 2006.161.08:04:33.40#ibcon#enter sib2, iclass 33, count 2 2006.161.08:04:33.40#ibcon#flushed, iclass 33, count 2 2006.161.08:04:33.40#ibcon#about to write, iclass 33, count 2 2006.161.08:04:33.40#ibcon#wrote, iclass 33, count 2 2006.161.08:04:33.40#ibcon#about to read 3, iclass 33, count 2 2006.161.08:04:33.43#ibcon#read 3, iclass 33, count 2 2006.161.08:04:33.43#ibcon#about to read 4, iclass 33, count 2 2006.161.08:04:33.43#ibcon#read 4, iclass 33, count 2 2006.161.08:04:33.43#ibcon#about to read 5, iclass 33, count 2 2006.161.08:04:33.43#ibcon#read 5, iclass 33, count 2 2006.161.08:04:33.43#ibcon#about to read 6, iclass 33, count 2 2006.161.08:04:33.43#ibcon#read 6, iclass 33, count 2 2006.161.08:04:33.43#ibcon#end of sib2, iclass 33, count 2 2006.161.08:04:33.43#ibcon#*after write, iclass 33, count 2 2006.161.08:04:33.43#ibcon#*before return 0, iclass 33, count 2 2006.161.08:04:33.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:33.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:04:33.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.08:04:33.43#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:33.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:33.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:33.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:33.55#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:04:33.55#ibcon#first serial, iclass 33, count 0 2006.161.08:04:33.55#ibcon#enter sib2, iclass 33, count 0 2006.161.08:04:33.55#ibcon#flushed, iclass 33, count 0 2006.161.08:04:33.55#ibcon#about to write, iclass 33, count 0 2006.161.08:04:33.55#ibcon#wrote, iclass 33, count 0 2006.161.08:04:33.55#ibcon#about to read 3, iclass 33, count 0 2006.161.08:04:33.57#ibcon#read 3, iclass 33, count 0 2006.161.08:04:33.57#ibcon#about to read 4, iclass 33, count 0 2006.161.08:04:33.57#ibcon#read 4, iclass 33, count 0 2006.161.08:04:33.57#ibcon#about to read 5, iclass 33, count 0 2006.161.08:04:33.57#ibcon#read 5, iclass 33, count 0 2006.161.08:04:33.57#ibcon#about to read 6, iclass 33, count 0 2006.161.08:04:33.57#ibcon#read 6, iclass 33, count 0 2006.161.08:04:33.57#ibcon#end of sib2, iclass 33, count 0 2006.161.08:04:33.57#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:04:33.57#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:04:33.57#ibcon#[27=USB\r\n] 2006.161.08:04:33.57#ibcon#*before write, iclass 33, count 0 2006.161.08:04:33.57#ibcon#enter sib2, iclass 33, count 0 2006.161.08:04:33.57#ibcon#flushed, iclass 33, count 0 2006.161.08:04:33.57#ibcon#about to write, iclass 33, count 0 2006.161.08:04:33.57#ibcon#wrote, iclass 33, count 0 2006.161.08:04:33.57#ibcon#about to read 3, iclass 33, count 0 2006.161.08:04:33.60#ibcon#read 3, iclass 33, count 0 2006.161.08:04:33.60#ibcon#about to read 4, iclass 33, count 0 2006.161.08:04:33.60#ibcon#read 4, iclass 33, count 0 2006.161.08:04:33.60#ibcon#about to read 5, iclass 33, count 0 2006.161.08:04:33.60#ibcon#read 5, iclass 33, count 0 2006.161.08:04:33.60#ibcon#about to read 6, iclass 33, count 0 2006.161.08:04:33.60#ibcon#read 6, iclass 33, count 0 2006.161.08:04:33.60#ibcon#end of sib2, iclass 33, count 0 2006.161.08:04:33.60#ibcon#*after write, iclass 33, count 0 2006.161.08:04:33.60#ibcon#*before return 0, iclass 33, count 0 2006.161.08:04:33.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:33.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:04:33.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:04:33.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:04:33.60$vc4f8/vblo=6,752.99 2006.161.08:04:33.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.08:04:33.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.08:04:33.60#ibcon#ireg 17 cls_cnt 0 2006.161.08:04:33.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:04:33.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:04:33.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:04:33.60#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:04:33.60#ibcon#first serial, iclass 35, count 0 2006.161.08:04:33.60#ibcon#enter sib2, iclass 35, count 0 2006.161.08:04:33.60#ibcon#flushed, iclass 35, count 0 2006.161.08:04:33.60#ibcon#about to write, iclass 35, count 0 2006.161.08:04:33.60#ibcon#wrote, iclass 35, count 0 2006.161.08:04:33.60#ibcon#about to read 3, iclass 35, count 0 2006.161.08:04:33.62#ibcon#read 3, iclass 35, count 0 2006.161.08:04:33.62#ibcon#about to read 4, iclass 35, count 0 2006.161.08:04:33.62#ibcon#read 4, iclass 35, count 0 2006.161.08:04:33.62#ibcon#about to read 5, iclass 35, count 0 2006.161.08:04:33.62#ibcon#read 5, iclass 35, count 0 2006.161.08:04:33.62#ibcon#about to read 6, iclass 35, count 0 2006.161.08:04:33.62#ibcon#read 6, iclass 35, count 0 2006.161.08:04:33.62#ibcon#end of sib2, iclass 35, count 0 2006.161.08:04:33.62#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:04:33.62#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:04:33.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:04:33.62#ibcon#*before write, iclass 35, count 0 2006.161.08:04:33.62#ibcon#enter sib2, iclass 35, count 0 2006.161.08:04:33.62#ibcon#flushed, iclass 35, count 0 2006.161.08:04:33.62#ibcon#about to write, iclass 35, count 0 2006.161.08:04:33.62#ibcon#wrote, iclass 35, count 0 2006.161.08:04:33.62#ibcon#about to read 3, iclass 35, count 0 2006.161.08:04:33.66#ibcon#read 3, iclass 35, count 0 2006.161.08:04:33.66#ibcon#about to read 4, iclass 35, count 0 2006.161.08:04:33.66#ibcon#read 4, iclass 35, count 0 2006.161.08:04:33.66#ibcon#about to read 5, iclass 35, count 0 2006.161.08:04:33.66#ibcon#read 5, iclass 35, count 0 2006.161.08:04:33.66#ibcon#about to read 6, iclass 35, count 0 2006.161.08:04:33.66#ibcon#read 6, iclass 35, count 0 2006.161.08:04:33.66#ibcon#end of sib2, iclass 35, count 0 2006.161.08:04:33.66#ibcon#*after write, iclass 35, count 0 2006.161.08:04:33.66#ibcon#*before return 0, iclass 35, count 0 2006.161.08:04:33.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:04:33.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:04:33.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:04:33.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:04:33.66$vc4f8/vb=6,4 2006.161.08:04:33.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.08:04:33.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.08:04:33.66#ibcon#ireg 11 cls_cnt 2 2006.161.08:04:33.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:04:33.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:04:33.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:04:33.72#ibcon#enter wrdev, iclass 37, count 2 2006.161.08:04:33.72#ibcon#first serial, iclass 37, count 2 2006.161.08:04:33.72#ibcon#enter sib2, iclass 37, count 2 2006.161.08:04:33.72#ibcon#flushed, iclass 37, count 2 2006.161.08:04:33.72#ibcon#about to write, iclass 37, count 2 2006.161.08:04:33.72#ibcon#wrote, iclass 37, count 2 2006.161.08:04:33.72#ibcon#about to read 3, iclass 37, count 2 2006.161.08:04:33.74#ibcon#read 3, iclass 37, count 2 2006.161.08:04:33.74#ibcon#about to read 4, iclass 37, count 2 2006.161.08:04:33.74#ibcon#read 4, iclass 37, count 2 2006.161.08:04:33.74#ibcon#about to read 5, iclass 37, count 2 2006.161.08:04:33.74#ibcon#read 5, iclass 37, count 2 2006.161.08:04:33.74#ibcon#about to read 6, iclass 37, count 2 2006.161.08:04:33.74#ibcon#read 6, iclass 37, count 2 2006.161.08:04:33.74#ibcon#end of sib2, iclass 37, count 2 2006.161.08:04:33.74#ibcon#*mode == 0, iclass 37, count 2 2006.161.08:04:33.74#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.08:04:33.74#ibcon#[27=AT06-04\r\n] 2006.161.08:04:33.74#ibcon#*before write, iclass 37, count 2 2006.161.08:04:33.74#ibcon#enter sib2, iclass 37, count 2 2006.161.08:04:33.74#ibcon#flushed, iclass 37, count 2 2006.161.08:04:33.74#ibcon#about to write, iclass 37, count 2 2006.161.08:04:33.74#ibcon#wrote, iclass 37, count 2 2006.161.08:04:33.74#ibcon#about to read 3, iclass 37, count 2 2006.161.08:04:33.77#ibcon#read 3, iclass 37, count 2 2006.161.08:04:33.77#ibcon#about to read 4, iclass 37, count 2 2006.161.08:04:33.77#ibcon#read 4, iclass 37, count 2 2006.161.08:04:33.77#ibcon#about to read 5, iclass 37, count 2 2006.161.08:04:33.77#ibcon#read 5, iclass 37, count 2 2006.161.08:04:33.77#ibcon#about to read 6, iclass 37, count 2 2006.161.08:04:33.77#ibcon#read 6, iclass 37, count 2 2006.161.08:04:33.77#ibcon#end of sib2, iclass 37, count 2 2006.161.08:04:33.77#ibcon#*after write, iclass 37, count 2 2006.161.08:04:33.77#ibcon#*before return 0, iclass 37, count 2 2006.161.08:04:33.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:04:33.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:04:33.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.08:04:33.77#ibcon#ireg 7 cls_cnt 0 2006.161.08:04:33.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:04:33.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:04:33.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:04:33.89#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:04:33.89#ibcon#first serial, iclass 37, count 0 2006.161.08:04:33.89#ibcon#enter sib2, iclass 37, count 0 2006.161.08:04:33.89#ibcon#flushed, iclass 37, count 0 2006.161.08:04:33.89#ibcon#about to write, iclass 37, count 0 2006.161.08:04:33.89#ibcon#wrote, iclass 37, count 0 2006.161.08:04:33.89#ibcon#about to read 3, iclass 37, count 0 2006.161.08:04:33.91#ibcon#read 3, iclass 37, count 0 2006.161.08:04:33.91#ibcon#about to read 4, iclass 37, count 0 2006.161.08:04:33.91#ibcon#read 4, iclass 37, count 0 2006.161.08:04:33.91#ibcon#about to read 5, iclass 37, count 0 2006.161.08:04:33.91#ibcon#read 5, iclass 37, count 0 2006.161.08:04:33.91#ibcon#about to read 6, iclass 37, count 0 2006.161.08:04:33.91#ibcon#read 6, iclass 37, count 0 2006.161.08:04:33.91#ibcon#end of sib2, iclass 37, count 0 2006.161.08:04:33.91#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:04:33.91#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:04:33.91#ibcon#[27=USB\r\n] 2006.161.08:04:33.91#ibcon#*before write, iclass 37, count 0 2006.161.08:04:33.91#ibcon#enter sib2, iclass 37, count 0 2006.161.08:04:33.91#ibcon#flushed, iclass 37, count 0 2006.161.08:04:33.91#ibcon#about to write, iclass 37, count 0 2006.161.08:04:33.91#ibcon#wrote, iclass 37, count 0 2006.161.08:04:33.91#ibcon#about to read 3, iclass 37, count 0 2006.161.08:04:33.94#ibcon#read 3, iclass 37, count 0 2006.161.08:04:33.94#ibcon#about to read 4, iclass 37, count 0 2006.161.08:04:33.94#ibcon#read 4, iclass 37, count 0 2006.161.08:04:33.94#ibcon#about to read 5, iclass 37, count 0 2006.161.08:04:33.94#ibcon#read 5, iclass 37, count 0 2006.161.08:04:33.94#ibcon#about to read 6, iclass 37, count 0 2006.161.08:04:33.94#ibcon#read 6, iclass 37, count 0 2006.161.08:04:33.94#ibcon#end of sib2, iclass 37, count 0 2006.161.08:04:33.94#ibcon#*after write, iclass 37, count 0 2006.161.08:04:33.94#ibcon#*before return 0, iclass 37, count 0 2006.161.08:04:33.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:04:33.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:04:33.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:04:33.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:04:33.94$vc4f8/vabw=wide 2006.161.08:04:33.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.08:04:33.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.08:04:33.94#ibcon#ireg 8 cls_cnt 0 2006.161.08:04:33.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:04:33.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:04:33.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:04:33.94#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:04:33.94#ibcon#first serial, iclass 39, count 0 2006.161.08:04:33.94#ibcon#enter sib2, iclass 39, count 0 2006.161.08:04:33.94#ibcon#flushed, iclass 39, count 0 2006.161.08:04:33.94#ibcon#about to write, iclass 39, count 0 2006.161.08:04:33.94#ibcon#wrote, iclass 39, count 0 2006.161.08:04:33.94#ibcon#about to read 3, iclass 39, count 0 2006.161.08:04:33.96#ibcon#read 3, iclass 39, count 0 2006.161.08:04:33.96#ibcon#about to read 4, iclass 39, count 0 2006.161.08:04:33.96#ibcon#read 4, iclass 39, count 0 2006.161.08:04:33.96#ibcon#about to read 5, iclass 39, count 0 2006.161.08:04:33.96#ibcon#read 5, iclass 39, count 0 2006.161.08:04:33.96#ibcon#about to read 6, iclass 39, count 0 2006.161.08:04:33.96#ibcon#read 6, iclass 39, count 0 2006.161.08:04:33.96#ibcon#end of sib2, iclass 39, count 0 2006.161.08:04:33.96#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:04:33.96#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:04:33.96#ibcon#[25=BW32\r\n] 2006.161.08:04:33.96#ibcon#*before write, iclass 39, count 0 2006.161.08:04:33.96#ibcon#enter sib2, iclass 39, count 0 2006.161.08:04:33.96#ibcon#flushed, iclass 39, count 0 2006.161.08:04:33.96#ibcon#about to write, iclass 39, count 0 2006.161.08:04:33.96#ibcon#wrote, iclass 39, count 0 2006.161.08:04:33.96#ibcon#about to read 3, iclass 39, count 0 2006.161.08:04:33.99#ibcon#read 3, iclass 39, count 0 2006.161.08:04:33.99#ibcon#about to read 4, iclass 39, count 0 2006.161.08:04:33.99#ibcon#read 4, iclass 39, count 0 2006.161.08:04:33.99#ibcon#about to read 5, iclass 39, count 0 2006.161.08:04:33.99#ibcon#read 5, iclass 39, count 0 2006.161.08:04:33.99#ibcon#about to read 6, iclass 39, count 0 2006.161.08:04:33.99#ibcon#read 6, iclass 39, count 0 2006.161.08:04:33.99#ibcon#end of sib2, iclass 39, count 0 2006.161.08:04:33.99#ibcon#*after write, iclass 39, count 0 2006.161.08:04:33.99#ibcon#*before return 0, iclass 39, count 0 2006.161.08:04:33.99#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:04:33.99#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:04:33.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:04:33.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:04:33.99$vc4f8/vbbw=wide 2006.161.08:04:33.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:04:33.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:04:33.99#ibcon#ireg 8 cls_cnt 0 2006.161.08:04:33.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:04:34.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:04:34.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:04:34.06#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:04:34.06#ibcon#first serial, iclass 3, count 0 2006.161.08:04:34.06#ibcon#enter sib2, iclass 3, count 0 2006.161.08:04:34.06#ibcon#flushed, iclass 3, count 0 2006.161.08:04:34.06#ibcon#about to write, iclass 3, count 0 2006.161.08:04:34.06#ibcon#wrote, iclass 3, count 0 2006.161.08:04:34.06#ibcon#about to read 3, iclass 3, count 0 2006.161.08:04:34.08#ibcon#read 3, iclass 3, count 0 2006.161.08:04:34.08#ibcon#about to read 4, iclass 3, count 0 2006.161.08:04:34.08#ibcon#read 4, iclass 3, count 0 2006.161.08:04:34.08#ibcon#about to read 5, iclass 3, count 0 2006.161.08:04:34.08#ibcon#read 5, iclass 3, count 0 2006.161.08:04:34.08#ibcon#about to read 6, iclass 3, count 0 2006.161.08:04:34.08#ibcon#read 6, iclass 3, count 0 2006.161.08:04:34.08#ibcon#end of sib2, iclass 3, count 0 2006.161.08:04:34.08#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:04:34.08#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:04:34.08#ibcon#[27=BW32\r\n] 2006.161.08:04:34.08#ibcon#*before write, iclass 3, count 0 2006.161.08:04:34.08#ibcon#enter sib2, iclass 3, count 0 2006.161.08:04:34.08#ibcon#flushed, iclass 3, count 0 2006.161.08:04:34.08#ibcon#about to write, iclass 3, count 0 2006.161.08:04:34.08#ibcon#wrote, iclass 3, count 0 2006.161.08:04:34.08#ibcon#about to read 3, iclass 3, count 0 2006.161.08:04:34.11#ibcon#read 3, iclass 3, count 0 2006.161.08:04:34.11#ibcon#about to read 4, iclass 3, count 0 2006.161.08:04:34.11#ibcon#read 4, iclass 3, count 0 2006.161.08:04:34.11#ibcon#about to read 5, iclass 3, count 0 2006.161.08:04:34.11#ibcon#read 5, iclass 3, count 0 2006.161.08:04:34.11#ibcon#about to read 6, iclass 3, count 0 2006.161.08:04:34.11#ibcon#read 6, iclass 3, count 0 2006.161.08:04:34.11#ibcon#end of sib2, iclass 3, count 0 2006.161.08:04:34.11#ibcon#*after write, iclass 3, count 0 2006.161.08:04:34.11#ibcon#*before return 0, iclass 3, count 0 2006.161.08:04:34.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:04:34.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:04:34.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:04:34.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:04:34.11$4f8m12a/ifd4f 2006.161.08:04:34.11$ifd4f/lo= 2006.161.08:04:34.11$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:04:34.11$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:04:34.11$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:04:34.11$ifd4f/patch= 2006.161.08:04:34.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:04:34.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:04:34.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:04:34.12$4f8m12a/"form=m,16.000,1:2 2006.161.08:04:34.12$4f8m12a/"tpicd 2006.161.08:04:34.12$4f8m12a/echo=off 2006.161.08:04:34.12$4f8m12a/xlog=off 2006.161.08:04:34.12:!2006.161.08:05:00 2006.161.08:04:41.13#trakl#Source acquired 2006.161.08:04:42.13#flagr#flagr/antenna,acquired 2006.161.08:05:00.01:preob 2006.161.08:05:01.13/onsource/TRACKING 2006.161.08:05:01.13:!2006.161.08:05:10 2006.161.08:05:10.00:data_valid=on 2006.161.08:05:10.00:midob 2006.161.08:05:10.13/onsource/TRACKING 2006.161.08:05:10.13/wx/24.02,1002.2,85 2006.161.08:05:10.36/cable/+6.4990E-03 2006.161.08:05:11.45/va/01,08,usb,yes,29,31 2006.161.08:05:11.45/va/02,07,usb,yes,30,31 2006.161.08:05:11.45/va/03,06,usb,yes,31,31 2006.161.08:05:11.45/va/04,07,usb,yes,30,32 2006.161.08:05:11.45/va/05,07,usb,yes,30,32 2006.161.08:05:11.45/va/06,06,usb,yes,30,29 2006.161.08:05:11.45/va/07,06,usb,yes,30,30 2006.161.08:05:11.45/va/08,07,usb,yes,28,28 2006.161.08:05:11.68/valo/01,532.99,yes,locked 2006.161.08:05:11.68/valo/02,572.99,yes,locked 2006.161.08:05:11.68/valo/03,672.99,yes,locked 2006.161.08:05:11.68/valo/04,832.99,yes,locked 2006.161.08:05:11.68/valo/05,652.99,yes,locked 2006.161.08:05:11.68/valo/06,772.99,yes,locked 2006.161.08:05:11.68/valo/07,832.99,yes,locked 2006.161.08:05:11.68/valo/08,852.99,yes,locked 2006.161.08:05:12.77/vb/01,04,usb,yes,29,28 2006.161.08:05:12.77/vb/02,04,usb,yes,31,32 2006.161.08:05:12.77/vb/03,04,usb,yes,27,31 2006.161.08:05:12.77/vb/04,04,usb,yes,28,28 2006.161.08:05:12.77/vb/05,04,usb,yes,27,31 2006.161.08:05:12.77/vb/06,04,usb,yes,28,30 2006.161.08:05:12.77/vb/07,04,usb,yes,30,30 2006.161.08:05:12.77/vb/08,04,usb,yes,27,31 2006.161.08:05:13.00/vblo/01,632.99,yes,locked 2006.161.08:05:13.00/vblo/02,640.99,yes,locked 2006.161.08:05:13.00/vblo/03,656.99,yes,locked 2006.161.08:05:13.00/vblo/04,712.99,yes,locked 2006.161.08:05:13.00/vblo/05,744.99,yes,locked 2006.161.08:05:13.00/vblo/06,752.99,yes,locked 2006.161.08:05:13.00/vblo/07,734.99,yes,locked 2006.161.08:05:13.00/vblo/08,744.99,yes,locked 2006.161.08:05:13.15/vabw/8 2006.161.08:05:13.30/vbbw/8 2006.161.08:05:13.39/xfe/off,on,14.7 2006.161.08:05:13.76/ifatt/23,28,28,28 2006.161.08:05:14.07/fmout-gps/S +4.50E-07 2006.161.08:05:14.12:!2006.161.08:06:10 2006.161.08:06:10.01:data_valid=off 2006.161.08:06:10.02:postob 2006.161.08:06:10.09/cable/+6.5000E-03 2006.161.08:06:10.10/wx/24.01,1002.3,86 2006.161.08:06:11.07/fmout-gps/S +4.50E-07 2006.161.08:06:11.08:scan_name=161-0807,k06161,60 2006.161.08:06:11.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.161.08:06:11.13#flagr#flagr/antenna,new-source 2006.161.08:06:12.13:checkk5 2006.161.08:06:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:06:12.97/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:06:13.40/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:06:13.84/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:06:14.24/chk_obsdata//k5ts1/T1610805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:06:14.64/chk_obsdata//k5ts2/T1610805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:06:15.02/chk_obsdata//k5ts3/T1610805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:06:15.41/chk_obsdata//k5ts4/T1610805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:06:16.25/k5log//k5ts1_log_newline 2006.161.08:06:17.03/k5log//k5ts2_log_newline 2006.161.08:06:17.85/k5log//k5ts3_log_newline 2006.161.08:06:18.63/k5log//k5ts4_log_newline 2006.161.08:06:18.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:06:18.66:4f8m12a=2 2006.161.08:06:18.66$4f8m12a/echo=on 2006.161.08:06:18.66$4f8m12a/pcalon 2006.161.08:06:18.66$pcalon/"no phase cal control is implemented here 2006.161.08:06:18.66$4f8m12a/"tpicd=stop 2006.161.08:06:18.66$4f8m12a/vc4f8 2006.161.08:06:18.66$vc4f8/valo=1,532.99 2006.161.08:06:18.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:06:18.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:06:18.66#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:18.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:18.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:18.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:18.66#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:06:18.66#ibcon#first serial, iclass 12, count 0 2006.161.08:06:18.66#ibcon#enter sib2, iclass 12, count 0 2006.161.08:06:18.66#ibcon#flushed, iclass 12, count 0 2006.161.08:06:18.66#ibcon#about to write, iclass 12, count 0 2006.161.08:06:18.66#ibcon#wrote, iclass 12, count 0 2006.161.08:06:18.66#ibcon#about to read 3, iclass 12, count 0 2006.161.08:06:18.70#ibcon#read 3, iclass 12, count 0 2006.161.08:06:18.70#ibcon#about to read 4, iclass 12, count 0 2006.161.08:06:18.70#ibcon#read 4, iclass 12, count 0 2006.161.08:06:18.70#ibcon#about to read 5, iclass 12, count 0 2006.161.08:06:18.70#ibcon#read 5, iclass 12, count 0 2006.161.08:06:18.70#ibcon#about to read 6, iclass 12, count 0 2006.161.08:06:18.70#ibcon#read 6, iclass 12, count 0 2006.161.08:06:18.70#ibcon#end of sib2, iclass 12, count 0 2006.161.08:06:18.70#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:06:18.70#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:06:18.70#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:06:18.70#ibcon#*before write, iclass 12, count 0 2006.161.08:06:18.70#ibcon#enter sib2, iclass 12, count 0 2006.161.08:06:18.70#ibcon#flushed, iclass 12, count 0 2006.161.08:06:18.70#ibcon#about to write, iclass 12, count 0 2006.161.08:06:18.70#ibcon#wrote, iclass 12, count 0 2006.161.08:06:18.70#ibcon#about to read 3, iclass 12, count 0 2006.161.08:06:18.75#ibcon#read 3, iclass 12, count 0 2006.161.08:06:18.75#ibcon#about to read 4, iclass 12, count 0 2006.161.08:06:18.75#ibcon#read 4, iclass 12, count 0 2006.161.08:06:18.75#ibcon#about to read 5, iclass 12, count 0 2006.161.08:06:18.75#ibcon#read 5, iclass 12, count 0 2006.161.08:06:18.75#ibcon#about to read 6, iclass 12, count 0 2006.161.08:06:18.75#ibcon#read 6, iclass 12, count 0 2006.161.08:06:18.75#ibcon#end of sib2, iclass 12, count 0 2006.161.08:06:18.75#ibcon#*after write, iclass 12, count 0 2006.161.08:06:18.75#ibcon#*before return 0, iclass 12, count 0 2006.161.08:06:18.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:18.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:18.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:06:18.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:06:18.75$vc4f8/va=1,8 2006.161.08:06:18.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.08:06:18.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.08:06:18.75#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:18.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:18.75#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:18.75#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:18.75#ibcon#enter wrdev, iclass 14, count 2 2006.161.08:06:18.75#ibcon#first serial, iclass 14, count 2 2006.161.08:06:18.75#ibcon#enter sib2, iclass 14, count 2 2006.161.08:06:18.75#ibcon#flushed, iclass 14, count 2 2006.161.08:06:18.75#ibcon#about to write, iclass 14, count 2 2006.161.08:06:18.75#ibcon#wrote, iclass 14, count 2 2006.161.08:06:18.75#ibcon#about to read 3, iclass 14, count 2 2006.161.08:06:18.77#ibcon#read 3, iclass 14, count 2 2006.161.08:06:18.77#ibcon#about to read 4, iclass 14, count 2 2006.161.08:06:18.77#ibcon#read 4, iclass 14, count 2 2006.161.08:06:18.77#ibcon#about to read 5, iclass 14, count 2 2006.161.08:06:18.77#ibcon#read 5, iclass 14, count 2 2006.161.08:06:18.77#ibcon#about to read 6, iclass 14, count 2 2006.161.08:06:18.77#ibcon#read 6, iclass 14, count 2 2006.161.08:06:18.77#ibcon#end of sib2, iclass 14, count 2 2006.161.08:06:18.77#ibcon#*mode == 0, iclass 14, count 2 2006.161.08:06:18.77#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.08:06:18.77#ibcon#[25=AT01-08\r\n] 2006.161.08:06:18.77#ibcon#*before write, iclass 14, count 2 2006.161.08:06:18.77#ibcon#enter sib2, iclass 14, count 2 2006.161.08:06:18.77#ibcon#flushed, iclass 14, count 2 2006.161.08:06:18.77#ibcon#about to write, iclass 14, count 2 2006.161.08:06:18.77#ibcon#wrote, iclass 14, count 2 2006.161.08:06:18.77#ibcon#about to read 3, iclass 14, count 2 2006.161.08:06:18.80#ibcon#read 3, iclass 14, count 2 2006.161.08:06:18.80#ibcon#about to read 4, iclass 14, count 2 2006.161.08:06:18.80#ibcon#read 4, iclass 14, count 2 2006.161.08:06:18.80#ibcon#about to read 5, iclass 14, count 2 2006.161.08:06:18.80#ibcon#read 5, iclass 14, count 2 2006.161.08:06:18.80#ibcon#about to read 6, iclass 14, count 2 2006.161.08:06:18.80#ibcon#read 6, iclass 14, count 2 2006.161.08:06:18.80#ibcon#end of sib2, iclass 14, count 2 2006.161.08:06:18.80#ibcon#*after write, iclass 14, count 2 2006.161.08:06:18.80#ibcon#*before return 0, iclass 14, count 2 2006.161.08:06:18.80#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:18.80#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:18.80#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.08:06:18.80#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:18.80#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:18.92#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:18.92#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:18.92#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:06:18.92#ibcon#first serial, iclass 14, count 0 2006.161.08:06:18.92#ibcon#enter sib2, iclass 14, count 0 2006.161.08:06:18.92#ibcon#flushed, iclass 14, count 0 2006.161.08:06:18.92#ibcon#about to write, iclass 14, count 0 2006.161.08:06:18.92#ibcon#wrote, iclass 14, count 0 2006.161.08:06:18.92#ibcon#about to read 3, iclass 14, count 0 2006.161.08:06:18.94#ibcon#read 3, iclass 14, count 0 2006.161.08:06:18.94#ibcon#about to read 4, iclass 14, count 0 2006.161.08:06:18.94#ibcon#read 4, iclass 14, count 0 2006.161.08:06:18.94#ibcon#about to read 5, iclass 14, count 0 2006.161.08:06:18.94#ibcon#read 5, iclass 14, count 0 2006.161.08:06:18.94#ibcon#about to read 6, iclass 14, count 0 2006.161.08:06:18.94#ibcon#read 6, iclass 14, count 0 2006.161.08:06:18.94#ibcon#end of sib2, iclass 14, count 0 2006.161.08:06:18.94#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:06:18.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:06:18.94#ibcon#[25=USB\r\n] 2006.161.08:06:18.94#ibcon#*before write, iclass 14, count 0 2006.161.08:06:18.94#ibcon#enter sib2, iclass 14, count 0 2006.161.08:06:18.94#ibcon#flushed, iclass 14, count 0 2006.161.08:06:18.94#ibcon#about to write, iclass 14, count 0 2006.161.08:06:18.94#ibcon#wrote, iclass 14, count 0 2006.161.08:06:18.94#ibcon#about to read 3, iclass 14, count 0 2006.161.08:06:18.97#ibcon#read 3, iclass 14, count 0 2006.161.08:06:18.97#ibcon#about to read 4, iclass 14, count 0 2006.161.08:06:18.97#ibcon#read 4, iclass 14, count 0 2006.161.08:06:18.97#ibcon#about to read 5, iclass 14, count 0 2006.161.08:06:18.97#ibcon#read 5, iclass 14, count 0 2006.161.08:06:18.97#ibcon#about to read 6, iclass 14, count 0 2006.161.08:06:18.97#ibcon#read 6, iclass 14, count 0 2006.161.08:06:18.97#ibcon#end of sib2, iclass 14, count 0 2006.161.08:06:18.97#ibcon#*after write, iclass 14, count 0 2006.161.08:06:18.97#ibcon#*before return 0, iclass 14, count 0 2006.161.08:06:18.97#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:18.97#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:18.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:06:18.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:06:18.97$vc4f8/valo=2,572.99 2006.161.08:06:18.97#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.08:06:18.97#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.08:06:18.97#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:18.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:18.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:18.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:18.97#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:06:18.97#ibcon#first serial, iclass 16, count 0 2006.161.08:06:18.97#ibcon#enter sib2, iclass 16, count 0 2006.161.08:06:18.97#ibcon#flushed, iclass 16, count 0 2006.161.08:06:18.97#ibcon#about to write, iclass 16, count 0 2006.161.08:06:18.97#ibcon#wrote, iclass 16, count 0 2006.161.08:06:18.97#ibcon#about to read 3, iclass 16, count 0 2006.161.08:06:18.99#ibcon#read 3, iclass 16, count 0 2006.161.08:06:18.99#ibcon#about to read 4, iclass 16, count 0 2006.161.08:06:18.99#ibcon#read 4, iclass 16, count 0 2006.161.08:06:18.99#ibcon#about to read 5, iclass 16, count 0 2006.161.08:06:18.99#ibcon#read 5, iclass 16, count 0 2006.161.08:06:18.99#ibcon#about to read 6, iclass 16, count 0 2006.161.08:06:18.99#ibcon#read 6, iclass 16, count 0 2006.161.08:06:18.99#ibcon#end of sib2, iclass 16, count 0 2006.161.08:06:18.99#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:06:18.99#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:06:18.99#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:06:18.99#ibcon#*before write, iclass 16, count 0 2006.161.08:06:18.99#ibcon#enter sib2, iclass 16, count 0 2006.161.08:06:18.99#ibcon#flushed, iclass 16, count 0 2006.161.08:06:18.99#ibcon#about to write, iclass 16, count 0 2006.161.08:06:18.99#ibcon#wrote, iclass 16, count 0 2006.161.08:06:18.99#ibcon#about to read 3, iclass 16, count 0 2006.161.08:06:19.03#ibcon#read 3, iclass 16, count 0 2006.161.08:06:19.03#ibcon#about to read 4, iclass 16, count 0 2006.161.08:06:19.03#ibcon#read 4, iclass 16, count 0 2006.161.08:06:19.03#ibcon#about to read 5, iclass 16, count 0 2006.161.08:06:19.03#ibcon#read 5, iclass 16, count 0 2006.161.08:06:19.03#ibcon#about to read 6, iclass 16, count 0 2006.161.08:06:19.03#ibcon#read 6, iclass 16, count 0 2006.161.08:06:19.03#ibcon#end of sib2, iclass 16, count 0 2006.161.08:06:19.03#ibcon#*after write, iclass 16, count 0 2006.161.08:06:19.03#ibcon#*before return 0, iclass 16, count 0 2006.161.08:06:19.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:19.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:19.03#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:06:19.03#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:06:19.03$vc4f8/va=2,7 2006.161.08:06:19.03#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.08:06:19.03#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.08:06:19.03#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:19.03#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:19.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:19.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:19.10#ibcon#enter wrdev, iclass 18, count 2 2006.161.08:06:19.10#ibcon#first serial, iclass 18, count 2 2006.161.08:06:19.10#ibcon#enter sib2, iclass 18, count 2 2006.161.08:06:19.10#ibcon#flushed, iclass 18, count 2 2006.161.08:06:19.10#ibcon#about to write, iclass 18, count 2 2006.161.08:06:19.10#ibcon#wrote, iclass 18, count 2 2006.161.08:06:19.10#ibcon#about to read 3, iclass 18, count 2 2006.161.08:06:19.12#ibcon#read 3, iclass 18, count 2 2006.161.08:06:19.12#ibcon#about to read 4, iclass 18, count 2 2006.161.08:06:19.12#ibcon#read 4, iclass 18, count 2 2006.161.08:06:19.12#ibcon#about to read 5, iclass 18, count 2 2006.161.08:06:19.12#ibcon#read 5, iclass 18, count 2 2006.161.08:06:19.12#ibcon#about to read 6, iclass 18, count 2 2006.161.08:06:19.12#ibcon#read 6, iclass 18, count 2 2006.161.08:06:19.12#ibcon#end of sib2, iclass 18, count 2 2006.161.08:06:19.12#ibcon#*mode == 0, iclass 18, count 2 2006.161.08:06:19.12#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.08:06:19.12#ibcon#[25=AT02-07\r\n] 2006.161.08:06:19.12#ibcon#*before write, iclass 18, count 2 2006.161.08:06:19.12#ibcon#enter sib2, iclass 18, count 2 2006.161.08:06:19.12#ibcon#flushed, iclass 18, count 2 2006.161.08:06:19.12#ibcon#about to write, iclass 18, count 2 2006.161.08:06:19.12#ibcon#wrote, iclass 18, count 2 2006.161.08:06:19.12#ibcon#about to read 3, iclass 18, count 2 2006.161.08:06:19.14#ibcon#read 3, iclass 18, count 2 2006.161.08:06:19.14#ibcon#about to read 4, iclass 18, count 2 2006.161.08:06:19.14#ibcon#read 4, iclass 18, count 2 2006.161.08:06:19.14#ibcon#about to read 5, iclass 18, count 2 2006.161.08:06:19.14#ibcon#read 5, iclass 18, count 2 2006.161.08:06:19.14#ibcon#about to read 6, iclass 18, count 2 2006.161.08:06:19.14#ibcon#read 6, iclass 18, count 2 2006.161.08:06:19.14#ibcon#end of sib2, iclass 18, count 2 2006.161.08:06:19.14#ibcon#*after write, iclass 18, count 2 2006.161.08:06:19.14#ibcon#*before return 0, iclass 18, count 2 2006.161.08:06:19.14#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:19.14#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:19.14#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.08:06:19.14#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:19.14#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:19.26#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:19.26#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:19.26#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:06:19.26#ibcon#first serial, iclass 18, count 0 2006.161.08:06:19.26#ibcon#enter sib2, iclass 18, count 0 2006.161.08:06:19.26#ibcon#flushed, iclass 18, count 0 2006.161.08:06:19.26#ibcon#about to write, iclass 18, count 0 2006.161.08:06:19.26#ibcon#wrote, iclass 18, count 0 2006.161.08:06:19.26#ibcon#about to read 3, iclass 18, count 0 2006.161.08:06:19.28#ibcon#read 3, iclass 18, count 0 2006.161.08:06:19.28#ibcon#about to read 4, iclass 18, count 0 2006.161.08:06:19.28#ibcon#read 4, iclass 18, count 0 2006.161.08:06:19.28#ibcon#about to read 5, iclass 18, count 0 2006.161.08:06:19.28#ibcon#read 5, iclass 18, count 0 2006.161.08:06:19.28#ibcon#about to read 6, iclass 18, count 0 2006.161.08:06:19.28#ibcon#read 6, iclass 18, count 0 2006.161.08:06:19.28#ibcon#end of sib2, iclass 18, count 0 2006.161.08:06:19.28#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:06:19.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:06:19.28#ibcon#[25=USB\r\n] 2006.161.08:06:19.28#ibcon#*before write, iclass 18, count 0 2006.161.08:06:19.28#ibcon#enter sib2, iclass 18, count 0 2006.161.08:06:19.28#ibcon#flushed, iclass 18, count 0 2006.161.08:06:19.28#ibcon#about to write, iclass 18, count 0 2006.161.08:06:19.28#ibcon#wrote, iclass 18, count 0 2006.161.08:06:19.28#ibcon#about to read 3, iclass 18, count 0 2006.161.08:06:19.31#ibcon#read 3, iclass 18, count 0 2006.161.08:06:19.31#ibcon#about to read 4, iclass 18, count 0 2006.161.08:06:19.31#ibcon#read 4, iclass 18, count 0 2006.161.08:06:19.31#ibcon#about to read 5, iclass 18, count 0 2006.161.08:06:19.31#ibcon#read 5, iclass 18, count 0 2006.161.08:06:19.31#ibcon#about to read 6, iclass 18, count 0 2006.161.08:06:19.31#ibcon#read 6, iclass 18, count 0 2006.161.08:06:19.31#ibcon#end of sib2, iclass 18, count 0 2006.161.08:06:19.31#ibcon#*after write, iclass 18, count 0 2006.161.08:06:19.31#ibcon#*before return 0, iclass 18, count 0 2006.161.08:06:19.31#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:19.31#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:19.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:06:19.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:06:19.31$vc4f8/valo=3,672.99 2006.161.08:06:19.31#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.08:06:19.31#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.08:06:19.31#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:19.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:19.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:19.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:19.31#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:06:19.31#ibcon#first serial, iclass 20, count 0 2006.161.08:06:19.31#ibcon#enter sib2, iclass 20, count 0 2006.161.08:06:19.31#ibcon#flushed, iclass 20, count 0 2006.161.08:06:19.31#ibcon#about to write, iclass 20, count 0 2006.161.08:06:19.31#ibcon#wrote, iclass 20, count 0 2006.161.08:06:19.31#ibcon#about to read 3, iclass 20, count 0 2006.161.08:06:19.33#ibcon#read 3, iclass 20, count 0 2006.161.08:06:19.33#ibcon#about to read 4, iclass 20, count 0 2006.161.08:06:19.33#ibcon#read 4, iclass 20, count 0 2006.161.08:06:19.33#ibcon#about to read 5, iclass 20, count 0 2006.161.08:06:19.33#ibcon#read 5, iclass 20, count 0 2006.161.08:06:19.33#ibcon#about to read 6, iclass 20, count 0 2006.161.08:06:19.33#ibcon#read 6, iclass 20, count 0 2006.161.08:06:19.33#ibcon#end of sib2, iclass 20, count 0 2006.161.08:06:19.33#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:06:19.33#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:06:19.33#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:06:19.33#ibcon#*before write, iclass 20, count 0 2006.161.08:06:19.33#ibcon#enter sib2, iclass 20, count 0 2006.161.08:06:19.33#ibcon#flushed, iclass 20, count 0 2006.161.08:06:19.33#ibcon#about to write, iclass 20, count 0 2006.161.08:06:19.33#ibcon#wrote, iclass 20, count 0 2006.161.08:06:19.33#ibcon#about to read 3, iclass 20, count 0 2006.161.08:06:19.37#ibcon#read 3, iclass 20, count 0 2006.161.08:06:19.37#ibcon#about to read 4, iclass 20, count 0 2006.161.08:06:19.37#ibcon#read 4, iclass 20, count 0 2006.161.08:06:19.37#ibcon#about to read 5, iclass 20, count 0 2006.161.08:06:19.37#ibcon#read 5, iclass 20, count 0 2006.161.08:06:19.37#ibcon#about to read 6, iclass 20, count 0 2006.161.08:06:19.37#ibcon#read 6, iclass 20, count 0 2006.161.08:06:19.37#ibcon#end of sib2, iclass 20, count 0 2006.161.08:06:19.37#ibcon#*after write, iclass 20, count 0 2006.161.08:06:19.37#ibcon#*before return 0, iclass 20, count 0 2006.161.08:06:19.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:19.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:19.37#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:06:19.37#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:06:19.37$vc4f8/va=3,6 2006.161.08:06:19.37#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.08:06:19.37#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.08:06:19.37#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:19.37#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:19.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:19.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:19.44#ibcon#enter wrdev, iclass 22, count 2 2006.161.08:06:19.44#ibcon#first serial, iclass 22, count 2 2006.161.08:06:19.44#ibcon#enter sib2, iclass 22, count 2 2006.161.08:06:19.44#ibcon#flushed, iclass 22, count 2 2006.161.08:06:19.44#ibcon#about to write, iclass 22, count 2 2006.161.08:06:19.44#ibcon#wrote, iclass 22, count 2 2006.161.08:06:19.44#ibcon#about to read 3, iclass 22, count 2 2006.161.08:06:19.46#ibcon#read 3, iclass 22, count 2 2006.161.08:06:19.46#ibcon#about to read 4, iclass 22, count 2 2006.161.08:06:19.46#ibcon#read 4, iclass 22, count 2 2006.161.08:06:19.46#ibcon#about to read 5, iclass 22, count 2 2006.161.08:06:19.46#ibcon#read 5, iclass 22, count 2 2006.161.08:06:19.46#ibcon#about to read 6, iclass 22, count 2 2006.161.08:06:19.46#ibcon#read 6, iclass 22, count 2 2006.161.08:06:19.46#ibcon#end of sib2, iclass 22, count 2 2006.161.08:06:19.46#ibcon#*mode == 0, iclass 22, count 2 2006.161.08:06:19.46#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.08:06:19.46#ibcon#[25=AT03-06\r\n] 2006.161.08:06:19.46#ibcon#*before write, iclass 22, count 2 2006.161.08:06:19.46#ibcon#enter sib2, iclass 22, count 2 2006.161.08:06:19.46#ibcon#flushed, iclass 22, count 2 2006.161.08:06:19.46#ibcon#about to write, iclass 22, count 2 2006.161.08:06:19.46#ibcon#wrote, iclass 22, count 2 2006.161.08:06:19.46#ibcon#about to read 3, iclass 22, count 2 2006.161.08:06:19.48#ibcon#read 3, iclass 22, count 2 2006.161.08:06:19.48#ibcon#about to read 4, iclass 22, count 2 2006.161.08:06:19.48#ibcon#read 4, iclass 22, count 2 2006.161.08:06:19.48#ibcon#about to read 5, iclass 22, count 2 2006.161.08:06:19.48#ibcon#read 5, iclass 22, count 2 2006.161.08:06:19.48#ibcon#about to read 6, iclass 22, count 2 2006.161.08:06:19.48#ibcon#read 6, iclass 22, count 2 2006.161.08:06:19.48#ibcon#end of sib2, iclass 22, count 2 2006.161.08:06:19.48#ibcon#*after write, iclass 22, count 2 2006.161.08:06:19.48#ibcon#*before return 0, iclass 22, count 2 2006.161.08:06:19.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:19.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:19.48#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.08:06:19.48#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:19.48#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:19.60#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:19.60#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:19.60#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:06:19.60#ibcon#first serial, iclass 22, count 0 2006.161.08:06:19.60#ibcon#enter sib2, iclass 22, count 0 2006.161.08:06:19.60#ibcon#flushed, iclass 22, count 0 2006.161.08:06:19.60#ibcon#about to write, iclass 22, count 0 2006.161.08:06:19.60#ibcon#wrote, iclass 22, count 0 2006.161.08:06:19.60#ibcon#about to read 3, iclass 22, count 0 2006.161.08:06:19.62#ibcon#read 3, iclass 22, count 0 2006.161.08:06:19.62#ibcon#about to read 4, iclass 22, count 0 2006.161.08:06:19.62#ibcon#read 4, iclass 22, count 0 2006.161.08:06:19.62#ibcon#about to read 5, iclass 22, count 0 2006.161.08:06:19.62#ibcon#read 5, iclass 22, count 0 2006.161.08:06:19.62#ibcon#about to read 6, iclass 22, count 0 2006.161.08:06:19.62#ibcon#read 6, iclass 22, count 0 2006.161.08:06:19.62#ibcon#end of sib2, iclass 22, count 0 2006.161.08:06:19.62#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:06:19.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:06:19.62#ibcon#[25=USB\r\n] 2006.161.08:06:19.62#ibcon#*before write, iclass 22, count 0 2006.161.08:06:19.62#ibcon#enter sib2, iclass 22, count 0 2006.161.08:06:19.62#ibcon#flushed, iclass 22, count 0 2006.161.08:06:19.62#ibcon#about to write, iclass 22, count 0 2006.161.08:06:19.62#ibcon#wrote, iclass 22, count 0 2006.161.08:06:19.62#ibcon#about to read 3, iclass 22, count 0 2006.161.08:06:19.65#ibcon#read 3, iclass 22, count 0 2006.161.08:06:19.65#ibcon#about to read 4, iclass 22, count 0 2006.161.08:06:19.65#ibcon#read 4, iclass 22, count 0 2006.161.08:06:19.65#ibcon#about to read 5, iclass 22, count 0 2006.161.08:06:19.65#ibcon#read 5, iclass 22, count 0 2006.161.08:06:19.65#ibcon#about to read 6, iclass 22, count 0 2006.161.08:06:19.65#ibcon#read 6, iclass 22, count 0 2006.161.08:06:19.65#ibcon#end of sib2, iclass 22, count 0 2006.161.08:06:19.65#ibcon#*after write, iclass 22, count 0 2006.161.08:06:19.65#ibcon#*before return 0, iclass 22, count 0 2006.161.08:06:19.65#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:19.65#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:19.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:06:19.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:06:19.65$vc4f8/valo=4,832.99 2006.161.08:06:19.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:06:19.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:06:19.65#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:19.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:19.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:19.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:19.65#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:06:19.65#ibcon#first serial, iclass 24, count 0 2006.161.08:06:19.65#ibcon#enter sib2, iclass 24, count 0 2006.161.08:06:19.65#ibcon#flushed, iclass 24, count 0 2006.161.08:06:19.65#ibcon#about to write, iclass 24, count 0 2006.161.08:06:19.65#ibcon#wrote, iclass 24, count 0 2006.161.08:06:19.65#ibcon#about to read 3, iclass 24, count 0 2006.161.08:06:19.67#ibcon#read 3, iclass 24, count 0 2006.161.08:06:19.67#ibcon#about to read 4, iclass 24, count 0 2006.161.08:06:19.67#ibcon#read 4, iclass 24, count 0 2006.161.08:06:19.67#ibcon#about to read 5, iclass 24, count 0 2006.161.08:06:19.67#ibcon#read 5, iclass 24, count 0 2006.161.08:06:19.67#ibcon#about to read 6, iclass 24, count 0 2006.161.08:06:19.67#ibcon#read 6, iclass 24, count 0 2006.161.08:06:19.67#ibcon#end of sib2, iclass 24, count 0 2006.161.08:06:19.67#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:06:19.67#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:06:19.67#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:06:19.67#ibcon#*before write, iclass 24, count 0 2006.161.08:06:19.67#ibcon#enter sib2, iclass 24, count 0 2006.161.08:06:19.67#ibcon#flushed, iclass 24, count 0 2006.161.08:06:19.67#ibcon#about to write, iclass 24, count 0 2006.161.08:06:19.67#ibcon#wrote, iclass 24, count 0 2006.161.08:06:19.67#ibcon#about to read 3, iclass 24, count 0 2006.161.08:06:19.71#ibcon#read 3, iclass 24, count 0 2006.161.08:06:19.71#ibcon#about to read 4, iclass 24, count 0 2006.161.08:06:19.71#ibcon#read 4, iclass 24, count 0 2006.161.08:06:19.71#ibcon#about to read 5, iclass 24, count 0 2006.161.08:06:19.71#ibcon#read 5, iclass 24, count 0 2006.161.08:06:19.71#ibcon#about to read 6, iclass 24, count 0 2006.161.08:06:19.71#ibcon#read 6, iclass 24, count 0 2006.161.08:06:19.71#ibcon#end of sib2, iclass 24, count 0 2006.161.08:06:19.71#ibcon#*after write, iclass 24, count 0 2006.161.08:06:19.71#ibcon#*before return 0, iclass 24, count 0 2006.161.08:06:19.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:19.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:19.71#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:06:19.71#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:06:19.71$vc4f8/va=4,7 2006.161.08:06:19.71#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:06:19.71#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:06:19.71#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:19.71#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:19.77#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:19.77#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:19.77#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:06:19.77#ibcon#first serial, iclass 26, count 2 2006.161.08:06:19.77#ibcon#enter sib2, iclass 26, count 2 2006.161.08:06:19.77#ibcon#flushed, iclass 26, count 2 2006.161.08:06:19.77#ibcon#about to write, iclass 26, count 2 2006.161.08:06:19.77#ibcon#wrote, iclass 26, count 2 2006.161.08:06:19.77#ibcon#about to read 3, iclass 26, count 2 2006.161.08:06:19.79#ibcon#read 3, iclass 26, count 2 2006.161.08:06:19.79#ibcon#about to read 4, iclass 26, count 2 2006.161.08:06:19.79#ibcon#read 4, iclass 26, count 2 2006.161.08:06:19.79#ibcon#about to read 5, iclass 26, count 2 2006.161.08:06:19.79#ibcon#read 5, iclass 26, count 2 2006.161.08:06:19.79#ibcon#about to read 6, iclass 26, count 2 2006.161.08:06:19.79#ibcon#read 6, iclass 26, count 2 2006.161.08:06:19.79#ibcon#end of sib2, iclass 26, count 2 2006.161.08:06:19.79#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:06:19.79#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:06:19.79#ibcon#[25=AT04-07\r\n] 2006.161.08:06:19.79#ibcon#*before write, iclass 26, count 2 2006.161.08:06:19.79#ibcon#enter sib2, iclass 26, count 2 2006.161.08:06:19.79#ibcon#flushed, iclass 26, count 2 2006.161.08:06:19.79#ibcon#about to write, iclass 26, count 2 2006.161.08:06:19.79#ibcon#wrote, iclass 26, count 2 2006.161.08:06:19.79#ibcon#about to read 3, iclass 26, count 2 2006.161.08:06:19.82#ibcon#read 3, iclass 26, count 2 2006.161.08:06:19.82#ibcon#about to read 4, iclass 26, count 2 2006.161.08:06:19.82#ibcon#read 4, iclass 26, count 2 2006.161.08:06:19.82#ibcon#about to read 5, iclass 26, count 2 2006.161.08:06:19.82#ibcon#read 5, iclass 26, count 2 2006.161.08:06:19.82#ibcon#about to read 6, iclass 26, count 2 2006.161.08:06:19.82#ibcon#read 6, iclass 26, count 2 2006.161.08:06:19.82#ibcon#end of sib2, iclass 26, count 2 2006.161.08:06:19.82#ibcon#*after write, iclass 26, count 2 2006.161.08:06:19.82#ibcon#*before return 0, iclass 26, count 2 2006.161.08:06:19.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:19.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:19.82#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:06:19.82#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:19.82#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:19.94#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:19.94#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:19.94#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:06:19.94#ibcon#first serial, iclass 26, count 0 2006.161.08:06:19.94#ibcon#enter sib2, iclass 26, count 0 2006.161.08:06:19.94#ibcon#flushed, iclass 26, count 0 2006.161.08:06:19.94#ibcon#about to write, iclass 26, count 0 2006.161.08:06:19.94#ibcon#wrote, iclass 26, count 0 2006.161.08:06:19.94#ibcon#about to read 3, iclass 26, count 0 2006.161.08:06:19.96#ibcon#read 3, iclass 26, count 0 2006.161.08:06:19.96#ibcon#about to read 4, iclass 26, count 0 2006.161.08:06:19.96#ibcon#read 4, iclass 26, count 0 2006.161.08:06:19.96#ibcon#about to read 5, iclass 26, count 0 2006.161.08:06:19.96#ibcon#read 5, iclass 26, count 0 2006.161.08:06:19.96#ibcon#about to read 6, iclass 26, count 0 2006.161.08:06:19.96#ibcon#read 6, iclass 26, count 0 2006.161.08:06:19.96#ibcon#end of sib2, iclass 26, count 0 2006.161.08:06:19.96#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:06:19.96#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:06:19.96#ibcon#[25=USB\r\n] 2006.161.08:06:19.96#ibcon#*before write, iclass 26, count 0 2006.161.08:06:19.96#ibcon#enter sib2, iclass 26, count 0 2006.161.08:06:19.96#ibcon#flushed, iclass 26, count 0 2006.161.08:06:19.96#ibcon#about to write, iclass 26, count 0 2006.161.08:06:19.96#ibcon#wrote, iclass 26, count 0 2006.161.08:06:19.96#ibcon#about to read 3, iclass 26, count 0 2006.161.08:06:19.99#ibcon#read 3, iclass 26, count 0 2006.161.08:06:19.99#ibcon#about to read 4, iclass 26, count 0 2006.161.08:06:19.99#ibcon#read 4, iclass 26, count 0 2006.161.08:06:19.99#ibcon#about to read 5, iclass 26, count 0 2006.161.08:06:19.99#ibcon#read 5, iclass 26, count 0 2006.161.08:06:19.99#ibcon#about to read 6, iclass 26, count 0 2006.161.08:06:19.99#ibcon#read 6, iclass 26, count 0 2006.161.08:06:19.99#ibcon#end of sib2, iclass 26, count 0 2006.161.08:06:19.99#ibcon#*after write, iclass 26, count 0 2006.161.08:06:19.99#ibcon#*before return 0, iclass 26, count 0 2006.161.08:06:19.99#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:19.99#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:19.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:06:19.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:06:19.99$vc4f8/valo=5,652.99 2006.161.08:06:19.99#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:06:19.99#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:06:19.99#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:19.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:06:19.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:06:19.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:06:19.99#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:06:19.99#ibcon#first serial, iclass 28, count 0 2006.161.08:06:19.99#ibcon#enter sib2, iclass 28, count 0 2006.161.08:06:19.99#ibcon#flushed, iclass 28, count 0 2006.161.08:06:19.99#ibcon#about to write, iclass 28, count 0 2006.161.08:06:19.99#ibcon#wrote, iclass 28, count 0 2006.161.08:06:19.99#ibcon#about to read 3, iclass 28, count 0 2006.161.08:06:20.01#ibcon#read 3, iclass 28, count 0 2006.161.08:06:20.01#ibcon#about to read 4, iclass 28, count 0 2006.161.08:06:20.01#ibcon#read 4, iclass 28, count 0 2006.161.08:06:20.01#ibcon#about to read 5, iclass 28, count 0 2006.161.08:06:20.01#ibcon#read 5, iclass 28, count 0 2006.161.08:06:20.01#ibcon#about to read 6, iclass 28, count 0 2006.161.08:06:20.01#ibcon#read 6, iclass 28, count 0 2006.161.08:06:20.01#ibcon#end of sib2, iclass 28, count 0 2006.161.08:06:20.01#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:06:20.01#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:06:20.01#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:06:20.01#ibcon#*before write, iclass 28, count 0 2006.161.08:06:20.01#ibcon#enter sib2, iclass 28, count 0 2006.161.08:06:20.01#ibcon#flushed, iclass 28, count 0 2006.161.08:06:20.01#ibcon#about to write, iclass 28, count 0 2006.161.08:06:20.01#ibcon#wrote, iclass 28, count 0 2006.161.08:06:20.01#ibcon#about to read 3, iclass 28, count 0 2006.161.08:06:20.05#ibcon#read 3, iclass 28, count 0 2006.161.08:06:20.05#ibcon#about to read 4, iclass 28, count 0 2006.161.08:06:20.05#ibcon#read 4, iclass 28, count 0 2006.161.08:06:20.05#ibcon#about to read 5, iclass 28, count 0 2006.161.08:06:20.05#ibcon#read 5, iclass 28, count 0 2006.161.08:06:20.05#ibcon#about to read 6, iclass 28, count 0 2006.161.08:06:20.05#ibcon#read 6, iclass 28, count 0 2006.161.08:06:20.05#ibcon#end of sib2, iclass 28, count 0 2006.161.08:06:20.05#ibcon#*after write, iclass 28, count 0 2006.161.08:06:20.05#ibcon#*before return 0, iclass 28, count 0 2006.161.08:06:20.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:06:20.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:06:20.05#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:06:20.05#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:06:20.05$vc4f8/va=5,7 2006.161.08:06:20.05#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.08:06:20.05#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.08:06:20.05#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:20.05#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:06:20.12#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:06:20.12#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:06:20.12#ibcon#enter wrdev, iclass 30, count 2 2006.161.08:06:20.12#ibcon#first serial, iclass 30, count 2 2006.161.08:06:20.12#ibcon#enter sib2, iclass 30, count 2 2006.161.08:06:20.12#ibcon#flushed, iclass 30, count 2 2006.161.08:06:20.12#ibcon#about to write, iclass 30, count 2 2006.161.08:06:20.12#ibcon#wrote, iclass 30, count 2 2006.161.08:06:20.12#ibcon#about to read 3, iclass 30, count 2 2006.161.08:06:20.14#ibcon#read 3, iclass 30, count 2 2006.161.08:06:20.14#ibcon#about to read 4, iclass 30, count 2 2006.161.08:06:20.14#ibcon#read 4, iclass 30, count 2 2006.161.08:06:20.14#ibcon#about to read 5, iclass 30, count 2 2006.161.08:06:20.14#ibcon#read 5, iclass 30, count 2 2006.161.08:06:20.14#ibcon#about to read 6, iclass 30, count 2 2006.161.08:06:20.14#ibcon#read 6, iclass 30, count 2 2006.161.08:06:20.14#ibcon#end of sib2, iclass 30, count 2 2006.161.08:06:20.14#ibcon#*mode == 0, iclass 30, count 2 2006.161.08:06:20.14#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.08:06:20.14#ibcon#[25=AT05-07\r\n] 2006.161.08:06:20.14#ibcon#*before write, iclass 30, count 2 2006.161.08:06:20.14#ibcon#enter sib2, iclass 30, count 2 2006.161.08:06:20.14#ibcon#flushed, iclass 30, count 2 2006.161.08:06:20.14#ibcon#about to write, iclass 30, count 2 2006.161.08:06:20.14#ibcon#wrote, iclass 30, count 2 2006.161.08:06:20.14#ibcon#about to read 3, iclass 30, count 2 2006.161.08:06:20.16#ibcon#read 3, iclass 30, count 2 2006.161.08:06:20.16#ibcon#about to read 4, iclass 30, count 2 2006.161.08:06:20.16#ibcon#read 4, iclass 30, count 2 2006.161.08:06:20.16#ibcon#about to read 5, iclass 30, count 2 2006.161.08:06:20.16#ibcon#read 5, iclass 30, count 2 2006.161.08:06:20.16#ibcon#about to read 6, iclass 30, count 2 2006.161.08:06:20.16#ibcon#read 6, iclass 30, count 2 2006.161.08:06:20.16#ibcon#end of sib2, iclass 30, count 2 2006.161.08:06:20.16#ibcon#*after write, iclass 30, count 2 2006.161.08:06:20.16#ibcon#*before return 0, iclass 30, count 2 2006.161.08:06:20.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:06:20.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:06:20.16#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.08:06:20.16#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:20.16#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:06:20.28#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:06:20.28#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:06:20.28#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:06:20.28#ibcon#first serial, iclass 30, count 0 2006.161.08:06:20.28#ibcon#enter sib2, iclass 30, count 0 2006.161.08:06:20.28#ibcon#flushed, iclass 30, count 0 2006.161.08:06:20.28#ibcon#about to write, iclass 30, count 0 2006.161.08:06:20.28#ibcon#wrote, iclass 30, count 0 2006.161.08:06:20.28#ibcon#about to read 3, iclass 30, count 0 2006.161.08:06:20.30#ibcon#read 3, iclass 30, count 0 2006.161.08:06:20.30#ibcon#about to read 4, iclass 30, count 0 2006.161.08:06:20.30#ibcon#read 4, iclass 30, count 0 2006.161.08:06:20.30#ibcon#about to read 5, iclass 30, count 0 2006.161.08:06:20.30#ibcon#read 5, iclass 30, count 0 2006.161.08:06:20.30#ibcon#about to read 6, iclass 30, count 0 2006.161.08:06:20.30#ibcon#read 6, iclass 30, count 0 2006.161.08:06:20.30#ibcon#end of sib2, iclass 30, count 0 2006.161.08:06:20.30#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:06:20.30#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:06:20.30#ibcon#[25=USB\r\n] 2006.161.08:06:20.30#ibcon#*before write, iclass 30, count 0 2006.161.08:06:20.30#ibcon#enter sib2, iclass 30, count 0 2006.161.08:06:20.30#ibcon#flushed, iclass 30, count 0 2006.161.08:06:20.30#ibcon#about to write, iclass 30, count 0 2006.161.08:06:20.30#ibcon#wrote, iclass 30, count 0 2006.161.08:06:20.30#ibcon#about to read 3, iclass 30, count 0 2006.161.08:06:20.33#ibcon#read 3, iclass 30, count 0 2006.161.08:06:20.33#ibcon#about to read 4, iclass 30, count 0 2006.161.08:06:20.33#ibcon#read 4, iclass 30, count 0 2006.161.08:06:20.33#ibcon#about to read 5, iclass 30, count 0 2006.161.08:06:20.33#ibcon#read 5, iclass 30, count 0 2006.161.08:06:20.33#ibcon#about to read 6, iclass 30, count 0 2006.161.08:06:20.33#ibcon#read 6, iclass 30, count 0 2006.161.08:06:20.33#ibcon#end of sib2, iclass 30, count 0 2006.161.08:06:20.33#ibcon#*after write, iclass 30, count 0 2006.161.08:06:20.33#ibcon#*before return 0, iclass 30, count 0 2006.161.08:06:20.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:06:20.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:06:20.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:06:20.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:06:20.33$vc4f8/valo=6,772.99 2006.161.08:06:20.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.08:06:20.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.08:06:20.33#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:20.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:20.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:20.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:20.33#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:06:20.33#ibcon#first serial, iclass 32, count 0 2006.161.08:06:20.33#ibcon#enter sib2, iclass 32, count 0 2006.161.08:06:20.33#ibcon#flushed, iclass 32, count 0 2006.161.08:06:20.33#ibcon#about to write, iclass 32, count 0 2006.161.08:06:20.33#ibcon#wrote, iclass 32, count 0 2006.161.08:06:20.33#ibcon#about to read 3, iclass 32, count 0 2006.161.08:06:20.35#ibcon#read 3, iclass 32, count 0 2006.161.08:06:20.35#ibcon#about to read 4, iclass 32, count 0 2006.161.08:06:20.35#ibcon#read 4, iclass 32, count 0 2006.161.08:06:20.35#ibcon#about to read 5, iclass 32, count 0 2006.161.08:06:20.35#ibcon#read 5, iclass 32, count 0 2006.161.08:06:20.35#ibcon#about to read 6, iclass 32, count 0 2006.161.08:06:20.35#ibcon#read 6, iclass 32, count 0 2006.161.08:06:20.35#ibcon#end of sib2, iclass 32, count 0 2006.161.08:06:20.35#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:06:20.35#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:06:20.35#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:06:20.35#ibcon#*before write, iclass 32, count 0 2006.161.08:06:20.35#ibcon#enter sib2, iclass 32, count 0 2006.161.08:06:20.35#ibcon#flushed, iclass 32, count 0 2006.161.08:06:20.35#ibcon#about to write, iclass 32, count 0 2006.161.08:06:20.35#ibcon#wrote, iclass 32, count 0 2006.161.08:06:20.35#ibcon#about to read 3, iclass 32, count 0 2006.161.08:06:20.39#ibcon#read 3, iclass 32, count 0 2006.161.08:06:20.39#ibcon#about to read 4, iclass 32, count 0 2006.161.08:06:20.39#ibcon#read 4, iclass 32, count 0 2006.161.08:06:20.39#ibcon#about to read 5, iclass 32, count 0 2006.161.08:06:20.39#ibcon#read 5, iclass 32, count 0 2006.161.08:06:20.39#ibcon#about to read 6, iclass 32, count 0 2006.161.08:06:20.39#ibcon#read 6, iclass 32, count 0 2006.161.08:06:20.39#ibcon#end of sib2, iclass 32, count 0 2006.161.08:06:20.39#ibcon#*after write, iclass 32, count 0 2006.161.08:06:20.39#ibcon#*before return 0, iclass 32, count 0 2006.161.08:06:20.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:20.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:20.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:06:20.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:06:20.39$vc4f8/va=6,6 2006.161.08:06:20.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.08:06:20.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.08:06:20.39#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:20.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:20.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:20.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:20.45#ibcon#enter wrdev, iclass 34, count 2 2006.161.08:06:20.45#ibcon#first serial, iclass 34, count 2 2006.161.08:06:20.45#ibcon#enter sib2, iclass 34, count 2 2006.161.08:06:20.45#ibcon#flushed, iclass 34, count 2 2006.161.08:06:20.45#ibcon#about to write, iclass 34, count 2 2006.161.08:06:20.45#ibcon#wrote, iclass 34, count 2 2006.161.08:06:20.45#ibcon#about to read 3, iclass 34, count 2 2006.161.08:06:20.48#ibcon#read 3, iclass 34, count 2 2006.161.08:06:20.48#ibcon#about to read 4, iclass 34, count 2 2006.161.08:06:20.48#ibcon#read 4, iclass 34, count 2 2006.161.08:06:20.48#ibcon#about to read 5, iclass 34, count 2 2006.161.08:06:20.48#ibcon#read 5, iclass 34, count 2 2006.161.08:06:20.48#ibcon#about to read 6, iclass 34, count 2 2006.161.08:06:20.48#ibcon#read 6, iclass 34, count 2 2006.161.08:06:20.48#ibcon#end of sib2, iclass 34, count 2 2006.161.08:06:20.48#ibcon#*mode == 0, iclass 34, count 2 2006.161.08:06:20.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.08:06:20.48#ibcon#[25=AT06-06\r\n] 2006.161.08:06:20.48#ibcon#*before write, iclass 34, count 2 2006.161.08:06:20.48#ibcon#enter sib2, iclass 34, count 2 2006.161.08:06:20.48#ibcon#flushed, iclass 34, count 2 2006.161.08:06:20.48#ibcon#about to write, iclass 34, count 2 2006.161.08:06:20.48#ibcon#wrote, iclass 34, count 2 2006.161.08:06:20.48#ibcon#about to read 3, iclass 34, count 2 2006.161.08:06:20.50#ibcon#read 3, iclass 34, count 2 2006.161.08:06:20.50#ibcon#about to read 4, iclass 34, count 2 2006.161.08:06:20.50#ibcon#read 4, iclass 34, count 2 2006.161.08:06:20.50#ibcon#about to read 5, iclass 34, count 2 2006.161.08:06:20.50#ibcon#read 5, iclass 34, count 2 2006.161.08:06:20.50#ibcon#about to read 6, iclass 34, count 2 2006.161.08:06:20.50#ibcon#read 6, iclass 34, count 2 2006.161.08:06:20.50#ibcon#end of sib2, iclass 34, count 2 2006.161.08:06:20.50#ibcon#*after write, iclass 34, count 2 2006.161.08:06:20.50#ibcon#*before return 0, iclass 34, count 2 2006.161.08:06:20.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:20.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:20.50#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.08:06:20.50#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:20.50#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:20.62#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:20.62#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:20.62#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:06:20.62#ibcon#first serial, iclass 34, count 0 2006.161.08:06:20.62#ibcon#enter sib2, iclass 34, count 0 2006.161.08:06:20.62#ibcon#flushed, iclass 34, count 0 2006.161.08:06:20.62#ibcon#about to write, iclass 34, count 0 2006.161.08:06:20.62#ibcon#wrote, iclass 34, count 0 2006.161.08:06:20.62#ibcon#about to read 3, iclass 34, count 0 2006.161.08:06:20.64#ibcon#read 3, iclass 34, count 0 2006.161.08:06:20.64#ibcon#about to read 4, iclass 34, count 0 2006.161.08:06:20.64#ibcon#read 4, iclass 34, count 0 2006.161.08:06:20.64#ibcon#about to read 5, iclass 34, count 0 2006.161.08:06:20.64#ibcon#read 5, iclass 34, count 0 2006.161.08:06:20.64#ibcon#about to read 6, iclass 34, count 0 2006.161.08:06:20.64#ibcon#read 6, iclass 34, count 0 2006.161.08:06:20.64#ibcon#end of sib2, iclass 34, count 0 2006.161.08:06:20.64#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:06:20.64#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:06:20.64#ibcon#[25=USB\r\n] 2006.161.08:06:20.64#ibcon#*before write, iclass 34, count 0 2006.161.08:06:20.64#ibcon#enter sib2, iclass 34, count 0 2006.161.08:06:20.64#ibcon#flushed, iclass 34, count 0 2006.161.08:06:20.64#ibcon#about to write, iclass 34, count 0 2006.161.08:06:20.64#ibcon#wrote, iclass 34, count 0 2006.161.08:06:20.64#ibcon#about to read 3, iclass 34, count 0 2006.161.08:06:20.67#ibcon#read 3, iclass 34, count 0 2006.161.08:06:20.67#ibcon#about to read 4, iclass 34, count 0 2006.161.08:06:20.67#ibcon#read 4, iclass 34, count 0 2006.161.08:06:20.67#ibcon#about to read 5, iclass 34, count 0 2006.161.08:06:20.67#ibcon#read 5, iclass 34, count 0 2006.161.08:06:20.67#ibcon#about to read 6, iclass 34, count 0 2006.161.08:06:20.67#ibcon#read 6, iclass 34, count 0 2006.161.08:06:20.67#ibcon#end of sib2, iclass 34, count 0 2006.161.08:06:20.67#ibcon#*after write, iclass 34, count 0 2006.161.08:06:20.67#ibcon#*before return 0, iclass 34, count 0 2006.161.08:06:20.67#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:20.67#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:20.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:06:20.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:06:20.67$vc4f8/valo=7,832.99 2006.161.08:06:20.67#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:06:20.67#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:06:20.67#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:20.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:20.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:20.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:20.67#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:06:20.67#ibcon#first serial, iclass 36, count 0 2006.161.08:06:20.67#ibcon#enter sib2, iclass 36, count 0 2006.161.08:06:20.67#ibcon#flushed, iclass 36, count 0 2006.161.08:06:20.67#ibcon#about to write, iclass 36, count 0 2006.161.08:06:20.67#ibcon#wrote, iclass 36, count 0 2006.161.08:06:20.67#ibcon#about to read 3, iclass 36, count 0 2006.161.08:06:20.69#ibcon#read 3, iclass 36, count 0 2006.161.08:06:20.69#ibcon#about to read 4, iclass 36, count 0 2006.161.08:06:20.69#ibcon#read 4, iclass 36, count 0 2006.161.08:06:20.69#ibcon#about to read 5, iclass 36, count 0 2006.161.08:06:20.69#ibcon#read 5, iclass 36, count 0 2006.161.08:06:20.69#ibcon#about to read 6, iclass 36, count 0 2006.161.08:06:20.69#ibcon#read 6, iclass 36, count 0 2006.161.08:06:20.69#ibcon#end of sib2, iclass 36, count 0 2006.161.08:06:20.69#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:06:20.69#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:06:20.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:06:20.69#ibcon#*before write, iclass 36, count 0 2006.161.08:06:20.69#ibcon#enter sib2, iclass 36, count 0 2006.161.08:06:20.69#ibcon#flushed, iclass 36, count 0 2006.161.08:06:20.69#ibcon#about to write, iclass 36, count 0 2006.161.08:06:20.69#ibcon#wrote, iclass 36, count 0 2006.161.08:06:20.69#ibcon#about to read 3, iclass 36, count 0 2006.161.08:06:20.73#ibcon#read 3, iclass 36, count 0 2006.161.08:06:20.73#ibcon#about to read 4, iclass 36, count 0 2006.161.08:06:20.73#ibcon#read 4, iclass 36, count 0 2006.161.08:06:20.73#ibcon#about to read 5, iclass 36, count 0 2006.161.08:06:20.73#ibcon#read 5, iclass 36, count 0 2006.161.08:06:20.73#ibcon#about to read 6, iclass 36, count 0 2006.161.08:06:20.73#ibcon#read 6, iclass 36, count 0 2006.161.08:06:20.73#ibcon#end of sib2, iclass 36, count 0 2006.161.08:06:20.73#ibcon#*after write, iclass 36, count 0 2006.161.08:06:20.73#ibcon#*before return 0, iclass 36, count 0 2006.161.08:06:20.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:20.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:20.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:06:20.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:06:20.73$vc4f8/va=7,6 2006.161.08:06:20.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.08:06:20.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.08:06:20.73#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:20.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:20.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:20.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:20.80#ibcon#enter wrdev, iclass 38, count 2 2006.161.08:06:20.80#ibcon#first serial, iclass 38, count 2 2006.161.08:06:20.80#ibcon#enter sib2, iclass 38, count 2 2006.161.08:06:20.80#ibcon#flushed, iclass 38, count 2 2006.161.08:06:20.80#ibcon#about to write, iclass 38, count 2 2006.161.08:06:20.80#ibcon#wrote, iclass 38, count 2 2006.161.08:06:20.80#ibcon#about to read 3, iclass 38, count 2 2006.161.08:06:20.82#ibcon#read 3, iclass 38, count 2 2006.161.08:06:20.82#ibcon#about to read 4, iclass 38, count 2 2006.161.08:06:20.82#ibcon#read 4, iclass 38, count 2 2006.161.08:06:20.82#ibcon#about to read 5, iclass 38, count 2 2006.161.08:06:20.82#ibcon#read 5, iclass 38, count 2 2006.161.08:06:20.82#ibcon#about to read 6, iclass 38, count 2 2006.161.08:06:20.82#ibcon#read 6, iclass 38, count 2 2006.161.08:06:20.82#ibcon#end of sib2, iclass 38, count 2 2006.161.08:06:20.82#ibcon#*mode == 0, iclass 38, count 2 2006.161.08:06:20.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.08:06:20.82#ibcon#[25=AT07-06\r\n] 2006.161.08:06:20.82#ibcon#*before write, iclass 38, count 2 2006.161.08:06:20.82#ibcon#enter sib2, iclass 38, count 2 2006.161.08:06:20.82#ibcon#flushed, iclass 38, count 2 2006.161.08:06:20.82#ibcon#about to write, iclass 38, count 2 2006.161.08:06:20.82#ibcon#wrote, iclass 38, count 2 2006.161.08:06:20.82#ibcon#about to read 3, iclass 38, count 2 2006.161.08:06:20.84#ibcon#read 3, iclass 38, count 2 2006.161.08:06:20.84#ibcon#about to read 4, iclass 38, count 2 2006.161.08:06:20.84#ibcon#read 4, iclass 38, count 2 2006.161.08:06:20.84#ibcon#about to read 5, iclass 38, count 2 2006.161.08:06:20.84#ibcon#read 5, iclass 38, count 2 2006.161.08:06:20.84#ibcon#about to read 6, iclass 38, count 2 2006.161.08:06:20.84#ibcon#read 6, iclass 38, count 2 2006.161.08:06:20.84#ibcon#end of sib2, iclass 38, count 2 2006.161.08:06:20.84#ibcon#*after write, iclass 38, count 2 2006.161.08:06:20.84#ibcon#*before return 0, iclass 38, count 2 2006.161.08:06:20.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:20.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:20.84#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.08:06:20.84#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:20.84#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:06:20.96#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:06:20.96#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:06:20.96#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:06:20.96#ibcon#first serial, iclass 38, count 0 2006.161.08:06:20.96#ibcon#enter sib2, iclass 38, count 0 2006.161.08:06:20.96#ibcon#flushed, iclass 38, count 0 2006.161.08:06:20.96#ibcon#about to write, iclass 38, count 0 2006.161.08:06:20.96#ibcon#wrote, iclass 38, count 0 2006.161.08:06:20.96#ibcon#about to read 3, iclass 38, count 0 2006.161.08:06:20.98#ibcon#read 3, iclass 38, count 0 2006.161.08:06:20.98#ibcon#about to read 4, iclass 38, count 0 2006.161.08:06:20.98#ibcon#read 4, iclass 38, count 0 2006.161.08:06:20.98#ibcon#about to read 5, iclass 38, count 0 2006.161.08:06:20.98#ibcon#read 5, iclass 38, count 0 2006.161.08:06:20.98#ibcon#about to read 6, iclass 38, count 0 2006.161.08:06:20.98#ibcon#read 6, iclass 38, count 0 2006.161.08:06:20.98#ibcon#end of sib2, iclass 38, count 0 2006.161.08:06:20.98#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:06:20.98#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:06:20.98#ibcon#[25=USB\r\n] 2006.161.08:06:20.98#ibcon#*before write, iclass 38, count 0 2006.161.08:06:20.98#ibcon#enter sib2, iclass 38, count 0 2006.161.08:06:20.98#ibcon#flushed, iclass 38, count 0 2006.161.08:06:20.98#ibcon#about to write, iclass 38, count 0 2006.161.08:06:20.98#ibcon#wrote, iclass 38, count 0 2006.161.08:06:20.98#ibcon#about to read 3, iclass 38, count 0 2006.161.08:06:21.01#ibcon#read 3, iclass 38, count 0 2006.161.08:06:21.01#ibcon#about to read 4, iclass 38, count 0 2006.161.08:06:21.01#ibcon#read 4, iclass 38, count 0 2006.161.08:06:21.01#ibcon#about to read 5, iclass 38, count 0 2006.161.08:06:21.01#ibcon#read 5, iclass 38, count 0 2006.161.08:06:21.01#ibcon#about to read 6, iclass 38, count 0 2006.161.08:06:21.01#ibcon#read 6, iclass 38, count 0 2006.161.08:06:21.01#ibcon#end of sib2, iclass 38, count 0 2006.161.08:06:21.01#ibcon#*after write, iclass 38, count 0 2006.161.08:06:21.01#ibcon#*before return 0, iclass 38, count 0 2006.161.08:06:21.01#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:06:21.01#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:06:21.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:06:21.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:06:21.01$vc4f8/valo=8,852.99 2006.161.08:06:21.01#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.08:06:21.01#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.08:06:21.01#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:21.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:06:21.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:06:21.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:06:21.01#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:06:21.01#ibcon#first serial, iclass 40, count 0 2006.161.08:06:21.01#ibcon#enter sib2, iclass 40, count 0 2006.161.08:06:21.01#ibcon#flushed, iclass 40, count 0 2006.161.08:06:21.01#ibcon#about to write, iclass 40, count 0 2006.161.08:06:21.01#ibcon#wrote, iclass 40, count 0 2006.161.08:06:21.01#ibcon#about to read 3, iclass 40, count 0 2006.161.08:06:21.03#ibcon#read 3, iclass 40, count 0 2006.161.08:06:21.03#ibcon#about to read 4, iclass 40, count 0 2006.161.08:06:21.03#ibcon#read 4, iclass 40, count 0 2006.161.08:06:21.03#ibcon#about to read 5, iclass 40, count 0 2006.161.08:06:21.03#ibcon#read 5, iclass 40, count 0 2006.161.08:06:21.03#ibcon#about to read 6, iclass 40, count 0 2006.161.08:06:21.03#ibcon#read 6, iclass 40, count 0 2006.161.08:06:21.03#ibcon#end of sib2, iclass 40, count 0 2006.161.08:06:21.03#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:06:21.03#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:06:21.03#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:06:21.03#ibcon#*before write, iclass 40, count 0 2006.161.08:06:21.03#ibcon#enter sib2, iclass 40, count 0 2006.161.08:06:21.03#ibcon#flushed, iclass 40, count 0 2006.161.08:06:21.03#ibcon#about to write, iclass 40, count 0 2006.161.08:06:21.03#ibcon#wrote, iclass 40, count 0 2006.161.08:06:21.03#ibcon#about to read 3, iclass 40, count 0 2006.161.08:06:21.07#ibcon#read 3, iclass 40, count 0 2006.161.08:06:21.07#ibcon#about to read 4, iclass 40, count 0 2006.161.08:06:21.07#ibcon#read 4, iclass 40, count 0 2006.161.08:06:21.07#ibcon#about to read 5, iclass 40, count 0 2006.161.08:06:21.07#ibcon#read 5, iclass 40, count 0 2006.161.08:06:21.07#ibcon#about to read 6, iclass 40, count 0 2006.161.08:06:21.07#ibcon#read 6, iclass 40, count 0 2006.161.08:06:21.07#ibcon#end of sib2, iclass 40, count 0 2006.161.08:06:21.07#ibcon#*after write, iclass 40, count 0 2006.161.08:06:21.07#ibcon#*before return 0, iclass 40, count 0 2006.161.08:06:21.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:06:21.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:06:21.07#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:06:21.07#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:06:21.07$vc4f8/va=8,7 2006.161.08:06:21.07#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.08:06:21.07#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.08:06:21.07#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:21.07#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:06:21.13#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:06:21.13#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:06:21.13#ibcon#enter wrdev, iclass 4, count 2 2006.161.08:06:21.13#ibcon#first serial, iclass 4, count 2 2006.161.08:06:21.13#ibcon#enter sib2, iclass 4, count 2 2006.161.08:06:21.13#ibcon#flushed, iclass 4, count 2 2006.161.08:06:21.13#ibcon#about to write, iclass 4, count 2 2006.161.08:06:21.13#ibcon#wrote, iclass 4, count 2 2006.161.08:06:21.13#ibcon#about to read 3, iclass 4, count 2 2006.161.08:06:21.15#ibcon#read 3, iclass 4, count 2 2006.161.08:06:21.15#ibcon#about to read 4, iclass 4, count 2 2006.161.08:06:21.15#ibcon#read 4, iclass 4, count 2 2006.161.08:06:21.15#ibcon#about to read 5, iclass 4, count 2 2006.161.08:06:21.15#ibcon#read 5, iclass 4, count 2 2006.161.08:06:21.15#ibcon#about to read 6, iclass 4, count 2 2006.161.08:06:21.15#ibcon#read 6, iclass 4, count 2 2006.161.08:06:21.15#ibcon#end of sib2, iclass 4, count 2 2006.161.08:06:21.15#ibcon#*mode == 0, iclass 4, count 2 2006.161.08:06:21.15#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.08:06:21.15#ibcon#[25=AT08-07\r\n] 2006.161.08:06:21.15#ibcon#*before write, iclass 4, count 2 2006.161.08:06:21.15#ibcon#enter sib2, iclass 4, count 2 2006.161.08:06:21.15#ibcon#flushed, iclass 4, count 2 2006.161.08:06:21.15#ibcon#about to write, iclass 4, count 2 2006.161.08:06:21.15#ibcon#wrote, iclass 4, count 2 2006.161.08:06:21.15#ibcon#about to read 3, iclass 4, count 2 2006.161.08:06:21.18#ibcon#read 3, iclass 4, count 2 2006.161.08:06:21.18#ibcon#about to read 4, iclass 4, count 2 2006.161.08:06:21.18#ibcon#read 4, iclass 4, count 2 2006.161.08:06:21.18#ibcon#about to read 5, iclass 4, count 2 2006.161.08:06:21.18#ibcon#read 5, iclass 4, count 2 2006.161.08:06:21.18#ibcon#about to read 6, iclass 4, count 2 2006.161.08:06:21.18#ibcon#read 6, iclass 4, count 2 2006.161.08:06:21.18#ibcon#end of sib2, iclass 4, count 2 2006.161.08:06:21.18#ibcon#*after write, iclass 4, count 2 2006.161.08:06:21.18#ibcon#*before return 0, iclass 4, count 2 2006.161.08:06:21.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:06:21.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:06:21.18#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.08:06:21.18#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:21.18#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:06:21.30#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:06:21.30#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:06:21.30#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:06:21.30#ibcon#first serial, iclass 4, count 0 2006.161.08:06:21.30#ibcon#enter sib2, iclass 4, count 0 2006.161.08:06:21.30#ibcon#flushed, iclass 4, count 0 2006.161.08:06:21.30#ibcon#about to write, iclass 4, count 0 2006.161.08:06:21.30#ibcon#wrote, iclass 4, count 0 2006.161.08:06:21.30#ibcon#about to read 3, iclass 4, count 0 2006.161.08:06:21.32#ibcon#read 3, iclass 4, count 0 2006.161.08:06:21.32#ibcon#about to read 4, iclass 4, count 0 2006.161.08:06:21.32#ibcon#read 4, iclass 4, count 0 2006.161.08:06:21.32#ibcon#about to read 5, iclass 4, count 0 2006.161.08:06:21.32#ibcon#read 5, iclass 4, count 0 2006.161.08:06:21.32#ibcon#about to read 6, iclass 4, count 0 2006.161.08:06:21.32#ibcon#read 6, iclass 4, count 0 2006.161.08:06:21.32#ibcon#end of sib2, iclass 4, count 0 2006.161.08:06:21.32#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:06:21.32#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:06:21.32#ibcon#[25=USB\r\n] 2006.161.08:06:21.32#ibcon#*before write, iclass 4, count 0 2006.161.08:06:21.32#ibcon#enter sib2, iclass 4, count 0 2006.161.08:06:21.32#ibcon#flushed, iclass 4, count 0 2006.161.08:06:21.32#ibcon#about to write, iclass 4, count 0 2006.161.08:06:21.32#ibcon#wrote, iclass 4, count 0 2006.161.08:06:21.32#ibcon#about to read 3, iclass 4, count 0 2006.161.08:06:21.35#ibcon#read 3, iclass 4, count 0 2006.161.08:06:21.35#ibcon#about to read 4, iclass 4, count 0 2006.161.08:06:21.35#ibcon#read 4, iclass 4, count 0 2006.161.08:06:21.35#ibcon#about to read 5, iclass 4, count 0 2006.161.08:06:21.35#ibcon#read 5, iclass 4, count 0 2006.161.08:06:21.35#ibcon#about to read 6, iclass 4, count 0 2006.161.08:06:21.35#ibcon#read 6, iclass 4, count 0 2006.161.08:06:21.35#ibcon#end of sib2, iclass 4, count 0 2006.161.08:06:21.35#ibcon#*after write, iclass 4, count 0 2006.161.08:06:21.35#ibcon#*before return 0, iclass 4, count 0 2006.161.08:06:21.35#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:06:21.35#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:06:21.35#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:06:21.35#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:06:21.35$vc4f8/vblo=1,632.99 2006.161.08:06:21.35#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:06:21.35#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:06:21.35#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:21.35#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:06:21.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:06:21.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:06:21.35#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:06:21.35#ibcon#first serial, iclass 6, count 0 2006.161.08:06:21.35#ibcon#enter sib2, iclass 6, count 0 2006.161.08:06:21.35#ibcon#flushed, iclass 6, count 0 2006.161.08:06:21.35#ibcon#about to write, iclass 6, count 0 2006.161.08:06:21.35#ibcon#wrote, iclass 6, count 0 2006.161.08:06:21.35#ibcon#about to read 3, iclass 6, count 0 2006.161.08:06:21.38#ibcon#read 3, iclass 6, count 0 2006.161.08:06:21.38#ibcon#about to read 4, iclass 6, count 0 2006.161.08:06:21.38#ibcon#read 4, iclass 6, count 0 2006.161.08:06:21.38#ibcon#about to read 5, iclass 6, count 0 2006.161.08:06:21.38#ibcon#read 5, iclass 6, count 0 2006.161.08:06:21.38#ibcon#about to read 6, iclass 6, count 0 2006.161.08:06:21.38#ibcon#read 6, iclass 6, count 0 2006.161.08:06:21.38#ibcon#end of sib2, iclass 6, count 0 2006.161.08:06:21.38#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:06:21.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:06:21.38#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:06:21.38#ibcon#*before write, iclass 6, count 0 2006.161.08:06:21.38#ibcon#enter sib2, iclass 6, count 0 2006.161.08:06:21.38#ibcon#flushed, iclass 6, count 0 2006.161.08:06:21.38#ibcon#about to write, iclass 6, count 0 2006.161.08:06:21.38#ibcon#wrote, iclass 6, count 0 2006.161.08:06:21.38#ibcon#about to read 3, iclass 6, count 0 2006.161.08:06:21.42#ibcon#read 3, iclass 6, count 0 2006.161.08:06:21.42#ibcon#about to read 4, iclass 6, count 0 2006.161.08:06:21.42#ibcon#read 4, iclass 6, count 0 2006.161.08:06:21.42#ibcon#about to read 5, iclass 6, count 0 2006.161.08:06:21.42#ibcon#read 5, iclass 6, count 0 2006.161.08:06:21.42#ibcon#about to read 6, iclass 6, count 0 2006.161.08:06:21.42#ibcon#read 6, iclass 6, count 0 2006.161.08:06:21.42#ibcon#end of sib2, iclass 6, count 0 2006.161.08:06:21.42#ibcon#*after write, iclass 6, count 0 2006.161.08:06:21.42#ibcon#*before return 0, iclass 6, count 0 2006.161.08:06:21.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:06:21.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:06:21.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:06:21.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:06:21.42$vc4f8/vb=1,4 2006.161.08:06:21.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.08:06:21.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.08:06:21.42#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:21.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:06:21.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:06:21.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:06:21.42#ibcon#enter wrdev, iclass 10, count 2 2006.161.08:06:21.42#ibcon#first serial, iclass 10, count 2 2006.161.08:06:21.42#ibcon#enter sib2, iclass 10, count 2 2006.161.08:06:21.42#ibcon#flushed, iclass 10, count 2 2006.161.08:06:21.42#ibcon#about to write, iclass 10, count 2 2006.161.08:06:21.42#ibcon#wrote, iclass 10, count 2 2006.161.08:06:21.42#ibcon#about to read 3, iclass 10, count 2 2006.161.08:06:21.44#ibcon#read 3, iclass 10, count 2 2006.161.08:06:21.44#ibcon#about to read 4, iclass 10, count 2 2006.161.08:06:21.44#ibcon#read 4, iclass 10, count 2 2006.161.08:06:21.44#ibcon#about to read 5, iclass 10, count 2 2006.161.08:06:21.44#ibcon#read 5, iclass 10, count 2 2006.161.08:06:21.44#ibcon#about to read 6, iclass 10, count 2 2006.161.08:06:21.44#ibcon#read 6, iclass 10, count 2 2006.161.08:06:21.44#ibcon#end of sib2, iclass 10, count 2 2006.161.08:06:21.44#ibcon#*mode == 0, iclass 10, count 2 2006.161.08:06:21.44#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.08:06:21.44#ibcon#[27=AT01-04\r\n] 2006.161.08:06:21.44#ibcon#*before write, iclass 10, count 2 2006.161.08:06:21.44#ibcon#enter sib2, iclass 10, count 2 2006.161.08:06:21.44#ibcon#flushed, iclass 10, count 2 2006.161.08:06:21.44#ibcon#about to write, iclass 10, count 2 2006.161.08:06:21.44#ibcon#wrote, iclass 10, count 2 2006.161.08:06:21.44#ibcon#about to read 3, iclass 10, count 2 2006.161.08:06:21.48#ibcon#read 3, iclass 10, count 2 2006.161.08:06:21.48#ibcon#about to read 4, iclass 10, count 2 2006.161.08:06:21.48#ibcon#read 4, iclass 10, count 2 2006.161.08:06:21.48#ibcon#about to read 5, iclass 10, count 2 2006.161.08:06:21.48#ibcon#read 5, iclass 10, count 2 2006.161.08:06:21.48#ibcon#about to read 6, iclass 10, count 2 2006.161.08:06:21.48#ibcon#read 6, iclass 10, count 2 2006.161.08:06:21.48#ibcon#end of sib2, iclass 10, count 2 2006.161.08:06:21.48#ibcon#*after write, iclass 10, count 2 2006.161.08:06:21.48#ibcon#*before return 0, iclass 10, count 2 2006.161.08:06:21.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:06:21.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:06:21.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.08:06:21.48#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:21.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:06:21.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:06:21.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:06:21.59#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:06:21.59#ibcon#first serial, iclass 10, count 0 2006.161.08:06:21.59#ibcon#enter sib2, iclass 10, count 0 2006.161.08:06:21.59#ibcon#flushed, iclass 10, count 0 2006.161.08:06:21.59#ibcon#about to write, iclass 10, count 0 2006.161.08:06:21.59#ibcon#wrote, iclass 10, count 0 2006.161.08:06:21.59#ibcon#about to read 3, iclass 10, count 0 2006.161.08:06:21.61#ibcon#read 3, iclass 10, count 0 2006.161.08:06:21.61#ibcon#about to read 4, iclass 10, count 0 2006.161.08:06:21.61#ibcon#read 4, iclass 10, count 0 2006.161.08:06:21.61#ibcon#about to read 5, iclass 10, count 0 2006.161.08:06:21.61#ibcon#read 5, iclass 10, count 0 2006.161.08:06:21.61#ibcon#about to read 6, iclass 10, count 0 2006.161.08:06:21.61#ibcon#read 6, iclass 10, count 0 2006.161.08:06:21.61#ibcon#end of sib2, iclass 10, count 0 2006.161.08:06:21.61#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:06:21.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:06:21.61#ibcon#[27=USB\r\n] 2006.161.08:06:21.61#ibcon#*before write, iclass 10, count 0 2006.161.08:06:21.61#ibcon#enter sib2, iclass 10, count 0 2006.161.08:06:21.61#ibcon#flushed, iclass 10, count 0 2006.161.08:06:21.61#ibcon#about to write, iclass 10, count 0 2006.161.08:06:21.61#ibcon#wrote, iclass 10, count 0 2006.161.08:06:21.61#ibcon#about to read 3, iclass 10, count 0 2006.161.08:06:21.64#ibcon#read 3, iclass 10, count 0 2006.161.08:06:21.64#ibcon#about to read 4, iclass 10, count 0 2006.161.08:06:21.64#ibcon#read 4, iclass 10, count 0 2006.161.08:06:21.64#ibcon#about to read 5, iclass 10, count 0 2006.161.08:06:21.64#ibcon#read 5, iclass 10, count 0 2006.161.08:06:21.64#ibcon#about to read 6, iclass 10, count 0 2006.161.08:06:21.64#ibcon#read 6, iclass 10, count 0 2006.161.08:06:21.64#ibcon#end of sib2, iclass 10, count 0 2006.161.08:06:21.64#ibcon#*after write, iclass 10, count 0 2006.161.08:06:21.64#ibcon#*before return 0, iclass 10, count 0 2006.161.08:06:21.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:06:21.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:06:21.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:06:21.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:06:21.64$vc4f8/vblo=2,640.99 2006.161.08:06:21.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:06:21.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:06:21.64#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:21.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:21.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:21.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:21.64#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:06:21.64#ibcon#first serial, iclass 12, count 0 2006.161.08:06:21.64#ibcon#enter sib2, iclass 12, count 0 2006.161.08:06:21.64#ibcon#flushed, iclass 12, count 0 2006.161.08:06:21.64#ibcon#about to write, iclass 12, count 0 2006.161.08:06:21.64#ibcon#wrote, iclass 12, count 0 2006.161.08:06:21.64#ibcon#about to read 3, iclass 12, count 0 2006.161.08:06:21.66#ibcon#read 3, iclass 12, count 0 2006.161.08:06:21.66#ibcon#about to read 4, iclass 12, count 0 2006.161.08:06:21.66#ibcon#read 4, iclass 12, count 0 2006.161.08:06:21.66#ibcon#about to read 5, iclass 12, count 0 2006.161.08:06:21.66#ibcon#read 5, iclass 12, count 0 2006.161.08:06:21.66#ibcon#about to read 6, iclass 12, count 0 2006.161.08:06:21.66#ibcon#read 6, iclass 12, count 0 2006.161.08:06:21.66#ibcon#end of sib2, iclass 12, count 0 2006.161.08:06:21.66#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:06:21.66#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:06:21.66#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:06:21.66#ibcon#*before write, iclass 12, count 0 2006.161.08:06:21.66#ibcon#enter sib2, iclass 12, count 0 2006.161.08:06:21.66#ibcon#flushed, iclass 12, count 0 2006.161.08:06:21.66#ibcon#about to write, iclass 12, count 0 2006.161.08:06:21.66#ibcon#wrote, iclass 12, count 0 2006.161.08:06:21.66#ibcon#about to read 3, iclass 12, count 0 2006.161.08:06:21.70#ibcon#read 3, iclass 12, count 0 2006.161.08:06:21.70#ibcon#about to read 4, iclass 12, count 0 2006.161.08:06:21.70#ibcon#read 4, iclass 12, count 0 2006.161.08:06:21.70#ibcon#about to read 5, iclass 12, count 0 2006.161.08:06:21.70#ibcon#read 5, iclass 12, count 0 2006.161.08:06:21.70#ibcon#about to read 6, iclass 12, count 0 2006.161.08:06:21.70#ibcon#read 6, iclass 12, count 0 2006.161.08:06:21.70#ibcon#end of sib2, iclass 12, count 0 2006.161.08:06:21.70#ibcon#*after write, iclass 12, count 0 2006.161.08:06:21.70#ibcon#*before return 0, iclass 12, count 0 2006.161.08:06:21.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:21.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:06:21.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:06:21.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:06:21.70$vc4f8/vb=2,4 2006.161.08:06:21.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.08:06:21.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.08:06:21.70#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:21.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:21.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:21.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:21.76#ibcon#enter wrdev, iclass 14, count 2 2006.161.08:06:21.76#ibcon#first serial, iclass 14, count 2 2006.161.08:06:21.76#ibcon#enter sib2, iclass 14, count 2 2006.161.08:06:21.76#ibcon#flushed, iclass 14, count 2 2006.161.08:06:21.76#ibcon#about to write, iclass 14, count 2 2006.161.08:06:21.76#ibcon#wrote, iclass 14, count 2 2006.161.08:06:21.76#ibcon#about to read 3, iclass 14, count 2 2006.161.08:06:21.78#ibcon#read 3, iclass 14, count 2 2006.161.08:06:21.78#ibcon#about to read 4, iclass 14, count 2 2006.161.08:06:21.78#ibcon#read 4, iclass 14, count 2 2006.161.08:06:21.78#ibcon#about to read 5, iclass 14, count 2 2006.161.08:06:21.78#ibcon#read 5, iclass 14, count 2 2006.161.08:06:21.78#ibcon#about to read 6, iclass 14, count 2 2006.161.08:06:21.78#ibcon#read 6, iclass 14, count 2 2006.161.08:06:21.78#ibcon#end of sib2, iclass 14, count 2 2006.161.08:06:21.78#ibcon#*mode == 0, iclass 14, count 2 2006.161.08:06:21.78#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.08:06:21.78#ibcon#[27=AT02-04\r\n] 2006.161.08:06:21.78#ibcon#*before write, iclass 14, count 2 2006.161.08:06:21.78#ibcon#enter sib2, iclass 14, count 2 2006.161.08:06:21.78#ibcon#flushed, iclass 14, count 2 2006.161.08:06:21.78#ibcon#about to write, iclass 14, count 2 2006.161.08:06:21.78#ibcon#wrote, iclass 14, count 2 2006.161.08:06:21.78#ibcon#about to read 3, iclass 14, count 2 2006.161.08:06:21.81#ibcon#read 3, iclass 14, count 2 2006.161.08:06:21.81#ibcon#about to read 4, iclass 14, count 2 2006.161.08:06:21.81#ibcon#read 4, iclass 14, count 2 2006.161.08:06:21.81#ibcon#about to read 5, iclass 14, count 2 2006.161.08:06:21.81#ibcon#read 5, iclass 14, count 2 2006.161.08:06:21.81#ibcon#about to read 6, iclass 14, count 2 2006.161.08:06:21.81#ibcon#read 6, iclass 14, count 2 2006.161.08:06:21.81#ibcon#end of sib2, iclass 14, count 2 2006.161.08:06:21.81#ibcon#*after write, iclass 14, count 2 2006.161.08:06:21.81#ibcon#*before return 0, iclass 14, count 2 2006.161.08:06:21.81#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:21.81#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:06:21.81#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.08:06:21.81#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:21.81#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:21.93#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:21.93#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:21.93#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:06:21.93#ibcon#first serial, iclass 14, count 0 2006.161.08:06:21.93#ibcon#enter sib2, iclass 14, count 0 2006.161.08:06:21.93#ibcon#flushed, iclass 14, count 0 2006.161.08:06:21.93#ibcon#about to write, iclass 14, count 0 2006.161.08:06:21.93#ibcon#wrote, iclass 14, count 0 2006.161.08:06:21.93#ibcon#about to read 3, iclass 14, count 0 2006.161.08:06:21.95#ibcon#read 3, iclass 14, count 0 2006.161.08:06:21.95#ibcon#about to read 4, iclass 14, count 0 2006.161.08:06:21.95#ibcon#read 4, iclass 14, count 0 2006.161.08:06:21.95#ibcon#about to read 5, iclass 14, count 0 2006.161.08:06:21.95#ibcon#read 5, iclass 14, count 0 2006.161.08:06:21.95#ibcon#about to read 6, iclass 14, count 0 2006.161.08:06:21.95#ibcon#read 6, iclass 14, count 0 2006.161.08:06:21.95#ibcon#end of sib2, iclass 14, count 0 2006.161.08:06:21.95#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:06:21.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:06:21.95#ibcon#[27=USB\r\n] 2006.161.08:06:21.95#ibcon#*before write, iclass 14, count 0 2006.161.08:06:21.95#ibcon#enter sib2, iclass 14, count 0 2006.161.08:06:21.95#ibcon#flushed, iclass 14, count 0 2006.161.08:06:21.95#ibcon#about to write, iclass 14, count 0 2006.161.08:06:21.95#ibcon#wrote, iclass 14, count 0 2006.161.08:06:21.95#ibcon#about to read 3, iclass 14, count 0 2006.161.08:06:21.98#ibcon#read 3, iclass 14, count 0 2006.161.08:06:21.98#ibcon#about to read 4, iclass 14, count 0 2006.161.08:06:21.98#ibcon#read 4, iclass 14, count 0 2006.161.08:06:21.98#ibcon#about to read 5, iclass 14, count 0 2006.161.08:06:21.98#ibcon#read 5, iclass 14, count 0 2006.161.08:06:21.98#ibcon#about to read 6, iclass 14, count 0 2006.161.08:06:21.98#ibcon#read 6, iclass 14, count 0 2006.161.08:06:21.98#ibcon#end of sib2, iclass 14, count 0 2006.161.08:06:21.98#ibcon#*after write, iclass 14, count 0 2006.161.08:06:21.98#ibcon#*before return 0, iclass 14, count 0 2006.161.08:06:21.98#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:21.98#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:06:21.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:06:21.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:06:21.98$vc4f8/vblo=3,656.99 2006.161.08:06:21.98#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.08:06:21.98#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.08:06:21.98#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:21.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:21.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:21.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:21.98#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:06:21.98#ibcon#first serial, iclass 16, count 0 2006.161.08:06:21.98#ibcon#enter sib2, iclass 16, count 0 2006.161.08:06:21.98#ibcon#flushed, iclass 16, count 0 2006.161.08:06:21.98#ibcon#about to write, iclass 16, count 0 2006.161.08:06:21.98#ibcon#wrote, iclass 16, count 0 2006.161.08:06:21.98#ibcon#about to read 3, iclass 16, count 0 2006.161.08:06:22.00#ibcon#read 3, iclass 16, count 0 2006.161.08:06:22.00#ibcon#about to read 4, iclass 16, count 0 2006.161.08:06:22.00#ibcon#read 4, iclass 16, count 0 2006.161.08:06:22.00#ibcon#about to read 5, iclass 16, count 0 2006.161.08:06:22.00#ibcon#read 5, iclass 16, count 0 2006.161.08:06:22.00#ibcon#about to read 6, iclass 16, count 0 2006.161.08:06:22.00#ibcon#read 6, iclass 16, count 0 2006.161.08:06:22.00#ibcon#end of sib2, iclass 16, count 0 2006.161.08:06:22.00#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:06:22.00#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:06:22.00#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:06:22.00#ibcon#*before write, iclass 16, count 0 2006.161.08:06:22.00#ibcon#enter sib2, iclass 16, count 0 2006.161.08:06:22.00#ibcon#flushed, iclass 16, count 0 2006.161.08:06:22.00#ibcon#about to write, iclass 16, count 0 2006.161.08:06:22.00#ibcon#wrote, iclass 16, count 0 2006.161.08:06:22.00#ibcon#about to read 3, iclass 16, count 0 2006.161.08:06:22.04#ibcon#read 3, iclass 16, count 0 2006.161.08:06:22.04#ibcon#about to read 4, iclass 16, count 0 2006.161.08:06:22.04#ibcon#read 4, iclass 16, count 0 2006.161.08:06:22.04#ibcon#about to read 5, iclass 16, count 0 2006.161.08:06:22.04#ibcon#read 5, iclass 16, count 0 2006.161.08:06:22.04#ibcon#about to read 6, iclass 16, count 0 2006.161.08:06:22.04#ibcon#read 6, iclass 16, count 0 2006.161.08:06:22.04#ibcon#end of sib2, iclass 16, count 0 2006.161.08:06:22.04#ibcon#*after write, iclass 16, count 0 2006.161.08:06:22.04#ibcon#*before return 0, iclass 16, count 0 2006.161.08:06:22.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:22.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:06:22.04#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:06:22.04#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:06:22.04$vc4f8/vb=3,4 2006.161.08:06:22.04#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.08:06:22.04#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.08:06:22.04#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:22.04#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:22.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:22.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:22.10#ibcon#enter wrdev, iclass 18, count 2 2006.161.08:06:22.10#ibcon#first serial, iclass 18, count 2 2006.161.08:06:22.10#ibcon#enter sib2, iclass 18, count 2 2006.161.08:06:22.10#ibcon#flushed, iclass 18, count 2 2006.161.08:06:22.10#ibcon#about to write, iclass 18, count 2 2006.161.08:06:22.10#ibcon#wrote, iclass 18, count 2 2006.161.08:06:22.10#ibcon#about to read 3, iclass 18, count 2 2006.161.08:06:22.13#ibcon#read 3, iclass 18, count 2 2006.161.08:06:22.13#ibcon#about to read 4, iclass 18, count 2 2006.161.08:06:22.13#ibcon#read 4, iclass 18, count 2 2006.161.08:06:22.13#ibcon#about to read 5, iclass 18, count 2 2006.161.08:06:22.13#ibcon#read 5, iclass 18, count 2 2006.161.08:06:22.13#ibcon#about to read 6, iclass 18, count 2 2006.161.08:06:22.13#ibcon#read 6, iclass 18, count 2 2006.161.08:06:22.13#ibcon#end of sib2, iclass 18, count 2 2006.161.08:06:22.13#ibcon#*mode == 0, iclass 18, count 2 2006.161.08:06:22.13#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.08:06:22.13#ibcon#[27=AT03-04\r\n] 2006.161.08:06:22.13#ibcon#*before write, iclass 18, count 2 2006.161.08:06:22.13#ibcon#enter sib2, iclass 18, count 2 2006.161.08:06:22.13#ibcon#flushed, iclass 18, count 2 2006.161.08:06:22.13#ibcon#about to write, iclass 18, count 2 2006.161.08:06:22.13#ibcon#wrote, iclass 18, count 2 2006.161.08:06:22.13#ibcon#about to read 3, iclass 18, count 2 2006.161.08:06:22.16#ibcon#read 3, iclass 18, count 2 2006.161.08:06:22.16#ibcon#about to read 4, iclass 18, count 2 2006.161.08:06:22.16#ibcon#read 4, iclass 18, count 2 2006.161.08:06:22.16#ibcon#about to read 5, iclass 18, count 2 2006.161.08:06:22.16#ibcon#read 5, iclass 18, count 2 2006.161.08:06:22.16#ibcon#about to read 6, iclass 18, count 2 2006.161.08:06:22.16#ibcon#read 6, iclass 18, count 2 2006.161.08:06:22.16#ibcon#end of sib2, iclass 18, count 2 2006.161.08:06:22.16#ibcon#*after write, iclass 18, count 2 2006.161.08:06:22.16#ibcon#*before return 0, iclass 18, count 2 2006.161.08:06:22.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:22.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:06:22.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.08:06:22.16#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:22.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:22.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:22.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:22.28#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:06:22.28#ibcon#first serial, iclass 18, count 0 2006.161.08:06:22.28#ibcon#enter sib2, iclass 18, count 0 2006.161.08:06:22.28#ibcon#flushed, iclass 18, count 0 2006.161.08:06:22.28#ibcon#about to write, iclass 18, count 0 2006.161.08:06:22.28#ibcon#wrote, iclass 18, count 0 2006.161.08:06:22.28#ibcon#about to read 3, iclass 18, count 0 2006.161.08:06:22.30#ibcon#read 3, iclass 18, count 0 2006.161.08:06:22.30#ibcon#about to read 4, iclass 18, count 0 2006.161.08:06:22.30#ibcon#read 4, iclass 18, count 0 2006.161.08:06:22.30#ibcon#about to read 5, iclass 18, count 0 2006.161.08:06:22.30#ibcon#read 5, iclass 18, count 0 2006.161.08:06:22.30#ibcon#about to read 6, iclass 18, count 0 2006.161.08:06:22.30#ibcon#read 6, iclass 18, count 0 2006.161.08:06:22.30#ibcon#end of sib2, iclass 18, count 0 2006.161.08:06:22.30#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:06:22.30#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:06:22.30#ibcon#[27=USB\r\n] 2006.161.08:06:22.30#ibcon#*before write, iclass 18, count 0 2006.161.08:06:22.30#ibcon#enter sib2, iclass 18, count 0 2006.161.08:06:22.30#ibcon#flushed, iclass 18, count 0 2006.161.08:06:22.30#ibcon#about to write, iclass 18, count 0 2006.161.08:06:22.30#ibcon#wrote, iclass 18, count 0 2006.161.08:06:22.30#ibcon#about to read 3, iclass 18, count 0 2006.161.08:06:22.33#ibcon#read 3, iclass 18, count 0 2006.161.08:06:22.33#ibcon#about to read 4, iclass 18, count 0 2006.161.08:06:22.33#ibcon#read 4, iclass 18, count 0 2006.161.08:06:22.33#ibcon#about to read 5, iclass 18, count 0 2006.161.08:06:22.33#ibcon#read 5, iclass 18, count 0 2006.161.08:06:22.33#ibcon#about to read 6, iclass 18, count 0 2006.161.08:06:22.33#ibcon#read 6, iclass 18, count 0 2006.161.08:06:22.33#ibcon#end of sib2, iclass 18, count 0 2006.161.08:06:22.33#ibcon#*after write, iclass 18, count 0 2006.161.08:06:22.33#ibcon#*before return 0, iclass 18, count 0 2006.161.08:06:22.33#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:22.33#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:06:22.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:06:22.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:06:22.33$vc4f8/vblo=4,712.99 2006.161.08:06:22.33#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.08:06:22.33#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.08:06:22.33#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:22.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:22.33#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:22.33#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:22.33#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:06:22.33#ibcon#first serial, iclass 20, count 0 2006.161.08:06:22.33#ibcon#enter sib2, iclass 20, count 0 2006.161.08:06:22.33#ibcon#flushed, iclass 20, count 0 2006.161.08:06:22.33#ibcon#about to write, iclass 20, count 0 2006.161.08:06:22.33#ibcon#wrote, iclass 20, count 0 2006.161.08:06:22.33#ibcon#about to read 3, iclass 20, count 0 2006.161.08:06:22.35#ibcon#read 3, iclass 20, count 0 2006.161.08:06:22.35#ibcon#about to read 4, iclass 20, count 0 2006.161.08:06:22.35#ibcon#read 4, iclass 20, count 0 2006.161.08:06:22.35#ibcon#about to read 5, iclass 20, count 0 2006.161.08:06:22.35#ibcon#read 5, iclass 20, count 0 2006.161.08:06:22.35#ibcon#about to read 6, iclass 20, count 0 2006.161.08:06:22.35#ibcon#read 6, iclass 20, count 0 2006.161.08:06:22.35#ibcon#end of sib2, iclass 20, count 0 2006.161.08:06:22.35#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:06:22.35#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:06:22.35#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:06:22.35#ibcon#*before write, iclass 20, count 0 2006.161.08:06:22.35#ibcon#enter sib2, iclass 20, count 0 2006.161.08:06:22.35#ibcon#flushed, iclass 20, count 0 2006.161.08:06:22.35#ibcon#about to write, iclass 20, count 0 2006.161.08:06:22.35#ibcon#wrote, iclass 20, count 0 2006.161.08:06:22.35#ibcon#about to read 3, iclass 20, count 0 2006.161.08:06:22.39#ibcon#read 3, iclass 20, count 0 2006.161.08:06:22.39#ibcon#about to read 4, iclass 20, count 0 2006.161.08:06:22.39#ibcon#read 4, iclass 20, count 0 2006.161.08:06:22.39#ibcon#about to read 5, iclass 20, count 0 2006.161.08:06:22.39#ibcon#read 5, iclass 20, count 0 2006.161.08:06:22.39#ibcon#about to read 6, iclass 20, count 0 2006.161.08:06:22.39#ibcon#read 6, iclass 20, count 0 2006.161.08:06:22.39#ibcon#end of sib2, iclass 20, count 0 2006.161.08:06:22.39#ibcon#*after write, iclass 20, count 0 2006.161.08:06:22.39#ibcon#*before return 0, iclass 20, count 0 2006.161.08:06:22.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:22.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:06:22.39#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:06:22.39#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:06:22.39$vc4f8/vb=4,4 2006.161.08:06:22.39#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.08:06:22.39#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.08:06:22.39#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:22.39#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:22.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:22.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:22.45#ibcon#enter wrdev, iclass 22, count 2 2006.161.08:06:22.45#ibcon#first serial, iclass 22, count 2 2006.161.08:06:22.45#ibcon#enter sib2, iclass 22, count 2 2006.161.08:06:22.45#ibcon#flushed, iclass 22, count 2 2006.161.08:06:22.45#ibcon#about to write, iclass 22, count 2 2006.161.08:06:22.45#ibcon#wrote, iclass 22, count 2 2006.161.08:06:22.45#ibcon#about to read 3, iclass 22, count 2 2006.161.08:06:22.47#ibcon#read 3, iclass 22, count 2 2006.161.08:06:22.47#ibcon#about to read 4, iclass 22, count 2 2006.161.08:06:22.47#ibcon#read 4, iclass 22, count 2 2006.161.08:06:22.47#ibcon#about to read 5, iclass 22, count 2 2006.161.08:06:22.47#ibcon#read 5, iclass 22, count 2 2006.161.08:06:22.47#ibcon#about to read 6, iclass 22, count 2 2006.161.08:06:22.47#ibcon#read 6, iclass 22, count 2 2006.161.08:06:22.47#ibcon#end of sib2, iclass 22, count 2 2006.161.08:06:22.47#ibcon#*mode == 0, iclass 22, count 2 2006.161.08:06:22.47#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.08:06:22.47#ibcon#[27=AT04-04\r\n] 2006.161.08:06:22.47#ibcon#*before write, iclass 22, count 2 2006.161.08:06:22.47#ibcon#enter sib2, iclass 22, count 2 2006.161.08:06:22.47#ibcon#flushed, iclass 22, count 2 2006.161.08:06:22.47#ibcon#about to write, iclass 22, count 2 2006.161.08:06:22.47#ibcon#wrote, iclass 22, count 2 2006.161.08:06:22.47#ibcon#about to read 3, iclass 22, count 2 2006.161.08:06:22.50#ibcon#read 3, iclass 22, count 2 2006.161.08:06:22.50#ibcon#about to read 4, iclass 22, count 2 2006.161.08:06:22.50#ibcon#read 4, iclass 22, count 2 2006.161.08:06:22.50#ibcon#about to read 5, iclass 22, count 2 2006.161.08:06:22.50#ibcon#read 5, iclass 22, count 2 2006.161.08:06:22.50#ibcon#about to read 6, iclass 22, count 2 2006.161.08:06:22.50#ibcon#read 6, iclass 22, count 2 2006.161.08:06:22.50#ibcon#end of sib2, iclass 22, count 2 2006.161.08:06:22.50#ibcon#*after write, iclass 22, count 2 2006.161.08:06:22.50#ibcon#*before return 0, iclass 22, count 2 2006.161.08:06:22.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:22.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:06:22.50#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.08:06:22.50#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:22.50#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:22.62#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:22.62#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:22.62#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:06:22.62#ibcon#first serial, iclass 22, count 0 2006.161.08:06:22.62#ibcon#enter sib2, iclass 22, count 0 2006.161.08:06:22.62#ibcon#flushed, iclass 22, count 0 2006.161.08:06:22.62#ibcon#about to write, iclass 22, count 0 2006.161.08:06:22.62#ibcon#wrote, iclass 22, count 0 2006.161.08:06:22.62#ibcon#about to read 3, iclass 22, count 0 2006.161.08:06:22.64#ibcon#read 3, iclass 22, count 0 2006.161.08:06:22.64#ibcon#about to read 4, iclass 22, count 0 2006.161.08:06:22.64#ibcon#read 4, iclass 22, count 0 2006.161.08:06:22.64#ibcon#about to read 5, iclass 22, count 0 2006.161.08:06:22.64#ibcon#read 5, iclass 22, count 0 2006.161.08:06:22.64#ibcon#about to read 6, iclass 22, count 0 2006.161.08:06:22.64#ibcon#read 6, iclass 22, count 0 2006.161.08:06:22.64#ibcon#end of sib2, iclass 22, count 0 2006.161.08:06:22.64#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:06:22.64#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:06:22.64#ibcon#[27=USB\r\n] 2006.161.08:06:22.64#ibcon#*before write, iclass 22, count 0 2006.161.08:06:22.64#ibcon#enter sib2, iclass 22, count 0 2006.161.08:06:22.64#ibcon#flushed, iclass 22, count 0 2006.161.08:06:22.64#ibcon#about to write, iclass 22, count 0 2006.161.08:06:22.64#ibcon#wrote, iclass 22, count 0 2006.161.08:06:22.64#ibcon#about to read 3, iclass 22, count 0 2006.161.08:06:22.67#ibcon#read 3, iclass 22, count 0 2006.161.08:06:22.67#ibcon#about to read 4, iclass 22, count 0 2006.161.08:06:22.67#ibcon#read 4, iclass 22, count 0 2006.161.08:06:22.67#ibcon#about to read 5, iclass 22, count 0 2006.161.08:06:22.67#ibcon#read 5, iclass 22, count 0 2006.161.08:06:22.67#ibcon#about to read 6, iclass 22, count 0 2006.161.08:06:22.67#ibcon#read 6, iclass 22, count 0 2006.161.08:06:22.67#ibcon#end of sib2, iclass 22, count 0 2006.161.08:06:22.67#ibcon#*after write, iclass 22, count 0 2006.161.08:06:22.67#ibcon#*before return 0, iclass 22, count 0 2006.161.08:06:22.67#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:22.67#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:06:22.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:06:22.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:06:22.67$vc4f8/vblo=5,744.99 2006.161.08:06:22.67#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:06:22.67#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:06:22.67#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:22.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:22.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:22.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:22.67#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:06:22.67#ibcon#first serial, iclass 24, count 0 2006.161.08:06:22.67#ibcon#enter sib2, iclass 24, count 0 2006.161.08:06:22.67#ibcon#flushed, iclass 24, count 0 2006.161.08:06:22.67#ibcon#about to write, iclass 24, count 0 2006.161.08:06:22.67#ibcon#wrote, iclass 24, count 0 2006.161.08:06:22.67#ibcon#about to read 3, iclass 24, count 0 2006.161.08:06:22.69#ibcon#read 3, iclass 24, count 0 2006.161.08:06:22.69#ibcon#about to read 4, iclass 24, count 0 2006.161.08:06:22.69#ibcon#read 4, iclass 24, count 0 2006.161.08:06:22.69#ibcon#about to read 5, iclass 24, count 0 2006.161.08:06:22.69#ibcon#read 5, iclass 24, count 0 2006.161.08:06:22.69#ibcon#about to read 6, iclass 24, count 0 2006.161.08:06:22.69#ibcon#read 6, iclass 24, count 0 2006.161.08:06:22.69#ibcon#end of sib2, iclass 24, count 0 2006.161.08:06:22.69#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:06:22.69#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:06:22.69#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:06:22.69#ibcon#*before write, iclass 24, count 0 2006.161.08:06:22.69#ibcon#enter sib2, iclass 24, count 0 2006.161.08:06:22.69#ibcon#flushed, iclass 24, count 0 2006.161.08:06:22.69#ibcon#about to write, iclass 24, count 0 2006.161.08:06:22.69#ibcon#wrote, iclass 24, count 0 2006.161.08:06:22.69#ibcon#about to read 3, iclass 24, count 0 2006.161.08:06:22.73#ibcon#read 3, iclass 24, count 0 2006.161.08:06:22.73#ibcon#about to read 4, iclass 24, count 0 2006.161.08:06:22.73#ibcon#read 4, iclass 24, count 0 2006.161.08:06:22.73#ibcon#about to read 5, iclass 24, count 0 2006.161.08:06:22.73#ibcon#read 5, iclass 24, count 0 2006.161.08:06:22.73#ibcon#about to read 6, iclass 24, count 0 2006.161.08:06:22.73#ibcon#read 6, iclass 24, count 0 2006.161.08:06:22.73#ibcon#end of sib2, iclass 24, count 0 2006.161.08:06:22.73#ibcon#*after write, iclass 24, count 0 2006.161.08:06:22.73#ibcon#*before return 0, iclass 24, count 0 2006.161.08:06:22.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:22.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:06:22.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:06:22.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:06:22.73$vc4f8/vb=5,4 2006.161.08:06:22.73#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:06:22.73#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:06:22.73#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:22.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:22.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:22.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:22.79#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:06:22.79#ibcon#first serial, iclass 26, count 2 2006.161.08:06:22.79#ibcon#enter sib2, iclass 26, count 2 2006.161.08:06:22.79#ibcon#flushed, iclass 26, count 2 2006.161.08:06:22.79#ibcon#about to write, iclass 26, count 2 2006.161.08:06:22.79#ibcon#wrote, iclass 26, count 2 2006.161.08:06:22.79#ibcon#about to read 3, iclass 26, count 2 2006.161.08:06:22.82#ibcon#read 3, iclass 26, count 2 2006.161.08:06:22.82#ibcon#about to read 4, iclass 26, count 2 2006.161.08:06:22.82#ibcon#read 4, iclass 26, count 2 2006.161.08:06:22.82#ibcon#about to read 5, iclass 26, count 2 2006.161.08:06:22.82#ibcon#read 5, iclass 26, count 2 2006.161.08:06:22.82#ibcon#about to read 6, iclass 26, count 2 2006.161.08:06:22.82#ibcon#read 6, iclass 26, count 2 2006.161.08:06:22.82#ibcon#end of sib2, iclass 26, count 2 2006.161.08:06:22.82#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:06:22.82#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:06:22.82#ibcon#[27=AT05-04\r\n] 2006.161.08:06:22.82#ibcon#*before write, iclass 26, count 2 2006.161.08:06:22.82#ibcon#enter sib2, iclass 26, count 2 2006.161.08:06:22.82#ibcon#flushed, iclass 26, count 2 2006.161.08:06:22.82#ibcon#about to write, iclass 26, count 2 2006.161.08:06:22.82#ibcon#wrote, iclass 26, count 2 2006.161.08:06:22.82#ibcon#about to read 3, iclass 26, count 2 2006.161.08:06:22.85#abcon#<5=/05 3.0 5.7 24.01 861002.3\r\n> 2006.161.08:06:22.85#ibcon#read 3, iclass 26, count 2 2006.161.08:06:22.85#ibcon#about to read 4, iclass 26, count 2 2006.161.08:06:22.85#ibcon#read 4, iclass 26, count 2 2006.161.08:06:22.85#ibcon#about to read 5, iclass 26, count 2 2006.161.08:06:22.85#ibcon#read 5, iclass 26, count 2 2006.161.08:06:22.85#ibcon#about to read 6, iclass 26, count 2 2006.161.08:06:22.85#ibcon#read 6, iclass 26, count 2 2006.161.08:06:22.85#ibcon#end of sib2, iclass 26, count 2 2006.161.08:06:22.85#ibcon#*after write, iclass 26, count 2 2006.161.08:06:22.85#ibcon#*before return 0, iclass 26, count 2 2006.161.08:06:22.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:22.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:06:22.85#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:06:22.85#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:22.85#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:22.87#abcon#{5=INTERFACE CLEAR} 2006.161.08:06:22.93#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:06:22.97#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:22.97#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:22.97#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:06:22.97#ibcon#first serial, iclass 26, count 0 2006.161.08:06:22.97#ibcon#enter sib2, iclass 26, count 0 2006.161.08:06:22.97#ibcon#flushed, iclass 26, count 0 2006.161.08:06:22.97#ibcon#about to write, iclass 26, count 0 2006.161.08:06:22.97#ibcon#wrote, iclass 26, count 0 2006.161.08:06:22.97#ibcon#about to read 3, iclass 26, count 0 2006.161.08:06:23.01#ibcon#read 3, iclass 26, count 0 2006.161.08:06:23.01#ibcon#about to read 4, iclass 26, count 0 2006.161.08:06:23.01#ibcon#read 4, iclass 26, count 0 2006.161.08:06:23.01#ibcon#about to read 5, iclass 26, count 0 2006.161.08:06:23.01#ibcon#read 5, iclass 26, count 0 2006.161.08:06:23.01#ibcon#about to read 6, iclass 26, count 0 2006.161.08:06:23.01#ibcon#read 6, iclass 26, count 0 2006.161.08:06:23.01#ibcon#end of sib2, iclass 26, count 0 2006.161.08:06:23.01#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:06:23.01#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:06:23.01#ibcon#[27=USB\r\n] 2006.161.08:06:23.01#ibcon#*before write, iclass 26, count 0 2006.161.08:06:23.01#ibcon#enter sib2, iclass 26, count 0 2006.161.08:06:23.01#ibcon#flushed, iclass 26, count 0 2006.161.08:06:23.01#ibcon#about to write, iclass 26, count 0 2006.161.08:06:23.01#ibcon#wrote, iclass 26, count 0 2006.161.08:06:23.01#ibcon#about to read 3, iclass 26, count 0 2006.161.08:06:23.04#ibcon#read 3, iclass 26, count 0 2006.161.08:06:23.04#ibcon#about to read 4, iclass 26, count 0 2006.161.08:06:23.04#ibcon#read 4, iclass 26, count 0 2006.161.08:06:23.04#ibcon#about to read 5, iclass 26, count 0 2006.161.08:06:23.04#ibcon#read 5, iclass 26, count 0 2006.161.08:06:23.04#ibcon#about to read 6, iclass 26, count 0 2006.161.08:06:23.04#ibcon#read 6, iclass 26, count 0 2006.161.08:06:23.04#ibcon#end of sib2, iclass 26, count 0 2006.161.08:06:23.04#ibcon#*after write, iclass 26, count 0 2006.161.08:06:23.04#ibcon#*before return 0, iclass 26, count 0 2006.161.08:06:23.04#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:23.04#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:06:23.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:06:23.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:06:23.04$vc4f8/vblo=6,752.99 2006.161.08:06:23.04#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.08:06:23.04#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.08:06:23.04#ibcon#ireg 17 cls_cnt 0 2006.161.08:06:23.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:23.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:23.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:23.04#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:06:23.04#ibcon#first serial, iclass 32, count 0 2006.161.08:06:23.04#ibcon#enter sib2, iclass 32, count 0 2006.161.08:06:23.04#ibcon#flushed, iclass 32, count 0 2006.161.08:06:23.04#ibcon#about to write, iclass 32, count 0 2006.161.08:06:23.04#ibcon#wrote, iclass 32, count 0 2006.161.08:06:23.04#ibcon#about to read 3, iclass 32, count 0 2006.161.08:06:23.06#ibcon#read 3, iclass 32, count 0 2006.161.08:06:23.06#ibcon#about to read 4, iclass 32, count 0 2006.161.08:06:23.06#ibcon#read 4, iclass 32, count 0 2006.161.08:06:23.06#ibcon#about to read 5, iclass 32, count 0 2006.161.08:06:23.06#ibcon#read 5, iclass 32, count 0 2006.161.08:06:23.06#ibcon#about to read 6, iclass 32, count 0 2006.161.08:06:23.06#ibcon#read 6, iclass 32, count 0 2006.161.08:06:23.06#ibcon#end of sib2, iclass 32, count 0 2006.161.08:06:23.06#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:06:23.06#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:06:23.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:06:23.06#ibcon#*before write, iclass 32, count 0 2006.161.08:06:23.06#ibcon#enter sib2, iclass 32, count 0 2006.161.08:06:23.06#ibcon#flushed, iclass 32, count 0 2006.161.08:06:23.06#ibcon#about to write, iclass 32, count 0 2006.161.08:06:23.06#ibcon#wrote, iclass 32, count 0 2006.161.08:06:23.06#ibcon#about to read 3, iclass 32, count 0 2006.161.08:06:23.10#ibcon#read 3, iclass 32, count 0 2006.161.08:06:23.10#ibcon#about to read 4, iclass 32, count 0 2006.161.08:06:23.10#ibcon#read 4, iclass 32, count 0 2006.161.08:06:23.10#ibcon#about to read 5, iclass 32, count 0 2006.161.08:06:23.10#ibcon#read 5, iclass 32, count 0 2006.161.08:06:23.10#ibcon#about to read 6, iclass 32, count 0 2006.161.08:06:23.10#ibcon#read 6, iclass 32, count 0 2006.161.08:06:23.10#ibcon#end of sib2, iclass 32, count 0 2006.161.08:06:23.10#ibcon#*after write, iclass 32, count 0 2006.161.08:06:23.10#ibcon#*before return 0, iclass 32, count 0 2006.161.08:06:23.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:23.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:06:23.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:06:23.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:06:23.10$vc4f8/vb=6,4 2006.161.08:06:23.10#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.08:06:23.10#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.08:06:23.10#ibcon#ireg 11 cls_cnt 2 2006.161.08:06:23.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:23.16#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:23.16#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:23.16#ibcon#enter wrdev, iclass 34, count 2 2006.161.08:06:23.16#ibcon#first serial, iclass 34, count 2 2006.161.08:06:23.16#ibcon#enter sib2, iclass 34, count 2 2006.161.08:06:23.16#ibcon#flushed, iclass 34, count 2 2006.161.08:06:23.16#ibcon#about to write, iclass 34, count 2 2006.161.08:06:23.16#ibcon#wrote, iclass 34, count 2 2006.161.08:06:23.16#ibcon#about to read 3, iclass 34, count 2 2006.161.08:06:23.18#ibcon#read 3, iclass 34, count 2 2006.161.08:06:23.18#ibcon#about to read 4, iclass 34, count 2 2006.161.08:06:23.18#ibcon#read 4, iclass 34, count 2 2006.161.08:06:23.18#ibcon#about to read 5, iclass 34, count 2 2006.161.08:06:23.18#ibcon#read 5, iclass 34, count 2 2006.161.08:06:23.18#ibcon#about to read 6, iclass 34, count 2 2006.161.08:06:23.18#ibcon#read 6, iclass 34, count 2 2006.161.08:06:23.18#ibcon#end of sib2, iclass 34, count 2 2006.161.08:06:23.18#ibcon#*mode == 0, iclass 34, count 2 2006.161.08:06:23.18#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.08:06:23.18#ibcon#[27=AT06-04\r\n] 2006.161.08:06:23.18#ibcon#*before write, iclass 34, count 2 2006.161.08:06:23.18#ibcon#enter sib2, iclass 34, count 2 2006.161.08:06:23.18#ibcon#flushed, iclass 34, count 2 2006.161.08:06:23.18#ibcon#about to write, iclass 34, count 2 2006.161.08:06:23.18#ibcon#wrote, iclass 34, count 2 2006.161.08:06:23.18#ibcon#about to read 3, iclass 34, count 2 2006.161.08:06:23.21#ibcon#read 3, iclass 34, count 2 2006.161.08:06:23.21#ibcon#about to read 4, iclass 34, count 2 2006.161.08:06:23.21#ibcon#read 4, iclass 34, count 2 2006.161.08:06:23.21#ibcon#about to read 5, iclass 34, count 2 2006.161.08:06:23.21#ibcon#read 5, iclass 34, count 2 2006.161.08:06:23.21#ibcon#about to read 6, iclass 34, count 2 2006.161.08:06:23.21#ibcon#read 6, iclass 34, count 2 2006.161.08:06:23.21#ibcon#end of sib2, iclass 34, count 2 2006.161.08:06:23.21#ibcon#*after write, iclass 34, count 2 2006.161.08:06:23.21#ibcon#*before return 0, iclass 34, count 2 2006.161.08:06:23.21#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:23.21#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:06:23.21#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.08:06:23.21#ibcon#ireg 7 cls_cnt 0 2006.161.08:06:23.21#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:23.33#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:23.33#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:23.33#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:06:23.33#ibcon#first serial, iclass 34, count 0 2006.161.08:06:23.33#ibcon#enter sib2, iclass 34, count 0 2006.161.08:06:23.33#ibcon#flushed, iclass 34, count 0 2006.161.08:06:23.33#ibcon#about to write, iclass 34, count 0 2006.161.08:06:23.33#ibcon#wrote, iclass 34, count 0 2006.161.08:06:23.33#ibcon#about to read 3, iclass 34, count 0 2006.161.08:06:23.35#ibcon#read 3, iclass 34, count 0 2006.161.08:06:23.35#ibcon#about to read 4, iclass 34, count 0 2006.161.08:06:23.35#ibcon#read 4, iclass 34, count 0 2006.161.08:06:23.35#ibcon#about to read 5, iclass 34, count 0 2006.161.08:06:23.35#ibcon#read 5, iclass 34, count 0 2006.161.08:06:23.35#ibcon#about to read 6, iclass 34, count 0 2006.161.08:06:23.35#ibcon#read 6, iclass 34, count 0 2006.161.08:06:23.35#ibcon#end of sib2, iclass 34, count 0 2006.161.08:06:23.35#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:06:23.35#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:06:23.35#ibcon#[27=USB\r\n] 2006.161.08:06:23.35#ibcon#*before write, iclass 34, count 0 2006.161.08:06:23.35#ibcon#enter sib2, iclass 34, count 0 2006.161.08:06:23.35#ibcon#flushed, iclass 34, count 0 2006.161.08:06:23.35#ibcon#about to write, iclass 34, count 0 2006.161.08:06:23.35#ibcon#wrote, iclass 34, count 0 2006.161.08:06:23.35#ibcon#about to read 3, iclass 34, count 0 2006.161.08:06:23.38#ibcon#read 3, iclass 34, count 0 2006.161.08:06:23.38#ibcon#about to read 4, iclass 34, count 0 2006.161.08:06:23.38#ibcon#read 4, iclass 34, count 0 2006.161.08:06:23.38#ibcon#about to read 5, iclass 34, count 0 2006.161.08:06:23.38#ibcon#read 5, iclass 34, count 0 2006.161.08:06:23.38#ibcon#about to read 6, iclass 34, count 0 2006.161.08:06:23.38#ibcon#read 6, iclass 34, count 0 2006.161.08:06:23.38#ibcon#end of sib2, iclass 34, count 0 2006.161.08:06:23.38#ibcon#*after write, iclass 34, count 0 2006.161.08:06:23.38#ibcon#*before return 0, iclass 34, count 0 2006.161.08:06:23.38#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:23.38#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:06:23.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:06:23.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:06:23.38$vc4f8/vabw=wide 2006.161.08:06:23.38#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:06:23.38#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:06:23.38#ibcon#ireg 8 cls_cnt 0 2006.161.08:06:23.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:23.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:23.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:23.38#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:06:23.38#ibcon#first serial, iclass 36, count 0 2006.161.08:06:23.38#ibcon#enter sib2, iclass 36, count 0 2006.161.08:06:23.38#ibcon#flushed, iclass 36, count 0 2006.161.08:06:23.38#ibcon#about to write, iclass 36, count 0 2006.161.08:06:23.38#ibcon#wrote, iclass 36, count 0 2006.161.08:06:23.38#ibcon#about to read 3, iclass 36, count 0 2006.161.08:06:23.40#ibcon#read 3, iclass 36, count 0 2006.161.08:06:23.40#ibcon#about to read 4, iclass 36, count 0 2006.161.08:06:23.40#ibcon#read 4, iclass 36, count 0 2006.161.08:06:23.40#ibcon#about to read 5, iclass 36, count 0 2006.161.08:06:23.40#ibcon#read 5, iclass 36, count 0 2006.161.08:06:23.40#ibcon#about to read 6, iclass 36, count 0 2006.161.08:06:23.40#ibcon#read 6, iclass 36, count 0 2006.161.08:06:23.40#ibcon#end of sib2, iclass 36, count 0 2006.161.08:06:23.40#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:06:23.40#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:06:23.40#ibcon#[25=BW32\r\n] 2006.161.08:06:23.40#ibcon#*before write, iclass 36, count 0 2006.161.08:06:23.40#ibcon#enter sib2, iclass 36, count 0 2006.161.08:06:23.40#ibcon#flushed, iclass 36, count 0 2006.161.08:06:23.40#ibcon#about to write, iclass 36, count 0 2006.161.08:06:23.40#ibcon#wrote, iclass 36, count 0 2006.161.08:06:23.40#ibcon#about to read 3, iclass 36, count 0 2006.161.08:06:23.43#ibcon#read 3, iclass 36, count 0 2006.161.08:06:23.43#ibcon#about to read 4, iclass 36, count 0 2006.161.08:06:23.43#ibcon#read 4, iclass 36, count 0 2006.161.08:06:23.43#ibcon#about to read 5, iclass 36, count 0 2006.161.08:06:23.43#ibcon#read 5, iclass 36, count 0 2006.161.08:06:23.43#ibcon#about to read 6, iclass 36, count 0 2006.161.08:06:23.43#ibcon#read 6, iclass 36, count 0 2006.161.08:06:23.43#ibcon#end of sib2, iclass 36, count 0 2006.161.08:06:23.43#ibcon#*after write, iclass 36, count 0 2006.161.08:06:23.43#ibcon#*before return 0, iclass 36, count 0 2006.161.08:06:23.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:23.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:06:23.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:06:23.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:06:23.43$vc4f8/vbbw=wide 2006.161.08:06:23.43#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:06:23.43#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:06:23.43#ibcon#ireg 8 cls_cnt 0 2006.161.08:06:23.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:06:23.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:06:23.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:06:23.50#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:06:23.50#ibcon#first serial, iclass 38, count 0 2006.161.08:06:23.50#ibcon#enter sib2, iclass 38, count 0 2006.161.08:06:23.50#ibcon#flushed, iclass 38, count 0 2006.161.08:06:23.50#ibcon#about to write, iclass 38, count 0 2006.161.08:06:23.50#ibcon#wrote, iclass 38, count 0 2006.161.08:06:23.50#ibcon#about to read 3, iclass 38, count 0 2006.161.08:06:23.52#ibcon#read 3, iclass 38, count 0 2006.161.08:06:23.52#ibcon#about to read 4, iclass 38, count 0 2006.161.08:06:23.52#ibcon#read 4, iclass 38, count 0 2006.161.08:06:23.52#ibcon#about to read 5, iclass 38, count 0 2006.161.08:06:23.52#ibcon#read 5, iclass 38, count 0 2006.161.08:06:23.52#ibcon#about to read 6, iclass 38, count 0 2006.161.08:06:23.52#ibcon#read 6, iclass 38, count 0 2006.161.08:06:23.52#ibcon#end of sib2, iclass 38, count 0 2006.161.08:06:23.52#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:06:23.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:06:23.52#ibcon#[27=BW32\r\n] 2006.161.08:06:23.52#ibcon#*before write, iclass 38, count 0 2006.161.08:06:23.52#ibcon#enter sib2, iclass 38, count 0 2006.161.08:06:23.52#ibcon#flushed, iclass 38, count 0 2006.161.08:06:23.52#ibcon#about to write, iclass 38, count 0 2006.161.08:06:23.52#ibcon#wrote, iclass 38, count 0 2006.161.08:06:23.52#ibcon#about to read 3, iclass 38, count 0 2006.161.08:06:23.55#ibcon#read 3, iclass 38, count 0 2006.161.08:06:23.55#ibcon#about to read 4, iclass 38, count 0 2006.161.08:06:23.55#ibcon#read 4, iclass 38, count 0 2006.161.08:06:23.55#ibcon#about to read 5, iclass 38, count 0 2006.161.08:06:23.55#ibcon#read 5, iclass 38, count 0 2006.161.08:06:23.55#ibcon#about to read 6, iclass 38, count 0 2006.161.08:06:23.55#ibcon#read 6, iclass 38, count 0 2006.161.08:06:23.55#ibcon#end of sib2, iclass 38, count 0 2006.161.08:06:23.55#ibcon#*after write, iclass 38, count 0 2006.161.08:06:23.55#ibcon#*before return 0, iclass 38, count 0 2006.161.08:06:23.55#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:06:23.55#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:06:23.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:06:23.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:06:23.55$4f8m12a/ifd4f 2006.161.08:06:23.55$ifd4f/lo= 2006.161.08:06:23.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:06:23.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:06:23.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:06:23.55$ifd4f/patch= 2006.161.08:06:23.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:06:23.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:06:23.56$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:06:23.56$4f8m12a/"form=m,16.000,1:2 2006.161.08:06:23.56$4f8m12a/"tpicd 2006.161.08:06:23.56$4f8m12a/echo=off 2006.161.08:06:23.56$4f8m12a/xlog=off 2006.161.08:06:23.56:!2006.161.08:06:50 2006.161.08:06:39.14#trakl#Source acquired 2006.161.08:06:41.14#flagr#flagr/antenna,acquired 2006.161.08:06:50.01:preob 2006.161.08:06:51.14/onsource/TRACKING 2006.161.08:06:51.14:!2006.161.08:07:00 2006.161.08:07:00.00:data_valid=on 2006.161.08:07:00.00:midob 2006.161.08:07:00.14/onsource/TRACKING 2006.161.08:07:00.14/wx/24.01,1002.3,85 2006.161.08:07:00.33/cable/+6.5006E-03 2006.161.08:07:01.42/va/01,08,usb,yes,28,30 2006.161.08:07:01.42/va/02,07,usb,yes,29,30 2006.161.08:07:01.42/va/03,06,usb,yes,30,30 2006.161.08:07:01.42/va/04,07,usb,yes,29,31 2006.161.08:07:01.42/va/05,07,usb,yes,29,31 2006.161.08:07:01.42/va/06,06,usb,yes,28,28 2006.161.08:07:01.42/va/07,06,usb,yes,29,29 2006.161.08:07:01.42/va/08,07,usb,yes,27,27 2006.161.08:07:01.65/valo/01,532.99,yes,locked 2006.161.08:07:01.65/valo/02,572.99,yes,locked 2006.161.08:07:01.65/valo/03,672.99,yes,locked 2006.161.08:07:01.65/valo/04,832.99,yes,locked 2006.161.08:07:01.65/valo/05,652.99,yes,locked 2006.161.08:07:01.65/valo/06,772.99,yes,locked 2006.161.08:07:01.65/valo/07,832.99,yes,locked 2006.161.08:07:01.65/valo/08,852.99,yes,locked 2006.161.08:07:02.74/vb/01,04,usb,yes,29,27 2006.161.08:07:02.74/vb/02,04,usb,yes,30,32 2006.161.08:07:02.74/vb/03,04,usb,yes,27,30 2006.161.08:07:02.74/vb/04,04,usb,yes,28,28 2006.161.08:07:02.74/vb/05,04,usb,yes,26,30 2006.161.08:07:02.74/vb/06,04,usb,yes,27,30 2006.161.08:07:02.74/vb/07,04,usb,yes,29,29 2006.161.08:07:02.74/vb/08,04,usb,yes,27,30 2006.161.08:07:02.98/vblo/01,632.99,yes,locked 2006.161.08:07:02.98/vblo/02,640.99,yes,locked 2006.161.08:07:02.98/vblo/03,656.99,yes,locked 2006.161.08:07:02.98/vblo/04,712.99,yes,locked 2006.161.08:07:02.98/vblo/05,744.99,yes,locked 2006.161.08:07:02.98/vblo/06,752.99,yes,locked 2006.161.08:07:02.98/vblo/07,734.99,yes,locked 2006.161.08:07:02.98/vblo/08,744.99,yes,locked 2006.161.08:07:03.13/vabw/8 2006.161.08:07:03.28/vbbw/8 2006.161.08:07:03.37/xfe/off,on,15.0 2006.161.08:07:03.76/ifatt/23,28,28,28 2006.161.08:07:04.07/fmout-gps/S +4.50E-07 2006.161.08:07:04.15:!2006.161.08:08:00 2006.161.08:08:00.01:data_valid=off 2006.161.08:08:00.02:postob 2006.161.08:08:00.08/cable/+6.4986E-03 2006.161.08:08:00.09/wx/24.00,1002.4,86 2006.161.08:08:01.07/fmout-gps/S +4.51E-07 2006.161.08:08:01.08:scan_name=161-0808,k06161,60 2006.161.08:08:01.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.161.08:08:01.14#flagr#flagr/antenna,new-source 2006.161.08:08:02.14:checkk5 2006.161.08:08:02.57/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:08:02.97/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:08:03.39/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:08:03.82/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:08:04.25/chk_obsdata//k5ts1/T1610807??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:08:04.67/chk_obsdata//k5ts2/T1610807??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:08:05.10/chk_obsdata//k5ts3/T1610807??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:08:05.79/chk_obsdata//k5ts4/T1610807??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:08:06.59/k5log//k5ts1_log_newline 2006.161.08:08:07.32/k5log//k5ts2_log_newline 2006.161.08:08:08.35/k5log//k5ts3_log_newline 2006.161.08:08:09.20/k5log//k5ts4_log_newline 2006.161.08:08:09.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:08:09.23:4f8m12a=2 2006.161.08:08:09.23$4f8m12a/echo=on 2006.161.08:08:09.23$4f8m12a/pcalon 2006.161.08:08:09.23$pcalon/"no phase cal control is implemented here 2006.161.08:08:09.23$4f8m12a/"tpicd=stop 2006.161.08:08:09.23$4f8m12a/vc4f8 2006.161.08:08:09.23$vc4f8/valo=1,532.99 2006.161.08:08:09.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:08:09.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:08:09.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:09.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:09.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:09.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:09.23#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:08:09.23#ibcon#first serial, iclass 7, count 0 2006.161.08:08:09.23#ibcon#enter sib2, iclass 7, count 0 2006.161.08:08:09.23#ibcon#flushed, iclass 7, count 0 2006.161.08:08:09.23#ibcon#about to write, iclass 7, count 0 2006.161.08:08:09.23#ibcon#wrote, iclass 7, count 0 2006.161.08:08:09.23#ibcon#about to read 3, iclass 7, count 0 2006.161.08:08:09.28#ibcon#read 3, iclass 7, count 0 2006.161.08:08:09.28#ibcon#about to read 4, iclass 7, count 0 2006.161.08:08:09.28#ibcon#read 4, iclass 7, count 0 2006.161.08:08:09.28#ibcon#about to read 5, iclass 7, count 0 2006.161.08:08:09.28#ibcon#read 5, iclass 7, count 0 2006.161.08:08:09.28#ibcon#about to read 6, iclass 7, count 0 2006.161.08:08:09.28#ibcon#read 6, iclass 7, count 0 2006.161.08:08:09.28#ibcon#end of sib2, iclass 7, count 0 2006.161.08:08:09.28#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:08:09.28#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:08:09.28#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:08:09.28#ibcon#*before write, iclass 7, count 0 2006.161.08:08:09.28#ibcon#enter sib2, iclass 7, count 0 2006.161.08:08:09.28#ibcon#flushed, iclass 7, count 0 2006.161.08:08:09.28#ibcon#about to write, iclass 7, count 0 2006.161.08:08:09.28#ibcon#wrote, iclass 7, count 0 2006.161.08:08:09.28#ibcon#about to read 3, iclass 7, count 0 2006.161.08:08:09.32#ibcon#read 3, iclass 7, count 0 2006.161.08:08:09.32#ibcon#about to read 4, iclass 7, count 0 2006.161.08:08:09.32#ibcon#read 4, iclass 7, count 0 2006.161.08:08:09.32#ibcon#about to read 5, iclass 7, count 0 2006.161.08:08:09.32#ibcon#read 5, iclass 7, count 0 2006.161.08:08:09.32#ibcon#about to read 6, iclass 7, count 0 2006.161.08:08:09.32#ibcon#read 6, iclass 7, count 0 2006.161.08:08:09.32#ibcon#end of sib2, iclass 7, count 0 2006.161.08:08:09.32#ibcon#*after write, iclass 7, count 0 2006.161.08:08:09.32#ibcon#*before return 0, iclass 7, count 0 2006.161.08:08:09.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:09.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:09.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:08:09.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:08:09.32$vc4f8/va=1,8 2006.161.08:08:09.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:08:09.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:08:09.32#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:09.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:09.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:09.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:09.32#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:08:09.32#ibcon#first serial, iclass 11, count 2 2006.161.08:08:09.32#ibcon#enter sib2, iclass 11, count 2 2006.161.08:08:09.32#ibcon#flushed, iclass 11, count 2 2006.161.08:08:09.32#ibcon#about to write, iclass 11, count 2 2006.161.08:08:09.32#ibcon#wrote, iclass 11, count 2 2006.161.08:08:09.32#ibcon#about to read 3, iclass 11, count 2 2006.161.08:08:09.35#ibcon#read 3, iclass 11, count 2 2006.161.08:08:09.35#ibcon#about to read 4, iclass 11, count 2 2006.161.08:08:09.35#ibcon#read 4, iclass 11, count 2 2006.161.08:08:09.35#ibcon#about to read 5, iclass 11, count 2 2006.161.08:08:09.35#ibcon#read 5, iclass 11, count 2 2006.161.08:08:09.35#ibcon#about to read 6, iclass 11, count 2 2006.161.08:08:09.35#ibcon#read 6, iclass 11, count 2 2006.161.08:08:09.35#ibcon#end of sib2, iclass 11, count 2 2006.161.08:08:09.35#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:08:09.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:08:09.35#ibcon#[25=AT01-08\r\n] 2006.161.08:08:09.35#ibcon#*before write, iclass 11, count 2 2006.161.08:08:09.35#ibcon#enter sib2, iclass 11, count 2 2006.161.08:08:09.35#ibcon#flushed, iclass 11, count 2 2006.161.08:08:09.35#ibcon#about to write, iclass 11, count 2 2006.161.08:08:09.35#ibcon#wrote, iclass 11, count 2 2006.161.08:08:09.35#ibcon#about to read 3, iclass 11, count 2 2006.161.08:08:09.38#ibcon#read 3, iclass 11, count 2 2006.161.08:08:09.38#ibcon#about to read 4, iclass 11, count 2 2006.161.08:08:09.38#ibcon#read 4, iclass 11, count 2 2006.161.08:08:09.38#ibcon#about to read 5, iclass 11, count 2 2006.161.08:08:09.38#ibcon#read 5, iclass 11, count 2 2006.161.08:08:09.38#ibcon#about to read 6, iclass 11, count 2 2006.161.08:08:09.38#ibcon#read 6, iclass 11, count 2 2006.161.08:08:09.38#ibcon#end of sib2, iclass 11, count 2 2006.161.08:08:09.38#ibcon#*after write, iclass 11, count 2 2006.161.08:08:09.38#ibcon#*before return 0, iclass 11, count 2 2006.161.08:08:09.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:09.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:09.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:08:09.38#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:09.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:09.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:09.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:09.50#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:08:09.50#ibcon#first serial, iclass 11, count 0 2006.161.08:08:09.50#ibcon#enter sib2, iclass 11, count 0 2006.161.08:08:09.50#ibcon#flushed, iclass 11, count 0 2006.161.08:08:09.50#ibcon#about to write, iclass 11, count 0 2006.161.08:08:09.50#ibcon#wrote, iclass 11, count 0 2006.161.08:08:09.50#ibcon#about to read 3, iclass 11, count 0 2006.161.08:08:09.52#ibcon#read 3, iclass 11, count 0 2006.161.08:08:09.52#ibcon#about to read 4, iclass 11, count 0 2006.161.08:08:09.52#ibcon#read 4, iclass 11, count 0 2006.161.08:08:09.52#ibcon#about to read 5, iclass 11, count 0 2006.161.08:08:09.52#ibcon#read 5, iclass 11, count 0 2006.161.08:08:09.52#ibcon#about to read 6, iclass 11, count 0 2006.161.08:08:09.52#ibcon#read 6, iclass 11, count 0 2006.161.08:08:09.52#ibcon#end of sib2, iclass 11, count 0 2006.161.08:08:09.52#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:08:09.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:08:09.52#ibcon#[25=USB\r\n] 2006.161.08:08:09.52#ibcon#*before write, iclass 11, count 0 2006.161.08:08:09.52#ibcon#enter sib2, iclass 11, count 0 2006.161.08:08:09.52#ibcon#flushed, iclass 11, count 0 2006.161.08:08:09.52#ibcon#about to write, iclass 11, count 0 2006.161.08:08:09.52#ibcon#wrote, iclass 11, count 0 2006.161.08:08:09.52#ibcon#about to read 3, iclass 11, count 0 2006.161.08:08:09.55#ibcon#read 3, iclass 11, count 0 2006.161.08:08:09.55#ibcon#about to read 4, iclass 11, count 0 2006.161.08:08:09.55#ibcon#read 4, iclass 11, count 0 2006.161.08:08:09.55#ibcon#about to read 5, iclass 11, count 0 2006.161.08:08:09.55#ibcon#read 5, iclass 11, count 0 2006.161.08:08:09.55#ibcon#about to read 6, iclass 11, count 0 2006.161.08:08:09.55#ibcon#read 6, iclass 11, count 0 2006.161.08:08:09.55#ibcon#end of sib2, iclass 11, count 0 2006.161.08:08:09.55#ibcon#*after write, iclass 11, count 0 2006.161.08:08:09.55#ibcon#*before return 0, iclass 11, count 0 2006.161.08:08:09.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:09.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:09.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:08:09.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:08:09.55$vc4f8/valo=2,572.99 2006.161.08:08:09.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:08:09.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:08:09.55#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:09.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:09.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:09.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:09.55#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:08:09.55#ibcon#first serial, iclass 13, count 0 2006.161.08:08:09.55#ibcon#enter sib2, iclass 13, count 0 2006.161.08:08:09.55#ibcon#flushed, iclass 13, count 0 2006.161.08:08:09.55#ibcon#about to write, iclass 13, count 0 2006.161.08:08:09.55#ibcon#wrote, iclass 13, count 0 2006.161.08:08:09.55#ibcon#about to read 3, iclass 13, count 0 2006.161.08:08:09.57#ibcon#read 3, iclass 13, count 0 2006.161.08:08:09.57#ibcon#about to read 4, iclass 13, count 0 2006.161.08:08:09.57#ibcon#read 4, iclass 13, count 0 2006.161.08:08:09.57#ibcon#about to read 5, iclass 13, count 0 2006.161.08:08:09.57#ibcon#read 5, iclass 13, count 0 2006.161.08:08:09.57#ibcon#about to read 6, iclass 13, count 0 2006.161.08:08:09.57#ibcon#read 6, iclass 13, count 0 2006.161.08:08:09.57#ibcon#end of sib2, iclass 13, count 0 2006.161.08:08:09.57#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:08:09.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:08:09.57#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:08:09.57#ibcon#*before write, iclass 13, count 0 2006.161.08:08:09.57#ibcon#enter sib2, iclass 13, count 0 2006.161.08:08:09.57#ibcon#flushed, iclass 13, count 0 2006.161.08:08:09.57#ibcon#about to write, iclass 13, count 0 2006.161.08:08:09.57#ibcon#wrote, iclass 13, count 0 2006.161.08:08:09.57#ibcon#about to read 3, iclass 13, count 0 2006.161.08:08:09.61#ibcon#read 3, iclass 13, count 0 2006.161.08:08:09.61#ibcon#about to read 4, iclass 13, count 0 2006.161.08:08:09.61#ibcon#read 4, iclass 13, count 0 2006.161.08:08:09.61#ibcon#about to read 5, iclass 13, count 0 2006.161.08:08:09.61#ibcon#read 5, iclass 13, count 0 2006.161.08:08:09.61#ibcon#about to read 6, iclass 13, count 0 2006.161.08:08:09.61#ibcon#read 6, iclass 13, count 0 2006.161.08:08:09.61#ibcon#end of sib2, iclass 13, count 0 2006.161.08:08:09.61#ibcon#*after write, iclass 13, count 0 2006.161.08:08:09.61#ibcon#*before return 0, iclass 13, count 0 2006.161.08:08:09.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:09.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:09.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:08:09.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:08:09.61$vc4f8/va=2,7 2006.161.08:08:09.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:08:09.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:08:09.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:09.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:09.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:09.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:09.67#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:08:09.67#ibcon#first serial, iclass 15, count 2 2006.161.08:08:09.67#ibcon#enter sib2, iclass 15, count 2 2006.161.08:08:09.67#ibcon#flushed, iclass 15, count 2 2006.161.08:08:09.67#ibcon#about to write, iclass 15, count 2 2006.161.08:08:09.67#ibcon#wrote, iclass 15, count 2 2006.161.08:08:09.67#ibcon#about to read 3, iclass 15, count 2 2006.161.08:08:09.70#ibcon#read 3, iclass 15, count 2 2006.161.08:08:09.70#ibcon#about to read 4, iclass 15, count 2 2006.161.08:08:09.70#ibcon#read 4, iclass 15, count 2 2006.161.08:08:09.70#ibcon#about to read 5, iclass 15, count 2 2006.161.08:08:09.70#ibcon#read 5, iclass 15, count 2 2006.161.08:08:09.70#ibcon#about to read 6, iclass 15, count 2 2006.161.08:08:09.70#ibcon#read 6, iclass 15, count 2 2006.161.08:08:09.70#ibcon#end of sib2, iclass 15, count 2 2006.161.08:08:09.70#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:08:09.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:08:09.70#ibcon#[25=AT02-07\r\n] 2006.161.08:08:09.70#ibcon#*before write, iclass 15, count 2 2006.161.08:08:09.70#ibcon#enter sib2, iclass 15, count 2 2006.161.08:08:09.70#ibcon#flushed, iclass 15, count 2 2006.161.08:08:09.70#ibcon#about to write, iclass 15, count 2 2006.161.08:08:09.70#ibcon#wrote, iclass 15, count 2 2006.161.08:08:09.70#ibcon#about to read 3, iclass 15, count 2 2006.161.08:08:09.73#ibcon#read 3, iclass 15, count 2 2006.161.08:08:09.73#ibcon#about to read 4, iclass 15, count 2 2006.161.08:08:09.73#ibcon#read 4, iclass 15, count 2 2006.161.08:08:09.73#ibcon#about to read 5, iclass 15, count 2 2006.161.08:08:09.73#ibcon#read 5, iclass 15, count 2 2006.161.08:08:09.73#ibcon#about to read 6, iclass 15, count 2 2006.161.08:08:09.73#ibcon#read 6, iclass 15, count 2 2006.161.08:08:09.73#ibcon#end of sib2, iclass 15, count 2 2006.161.08:08:09.73#ibcon#*after write, iclass 15, count 2 2006.161.08:08:09.73#ibcon#*before return 0, iclass 15, count 2 2006.161.08:08:09.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:09.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:09.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:08:09.73#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:09.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:09.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:09.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:09.85#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:08:09.85#ibcon#first serial, iclass 15, count 0 2006.161.08:08:09.85#ibcon#enter sib2, iclass 15, count 0 2006.161.08:08:09.85#ibcon#flushed, iclass 15, count 0 2006.161.08:08:09.85#ibcon#about to write, iclass 15, count 0 2006.161.08:08:09.85#ibcon#wrote, iclass 15, count 0 2006.161.08:08:09.85#ibcon#about to read 3, iclass 15, count 0 2006.161.08:08:09.87#ibcon#read 3, iclass 15, count 0 2006.161.08:08:09.87#ibcon#about to read 4, iclass 15, count 0 2006.161.08:08:09.87#ibcon#read 4, iclass 15, count 0 2006.161.08:08:09.87#ibcon#about to read 5, iclass 15, count 0 2006.161.08:08:09.87#ibcon#read 5, iclass 15, count 0 2006.161.08:08:09.87#ibcon#about to read 6, iclass 15, count 0 2006.161.08:08:09.87#ibcon#read 6, iclass 15, count 0 2006.161.08:08:09.87#ibcon#end of sib2, iclass 15, count 0 2006.161.08:08:09.87#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:08:09.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:08:09.87#ibcon#[25=USB\r\n] 2006.161.08:08:09.87#ibcon#*before write, iclass 15, count 0 2006.161.08:08:09.87#ibcon#enter sib2, iclass 15, count 0 2006.161.08:08:09.87#ibcon#flushed, iclass 15, count 0 2006.161.08:08:09.87#ibcon#about to write, iclass 15, count 0 2006.161.08:08:09.87#ibcon#wrote, iclass 15, count 0 2006.161.08:08:09.87#ibcon#about to read 3, iclass 15, count 0 2006.161.08:08:09.90#ibcon#read 3, iclass 15, count 0 2006.161.08:08:09.90#ibcon#about to read 4, iclass 15, count 0 2006.161.08:08:09.90#ibcon#read 4, iclass 15, count 0 2006.161.08:08:09.90#ibcon#about to read 5, iclass 15, count 0 2006.161.08:08:09.90#ibcon#read 5, iclass 15, count 0 2006.161.08:08:09.90#ibcon#about to read 6, iclass 15, count 0 2006.161.08:08:09.90#ibcon#read 6, iclass 15, count 0 2006.161.08:08:09.90#ibcon#end of sib2, iclass 15, count 0 2006.161.08:08:09.90#ibcon#*after write, iclass 15, count 0 2006.161.08:08:09.90#ibcon#*before return 0, iclass 15, count 0 2006.161.08:08:09.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:09.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:09.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:08:09.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:08:09.90$vc4f8/valo=3,672.99 2006.161.08:08:09.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:08:09.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:08:09.90#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:09.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:09.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:09.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:09.90#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:08:09.90#ibcon#first serial, iclass 17, count 0 2006.161.08:08:09.90#ibcon#enter sib2, iclass 17, count 0 2006.161.08:08:09.90#ibcon#flushed, iclass 17, count 0 2006.161.08:08:09.90#ibcon#about to write, iclass 17, count 0 2006.161.08:08:09.90#ibcon#wrote, iclass 17, count 0 2006.161.08:08:09.90#ibcon#about to read 3, iclass 17, count 0 2006.161.08:08:09.92#ibcon#read 3, iclass 17, count 0 2006.161.08:08:09.92#ibcon#about to read 4, iclass 17, count 0 2006.161.08:08:09.92#ibcon#read 4, iclass 17, count 0 2006.161.08:08:09.92#ibcon#about to read 5, iclass 17, count 0 2006.161.08:08:09.92#ibcon#read 5, iclass 17, count 0 2006.161.08:08:09.92#ibcon#about to read 6, iclass 17, count 0 2006.161.08:08:09.92#ibcon#read 6, iclass 17, count 0 2006.161.08:08:09.92#ibcon#end of sib2, iclass 17, count 0 2006.161.08:08:09.92#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:08:09.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:08:09.92#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:08:09.92#ibcon#*before write, iclass 17, count 0 2006.161.08:08:09.92#ibcon#enter sib2, iclass 17, count 0 2006.161.08:08:09.92#ibcon#flushed, iclass 17, count 0 2006.161.08:08:09.92#ibcon#about to write, iclass 17, count 0 2006.161.08:08:09.92#ibcon#wrote, iclass 17, count 0 2006.161.08:08:09.92#ibcon#about to read 3, iclass 17, count 0 2006.161.08:08:09.96#ibcon#read 3, iclass 17, count 0 2006.161.08:08:09.96#ibcon#about to read 4, iclass 17, count 0 2006.161.08:08:09.96#ibcon#read 4, iclass 17, count 0 2006.161.08:08:09.96#ibcon#about to read 5, iclass 17, count 0 2006.161.08:08:09.96#ibcon#read 5, iclass 17, count 0 2006.161.08:08:09.96#ibcon#about to read 6, iclass 17, count 0 2006.161.08:08:09.96#ibcon#read 6, iclass 17, count 0 2006.161.08:08:09.96#ibcon#end of sib2, iclass 17, count 0 2006.161.08:08:09.96#ibcon#*after write, iclass 17, count 0 2006.161.08:08:09.96#ibcon#*before return 0, iclass 17, count 0 2006.161.08:08:09.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:09.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:09.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:08:09.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:08:09.96$vc4f8/va=3,6 2006.161.08:08:09.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:08:09.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:08:09.96#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:09.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:10.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:10.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:10.02#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:08:10.02#ibcon#first serial, iclass 19, count 2 2006.161.08:08:10.02#ibcon#enter sib2, iclass 19, count 2 2006.161.08:08:10.02#ibcon#flushed, iclass 19, count 2 2006.161.08:08:10.02#ibcon#about to write, iclass 19, count 2 2006.161.08:08:10.02#ibcon#wrote, iclass 19, count 2 2006.161.08:08:10.02#ibcon#about to read 3, iclass 19, count 2 2006.161.08:08:10.04#ibcon#read 3, iclass 19, count 2 2006.161.08:08:10.04#ibcon#about to read 4, iclass 19, count 2 2006.161.08:08:10.04#ibcon#read 4, iclass 19, count 2 2006.161.08:08:10.04#ibcon#about to read 5, iclass 19, count 2 2006.161.08:08:10.04#ibcon#read 5, iclass 19, count 2 2006.161.08:08:10.04#ibcon#about to read 6, iclass 19, count 2 2006.161.08:08:10.04#ibcon#read 6, iclass 19, count 2 2006.161.08:08:10.04#ibcon#end of sib2, iclass 19, count 2 2006.161.08:08:10.04#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:08:10.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:08:10.04#ibcon#[25=AT03-06\r\n] 2006.161.08:08:10.04#ibcon#*before write, iclass 19, count 2 2006.161.08:08:10.04#ibcon#enter sib2, iclass 19, count 2 2006.161.08:08:10.04#ibcon#flushed, iclass 19, count 2 2006.161.08:08:10.04#ibcon#about to write, iclass 19, count 2 2006.161.08:08:10.04#ibcon#wrote, iclass 19, count 2 2006.161.08:08:10.04#ibcon#about to read 3, iclass 19, count 2 2006.161.08:08:10.07#ibcon#read 3, iclass 19, count 2 2006.161.08:08:10.07#ibcon#about to read 4, iclass 19, count 2 2006.161.08:08:10.07#ibcon#read 4, iclass 19, count 2 2006.161.08:08:10.07#ibcon#about to read 5, iclass 19, count 2 2006.161.08:08:10.07#ibcon#read 5, iclass 19, count 2 2006.161.08:08:10.07#ibcon#about to read 6, iclass 19, count 2 2006.161.08:08:10.07#ibcon#read 6, iclass 19, count 2 2006.161.08:08:10.07#ibcon#end of sib2, iclass 19, count 2 2006.161.08:08:10.07#ibcon#*after write, iclass 19, count 2 2006.161.08:08:10.07#ibcon#*before return 0, iclass 19, count 2 2006.161.08:08:10.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:10.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:10.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:08:10.07#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:10.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:10.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:10.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:10.19#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:08:10.19#ibcon#first serial, iclass 19, count 0 2006.161.08:08:10.19#ibcon#enter sib2, iclass 19, count 0 2006.161.08:08:10.19#ibcon#flushed, iclass 19, count 0 2006.161.08:08:10.19#ibcon#about to write, iclass 19, count 0 2006.161.08:08:10.19#ibcon#wrote, iclass 19, count 0 2006.161.08:08:10.19#ibcon#about to read 3, iclass 19, count 0 2006.161.08:08:10.21#ibcon#read 3, iclass 19, count 0 2006.161.08:08:10.21#ibcon#about to read 4, iclass 19, count 0 2006.161.08:08:10.21#ibcon#read 4, iclass 19, count 0 2006.161.08:08:10.21#ibcon#about to read 5, iclass 19, count 0 2006.161.08:08:10.21#ibcon#read 5, iclass 19, count 0 2006.161.08:08:10.21#ibcon#about to read 6, iclass 19, count 0 2006.161.08:08:10.21#ibcon#read 6, iclass 19, count 0 2006.161.08:08:10.21#ibcon#end of sib2, iclass 19, count 0 2006.161.08:08:10.21#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:08:10.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:08:10.21#ibcon#[25=USB\r\n] 2006.161.08:08:10.21#ibcon#*before write, iclass 19, count 0 2006.161.08:08:10.21#ibcon#enter sib2, iclass 19, count 0 2006.161.08:08:10.21#ibcon#flushed, iclass 19, count 0 2006.161.08:08:10.21#ibcon#about to write, iclass 19, count 0 2006.161.08:08:10.21#ibcon#wrote, iclass 19, count 0 2006.161.08:08:10.21#ibcon#about to read 3, iclass 19, count 0 2006.161.08:08:10.24#ibcon#read 3, iclass 19, count 0 2006.161.08:08:10.24#ibcon#about to read 4, iclass 19, count 0 2006.161.08:08:10.24#ibcon#read 4, iclass 19, count 0 2006.161.08:08:10.24#ibcon#about to read 5, iclass 19, count 0 2006.161.08:08:10.24#ibcon#read 5, iclass 19, count 0 2006.161.08:08:10.24#ibcon#about to read 6, iclass 19, count 0 2006.161.08:08:10.24#ibcon#read 6, iclass 19, count 0 2006.161.08:08:10.24#ibcon#end of sib2, iclass 19, count 0 2006.161.08:08:10.24#ibcon#*after write, iclass 19, count 0 2006.161.08:08:10.24#ibcon#*before return 0, iclass 19, count 0 2006.161.08:08:10.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:10.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:10.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:08:10.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:08:10.24$vc4f8/valo=4,832.99 2006.161.08:08:10.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:08:10.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:08:10.24#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:10.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:10.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:10.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:10.24#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:08:10.24#ibcon#first serial, iclass 21, count 0 2006.161.08:08:10.24#ibcon#enter sib2, iclass 21, count 0 2006.161.08:08:10.24#ibcon#flushed, iclass 21, count 0 2006.161.08:08:10.24#ibcon#about to write, iclass 21, count 0 2006.161.08:08:10.24#ibcon#wrote, iclass 21, count 0 2006.161.08:08:10.24#ibcon#about to read 3, iclass 21, count 0 2006.161.08:08:10.26#ibcon#read 3, iclass 21, count 0 2006.161.08:08:10.26#ibcon#about to read 4, iclass 21, count 0 2006.161.08:08:10.26#ibcon#read 4, iclass 21, count 0 2006.161.08:08:10.26#ibcon#about to read 5, iclass 21, count 0 2006.161.08:08:10.26#ibcon#read 5, iclass 21, count 0 2006.161.08:08:10.26#ibcon#about to read 6, iclass 21, count 0 2006.161.08:08:10.26#ibcon#read 6, iclass 21, count 0 2006.161.08:08:10.26#ibcon#end of sib2, iclass 21, count 0 2006.161.08:08:10.26#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:08:10.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:08:10.26#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:08:10.26#ibcon#*before write, iclass 21, count 0 2006.161.08:08:10.26#ibcon#enter sib2, iclass 21, count 0 2006.161.08:08:10.26#ibcon#flushed, iclass 21, count 0 2006.161.08:08:10.26#ibcon#about to write, iclass 21, count 0 2006.161.08:08:10.26#ibcon#wrote, iclass 21, count 0 2006.161.08:08:10.26#ibcon#about to read 3, iclass 21, count 0 2006.161.08:08:10.30#ibcon#read 3, iclass 21, count 0 2006.161.08:08:10.30#ibcon#about to read 4, iclass 21, count 0 2006.161.08:08:10.30#ibcon#read 4, iclass 21, count 0 2006.161.08:08:10.30#ibcon#about to read 5, iclass 21, count 0 2006.161.08:08:10.30#ibcon#read 5, iclass 21, count 0 2006.161.08:08:10.30#ibcon#about to read 6, iclass 21, count 0 2006.161.08:08:10.30#ibcon#read 6, iclass 21, count 0 2006.161.08:08:10.30#ibcon#end of sib2, iclass 21, count 0 2006.161.08:08:10.30#ibcon#*after write, iclass 21, count 0 2006.161.08:08:10.30#ibcon#*before return 0, iclass 21, count 0 2006.161.08:08:10.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:10.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:10.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:08:10.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:08:10.30$vc4f8/va=4,7 2006.161.08:08:10.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:08:10.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:08:10.30#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:10.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:10.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:10.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:10.36#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:08:10.36#ibcon#first serial, iclass 23, count 2 2006.161.08:08:10.36#ibcon#enter sib2, iclass 23, count 2 2006.161.08:08:10.36#ibcon#flushed, iclass 23, count 2 2006.161.08:08:10.36#ibcon#about to write, iclass 23, count 2 2006.161.08:08:10.36#ibcon#wrote, iclass 23, count 2 2006.161.08:08:10.36#ibcon#about to read 3, iclass 23, count 2 2006.161.08:08:10.38#ibcon#read 3, iclass 23, count 2 2006.161.08:08:10.38#ibcon#about to read 4, iclass 23, count 2 2006.161.08:08:10.38#ibcon#read 4, iclass 23, count 2 2006.161.08:08:10.38#ibcon#about to read 5, iclass 23, count 2 2006.161.08:08:10.38#ibcon#read 5, iclass 23, count 2 2006.161.08:08:10.38#ibcon#about to read 6, iclass 23, count 2 2006.161.08:08:10.38#ibcon#read 6, iclass 23, count 2 2006.161.08:08:10.38#ibcon#end of sib2, iclass 23, count 2 2006.161.08:08:10.38#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:08:10.38#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:08:10.38#ibcon#[25=AT04-07\r\n] 2006.161.08:08:10.38#ibcon#*before write, iclass 23, count 2 2006.161.08:08:10.38#ibcon#enter sib2, iclass 23, count 2 2006.161.08:08:10.38#ibcon#flushed, iclass 23, count 2 2006.161.08:08:10.38#ibcon#about to write, iclass 23, count 2 2006.161.08:08:10.38#ibcon#wrote, iclass 23, count 2 2006.161.08:08:10.38#ibcon#about to read 3, iclass 23, count 2 2006.161.08:08:10.41#ibcon#read 3, iclass 23, count 2 2006.161.08:08:10.41#ibcon#about to read 4, iclass 23, count 2 2006.161.08:08:10.41#ibcon#read 4, iclass 23, count 2 2006.161.08:08:10.41#ibcon#about to read 5, iclass 23, count 2 2006.161.08:08:10.41#ibcon#read 5, iclass 23, count 2 2006.161.08:08:10.41#ibcon#about to read 6, iclass 23, count 2 2006.161.08:08:10.41#ibcon#read 6, iclass 23, count 2 2006.161.08:08:10.41#ibcon#end of sib2, iclass 23, count 2 2006.161.08:08:10.41#ibcon#*after write, iclass 23, count 2 2006.161.08:08:10.41#ibcon#*before return 0, iclass 23, count 2 2006.161.08:08:10.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:10.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:10.41#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:08:10.41#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:10.41#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:10.53#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:10.53#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:10.53#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:08:10.53#ibcon#first serial, iclass 23, count 0 2006.161.08:08:10.53#ibcon#enter sib2, iclass 23, count 0 2006.161.08:08:10.53#ibcon#flushed, iclass 23, count 0 2006.161.08:08:10.53#ibcon#about to write, iclass 23, count 0 2006.161.08:08:10.53#ibcon#wrote, iclass 23, count 0 2006.161.08:08:10.53#ibcon#about to read 3, iclass 23, count 0 2006.161.08:08:10.55#ibcon#read 3, iclass 23, count 0 2006.161.08:08:10.55#ibcon#about to read 4, iclass 23, count 0 2006.161.08:08:10.55#ibcon#read 4, iclass 23, count 0 2006.161.08:08:10.55#ibcon#about to read 5, iclass 23, count 0 2006.161.08:08:10.55#ibcon#read 5, iclass 23, count 0 2006.161.08:08:10.55#ibcon#about to read 6, iclass 23, count 0 2006.161.08:08:10.55#ibcon#read 6, iclass 23, count 0 2006.161.08:08:10.55#ibcon#end of sib2, iclass 23, count 0 2006.161.08:08:10.55#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:08:10.55#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:08:10.55#ibcon#[25=USB\r\n] 2006.161.08:08:10.55#ibcon#*before write, iclass 23, count 0 2006.161.08:08:10.55#ibcon#enter sib2, iclass 23, count 0 2006.161.08:08:10.55#ibcon#flushed, iclass 23, count 0 2006.161.08:08:10.55#ibcon#about to write, iclass 23, count 0 2006.161.08:08:10.55#ibcon#wrote, iclass 23, count 0 2006.161.08:08:10.55#ibcon#about to read 3, iclass 23, count 0 2006.161.08:08:10.58#ibcon#read 3, iclass 23, count 0 2006.161.08:08:10.58#ibcon#about to read 4, iclass 23, count 0 2006.161.08:08:10.58#ibcon#read 4, iclass 23, count 0 2006.161.08:08:10.58#ibcon#about to read 5, iclass 23, count 0 2006.161.08:08:10.58#ibcon#read 5, iclass 23, count 0 2006.161.08:08:10.58#ibcon#about to read 6, iclass 23, count 0 2006.161.08:08:10.58#ibcon#read 6, iclass 23, count 0 2006.161.08:08:10.58#ibcon#end of sib2, iclass 23, count 0 2006.161.08:08:10.58#ibcon#*after write, iclass 23, count 0 2006.161.08:08:10.58#ibcon#*before return 0, iclass 23, count 0 2006.161.08:08:10.58#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:10.58#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:10.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:08:10.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:08:10.58$vc4f8/valo=5,652.99 2006.161.08:08:10.58#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:08:10.58#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:08:10.58#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:10.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:10.58#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:10.58#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:10.58#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:08:10.58#ibcon#first serial, iclass 25, count 0 2006.161.08:08:10.58#ibcon#enter sib2, iclass 25, count 0 2006.161.08:08:10.58#ibcon#flushed, iclass 25, count 0 2006.161.08:08:10.58#ibcon#about to write, iclass 25, count 0 2006.161.08:08:10.58#ibcon#wrote, iclass 25, count 0 2006.161.08:08:10.58#ibcon#about to read 3, iclass 25, count 0 2006.161.08:08:10.60#ibcon#read 3, iclass 25, count 0 2006.161.08:08:10.60#ibcon#about to read 4, iclass 25, count 0 2006.161.08:08:10.60#ibcon#read 4, iclass 25, count 0 2006.161.08:08:10.60#ibcon#about to read 5, iclass 25, count 0 2006.161.08:08:10.60#ibcon#read 5, iclass 25, count 0 2006.161.08:08:10.60#ibcon#about to read 6, iclass 25, count 0 2006.161.08:08:10.60#ibcon#read 6, iclass 25, count 0 2006.161.08:08:10.60#ibcon#end of sib2, iclass 25, count 0 2006.161.08:08:10.60#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:08:10.60#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:08:10.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:08:10.60#ibcon#*before write, iclass 25, count 0 2006.161.08:08:10.60#ibcon#enter sib2, iclass 25, count 0 2006.161.08:08:10.60#ibcon#flushed, iclass 25, count 0 2006.161.08:08:10.60#ibcon#about to write, iclass 25, count 0 2006.161.08:08:10.60#ibcon#wrote, iclass 25, count 0 2006.161.08:08:10.60#ibcon#about to read 3, iclass 25, count 0 2006.161.08:08:10.64#ibcon#read 3, iclass 25, count 0 2006.161.08:08:10.64#ibcon#about to read 4, iclass 25, count 0 2006.161.08:08:10.64#ibcon#read 4, iclass 25, count 0 2006.161.08:08:10.64#ibcon#about to read 5, iclass 25, count 0 2006.161.08:08:10.64#ibcon#read 5, iclass 25, count 0 2006.161.08:08:10.64#ibcon#about to read 6, iclass 25, count 0 2006.161.08:08:10.64#ibcon#read 6, iclass 25, count 0 2006.161.08:08:10.64#ibcon#end of sib2, iclass 25, count 0 2006.161.08:08:10.64#ibcon#*after write, iclass 25, count 0 2006.161.08:08:10.64#ibcon#*before return 0, iclass 25, count 0 2006.161.08:08:10.64#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:10.64#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:10.64#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:08:10.64#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:08:10.64$vc4f8/va=5,7 2006.161.08:08:10.64#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:08:10.64#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:08:10.64#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:10.64#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:10.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:10.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:10.70#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:08:10.70#ibcon#first serial, iclass 27, count 2 2006.161.08:08:10.70#ibcon#enter sib2, iclass 27, count 2 2006.161.08:08:10.70#ibcon#flushed, iclass 27, count 2 2006.161.08:08:10.70#ibcon#about to write, iclass 27, count 2 2006.161.08:08:10.70#ibcon#wrote, iclass 27, count 2 2006.161.08:08:10.70#ibcon#about to read 3, iclass 27, count 2 2006.161.08:08:10.72#ibcon#read 3, iclass 27, count 2 2006.161.08:08:10.72#ibcon#about to read 4, iclass 27, count 2 2006.161.08:08:10.72#ibcon#read 4, iclass 27, count 2 2006.161.08:08:10.72#ibcon#about to read 5, iclass 27, count 2 2006.161.08:08:10.72#ibcon#read 5, iclass 27, count 2 2006.161.08:08:10.72#ibcon#about to read 6, iclass 27, count 2 2006.161.08:08:10.72#ibcon#read 6, iclass 27, count 2 2006.161.08:08:10.72#ibcon#end of sib2, iclass 27, count 2 2006.161.08:08:10.72#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:08:10.72#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:08:10.72#ibcon#[25=AT05-07\r\n] 2006.161.08:08:10.72#ibcon#*before write, iclass 27, count 2 2006.161.08:08:10.72#ibcon#enter sib2, iclass 27, count 2 2006.161.08:08:10.72#ibcon#flushed, iclass 27, count 2 2006.161.08:08:10.72#ibcon#about to write, iclass 27, count 2 2006.161.08:08:10.72#ibcon#wrote, iclass 27, count 2 2006.161.08:08:10.72#ibcon#about to read 3, iclass 27, count 2 2006.161.08:08:10.75#ibcon#read 3, iclass 27, count 2 2006.161.08:08:10.75#ibcon#about to read 4, iclass 27, count 2 2006.161.08:08:10.75#ibcon#read 4, iclass 27, count 2 2006.161.08:08:10.75#ibcon#about to read 5, iclass 27, count 2 2006.161.08:08:10.75#ibcon#read 5, iclass 27, count 2 2006.161.08:08:10.75#ibcon#about to read 6, iclass 27, count 2 2006.161.08:08:10.75#ibcon#read 6, iclass 27, count 2 2006.161.08:08:10.75#ibcon#end of sib2, iclass 27, count 2 2006.161.08:08:10.75#ibcon#*after write, iclass 27, count 2 2006.161.08:08:10.75#ibcon#*before return 0, iclass 27, count 2 2006.161.08:08:10.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:10.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:10.75#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:08:10.75#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:10.75#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:10.87#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:10.87#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:10.87#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:08:10.87#ibcon#first serial, iclass 27, count 0 2006.161.08:08:10.87#ibcon#enter sib2, iclass 27, count 0 2006.161.08:08:10.87#ibcon#flushed, iclass 27, count 0 2006.161.08:08:10.87#ibcon#about to write, iclass 27, count 0 2006.161.08:08:10.87#ibcon#wrote, iclass 27, count 0 2006.161.08:08:10.87#ibcon#about to read 3, iclass 27, count 0 2006.161.08:08:10.89#ibcon#read 3, iclass 27, count 0 2006.161.08:08:10.89#ibcon#about to read 4, iclass 27, count 0 2006.161.08:08:10.89#ibcon#read 4, iclass 27, count 0 2006.161.08:08:10.89#ibcon#about to read 5, iclass 27, count 0 2006.161.08:08:10.89#ibcon#read 5, iclass 27, count 0 2006.161.08:08:10.89#ibcon#about to read 6, iclass 27, count 0 2006.161.08:08:10.89#ibcon#read 6, iclass 27, count 0 2006.161.08:08:10.89#ibcon#end of sib2, iclass 27, count 0 2006.161.08:08:10.89#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:08:10.89#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:08:10.89#ibcon#[25=USB\r\n] 2006.161.08:08:10.89#ibcon#*before write, iclass 27, count 0 2006.161.08:08:10.89#ibcon#enter sib2, iclass 27, count 0 2006.161.08:08:10.89#ibcon#flushed, iclass 27, count 0 2006.161.08:08:10.89#ibcon#about to write, iclass 27, count 0 2006.161.08:08:10.89#ibcon#wrote, iclass 27, count 0 2006.161.08:08:10.89#ibcon#about to read 3, iclass 27, count 0 2006.161.08:08:10.92#ibcon#read 3, iclass 27, count 0 2006.161.08:08:10.92#ibcon#about to read 4, iclass 27, count 0 2006.161.08:08:10.92#ibcon#read 4, iclass 27, count 0 2006.161.08:08:10.92#ibcon#about to read 5, iclass 27, count 0 2006.161.08:08:10.92#ibcon#read 5, iclass 27, count 0 2006.161.08:08:10.92#ibcon#about to read 6, iclass 27, count 0 2006.161.08:08:10.92#ibcon#read 6, iclass 27, count 0 2006.161.08:08:10.92#ibcon#end of sib2, iclass 27, count 0 2006.161.08:08:10.92#ibcon#*after write, iclass 27, count 0 2006.161.08:08:10.92#ibcon#*before return 0, iclass 27, count 0 2006.161.08:08:10.92#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:10.92#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:10.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:08:10.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:08:10.92$vc4f8/valo=6,772.99 2006.161.08:08:10.92#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:08:10.92#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:08:10.92#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:10.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:10.92#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:10.92#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:10.92#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:08:10.92#ibcon#first serial, iclass 29, count 0 2006.161.08:08:10.92#ibcon#enter sib2, iclass 29, count 0 2006.161.08:08:10.92#ibcon#flushed, iclass 29, count 0 2006.161.08:08:10.92#ibcon#about to write, iclass 29, count 0 2006.161.08:08:10.92#ibcon#wrote, iclass 29, count 0 2006.161.08:08:10.92#ibcon#about to read 3, iclass 29, count 0 2006.161.08:08:10.94#ibcon#read 3, iclass 29, count 0 2006.161.08:08:10.94#ibcon#about to read 4, iclass 29, count 0 2006.161.08:08:10.94#ibcon#read 4, iclass 29, count 0 2006.161.08:08:10.94#ibcon#about to read 5, iclass 29, count 0 2006.161.08:08:10.94#ibcon#read 5, iclass 29, count 0 2006.161.08:08:10.94#ibcon#about to read 6, iclass 29, count 0 2006.161.08:08:10.94#ibcon#read 6, iclass 29, count 0 2006.161.08:08:10.94#ibcon#end of sib2, iclass 29, count 0 2006.161.08:08:10.94#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:08:10.94#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:08:10.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:08:10.94#ibcon#*before write, iclass 29, count 0 2006.161.08:08:10.94#ibcon#enter sib2, iclass 29, count 0 2006.161.08:08:10.94#ibcon#flushed, iclass 29, count 0 2006.161.08:08:10.94#ibcon#about to write, iclass 29, count 0 2006.161.08:08:10.94#ibcon#wrote, iclass 29, count 0 2006.161.08:08:10.94#ibcon#about to read 3, iclass 29, count 0 2006.161.08:08:10.98#ibcon#read 3, iclass 29, count 0 2006.161.08:08:10.98#ibcon#about to read 4, iclass 29, count 0 2006.161.08:08:10.98#ibcon#read 4, iclass 29, count 0 2006.161.08:08:10.98#ibcon#about to read 5, iclass 29, count 0 2006.161.08:08:10.98#ibcon#read 5, iclass 29, count 0 2006.161.08:08:10.98#ibcon#about to read 6, iclass 29, count 0 2006.161.08:08:10.98#ibcon#read 6, iclass 29, count 0 2006.161.08:08:10.98#ibcon#end of sib2, iclass 29, count 0 2006.161.08:08:10.98#ibcon#*after write, iclass 29, count 0 2006.161.08:08:10.98#ibcon#*before return 0, iclass 29, count 0 2006.161.08:08:10.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:10.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:10.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:08:10.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:08:10.98$vc4f8/va=6,6 2006.161.08:08:10.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.08:08:10.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.08:08:10.98#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:10.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:11.04#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:11.04#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:11.04#ibcon#enter wrdev, iclass 31, count 2 2006.161.08:08:11.04#ibcon#first serial, iclass 31, count 2 2006.161.08:08:11.04#ibcon#enter sib2, iclass 31, count 2 2006.161.08:08:11.04#ibcon#flushed, iclass 31, count 2 2006.161.08:08:11.04#ibcon#about to write, iclass 31, count 2 2006.161.08:08:11.04#ibcon#wrote, iclass 31, count 2 2006.161.08:08:11.04#ibcon#about to read 3, iclass 31, count 2 2006.161.08:08:11.06#ibcon#read 3, iclass 31, count 2 2006.161.08:08:11.06#ibcon#about to read 4, iclass 31, count 2 2006.161.08:08:11.06#ibcon#read 4, iclass 31, count 2 2006.161.08:08:11.06#ibcon#about to read 5, iclass 31, count 2 2006.161.08:08:11.06#ibcon#read 5, iclass 31, count 2 2006.161.08:08:11.06#ibcon#about to read 6, iclass 31, count 2 2006.161.08:08:11.06#ibcon#read 6, iclass 31, count 2 2006.161.08:08:11.06#ibcon#end of sib2, iclass 31, count 2 2006.161.08:08:11.06#ibcon#*mode == 0, iclass 31, count 2 2006.161.08:08:11.06#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.08:08:11.06#ibcon#[25=AT06-06\r\n] 2006.161.08:08:11.06#ibcon#*before write, iclass 31, count 2 2006.161.08:08:11.06#ibcon#enter sib2, iclass 31, count 2 2006.161.08:08:11.06#ibcon#flushed, iclass 31, count 2 2006.161.08:08:11.06#ibcon#about to write, iclass 31, count 2 2006.161.08:08:11.06#ibcon#wrote, iclass 31, count 2 2006.161.08:08:11.06#ibcon#about to read 3, iclass 31, count 2 2006.161.08:08:11.09#ibcon#read 3, iclass 31, count 2 2006.161.08:08:11.09#ibcon#about to read 4, iclass 31, count 2 2006.161.08:08:11.09#ibcon#read 4, iclass 31, count 2 2006.161.08:08:11.09#ibcon#about to read 5, iclass 31, count 2 2006.161.08:08:11.09#ibcon#read 5, iclass 31, count 2 2006.161.08:08:11.09#ibcon#about to read 6, iclass 31, count 2 2006.161.08:08:11.09#ibcon#read 6, iclass 31, count 2 2006.161.08:08:11.09#ibcon#end of sib2, iclass 31, count 2 2006.161.08:08:11.09#ibcon#*after write, iclass 31, count 2 2006.161.08:08:11.09#ibcon#*before return 0, iclass 31, count 2 2006.161.08:08:11.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:11.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:11.09#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.08:08:11.09#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:11.09#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:08:11.21#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:08:11.21#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:08:11.21#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:08:11.21#ibcon#first serial, iclass 31, count 0 2006.161.08:08:11.21#ibcon#enter sib2, iclass 31, count 0 2006.161.08:08:11.21#ibcon#flushed, iclass 31, count 0 2006.161.08:08:11.21#ibcon#about to write, iclass 31, count 0 2006.161.08:08:11.21#ibcon#wrote, iclass 31, count 0 2006.161.08:08:11.21#ibcon#about to read 3, iclass 31, count 0 2006.161.08:08:11.23#ibcon#read 3, iclass 31, count 0 2006.161.08:08:11.23#ibcon#about to read 4, iclass 31, count 0 2006.161.08:08:11.23#ibcon#read 4, iclass 31, count 0 2006.161.08:08:11.23#ibcon#about to read 5, iclass 31, count 0 2006.161.08:08:11.23#ibcon#read 5, iclass 31, count 0 2006.161.08:08:11.23#ibcon#about to read 6, iclass 31, count 0 2006.161.08:08:11.23#ibcon#read 6, iclass 31, count 0 2006.161.08:08:11.23#ibcon#end of sib2, iclass 31, count 0 2006.161.08:08:11.23#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:08:11.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:08:11.23#ibcon#[25=USB\r\n] 2006.161.08:08:11.23#ibcon#*before write, iclass 31, count 0 2006.161.08:08:11.23#ibcon#enter sib2, iclass 31, count 0 2006.161.08:08:11.23#ibcon#flushed, iclass 31, count 0 2006.161.08:08:11.23#ibcon#about to write, iclass 31, count 0 2006.161.08:08:11.23#ibcon#wrote, iclass 31, count 0 2006.161.08:08:11.23#ibcon#about to read 3, iclass 31, count 0 2006.161.08:08:11.26#ibcon#read 3, iclass 31, count 0 2006.161.08:08:11.26#ibcon#about to read 4, iclass 31, count 0 2006.161.08:08:11.26#ibcon#read 4, iclass 31, count 0 2006.161.08:08:11.26#ibcon#about to read 5, iclass 31, count 0 2006.161.08:08:11.26#ibcon#read 5, iclass 31, count 0 2006.161.08:08:11.26#ibcon#about to read 6, iclass 31, count 0 2006.161.08:08:11.26#ibcon#read 6, iclass 31, count 0 2006.161.08:08:11.26#ibcon#end of sib2, iclass 31, count 0 2006.161.08:08:11.26#ibcon#*after write, iclass 31, count 0 2006.161.08:08:11.26#ibcon#*before return 0, iclass 31, count 0 2006.161.08:08:11.26#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:08:11.26#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:08:11.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:08:11.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:08:11.26$vc4f8/valo=7,832.99 2006.161.08:08:11.26#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.08:08:11.26#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.08:08:11.26#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:11.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:08:11.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:08:11.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:08:11.26#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:08:11.26#ibcon#first serial, iclass 33, count 0 2006.161.08:08:11.26#ibcon#enter sib2, iclass 33, count 0 2006.161.08:08:11.26#ibcon#flushed, iclass 33, count 0 2006.161.08:08:11.26#ibcon#about to write, iclass 33, count 0 2006.161.08:08:11.26#ibcon#wrote, iclass 33, count 0 2006.161.08:08:11.26#ibcon#about to read 3, iclass 33, count 0 2006.161.08:08:11.28#ibcon#read 3, iclass 33, count 0 2006.161.08:08:11.28#ibcon#about to read 4, iclass 33, count 0 2006.161.08:08:11.28#ibcon#read 4, iclass 33, count 0 2006.161.08:08:11.28#ibcon#about to read 5, iclass 33, count 0 2006.161.08:08:11.28#ibcon#read 5, iclass 33, count 0 2006.161.08:08:11.28#ibcon#about to read 6, iclass 33, count 0 2006.161.08:08:11.28#ibcon#read 6, iclass 33, count 0 2006.161.08:08:11.28#ibcon#end of sib2, iclass 33, count 0 2006.161.08:08:11.28#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:08:11.28#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:08:11.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:08:11.28#ibcon#*before write, iclass 33, count 0 2006.161.08:08:11.28#ibcon#enter sib2, iclass 33, count 0 2006.161.08:08:11.28#ibcon#flushed, iclass 33, count 0 2006.161.08:08:11.28#ibcon#about to write, iclass 33, count 0 2006.161.08:08:11.28#ibcon#wrote, iclass 33, count 0 2006.161.08:08:11.28#ibcon#about to read 3, iclass 33, count 0 2006.161.08:08:11.32#ibcon#read 3, iclass 33, count 0 2006.161.08:08:11.32#ibcon#about to read 4, iclass 33, count 0 2006.161.08:08:11.32#ibcon#read 4, iclass 33, count 0 2006.161.08:08:11.32#ibcon#about to read 5, iclass 33, count 0 2006.161.08:08:11.32#ibcon#read 5, iclass 33, count 0 2006.161.08:08:11.32#ibcon#about to read 6, iclass 33, count 0 2006.161.08:08:11.32#ibcon#read 6, iclass 33, count 0 2006.161.08:08:11.32#ibcon#end of sib2, iclass 33, count 0 2006.161.08:08:11.32#ibcon#*after write, iclass 33, count 0 2006.161.08:08:11.32#ibcon#*before return 0, iclass 33, count 0 2006.161.08:08:11.32#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:08:11.32#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:08:11.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:08:11.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:08:11.32$vc4f8/va=7,6 2006.161.08:08:11.32#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.08:08:11.32#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.08:08:11.32#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:11.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:08:11.38#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:08:11.38#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:08:11.38#ibcon#enter wrdev, iclass 35, count 2 2006.161.08:08:11.38#ibcon#first serial, iclass 35, count 2 2006.161.08:08:11.38#ibcon#enter sib2, iclass 35, count 2 2006.161.08:08:11.38#ibcon#flushed, iclass 35, count 2 2006.161.08:08:11.38#ibcon#about to write, iclass 35, count 2 2006.161.08:08:11.38#ibcon#wrote, iclass 35, count 2 2006.161.08:08:11.38#ibcon#about to read 3, iclass 35, count 2 2006.161.08:08:11.40#ibcon#read 3, iclass 35, count 2 2006.161.08:08:11.40#ibcon#about to read 4, iclass 35, count 2 2006.161.08:08:11.40#ibcon#read 4, iclass 35, count 2 2006.161.08:08:11.40#ibcon#about to read 5, iclass 35, count 2 2006.161.08:08:11.40#ibcon#read 5, iclass 35, count 2 2006.161.08:08:11.40#ibcon#about to read 6, iclass 35, count 2 2006.161.08:08:11.40#ibcon#read 6, iclass 35, count 2 2006.161.08:08:11.40#ibcon#end of sib2, iclass 35, count 2 2006.161.08:08:11.40#ibcon#*mode == 0, iclass 35, count 2 2006.161.08:08:11.40#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.08:08:11.40#ibcon#[25=AT07-06\r\n] 2006.161.08:08:11.40#ibcon#*before write, iclass 35, count 2 2006.161.08:08:11.40#ibcon#enter sib2, iclass 35, count 2 2006.161.08:08:11.40#ibcon#flushed, iclass 35, count 2 2006.161.08:08:11.40#ibcon#about to write, iclass 35, count 2 2006.161.08:08:11.40#ibcon#wrote, iclass 35, count 2 2006.161.08:08:11.40#ibcon#about to read 3, iclass 35, count 2 2006.161.08:08:11.43#ibcon#read 3, iclass 35, count 2 2006.161.08:08:11.43#ibcon#about to read 4, iclass 35, count 2 2006.161.08:08:11.43#ibcon#read 4, iclass 35, count 2 2006.161.08:08:11.43#ibcon#about to read 5, iclass 35, count 2 2006.161.08:08:11.43#ibcon#read 5, iclass 35, count 2 2006.161.08:08:11.43#ibcon#about to read 6, iclass 35, count 2 2006.161.08:08:11.43#ibcon#read 6, iclass 35, count 2 2006.161.08:08:11.43#ibcon#end of sib2, iclass 35, count 2 2006.161.08:08:11.43#ibcon#*after write, iclass 35, count 2 2006.161.08:08:11.43#ibcon#*before return 0, iclass 35, count 2 2006.161.08:08:11.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:08:11.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:08:11.43#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.08:08:11.43#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:11.43#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:08:11.56#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:08:11.56#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:08:11.56#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:08:11.56#ibcon#first serial, iclass 35, count 0 2006.161.08:08:11.56#ibcon#enter sib2, iclass 35, count 0 2006.161.08:08:11.56#ibcon#flushed, iclass 35, count 0 2006.161.08:08:11.56#ibcon#about to write, iclass 35, count 0 2006.161.08:08:11.56#ibcon#wrote, iclass 35, count 0 2006.161.08:08:11.56#ibcon#about to read 3, iclass 35, count 0 2006.161.08:08:11.58#ibcon#read 3, iclass 35, count 0 2006.161.08:08:11.58#ibcon#about to read 4, iclass 35, count 0 2006.161.08:08:11.58#ibcon#read 4, iclass 35, count 0 2006.161.08:08:11.58#ibcon#about to read 5, iclass 35, count 0 2006.161.08:08:11.58#ibcon#read 5, iclass 35, count 0 2006.161.08:08:11.58#ibcon#about to read 6, iclass 35, count 0 2006.161.08:08:11.58#ibcon#read 6, iclass 35, count 0 2006.161.08:08:11.58#ibcon#end of sib2, iclass 35, count 0 2006.161.08:08:11.58#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:08:11.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:08:11.58#ibcon#[25=USB\r\n] 2006.161.08:08:11.58#ibcon#*before write, iclass 35, count 0 2006.161.08:08:11.58#ibcon#enter sib2, iclass 35, count 0 2006.161.08:08:11.58#ibcon#flushed, iclass 35, count 0 2006.161.08:08:11.58#ibcon#about to write, iclass 35, count 0 2006.161.08:08:11.58#ibcon#wrote, iclass 35, count 0 2006.161.08:08:11.58#ibcon#about to read 3, iclass 35, count 0 2006.161.08:08:11.61#ibcon#read 3, iclass 35, count 0 2006.161.08:08:11.61#ibcon#about to read 4, iclass 35, count 0 2006.161.08:08:11.61#ibcon#read 4, iclass 35, count 0 2006.161.08:08:11.61#ibcon#about to read 5, iclass 35, count 0 2006.161.08:08:11.61#ibcon#read 5, iclass 35, count 0 2006.161.08:08:11.61#ibcon#about to read 6, iclass 35, count 0 2006.161.08:08:11.61#ibcon#read 6, iclass 35, count 0 2006.161.08:08:11.61#ibcon#end of sib2, iclass 35, count 0 2006.161.08:08:11.61#ibcon#*after write, iclass 35, count 0 2006.161.08:08:11.61#ibcon#*before return 0, iclass 35, count 0 2006.161.08:08:11.61#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:08:11.61#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:08:11.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:08:11.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:08:11.61$vc4f8/valo=8,852.99 2006.161.08:08:11.61#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:08:11.61#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:08:11.61#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:11.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:08:11.61#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:08:11.61#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:08:11.61#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:08:11.61#ibcon#first serial, iclass 37, count 0 2006.161.08:08:11.61#ibcon#enter sib2, iclass 37, count 0 2006.161.08:08:11.61#ibcon#flushed, iclass 37, count 0 2006.161.08:08:11.61#ibcon#about to write, iclass 37, count 0 2006.161.08:08:11.61#ibcon#wrote, iclass 37, count 0 2006.161.08:08:11.61#ibcon#about to read 3, iclass 37, count 0 2006.161.08:08:11.63#ibcon#read 3, iclass 37, count 0 2006.161.08:08:11.63#ibcon#about to read 4, iclass 37, count 0 2006.161.08:08:11.63#ibcon#read 4, iclass 37, count 0 2006.161.08:08:11.63#ibcon#about to read 5, iclass 37, count 0 2006.161.08:08:11.63#ibcon#read 5, iclass 37, count 0 2006.161.08:08:11.63#ibcon#about to read 6, iclass 37, count 0 2006.161.08:08:11.63#ibcon#read 6, iclass 37, count 0 2006.161.08:08:11.63#ibcon#end of sib2, iclass 37, count 0 2006.161.08:08:11.63#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:08:11.63#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:08:11.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:08:11.63#ibcon#*before write, iclass 37, count 0 2006.161.08:08:11.63#ibcon#enter sib2, iclass 37, count 0 2006.161.08:08:11.63#ibcon#flushed, iclass 37, count 0 2006.161.08:08:11.63#ibcon#about to write, iclass 37, count 0 2006.161.08:08:11.63#ibcon#wrote, iclass 37, count 0 2006.161.08:08:11.63#ibcon#about to read 3, iclass 37, count 0 2006.161.08:08:11.67#ibcon#read 3, iclass 37, count 0 2006.161.08:08:11.67#ibcon#about to read 4, iclass 37, count 0 2006.161.08:08:11.67#ibcon#read 4, iclass 37, count 0 2006.161.08:08:11.67#ibcon#about to read 5, iclass 37, count 0 2006.161.08:08:11.67#ibcon#read 5, iclass 37, count 0 2006.161.08:08:11.67#ibcon#about to read 6, iclass 37, count 0 2006.161.08:08:11.67#ibcon#read 6, iclass 37, count 0 2006.161.08:08:11.67#ibcon#end of sib2, iclass 37, count 0 2006.161.08:08:11.67#ibcon#*after write, iclass 37, count 0 2006.161.08:08:11.67#ibcon#*before return 0, iclass 37, count 0 2006.161.08:08:11.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:08:11.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:08:11.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:08:11.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:08:11.67$vc4f8/va=8,7 2006.161.08:08:11.67#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:08:11.67#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:08:11.67#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:11.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:08:11.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:08:11.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:08:11.73#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:08:11.73#ibcon#first serial, iclass 39, count 2 2006.161.08:08:11.73#ibcon#enter sib2, iclass 39, count 2 2006.161.08:08:11.73#ibcon#flushed, iclass 39, count 2 2006.161.08:08:11.73#ibcon#about to write, iclass 39, count 2 2006.161.08:08:11.73#ibcon#wrote, iclass 39, count 2 2006.161.08:08:11.73#ibcon#about to read 3, iclass 39, count 2 2006.161.08:08:11.75#ibcon#read 3, iclass 39, count 2 2006.161.08:08:11.75#ibcon#about to read 4, iclass 39, count 2 2006.161.08:08:11.75#ibcon#read 4, iclass 39, count 2 2006.161.08:08:11.75#ibcon#about to read 5, iclass 39, count 2 2006.161.08:08:11.75#ibcon#read 5, iclass 39, count 2 2006.161.08:08:11.75#ibcon#about to read 6, iclass 39, count 2 2006.161.08:08:11.75#ibcon#read 6, iclass 39, count 2 2006.161.08:08:11.75#ibcon#end of sib2, iclass 39, count 2 2006.161.08:08:11.75#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:08:11.75#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:08:11.75#ibcon#[25=AT08-07\r\n] 2006.161.08:08:11.75#ibcon#*before write, iclass 39, count 2 2006.161.08:08:11.75#ibcon#enter sib2, iclass 39, count 2 2006.161.08:08:11.75#ibcon#flushed, iclass 39, count 2 2006.161.08:08:11.75#ibcon#about to write, iclass 39, count 2 2006.161.08:08:11.75#ibcon#wrote, iclass 39, count 2 2006.161.08:08:11.75#ibcon#about to read 3, iclass 39, count 2 2006.161.08:08:11.78#ibcon#read 3, iclass 39, count 2 2006.161.08:08:11.78#ibcon#about to read 4, iclass 39, count 2 2006.161.08:08:11.78#ibcon#read 4, iclass 39, count 2 2006.161.08:08:11.78#ibcon#about to read 5, iclass 39, count 2 2006.161.08:08:11.78#ibcon#read 5, iclass 39, count 2 2006.161.08:08:11.78#ibcon#about to read 6, iclass 39, count 2 2006.161.08:08:11.78#ibcon#read 6, iclass 39, count 2 2006.161.08:08:11.78#ibcon#end of sib2, iclass 39, count 2 2006.161.08:08:11.78#ibcon#*after write, iclass 39, count 2 2006.161.08:08:11.78#ibcon#*before return 0, iclass 39, count 2 2006.161.08:08:11.78#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:08:11.78#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:08:11.78#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:08:11.78#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:11.78#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:08:11.90#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:08:11.90#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:08:11.90#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:08:11.90#ibcon#first serial, iclass 39, count 0 2006.161.08:08:11.90#ibcon#enter sib2, iclass 39, count 0 2006.161.08:08:11.90#ibcon#flushed, iclass 39, count 0 2006.161.08:08:11.90#ibcon#about to write, iclass 39, count 0 2006.161.08:08:11.90#ibcon#wrote, iclass 39, count 0 2006.161.08:08:11.90#ibcon#about to read 3, iclass 39, count 0 2006.161.08:08:11.92#ibcon#read 3, iclass 39, count 0 2006.161.08:08:11.92#ibcon#about to read 4, iclass 39, count 0 2006.161.08:08:11.92#ibcon#read 4, iclass 39, count 0 2006.161.08:08:11.92#ibcon#about to read 5, iclass 39, count 0 2006.161.08:08:11.92#ibcon#read 5, iclass 39, count 0 2006.161.08:08:11.92#ibcon#about to read 6, iclass 39, count 0 2006.161.08:08:11.92#ibcon#read 6, iclass 39, count 0 2006.161.08:08:11.92#ibcon#end of sib2, iclass 39, count 0 2006.161.08:08:11.92#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:08:11.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:08:11.92#ibcon#[25=USB\r\n] 2006.161.08:08:11.92#ibcon#*before write, iclass 39, count 0 2006.161.08:08:11.92#ibcon#enter sib2, iclass 39, count 0 2006.161.08:08:11.92#ibcon#flushed, iclass 39, count 0 2006.161.08:08:11.92#ibcon#about to write, iclass 39, count 0 2006.161.08:08:11.92#ibcon#wrote, iclass 39, count 0 2006.161.08:08:11.92#ibcon#about to read 3, iclass 39, count 0 2006.161.08:08:11.95#ibcon#read 3, iclass 39, count 0 2006.161.08:08:11.95#ibcon#about to read 4, iclass 39, count 0 2006.161.08:08:11.95#ibcon#read 4, iclass 39, count 0 2006.161.08:08:11.95#ibcon#about to read 5, iclass 39, count 0 2006.161.08:08:11.95#ibcon#read 5, iclass 39, count 0 2006.161.08:08:11.95#ibcon#about to read 6, iclass 39, count 0 2006.161.08:08:11.95#ibcon#read 6, iclass 39, count 0 2006.161.08:08:11.95#ibcon#end of sib2, iclass 39, count 0 2006.161.08:08:11.95#ibcon#*after write, iclass 39, count 0 2006.161.08:08:11.95#ibcon#*before return 0, iclass 39, count 0 2006.161.08:08:11.95#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:08:11.95#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:08:11.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:08:11.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:08:11.95$vc4f8/vblo=1,632.99 2006.161.08:08:11.95#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:08:11.95#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:08:11.95#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:11.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:08:11.95#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:08:11.95#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:08:11.95#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:08:11.95#ibcon#first serial, iclass 3, count 0 2006.161.08:08:11.95#ibcon#enter sib2, iclass 3, count 0 2006.161.08:08:11.95#ibcon#flushed, iclass 3, count 0 2006.161.08:08:11.95#ibcon#about to write, iclass 3, count 0 2006.161.08:08:11.95#ibcon#wrote, iclass 3, count 0 2006.161.08:08:11.95#ibcon#about to read 3, iclass 3, count 0 2006.161.08:08:11.97#ibcon#read 3, iclass 3, count 0 2006.161.08:08:11.97#ibcon#about to read 4, iclass 3, count 0 2006.161.08:08:11.97#ibcon#read 4, iclass 3, count 0 2006.161.08:08:11.97#ibcon#about to read 5, iclass 3, count 0 2006.161.08:08:11.97#ibcon#read 5, iclass 3, count 0 2006.161.08:08:11.97#ibcon#about to read 6, iclass 3, count 0 2006.161.08:08:11.97#ibcon#read 6, iclass 3, count 0 2006.161.08:08:11.97#ibcon#end of sib2, iclass 3, count 0 2006.161.08:08:11.97#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:08:11.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:08:11.97#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:08:11.97#ibcon#*before write, iclass 3, count 0 2006.161.08:08:11.97#ibcon#enter sib2, iclass 3, count 0 2006.161.08:08:11.97#ibcon#flushed, iclass 3, count 0 2006.161.08:08:11.97#ibcon#about to write, iclass 3, count 0 2006.161.08:08:11.97#ibcon#wrote, iclass 3, count 0 2006.161.08:08:11.97#ibcon#about to read 3, iclass 3, count 0 2006.161.08:08:12.01#ibcon#read 3, iclass 3, count 0 2006.161.08:08:12.01#ibcon#about to read 4, iclass 3, count 0 2006.161.08:08:12.01#ibcon#read 4, iclass 3, count 0 2006.161.08:08:12.01#ibcon#about to read 5, iclass 3, count 0 2006.161.08:08:12.01#ibcon#read 5, iclass 3, count 0 2006.161.08:08:12.01#ibcon#about to read 6, iclass 3, count 0 2006.161.08:08:12.01#ibcon#read 6, iclass 3, count 0 2006.161.08:08:12.01#ibcon#end of sib2, iclass 3, count 0 2006.161.08:08:12.01#ibcon#*after write, iclass 3, count 0 2006.161.08:08:12.01#ibcon#*before return 0, iclass 3, count 0 2006.161.08:08:12.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:08:12.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:08:12.01#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:08:12.01#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:08:12.01$vc4f8/vb=1,4 2006.161.08:08:12.01#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:08:12.01#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:08:12.01#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:12.01#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:08:12.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:08:12.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:08:12.01#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:08:12.01#ibcon#first serial, iclass 5, count 2 2006.161.08:08:12.01#ibcon#enter sib2, iclass 5, count 2 2006.161.08:08:12.01#ibcon#flushed, iclass 5, count 2 2006.161.08:08:12.01#ibcon#about to write, iclass 5, count 2 2006.161.08:08:12.01#ibcon#wrote, iclass 5, count 2 2006.161.08:08:12.01#ibcon#about to read 3, iclass 5, count 2 2006.161.08:08:12.03#ibcon#read 3, iclass 5, count 2 2006.161.08:08:12.03#ibcon#about to read 4, iclass 5, count 2 2006.161.08:08:12.03#ibcon#read 4, iclass 5, count 2 2006.161.08:08:12.03#ibcon#about to read 5, iclass 5, count 2 2006.161.08:08:12.03#ibcon#read 5, iclass 5, count 2 2006.161.08:08:12.03#ibcon#about to read 6, iclass 5, count 2 2006.161.08:08:12.03#ibcon#read 6, iclass 5, count 2 2006.161.08:08:12.03#ibcon#end of sib2, iclass 5, count 2 2006.161.08:08:12.03#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:08:12.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:08:12.03#ibcon#[27=AT01-04\r\n] 2006.161.08:08:12.03#ibcon#*before write, iclass 5, count 2 2006.161.08:08:12.03#ibcon#enter sib2, iclass 5, count 2 2006.161.08:08:12.03#ibcon#flushed, iclass 5, count 2 2006.161.08:08:12.03#ibcon#about to write, iclass 5, count 2 2006.161.08:08:12.03#ibcon#wrote, iclass 5, count 2 2006.161.08:08:12.03#ibcon#about to read 3, iclass 5, count 2 2006.161.08:08:12.06#ibcon#read 3, iclass 5, count 2 2006.161.08:08:12.06#ibcon#about to read 4, iclass 5, count 2 2006.161.08:08:12.06#ibcon#read 4, iclass 5, count 2 2006.161.08:08:12.06#ibcon#about to read 5, iclass 5, count 2 2006.161.08:08:12.06#ibcon#read 5, iclass 5, count 2 2006.161.08:08:12.06#ibcon#about to read 6, iclass 5, count 2 2006.161.08:08:12.06#ibcon#read 6, iclass 5, count 2 2006.161.08:08:12.06#ibcon#end of sib2, iclass 5, count 2 2006.161.08:08:12.06#ibcon#*after write, iclass 5, count 2 2006.161.08:08:12.06#ibcon#*before return 0, iclass 5, count 2 2006.161.08:08:12.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:08:12.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:08:12.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:08:12.06#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:12.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:08:12.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:08:12.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:08:12.18#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:08:12.18#ibcon#first serial, iclass 5, count 0 2006.161.08:08:12.18#ibcon#enter sib2, iclass 5, count 0 2006.161.08:08:12.18#ibcon#flushed, iclass 5, count 0 2006.161.08:08:12.18#ibcon#about to write, iclass 5, count 0 2006.161.08:08:12.18#ibcon#wrote, iclass 5, count 0 2006.161.08:08:12.18#ibcon#about to read 3, iclass 5, count 0 2006.161.08:08:12.20#ibcon#read 3, iclass 5, count 0 2006.161.08:08:12.20#ibcon#about to read 4, iclass 5, count 0 2006.161.08:08:12.20#ibcon#read 4, iclass 5, count 0 2006.161.08:08:12.20#ibcon#about to read 5, iclass 5, count 0 2006.161.08:08:12.20#ibcon#read 5, iclass 5, count 0 2006.161.08:08:12.20#ibcon#about to read 6, iclass 5, count 0 2006.161.08:08:12.20#ibcon#read 6, iclass 5, count 0 2006.161.08:08:12.20#ibcon#end of sib2, iclass 5, count 0 2006.161.08:08:12.20#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:08:12.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:08:12.20#ibcon#[27=USB\r\n] 2006.161.08:08:12.20#ibcon#*before write, iclass 5, count 0 2006.161.08:08:12.20#ibcon#enter sib2, iclass 5, count 0 2006.161.08:08:12.20#ibcon#flushed, iclass 5, count 0 2006.161.08:08:12.20#ibcon#about to write, iclass 5, count 0 2006.161.08:08:12.20#ibcon#wrote, iclass 5, count 0 2006.161.08:08:12.20#ibcon#about to read 3, iclass 5, count 0 2006.161.08:08:12.23#ibcon#read 3, iclass 5, count 0 2006.161.08:08:12.23#ibcon#about to read 4, iclass 5, count 0 2006.161.08:08:12.23#ibcon#read 4, iclass 5, count 0 2006.161.08:08:12.23#ibcon#about to read 5, iclass 5, count 0 2006.161.08:08:12.23#ibcon#read 5, iclass 5, count 0 2006.161.08:08:12.23#ibcon#about to read 6, iclass 5, count 0 2006.161.08:08:12.23#ibcon#read 6, iclass 5, count 0 2006.161.08:08:12.23#ibcon#end of sib2, iclass 5, count 0 2006.161.08:08:12.23#ibcon#*after write, iclass 5, count 0 2006.161.08:08:12.23#ibcon#*before return 0, iclass 5, count 0 2006.161.08:08:12.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:08:12.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:08:12.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:08:12.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:08:12.23$vc4f8/vblo=2,640.99 2006.161.08:08:12.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:08:12.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:08:12.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:12.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:12.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:12.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:12.23#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:08:12.23#ibcon#first serial, iclass 7, count 0 2006.161.08:08:12.23#ibcon#enter sib2, iclass 7, count 0 2006.161.08:08:12.23#ibcon#flushed, iclass 7, count 0 2006.161.08:08:12.23#ibcon#about to write, iclass 7, count 0 2006.161.08:08:12.23#ibcon#wrote, iclass 7, count 0 2006.161.08:08:12.23#ibcon#about to read 3, iclass 7, count 0 2006.161.08:08:12.25#ibcon#read 3, iclass 7, count 0 2006.161.08:08:12.25#ibcon#about to read 4, iclass 7, count 0 2006.161.08:08:12.25#ibcon#read 4, iclass 7, count 0 2006.161.08:08:12.25#ibcon#about to read 5, iclass 7, count 0 2006.161.08:08:12.25#ibcon#read 5, iclass 7, count 0 2006.161.08:08:12.25#ibcon#about to read 6, iclass 7, count 0 2006.161.08:08:12.25#ibcon#read 6, iclass 7, count 0 2006.161.08:08:12.25#ibcon#end of sib2, iclass 7, count 0 2006.161.08:08:12.25#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:08:12.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:08:12.25#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:08:12.25#ibcon#*before write, iclass 7, count 0 2006.161.08:08:12.25#ibcon#enter sib2, iclass 7, count 0 2006.161.08:08:12.25#ibcon#flushed, iclass 7, count 0 2006.161.08:08:12.25#ibcon#about to write, iclass 7, count 0 2006.161.08:08:12.25#ibcon#wrote, iclass 7, count 0 2006.161.08:08:12.25#ibcon#about to read 3, iclass 7, count 0 2006.161.08:08:12.29#ibcon#read 3, iclass 7, count 0 2006.161.08:08:12.29#ibcon#about to read 4, iclass 7, count 0 2006.161.08:08:12.29#ibcon#read 4, iclass 7, count 0 2006.161.08:08:12.29#ibcon#about to read 5, iclass 7, count 0 2006.161.08:08:12.29#ibcon#read 5, iclass 7, count 0 2006.161.08:08:12.29#ibcon#about to read 6, iclass 7, count 0 2006.161.08:08:12.29#ibcon#read 6, iclass 7, count 0 2006.161.08:08:12.29#ibcon#end of sib2, iclass 7, count 0 2006.161.08:08:12.29#ibcon#*after write, iclass 7, count 0 2006.161.08:08:12.29#ibcon#*before return 0, iclass 7, count 0 2006.161.08:08:12.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:12.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:08:12.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:08:12.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:08:12.29$vc4f8/vb=2,4 2006.161.08:08:12.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:08:12.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:08:12.29#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:12.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:12.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:12.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:12.35#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:08:12.35#ibcon#first serial, iclass 11, count 2 2006.161.08:08:12.35#ibcon#enter sib2, iclass 11, count 2 2006.161.08:08:12.35#ibcon#flushed, iclass 11, count 2 2006.161.08:08:12.35#ibcon#about to write, iclass 11, count 2 2006.161.08:08:12.35#ibcon#wrote, iclass 11, count 2 2006.161.08:08:12.35#ibcon#about to read 3, iclass 11, count 2 2006.161.08:08:12.37#ibcon#read 3, iclass 11, count 2 2006.161.08:08:12.37#ibcon#about to read 4, iclass 11, count 2 2006.161.08:08:12.37#ibcon#read 4, iclass 11, count 2 2006.161.08:08:12.37#ibcon#about to read 5, iclass 11, count 2 2006.161.08:08:12.37#ibcon#read 5, iclass 11, count 2 2006.161.08:08:12.37#ibcon#about to read 6, iclass 11, count 2 2006.161.08:08:12.37#ibcon#read 6, iclass 11, count 2 2006.161.08:08:12.37#ibcon#end of sib2, iclass 11, count 2 2006.161.08:08:12.37#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:08:12.37#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:08:12.37#ibcon#[27=AT02-04\r\n] 2006.161.08:08:12.37#ibcon#*before write, iclass 11, count 2 2006.161.08:08:12.37#ibcon#enter sib2, iclass 11, count 2 2006.161.08:08:12.37#ibcon#flushed, iclass 11, count 2 2006.161.08:08:12.37#ibcon#about to write, iclass 11, count 2 2006.161.08:08:12.37#ibcon#wrote, iclass 11, count 2 2006.161.08:08:12.37#ibcon#about to read 3, iclass 11, count 2 2006.161.08:08:12.40#ibcon#read 3, iclass 11, count 2 2006.161.08:08:12.40#ibcon#about to read 4, iclass 11, count 2 2006.161.08:08:12.40#ibcon#read 4, iclass 11, count 2 2006.161.08:08:12.40#ibcon#about to read 5, iclass 11, count 2 2006.161.08:08:12.40#ibcon#read 5, iclass 11, count 2 2006.161.08:08:12.40#ibcon#about to read 6, iclass 11, count 2 2006.161.08:08:12.40#ibcon#read 6, iclass 11, count 2 2006.161.08:08:12.40#ibcon#end of sib2, iclass 11, count 2 2006.161.08:08:12.40#ibcon#*after write, iclass 11, count 2 2006.161.08:08:12.40#ibcon#*before return 0, iclass 11, count 2 2006.161.08:08:12.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:12.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:08:12.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:08:12.40#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:12.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:12.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:12.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:12.52#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:08:12.52#ibcon#first serial, iclass 11, count 0 2006.161.08:08:12.52#ibcon#enter sib2, iclass 11, count 0 2006.161.08:08:12.52#ibcon#flushed, iclass 11, count 0 2006.161.08:08:12.52#ibcon#about to write, iclass 11, count 0 2006.161.08:08:12.52#ibcon#wrote, iclass 11, count 0 2006.161.08:08:12.52#ibcon#about to read 3, iclass 11, count 0 2006.161.08:08:12.54#ibcon#read 3, iclass 11, count 0 2006.161.08:08:12.54#ibcon#about to read 4, iclass 11, count 0 2006.161.08:08:12.54#ibcon#read 4, iclass 11, count 0 2006.161.08:08:12.54#ibcon#about to read 5, iclass 11, count 0 2006.161.08:08:12.54#ibcon#read 5, iclass 11, count 0 2006.161.08:08:12.54#ibcon#about to read 6, iclass 11, count 0 2006.161.08:08:12.54#ibcon#read 6, iclass 11, count 0 2006.161.08:08:12.54#ibcon#end of sib2, iclass 11, count 0 2006.161.08:08:12.54#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:08:12.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:08:12.54#ibcon#[27=USB\r\n] 2006.161.08:08:12.54#ibcon#*before write, iclass 11, count 0 2006.161.08:08:12.54#ibcon#enter sib2, iclass 11, count 0 2006.161.08:08:12.54#ibcon#flushed, iclass 11, count 0 2006.161.08:08:12.54#ibcon#about to write, iclass 11, count 0 2006.161.08:08:12.54#ibcon#wrote, iclass 11, count 0 2006.161.08:08:12.54#ibcon#about to read 3, iclass 11, count 0 2006.161.08:08:12.57#ibcon#read 3, iclass 11, count 0 2006.161.08:08:12.57#ibcon#about to read 4, iclass 11, count 0 2006.161.08:08:12.57#ibcon#read 4, iclass 11, count 0 2006.161.08:08:12.57#ibcon#about to read 5, iclass 11, count 0 2006.161.08:08:12.57#ibcon#read 5, iclass 11, count 0 2006.161.08:08:12.57#ibcon#about to read 6, iclass 11, count 0 2006.161.08:08:12.57#ibcon#read 6, iclass 11, count 0 2006.161.08:08:12.57#ibcon#end of sib2, iclass 11, count 0 2006.161.08:08:12.57#ibcon#*after write, iclass 11, count 0 2006.161.08:08:12.57#ibcon#*before return 0, iclass 11, count 0 2006.161.08:08:12.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:12.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:08:12.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:08:12.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:08:12.57$vc4f8/vblo=3,656.99 2006.161.08:08:12.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:08:12.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:08:12.57#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:12.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:12.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:12.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:12.57#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:08:12.57#ibcon#first serial, iclass 13, count 0 2006.161.08:08:12.57#ibcon#enter sib2, iclass 13, count 0 2006.161.08:08:12.57#ibcon#flushed, iclass 13, count 0 2006.161.08:08:12.57#ibcon#about to write, iclass 13, count 0 2006.161.08:08:12.57#ibcon#wrote, iclass 13, count 0 2006.161.08:08:12.57#ibcon#about to read 3, iclass 13, count 0 2006.161.08:08:12.59#ibcon#read 3, iclass 13, count 0 2006.161.08:08:12.59#ibcon#about to read 4, iclass 13, count 0 2006.161.08:08:12.59#ibcon#read 4, iclass 13, count 0 2006.161.08:08:12.59#ibcon#about to read 5, iclass 13, count 0 2006.161.08:08:12.59#ibcon#read 5, iclass 13, count 0 2006.161.08:08:12.59#ibcon#about to read 6, iclass 13, count 0 2006.161.08:08:12.59#ibcon#read 6, iclass 13, count 0 2006.161.08:08:12.59#ibcon#end of sib2, iclass 13, count 0 2006.161.08:08:12.59#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:08:12.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:08:12.59#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:08:12.59#ibcon#*before write, iclass 13, count 0 2006.161.08:08:12.59#ibcon#enter sib2, iclass 13, count 0 2006.161.08:08:12.59#ibcon#flushed, iclass 13, count 0 2006.161.08:08:12.59#ibcon#about to write, iclass 13, count 0 2006.161.08:08:12.59#ibcon#wrote, iclass 13, count 0 2006.161.08:08:12.59#ibcon#about to read 3, iclass 13, count 0 2006.161.08:08:12.63#ibcon#read 3, iclass 13, count 0 2006.161.08:08:12.63#ibcon#about to read 4, iclass 13, count 0 2006.161.08:08:12.63#ibcon#read 4, iclass 13, count 0 2006.161.08:08:12.63#ibcon#about to read 5, iclass 13, count 0 2006.161.08:08:12.63#ibcon#read 5, iclass 13, count 0 2006.161.08:08:12.63#ibcon#about to read 6, iclass 13, count 0 2006.161.08:08:12.63#ibcon#read 6, iclass 13, count 0 2006.161.08:08:12.63#ibcon#end of sib2, iclass 13, count 0 2006.161.08:08:12.63#ibcon#*after write, iclass 13, count 0 2006.161.08:08:12.63#ibcon#*before return 0, iclass 13, count 0 2006.161.08:08:12.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:12.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:08:12.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:08:12.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:08:12.63$vc4f8/vb=3,4 2006.161.08:08:12.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:08:12.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:08:12.63#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:12.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:12.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:12.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:12.69#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:08:12.69#ibcon#first serial, iclass 15, count 2 2006.161.08:08:12.69#ibcon#enter sib2, iclass 15, count 2 2006.161.08:08:12.69#ibcon#flushed, iclass 15, count 2 2006.161.08:08:12.69#ibcon#about to write, iclass 15, count 2 2006.161.08:08:12.69#ibcon#wrote, iclass 15, count 2 2006.161.08:08:12.69#ibcon#about to read 3, iclass 15, count 2 2006.161.08:08:12.71#ibcon#read 3, iclass 15, count 2 2006.161.08:08:12.71#ibcon#about to read 4, iclass 15, count 2 2006.161.08:08:12.71#ibcon#read 4, iclass 15, count 2 2006.161.08:08:12.71#ibcon#about to read 5, iclass 15, count 2 2006.161.08:08:12.71#ibcon#read 5, iclass 15, count 2 2006.161.08:08:12.71#ibcon#about to read 6, iclass 15, count 2 2006.161.08:08:12.71#ibcon#read 6, iclass 15, count 2 2006.161.08:08:12.71#ibcon#end of sib2, iclass 15, count 2 2006.161.08:08:12.71#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:08:12.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:08:12.71#ibcon#[27=AT03-04\r\n] 2006.161.08:08:12.71#ibcon#*before write, iclass 15, count 2 2006.161.08:08:12.71#ibcon#enter sib2, iclass 15, count 2 2006.161.08:08:12.71#ibcon#flushed, iclass 15, count 2 2006.161.08:08:12.71#ibcon#about to write, iclass 15, count 2 2006.161.08:08:12.71#ibcon#wrote, iclass 15, count 2 2006.161.08:08:12.71#ibcon#about to read 3, iclass 15, count 2 2006.161.08:08:12.74#ibcon#read 3, iclass 15, count 2 2006.161.08:08:12.74#ibcon#about to read 4, iclass 15, count 2 2006.161.08:08:12.74#ibcon#read 4, iclass 15, count 2 2006.161.08:08:12.74#ibcon#about to read 5, iclass 15, count 2 2006.161.08:08:12.74#ibcon#read 5, iclass 15, count 2 2006.161.08:08:12.74#ibcon#about to read 6, iclass 15, count 2 2006.161.08:08:12.74#ibcon#read 6, iclass 15, count 2 2006.161.08:08:12.74#ibcon#end of sib2, iclass 15, count 2 2006.161.08:08:12.74#ibcon#*after write, iclass 15, count 2 2006.161.08:08:12.74#ibcon#*before return 0, iclass 15, count 2 2006.161.08:08:12.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:12.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:08:12.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:08:12.74#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:12.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:12.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:12.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:12.86#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:08:12.86#ibcon#first serial, iclass 15, count 0 2006.161.08:08:12.86#ibcon#enter sib2, iclass 15, count 0 2006.161.08:08:12.86#ibcon#flushed, iclass 15, count 0 2006.161.08:08:12.86#ibcon#about to write, iclass 15, count 0 2006.161.08:08:12.86#ibcon#wrote, iclass 15, count 0 2006.161.08:08:12.86#ibcon#about to read 3, iclass 15, count 0 2006.161.08:08:12.88#ibcon#read 3, iclass 15, count 0 2006.161.08:08:12.88#ibcon#about to read 4, iclass 15, count 0 2006.161.08:08:12.88#ibcon#read 4, iclass 15, count 0 2006.161.08:08:12.88#ibcon#about to read 5, iclass 15, count 0 2006.161.08:08:12.88#ibcon#read 5, iclass 15, count 0 2006.161.08:08:12.88#ibcon#about to read 6, iclass 15, count 0 2006.161.08:08:12.88#ibcon#read 6, iclass 15, count 0 2006.161.08:08:12.88#ibcon#end of sib2, iclass 15, count 0 2006.161.08:08:12.88#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:08:12.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:08:12.88#ibcon#[27=USB\r\n] 2006.161.08:08:12.88#ibcon#*before write, iclass 15, count 0 2006.161.08:08:12.88#ibcon#enter sib2, iclass 15, count 0 2006.161.08:08:12.88#ibcon#flushed, iclass 15, count 0 2006.161.08:08:12.88#ibcon#about to write, iclass 15, count 0 2006.161.08:08:12.88#ibcon#wrote, iclass 15, count 0 2006.161.08:08:12.88#ibcon#about to read 3, iclass 15, count 0 2006.161.08:08:12.91#ibcon#read 3, iclass 15, count 0 2006.161.08:08:12.91#ibcon#about to read 4, iclass 15, count 0 2006.161.08:08:12.91#ibcon#read 4, iclass 15, count 0 2006.161.08:08:12.91#ibcon#about to read 5, iclass 15, count 0 2006.161.08:08:12.91#ibcon#read 5, iclass 15, count 0 2006.161.08:08:12.91#ibcon#about to read 6, iclass 15, count 0 2006.161.08:08:12.91#ibcon#read 6, iclass 15, count 0 2006.161.08:08:12.91#ibcon#end of sib2, iclass 15, count 0 2006.161.08:08:12.91#ibcon#*after write, iclass 15, count 0 2006.161.08:08:12.91#ibcon#*before return 0, iclass 15, count 0 2006.161.08:08:12.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:12.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:08:12.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:08:12.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:08:12.91$vc4f8/vblo=4,712.99 2006.161.08:08:12.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:08:12.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:08:12.91#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:12.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:12.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:12.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:12.91#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:08:12.91#ibcon#first serial, iclass 17, count 0 2006.161.08:08:12.91#ibcon#enter sib2, iclass 17, count 0 2006.161.08:08:12.91#ibcon#flushed, iclass 17, count 0 2006.161.08:08:12.91#ibcon#about to write, iclass 17, count 0 2006.161.08:08:12.91#ibcon#wrote, iclass 17, count 0 2006.161.08:08:12.91#ibcon#about to read 3, iclass 17, count 0 2006.161.08:08:12.93#ibcon#read 3, iclass 17, count 0 2006.161.08:08:12.93#ibcon#about to read 4, iclass 17, count 0 2006.161.08:08:12.93#ibcon#read 4, iclass 17, count 0 2006.161.08:08:12.93#ibcon#about to read 5, iclass 17, count 0 2006.161.08:08:12.93#ibcon#read 5, iclass 17, count 0 2006.161.08:08:12.93#ibcon#about to read 6, iclass 17, count 0 2006.161.08:08:12.93#ibcon#read 6, iclass 17, count 0 2006.161.08:08:12.93#ibcon#end of sib2, iclass 17, count 0 2006.161.08:08:12.93#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:08:12.93#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:08:12.93#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:08:12.93#ibcon#*before write, iclass 17, count 0 2006.161.08:08:12.93#ibcon#enter sib2, iclass 17, count 0 2006.161.08:08:12.93#ibcon#flushed, iclass 17, count 0 2006.161.08:08:12.93#ibcon#about to write, iclass 17, count 0 2006.161.08:08:12.93#ibcon#wrote, iclass 17, count 0 2006.161.08:08:12.93#ibcon#about to read 3, iclass 17, count 0 2006.161.08:08:12.97#ibcon#read 3, iclass 17, count 0 2006.161.08:08:12.97#ibcon#about to read 4, iclass 17, count 0 2006.161.08:08:12.97#ibcon#read 4, iclass 17, count 0 2006.161.08:08:12.97#ibcon#about to read 5, iclass 17, count 0 2006.161.08:08:12.97#ibcon#read 5, iclass 17, count 0 2006.161.08:08:12.97#ibcon#about to read 6, iclass 17, count 0 2006.161.08:08:12.97#ibcon#read 6, iclass 17, count 0 2006.161.08:08:12.97#ibcon#end of sib2, iclass 17, count 0 2006.161.08:08:12.97#ibcon#*after write, iclass 17, count 0 2006.161.08:08:12.97#ibcon#*before return 0, iclass 17, count 0 2006.161.08:08:12.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:12.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:08:12.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:08:12.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:08:12.97$vc4f8/vb=4,4 2006.161.08:08:12.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:08:12.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:08:12.97#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:12.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:13.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:13.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:13.03#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:08:13.03#ibcon#first serial, iclass 19, count 2 2006.161.08:08:13.03#ibcon#enter sib2, iclass 19, count 2 2006.161.08:08:13.03#ibcon#flushed, iclass 19, count 2 2006.161.08:08:13.03#ibcon#about to write, iclass 19, count 2 2006.161.08:08:13.03#ibcon#wrote, iclass 19, count 2 2006.161.08:08:13.03#ibcon#about to read 3, iclass 19, count 2 2006.161.08:08:13.05#ibcon#read 3, iclass 19, count 2 2006.161.08:08:13.05#ibcon#about to read 4, iclass 19, count 2 2006.161.08:08:13.05#ibcon#read 4, iclass 19, count 2 2006.161.08:08:13.05#ibcon#about to read 5, iclass 19, count 2 2006.161.08:08:13.05#ibcon#read 5, iclass 19, count 2 2006.161.08:08:13.05#ibcon#about to read 6, iclass 19, count 2 2006.161.08:08:13.05#ibcon#read 6, iclass 19, count 2 2006.161.08:08:13.05#ibcon#end of sib2, iclass 19, count 2 2006.161.08:08:13.05#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:08:13.05#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:08:13.05#ibcon#[27=AT04-04\r\n] 2006.161.08:08:13.05#ibcon#*before write, iclass 19, count 2 2006.161.08:08:13.05#ibcon#enter sib2, iclass 19, count 2 2006.161.08:08:13.05#ibcon#flushed, iclass 19, count 2 2006.161.08:08:13.05#ibcon#about to write, iclass 19, count 2 2006.161.08:08:13.05#ibcon#wrote, iclass 19, count 2 2006.161.08:08:13.05#ibcon#about to read 3, iclass 19, count 2 2006.161.08:08:13.08#ibcon#read 3, iclass 19, count 2 2006.161.08:08:13.08#ibcon#about to read 4, iclass 19, count 2 2006.161.08:08:13.08#ibcon#read 4, iclass 19, count 2 2006.161.08:08:13.08#ibcon#about to read 5, iclass 19, count 2 2006.161.08:08:13.08#ibcon#read 5, iclass 19, count 2 2006.161.08:08:13.08#ibcon#about to read 6, iclass 19, count 2 2006.161.08:08:13.08#ibcon#read 6, iclass 19, count 2 2006.161.08:08:13.08#ibcon#end of sib2, iclass 19, count 2 2006.161.08:08:13.08#ibcon#*after write, iclass 19, count 2 2006.161.08:08:13.08#ibcon#*before return 0, iclass 19, count 2 2006.161.08:08:13.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:13.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:08:13.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:08:13.08#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:13.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:13.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:13.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:13.20#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:08:13.20#ibcon#first serial, iclass 19, count 0 2006.161.08:08:13.20#ibcon#enter sib2, iclass 19, count 0 2006.161.08:08:13.20#ibcon#flushed, iclass 19, count 0 2006.161.08:08:13.20#ibcon#about to write, iclass 19, count 0 2006.161.08:08:13.20#ibcon#wrote, iclass 19, count 0 2006.161.08:08:13.20#ibcon#about to read 3, iclass 19, count 0 2006.161.08:08:13.22#ibcon#read 3, iclass 19, count 0 2006.161.08:08:13.22#ibcon#about to read 4, iclass 19, count 0 2006.161.08:08:13.22#ibcon#read 4, iclass 19, count 0 2006.161.08:08:13.22#ibcon#about to read 5, iclass 19, count 0 2006.161.08:08:13.22#ibcon#read 5, iclass 19, count 0 2006.161.08:08:13.22#ibcon#about to read 6, iclass 19, count 0 2006.161.08:08:13.22#ibcon#read 6, iclass 19, count 0 2006.161.08:08:13.22#ibcon#end of sib2, iclass 19, count 0 2006.161.08:08:13.22#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:08:13.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:08:13.22#ibcon#[27=USB\r\n] 2006.161.08:08:13.22#ibcon#*before write, iclass 19, count 0 2006.161.08:08:13.22#ibcon#enter sib2, iclass 19, count 0 2006.161.08:08:13.22#ibcon#flushed, iclass 19, count 0 2006.161.08:08:13.22#ibcon#about to write, iclass 19, count 0 2006.161.08:08:13.22#ibcon#wrote, iclass 19, count 0 2006.161.08:08:13.22#ibcon#about to read 3, iclass 19, count 0 2006.161.08:08:13.25#ibcon#read 3, iclass 19, count 0 2006.161.08:08:13.25#ibcon#about to read 4, iclass 19, count 0 2006.161.08:08:13.25#ibcon#read 4, iclass 19, count 0 2006.161.08:08:13.25#ibcon#about to read 5, iclass 19, count 0 2006.161.08:08:13.25#ibcon#read 5, iclass 19, count 0 2006.161.08:08:13.25#ibcon#about to read 6, iclass 19, count 0 2006.161.08:08:13.25#ibcon#read 6, iclass 19, count 0 2006.161.08:08:13.25#ibcon#end of sib2, iclass 19, count 0 2006.161.08:08:13.25#ibcon#*after write, iclass 19, count 0 2006.161.08:08:13.25#ibcon#*before return 0, iclass 19, count 0 2006.161.08:08:13.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:13.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:08:13.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:08:13.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:08:13.25$vc4f8/vblo=5,744.99 2006.161.08:08:13.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:08:13.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:08:13.25#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:13.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:13.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:13.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:13.25#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:08:13.25#ibcon#first serial, iclass 21, count 0 2006.161.08:08:13.25#ibcon#enter sib2, iclass 21, count 0 2006.161.08:08:13.25#ibcon#flushed, iclass 21, count 0 2006.161.08:08:13.25#ibcon#about to write, iclass 21, count 0 2006.161.08:08:13.25#ibcon#wrote, iclass 21, count 0 2006.161.08:08:13.25#ibcon#about to read 3, iclass 21, count 0 2006.161.08:08:13.27#ibcon#read 3, iclass 21, count 0 2006.161.08:08:13.27#ibcon#about to read 4, iclass 21, count 0 2006.161.08:08:13.27#ibcon#read 4, iclass 21, count 0 2006.161.08:08:13.27#ibcon#about to read 5, iclass 21, count 0 2006.161.08:08:13.27#ibcon#read 5, iclass 21, count 0 2006.161.08:08:13.27#ibcon#about to read 6, iclass 21, count 0 2006.161.08:08:13.27#ibcon#read 6, iclass 21, count 0 2006.161.08:08:13.27#ibcon#end of sib2, iclass 21, count 0 2006.161.08:08:13.27#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:08:13.27#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:08:13.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:08:13.27#ibcon#*before write, iclass 21, count 0 2006.161.08:08:13.27#ibcon#enter sib2, iclass 21, count 0 2006.161.08:08:13.27#ibcon#flushed, iclass 21, count 0 2006.161.08:08:13.27#ibcon#about to write, iclass 21, count 0 2006.161.08:08:13.27#ibcon#wrote, iclass 21, count 0 2006.161.08:08:13.27#ibcon#about to read 3, iclass 21, count 0 2006.161.08:08:13.31#ibcon#read 3, iclass 21, count 0 2006.161.08:08:13.31#ibcon#about to read 4, iclass 21, count 0 2006.161.08:08:13.31#ibcon#read 4, iclass 21, count 0 2006.161.08:08:13.31#ibcon#about to read 5, iclass 21, count 0 2006.161.08:08:13.31#ibcon#read 5, iclass 21, count 0 2006.161.08:08:13.31#ibcon#about to read 6, iclass 21, count 0 2006.161.08:08:13.31#ibcon#read 6, iclass 21, count 0 2006.161.08:08:13.31#ibcon#end of sib2, iclass 21, count 0 2006.161.08:08:13.31#ibcon#*after write, iclass 21, count 0 2006.161.08:08:13.31#ibcon#*before return 0, iclass 21, count 0 2006.161.08:08:13.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:13.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:08:13.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:08:13.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:08:13.31$vc4f8/vb=5,4 2006.161.08:08:13.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:08:13.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:08:13.31#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:13.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:13.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:13.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:13.37#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:08:13.37#ibcon#first serial, iclass 23, count 2 2006.161.08:08:13.37#ibcon#enter sib2, iclass 23, count 2 2006.161.08:08:13.37#ibcon#flushed, iclass 23, count 2 2006.161.08:08:13.37#ibcon#about to write, iclass 23, count 2 2006.161.08:08:13.37#ibcon#wrote, iclass 23, count 2 2006.161.08:08:13.37#ibcon#about to read 3, iclass 23, count 2 2006.161.08:08:13.39#ibcon#read 3, iclass 23, count 2 2006.161.08:08:13.39#ibcon#about to read 4, iclass 23, count 2 2006.161.08:08:13.39#ibcon#read 4, iclass 23, count 2 2006.161.08:08:13.39#ibcon#about to read 5, iclass 23, count 2 2006.161.08:08:13.39#ibcon#read 5, iclass 23, count 2 2006.161.08:08:13.39#ibcon#about to read 6, iclass 23, count 2 2006.161.08:08:13.39#ibcon#read 6, iclass 23, count 2 2006.161.08:08:13.39#ibcon#end of sib2, iclass 23, count 2 2006.161.08:08:13.39#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:08:13.39#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:08:13.39#ibcon#[27=AT05-04\r\n] 2006.161.08:08:13.39#ibcon#*before write, iclass 23, count 2 2006.161.08:08:13.39#ibcon#enter sib2, iclass 23, count 2 2006.161.08:08:13.39#ibcon#flushed, iclass 23, count 2 2006.161.08:08:13.39#ibcon#about to write, iclass 23, count 2 2006.161.08:08:13.39#ibcon#wrote, iclass 23, count 2 2006.161.08:08:13.39#ibcon#about to read 3, iclass 23, count 2 2006.161.08:08:13.42#ibcon#read 3, iclass 23, count 2 2006.161.08:08:13.42#ibcon#about to read 4, iclass 23, count 2 2006.161.08:08:13.42#ibcon#read 4, iclass 23, count 2 2006.161.08:08:13.42#ibcon#about to read 5, iclass 23, count 2 2006.161.08:08:13.42#ibcon#read 5, iclass 23, count 2 2006.161.08:08:13.42#ibcon#about to read 6, iclass 23, count 2 2006.161.08:08:13.42#ibcon#read 6, iclass 23, count 2 2006.161.08:08:13.42#ibcon#end of sib2, iclass 23, count 2 2006.161.08:08:13.42#ibcon#*after write, iclass 23, count 2 2006.161.08:08:13.42#ibcon#*before return 0, iclass 23, count 2 2006.161.08:08:13.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:13.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:08:13.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:08:13.42#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:13.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:13.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:13.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:13.54#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:08:13.54#ibcon#first serial, iclass 23, count 0 2006.161.08:08:13.54#ibcon#enter sib2, iclass 23, count 0 2006.161.08:08:13.54#ibcon#flushed, iclass 23, count 0 2006.161.08:08:13.54#ibcon#about to write, iclass 23, count 0 2006.161.08:08:13.54#ibcon#wrote, iclass 23, count 0 2006.161.08:08:13.54#ibcon#about to read 3, iclass 23, count 0 2006.161.08:08:13.56#ibcon#read 3, iclass 23, count 0 2006.161.08:08:13.56#ibcon#about to read 4, iclass 23, count 0 2006.161.08:08:13.56#ibcon#read 4, iclass 23, count 0 2006.161.08:08:13.56#ibcon#about to read 5, iclass 23, count 0 2006.161.08:08:13.56#ibcon#read 5, iclass 23, count 0 2006.161.08:08:13.56#ibcon#about to read 6, iclass 23, count 0 2006.161.08:08:13.56#ibcon#read 6, iclass 23, count 0 2006.161.08:08:13.56#ibcon#end of sib2, iclass 23, count 0 2006.161.08:08:13.56#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:08:13.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:08:13.56#ibcon#[27=USB\r\n] 2006.161.08:08:13.56#ibcon#*before write, iclass 23, count 0 2006.161.08:08:13.56#ibcon#enter sib2, iclass 23, count 0 2006.161.08:08:13.56#ibcon#flushed, iclass 23, count 0 2006.161.08:08:13.56#ibcon#about to write, iclass 23, count 0 2006.161.08:08:13.56#ibcon#wrote, iclass 23, count 0 2006.161.08:08:13.56#ibcon#about to read 3, iclass 23, count 0 2006.161.08:08:13.59#ibcon#read 3, iclass 23, count 0 2006.161.08:08:13.59#ibcon#about to read 4, iclass 23, count 0 2006.161.08:08:13.59#ibcon#read 4, iclass 23, count 0 2006.161.08:08:13.59#ibcon#about to read 5, iclass 23, count 0 2006.161.08:08:13.59#ibcon#read 5, iclass 23, count 0 2006.161.08:08:13.59#ibcon#about to read 6, iclass 23, count 0 2006.161.08:08:13.59#ibcon#read 6, iclass 23, count 0 2006.161.08:08:13.59#ibcon#end of sib2, iclass 23, count 0 2006.161.08:08:13.59#ibcon#*after write, iclass 23, count 0 2006.161.08:08:13.59#ibcon#*before return 0, iclass 23, count 0 2006.161.08:08:13.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:13.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:08:13.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:08:13.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:08:13.59$vc4f8/vblo=6,752.99 2006.161.08:08:13.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:08:13.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:08:13.59#ibcon#ireg 17 cls_cnt 0 2006.161.08:08:13.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:13.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:13.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:13.59#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:08:13.59#ibcon#first serial, iclass 25, count 0 2006.161.08:08:13.59#ibcon#enter sib2, iclass 25, count 0 2006.161.08:08:13.59#ibcon#flushed, iclass 25, count 0 2006.161.08:08:13.59#ibcon#about to write, iclass 25, count 0 2006.161.08:08:13.59#ibcon#wrote, iclass 25, count 0 2006.161.08:08:13.59#ibcon#about to read 3, iclass 25, count 0 2006.161.08:08:13.61#ibcon#read 3, iclass 25, count 0 2006.161.08:08:13.61#ibcon#about to read 4, iclass 25, count 0 2006.161.08:08:13.61#ibcon#read 4, iclass 25, count 0 2006.161.08:08:13.61#ibcon#about to read 5, iclass 25, count 0 2006.161.08:08:13.61#ibcon#read 5, iclass 25, count 0 2006.161.08:08:13.61#ibcon#about to read 6, iclass 25, count 0 2006.161.08:08:13.61#ibcon#read 6, iclass 25, count 0 2006.161.08:08:13.61#ibcon#end of sib2, iclass 25, count 0 2006.161.08:08:13.61#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:08:13.61#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:08:13.61#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:08:13.61#ibcon#*before write, iclass 25, count 0 2006.161.08:08:13.61#ibcon#enter sib2, iclass 25, count 0 2006.161.08:08:13.61#ibcon#flushed, iclass 25, count 0 2006.161.08:08:13.61#ibcon#about to write, iclass 25, count 0 2006.161.08:08:13.61#ibcon#wrote, iclass 25, count 0 2006.161.08:08:13.61#ibcon#about to read 3, iclass 25, count 0 2006.161.08:08:13.65#ibcon#read 3, iclass 25, count 0 2006.161.08:08:13.65#ibcon#about to read 4, iclass 25, count 0 2006.161.08:08:13.65#ibcon#read 4, iclass 25, count 0 2006.161.08:08:13.65#ibcon#about to read 5, iclass 25, count 0 2006.161.08:08:13.65#ibcon#read 5, iclass 25, count 0 2006.161.08:08:13.65#ibcon#about to read 6, iclass 25, count 0 2006.161.08:08:13.65#ibcon#read 6, iclass 25, count 0 2006.161.08:08:13.65#ibcon#end of sib2, iclass 25, count 0 2006.161.08:08:13.65#ibcon#*after write, iclass 25, count 0 2006.161.08:08:13.65#ibcon#*before return 0, iclass 25, count 0 2006.161.08:08:13.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:13.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:08:13.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:08:13.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:08:13.65$vc4f8/vb=6,4 2006.161.08:08:13.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:08:13.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:08:13.65#ibcon#ireg 11 cls_cnt 2 2006.161.08:08:13.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:13.71#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:13.71#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:13.71#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:08:13.71#ibcon#first serial, iclass 27, count 2 2006.161.08:08:13.71#ibcon#enter sib2, iclass 27, count 2 2006.161.08:08:13.71#ibcon#flushed, iclass 27, count 2 2006.161.08:08:13.71#ibcon#about to write, iclass 27, count 2 2006.161.08:08:13.71#ibcon#wrote, iclass 27, count 2 2006.161.08:08:13.71#ibcon#about to read 3, iclass 27, count 2 2006.161.08:08:13.73#ibcon#read 3, iclass 27, count 2 2006.161.08:08:13.73#ibcon#about to read 4, iclass 27, count 2 2006.161.08:08:13.73#ibcon#read 4, iclass 27, count 2 2006.161.08:08:13.73#ibcon#about to read 5, iclass 27, count 2 2006.161.08:08:13.73#ibcon#read 5, iclass 27, count 2 2006.161.08:08:13.73#ibcon#about to read 6, iclass 27, count 2 2006.161.08:08:13.73#ibcon#read 6, iclass 27, count 2 2006.161.08:08:13.73#ibcon#end of sib2, iclass 27, count 2 2006.161.08:08:13.73#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:08:13.73#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:08:13.73#ibcon#[27=AT06-04\r\n] 2006.161.08:08:13.73#ibcon#*before write, iclass 27, count 2 2006.161.08:08:13.73#ibcon#enter sib2, iclass 27, count 2 2006.161.08:08:13.73#ibcon#flushed, iclass 27, count 2 2006.161.08:08:13.73#ibcon#about to write, iclass 27, count 2 2006.161.08:08:13.73#ibcon#wrote, iclass 27, count 2 2006.161.08:08:13.73#ibcon#about to read 3, iclass 27, count 2 2006.161.08:08:13.76#ibcon#read 3, iclass 27, count 2 2006.161.08:08:13.76#ibcon#about to read 4, iclass 27, count 2 2006.161.08:08:13.76#ibcon#read 4, iclass 27, count 2 2006.161.08:08:13.76#ibcon#about to read 5, iclass 27, count 2 2006.161.08:08:13.76#ibcon#read 5, iclass 27, count 2 2006.161.08:08:13.76#ibcon#about to read 6, iclass 27, count 2 2006.161.08:08:13.76#ibcon#read 6, iclass 27, count 2 2006.161.08:08:13.76#ibcon#end of sib2, iclass 27, count 2 2006.161.08:08:13.76#ibcon#*after write, iclass 27, count 2 2006.161.08:08:13.76#ibcon#*before return 0, iclass 27, count 2 2006.161.08:08:13.76#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:13.76#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:08:13.76#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:08:13.76#ibcon#ireg 7 cls_cnt 0 2006.161.08:08:13.76#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:13.88#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:13.88#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:13.88#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:08:13.88#ibcon#first serial, iclass 27, count 0 2006.161.08:08:13.88#ibcon#enter sib2, iclass 27, count 0 2006.161.08:08:13.88#ibcon#flushed, iclass 27, count 0 2006.161.08:08:13.88#ibcon#about to write, iclass 27, count 0 2006.161.08:08:13.88#ibcon#wrote, iclass 27, count 0 2006.161.08:08:13.88#ibcon#about to read 3, iclass 27, count 0 2006.161.08:08:13.90#ibcon#read 3, iclass 27, count 0 2006.161.08:08:13.90#ibcon#about to read 4, iclass 27, count 0 2006.161.08:08:13.90#ibcon#read 4, iclass 27, count 0 2006.161.08:08:13.90#ibcon#about to read 5, iclass 27, count 0 2006.161.08:08:13.90#ibcon#read 5, iclass 27, count 0 2006.161.08:08:13.90#ibcon#about to read 6, iclass 27, count 0 2006.161.08:08:13.90#ibcon#read 6, iclass 27, count 0 2006.161.08:08:13.90#ibcon#end of sib2, iclass 27, count 0 2006.161.08:08:13.90#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:08:13.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:08:13.90#ibcon#[27=USB\r\n] 2006.161.08:08:13.90#ibcon#*before write, iclass 27, count 0 2006.161.08:08:13.90#ibcon#enter sib2, iclass 27, count 0 2006.161.08:08:13.90#ibcon#flushed, iclass 27, count 0 2006.161.08:08:13.90#ibcon#about to write, iclass 27, count 0 2006.161.08:08:13.90#ibcon#wrote, iclass 27, count 0 2006.161.08:08:13.90#ibcon#about to read 3, iclass 27, count 0 2006.161.08:08:13.93#ibcon#read 3, iclass 27, count 0 2006.161.08:08:13.93#ibcon#about to read 4, iclass 27, count 0 2006.161.08:08:13.93#ibcon#read 4, iclass 27, count 0 2006.161.08:08:13.93#ibcon#about to read 5, iclass 27, count 0 2006.161.08:08:13.93#ibcon#read 5, iclass 27, count 0 2006.161.08:08:13.93#ibcon#about to read 6, iclass 27, count 0 2006.161.08:08:13.93#ibcon#read 6, iclass 27, count 0 2006.161.08:08:13.93#ibcon#end of sib2, iclass 27, count 0 2006.161.08:08:13.93#ibcon#*after write, iclass 27, count 0 2006.161.08:08:13.93#ibcon#*before return 0, iclass 27, count 0 2006.161.08:08:13.93#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:13.93#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:08:13.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:08:13.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:08:13.93$vc4f8/vabw=wide 2006.161.08:08:13.93#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:08:13.93#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:08:13.93#ibcon#ireg 8 cls_cnt 0 2006.161.08:08:13.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:13.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:13.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:13.93#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:08:13.93#ibcon#first serial, iclass 29, count 0 2006.161.08:08:13.93#ibcon#enter sib2, iclass 29, count 0 2006.161.08:08:13.93#ibcon#flushed, iclass 29, count 0 2006.161.08:08:13.93#ibcon#about to write, iclass 29, count 0 2006.161.08:08:13.93#ibcon#wrote, iclass 29, count 0 2006.161.08:08:13.93#ibcon#about to read 3, iclass 29, count 0 2006.161.08:08:13.95#ibcon#read 3, iclass 29, count 0 2006.161.08:08:13.95#ibcon#about to read 4, iclass 29, count 0 2006.161.08:08:13.95#ibcon#read 4, iclass 29, count 0 2006.161.08:08:13.95#ibcon#about to read 5, iclass 29, count 0 2006.161.08:08:13.95#ibcon#read 5, iclass 29, count 0 2006.161.08:08:13.95#ibcon#about to read 6, iclass 29, count 0 2006.161.08:08:13.95#ibcon#read 6, iclass 29, count 0 2006.161.08:08:13.95#ibcon#end of sib2, iclass 29, count 0 2006.161.08:08:13.95#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:08:13.95#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:08:13.95#ibcon#[25=BW32\r\n] 2006.161.08:08:13.95#ibcon#*before write, iclass 29, count 0 2006.161.08:08:13.95#ibcon#enter sib2, iclass 29, count 0 2006.161.08:08:13.95#ibcon#flushed, iclass 29, count 0 2006.161.08:08:13.95#ibcon#about to write, iclass 29, count 0 2006.161.08:08:13.95#ibcon#wrote, iclass 29, count 0 2006.161.08:08:13.95#ibcon#about to read 3, iclass 29, count 0 2006.161.08:08:13.98#ibcon#read 3, iclass 29, count 0 2006.161.08:08:13.98#ibcon#about to read 4, iclass 29, count 0 2006.161.08:08:13.98#ibcon#read 4, iclass 29, count 0 2006.161.08:08:13.98#ibcon#about to read 5, iclass 29, count 0 2006.161.08:08:13.98#ibcon#read 5, iclass 29, count 0 2006.161.08:08:13.98#ibcon#about to read 6, iclass 29, count 0 2006.161.08:08:13.98#ibcon#read 6, iclass 29, count 0 2006.161.08:08:13.98#ibcon#end of sib2, iclass 29, count 0 2006.161.08:08:13.98#ibcon#*after write, iclass 29, count 0 2006.161.08:08:13.98#ibcon#*before return 0, iclass 29, count 0 2006.161.08:08:13.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:13.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:08:13.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:08:13.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:08:13.98$vc4f8/vbbw=wide 2006.161.08:08:13.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:08:13.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:08:13.98#ibcon#ireg 8 cls_cnt 0 2006.161.08:08:13.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:08:14.05#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:08:14.05#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:08:14.05#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:08:14.05#ibcon#first serial, iclass 31, count 0 2006.161.08:08:14.05#ibcon#enter sib2, iclass 31, count 0 2006.161.08:08:14.05#ibcon#flushed, iclass 31, count 0 2006.161.08:08:14.05#ibcon#about to write, iclass 31, count 0 2006.161.08:08:14.05#ibcon#wrote, iclass 31, count 0 2006.161.08:08:14.05#ibcon#about to read 3, iclass 31, count 0 2006.161.08:08:14.07#ibcon#read 3, iclass 31, count 0 2006.161.08:08:14.07#ibcon#about to read 4, iclass 31, count 0 2006.161.08:08:14.07#ibcon#read 4, iclass 31, count 0 2006.161.08:08:14.07#ibcon#about to read 5, iclass 31, count 0 2006.161.08:08:14.07#ibcon#read 5, iclass 31, count 0 2006.161.08:08:14.07#ibcon#about to read 6, iclass 31, count 0 2006.161.08:08:14.07#ibcon#read 6, iclass 31, count 0 2006.161.08:08:14.07#ibcon#end of sib2, iclass 31, count 0 2006.161.08:08:14.07#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:08:14.07#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:08:14.07#ibcon#[27=BW32\r\n] 2006.161.08:08:14.07#ibcon#*before write, iclass 31, count 0 2006.161.08:08:14.07#ibcon#enter sib2, iclass 31, count 0 2006.161.08:08:14.07#ibcon#flushed, iclass 31, count 0 2006.161.08:08:14.07#ibcon#about to write, iclass 31, count 0 2006.161.08:08:14.07#ibcon#wrote, iclass 31, count 0 2006.161.08:08:14.07#ibcon#about to read 3, iclass 31, count 0 2006.161.08:08:14.10#ibcon#read 3, iclass 31, count 0 2006.161.08:08:14.10#ibcon#about to read 4, iclass 31, count 0 2006.161.08:08:14.10#ibcon#read 4, iclass 31, count 0 2006.161.08:08:14.10#ibcon#about to read 5, iclass 31, count 0 2006.161.08:08:14.10#ibcon#read 5, iclass 31, count 0 2006.161.08:08:14.10#ibcon#about to read 6, iclass 31, count 0 2006.161.08:08:14.10#ibcon#read 6, iclass 31, count 0 2006.161.08:08:14.10#ibcon#end of sib2, iclass 31, count 0 2006.161.08:08:14.10#ibcon#*after write, iclass 31, count 0 2006.161.08:08:14.10#ibcon#*before return 0, iclass 31, count 0 2006.161.08:08:14.10#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:08:14.10#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:08:14.10#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:08:14.10#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:08:14.10$4f8m12a/ifd4f 2006.161.08:08:14.10$ifd4f/lo= 2006.161.08:08:14.10$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:08:14.10$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:08:14.10$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:08:14.10$ifd4f/patch= 2006.161.08:08:14.10$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:08:14.10$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:08:14.10$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:08:14.10$4f8m12a/"form=m,16.000,1:2 2006.161.08:08:14.10$4f8m12a/"tpicd 2006.161.08:08:14.10$4f8m12a/echo=off 2006.161.08:08:14.11$4f8m12a/xlog=off 2006.161.08:08:14.11:!2006.161.08:08:40 2006.161.08:08:25.14#trakl#Source acquired 2006.161.08:08:25.14#flagr#flagr/antenna,acquired 2006.161.08:08:40.01:preob 2006.161.08:08:41.14/onsource/TRACKING 2006.161.08:08:41.14:!2006.161.08:08:50 2006.161.08:08:50.00:data_valid=on 2006.161.08:08:50.00:midob 2006.161.08:08:50.14/onsource/TRACKING 2006.161.08:08:50.14/wx/24.00,1002.5,86 2006.161.08:08:50.33/cable/+6.4997E-03 2006.161.08:08:51.42/va/01,08,usb,yes,29,31 2006.161.08:08:51.42/va/02,07,usb,yes,29,30 2006.161.08:08:51.42/va/03,06,usb,yes,31,31 2006.161.08:08:51.42/va/04,07,usb,yes,30,32 2006.161.08:08:51.42/va/05,07,usb,yes,30,32 2006.161.08:08:51.42/va/06,06,usb,yes,29,29 2006.161.08:08:51.42/va/07,06,usb,yes,29,29 2006.161.08:08:51.42/va/08,07,usb,yes,28,27 2006.161.08:08:51.65/valo/01,532.99,yes,locked 2006.161.08:08:51.65/valo/02,572.99,yes,locked 2006.161.08:08:51.65/valo/03,672.99,yes,locked 2006.161.08:08:51.65/valo/04,832.99,yes,locked 2006.161.08:08:51.65/valo/05,652.99,yes,locked 2006.161.08:08:51.65/valo/06,772.99,yes,locked 2006.161.08:08:51.65/valo/07,832.99,yes,locked 2006.161.08:08:51.65/valo/08,852.99,yes,locked 2006.161.08:08:52.74/vb/01,04,usb,yes,29,28 2006.161.08:08:52.74/vb/02,04,usb,yes,31,32 2006.161.08:08:52.74/vb/03,04,usb,yes,27,31 2006.161.08:08:52.74/vb/04,04,usb,yes,28,28 2006.161.08:08:52.74/vb/05,04,usb,yes,27,30 2006.161.08:08:52.74/vb/06,04,usb,yes,28,30 2006.161.08:08:52.74/vb/07,04,usb,yes,29,29 2006.161.08:08:52.74/vb/08,04,usb,yes,27,30 2006.161.08:08:52.97/vblo/01,632.99,yes,locked 2006.161.08:08:52.97/vblo/02,640.99,yes,locked 2006.161.08:08:52.97/vblo/03,656.99,yes,locked 2006.161.08:08:52.97/vblo/04,712.99,yes,locked 2006.161.08:08:52.97/vblo/05,744.99,yes,locked 2006.161.08:08:52.97/vblo/06,752.99,yes,locked 2006.161.08:08:52.97/vblo/07,734.99,yes,locked 2006.161.08:08:52.97/vblo/08,744.99,yes,locked 2006.161.08:08:53.12/vabw/8 2006.161.08:08:53.27/vbbw/8 2006.161.08:08:53.37/xfe/off,on,14.7 2006.161.08:08:53.76/ifatt/23,28,28,28 2006.161.08:08:54.07/fmout-gps/S +4.50E-07 2006.161.08:08:54.11:!2006.161.08:09:50 2006.161.08:09:50.00:data_valid=off 2006.161.08:09:50.01:postob 2006.161.08:09:50.17/cable/+6.5008E-03 2006.161.08:09:50.18/wx/24.00,1002.5,86 2006.161.08:09:51.07/fmout-gps/S +4.50E-07 2006.161.08:09:51.08:scan_name=161-0811,k06161,130 2006.161.08:09:51.08:source=0722+145,072516.81,142513.7,2000.0,ccw 2006.161.08:09:51.14#flagr#flagr/antenna,new-source 2006.161.08:09:52.14:checkk5 2006.161.08:09:52.63/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:09:53.04/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:09:53.46/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:09:53.97/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:09:54.62/chk_obsdata//k5ts1/T1610808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:09:55.03/chk_obsdata//k5ts2/T1610808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:09:55.42/chk_obsdata//k5ts3/T1610808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:09:55.84/chk_obsdata//k5ts4/T1610808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:09:56.65/k5log//k5ts1_log_newline 2006.161.08:09:57.40/k5log//k5ts2_log_newline 2006.161.08:09:58.59/k5log//k5ts3_log_newline 2006.161.08:09:59.38/k5log//k5ts4_log_newline 2006.161.08:09:59.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:09:59.40:4f8m12a=2 2006.161.08:09:59.40$4f8m12a/echo=on 2006.161.08:09:59.40$4f8m12a/pcalon 2006.161.08:09:59.40$pcalon/"no phase cal control is implemented here 2006.161.08:09:59.40$4f8m12a/"tpicd=stop 2006.161.08:09:59.40$4f8m12a/vc4f8 2006.161.08:09:59.40$vc4f8/valo=1,532.99 2006.161.08:09:59.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:09:59.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:09:59.41#ibcon#ireg 17 cls_cnt 0 2006.161.08:09:59.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:09:59.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:09:59.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:09:59.41#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:09:59.41#ibcon#first serial, iclass 4, count 0 2006.161.08:09:59.41#ibcon#enter sib2, iclass 4, count 0 2006.161.08:09:59.41#ibcon#flushed, iclass 4, count 0 2006.161.08:09:59.41#ibcon#about to write, iclass 4, count 0 2006.161.08:09:59.41#ibcon#wrote, iclass 4, count 0 2006.161.08:09:59.41#ibcon#about to read 3, iclass 4, count 0 2006.161.08:09:59.45#ibcon#read 3, iclass 4, count 0 2006.161.08:09:59.45#ibcon#about to read 4, iclass 4, count 0 2006.161.08:09:59.45#ibcon#read 4, iclass 4, count 0 2006.161.08:09:59.45#ibcon#about to read 5, iclass 4, count 0 2006.161.08:09:59.45#ibcon#read 5, iclass 4, count 0 2006.161.08:09:59.45#ibcon#about to read 6, iclass 4, count 0 2006.161.08:09:59.45#ibcon#read 6, iclass 4, count 0 2006.161.08:09:59.45#ibcon#end of sib2, iclass 4, count 0 2006.161.08:09:59.45#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:09:59.45#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:09:59.45#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:09:59.45#ibcon#*before write, iclass 4, count 0 2006.161.08:09:59.45#ibcon#enter sib2, iclass 4, count 0 2006.161.08:09:59.45#ibcon#flushed, iclass 4, count 0 2006.161.08:09:59.45#ibcon#about to write, iclass 4, count 0 2006.161.08:09:59.45#ibcon#wrote, iclass 4, count 0 2006.161.08:09:59.45#ibcon#about to read 3, iclass 4, count 0 2006.161.08:09:59.49#ibcon#read 3, iclass 4, count 0 2006.161.08:09:59.49#ibcon#about to read 4, iclass 4, count 0 2006.161.08:09:59.49#ibcon#read 4, iclass 4, count 0 2006.161.08:09:59.49#ibcon#about to read 5, iclass 4, count 0 2006.161.08:09:59.49#ibcon#read 5, iclass 4, count 0 2006.161.08:09:59.49#ibcon#about to read 6, iclass 4, count 0 2006.161.08:09:59.49#ibcon#read 6, iclass 4, count 0 2006.161.08:09:59.49#ibcon#end of sib2, iclass 4, count 0 2006.161.08:09:59.49#ibcon#*after write, iclass 4, count 0 2006.161.08:09:59.49#ibcon#*before return 0, iclass 4, count 0 2006.161.08:09:59.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:09:59.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:09:59.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:09:59.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:09:59.49$vc4f8/va=1,8 2006.161.08:09:59.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:09:59.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:09:59.49#ibcon#ireg 11 cls_cnt 2 2006.161.08:09:59.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:09:59.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:09:59.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:09:59.49#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:09:59.49#ibcon#first serial, iclass 6, count 2 2006.161.08:09:59.49#ibcon#enter sib2, iclass 6, count 2 2006.161.08:09:59.49#ibcon#flushed, iclass 6, count 2 2006.161.08:09:59.49#ibcon#about to write, iclass 6, count 2 2006.161.08:09:59.49#ibcon#wrote, iclass 6, count 2 2006.161.08:09:59.49#ibcon#about to read 3, iclass 6, count 2 2006.161.08:09:59.52#ibcon#read 3, iclass 6, count 2 2006.161.08:09:59.52#ibcon#about to read 4, iclass 6, count 2 2006.161.08:09:59.52#ibcon#read 4, iclass 6, count 2 2006.161.08:09:59.52#ibcon#about to read 5, iclass 6, count 2 2006.161.08:09:59.52#ibcon#read 5, iclass 6, count 2 2006.161.08:09:59.52#ibcon#about to read 6, iclass 6, count 2 2006.161.08:09:59.52#ibcon#read 6, iclass 6, count 2 2006.161.08:09:59.52#ibcon#end of sib2, iclass 6, count 2 2006.161.08:09:59.52#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:09:59.52#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:09:59.52#ibcon#[25=AT01-08\r\n] 2006.161.08:09:59.52#ibcon#*before write, iclass 6, count 2 2006.161.08:09:59.52#ibcon#enter sib2, iclass 6, count 2 2006.161.08:09:59.52#ibcon#flushed, iclass 6, count 2 2006.161.08:09:59.52#ibcon#about to write, iclass 6, count 2 2006.161.08:09:59.52#ibcon#wrote, iclass 6, count 2 2006.161.08:09:59.52#ibcon#about to read 3, iclass 6, count 2 2006.161.08:09:59.54#ibcon#read 3, iclass 6, count 2 2006.161.08:09:59.54#ibcon#about to read 4, iclass 6, count 2 2006.161.08:09:59.54#ibcon#read 4, iclass 6, count 2 2006.161.08:09:59.54#ibcon#about to read 5, iclass 6, count 2 2006.161.08:09:59.54#ibcon#read 5, iclass 6, count 2 2006.161.08:09:59.54#ibcon#about to read 6, iclass 6, count 2 2006.161.08:09:59.54#ibcon#read 6, iclass 6, count 2 2006.161.08:09:59.54#ibcon#end of sib2, iclass 6, count 2 2006.161.08:09:59.54#ibcon#*after write, iclass 6, count 2 2006.161.08:09:59.54#ibcon#*before return 0, iclass 6, count 2 2006.161.08:09:59.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:09:59.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:09:59.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:09:59.54#ibcon#ireg 7 cls_cnt 0 2006.161.08:09:59.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:09:59.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:09:59.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:09:59.66#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:09:59.66#ibcon#first serial, iclass 6, count 0 2006.161.08:09:59.66#ibcon#enter sib2, iclass 6, count 0 2006.161.08:09:59.66#ibcon#flushed, iclass 6, count 0 2006.161.08:09:59.66#ibcon#about to write, iclass 6, count 0 2006.161.08:09:59.66#ibcon#wrote, iclass 6, count 0 2006.161.08:09:59.66#ibcon#about to read 3, iclass 6, count 0 2006.161.08:09:59.68#ibcon#read 3, iclass 6, count 0 2006.161.08:09:59.68#ibcon#about to read 4, iclass 6, count 0 2006.161.08:09:59.68#ibcon#read 4, iclass 6, count 0 2006.161.08:09:59.68#ibcon#about to read 5, iclass 6, count 0 2006.161.08:09:59.68#ibcon#read 5, iclass 6, count 0 2006.161.08:09:59.68#ibcon#about to read 6, iclass 6, count 0 2006.161.08:09:59.68#ibcon#read 6, iclass 6, count 0 2006.161.08:09:59.68#ibcon#end of sib2, iclass 6, count 0 2006.161.08:09:59.68#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:09:59.68#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:09:59.68#ibcon#[25=USB\r\n] 2006.161.08:09:59.68#ibcon#*before write, iclass 6, count 0 2006.161.08:09:59.68#ibcon#enter sib2, iclass 6, count 0 2006.161.08:09:59.68#ibcon#flushed, iclass 6, count 0 2006.161.08:09:59.68#ibcon#about to write, iclass 6, count 0 2006.161.08:09:59.68#ibcon#wrote, iclass 6, count 0 2006.161.08:09:59.68#ibcon#about to read 3, iclass 6, count 0 2006.161.08:09:59.71#ibcon#read 3, iclass 6, count 0 2006.161.08:09:59.71#ibcon#about to read 4, iclass 6, count 0 2006.161.08:09:59.71#ibcon#read 4, iclass 6, count 0 2006.161.08:09:59.71#ibcon#about to read 5, iclass 6, count 0 2006.161.08:09:59.71#ibcon#read 5, iclass 6, count 0 2006.161.08:09:59.71#ibcon#about to read 6, iclass 6, count 0 2006.161.08:09:59.71#ibcon#read 6, iclass 6, count 0 2006.161.08:09:59.71#ibcon#end of sib2, iclass 6, count 0 2006.161.08:09:59.71#ibcon#*after write, iclass 6, count 0 2006.161.08:09:59.71#ibcon#*before return 0, iclass 6, count 0 2006.161.08:09:59.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:09:59.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:09:59.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:09:59.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:09:59.71$vc4f8/valo=2,572.99 2006.161.08:09:59.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:09:59.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:09:59.71#ibcon#ireg 17 cls_cnt 0 2006.161.08:09:59.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:09:59.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:09:59.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:09:59.71#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:09:59.71#ibcon#first serial, iclass 10, count 0 2006.161.08:09:59.71#ibcon#enter sib2, iclass 10, count 0 2006.161.08:09:59.71#ibcon#flushed, iclass 10, count 0 2006.161.08:09:59.71#ibcon#about to write, iclass 10, count 0 2006.161.08:09:59.71#ibcon#wrote, iclass 10, count 0 2006.161.08:09:59.71#ibcon#about to read 3, iclass 10, count 0 2006.161.08:09:59.74#ibcon#read 3, iclass 10, count 0 2006.161.08:09:59.74#ibcon#about to read 4, iclass 10, count 0 2006.161.08:09:59.74#ibcon#read 4, iclass 10, count 0 2006.161.08:09:59.74#ibcon#about to read 5, iclass 10, count 0 2006.161.08:09:59.74#ibcon#read 5, iclass 10, count 0 2006.161.08:09:59.74#ibcon#about to read 6, iclass 10, count 0 2006.161.08:09:59.74#ibcon#read 6, iclass 10, count 0 2006.161.08:09:59.74#ibcon#end of sib2, iclass 10, count 0 2006.161.08:09:59.74#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:09:59.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:09:59.74#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:09:59.74#ibcon#*before write, iclass 10, count 0 2006.161.08:09:59.74#ibcon#enter sib2, iclass 10, count 0 2006.161.08:09:59.74#ibcon#flushed, iclass 10, count 0 2006.161.08:09:59.74#ibcon#about to write, iclass 10, count 0 2006.161.08:09:59.74#ibcon#wrote, iclass 10, count 0 2006.161.08:09:59.74#ibcon#about to read 3, iclass 10, count 0 2006.161.08:09:59.78#ibcon#read 3, iclass 10, count 0 2006.161.08:09:59.78#ibcon#about to read 4, iclass 10, count 0 2006.161.08:09:59.78#ibcon#read 4, iclass 10, count 0 2006.161.08:09:59.78#ibcon#about to read 5, iclass 10, count 0 2006.161.08:09:59.78#ibcon#read 5, iclass 10, count 0 2006.161.08:09:59.78#ibcon#about to read 6, iclass 10, count 0 2006.161.08:09:59.78#ibcon#read 6, iclass 10, count 0 2006.161.08:09:59.78#ibcon#end of sib2, iclass 10, count 0 2006.161.08:09:59.78#ibcon#*after write, iclass 10, count 0 2006.161.08:09:59.78#ibcon#*before return 0, iclass 10, count 0 2006.161.08:09:59.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:09:59.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:09:59.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:09:59.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:09:59.78$vc4f8/va=2,7 2006.161.08:09:59.78#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.08:09:59.78#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.08:09:59.78#ibcon#ireg 11 cls_cnt 2 2006.161.08:09:59.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:09:59.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:09:59.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:09:59.83#ibcon#enter wrdev, iclass 12, count 2 2006.161.08:09:59.83#ibcon#first serial, iclass 12, count 2 2006.161.08:09:59.83#ibcon#enter sib2, iclass 12, count 2 2006.161.08:09:59.83#ibcon#flushed, iclass 12, count 2 2006.161.08:09:59.83#ibcon#about to write, iclass 12, count 2 2006.161.08:09:59.83#ibcon#wrote, iclass 12, count 2 2006.161.08:09:59.83#ibcon#about to read 3, iclass 12, count 2 2006.161.08:09:59.86#ibcon#read 3, iclass 12, count 2 2006.161.08:09:59.86#ibcon#about to read 4, iclass 12, count 2 2006.161.08:09:59.86#ibcon#read 4, iclass 12, count 2 2006.161.08:09:59.86#ibcon#about to read 5, iclass 12, count 2 2006.161.08:09:59.86#ibcon#read 5, iclass 12, count 2 2006.161.08:09:59.86#ibcon#about to read 6, iclass 12, count 2 2006.161.08:09:59.86#ibcon#read 6, iclass 12, count 2 2006.161.08:09:59.86#ibcon#end of sib2, iclass 12, count 2 2006.161.08:09:59.86#ibcon#*mode == 0, iclass 12, count 2 2006.161.08:09:59.86#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.08:09:59.86#ibcon#[25=AT02-07\r\n] 2006.161.08:09:59.86#ibcon#*before write, iclass 12, count 2 2006.161.08:09:59.86#ibcon#enter sib2, iclass 12, count 2 2006.161.08:09:59.86#ibcon#flushed, iclass 12, count 2 2006.161.08:09:59.86#ibcon#about to write, iclass 12, count 2 2006.161.08:09:59.86#ibcon#wrote, iclass 12, count 2 2006.161.08:09:59.86#ibcon#about to read 3, iclass 12, count 2 2006.161.08:09:59.89#ibcon#read 3, iclass 12, count 2 2006.161.08:09:59.89#ibcon#about to read 4, iclass 12, count 2 2006.161.08:09:59.89#ibcon#read 4, iclass 12, count 2 2006.161.08:09:59.89#ibcon#about to read 5, iclass 12, count 2 2006.161.08:09:59.89#ibcon#read 5, iclass 12, count 2 2006.161.08:09:59.89#ibcon#about to read 6, iclass 12, count 2 2006.161.08:09:59.89#ibcon#read 6, iclass 12, count 2 2006.161.08:09:59.89#ibcon#end of sib2, iclass 12, count 2 2006.161.08:09:59.89#ibcon#*after write, iclass 12, count 2 2006.161.08:09:59.89#ibcon#*before return 0, iclass 12, count 2 2006.161.08:09:59.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:09:59.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:09:59.89#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.08:09:59.89#ibcon#ireg 7 cls_cnt 0 2006.161.08:09:59.89#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:00.01#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:00.01#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:00.01#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:10:00.01#ibcon#first serial, iclass 12, count 0 2006.161.08:10:00.01#ibcon#enter sib2, iclass 12, count 0 2006.161.08:10:00.01#ibcon#flushed, iclass 12, count 0 2006.161.08:10:00.01#ibcon#about to write, iclass 12, count 0 2006.161.08:10:00.01#ibcon#wrote, iclass 12, count 0 2006.161.08:10:00.01#ibcon#about to read 3, iclass 12, count 0 2006.161.08:10:00.03#ibcon#read 3, iclass 12, count 0 2006.161.08:10:00.03#ibcon#about to read 4, iclass 12, count 0 2006.161.08:10:00.03#ibcon#read 4, iclass 12, count 0 2006.161.08:10:00.03#ibcon#about to read 5, iclass 12, count 0 2006.161.08:10:00.03#ibcon#read 5, iclass 12, count 0 2006.161.08:10:00.03#ibcon#about to read 6, iclass 12, count 0 2006.161.08:10:00.03#ibcon#read 6, iclass 12, count 0 2006.161.08:10:00.03#ibcon#end of sib2, iclass 12, count 0 2006.161.08:10:00.03#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:10:00.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:10:00.03#ibcon#[25=USB\r\n] 2006.161.08:10:00.03#ibcon#*before write, iclass 12, count 0 2006.161.08:10:00.03#ibcon#enter sib2, iclass 12, count 0 2006.161.08:10:00.03#ibcon#flushed, iclass 12, count 0 2006.161.08:10:00.03#ibcon#about to write, iclass 12, count 0 2006.161.08:10:00.03#ibcon#wrote, iclass 12, count 0 2006.161.08:10:00.03#ibcon#about to read 3, iclass 12, count 0 2006.161.08:10:00.06#ibcon#read 3, iclass 12, count 0 2006.161.08:10:00.06#ibcon#about to read 4, iclass 12, count 0 2006.161.08:10:00.06#ibcon#read 4, iclass 12, count 0 2006.161.08:10:00.06#ibcon#about to read 5, iclass 12, count 0 2006.161.08:10:00.06#ibcon#read 5, iclass 12, count 0 2006.161.08:10:00.06#ibcon#about to read 6, iclass 12, count 0 2006.161.08:10:00.06#ibcon#read 6, iclass 12, count 0 2006.161.08:10:00.06#ibcon#end of sib2, iclass 12, count 0 2006.161.08:10:00.06#ibcon#*after write, iclass 12, count 0 2006.161.08:10:00.06#ibcon#*before return 0, iclass 12, count 0 2006.161.08:10:00.06#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:00.06#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:00.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:10:00.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:10:00.06$vc4f8/valo=3,672.99 2006.161.08:10:00.06#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:10:00.06#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:10:00.06#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:00.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:00.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:00.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:00.06#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:10:00.06#ibcon#first serial, iclass 14, count 0 2006.161.08:10:00.06#ibcon#enter sib2, iclass 14, count 0 2006.161.08:10:00.06#ibcon#flushed, iclass 14, count 0 2006.161.08:10:00.06#ibcon#about to write, iclass 14, count 0 2006.161.08:10:00.06#ibcon#wrote, iclass 14, count 0 2006.161.08:10:00.06#ibcon#about to read 3, iclass 14, count 0 2006.161.08:10:00.08#ibcon#read 3, iclass 14, count 0 2006.161.08:10:00.08#ibcon#about to read 4, iclass 14, count 0 2006.161.08:10:00.08#ibcon#read 4, iclass 14, count 0 2006.161.08:10:00.08#ibcon#about to read 5, iclass 14, count 0 2006.161.08:10:00.08#ibcon#read 5, iclass 14, count 0 2006.161.08:10:00.08#ibcon#about to read 6, iclass 14, count 0 2006.161.08:10:00.08#ibcon#read 6, iclass 14, count 0 2006.161.08:10:00.08#ibcon#end of sib2, iclass 14, count 0 2006.161.08:10:00.08#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:10:00.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:10:00.08#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:10:00.08#ibcon#*before write, iclass 14, count 0 2006.161.08:10:00.08#ibcon#enter sib2, iclass 14, count 0 2006.161.08:10:00.08#ibcon#flushed, iclass 14, count 0 2006.161.08:10:00.08#ibcon#about to write, iclass 14, count 0 2006.161.08:10:00.08#ibcon#wrote, iclass 14, count 0 2006.161.08:10:00.08#ibcon#about to read 3, iclass 14, count 0 2006.161.08:10:00.12#ibcon#read 3, iclass 14, count 0 2006.161.08:10:00.12#ibcon#about to read 4, iclass 14, count 0 2006.161.08:10:00.12#ibcon#read 4, iclass 14, count 0 2006.161.08:10:00.12#ibcon#about to read 5, iclass 14, count 0 2006.161.08:10:00.12#ibcon#read 5, iclass 14, count 0 2006.161.08:10:00.12#ibcon#about to read 6, iclass 14, count 0 2006.161.08:10:00.12#ibcon#read 6, iclass 14, count 0 2006.161.08:10:00.12#ibcon#end of sib2, iclass 14, count 0 2006.161.08:10:00.12#ibcon#*after write, iclass 14, count 0 2006.161.08:10:00.12#ibcon#*before return 0, iclass 14, count 0 2006.161.08:10:00.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:00.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:00.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:10:00.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:10:00.12$vc4f8/va=3,6 2006.161.08:10:00.12#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.08:10:00.12#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.08:10:00.12#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:00.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:00.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:00.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:00.18#ibcon#enter wrdev, iclass 16, count 2 2006.161.08:10:00.18#ibcon#first serial, iclass 16, count 2 2006.161.08:10:00.18#ibcon#enter sib2, iclass 16, count 2 2006.161.08:10:00.18#ibcon#flushed, iclass 16, count 2 2006.161.08:10:00.18#ibcon#about to write, iclass 16, count 2 2006.161.08:10:00.18#ibcon#wrote, iclass 16, count 2 2006.161.08:10:00.18#ibcon#about to read 3, iclass 16, count 2 2006.161.08:10:00.20#ibcon#read 3, iclass 16, count 2 2006.161.08:10:00.20#ibcon#about to read 4, iclass 16, count 2 2006.161.08:10:00.20#ibcon#read 4, iclass 16, count 2 2006.161.08:10:00.20#ibcon#about to read 5, iclass 16, count 2 2006.161.08:10:00.20#ibcon#read 5, iclass 16, count 2 2006.161.08:10:00.20#ibcon#about to read 6, iclass 16, count 2 2006.161.08:10:00.20#ibcon#read 6, iclass 16, count 2 2006.161.08:10:00.20#ibcon#end of sib2, iclass 16, count 2 2006.161.08:10:00.20#ibcon#*mode == 0, iclass 16, count 2 2006.161.08:10:00.20#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.08:10:00.20#ibcon#[25=AT03-06\r\n] 2006.161.08:10:00.20#ibcon#*before write, iclass 16, count 2 2006.161.08:10:00.20#ibcon#enter sib2, iclass 16, count 2 2006.161.08:10:00.20#ibcon#flushed, iclass 16, count 2 2006.161.08:10:00.20#ibcon#about to write, iclass 16, count 2 2006.161.08:10:00.20#ibcon#wrote, iclass 16, count 2 2006.161.08:10:00.20#ibcon#about to read 3, iclass 16, count 2 2006.161.08:10:00.23#ibcon#read 3, iclass 16, count 2 2006.161.08:10:00.23#ibcon#about to read 4, iclass 16, count 2 2006.161.08:10:00.23#ibcon#read 4, iclass 16, count 2 2006.161.08:10:00.23#ibcon#about to read 5, iclass 16, count 2 2006.161.08:10:00.23#ibcon#read 5, iclass 16, count 2 2006.161.08:10:00.23#ibcon#about to read 6, iclass 16, count 2 2006.161.08:10:00.23#ibcon#read 6, iclass 16, count 2 2006.161.08:10:00.23#ibcon#end of sib2, iclass 16, count 2 2006.161.08:10:00.23#ibcon#*after write, iclass 16, count 2 2006.161.08:10:00.23#ibcon#*before return 0, iclass 16, count 2 2006.161.08:10:00.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:00.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:00.23#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.08:10:00.23#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:00.23#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:00.35#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:00.35#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:00.35#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:10:00.35#ibcon#first serial, iclass 16, count 0 2006.161.08:10:00.35#ibcon#enter sib2, iclass 16, count 0 2006.161.08:10:00.35#ibcon#flushed, iclass 16, count 0 2006.161.08:10:00.35#ibcon#about to write, iclass 16, count 0 2006.161.08:10:00.35#ibcon#wrote, iclass 16, count 0 2006.161.08:10:00.35#ibcon#about to read 3, iclass 16, count 0 2006.161.08:10:00.37#ibcon#read 3, iclass 16, count 0 2006.161.08:10:00.37#ibcon#about to read 4, iclass 16, count 0 2006.161.08:10:00.37#ibcon#read 4, iclass 16, count 0 2006.161.08:10:00.37#ibcon#about to read 5, iclass 16, count 0 2006.161.08:10:00.37#ibcon#read 5, iclass 16, count 0 2006.161.08:10:00.37#ibcon#about to read 6, iclass 16, count 0 2006.161.08:10:00.37#ibcon#read 6, iclass 16, count 0 2006.161.08:10:00.37#ibcon#end of sib2, iclass 16, count 0 2006.161.08:10:00.37#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:10:00.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:10:00.37#ibcon#[25=USB\r\n] 2006.161.08:10:00.37#ibcon#*before write, iclass 16, count 0 2006.161.08:10:00.37#ibcon#enter sib2, iclass 16, count 0 2006.161.08:10:00.37#ibcon#flushed, iclass 16, count 0 2006.161.08:10:00.37#ibcon#about to write, iclass 16, count 0 2006.161.08:10:00.37#ibcon#wrote, iclass 16, count 0 2006.161.08:10:00.37#ibcon#about to read 3, iclass 16, count 0 2006.161.08:10:00.40#ibcon#read 3, iclass 16, count 0 2006.161.08:10:00.40#ibcon#about to read 4, iclass 16, count 0 2006.161.08:10:00.40#ibcon#read 4, iclass 16, count 0 2006.161.08:10:00.40#ibcon#about to read 5, iclass 16, count 0 2006.161.08:10:00.40#ibcon#read 5, iclass 16, count 0 2006.161.08:10:00.40#ibcon#about to read 6, iclass 16, count 0 2006.161.08:10:00.40#ibcon#read 6, iclass 16, count 0 2006.161.08:10:00.40#ibcon#end of sib2, iclass 16, count 0 2006.161.08:10:00.40#ibcon#*after write, iclass 16, count 0 2006.161.08:10:00.40#ibcon#*before return 0, iclass 16, count 0 2006.161.08:10:00.40#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:00.40#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:00.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:10:00.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:10:00.40$vc4f8/valo=4,832.99 2006.161.08:10:00.40#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.08:10:00.40#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.08:10:00.40#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:00.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:00.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:00.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:00.40#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:10:00.40#ibcon#first serial, iclass 18, count 0 2006.161.08:10:00.40#ibcon#enter sib2, iclass 18, count 0 2006.161.08:10:00.40#ibcon#flushed, iclass 18, count 0 2006.161.08:10:00.40#ibcon#about to write, iclass 18, count 0 2006.161.08:10:00.40#ibcon#wrote, iclass 18, count 0 2006.161.08:10:00.40#ibcon#about to read 3, iclass 18, count 0 2006.161.08:10:00.42#ibcon#read 3, iclass 18, count 0 2006.161.08:10:00.42#ibcon#about to read 4, iclass 18, count 0 2006.161.08:10:00.42#ibcon#read 4, iclass 18, count 0 2006.161.08:10:00.42#ibcon#about to read 5, iclass 18, count 0 2006.161.08:10:00.42#ibcon#read 5, iclass 18, count 0 2006.161.08:10:00.42#ibcon#about to read 6, iclass 18, count 0 2006.161.08:10:00.42#ibcon#read 6, iclass 18, count 0 2006.161.08:10:00.42#ibcon#end of sib2, iclass 18, count 0 2006.161.08:10:00.42#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:10:00.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:10:00.42#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:10:00.42#ibcon#*before write, iclass 18, count 0 2006.161.08:10:00.42#ibcon#enter sib2, iclass 18, count 0 2006.161.08:10:00.42#ibcon#flushed, iclass 18, count 0 2006.161.08:10:00.42#ibcon#about to write, iclass 18, count 0 2006.161.08:10:00.42#ibcon#wrote, iclass 18, count 0 2006.161.08:10:00.42#ibcon#about to read 3, iclass 18, count 0 2006.161.08:10:00.46#ibcon#read 3, iclass 18, count 0 2006.161.08:10:00.46#ibcon#about to read 4, iclass 18, count 0 2006.161.08:10:00.46#ibcon#read 4, iclass 18, count 0 2006.161.08:10:00.46#ibcon#about to read 5, iclass 18, count 0 2006.161.08:10:00.46#ibcon#read 5, iclass 18, count 0 2006.161.08:10:00.46#ibcon#about to read 6, iclass 18, count 0 2006.161.08:10:00.46#ibcon#read 6, iclass 18, count 0 2006.161.08:10:00.46#ibcon#end of sib2, iclass 18, count 0 2006.161.08:10:00.46#ibcon#*after write, iclass 18, count 0 2006.161.08:10:00.46#ibcon#*before return 0, iclass 18, count 0 2006.161.08:10:00.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:00.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:00.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:10:00.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:10:00.46$vc4f8/va=4,7 2006.161.08:10:00.46#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.08:10:00.46#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.08:10:00.46#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:00.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:00.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:00.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:00.52#ibcon#enter wrdev, iclass 20, count 2 2006.161.08:10:00.52#ibcon#first serial, iclass 20, count 2 2006.161.08:10:00.52#ibcon#enter sib2, iclass 20, count 2 2006.161.08:10:00.52#ibcon#flushed, iclass 20, count 2 2006.161.08:10:00.52#ibcon#about to write, iclass 20, count 2 2006.161.08:10:00.52#ibcon#wrote, iclass 20, count 2 2006.161.08:10:00.52#ibcon#about to read 3, iclass 20, count 2 2006.161.08:10:00.54#ibcon#read 3, iclass 20, count 2 2006.161.08:10:00.54#ibcon#about to read 4, iclass 20, count 2 2006.161.08:10:00.54#ibcon#read 4, iclass 20, count 2 2006.161.08:10:00.54#ibcon#about to read 5, iclass 20, count 2 2006.161.08:10:00.54#ibcon#read 5, iclass 20, count 2 2006.161.08:10:00.54#ibcon#about to read 6, iclass 20, count 2 2006.161.08:10:00.54#ibcon#read 6, iclass 20, count 2 2006.161.08:10:00.54#ibcon#end of sib2, iclass 20, count 2 2006.161.08:10:00.54#ibcon#*mode == 0, iclass 20, count 2 2006.161.08:10:00.54#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.08:10:00.54#ibcon#[25=AT04-07\r\n] 2006.161.08:10:00.54#ibcon#*before write, iclass 20, count 2 2006.161.08:10:00.54#ibcon#enter sib2, iclass 20, count 2 2006.161.08:10:00.54#ibcon#flushed, iclass 20, count 2 2006.161.08:10:00.54#ibcon#about to write, iclass 20, count 2 2006.161.08:10:00.54#ibcon#wrote, iclass 20, count 2 2006.161.08:10:00.54#ibcon#about to read 3, iclass 20, count 2 2006.161.08:10:00.57#ibcon#read 3, iclass 20, count 2 2006.161.08:10:00.57#ibcon#about to read 4, iclass 20, count 2 2006.161.08:10:00.57#ibcon#read 4, iclass 20, count 2 2006.161.08:10:00.57#ibcon#about to read 5, iclass 20, count 2 2006.161.08:10:00.57#ibcon#read 5, iclass 20, count 2 2006.161.08:10:00.57#ibcon#about to read 6, iclass 20, count 2 2006.161.08:10:00.57#ibcon#read 6, iclass 20, count 2 2006.161.08:10:00.57#ibcon#end of sib2, iclass 20, count 2 2006.161.08:10:00.57#ibcon#*after write, iclass 20, count 2 2006.161.08:10:00.57#ibcon#*before return 0, iclass 20, count 2 2006.161.08:10:00.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:00.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:00.57#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.08:10:00.57#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:00.57#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:00.69#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:00.69#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:00.69#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:10:00.69#ibcon#first serial, iclass 20, count 0 2006.161.08:10:00.69#ibcon#enter sib2, iclass 20, count 0 2006.161.08:10:00.69#ibcon#flushed, iclass 20, count 0 2006.161.08:10:00.69#ibcon#about to write, iclass 20, count 0 2006.161.08:10:00.69#ibcon#wrote, iclass 20, count 0 2006.161.08:10:00.69#ibcon#about to read 3, iclass 20, count 0 2006.161.08:10:00.71#ibcon#read 3, iclass 20, count 0 2006.161.08:10:00.71#ibcon#about to read 4, iclass 20, count 0 2006.161.08:10:00.71#ibcon#read 4, iclass 20, count 0 2006.161.08:10:00.71#ibcon#about to read 5, iclass 20, count 0 2006.161.08:10:00.71#ibcon#read 5, iclass 20, count 0 2006.161.08:10:00.71#ibcon#about to read 6, iclass 20, count 0 2006.161.08:10:00.71#ibcon#read 6, iclass 20, count 0 2006.161.08:10:00.71#ibcon#end of sib2, iclass 20, count 0 2006.161.08:10:00.71#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:10:00.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:10:00.71#ibcon#[25=USB\r\n] 2006.161.08:10:00.71#ibcon#*before write, iclass 20, count 0 2006.161.08:10:00.71#ibcon#enter sib2, iclass 20, count 0 2006.161.08:10:00.71#ibcon#flushed, iclass 20, count 0 2006.161.08:10:00.71#ibcon#about to write, iclass 20, count 0 2006.161.08:10:00.71#ibcon#wrote, iclass 20, count 0 2006.161.08:10:00.71#ibcon#about to read 3, iclass 20, count 0 2006.161.08:10:00.74#ibcon#read 3, iclass 20, count 0 2006.161.08:10:00.74#ibcon#about to read 4, iclass 20, count 0 2006.161.08:10:00.74#ibcon#read 4, iclass 20, count 0 2006.161.08:10:00.74#ibcon#about to read 5, iclass 20, count 0 2006.161.08:10:00.74#ibcon#read 5, iclass 20, count 0 2006.161.08:10:00.74#ibcon#about to read 6, iclass 20, count 0 2006.161.08:10:00.74#ibcon#read 6, iclass 20, count 0 2006.161.08:10:00.74#ibcon#end of sib2, iclass 20, count 0 2006.161.08:10:00.74#ibcon#*after write, iclass 20, count 0 2006.161.08:10:00.74#ibcon#*before return 0, iclass 20, count 0 2006.161.08:10:00.74#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:00.74#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:00.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:10:00.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:10:00.74$vc4f8/valo=5,652.99 2006.161.08:10:00.74#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:10:00.74#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:10:00.74#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:00.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:00.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:00.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:00.74#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:10:00.74#ibcon#first serial, iclass 22, count 0 2006.161.08:10:00.74#ibcon#enter sib2, iclass 22, count 0 2006.161.08:10:00.74#ibcon#flushed, iclass 22, count 0 2006.161.08:10:00.74#ibcon#about to write, iclass 22, count 0 2006.161.08:10:00.74#ibcon#wrote, iclass 22, count 0 2006.161.08:10:00.74#ibcon#about to read 3, iclass 22, count 0 2006.161.08:10:00.76#ibcon#read 3, iclass 22, count 0 2006.161.08:10:00.76#ibcon#about to read 4, iclass 22, count 0 2006.161.08:10:00.76#ibcon#read 4, iclass 22, count 0 2006.161.08:10:00.76#ibcon#about to read 5, iclass 22, count 0 2006.161.08:10:00.76#ibcon#read 5, iclass 22, count 0 2006.161.08:10:00.76#ibcon#about to read 6, iclass 22, count 0 2006.161.08:10:00.76#ibcon#read 6, iclass 22, count 0 2006.161.08:10:00.76#ibcon#end of sib2, iclass 22, count 0 2006.161.08:10:00.76#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:10:00.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:10:00.76#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:10:00.76#ibcon#*before write, iclass 22, count 0 2006.161.08:10:00.76#ibcon#enter sib2, iclass 22, count 0 2006.161.08:10:00.76#ibcon#flushed, iclass 22, count 0 2006.161.08:10:00.76#ibcon#about to write, iclass 22, count 0 2006.161.08:10:00.76#ibcon#wrote, iclass 22, count 0 2006.161.08:10:00.76#ibcon#about to read 3, iclass 22, count 0 2006.161.08:10:00.80#ibcon#read 3, iclass 22, count 0 2006.161.08:10:00.80#ibcon#about to read 4, iclass 22, count 0 2006.161.08:10:00.80#ibcon#read 4, iclass 22, count 0 2006.161.08:10:00.80#ibcon#about to read 5, iclass 22, count 0 2006.161.08:10:00.80#ibcon#read 5, iclass 22, count 0 2006.161.08:10:00.80#ibcon#about to read 6, iclass 22, count 0 2006.161.08:10:00.80#ibcon#read 6, iclass 22, count 0 2006.161.08:10:00.80#ibcon#end of sib2, iclass 22, count 0 2006.161.08:10:00.80#ibcon#*after write, iclass 22, count 0 2006.161.08:10:00.80#ibcon#*before return 0, iclass 22, count 0 2006.161.08:10:00.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:00.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:00.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:10:00.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:10:00.80$vc4f8/va=5,7 2006.161.08:10:00.80#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:10:00.80#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:10:00.80#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:00.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:00.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:00.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:00.86#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:10:00.86#ibcon#first serial, iclass 24, count 2 2006.161.08:10:00.86#ibcon#enter sib2, iclass 24, count 2 2006.161.08:10:00.86#ibcon#flushed, iclass 24, count 2 2006.161.08:10:00.86#ibcon#about to write, iclass 24, count 2 2006.161.08:10:00.86#ibcon#wrote, iclass 24, count 2 2006.161.08:10:00.86#ibcon#about to read 3, iclass 24, count 2 2006.161.08:10:00.88#ibcon#read 3, iclass 24, count 2 2006.161.08:10:00.88#ibcon#about to read 4, iclass 24, count 2 2006.161.08:10:00.88#ibcon#read 4, iclass 24, count 2 2006.161.08:10:00.88#ibcon#about to read 5, iclass 24, count 2 2006.161.08:10:00.88#ibcon#read 5, iclass 24, count 2 2006.161.08:10:00.88#ibcon#about to read 6, iclass 24, count 2 2006.161.08:10:00.88#ibcon#read 6, iclass 24, count 2 2006.161.08:10:00.88#ibcon#end of sib2, iclass 24, count 2 2006.161.08:10:00.88#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:10:00.88#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:10:00.88#ibcon#[25=AT05-07\r\n] 2006.161.08:10:00.88#ibcon#*before write, iclass 24, count 2 2006.161.08:10:00.88#ibcon#enter sib2, iclass 24, count 2 2006.161.08:10:00.88#ibcon#flushed, iclass 24, count 2 2006.161.08:10:00.88#ibcon#about to write, iclass 24, count 2 2006.161.08:10:00.88#ibcon#wrote, iclass 24, count 2 2006.161.08:10:00.88#ibcon#about to read 3, iclass 24, count 2 2006.161.08:10:00.91#ibcon#read 3, iclass 24, count 2 2006.161.08:10:00.91#ibcon#about to read 4, iclass 24, count 2 2006.161.08:10:00.91#ibcon#read 4, iclass 24, count 2 2006.161.08:10:00.91#ibcon#about to read 5, iclass 24, count 2 2006.161.08:10:00.91#ibcon#read 5, iclass 24, count 2 2006.161.08:10:00.91#ibcon#about to read 6, iclass 24, count 2 2006.161.08:10:00.91#ibcon#read 6, iclass 24, count 2 2006.161.08:10:00.91#ibcon#end of sib2, iclass 24, count 2 2006.161.08:10:00.91#ibcon#*after write, iclass 24, count 2 2006.161.08:10:00.91#ibcon#*before return 0, iclass 24, count 2 2006.161.08:10:00.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:00.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:00.91#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:10:00.91#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:00.91#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:01.03#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:01.03#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:01.03#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:10:01.03#ibcon#first serial, iclass 24, count 0 2006.161.08:10:01.03#ibcon#enter sib2, iclass 24, count 0 2006.161.08:10:01.03#ibcon#flushed, iclass 24, count 0 2006.161.08:10:01.03#ibcon#about to write, iclass 24, count 0 2006.161.08:10:01.03#ibcon#wrote, iclass 24, count 0 2006.161.08:10:01.03#ibcon#about to read 3, iclass 24, count 0 2006.161.08:10:01.05#ibcon#read 3, iclass 24, count 0 2006.161.08:10:01.05#ibcon#about to read 4, iclass 24, count 0 2006.161.08:10:01.05#ibcon#read 4, iclass 24, count 0 2006.161.08:10:01.05#ibcon#about to read 5, iclass 24, count 0 2006.161.08:10:01.05#ibcon#read 5, iclass 24, count 0 2006.161.08:10:01.05#ibcon#about to read 6, iclass 24, count 0 2006.161.08:10:01.05#ibcon#read 6, iclass 24, count 0 2006.161.08:10:01.05#ibcon#end of sib2, iclass 24, count 0 2006.161.08:10:01.05#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:10:01.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:10:01.05#ibcon#[25=USB\r\n] 2006.161.08:10:01.05#ibcon#*before write, iclass 24, count 0 2006.161.08:10:01.05#ibcon#enter sib2, iclass 24, count 0 2006.161.08:10:01.05#ibcon#flushed, iclass 24, count 0 2006.161.08:10:01.05#ibcon#about to write, iclass 24, count 0 2006.161.08:10:01.05#ibcon#wrote, iclass 24, count 0 2006.161.08:10:01.05#ibcon#about to read 3, iclass 24, count 0 2006.161.08:10:01.08#ibcon#read 3, iclass 24, count 0 2006.161.08:10:01.08#ibcon#about to read 4, iclass 24, count 0 2006.161.08:10:01.08#ibcon#read 4, iclass 24, count 0 2006.161.08:10:01.08#ibcon#about to read 5, iclass 24, count 0 2006.161.08:10:01.08#ibcon#read 5, iclass 24, count 0 2006.161.08:10:01.08#ibcon#about to read 6, iclass 24, count 0 2006.161.08:10:01.08#ibcon#read 6, iclass 24, count 0 2006.161.08:10:01.08#ibcon#end of sib2, iclass 24, count 0 2006.161.08:10:01.08#ibcon#*after write, iclass 24, count 0 2006.161.08:10:01.08#ibcon#*before return 0, iclass 24, count 0 2006.161.08:10:01.08#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:01.08#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:01.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:10:01.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:10:01.08$vc4f8/valo=6,772.99 2006.161.08:10:01.08#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:10:01.08#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:10:01.08#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:01.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:01.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:01.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:01.08#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:10:01.08#ibcon#first serial, iclass 26, count 0 2006.161.08:10:01.08#ibcon#enter sib2, iclass 26, count 0 2006.161.08:10:01.08#ibcon#flushed, iclass 26, count 0 2006.161.08:10:01.08#ibcon#about to write, iclass 26, count 0 2006.161.08:10:01.08#ibcon#wrote, iclass 26, count 0 2006.161.08:10:01.08#ibcon#about to read 3, iclass 26, count 0 2006.161.08:10:01.10#ibcon#read 3, iclass 26, count 0 2006.161.08:10:01.10#ibcon#about to read 4, iclass 26, count 0 2006.161.08:10:01.10#ibcon#read 4, iclass 26, count 0 2006.161.08:10:01.10#ibcon#about to read 5, iclass 26, count 0 2006.161.08:10:01.10#ibcon#read 5, iclass 26, count 0 2006.161.08:10:01.10#ibcon#about to read 6, iclass 26, count 0 2006.161.08:10:01.10#ibcon#read 6, iclass 26, count 0 2006.161.08:10:01.10#ibcon#end of sib2, iclass 26, count 0 2006.161.08:10:01.10#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:10:01.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:10:01.10#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:10:01.10#ibcon#*before write, iclass 26, count 0 2006.161.08:10:01.10#ibcon#enter sib2, iclass 26, count 0 2006.161.08:10:01.10#ibcon#flushed, iclass 26, count 0 2006.161.08:10:01.10#ibcon#about to write, iclass 26, count 0 2006.161.08:10:01.10#ibcon#wrote, iclass 26, count 0 2006.161.08:10:01.10#ibcon#about to read 3, iclass 26, count 0 2006.161.08:10:01.14#ibcon#read 3, iclass 26, count 0 2006.161.08:10:01.14#ibcon#about to read 4, iclass 26, count 0 2006.161.08:10:01.14#ibcon#read 4, iclass 26, count 0 2006.161.08:10:01.14#ibcon#about to read 5, iclass 26, count 0 2006.161.08:10:01.14#ibcon#read 5, iclass 26, count 0 2006.161.08:10:01.14#ibcon#about to read 6, iclass 26, count 0 2006.161.08:10:01.14#ibcon#read 6, iclass 26, count 0 2006.161.08:10:01.14#ibcon#end of sib2, iclass 26, count 0 2006.161.08:10:01.14#ibcon#*after write, iclass 26, count 0 2006.161.08:10:01.14#ibcon#*before return 0, iclass 26, count 0 2006.161.08:10:01.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:01.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:01.14#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:10:01.14#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:10:01.14$vc4f8/va=6,6 2006.161.08:10:01.14#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:10:01.14#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:10:01.14#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:01.14#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:01.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:01.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:01.20#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:10:01.20#ibcon#first serial, iclass 28, count 2 2006.161.08:10:01.20#ibcon#enter sib2, iclass 28, count 2 2006.161.08:10:01.20#ibcon#flushed, iclass 28, count 2 2006.161.08:10:01.20#ibcon#about to write, iclass 28, count 2 2006.161.08:10:01.20#ibcon#wrote, iclass 28, count 2 2006.161.08:10:01.20#ibcon#about to read 3, iclass 28, count 2 2006.161.08:10:01.22#ibcon#read 3, iclass 28, count 2 2006.161.08:10:01.22#ibcon#about to read 4, iclass 28, count 2 2006.161.08:10:01.22#ibcon#read 4, iclass 28, count 2 2006.161.08:10:01.22#ibcon#about to read 5, iclass 28, count 2 2006.161.08:10:01.22#ibcon#read 5, iclass 28, count 2 2006.161.08:10:01.22#ibcon#about to read 6, iclass 28, count 2 2006.161.08:10:01.22#ibcon#read 6, iclass 28, count 2 2006.161.08:10:01.22#ibcon#end of sib2, iclass 28, count 2 2006.161.08:10:01.22#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:10:01.22#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:10:01.22#ibcon#[25=AT06-06\r\n] 2006.161.08:10:01.22#ibcon#*before write, iclass 28, count 2 2006.161.08:10:01.22#ibcon#enter sib2, iclass 28, count 2 2006.161.08:10:01.22#ibcon#flushed, iclass 28, count 2 2006.161.08:10:01.22#ibcon#about to write, iclass 28, count 2 2006.161.08:10:01.22#ibcon#wrote, iclass 28, count 2 2006.161.08:10:01.22#ibcon#about to read 3, iclass 28, count 2 2006.161.08:10:01.25#ibcon#read 3, iclass 28, count 2 2006.161.08:10:01.25#ibcon#about to read 4, iclass 28, count 2 2006.161.08:10:01.25#ibcon#read 4, iclass 28, count 2 2006.161.08:10:01.25#ibcon#about to read 5, iclass 28, count 2 2006.161.08:10:01.25#ibcon#read 5, iclass 28, count 2 2006.161.08:10:01.25#ibcon#about to read 6, iclass 28, count 2 2006.161.08:10:01.25#ibcon#read 6, iclass 28, count 2 2006.161.08:10:01.25#ibcon#end of sib2, iclass 28, count 2 2006.161.08:10:01.25#ibcon#*after write, iclass 28, count 2 2006.161.08:10:01.25#ibcon#*before return 0, iclass 28, count 2 2006.161.08:10:01.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:01.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:01.25#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:10:01.25#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:01.25#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:10:01.37#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:10:01.37#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:10:01.37#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:10:01.37#ibcon#first serial, iclass 28, count 0 2006.161.08:10:01.37#ibcon#enter sib2, iclass 28, count 0 2006.161.08:10:01.37#ibcon#flushed, iclass 28, count 0 2006.161.08:10:01.37#ibcon#about to write, iclass 28, count 0 2006.161.08:10:01.37#ibcon#wrote, iclass 28, count 0 2006.161.08:10:01.37#ibcon#about to read 3, iclass 28, count 0 2006.161.08:10:01.39#ibcon#read 3, iclass 28, count 0 2006.161.08:10:01.39#ibcon#about to read 4, iclass 28, count 0 2006.161.08:10:01.39#ibcon#read 4, iclass 28, count 0 2006.161.08:10:01.39#ibcon#about to read 5, iclass 28, count 0 2006.161.08:10:01.39#ibcon#read 5, iclass 28, count 0 2006.161.08:10:01.39#ibcon#about to read 6, iclass 28, count 0 2006.161.08:10:01.39#ibcon#read 6, iclass 28, count 0 2006.161.08:10:01.39#ibcon#end of sib2, iclass 28, count 0 2006.161.08:10:01.39#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:10:01.39#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:10:01.39#ibcon#[25=USB\r\n] 2006.161.08:10:01.39#ibcon#*before write, iclass 28, count 0 2006.161.08:10:01.39#ibcon#enter sib2, iclass 28, count 0 2006.161.08:10:01.39#ibcon#flushed, iclass 28, count 0 2006.161.08:10:01.39#ibcon#about to write, iclass 28, count 0 2006.161.08:10:01.39#ibcon#wrote, iclass 28, count 0 2006.161.08:10:01.39#ibcon#about to read 3, iclass 28, count 0 2006.161.08:10:01.42#ibcon#read 3, iclass 28, count 0 2006.161.08:10:01.42#ibcon#about to read 4, iclass 28, count 0 2006.161.08:10:01.42#ibcon#read 4, iclass 28, count 0 2006.161.08:10:01.42#ibcon#about to read 5, iclass 28, count 0 2006.161.08:10:01.42#ibcon#read 5, iclass 28, count 0 2006.161.08:10:01.42#ibcon#about to read 6, iclass 28, count 0 2006.161.08:10:01.42#ibcon#read 6, iclass 28, count 0 2006.161.08:10:01.42#ibcon#end of sib2, iclass 28, count 0 2006.161.08:10:01.42#ibcon#*after write, iclass 28, count 0 2006.161.08:10:01.42#ibcon#*before return 0, iclass 28, count 0 2006.161.08:10:01.42#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:10:01.42#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:10:01.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:10:01.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:10:01.42$vc4f8/valo=7,832.99 2006.161.08:10:01.42#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:10:01.42#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:10:01.42#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:01.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:10:01.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:10:01.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:10:01.42#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:10:01.42#ibcon#first serial, iclass 30, count 0 2006.161.08:10:01.42#ibcon#enter sib2, iclass 30, count 0 2006.161.08:10:01.42#ibcon#flushed, iclass 30, count 0 2006.161.08:10:01.42#ibcon#about to write, iclass 30, count 0 2006.161.08:10:01.42#ibcon#wrote, iclass 30, count 0 2006.161.08:10:01.42#ibcon#about to read 3, iclass 30, count 0 2006.161.08:10:01.44#ibcon#read 3, iclass 30, count 0 2006.161.08:10:01.44#ibcon#about to read 4, iclass 30, count 0 2006.161.08:10:01.44#ibcon#read 4, iclass 30, count 0 2006.161.08:10:01.44#ibcon#about to read 5, iclass 30, count 0 2006.161.08:10:01.44#ibcon#read 5, iclass 30, count 0 2006.161.08:10:01.44#ibcon#about to read 6, iclass 30, count 0 2006.161.08:10:01.44#ibcon#read 6, iclass 30, count 0 2006.161.08:10:01.44#ibcon#end of sib2, iclass 30, count 0 2006.161.08:10:01.44#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:10:01.44#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:10:01.44#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:10:01.44#ibcon#*before write, iclass 30, count 0 2006.161.08:10:01.44#ibcon#enter sib2, iclass 30, count 0 2006.161.08:10:01.44#ibcon#flushed, iclass 30, count 0 2006.161.08:10:01.44#ibcon#about to write, iclass 30, count 0 2006.161.08:10:01.44#ibcon#wrote, iclass 30, count 0 2006.161.08:10:01.44#ibcon#about to read 3, iclass 30, count 0 2006.161.08:10:01.48#ibcon#read 3, iclass 30, count 0 2006.161.08:10:01.48#ibcon#about to read 4, iclass 30, count 0 2006.161.08:10:01.48#ibcon#read 4, iclass 30, count 0 2006.161.08:10:01.48#ibcon#about to read 5, iclass 30, count 0 2006.161.08:10:01.48#ibcon#read 5, iclass 30, count 0 2006.161.08:10:01.48#ibcon#about to read 6, iclass 30, count 0 2006.161.08:10:01.48#ibcon#read 6, iclass 30, count 0 2006.161.08:10:01.48#ibcon#end of sib2, iclass 30, count 0 2006.161.08:10:01.48#ibcon#*after write, iclass 30, count 0 2006.161.08:10:01.48#ibcon#*before return 0, iclass 30, count 0 2006.161.08:10:01.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:10:01.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:10:01.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:10:01.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:10:01.48$vc4f8/va=7,6 2006.161.08:10:01.48#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:10:01.48#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:10:01.48#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:01.48#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:10:01.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:10:01.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:10:01.54#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:10:01.54#ibcon#first serial, iclass 32, count 2 2006.161.08:10:01.54#ibcon#enter sib2, iclass 32, count 2 2006.161.08:10:01.54#ibcon#flushed, iclass 32, count 2 2006.161.08:10:01.54#ibcon#about to write, iclass 32, count 2 2006.161.08:10:01.54#ibcon#wrote, iclass 32, count 2 2006.161.08:10:01.54#ibcon#about to read 3, iclass 32, count 2 2006.161.08:10:01.56#ibcon#read 3, iclass 32, count 2 2006.161.08:10:01.56#ibcon#about to read 4, iclass 32, count 2 2006.161.08:10:01.56#ibcon#read 4, iclass 32, count 2 2006.161.08:10:01.56#ibcon#about to read 5, iclass 32, count 2 2006.161.08:10:01.56#ibcon#read 5, iclass 32, count 2 2006.161.08:10:01.56#ibcon#about to read 6, iclass 32, count 2 2006.161.08:10:01.56#ibcon#read 6, iclass 32, count 2 2006.161.08:10:01.56#ibcon#end of sib2, iclass 32, count 2 2006.161.08:10:01.56#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:10:01.56#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:10:01.56#ibcon#[25=AT07-06\r\n] 2006.161.08:10:01.56#ibcon#*before write, iclass 32, count 2 2006.161.08:10:01.56#ibcon#enter sib2, iclass 32, count 2 2006.161.08:10:01.56#ibcon#flushed, iclass 32, count 2 2006.161.08:10:01.56#ibcon#about to write, iclass 32, count 2 2006.161.08:10:01.56#ibcon#wrote, iclass 32, count 2 2006.161.08:10:01.56#ibcon#about to read 3, iclass 32, count 2 2006.161.08:10:01.59#ibcon#read 3, iclass 32, count 2 2006.161.08:10:01.59#ibcon#about to read 4, iclass 32, count 2 2006.161.08:10:01.59#ibcon#read 4, iclass 32, count 2 2006.161.08:10:01.59#ibcon#about to read 5, iclass 32, count 2 2006.161.08:10:01.59#ibcon#read 5, iclass 32, count 2 2006.161.08:10:01.59#ibcon#about to read 6, iclass 32, count 2 2006.161.08:10:01.59#ibcon#read 6, iclass 32, count 2 2006.161.08:10:01.59#ibcon#end of sib2, iclass 32, count 2 2006.161.08:10:01.59#ibcon#*after write, iclass 32, count 2 2006.161.08:10:01.59#ibcon#*before return 0, iclass 32, count 2 2006.161.08:10:01.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:10:01.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:10:01.59#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:10:01.59#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:01.59#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:10:01.71#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:10:01.71#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:10:01.71#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:10:01.71#ibcon#first serial, iclass 32, count 0 2006.161.08:10:01.71#ibcon#enter sib2, iclass 32, count 0 2006.161.08:10:01.71#ibcon#flushed, iclass 32, count 0 2006.161.08:10:01.71#ibcon#about to write, iclass 32, count 0 2006.161.08:10:01.71#ibcon#wrote, iclass 32, count 0 2006.161.08:10:01.71#ibcon#about to read 3, iclass 32, count 0 2006.161.08:10:01.73#ibcon#read 3, iclass 32, count 0 2006.161.08:10:01.73#ibcon#about to read 4, iclass 32, count 0 2006.161.08:10:01.73#ibcon#read 4, iclass 32, count 0 2006.161.08:10:01.73#ibcon#about to read 5, iclass 32, count 0 2006.161.08:10:01.73#ibcon#read 5, iclass 32, count 0 2006.161.08:10:01.73#ibcon#about to read 6, iclass 32, count 0 2006.161.08:10:01.73#ibcon#read 6, iclass 32, count 0 2006.161.08:10:01.73#ibcon#end of sib2, iclass 32, count 0 2006.161.08:10:01.73#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:10:01.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:10:01.73#ibcon#[25=USB\r\n] 2006.161.08:10:01.73#ibcon#*before write, iclass 32, count 0 2006.161.08:10:01.73#ibcon#enter sib2, iclass 32, count 0 2006.161.08:10:01.73#ibcon#flushed, iclass 32, count 0 2006.161.08:10:01.73#ibcon#about to write, iclass 32, count 0 2006.161.08:10:01.73#ibcon#wrote, iclass 32, count 0 2006.161.08:10:01.73#ibcon#about to read 3, iclass 32, count 0 2006.161.08:10:01.76#ibcon#read 3, iclass 32, count 0 2006.161.08:10:01.76#ibcon#about to read 4, iclass 32, count 0 2006.161.08:10:01.76#ibcon#read 4, iclass 32, count 0 2006.161.08:10:01.76#ibcon#about to read 5, iclass 32, count 0 2006.161.08:10:01.76#ibcon#read 5, iclass 32, count 0 2006.161.08:10:01.76#ibcon#about to read 6, iclass 32, count 0 2006.161.08:10:01.76#ibcon#read 6, iclass 32, count 0 2006.161.08:10:01.76#ibcon#end of sib2, iclass 32, count 0 2006.161.08:10:01.76#ibcon#*after write, iclass 32, count 0 2006.161.08:10:01.76#ibcon#*before return 0, iclass 32, count 0 2006.161.08:10:01.76#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:10:01.76#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:10:01.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:10:01.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:10:01.76$vc4f8/valo=8,852.99 2006.161.08:10:01.76#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:10:01.76#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:10:01.76#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:01.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:10:01.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:10:01.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:10:01.76#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:10:01.76#ibcon#first serial, iclass 34, count 0 2006.161.08:10:01.76#ibcon#enter sib2, iclass 34, count 0 2006.161.08:10:01.76#ibcon#flushed, iclass 34, count 0 2006.161.08:10:01.76#ibcon#about to write, iclass 34, count 0 2006.161.08:10:01.76#ibcon#wrote, iclass 34, count 0 2006.161.08:10:01.76#ibcon#about to read 3, iclass 34, count 0 2006.161.08:10:01.78#ibcon#read 3, iclass 34, count 0 2006.161.08:10:01.78#ibcon#about to read 4, iclass 34, count 0 2006.161.08:10:01.78#ibcon#read 4, iclass 34, count 0 2006.161.08:10:01.78#ibcon#about to read 5, iclass 34, count 0 2006.161.08:10:01.78#ibcon#read 5, iclass 34, count 0 2006.161.08:10:01.78#ibcon#about to read 6, iclass 34, count 0 2006.161.08:10:01.78#ibcon#read 6, iclass 34, count 0 2006.161.08:10:01.78#ibcon#end of sib2, iclass 34, count 0 2006.161.08:10:01.78#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:10:01.78#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:10:01.78#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:10:01.78#ibcon#*before write, iclass 34, count 0 2006.161.08:10:01.78#ibcon#enter sib2, iclass 34, count 0 2006.161.08:10:01.78#ibcon#flushed, iclass 34, count 0 2006.161.08:10:01.78#ibcon#about to write, iclass 34, count 0 2006.161.08:10:01.78#ibcon#wrote, iclass 34, count 0 2006.161.08:10:01.78#ibcon#about to read 3, iclass 34, count 0 2006.161.08:10:01.82#ibcon#read 3, iclass 34, count 0 2006.161.08:10:01.82#ibcon#about to read 4, iclass 34, count 0 2006.161.08:10:01.82#ibcon#read 4, iclass 34, count 0 2006.161.08:10:01.82#ibcon#about to read 5, iclass 34, count 0 2006.161.08:10:01.82#ibcon#read 5, iclass 34, count 0 2006.161.08:10:01.82#ibcon#about to read 6, iclass 34, count 0 2006.161.08:10:01.82#ibcon#read 6, iclass 34, count 0 2006.161.08:10:01.82#ibcon#end of sib2, iclass 34, count 0 2006.161.08:10:01.82#ibcon#*after write, iclass 34, count 0 2006.161.08:10:01.82#ibcon#*before return 0, iclass 34, count 0 2006.161.08:10:01.82#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:10:01.82#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:10:01.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:10:01.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:10:01.82$vc4f8/va=8,7 2006.161.08:10:01.82#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:10:01.82#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:10:01.82#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:01.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:10:01.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:10:01.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:10:01.88#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:10:01.88#ibcon#first serial, iclass 36, count 2 2006.161.08:10:01.88#ibcon#enter sib2, iclass 36, count 2 2006.161.08:10:01.88#ibcon#flushed, iclass 36, count 2 2006.161.08:10:01.88#ibcon#about to write, iclass 36, count 2 2006.161.08:10:01.88#ibcon#wrote, iclass 36, count 2 2006.161.08:10:01.88#ibcon#about to read 3, iclass 36, count 2 2006.161.08:10:01.90#ibcon#read 3, iclass 36, count 2 2006.161.08:10:01.90#ibcon#about to read 4, iclass 36, count 2 2006.161.08:10:01.90#ibcon#read 4, iclass 36, count 2 2006.161.08:10:01.90#ibcon#about to read 5, iclass 36, count 2 2006.161.08:10:01.90#ibcon#read 5, iclass 36, count 2 2006.161.08:10:01.90#ibcon#about to read 6, iclass 36, count 2 2006.161.08:10:01.90#ibcon#read 6, iclass 36, count 2 2006.161.08:10:01.90#ibcon#end of sib2, iclass 36, count 2 2006.161.08:10:01.90#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:10:01.90#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:10:01.90#ibcon#[25=AT08-07\r\n] 2006.161.08:10:01.90#ibcon#*before write, iclass 36, count 2 2006.161.08:10:01.90#ibcon#enter sib2, iclass 36, count 2 2006.161.08:10:01.90#ibcon#flushed, iclass 36, count 2 2006.161.08:10:01.90#ibcon#about to write, iclass 36, count 2 2006.161.08:10:01.90#ibcon#wrote, iclass 36, count 2 2006.161.08:10:01.90#ibcon#about to read 3, iclass 36, count 2 2006.161.08:10:01.93#ibcon#read 3, iclass 36, count 2 2006.161.08:10:01.93#ibcon#about to read 4, iclass 36, count 2 2006.161.08:10:01.93#ibcon#read 4, iclass 36, count 2 2006.161.08:10:01.93#ibcon#about to read 5, iclass 36, count 2 2006.161.08:10:01.93#ibcon#read 5, iclass 36, count 2 2006.161.08:10:01.93#ibcon#about to read 6, iclass 36, count 2 2006.161.08:10:01.93#ibcon#read 6, iclass 36, count 2 2006.161.08:10:01.93#ibcon#end of sib2, iclass 36, count 2 2006.161.08:10:01.93#ibcon#*after write, iclass 36, count 2 2006.161.08:10:01.93#ibcon#*before return 0, iclass 36, count 2 2006.161.08:10:01.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:10:01.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:10:01.93#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:10:01.93#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:01.93#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:10:02.05#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:10:02.05#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:10:02.05#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:10:02.05#ibcon#first serial, iclass 36, count 0 2006.161.08:10:02.05#ibcon#enter sib2, iclass 36, count 0 2006.161.08:10:02.05#ibcon#flushed, iclass 36, count 0 2006.161.08:10:02.05#ibcon#about to write, iclass 36, count 0 2006.161.08:10:02.05#ibcon#wrote, iclass 36, count 0 2006.161.08:10:02.05#ibcon#about to read 3, iclass 36, count 0 2006.161.08:10:02.07#ibcon#read 3, iclass 36, count 0 2006.161.08:10:02.07#ibcon#about to read 4, iclass 36, count 0 2006.161.08:10:02.07#ibcon#read 4, iclass 36, count 0 2006.161.08:10:02.07#ibcon#about to read 5, iclass 36, count 0 2006.161.08:10:02.07#ibcon#read 5, iclass 36, count 0 2006.161.08:10:02.07#ibcon#about to read 6, iclass 36, count 0 2006.161.08:10:02.07#ibcon#read 6, iclass 36, count 0 2006.161.08:10:02.07#ibcon#end of sib2, iclass 36, count 0 2006.161.08:10:02.07#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:10:02.07#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:10:02.07#ibcon#[25=USB\r\n] 2006.161.08:10:02.07#ibcon#*before write, iclass 36, count 0 2006.161.08:10:02.07#ibcon#enter sib2, iclass 36, count 0 2006.161.08:10:02.07#ibcon#flushed, iclass 36, count 0 2006.161.08:10:02.07#ibcon#about to write, iclass 36, count 0 2006.161.08:10:02.07#ibcon#wrote, iclass 36, count 0 2006.161.08:10:02.07#ibcon#about to read 3, iclass 36, count 0 2006.161.08:10:02.10#ibcon#read 3, iclass 36, count 0 2006.161.08:10:02.10#ibcon#about to read 4, iclass 36, count 0 2006.161.08:10:02.10#ibcon#read 4, iclass 36, count 0 2006.161.08:10:02.10#ibcon#about to read 5, iclass 36, count 0 2006.161.08:10:02.10#ibcon#read 5, iclass 36, count 0 2006.161.08:10:02.10#ibcon#about to read 6, iclass 36, count 0 2006.161.08:10:02.10#ibcon#read 6, iclass 36, count 0 2006.161.08:10:02.10#ibcon#end of sib2, iclass 36, count 0 2006.161.08:10:02.10#ibcon#*after write, iclass 36, count 0 2006.161.08:10:02.10#ibcon#*before return 0, iclass 36, count 0 2006.161.08:10:02.10#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:10:02.10#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:10:02.10#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:10:02.10#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:10:02.10$vc4f8/vblo=1,632.99 2006.161.08:10:02.10#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:10:02.10#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:10:02.10#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:02.10#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:10:02.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:10:02.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:10:02.10#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:10:02.10#ibcon#first serial, iclass 38, count 0 2006.161.08:10:02.10#ibcon#enter sib2, iclass 38, count 0 2006.161.08:10:02.10#ibcon#flushed, iclass 38, count 0 2006.161.08:10:02.10#ibcon#about to write, iclass 38, count 0 2006.161.08:10:02.10#ibcon#wrote, iclass 38, count 0 2006.161.08:10:02.10#ibcon#about to read 3, iclass 38, count 0 2006.161.08:10:02.12#ibcon#read 3, iclass 38, count 0 2006.161.08:10:02.12#ibcon#about to read 4, iclass 38, count 0 2006.161.08:10:02.12#ibcon#read 4, iclass 38, count 0 2006.161.08:10:02.12#ibcon#about to read 5, iclass 38, count 0 2006.161.08:10:02.12#ibcon#read 5, iclass 38, count 0 2006.161.08:10:02.12#ibcon#about to read 6, iclass 38, count 0 2006.161.08:10:02.12#ibcon#read 6, iclass 38, count 0 2006.161.08:10:02.12#ibcon#end of sib2, iclass 38, count 0 2006.161.08:10:02.12#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:10:02.12#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:10:02.12#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:10:02.12#ibcon#*before write, iclass 38, count 0 2006.161.08:10:02.12#ibcon#enter sib2, iclass 38, count 0 2006.161.08:10:02.12#ibcon#flushed, iclass 38, count 0 2006.161.08:10:02.12#ibcon#about to write, iclass 38, count 0 2006.161.08:10:02.12#ibcon#wrote, iclass 38, count 0 2006.161.08:10:02.12#ibcon#about to read 3, iclass 38, count 0 2006.161.08:10:02.16#ibcon#read 3, iclass 38, count 0 2006.161.08:10:02.16#ibcon#about to read 4, iclass 38, count 0 2006.161.08:10:02.16#ibcon#read 4, iclass 38, count 0 2006.161.08:10:02.16#ibcon#about to read 5, iclass 38, count 0 2006.161.08:10:02.16#ibcon#read 5, iclass 38, count 0 2006.161.08:10:02.16#ibcon#about to read 6, iclass 38, count 0 2006.161.08:10:02.16#ibcon#read 6, iclass 38, count 0 2006.161.08:10:02.16#ibcon#end of sib2, iclass 38, count 0 2006.161.08:10:02.16#ibcon#*after write, iclass 38, count 0 2006.161.08:10:02.16#ibcon#*before return 0, iclass 38, count 0 2006.161.08:10:02.16#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:10:02.16#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:10:02.16#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:10:02.16#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:10:02.16$vc4f8/vb=1,4 2006.161.08:10:02.16#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:10:02.16#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:10:02.16#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:02.16#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:10:02.16#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:10:02.16#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:10:02.16#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:10:02.16#ibcon#first serial, iclass 40, count 2 2006.161.08:10:02.16#ibcon#enter sib2, iclass 40, count 2 2006.161.08:10:02.16#ibcon#flushed, iclass 40, count 2 2006.161.08:10:02.16#ibcon#about to write, iclass 40, count 2 2006.161.08:10:02.16#ibcon#wrote, iclass 40, count 2 2006.161.08:10:02.16#ibcon#about to read 3, iclass 40, count 2 2006.161.08:10:02.18#ibcon#read 3, iclass 40, count 2 2006.161.08:10:02.18#ibcon#about to read 4, iclass 40, count 2 2006.161.08:10:02.18#ibcon#read 4, iclass 40, count 2 2006.161.08:10:02.18#ibcon#about to read 5, iclass 40, count 2 2006.161.08:10:02.18#ibcon#read 5, iclass 40, count 2 2006.161.08:10:02.18#ibcon#about to read 6, iclass 40, count 2 2006.161.08:10:02.18#ibcon#read 6, iclass 40, count 2 2006.161.08:10:02.18#ibcon#end of sib2, iclass 40, count 2 2006.161.08:10:02.18#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:10:02.18#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:10:02.18#ibcon#[27=AT01-04\r\n] 2006.161.08:10:02.18#ibcon#*before write, iclass 40, count 2 2006.161.08:10:02.18#ibcon#enter sib2, iclass 40, count 2 2006.161.08:10:02.18#ibcon#flushed, iclass 40, count 2 2006.161.08:10:02.18#ibcon#about to write, iclass 40, count 2 2006.161.08:10:02.18#ibcon#wrote, iclass 40, count 2 2006.161.08:10:02.18#ibcon#about to read 3, iclass 40, count 2 2006.161.08:10:02.21#ibcon#read 3, iclass 40, count 2 2006.161.08:10:02.21#ibcon#about to read 4, iclass 40, count 2 2006.161.08:10:02.21#ibcon#read 4, iclass 40, count 2 2006.161.08:10:02.21#ibcon#about to read 5, iclass 40, count 2 2006.161.08:10:02.21#ibcon#read 5, iclass 40, count 2 2006.161.08:10:02.21#ibcon#about to read 6, iclass 40, count 2 2006.161.08:10:02.21#ibcon#read 6, iclass 40, count 2 2006.161.08:10:02.21#ibcon#end of sib2, iclass 40, count 2 2006.161.08:10:02.21#ibcon#*after write, iclass 40, count 2 2006.161.08:10:02.21#ibcon#*before return 0, iclass 40, count 2 2006.161.08:10:02.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:10:02.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:10:02.21#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:10:02.21#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:02.21#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:10:02.33#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:10:02.33#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:10:02.33#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:10:02.33#ibcon#first serial, iclass 40, count 0 2006.161.08:10:02.33#ibcon#enter sib2, iclass 40, count 0 2006.161.08:10:02.33#ibcon#flushed, iclass 40, count 0 2006.161.08:10:02.33#ibcon#about to write, iclass 40, count 0 2006.161.08:10:02.33#ibcon#wrote, iclass 40, count 0 2006.161.08:10:02.33#ibcon#about to read 3, iclass 40, count 0 2006.161.08:10:02.35#ibcon#read 3, iclass 40, count 0 2006.161.08:10:02.35#ibcon#about to read 4, iclass 40, count 0 2006.161.08:10:02.35#ibcon#read 4, iclass 40, count 0 2006.161.08:10:02.35#ibcon#about to read 5, iclass 40, count 0 2006.161.08:10:02.35#ibcon#read 5, iclass 40, count 0 2006.161.08:10:02.35#ibcon#about to read 6, iclass 40, count 0 2006.161.08:10:02.35#ibcon#read 6, iclass 40, count 0 2006.161.08:10:02.35#ibcon#end of sib2, iclass 40, count 0 2006.161.08:10:02.35#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:10:02.35#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:10:02.35#ibcon#[27=USB\r\n] 2006.161.08:10:02.35#ibcon#*before write, iclass 40, count 0 2006.161.08:10:02.35#ibcon#enter sib2, iclass 40, count 0 2006.161.08:10:02.35#ibcon#flushed, iclass 40, count 0 2006.161.08:10:02.35#ibcon#about to write, iclass 40, count 0 2006.161.08:10:02.35#ibcon#wrote, iclass 40, count 0 2006.161.08:10:02.35#ibcon#about to read 3, iclass 40, count 0 2006.161.08:10:02.38#ibcon#read 3, iclass 40, count 0 2006.161.08:10:02.38#ibcon#about to read 4, iclass 40, count 0 2006.161.08:10:02.38#ibcon#read 4, iclass 40, count 0 2006.161.08:10:02.38#ibcon#about to read 5, iclass 40, count 0 2006.161.08:10:02.38#ibcon#read 5, iclass 40, count 0 2006.161.08:10:02.38#ibcon#about to read 6, iclass 40, count 0 2006.161.08:10:02.38#ibcon#read 6, iclass 40, count 0 2006.161.08:10:02.38#ibcon#end of sib2, iclass 40, count 0 2006.161.08:10:02.38#ibcon#*after write, iclass 40, count 0 2006.161.08:10:02.38#ibcon#*before return 0, iclass 40, count 0 2006.161.08:10:02.38#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:10:02.38#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:10:02.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:10:02.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:10:02.38$vc4f8/vblo=2,640.99 2006.161.08:10:02.38#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:10:02.38#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:10:02.38#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:02.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:10:02.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:10:02.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:10:02.38#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:10:02.38#ibcon#first serial, iclass 4, count 0 2006.161.08:10:02.38#ibcon#enter sib2, iclass 4, count 0 2006.161.08:10:02.38#ibcon#flushed, iclass 4, count 0 2006.161.08:10:02.38#ibcon#about to write, iclass 4, count 0 2006.161.08:10:02.38#ibcon#wrote, iclass 4, count 0 2006.161.08:10:02.38#ibcon#about to read 3, iclass 4, count 0 2006.161.08:10:02.40#ibcon#read 3, iclass 4, count 0 2006.161.08:10:02.40#ibcon#about to read 4, iclass 4, count 0 2006.161.08:10:02.40#ibcon#read 4, iclass 4, count 0 2006.161.08:10:02.40#ibcon#about to read 5, iclass 4, count 0 2006.161.08:10:02.40#ibcon#read 5, iclass 4, count 0 2006.161.08:10:02.40#ibcon#about to read 6, iclass 4, count 0 2006.161.08:10:02.40#ibcon#read 6, iclass 4, count 0 2006.161.08:10:02.40#ibcon#end of sib2, iclass 4, count 0 2006.161.08:10:02.40#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:10:02.40#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:10:02.40#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:10:02.40#ibcon#*before write, iclass 4, count 0 2006.161.08:10:02.40#ibcon#enter sib2, iclass 4, count 0 2006.161.08:10:02.40#ibcon#flushed, iclass 4, count 0 2006.161.08:10:02.40#ibcon#about to write, iclass 4, count 0 2006.161.08:10:02.40#ibcon#wrote, iclass 4, count 0 2006.161.08:10:02.40#ibcon#about to read 3, iclass 4, count 0 2006.161.08:10:02.44#ibcon#read 3, iclass 4, count 0 2006.161.08:10:02.44#ibcon#about to read 4, iclass 4, count 0 2006.161.08:10:02.44#ibcon#read 4, iclass 4, count 0 2006.161.08:10:02.44#ibcon#about to read 5, iclass 4, count 0 2006.161.08:10:02.44#ibcon#read 5, iclass 4, count 0 2006.161.08:10:02.44#ibcon#about to read 6, iclass 4, count 0 2006.161.08:10:02.44#ibcon#read 6, iclass 4, count 0 2006.161.08:10:02.44#ibcon#end of sib2, iclass 4, count 0 2006.161.08:10:02.44#ibcon#*after write, iclass 4, count 0 2006.161.08:10:02.44#ibcon#*before return 0, iclass 4, count 0 2006.161.08:10:02.44#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:10:02.44#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:10:02.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:10:02.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:10:02.44$vc4f8/vb=2,4 2006.161.08:10:02.44#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:10:02.44#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:10:02.44#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:02.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:10:02.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:10:02.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:10:02.50#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:10:02.50#ibcon#first serial, iclass 6, count 2 2006.161.08:10:02.50#ibcon#enter sib2, iclass 6, count 2 2006.161.08:10:02.50#ibcon#flushed, iclass 6, count 2 2006.161.08:10:02.50#ibcon#about to write, iclass 6, count 2 2006.161.08:10:02.50#ibcon#wrote, iclass 6, count 2 2006.161.08:10:02.50#ibcon#about to read 3, iclass 6, count 2 2006.161.08:10:02.52#ibcon#read 3, iclass 6, count 2 2006.161.08:10:02.52#ibcon#about to read 4, iclass 6, count 2 2006.161.08:10:02.52#ibcon#read 4, iclass 6, count 2 2006.161.08:10:02.52#ibcon#about to read 5, iclass 6, count 2 2006.161.08:10:02.52#ibcon#read 5, iclass 6, count 2 2006.161.08:10:02.52#ibcon#about to read 6, iclass 6, count 2 2006.161.08:10:02.52#ibcon#read 6, iclass 6, count 2 2006.161.08:10:02.52#ibcon#end of sib2, iclass 6, count 2 2006.161.08:10:02.52#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:10:02.52#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:10:02.52#ibcon#[27=AT02-04\r\n] 2006.161.08:10:02.52#ibcon#*before write, iclass 6, count 2 2006.161.08:10:02.52#ibcon#enter sib2, iclass 6, count 2 2006.161.08:10:02.52#ibcon#flushed, iclass 6, count 2 2006.161.08:10:02.52#ibcon#about to write, iclass 6, count 2 2006.161.08:10:02.52#ibcon#wrote, iclass 6, count 2 2006.161.08:10:02.52#ibcon#about to read 3, iclass 6, count 2 2006.161.08:10:02.55#ibcon#read 3, iclass 6, count 2 2006.161.08:10:02.55#ibcon#about to read 4, iclass 6, count 2 2006.161.08:10:02.55#ibcon#read 4, iclass 6, count 2 2006.161.08:10:02.55#ibcon#about to read 5, iclass 6, count 2 2006.161.08:10:02.55#ibcon#read 5, iclass 6, count 2 2006.161.08:10:02.55#ibcon#about to read 6, iclass 6, count 2 2006.161.08:10:02.55#ibcon#read 6, iclass 6, count 2 2006.161.08:10:02.55#ibcon#end of sib2, iclass 6, count 2 2006.161.08:10:02.55#ibcon#*after write, iclass 6, count 2 2006.161.08:10:02.55#ibcon#*before return 0, iclass 6, count 2 2006.161.08:10:02.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:10:02.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:10:02.55#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:10:02.55#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:02.55#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:10:02.67#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:10:02.67#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:10:02.67#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:10:02.67#ibcon#first serial, iclass 6, count 0 2006.161.08:10:02.67#ibcon#enter sib2, iclass 6, count 0 2006.161.08:10:02.67#ibcon#flushed, iclass 6, count 0 2006.161.08:10:02.67#ibcon#about to write, iclass 6, count 0 2006.161.08:10:02.67#ibcon#wrote, iclass 6, count 0 2006.161.08:10:02.67#ibcon#about to read 3, iclass 6, count 0 2006.161.08:10:02.69#ibcon#read 3, iclass 6, count 0 2006.161.08:10:02.69#ibcon#about to read 4, iclass 6, count 0 2006.161.08:10:02.69#ibcon#read 4, iclass 6, count 0 2006.161.08:10:02.69#ibcon#about to read 5, iclass 6, count 0 2006.161.08:10:02.69#ibcon#read 5, iclass 6, count 0 2006.161.08:10:02.69#ibcon#about to read 6, iclass 6, count 0 2006.161.08:10:02.69#ibcon#read 6, iclass 6, count 0 2006.161.08:10:02.69#ibcon#end of sib2, iclass 6, count 0 2006.161.08:10:02.69#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:10:02.69#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:10:02.69#ibcon#[27=USB\r\n] 2006.161.08:10:02.69#ibcon#*before write, iclass 6, count 0 2006.161.08:10:02.69#ibcon#enter sib2, iclass 6, count 0 2006.161.08:10:02.69#ibcon#flushed, iclass 6, count 0 2006.161.08:10:02.69#ibcon#about to write, iclass 6, count 0 2006.161.08:10:02.69#ibcon#wrote, iclass 6, count 0 2006.161.08:10:02.69#ibcon#about to read 3, iclass 6, count 0 2006.161.08:10:02.72#ibcon#read 3, iclass 6, count 0 2006.161.08:10:02.72#ibcon#about to read 4, iclass 6, count 0 2006.161.08:10:02.72#ibcon#read 4, iclass 6, count 0 2006.161.08:10:02.72#ibcon#about to read 5, iclass 6, count 0 2006.161.08:10:02.72#ibcon#read 5, iclass 6, count 0 2006.161.08:10:02.72#ibcon#about to read 6, iclass 6, count 0 2006.161.08:10:02.72#ibcon#read 6, iclass 6, count 0 2006.161.08:10:02.72#ibcon#end of sib2, iclass 6, count 0 2006.161.08:10:02.72#ibcon#*after write, iclass 6, count 0 2006.161.08:10:02.72#ibcon#*before return 0, iclass 6, count 0 2006.161.08:10:02.72#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:10:02.72#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:10:02.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:10:02.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:10:02.72$vc4f8/vblo=3,656.99 2006.161.08:10:02.72#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:10:02.72#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:10:02.72#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:02.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:10:02.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:10:02.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:10:02.72#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:10:02.72#ibcon#first serial, iclass 10, count 0 2006.161.08:10:02.72#ibcon#enter sib2, iclass 10, count 0 2006.161.08:10:02.72#ibcon#flushed, iclass 10, count 0 2006.161.08:10:02.72#ibcon#about to write, iclass 10, count 0 2006.161.08:10:02.72#ibcon#wrote, iclass 10, count 0 2006.161.08:10:02.72#ibcon#about to read 3, iclass 10, count 0 2006.161.08:10:02.74#ibcon#read 3, iclass 10, count 0 2006.161.08:10:02.74#ibcon#about to read 4, iclass 10, count 0 2006.161.08:10:02.74#ibcon#read 4, iclass 10, count 0 2006.161.08:10:02.74#ibcon#about to read 5, iclass 10, count 0 2006.161.08:10:02.74#ibcon#read 5, iclass 10, count 0 2006.161.08:10:02.74#ibcon#about to read 6, iclass 10, count 0 2006.161.08:10:02.74#ibcon#read 6, iclass 10, count 0 2006.161.08:10:02.74#ibcon#end of sib2, iclass 10, count 0 2006.161.08:10:02.74#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:10:02.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:10:02.74#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:10:02.74#ibcon#*before write, iclass 10, count 0 2006.161.08:10:02.74#ibcon#enter sib2, iclass 10, count 0 2006.161.08:10:02.74#ibcon#flushed, iclass 10, count 0 2006.161.08:10:02.74#ibcon#about to write, iclass 10, count 0 2006.161.08:10:02.74#ibcon#wrote, iclass 10, count 0 2006.161.08:10:02.74#ibcon#about to read 3, iclass 10, count 0 2006.161.08:10:02.78#ibcon#read 3, iclass 10, count 0 2006.161.08:10:02.78#ibcon#about to read 4, iclass 10, count 0 2006.161.08:10:02.78#ibcon#read 4, iclass 10, count 0 2006.161.08:10:02.78#ibcon#about to read 5, iclass 10, count 0 2006.161.08:10:02.78#ibcon#read 5, iclass 10, count 0 2006.161.08:10:02.78#ibcon#about to read 6, iclass 10, count 0 2006.161.08:10:02.78#ibcon#read 6, iclass 10, count 0 2006.161.08:10:02.78#ibcon#end of sib2, iclass 10, count 0 2006.161.08:10:02.78#ibcon#*after write, iclass 10, count 0 2006.161.08:10:02.78#ibcon#*before return 0, iclass 10, count 0 2006.161.08:10:02.78#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:10:02.78#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:10:02.78#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:10:02.78#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:10:02.78$vc4f8/vb=3,4 2006.161.08:10:02.78#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.08:10:02.78#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.08:10:02.78#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:02.78#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:10:02.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:10:02.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:10:02.84#ibcon#enter wrdev, iclass 12, count 2 2006.161.08:10:02.84#ibcon#first serial, iclass 12, count 2 2006.161.08:10:02.84#ibcon#enter sib2, iclass 12, count 2 2006.161.08:10:02.84#ibcon#flushed, iclass 12, count 2 2006.161.08:10:02.84#ibcon#about to write, iclass 12, count 2 2006.161.08:10:02.84#ibcon#wrote, iclass 12, count 2 2006.161.08:10:02.84#ibcon#about to read 3, iclass 12, count 2 2006.161.08:10:02.86#ibcon#read 3, iclass 12, count 2 2006.161.08:10:02.86#ibcon#about to read 4, iclass 12, count 2 2006.161.08:10:02.86#ibcon#read 4, iclass 12, count 2 2006.161.08:10:02.86#ibcon#about to read 5, iclass 12, count 2 2006.161.08:10:02.86#ibcon#read 5, iclass 12, count 2 2006.161.08:10:02.86#ibcon#about to read 6, iclass 12, count 2 2006.161.08:10:02.86#ibcon#read 6, iclass 12, count 2 2006.161.08:10:02.86#ibcon#end of sib2, iclass 12, count 2 2006.161.08:10:02.86#ibcon#*mode == 0, iclass 12, count 2 2006.161.08:10:02.86#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.08:10:02.86#ibcon#[27=AT03-04\r\n] 2006.161.08:10:02.86#ibcon#*before write, iclass 12, count 2 2006.161.08:10:02.86#ibcon#enter sib2, iclass 12, count 2 2006.161.08:10:02.86#ibcon#flushed, iclass 12, count 2 2006.161.08:10:02.86#ibcon#about to write, iclass 12, count 2 2006.161.08:10:02.86#ibcon#wrote, iclass 12, count 2 2006.161.08:10:02.86#ibcon#about to read 3, iclass 12, count 2 2006.161.08:10:02.89#ibcon#read 3, iclass 12, count 2 2006.161.08:10:02.89#ibcon#about to read 4, iclass 12, count 2 2006.161.08:10:02.89#ibcon#read 4, iclass 12, count 2 2006.161.08:10:02.89#ibcon#about to read 5, iclass 12, count 2 2006.161.08:10:02.89#ibcon#read 5, iclass 12, count 2 2006.161.08:10:02.89#ibcon#about to read 6, iclass 12, count 2 2006.161.08:10:02.89#ibcon#read 6, iclass 12, count 2 2006.161.08:10:02.89#ibcon#end of sib2, iclass 12, count 2 2006.161.08:10:02.89#ibcon#*after write, iclass 12, count 2 2006.161.08:10:02.89#ibcon#*before return 0, iclass 12, count 2 2006.161.08:10:02.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:10:02.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:10:02.89#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.08:10:02.89#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:02.89#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:03.01#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:03.01#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:03.01#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:10:03.01#ibcon#first serial, iclass 12, count 0 2006.161.08:10:03.01#ibcon#enter sib2, iclass 12, count 0 2006.161.08:10:03.01#ibcon#flushed, iclass 12, count 0 2006.161.08:10:03.01#ibcon#about to write, iclass 12, count 0 2006.161.08:10:03.01#ibcon#wrote, iclass 12, count 0 2006.161.08:10:03.01#ibcon#about to read 3, iclass 12, count 0 2006.161.08:10:03.03#ibcon#read 3, iclass 12, count 0 2006.161.08:10:03.03#ibcon#about to read 4, iclass 12, count 0 2006.161.08:10:03.03#ibcon#read 4, iclass 12, count 0 2006.161.08:10:03.03#ibcon#about to read 5, iclass 12, count 0 2006.161.08:10:03.03#ibcon#read 5, iclass 12, count 0 2006.161.08:10:03.03#ibcon#about to read 6, iclass 12, count 0 2006.161.08:10:03.03#ibcon#read 6, iclass 12, count 0 2006.161.08:10:03.03#ibcon#end of sib2, iclass 12, count 0 2006.161.08:10:03.03#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:10:03.03#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:10:03.03#ibcon#[27=USB\r\n] 2006.161.08:10:03.03#ibcon#*before write, iclass 12, count 0 2006.161.08:10:03.03#ibcon#enter sib2, iclass 12, count 0 2006.161.08:10:03.03#ibcon#flushed, iclass 12, count 0 2006.161.08:10:03.03#ibcon#about to write, iclass 12, count 0 2006.161.08:10:03.03#ibcon#wrote, iclass 12, count 0 2006.161.08:10:03.03#ibcon#about to read 3, iclass 12, count 0 2006.161.08:10:03.06#ibcon#read 3, iclass 12, count 0 2006.161.08:10:03.06#ibcon#about to read 4, iclass 12, count 0 2006.161.08:10:03.06#ibcon#read 4, iclass 12, count 0 2006.161.08:10:03.06#ibcon#about to read 5, iclass 12, count 0 2006.161.08:10:03.06#ibcon#read 5, iclass 12, count 0 2006.161.08:10:03.06#ibcon#about to read 6, iclass 12, count 0 2006.161.08:10:03.06#ibcon#read 6, iclass 12, count 0 2006.161.08:10:03.06#ibcon#end of sib2, iclass 12, count 0 2006.161.08:10:03.06#ibcon#*after write, iclass 12, count 0 2006.161.08:10:03.06#ibcon#*before return 0, iclass 12, count 0 2006.161.08:10:03.06#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:03.06#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:10:03.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:10:03.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:10:03.06$vc4f8/vblo=4,712.99 2006.161.08:10:03.06#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:10:03.06#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:10:03.06#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:03.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:03.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:03.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:03.06#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:10:03.06#ibcon#first serial, iclass 14, count 0 2006.161.08:10:03.06#ibcon#enter sib2, iclass 14, count 0 2006.161.08:10:03.06#ibcon#flushed, iclass 14, count 0 2006.161.08:10:03.06#ibcon#about to write, iclass 14, count 0 2006.161.08:10:03.06#ibcon#wrote, iclass 14, count 0 2006.161.08:10:03.06#ibcon#about to read 3, iclass 14, count 0 2006.161.08:10:03.08#ibcon#read 3, iclass 14, count 0 2006.161.08:10:03.08#ibcon#about to read 4, iclass 14, count 0 2006.161.08:10:03.08#ibcon#read 4, iclass 14, count 0 2006.161.08:10:03.08#ibcon#about to read 5, iclass 14, count 0 2006.161.08:10:03.08#ibcon#read 5, iclass 14, count 0 2006.161.08:10:03.08#ibcon#about to read 6, iclass 14, count 0 2006.161.08:10:03.08#ibcon#read 6, iclass 14, count 0 2006.161.08:10:03.08#ibcon#end of sib2, iclass 14, count 0 2006.161.08:10:03.08#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:10:03.08#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:10:03.08#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:10:03.08#ibcon#*before write, iclass 14, count 0 2006.161.08:10:03.08#ibcon#enter sib2, iclass 14, count 0 2006.161.08:10:03.08#ibcon#flushed, iclass 14, count 0 2006.161.08:10:03.08#ibcon#about to write, iclass 14, count 0 2006.161.08:10:03.08#ibcon#wrote, iclass 14, count 0 2006.161.08:10:03.08#ibcon#about to read 3, iclass 14, count 0 2006.161.08:10:03.12#ibcon#read 3, iclass 14, count 0 2006.161.08:10:03.12#ibcon#about to read 4, iclass 14, count 0 2006.161.08:10:03.12#ibcon#read 4, iclass 14, count 0 2006.161.08:10:03.12#ibcon#about to read 5, iclass 14, count 0 2006.161.08:10:03.12#ibcon#read 5, iclass 14, count 0 2006.161.08:10:03.12#ibcon#about to read 6, iclass 14, count 0 2006.161.08:10:03.12#ibcon#read 6, iclass 14, count 0 2006.161.08:10:03.12#ibcon#end of sib2, iclass 14, count 0 2006.161.08:10:03.12#ibcon#*after write, iclass 14, count 0 2006.161.08:10:03.12#ibcon#*before return 0, iclass 14, count 0 2006.161.08:10:03.12#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:03.12#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:10:03.12#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:10:03.12#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:10:03.12$vc4f8/vb=4,4 2006.161.08:10:03.12#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.08:10:03.12#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.08:10:03.12#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:03.12#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:03.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:03.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:03.18#ibcon#enter wrdev, iclass 16, count 2 2006.161.08:10:03.18#ibcon#first serial, iclass 16, count 2 2006.161.08:10:03.18#ibcon#enter sib2, iclass 16, count 2 2006.161.08:10:03.18#ibcon#flushed, iclass 16, count 2 2006.161.08:10:03.18#ibcon#about to write, iclass 16, count 2 2006.161.08:10:03.18#ibcon#wrote, iclass 16, count 2 2006.161.08:10:03.18#ibcon#about to read 3, iclass 16, count 2 2006.161.08:10:03.20#ibcon#read 3, iclass 16, count 2 2006.161.08:10:03.20#ibcon#about to read 4, iclass 16, count 2 2006.161.08:10:03.20#ibcon#read 4, iclass 16, count 2 2006.161.08:10:03.20#ibcon#about to read 5, iclass 16, count 2 2006.161.08:10:03.20#ibcon#read 5, iclass 16, count 2 2006.161.08:10:03.20#ibcon#about to read 6, iclass 16, count 2 2006.161.08:10:03.20#ibcon#read 6, iclass 16, count 2 2006.161.08:10:03.20#ibcon#end of sib2, iclass 16, count 2 2006.161.08:10:03.20#ibcon#*mode == 0, iclass 16, count 2 2006.161.08:10:03.20#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.08:10:03.20#ibcon#[27=AT04-04\r\n] 2006.161.08:10:03.20#ibcon#*before write, iclass 16, count 2 2006.161.08:10:03.20#ibcon#enter sib2, iclass 16, count 2 2006.161.08:10:03.20#ibcon#flushed, iclass 16, count 2 2006.161.08:10:03.20#ibcon#about to write, iclass 16, count 2 2006.161.08:10:03.20#ibcon#wrote, iclass 16, count 2 2006.161.08:10:03.20#ibcon#about to read 3, iclass 16, count 2 2006.161.08:10:03.23#ibcon#read 3, iclass 16, count 2 2006.161.08:10:03.23#ibcon#about to read 4, iclass 16, count 2 2006.161.08:10:03.23#ibcon#read 4, iclass 16, count 2 2006.161.08:10:03.23#ibcon#about to read 5, iclass 16, count 2 2006.161.08:10:03.23#ibcon#read 5, iclass 16, count 2 2006.161.08:10:03.23#ibcon#about to read 6, iclass 16, count 2 2006.161.08:10:03.23#ibcon#read 6, iclass 16, count 2 2006.161.08:10:03.23#ibcon#end of sib2, iclass 16, count 2 2006.161.08:10:03.23#ibcon#*after write, iclass 16, count 2 2006.161.08:10:03.23#ibcon#*before return 0, iclass 16, count 2 2006.161.08:10:03.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:03.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:10:03.23#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.08:10:03.23#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:03.23#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:03.35#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:03.35#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:03.35#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:10:03.35#ibcon#first serial, iclass 16, count 0 2006.161.08:10:03.35#ibcon#enter sib2, iclass 16, count 0 2006.161.08:10:03.35#ibcon#flushed, iclass 16, count 0 2006.161.08:10:03.35#ibcon#about to write, iclass 16, count 0 2006.161.08:10:03.35#ibcon#wrote, iclass 16, count 0 2006.161.08:10:03.35#ibcon#about to read 3, iclass 16, count 0 2006.161.08:10:03.37#ibcon#read 3, iclass 16, count 0 2006.161.08:10:03.37#ibcon#about to read 4, iclass 16, count 0 2006.161.08:10:03.37#ibcon#read 4, iclass 16, count 0 2006.161.08:10:03.37#ibcon#about to read 5, iclass 16, count 0 2006.161.08:10:03.37#ibcon#read 5, iclass 16, count 0 2006.161.08:10:03.37#ibcon#about to read 6, iclass 16, count 0 2006.161.08:10:03.37#ibcon#read 6, iclass 16, count 0 2006.161.08:10:03.37#ibcon#end of sib2, iclass 16, count 0 2006.161.08:10:03.37#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:10:03.37#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:10:03.37#ibcon#[27=USB\r\n] 2006.161.08:10:03.37#ibcon#*before write, iclass 16, count 0 2006.161.08:10:03.37#ibcon#enter sib2, iclass 16, count 0 2006.161.08:10:03.37#ibcon#flushed, iclass 16, count 0 2006.161.08:10:03.37#ibcon#about to write, iclass 16, count 0 2006.161.08:10:03.37#ibcon#wrote, iclass 16, count 0 2006.161.08:10:03.37#ibcon#about to read 3, iclass 16, count 0 2006.161.08:10:03.40#ibcon#read 3, iclass 16, count 0 2006.161.08:10:03.40#ibcon#about to read 4, iclass 16, count 0 2006.161.08:10:03.40#ibcon#read 4, iclass 16, count 0 2006.161.08:10:03.40#ibcon#about to read 5, iclass 16, count 0 2006.161.08:10:03.40#ibcon#read 5, iclass 16, count 0 2006.161.08:10:03.40#ibcon#about to read 6, iclass 16, count 0 2006.161.08:10:03.40#ibcon#read 6, iclass 16, count 0 2006.161.08:10:03.40#ibcon#end of sib2, iclass 16, count 0 2006.161.08:10:03.40#ibcon#*after write, iclass 16, count 0 2006.161.08:10:03.40#ibcon#*before return 0, iclass 16, count 0 2006.161.08:10:03.40#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:03.40#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:10:03.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:10:03.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:10:03.40$vc4f8/vblo=5,744.99 2006.161.08:10:03.40#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.08:10:03.40#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.08:10:03.40#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:03.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:03.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:03.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:03.40#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:10:03.40#ibcon#first serial, iclass 18, count 0 2006.161.08:10:03.40#ibcon#enter sib2, iclass 18, count 0 2006.161.08:10:03.40#ibcon#flushed, iclass 18, count 0 2006.161.08:10:03.40#ibcon#about to write, iclass 18, count 0 2006.161.08:10:03.40#ibcon#wrote, iclass 18, count 0 2006.161.08:10:03.40#ibcon#about to read 3, iclass 18, count 0 2006.161.08:10:03.42#ibcon#read 3, iclass 18, count 0 2006.161.08:10:03.42#ibcon#about to read 4, iclass 18, count 0 2006.161.08:10:03.42#ibcon#read 4, iclass 18, count 0 2006.161.08:10:03.42#ibcon#about to read 5, iclass 18, count 0 2006.161.08:10:03.42#ibcon#read 5, iclass 18, count 0 2006.161.08:10:03.42#ibcon#about to read 6, iclass 18, count 0 2006.161.08:10:03.42#ibcon#read 6, iclass 18, count 0 2006.161.08:10:03.42#ibcon#end of sib2, iclass 18, count 0 2006.161.08:10:03.42#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:10:03.42#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:10:03.42#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:10:03.42#ibcon#*before write, iclass 18, count 0 2006.161.08:10:03.42#ibcon#enter sib2, iclass 18, count 0 2006.161.08:10:03.42#ibcon#flushed, iclass 18, count 0 2006.161.08:10:03.42#ibcon#about to write, iclass 18, count 0 2006.161.08:10:03.42#ibcon#wrote, iclass 18, count 0 2006.161.08:10:03.42#ibcon#about to read 3, iclass 18, count 0 2006.161.08:10:03.46#ibcon#read 3, iclass 18, count 0 2006.161.08:10:03.46#ibcon#about to read 4, iclass 18, count 0 2006.161.08:10:03.46#ibcon#read 4, iclass 18, count 0 2006.161.08:10:03.46#ibcon#about to read 5, iclass 18, count 0 2006.161.08:10:03.46#ibcon#read 5, iclass 18, count 0 2006.161.08:10:03.46#ibcon#about to read 6, iclass 18, count 0 2006.161.08:10:03.46#ibcon#read 6, iclass 18, count 0 2006.161.08:10:03.46#ibcon#end of sib2, iclass 18, count 0 2006.161.08:10:03.46#ibcon#*after write, iclass 18, count 0 2006.161.08:10:03.46#ibcon#*before return 0, iclass 18, count 0 2006.161.08:10:03.46#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:03.46#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:10:03.46#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:10:03.46#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:10:03.46$vc4f8/vb=5,4 2006.161.08:10:03.46#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.08:10:03.46#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.08:10:03.46#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:03.46#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:03.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:03.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:03.52#ibcon#enter wrdev, iclass 20, count 2 2006.161.08:10:03.52#ibcon#first serial, iclass 20, count 2 2006.161.08:10:03.52#ibcon#enter sib2, iclass 20, count 2 2006.161.08:10:03.52#ibcon#flushed, iclass 20, count 2 2006.161.08:10:03.52#ibcon#about to write, iclass 20, count 2 2006.161.08:10:03.52#ibcon#wrote, iclass 20, count 2 2006.161.08:10:03.52#ibcon#about to read 3, iclass 20, count 2 2006.161.08:10:03.54#ibcon#read 3, iclass 20, count 2 2006.161.08:10:03.54#ibcon#about to read 4, iclass 20, count 2 2006.161.08:10:03.54#ibcon#read 4, iclass 20, count 2 2006.161.08:10:03.54#ibcon#about to read 5, iclass 20, count 2 2006.161.08:10:03.54#ibcon#read 5, iclass 20, count 2 2006.161.08:10:03.54#ibcon#about to read 6, iclass 20, count 2 2006.161.08:10:03.54#ibcon#read 6, iclass 20, count 2 2006.161.08:10:03.54#ibcon#end of sib2, iclass 20, count 2 2006.161.08:10:03.54#ibcon#*mode == 0, iclass 20, count 2 2006.161.08:10:03.54#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.08:10:03.54#ibcon#[27=AT05-04\r\n] 2006.161.08:10:03.54#ibcon#*before write, iclass 20, count 2 2006.161.08:10:03.54#ibcon#enter sib2, iclass 20, count 2 2006.161.08:10:03.54#ibcon#flushed, iclass 20, count 2 2006.161.08:10:03.54#ibcon#about to write, iclass 20, count 2 2006.161.08:10:03.54#ibcon#wrote, iclass 20, count 2 2006.161.08:10:03.54#ibcon#about to read 3, iclass 20, count 2 2006.161.08:10:03.57#ibcon#read 3, iclass 20, count 2 2006.161.08:10:03.57#ibcon#about to read 4, iclass 20, count 2 2006.161.08:10:03.57#ibcon#read 4, iclass 20, count 2 2006.161.08:10:03.57#ibcon#about to read 5, iclass 20, count 2 2006.161.08:10:03.57#ibcon#read 5, iclass 20, count 2 2006.161.08:10:03.57#ibcon#about to read 6, iclass 20, count 2 2006.161.08:10:03.57#ibcon#read 6, iclass 20, count 2 2006.161.08:10:03.57#ibcon#end of sib2, iclass 20, count 2 2006.161.08:10:03.57#ibcon#*after write, iclass 20, count 2 2006.161.08:10:03.57#ibcon#*before return 0, iclass 20, count 2 2006.161.08:10:03.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:03.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:10:03.57#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.08:10:03.57#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:03.57#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:03.69#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:03.69#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:03.69#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:10:03.69#ibcon#first serial, iclass 20, count 0 2006.161.08:10:03.69#ibcon#enter sib2, iclass 20, count 0 2006.161.08:10:03.69#ibcon#flushed, iclass 20, count 0 2006.161.08:10:03.69#ibcon#about to write, iclass 20, count 0 2006.161.08:10:03.69#ibcon#wrote, iclass 20, count 0 2006.161.08:10:03.69#ibcon#about to read 3, iclass 20, count 0 2006.161.08:10:03.71#ibcon#read 3, iclass 20, count 0 2006.161.08:10:03.71#ibcon#about to read 4, iclass 20, count 0 2006.161.08:10:03.71#ibcon#read 4, iclass 20, count 0 2006.161.08:10:03.71#ibcon#about to read 5, iclass 20, count 0 2006.161.08:10:03.71#ibcon#read 5, iclass 20, count 0 2006.161.08:10:03.71#ibcon#about to read 6, iclass 20, count 0 2006.161.08:10:03.71#ibcon#read 6, iclass 20, count 0 2006.161.08:10:03.71#ibcon#end of sib2, iclass 20, count 0 2006.161.08:10:03.71#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:10:03.71#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:10:03.71#ibcon#[27=USB\r\n] 2006.161.08:10:03.71#ibcon#*before write, iclass 20, count 0 2006.161.08:10:03.71#ibcon#enter sib2, iclass 20, count 0 2006.161.08:10:03.71#ibcon#flushed, iclass 20, count 0 2006.161.08:10:03.71#ibcon#about to write, iclass 20, count 0 2006.161.08:10:03.71#ibcon#wrote, iclass 20, count 0 2006.161.08:10:03.71#ibcon#about to read 3, iclass 20, count 0 2006.161.08:10:03.74#ibcon#read 3, iclass 20, count 0 2006.161.08:10:03.74#ibcon#about to read 4, iclass 20, count 0 2006.161.08:10:03.74#ibcon#read 4, iclass 20, count 0 2006.161.08:10:03.74#ibcon#about to read 5, iclass 20, count 0 2006.161.08:10:03.74#ibcon#read 5, iclass 20, count 0 2006.161.08:10:03.74#ibcon#about to read 6, iclass 20, count 0 2006.161.08:10:03.74#ibcon#read 6, iclass 20, count 0 2006.161.08:10:03.74#ibcon#end of sib2, iclass 20, count 0 2006.161.08:10:03.74#ibcon#*after write, iclass 20, count 0 2006.161.08:10:03.74#ibcon#*before return 0, iclass 20, count 0 2006.161.08:10:03.74#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:03.74#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:10:03.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:10:03.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:10:03.74$vc4f8/vblo=6,752.99 2006.161.08:10:03.74#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:10:03.74#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:10:03.74#ibcon#ireg 17 cls_cnt 0 2006.161.08:10:03.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:03.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:03.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:03.74#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:10:03.74#ibcon#first serial, iclass 22, count 0 2006.161.08:10:03.74#ibcon#enter sib2, iclass 22, count 0 2006.161.08:10:03.74#ibcon#flushed, iclass 22, count 0 2006.161.08:10:03.74#ibcon#about to write, iclass 22, count 0 2006.161.08:10:03.74#ibcon#wrote, iclass 22, count 0 2006.161.08:10:03.74#ibcon#about to read 3, iclass 22, count 0 2006.161.08:10:03.76#ibcon#read 3, iclass 22, count 0 2006.161.08:10:03.76#ibcon#about to read 4, iclass 22, count 0 2006.161.08:10:03.76#ibcon#read 4, iclass 22, count 0 2006.161.08:10:03.76#ibcon#about to read 5, iclass 22, count 0 2006.161.08:10:03.76#ibcon#read 5, iclass 22, count 0 2006.161.08:10:03.76#ibcon#about to read 6, iclass 22, count 0 2006.161.08:10:03.76#ibcon#read 6, iclass 22, count 0 2006.161.08:10:03.76#ibcon#end of sib2, iclass 22, count 0 2006.161.08:10:03.76#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:10:03.76#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:10:03.76#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:10:03.76#ibcon#*before write, iclass 22, count 0 2006.161.08:10:03.76#ibcon#enter sib2, iclass 22, count 0 2006.161.08:10:03.76#ibcon#flushed, iclass 22, count 0 2006.161.08:10:03.76#ibcon#about to write, iclass 22, count 0 2006.161.08:10:03.76#ibcon#wrote, iclass 22, count 0 2006.161.08:10:03.76#ibcon#about to read 3, iclass 22, count 0 2006.161.08:10:03.80#ibcon#read 3, iclass 22, count 0 2006.161.08:10:03.80#ibcon#about to read 4, iclass 22, count 0 2006.161.08:10:03.80#ibcon#read 4, iclass 22, count 0 2006.161.08:10:03.80#ibcon#about to read 5, iclass 22, count 0 2006.161.08:10:03.80#ibcon#read 5, iclass 22, count 0 2006.161.08:10:03.80#ibcon#about to read 6, iclass 22, count 0 2006.161.08:10:03.80#ibcon#read 6, iclass 22, count 0 2006.161.08:10:03.80#ibcon#end of sib2, iclass 22, count 0 2006.161.08:10:03.80#ibcon#*after write, iclass 22, count 0 2006.161.08:10:03.80#ibcon#*before return 0, iclass 22, count 0 2006.161.08:10:03.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:03.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:10:03.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:10:03.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:10:03.80$vc4f8/vb=6,4 2006.161.08:10:03.80#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:10:03.80#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:10:03.80#ibcon#ireg 11 cls_cnt 2 2006.161.08:10:03.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:03.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:03.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:03.86#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:10:03.86#ibcon#first serial, iclass 24, count 2 2006.161.08:10:03.86#ibcon#enter sib2, iclass 24, count 2 2006.161.08:10:03.86#ibcon#flushed, iclass 24, count 2 2006.161.08:10:03.86#ibcon#about to write, iclass 24, count 2 2006.161.08:10:03.86#ibcon#wrote, iclass 24, count 2 2006.161.08:10:03.86#ibcon#about to read 3, iclass 24, count 2 2006.161.08:10:03.88#ibcon#read 3, iclass 24, count 2 2006.161.08:10:03.88#ibcon#about to read 4, iclass 24, count 2 2006.161.08:10:03.88#ibcon#read 4, iclass 24, count 2 2006.161.08:10:03.88#ibcon#about to read 5, iclass 24, count 2 2006.161.08:10:03.88#ibcon#read 5, iclass 24, count 2 2006.161.08:10:03.88#ibcon#about to read 6, iclass 24, count 2 2006.161.08:10:03.88#ibcon#read 6, iclass 24, count 2 2006.161.08:10:03.88#ibcon#end of sib2, iclass 24, count 2 2006.161.08:10:03.88#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:10:03.88#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:10:03.88#ibcon#[27=AT06-04\r\n] 2006.161.08:10:03.88#ibcon#*before write, iclass 24, count 2 2006.161.08:10:03.88#ibcon#enter sib2, iclass 24, count 2 2006.161.08:10:03.88#ibcon#flushed, iclass 24, count 2 2006.161.08:10:03.88#ibcon#about to write, iclass 24, count 2 2006.161.08:10:03.88#ibcon#wrote, iclass 24, count 2 2006.161.08:10:03.88#ibcon#about to read 3, iclass 24, count 2 2006.161.08:10:03.91#ibcon#read 3, iclass 24, count 2 2006.161.08:10:03.91#ibcon#about to read 4, iclass 24, count 2 2006.161.08:10:03.91#ibcon#read 4, iclass 24, count 2 2006.161.08:10:03.91#ibcon#about to read 5, iclass 24, count 2 2006.161.08:10:03.91#ibcon#read 5, iclass 24, count 2 2006.161.08:10:03.91#ibcon#about to read 6, iclass 24, count 2 2006.161.08:10:03.91#ibcon#read 6, iclass 24, count 2 2006.161.08:10:03.91#ibcon#end of sib2, iclass 24, count 2 2006.161.08:10:03.91#ibcon#*after write, iclass 24, count 2 2006.161.08:10:03.91#ibcon#*before return 0, iclass 24, count 2 2006.161.08:10:03.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:03.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:10:03.91#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:10:03.91#ibcon#ireg 7 cls_cnt 0 2006.161.08:10:03.91#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:04.03#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:04.03#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:04.03#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:10:04.03#ibcon#first serial, iclass 24, count 0 2006.161.08:10:04.03#ibcon#enter sib2, iclass 24, count 0 2006.161.08:10:04.03#ibcon#flushed, iclass 24, count 0 2006.161.08:10:04.03#ibcon#about to write, iclass 24, count 0 2006.161.08:10:04.03#ibcon#wrote, iclass 24, count 0 2006.161.08:10:04.03#ibcon#about to read 3, iclass 24, count 0 2006.161.08:10:04.05#ibcon#read 3, iclass 24, count 0 2006.161.08:10:04.05#ibcon#about to read 4, iclass 24, count 0 2006.161.08:10:04.05#ibcon#read 4, iclass 24, count 0 2006.161.08:10:04.05#ibcon#about to read 5, iclass 24, count 0 2006.161.08:10:04.05#ibcon#read 5, iclass 24, count 0 2006.161.08:10:04.05#ibcon#about to read 6, iclass 24, count 0 2006.161.08:10:04.05#ibcon#read 6, iclass 24, count 0 2006.161.08:10:04.05#ibcon#end of sib2, iclass 24, count 0 2006.161.08:10:04.05#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:10:04.05#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:10:04.05#ibcon#[27=USB\r\n] 2006.161.08:10:04.05#ibcon#*before write, iclass 24, count 0 2006.161.08:10:04.05#ibcon#enter sib2, iclass 24, count 0 2006.161.08:10:04.05#ibcon#flushed, iclass 24, count 0 2006.161.08:10:04.05#ibcon#about to write, iclass 24, count 0 2006.161.08:10:04.05#ibcon#wrote, iclass 24, count 0 2006.161.08:10:04.05#ibcon#about to read 3, iclass 24, count 0 2006.161.08:10:04.08#ibcon#read 3, iclass 24, count 0 2006.161.08:10:04.08#ibcon#about to read 4, iclass 24, count 0 2006.161.08:10:04.08#ibcon#read 4, iclass 24, count 0 2006.161.08:10:04.08#ibcon#about to read 5, iclass 24, count 0 2006.161.08:10:04.08#ibcon#read 5, iclass 24, count 0 2006.161.08:10:04.08#ibcon#about to read 6, iclass 24, count 0 2006.161.08:10:04.08#ibcon#read 6, iclass 24, count 0 2006.161.08:10:04.08#ibcon#end of sib2, iclass 24, count 0 2006.161.08:10:04.08#ibcon#*after write, iclass 24, count 0 2006.161.08:10:04.08#ibcon#*before return 0, iclass 24, count 0 2006.161.08:10:04.08#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:04.08#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:10:04.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:10:04.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:10:04.08$vc4f8/vabw=wide 2006.161.08:10:04.08#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:10:04.08#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:10:04.08#ibcon#ireg 8 cls_cnt 0 2006.161.08:10:04.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:04.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:04.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:04.08#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:10:04.08#ibcon#first serial, iclass 26, count 0 2006.161.08:10:04.08#ibcon#enter sib2, iclass 26, count 0 2006.161.08:10:04.08#ibcon#flushed, iclass 26, count 0 2006.161.08:10:04.08#ibcon#about to write, iclass 26, count 0 2006.161.08:10:04.08#ibcon#wrote, iclass 26, count 0 2006.161.08:10:04.08#ibcon#about to read 3, iclass 26, count 0 2006.161.08:10:04.10#ibcon#read 3, iclass 26, count 0 2006.161.08:10:04.10#ibcon#about to read 4, iclass 26, count 0 2006.161.08:10:04.10#ibcon#read 4, iclass 26, count 0 2006.161.08:10:04.10#ibcon#about to read 5, iclass 26, count 0 2006.161.08:10:04.10#ibcon#read 5, iclass 26, count 0 2006.161.08:10:04.10#ibcon#about to read 6, iclass 26, count 0 2006.161.08:10:04.10#ibcon#read 6, iclass 26, count 0 2006.161.08:10:04.10#ibcon#end of sib2, iclass 26, count 0 2006.161.08:10:04.10#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:10:04.10#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:10:04.10#ibcon#[25=BW32\r\n] 2006.161.08:10:04.10#ibcon#*before write, iclass 26, count 0 2006.161.08:10:04.10#ibcon#enter sib2, iclass 26, count 0 2006.161.08:10:04.10#ibcon#flushed, iclass 26, count 0 2006.161.08:10:04.10#ibcon#about to write, iclass 26, count 0 2006.161.08:10:04.10#ibcon#wrote, iclass 26, count 0 2006.161.08:10:04.10#ibcon#about to read 3, iclass 26, count 0 2006.161.08:10:04.13#ibcon#read 3, iclass 26, count 0 2006.161.08:10:04.13#ibcon#about to read 4, iclass 26, count 0 2006.161.08:10:04.13#ibcon#read 4, iclass 26, count 0 2006.161.08:10:04.13#ibcon#about to read 5, iclass 26, count 0 2006.161.08:10:04.13#ibcon#read 5, iclass 26, count 0 2006.161.08:10:04.13#ibcon#about to read 6, iclass 26, count 0 2006.161.08:10:04.13#ibcon#read 6, iclass 26, count 0 2006.161.08:10:04.13#ibcon#end of sib2, iclass 26, count 0 2006.161.08:10:04.13#ibcon#*after write, iclass 26, count 0 2006.161.08:10:04.13#ibcon#*before return 0, iclass 26, count 0 2006.161.08:10:04.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:04.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:10:04.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:10:04.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:10:04.13$vc4f8/vbbw=wide 2006.161.08:10:04.13#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:10:04.13#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:10:04.13#ibcon#ireg 8 cls_cnt 0 2006.161.08:10:04.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:10:04.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:10:04.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:10:04.20#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:10:04.20#ibcon#first serial, iclass 28, count 0 2006.161.08:10:04.20#ibcon#enter sib2, iclass 28, count 0 2006.161.08:10:04.20#ibcon#flushed, iclass 28, count 0 2006.161.08:10:04.20#ibcon#about to write, iclass 28, count 0 2006.161.08:10:04.20#ibcon#wrote, iclass 28, count 0 2006.161.08:10:04.20#ibcon#about to read 3, iclass 28, count 0 2006.161.08:10:04.22#ibcon#read 3, iclass 28, count 0 2006.161.08:10:04.22#ibcon#about to read 4, iclass 28, count 0 2006.161.08:10:04.22#ibcon#read 4, iclass 28, count 0 2006.161.08:10:04.22#ibcon#about to read 5, iclass 28, count 0 2006.161.08:10:04.22#ibcon#read 5, iclass 28, count 0 2006.161.08:10:04.22#ibcon#about to read 6, iclass 28, count 0 2006.161.08:10:04.22#ibcon#read 6, iclass 28, count 0 2006.161.08:10:04.22#ibcon#end of sib2, iclass 28, count 0 2006.161.08:10:04.22#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:10:04.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:10:04.22#ibcon#[27=BW32\r\n] 2006.161.08:10:04.22#ibcon#*before write, iclass 28, count 0 2006.161.08:10:04.22#ibcon#enter sib2, iclass 28, count 0 2006.161.08:10:04.22#ibcon#flushed, iclass 28, count 0 2006.161.08:10:04.22#ibcon#about to write, iclass 28, count 0 2006.161.08:10:04.22#ibcon#wrote, iclass 28, count 0 2006.161.08:10:04.22#ibcon#about to read 3, iclass 28, count 0 2006.161.08:10:04.25#ibcon#read 3, iclass 28, count 0 2006.161.08:10:04.25#ibcon#about to read 4, iclass 28, count 0 2006.161.08:10:04.25#ibcon#read 4, iclass 28, count 0 2006.161.08:10:04.25#ibcon#about to read 5, iclass 28, count 0 2006.161.08:10:04.25#ibcon#read 5, iclass 28, count 0 2006.161.08:10:04.25#ibcon#about to read 6, iclass 28, count 0 2006.161.08:10:04.25#ibcon#read 6, iclass 28, count 0 2006.161.08:10:04.25#ibcon#end of sib2, iclass 28, count 0 2006.161.08:10:04.25#ibcon#*after write, iclass 28, count 0 2006.161.08:10:04.25#ibcon#*before return 0, iclass 28, count 0 2006.161.08:10:04.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:10:04.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:10:04.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:10:04.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:10:04.25$4f8m12a/ifd4f 2006.161.08:10:04.25$ifd4f/lo= 2006.161.08:10:04.25$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:10:04.25$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:10:04.25$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:10:04.25$ifd4f/patch= 2006.161.08:10:04.25$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:10:04.25$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:10:04.25$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:10:04.25$4f8m12a/"form=m,16.000,1:2 2006.161.08:10:04.25$4f8m12a/"tpicd 2006.161.08:10:04.25$4f8m12a/echo=off 2006.161.08:10:04.25$4f8m12a/xlog=off 2006.161.08:10:04.25:!2006.161.08:10:50 2006.161.08:10:24.14#trakl#Source acquired 2006.161.08:10:24.14#flagr#flagr/antenna,acquired 2006.161.08:10:50.00:preob 2006.161.08:10:50.14/onsource/TRACKING 2006.161.08:10:50.14:!2006.161.08:11:00 2006.161.08:11:00.00:data_valid=on 2006.161.08:11:00.00:midob 2006.161.08:11:00.14/onsource/TRACKING 2006.161.08:11:00.14/wx/24.00,1002.6,86 2006.161.08:11:00.34/cable/+6.4996E-03 2006.161.08:11:01.43/va/01,08,usb,yes,29,30 2006.161.08:11:01.43/va/02,07,usb,yes,29,30 2006.161.08:11:01.43/va/03,06,usb,yes,30,30 2006.161.08:11:01.43/va/04,07,usb,yes,30,32 2006.161.08:11:01.43/va/05,07,usb,yes,29,31 2006.161.08:11:01.43/va/06,06,usb,yes,29,28 2006.161.08:11:01.43/va/07,06,usb,yes,29,29 2006.161.08:11:01.43/va/08,07,usb,yes,27,27 2006.161.08:11:01.66/valo/01,532.99,yes,locked 2006.161.08:11:01.66/valo/02,572.99,yes,locked 2006.161.08:11:01.66/valo/03,672.99,yes,locked 2006.161.08:11:01.66/valo/04,832.99,yes,locked 2006.161.08:11:01.66/valo/05,652.99,yes,locked 2006.161.08:11:01.66/valo/06,772.99,yes,locked 2006.161.08:11:01.66/valo/07,832.99,yes,locked 2006.161.08:11:01.66/valo/08,852.99,yes,locked 2006.161.08:11:02.75/vb/01,04,usb,yes,29,28 2006.161.08:11:02.75/vb/02,04,usb,yes,30,32 2006.161.08:11:02.75/vb/03,04,usb,yes,27,30 2006.161.08:11:02.75/vb/04,04,usb,yes,28,28 2006.161.08:11:02.75/vb/05,04,usb,yes,26,30 2006.161.08:11:02.75/vb/06,04,usb,yes,27,30 2006.161.08:11:02.75/vb/07,04,usb,yes,29,29 2006.161.08:11:02.75/vb/08,04,usb,yes,27,30 2006.161.08:11:02.98/vblo/01,632.99,yes,locked 2006.161.08:11:02.98/vblo/02,640.99,yes,locked 2006.161.08:11:02.98/vblo/03,656.99,yes,locked 2006.161.08:11:02.98/vblo/04,712.99,yes,locked 2006.161.08:11:02.98/vblo/05,744.99,yes,locked 2006.161.08:11:02.98/vblo/06,752.99,yes,locked 2006.161.08:11:02.98/vblo/07,734.99,yes,locked 2006.161.08:11:02.98/vblo/08,744.99,yes,locked 2006.161.08:11:03.13/vabw/8 2006.161.08:11:03.28/vbbw/8 2006.161.08:11:03.37/xfe/off,on,15.2 2006.161.08:11:03.76/ifatt/23,28,28,28 2006.161.08:11:04.08/fmout-gps/S +4.50E-07 2006.161.08:11:04.12:!2006.161.08:13:10 2006.161.08:13:10.00:data_valid=off 2006.161.08:13:10.01:postob 2006.161.08:13:10.13/cable/+6.5004E-03 2006.161.08:13:10.14/wx/23.99,1002.5,87 2006.161.08:13:11.07/fmout-gps/S +4.50E-07 2006.161.08:13:11.08:scan_name=161-0814,k06161,60 2006.161.08:13:11.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.161.08:13:12.13#flagr#flagr/antenna,new-source 2006.161.08:13:12.14:checkk5 2006.161.08:13:12.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:13:13.00/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:13:13.46/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:13:13.88/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:13:14.31/chk_obsdata//k5ts1/T1610811??a.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.161.08:13:14.75/chk_obsdata//k5ts2/T1610811??b.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.161.08:13:15.17/chk_obsdata//k5ts3/T1610811??c.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.161.08:13:15.57/chk_obsdata//k5ts4/T1610811??d.dat file size is correct (nominal:1040MB, actual:1032MB). 2006.161.08:13:16.40/k5log//k5ts1_log_newline 2006.161.08:13:17.61/k5log//k5ts2_log_newline 2006.161.08:13:18.37/k5log//k5ts3_log_newline 2006.161.08:13:19.17/k5log//k5ts4_log_newline 2006.161.08:13:19.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:13:19.23:4f8m12a=2 2006.161.08:13:19.23$4f8m12a/echo=on 2006.161.08:13:19.23$4f8m12a/pcalon 2006.161.08:13:19.23$pcalon/"no phase cal control is implemented here 2006.161.08:13:19.23$4f8m12a/"tpicd=stop 2006.161.08:13:19.23$4f8m12a/vc4f8 2006.161.08:13:19.23$vc4f8/valo=1,532.99 2006.161.08:13:19.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.08:13:19.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.08:13:19.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:19.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:19.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:19.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:19.23#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:13:19.23#ibcon#first serial, iclass 35, count 0 2006.161.08:13:19.23#ibcon#enter sib2, iclass 35, count 0 2006.161.08:13:19.23#ibcon#flushed, iclass 35, count 0 2006.161.08:13:19.23#ibcon#about to write, iclass 35, count 0 2006.161.08:13:19.23#ibcon#wrote, iclass 35, count 0 2006.161.08:13:19.23#ibcon#about to read 3, iclass 35, count 0 2006.161.08:13:19.25#ibcon#read 3, iclass 35, count 0 2006.161.08:13:19.25#ibcon#about to read 4, iclass 35, count 0 2006.161.08:13:19.25#ibcon#read 4, iclass 35, count 0 2006.161.08:13:19.25#ibcon#about to read 5, iclass 35, count 0 2006.161.08:13:19.25#ibcon#read 5, iclass 35, count 0 2006.161.08:13:19.25#ibcon#about to read 6, iclass 35, count 0 2006.161.08:13:19.25#ibcon#read 6, iclass 35, count 0 2006.161.08:13:19.25#ibcon#end of sib2, iclass 35, count 0 2006.161.08:13:19.25#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:13:19.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:13:19.25#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:13:19.25#ibcon#*before write, iclass 35, count 0 2006.161.08:13:19.25#ibcon#enter sib2, iclass 35, count 0 2006.161.08:13:19.25#ibcon#flushed, iclass 35, count 0 2006.161.08:13:19.25#ibcon#about to write, iclass 35, count 0 2006.161.08:13:19.25#ibcon#wrote, iclass 35, count 0 2006.161.08:13:19.25#ibcon#about to read 3, iclass 35, count 0 2006.161.08:13:19.31#ibcon#read 3, iclass 35, count 0 2006.161.08:13:19.31#ibcon#about to read 4, iclass 35, count 0 2006.161.08:13:19.31#ibcon#read 4, iclass 35, count 0 2006.161.08:13:19.31#ibcon#about to read 5, iclass 35, count 0 2006.161.08:13:19.31#ibcon#read 5, iclass 35, count 0 2006.161.08:13:19.31#ibcon#about to read 6, iclass 35, count 0 2006.161.08:13:19.31#ibcon#read 6, iclass 35, count 0 2006.161.08:13:19.31#ibcon#end of sib2, iclass 35, count 0 2006.161.08:13:19.31#ibcon#*after write, iclass 35, count 0 2006.161.08:13:19.31#ibcon#*before return 0, iclass 35, count 0 2006.161.08:13:19.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:19.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:19.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:13:19.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:13:19.31$vc4f8/va=1,8 2006.161.08:13:19.31#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.08:13:19.31#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.08:13:19.31#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:19.31#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:19.31#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:19.31#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:19.31#ibcon#enter wrdev, iclass 37, count 2 2006.161.08:13:19.31#ibcon#first serial, iclass 37, count 2 2006.161.08:13:19.31#ibcon#enter sib2, iclass 37, count 2 2006.161.08:13:19.31#ibcon#flushed, iclass 37, count 2 2006.161.08:13:19.31#ibcon#about to write, iclass 37, count 2 2006.161.08:13:19.31#ibcon#wrote, iclass 37, count 2 2006.161.08:13:19.31#ibcon#about to read 3, iclass 37, count 2 2006.161.08:13:19.32#ibcon#read 3, iclass 37, count 2 2006.161.08:13:19.32#ibcon#about to read 4, iclass 37, count 2 2006.161.08:13:19.32#ibcon#read 4, iclass 37, count 2 2006.161.08:13:19.32#ibcon#about to read 5, iclass 37, count 2 2006.161.08:13:19.32#ibcon#read 5, iclass 37, count 2 2006.161.08:13:19.32#ibcon#about to read 6, iclass 37, count 2 2006.161.08:13:19.32#ibcon#read 6, iclass 37, count 2 2006.161.08:13:19.32#ibcon#end of sib2, iclass 37, count 2 2006.161.08:13:19.32#ibcon#*mode == 0, iclass 37, count 2 2006.161.08:13:19.32#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.08:13:19.32#ibcon#[25=AT01-08\r\n] 2006.161.08:13:19.32#ibcon#*before write, iclass 37, count 2 2006.161.08:13:19.32#ibcon#enter sib2, iclass 37, count 2 2006.161.08:13:19.32#ibcon#flushed, iclass 37, count 2 2006.161.08:13:19.32#ibcon#about to write, iclass 37, count 2 2006.161.08:13:19.32#ibcon#wrote, iclass 37, count 2 2006.161.08:13:19.32#ibcon#about to read 3, iclass 37, count 2 2006.161.08:13:19.35#ibcon#read 3, iclass 37, count 2 2006.161.08:13:19.35#ibcon#about to read 4, iclass 37, count 2 2006.161.08:13:19.35#ibcon#read 4, iclass 37, count 2 2006.161.08:13:19.35#ibcon#about to read 5, iclass 37, count 2 2006.161.08:13:19.35#ibcon#read 5, iclass 37, count 2 2006.161.08:13:19.35#ibcon#about to read 6, iclass 37, count 2 2006.161.08:13:19.35#ibcon#read 6, iclass 37, count 2 2006.161.08:13:19.35#ibcon#end of sib2, iclass 37, count 2 2006.161.08:13:19.35#ibcon#*after write, iclass 37, count 2 2006.161.08:13:19.35#ibcon#*before return 0, iclass 37, count 2 2006.161.08:13:19.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:19.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:19.35#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.08:13:19.35#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:19.35#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:19.47#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:19.47#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:19.47#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:13:19.47#ibcon#first serial, iclass 37, count 0 2006.161.08:13:19.47#ibcon#enter sib2, iclass 37, count 0 2006.161.08:13:19.47#ibcon#flushed, iclass 37, count 0 2006.161.08:13:19.47#ibcon#about to write, iclass 37, count 0 2006.161.08:13:19.47#ibcon#wrote, iclass 37, count 0 2006.161.08:13:19.47#ibcon#about to read 3, iclass 37, count 0 2006.161.08:13:19.49#ibcon#read 3, iclass 37, count 0 2006.161.08:13:19.49#ibcon#about to read 4, iclass 37, count 0 2006.161.08:13:19.49#ibcon#read 4, iclass 37, count 0 2006.161.08:13:19.49#ibcon#about to read 5, iclass 37, count 0 2006.161.08:13:19.49#ibcon#read 5, iclass 37, count 0 2006.161.08:13:19.49#ibcon#about to read 6, iclass 37, count 0 2006.161.08:13:19.49#ibcon#read 6, iclass 37, count 0 2006.161.08:13:19.49#ibcon#end of sib2, iclass 37, count 0 2006.161.08:13:19.49#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:13:19.49#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:13:19.49#ibcon#[25=USB\r\n] 2006.161.08:13:19.49#ibcon#*before write, iclass 37, count 0 2006.161.08:13:19.49#ibcon#enter sib2, iclass 37, count 0 2006.161.08:13:19.49#ibcon#flushed, iclass 37, count 0 2006.161.08:13:19.49#ibcon#about to write, iclass 37, count 0 2006.161.08:13:19.49#ibcon#wrote, iclass 37, count 0 2006.161.08:13:19.49#ibcon#about to read 3, iclass 37, count 0 2006.161.08:13:19.52#ibcon#read 3, iclass 37, count 0 2006.161.08:13:19.52#ibcon#about to read 4, iclass 37, count 0 2006.161.08:13:19.52#ibcon#read 4, iclass 37, count 0 2006.161.08:13:19.52#ibcon#about to read 5, iclass 37, count 0 2006.161.08:13:19.52#ibcon#read 5, iclass 37, count 0 2006.161.08:13:19.52#ibcon#about to read 6, iclass 37, count 0 2006.161.08:13:19.52#ibcon#read 6, iclass 37, count 0 2006.161.08:13:19.52#ibcon#end of sib2, iclass 37, count 0 2006.161.08:13:19.52#ibcon#*after write, iclass 37, count 0 2006.161.08:13:19.52#ibcon#*before return 0, iclass 37, count 0 2006.161.08:13:19.52#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:19.52#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:19.52#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:13:19.52#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:13:19.52$vc4f8/valo=2,572.99 2006.161.08:13:19.52#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.08:13:19.52#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.08:13:19.52#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:19.52#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:19.52#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:19.52#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:19.52#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:13:19.52#ibcon#first serial, iclass 39, count 0 2006.161.08:13:19.52#ibcon#enter sib2, iclass 39, count 0 2006.161.08:13:19.52#ibcon#flushed, iclass 39, count 0 2006.161.08:13:19.52#ibcon#about to write, iclass 39, count 0 2006.161.08:13:19.52#ibcon#wrote, iclass 39, count 0 2006.161.08:13:19.52#ibcon#about to read 3, iclass 39, count 0 2006.161.08:13:19.54#ibcon#read 3, iclass 39, count 0 2006.161.08:13:19.54#ibcon#about to read 4, iclass 39, count 0 2006.161.08:13:19.54#ibcon#read 4, iclass 39, count 0 2006.161.08:13:19.54#ibcon#about to read 5, iclass 39, count 0 2006.161.08:13:19.54#ibcon#read 5, iclass 39, count 0 2006.161.08:13:19.54#ibcon#about to read 6, iclass 39, count 0 2006.161.08:13:19.54#ibcon#read 6, iclass 39, count 0 2006.161.08:13:19.54#ibcon#end of sib2, iclass 39, count 0 2006.161.08:13:19.54#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:13:19.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:13:19.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:13:19.54#ibcon#*before write, iclass 39, count 0 2006.161.08:13:19.54#ibcon#enter sib2, iclass 39, count 0 2006.161.08:13:19.54#ibcon#flushed, iclass 39, count 0 2006.161.08:13:19.54#ibcon#about to write, iclass 39, count 0 2006.161.08:13:19.54#ibcon#wrote, iclass 39, count 0 2006.161.08:13:19.54#ibcon#about to read 3, iclass 39, count 0 2006.161.08:13:19.58#ibcon#read 3, iclass 39, count 0 2006.161.08:13:19.58#ibcon#about to read 4, iclass 39, count 0 2006.161.08:13:19.58#ibcon#read 4, iclass 39, count 0 2006.161.08:13:19.58#ibcon#about to read 5, iclass 39, count 0 2006.161.08:13:19.58#ibcon#read 5, iclass 39, count 0 2006.161.08:13:19.58#ibcon#about to read 6, iclass 39, count 0 2006.161.08:13:19.58#ibcon#read 6, iclass 39, count 0 2006.161.08:13:19.58#ibcon#end of sib2, iclass 39, count 0 2006.161.08:13:19.58#ibcon#*after write, iclass 39, count 0 2006.161.08:13:19.58#ibcon#*before return 0, iclass 39, count 0 2006.161.08:13:19.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:19.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:19.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:13:19.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:13:19.58$vc4f8/va=2,7 2006.161.08:13:19.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.08:13:19.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.08:13:19.58#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:19.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:19.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:19.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:19.65#ibcon#enter wrdev, iclass 3, count 2 2006.161.08:13:19.65#ibcon#first serial, iclass 3, count 2 2006.161.08:13:19.65#ibcon#enter sib2, iclass 3, count 2 2006.161.08:13:19.65#ibcon#flushed, iclass 3, count 2 2006.161.08:13:19.65#ibcon#about to write, iclass 3, count 2 2006.161.08:13:19.65#ibcon#wrote, iclass 3, count 2 2006.161.08:13:19.65#ibcon#about to read 3, iclass 3, count 2 2006.161.08:13:19.66#ibcon#read 3, iclass 3, count 2 2006.161.08:13:19.66#ibcon#about to read 4, iclass 3, count 2 2006.161.08:13:19.66#ibcon#read 4, iclass 3, count 2 2006.161.08:13:19.66#ibcon#about to read 5, iclass 3, count 2 2006.161.08:13:19.66#ibcon#read 5, iclass 3, count 2 2006.161.08:13:19.66#ibcon#about to read 6, iclass 3, count 2 2006.161.08:13:19.66#ibcon#read 6, iclass 3, count 2 2006.161.08:13:19.66#ibcon#end of sib2, iclass 3, count 2 2006.161.08:13:19.66#ibcon#*mode == 0, iclass 3, count 2 2006.161.08:13:19.66#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.08:13:19.66#ibcon#[25=AT02-07\r\n] 2006.161.08:13:19.66#ibcon#*before write, iclass 3, count 2 2006.161.08:13:19.66#ibcon#enter sib2, iclass 3, count 2 2006.161.08:13:19.66#ibcon#flushed, iclass 3, count 2 2006.161.08:13:19.66#ibcon#about to write, iclass 3, count 2 2006.161.08:13:19.66#ibcon#wrote, iclass 3, count 2 2006.161.08:13:19.66#ibcon#about to read 3, iclass 3, count 2 2006.161.08:13:19.69#ibcon#read 3, iclass 3, count 2 2006.161.08:13:19.69#ibcon#about to read 4, iclass 3, count 2 2006.161.08:13:19.69#ibcon#read 4, iclass 3, count 2 2006.161.08:13:19.69#ibcon#about to read 5, iclass 3, count 2 2006.161.08:13:19.69#ibcon#read 5, iclass 3, count 2 2006.161.08:13:19.69#ibcon#about to read 6, iclass 3, count 2 2006.161.08:13:19.69#ibcon#read 6, iclass 3, count 2 2006.161.08:13:19.69#ibcon#end of sib2, iclass 3, count 2 2006.161.08:13:19.69#ibcon#*after write, iclass 3, count 2 2006.161.08:13:19.69#ibcon#*before return 0, iclass 3, count 2 2006.161.08:13:19.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:19.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:19.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.08:13:19.69#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:19.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:19.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:19.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:19.81#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:13:19.81#ibcon#first serial, iclass 3, count 0 2006.161.08:13:19.81#ibcon#enter sib2, iclass 3, count 0 2006.161.08:13:19.81#ibcon#flushed, iclass 3, count 0 2006.161.08:13:19.81#ibcon#about to write, iclass 3, count 0 2006.161.08:13:19.81#ibcon#wrote, iclass 3, count 0 2006.161.08:13:19.81#ibcon#about to read 3, iclass 3, count 0 2006.161.08:13:19.83#ibcon#read 3, iclass 3, count 0 2006.161.08:13:19.83#ibcon#about to read 4, iclass 3, count 0 2006.161.08:13:19.83#ibcon#read 4, iclass 3, count 0 2006.161.08:13:19.83#ibcon#about to read 5, iclass 3, count 0 2006.161.08:13:19.83#ibcon#read 5, iclass 3, count 0 2006.161.08:13:19.83#ibcon#about to read 6, iclass 3, count 0 2006.161.08:13:19.83#ibcon#read 6, iclass 3, count 0 2006.161.08:13:19.83#ibcon#end of sib2, iclass 3, count 0 2006.161.08:13:19.83#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:13:19.83#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:13:19.83#ibcon#[25=USB\r\n] 2006.161.08:13:19.83#ibcon#*before write, iclass 3, count 0 2006.161.08:13:19.83#ibcon#enter sib2, iclass 3, count 0 2006.161.08:13:19.83#ibcon#flushed, iclass 3, count 0 2006.161.08:13:19.83#ibcon#about to write, iclass 3, count 0 2006.161.08:13:19.83#ibcon#wrote, iclass 3, count 0 2006.161.08:13:19.83#ibcon#about to read 3, iclass 3, count 0 2006.161.08:13:19.86#ibcon#read 3, iclass 3, count 0 2006.161.08:13:19.86#ibcon#about to read 4, iclass 3, count 0 2006.161.08:13:19.86#ibcon#read 4, iclass 3, count 0 2006.161.08:13:19.86#ibcon#about to read 5, iclass 3, count 0 2006.161.08:13:19.86#ibcon#read 5, iclass 3, count 0 2006.161.08:13:19.86#ibcon#about to read 6, iclass 3, count 0 2006.161.08:13:19.86#ibcon#read 6, iclass 3, count 0 2006.161.08:13:19.86#ibcon#end of sib2, iclass 3, count 0 2006.161.08:13:19.86#ibcon#*after write, iclass 3, count 0 2006.161.08:13:19.86#ibcon#*before return 0, iclass 3, count 0 2006.161.08:13:19.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:19.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:19.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:13:19.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:13:19.86$vc4f8/valo=3,672.99 2006.161.08:13:19.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.08:13:19.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.08:13:19.86#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:19.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:19.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:19.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:19.86#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:13:19.86#ibcon#first serial, iclass 5, count 0 2006.161.08:13:19.86#ibcon#enter sib2, iclass 5, count 0 2006.161.08:13:19.86#ibcon#flushed, iclass 5, count 0 2006.161.08:13:19.86#ibcon#about to write, iclass 5, count 0 2006.161.08:13:19.86#ibcon#wrote, iclass 5, count 0 2006.161.08:13:19.86#ibcon#about to read 3, iclass 5, count 0 2006.161.08:13:19.88#ibcon#read 3, iclass 5, count 0 2006.161.08:13:19.88#ibcon#about to read 4, iclass 5, count 0 2006.161.08:13:19.88#ibcon#read 4, iclass 5, count 0 2006.161.08:13:19.88#ibcon#about to read 5, iclass 5, count 0 2006.161.08:13:19.88#ibcon#read 5, iclass 5, count 0 2006.161.08:13:19.88#ibcon#about to read 6, iclass 5, count 0 2006.161.08:13:19.88#ibcon#read 6, iclass 5, count 0 2006.161.08:13:19.88#ibcon#end of sib2, iclass 5, count 0 2006.161.08:13:19.88#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:13:19.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:13:19.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:13:19.88#ibcon#*before write, iclass 5, count 0 2006.161.08:13:19.88#ibcon#enter sib2, iclass 5, count 0 2006.161.08:13:19.88#ibcon#flushed, iclass 5, count 0 2006.161.08:13:19.88#ibcon#about to write, iclass 5, count 0 2006.161.08:13:19.88#ibcon#wrote, iclass 5, count 0 2006.161.08:13:19.88#ibcon#about to read 3, iclass 5, count 0 2006.161.08:13:19.92#ibcon#read 3, iclass 5, count 0 2006.161.08:13:19.92#ibcon#about to read 4, iclass 5, count 0 2006.161.08:13:19.92#ibcon#read 4, iclass 5, count 0 2006.161.08:13:19.92#ibcon#about to read 5, iclass 5, count 0 2006.161.08:13:19.92#ibcon#read 5, iclass 5, count 0 2006.161.08:13:19.92#ibcon#about to read 6, iclass 5, count 0 2006.161.08:13:19.92#ibcon#read 6, iclass 5, count 0 2006.161.08:13:19.92#ibcon#end of sib2, iclass 5, count 0 2006.161.08:13:19.92#ibcon#*after write, iclass 5, count 0 2006.161.08:13:19.92#ibcon#*before return 0, iclass 5, count 0 2006.161.08:13:19.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:19.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:19.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:13:19.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:13:19.92$vc4f8/va=3,6 2006.161.08:13:19.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.08:13:19.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.08:13:19.92#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:19.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:19.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:19.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:19.99#ibcon#enter wrdev, iclass 7, count 2 2006.161.08:13:19.99#ibcon#first serial, iclass 7, count 2 2006.161.08:13:19.99#ibcon#enter sib2, iclass 7, count 2 2006.161.08:13:19.99#ibcon#flushed, iclass 7, count 2 2006.161.08:13:19.99#ibcon#about to write, iclass 7, count 2 2006.161.08:13:19.99#ibcon#wrote, iclass 7, count 2 2006.161.08:13:19.99#ibcon#about to read 3, iclass 7, count 2 2006.161.08:13:20.00#ibcon#read 3, iclass 7, count 2 2006.161.08:13:20.00#ibcon#about to read 4, iclass 7, count 2 2006.161.08:13:20.00#ibcon#read 4, iclass 7, count 2 2006.161.08:13:20.00#ibcon#about to read 5, iclass 7, count 2 2006.161.08:13:20.00#ibcon#read 5, iclass 7, count 2 2006.161.08:13:20.00#ibcon#about to read 6, iclass 7, count 2 2006.161.08:13:20.00#ibcon#read 6, iclass 7, count 2 2006.161.08:13:20.00#ibcon#end of sib2, iclass 7, count 2 2006.161.08:13:20.00#ibcon#*mode == 0, iclass 7, count 2 2006.161.08:13:20.00#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.08:13:20.00#ibcon#[25=AT03-06\r\n] 2006.161.08:13:20.00#ibcon#*before write, iclass 7, count 2 2006.161.08:13:20.00#ibcon#enter sib2, iclass 7, count 2 2006.161.08:13:20.00#ibcon#flushed, iclass 7, count 2 2006.161.08:13:20.00#ibcon#about to write, iclass 7, count 2 2006.161.08:13:20.00#ibcon#wrote, iclass 7, count 2 2006.161.08:13:20.00#ibcon#about to read 3, iclass 7, count 2 2006.161.08:13:20.03#ibcon#read 3, iclass 7, count 2 2006.161.08:13:20.03#ibcon#about to read 4, iclass 7, count 2 2006.161.08:13:20.03#ibcon#read 4, iclass 7, count 2 2006.161.08:13:20.03#ibcon#about to read 5, iclass 7, count 2 2006.161.08:13:20.03#ibcon#read 5, iclass 7, count 2 2006.161.08:13:20.03#ibcon#about to read 6, iclass 7, count 2 2006.161.08:13:20.03#ibcon#read 6, iclass 7, count 2 2006.161.08:13:20.03#ibcon#end of sib2, iclass 7, count 2 2006.161.08:13:20.03#ibcon#*after write, iclass 7, count 2 2006.161.08:13:20.03#ibcon#*before return 0, iclass 7, count 2 2006.161.08:13:20.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:20.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:20.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.08:13:20.03#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:20.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:20.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:20.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:20.15#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:13:20.15#ibcon#first serial, iclass 7, count 0 2006.161.08:13:20.15#ibcon#enter sib2, iclass 7, count 0 2006.161.08:13:20.15#ibcon#flushed, iclass 7, count 0 2006.161.08:13:20.15#ibcon#about to write, iclass 7, count 0 2006.161.08:13:20.15#ibcon#wrote, iclass 7, count 0 2006.161.08:13:20.15#ibcon#about to read 3, iclass 7, count 0 2006.161.08:13:20.17#ibcon#read 3, iclass 7, count 0 2006.161.08:13:20.17#ibcon#about to read 4, iclass 7, count 0 2006.161.08:13:20.17#ibcon#read 4, iclass 7, count 0 2006.161.08:13:20.17#ibcon#about to read 5, iclass 7, count 0 2006.161.08:13:20.17#ibcon#read 5, iclass 7, count 0 2006.161.08:13:20.17#ibcon#about to read 6, iclass 7, count 0 2006.161.08:13:20.17#ibcon#read 6, iclass 7, count 0 2006.161.08:13:20.17#ibcon#end of sib2, iclass 7, count 0 2006.161.08:13:20.17#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:13:20.17#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:13:20.17#ibcon#[25=USB\r\n] 2006.161.08:13:20.17#ibcon#*before write, iclass 7, count 0 2006.161.08:13:20.17#ibcon#enter sib2, iclass 7, count 0 2006.161.08:13:20.17#ibcon#flushed, iclass 7, count 0 2006.161.08:13:20.17#ibcon#about to write, iclass 7, count 0 2006.161.08:13:20.17#ibcon#wrote, iclass 7, count 0 2006.161.08:13:20.17#ibcon#about to read 3, iclass 7, count 0 2006.161.08:13:20.20#ibcon#read 3, iclass 7, count 0 2006.161.08:13:20.20#ibcon#about to read 4, iclass 7, count 0 2006.161.08:13:20.20#ibcon#read 4, iclass 7, count 0 2006.161.08:13:20.20#ibcon#about to read 5, iclass 7, count 0 2006.161.08:13:20.20#ibcon#read 5, iclass 7, count 0 2006.161.08:13:20.20#ibcon#about to read 6, iclass 7, count 0 2006.161.08:13:20.20#ibcon#read 6, iclass 7, count 0 2006.161.08:13:20.20#ibcon#end of sib2, iclass 7, count 0 2006.161.08:13:20.20#ibcon#*after write, iclass 7, count 0 2006.161.08:13:20.20#ibcon#*before return 0, iclass 7, count 0 2006.161.08:13:20.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:20.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:20.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:13:20.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:13:20.20$vc4f8/valo=4,832.99 2006.161.08:13:20.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.08:13:20.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.08:13:20.20#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:20.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:20.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:20.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:20.20#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:13:20.20#ibcon#first serial, iclass 11, count 0 2006.161.08:13:20.20#ibcon#enter sib2, iclass 11, count 0 2006.161.08:13:20.20#ibcon#flushed, iclass 11, count 0 2006.161.08:13:20.20#ibcon#about to write, iclass 11, count 0 2006.161.08:13:20.20#ibcon#wrote, iclass 11, count 0 2006.161.08:13:20.20#ibcon#about to read 3, iclass 11, count 0 2006.161.08:13:20.22#ibcon#read 3, iclass 11, count 0 2006.161.08:13:20.22#ibcon#about to read 4, iclass 11, count 0 2006.161.08:13:20.22#ibcon#read 4, iclass 11, count 0 2006.161.08:13:20.22#ibcon#about to read 5, iclass 11, count 0 2006.161.08:13:20.22#ibcon#read 5, iclass 11, count 0 2006.161.08:13:20.22#ibcon#about to read 6, iclass 11, count 0 2006.161.08:13:20.22#ibcon#read 6, iclass 11, count 0 2006.161.08:13:20.22#ibcon#end of sib2, iclass 11, count 0 2006.161.08:13:20.22#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:13:20.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:13:20.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:13:20.22#ibcon#*before write, iclass 11, count 0 2006.161.08:13:20.22#ibcon#enter sib2, iclass 11, count 0 2006.161.08:13:20.22#ibcon#flushed, iclass 11, count 0 2006.161.08:13:20.22#ibcon#about to write, iclass 11, count 0 2006.161.08:13:20.22#ibcon#wrote, iclass 11, count 0 2006.161.08:13:20.22#ibcon#about to read 3, iclass 11, count 0 2006.161.08:13:20.26#ibcon#read 3, iclass 11, count 0 2006.161.08:13:20.26#ibcon#about to read 4, iclass 11, count 0 2006.161.08:13:20.26#ibcon#read 4, iclass 11, count 0 2006.161.08:13:20.26#ibcon#about to read 5, iclass 11, count 0 2006.161.08:13:20.26#ibcon#read 5, iclass 11, count 0 2006.161.08:13:20.26#ibcon#about to read 6, iclass 11, count 0 2006.161.08:13:20.26#ibcon#read 6, iclass 11, count 0 2006.161.08:13:20.26#ibcon#end of sib2, iclass 11, count 0 2006.161.08:13:20.26#ibcon#*after write, iclass 11, count 0 2006.161.08:13:20.26#ibcon#*before return 0, iclass 11, count 0 2006.161.08:13:20.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:20.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:20.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:13:20.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:13:20.26$vc4f8/va=4,7 2006.161.08:13:20.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.08:13:20.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.08:13:20.26#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:20.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:20.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:20.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:20.32#ibcon#enter wrdev, iclass 13, count 2 2006.161.08:13:20.32#ibcon#first serial, iclass 13, count 2 2006.161.08:13:20.32#ibcon#enter sib2, iclass 13, count 2 2006.161.08:13:20.32#ibcon#flushed, iclass 13, count 2 2006.161.08:13:20.32#ibcon#about to write, iclass 13, count 2 2006.161.08:13:20.32#ibcon#wrote, iclass 13, count 2 2006.161.08:13:20.32#ibcon#about to read 3, iclass 13, count 2 2006.161.08:13:20.34#ibcon#read 3, iclass 13, count 2 2006.161.08:13:20.34#ibcon#about to read 4, iclass 13, count 2 2006.161.08:13:20.34#ibcon#read 4, iclass 13, count 2 2006.161.08:13:20.34#ibcon#about to read 5, iclass 13, count 2 2006.161.08:13:20.34#ibcon#read 5, iclass 13, count 2 2006.161.08:13:20.34#ibcon#about to read 6, iclass 13, count 2 2006.161.08:13:20.34#ibcon#read 6, iclass 13, count 2 2006.161.08:13:20.34#ibcon#end of sib2, iclass 13, count 2 2006.161.08:13:20.34#ibcon#*mode == 0, iclass 13, count 2 2006.161.08:13:20.34#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.08:13:20.34#ibcon#[25=AT04-07\r\n] 2006.161.08:13:20.34#ibcon#*before write, iclass 13, count 2 2006.161.08:13:20.34#ibcon#enter sib2, iclass 13, count 2 2006.161.08:13:20.34#ibcon#flushed, iclass 13, count 2 2006.161.08:13:20.34#ibcon#about to write, iclass 13, count 2 2006.161.08:13:20.34#ibcon#wrote, iclass 13, count 2 2006.161.08:13:20.34#ibcon#about to read 3, iclass 13, count 2 2006.161.08:13:20.37#ibcon#read 3, iclass 13, count 2 2006.161.08:13:20.37#ibcon#about to read 4, iclass 13, count 2 2006.161.08:13:20.37#ibcon#read 4, iclass 13, count 2 2006.161.08:13:20.37#ibcon#about to read 5, iclass 13, count 2 2006.161.08:13:20.37#ibcon#read 5, iclass 13, count 2 2006.161.08:13:20.37#ibcon#about to read 6, iclass 13, count 2 2006.161.08:13:20.37#ibcon#read 6, iclass 13, count 2 2006.161.08:13:20.37#ibcon#end of sib2, iclass 13, count 2 2006.161.08:13:20.37#ibcon#*after write, iclass 13, count 2 2006.161.08:13:20.37#ibcon#*before return 0, iclass 13, count 2 2006.161.08:13:20.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:20.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:20.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.08:13:20.37#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:20.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:20.46#abcon#<5=/05 2.6 4.3 24.00 871002.5\r\n> 2006.161.08:13:20.48#abcon#{5=INTERFACE CLEAR} 2006.161.08:13:20.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:20.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:20.50#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:13:20.50#ibcon#first serial, iclass 13, count 0 2006.161.08:13:20.50#ibcon#enter sib2, iclass 13, count 0 2006.161.08:13:20.50#ibcon#flushed, iclass 13, count 0 2006.161.08:13:20.50#ibcon#about to write, iclass 13, count 0 2006.161.08:13:20.50#ibcon#wrote, iclass 13, count 0 2006.161.08:13:20.50#ibcon#about to read 3, iclass 13, count 0 2006.161.08:13:20.52#ibcon#read 3, iclass 13, count 0 2006.161.08:13:20.52#ibcon#about to read 4, iclass 13, count 0 2006.161.08:13:20.52#ibcon#read 4, iclass 13, count 0 2006.161.08:13:20.52#ibcon#about to read 5, iclass 13, count 0 2006.161.08:13:20.52#ibcon#read 5, iclass 13, count 0 2006.161.08:13:20.52#ibcon#about to read 6, iclass 13, count 0 2006.161.08:13:20.52#ibcon#read 6, iclass 13, count 0 2006.161.08:13:20.52#ibcon#end of sib2, iclass 13, count 0 2006.161.08:13:20.52#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:13:20.52#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:13:20.52#ibcon#[25=USB\r\n] 2006.161.08:13:20.52#ibcon#*before write, iclass 13, count 0 2006.161.08:13:20.52#ibcon#enter sib2, iclass 13, count 0 2006.161.08:13:20.52#ibcon#flushed, iclass 13, count 0 2006.161.08:13:20.52#ibcon#about to write, iclass 13, count 0 2006.161.08:13:20.52#ibcon#wrote, iclass 13, count 0 2006.161.08:13:20.52#ibcon#about to read 3, iclass 13, count 0 2006.161.08:13:20.54#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:13:20.55#ibcon#read 3, iclass 13, count 0 2006.161.08:13:20.55#ibcon#about to read 4, iclass 13, count 0 2006.161.08:13:20.55#ibcon#read 4, iclass 13, count 0 2006.161.08:13:20.55#ibcon#about to read 5, iclass 13, count 0 2006.161.08:13:20.55#ibcon#read 5, iclass 13, count 0 2006.161.08:13:20.55#ibcon#about to read 6, iclass 13, count 0 2006.161.08:13:20.55#ibcon#read 6, iclass 13, count 0 2006.161.08:13:20.55#ibcon#end of sib2, iclass 13, count 0 2006.161.08:13:20.55#ibcon#*after write, iclass 13, count 0 2006.161.08:13:20.55#ibcon#*before return 0, iclass 13, count 0 2006.161.08:13:20.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:20.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:20.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:13:20.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:13:20.55$vc4f8/valo=5,652.99 2006.161.08:13:20.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:13:20.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:13:20.55#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:20.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:20.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:20.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:20.55#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:13:20.55#ibcon#first serial, iclass 19, count 0 2006.161.08:13:20.55#ibcon#enter sib2, iclass 19, count 0 2006.161.08:13:20.55#ibcon#flushed, iclass 19, count 0 2006.161.08:13:20.55#ibcon#about to write, iclass 19, count 0 2006.161.08:13:20.55#ibcon#wrote, iclass 19, count 0 2006.161.08:13:20.55#ibcon#about to read 3, iclass 19, count 0 2006.161.08:13:20.57#ibcon#read 3, iclass 19, count 0 2006.161.08:13:20.57#ibcon#about to read 4, iclass 19, count 0 2006.161.08:13:20.57#ibcon#read 4, iclass 19, count 0 2006.161.08:13:20.57#ibcon#about to read 5, iclass 19, count 0 2006.161.08:13:20.57#ibcon#read 5, iclass 19, count 0 2006.161.08:13:20.57#ibcon#about to read 6, iclass 19, count 0 2006.161.08:13:20.57#ibcon#read 6, iclass 19, count 0 2006.161.08:13:20.57#ibcon#end of sib2, iclass 19, count 0 2006.161.08:13:20.57#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:13:20.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:13:20.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:13:20.57#ibcon#*before write, iclass 19, count 0 2006.161.08:13:20.57#ibcon#enter sib2, iclass 19, count 0 2006.161.08:13:20.57#ibcon#flushed, iclass 19, count 0 2006.161.08:13:20.57#ibcon#about to write, iclass 19, count 0 2006.161.08:13:20.57#ibcon#wrote, iclass 19, count 0 2006.161.08:13:20.57#ibcon#about to read 3, iclass 19, count 0 2006.161.08:13:20.61#ibcon#read 3, iclass 19, count 0 2006.161.08:13:20.61#ibcon#about to read 4, iclass 19, count 0 2006.161.08:13:20.61#ibcon#read 4, iclass 19, count 0 2006.161.08:13:20.61#ibcon#about to read 5, iclass 19, count 0 2006.161.08:13:20.61#ibcon#read 5, iclass 19, count 0 2006.161.08:13:20.61#ibcon#about to read 6, iclass 19, count 0 2006.161.08:13:20.61#ibcon#read 6, iclass 19, count 0 2006.161.08:13:20.61#ibcon#end of sib2, iclass 19, count 0 2006.161.08:13:20.61#ibcon#*after write, iclass 19, count 0 2006.161.08:13:20.61#ibcon#*before return 0, iclass 19, count 0 2006.161.08:13:20.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:20.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:20.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:13:20.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:13:20.61$vc4f8/va=5,7 2006.161.08:13:20.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:13:20.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:13:20.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:20.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:20.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:20.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:20.67#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:13:20.67#ibcon#first serial, iclass 21, count 2 2006.161.08:13:20.67#ibcon#enter sib2, iclass 21, count 2 2006.161.08:13:20.67#ibcon#flushed, iclass 21, count 2 2006.161.08:13:20.67#ibcon#about to write, iclass 21, count 2 2006.161.08:13:20.67#ibcon#wrote, iclass 21, count 2 2006.161.08:13:20.67#ibcon#about to read 3, iclass 21, count 2 2006.161.08:13:20.69#ibcon#read 3, iclass 21, count 2 2006.161.08:13:20.69#ibcon#about to read 4, iclass 21, count 2 2006.161.08:13:20.69#ibcon#read 4, iclass 21, count 2 2006.161.08:13:20.69#ibcon#about to read 5, iclass 21, count 2 2006.161.08:13:20.69#ibcon#read 5, iclass 21, count 2 2006.161.08:13:20.69#ibcon#about to read 6, iclass 21, count 2 2006.161.08:13:20.69#ibcon#read 6, iclass 21, count 2 2006.161.08:13:20.69#ibcon#end of sib2, iclass 21, count 2 2006.161.08:13:20.69#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:13:20.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:13:20.69#ibcon#[25=AT05-07\r\n] 2006.161.08:13:20.69#ibcon#*before write, iclass 21, count 2 2006.161.08:13:20.69#ibcon#enter sib2, iclass 21, count 2 2006.161.08:13:20.69#ibcon#flushed, iclass 21, count 2 2006.161.08:13:20.69#ibcon#about to write, iclass 21, count 2 2006.161.08:13:20.69#ibcon#wrote, iclass 21, count 2 2006.161.08:13:20.69#ibcon#about to read 3, iclass 21, count 2 2006.161.08:13:20.72#ibcon#read 3, iclass 21, count 2 2006.161.08:13:20.72#ibcon#about to read 4, iclass 21, count 2 2006.161.08:13:20.72#ibcon#read 4, iclass 21, count 2 2006.161.08:13:20.72#ibcon#about to read 5, iclass 21, count 2 2006.161.08:13:20.72#ibcon#read 5, iclass 21, count 2 2006.161.08:13:20.72#ibcon#about to read 6, iclass 21, count 2 2006.161.08:13:20.72#ibcon#read 6, iclass 21, count 2 2006.161.08:13:20.72#ibcon#end of sib2, iclass 21, count 2 2006.161.08:13:20.72#ibcon#*after write, iclass 21, count 2 2006.161.08:13:20.72#ibcon#*before return 0, iclass 21, count 2 2006.161.08:13:20.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:20.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:20.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:13:20.72#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:20.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:20.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:20.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:20.84#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:13:20.84#ibcon#first serial, iclass 21, count 0 2006.161.08:13:20.84#ibcon#enter sib2, iclass 21, count 0 2006.161.08:13:20.84#ibcon#flushed, iclass 21, count 0 2006.161.08:13:20.84#ibcon#about to write, iclass 21, count 0 2006.161.08:13:20.84#ibcon#wrote, iclass 21, count 0 2006.161.08:13:20.84#ibcon#about to read 3, iclass 21, count 0 2006.161.08:13:20.86#ibcon#read 3, iclass 21, count 0 2006.161.08:13:20.86#ibcon#about to read 4, iclass 21, count 0 2006.161.08:13:20.86#ibcon#read 4, iclass 21, count 0 2006.161.08:13:20.86#ibcon#about to read 5, iclass 21, count 0 2006.161.08:13:20.86#ibcon#read 5, iclass 21, count 0 2006.161.08:13:20.86#ibcon#about to read 6, iclass 21, count 0 2006.161.08:13:20.86#ibcon#read 6, iclass 21, count 0 2006.161.08:13:20.86#ibcon#end of sib2, iclass 21, count 0 2006.161.08:13:20.86#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:13:20.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:13:20.86#ibcon#[25=USB\r\n] 2006.161.08:13:20.86#ibcon#*before write, iclass 21, count 0 2006.161.08:13:20.86#ibcon#enter sib2, iclass 21, count 0 2006.161.08:13:20.86#ibcon#flushed, iclass 21, count 0 2006.161.08:13:20.86#ibcon#about to write, iclass 21, count 0 2006.161.08:13:20.86#ibcon#wrote, iclass 21, count 0 2006.161.08:13:20.86#ibcon#about to read 3, iclass 21, count 0 2006.161.08:13:20.89#ibcon#read 3, iclass 21, count 0 2006.161.08:13:20.89#ibcon#about to read 4, iclass 21, count 0 2006.161.08:13:20.89#ibcon#read 4, iclass 21, count 0 2006.161.08:13:20.89#ibcon#about to read 5, iclass 21, count 0 2006.161.08:13:20.89#ibcon#read 5, iclass 21, count 0 2006.161.08:13:20.89#ibcon#about to read 6, iclass 21, count 0 2006.161.08:13:20.89#ibcon#read 6, iclass 21, count 0 2006.161.08:13:20.89#ibcon#end of sib2, iclass 21, count 0 2006.161.08:13:20.89#ibcon#*after write, iclass 21, count 0 2006.161.08:13:20.89#ibcon#*before return 0, iclass 21, count 0 2006.161.08:13:20.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:20.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:20.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:13:20.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:13:20.89$vc4f8/valo=6,772.99 2006.161.08:13:20.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:13:20.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:13:20.89#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:20.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:20.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:20.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:20.89#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:13:20.89#ibcon#first serial, iclass 23, count 0 2006.161.08:13:20.89#ibcon#enter sib2, iclass 23, count 0 2006.161.08:13:20.89#ibcon#flushed, iclass 23, count 0 2006.161.08:13:20.89#ibcon#about to write, iclass 23, count 0 2006.161.08:13:20.89#ibcon#wrote, iclass 23, count 0 2006.161.08:13:20.89#ibcon#about to read 3, iclass 23, count 0 2006.161.08:13:20.91#ibcon#read 3, iclass 23, count 0 2006.161.08:13:20.91#ibcon#about to read 4, iclass 23, count 0 2006.161.08:13:20.91#ibcon#read 4, iclass 23, count 0 2006.161.08:13:20.91#ibcon#about to read 5, iclass 23, count 0 2006.161.08:13:20.91#ibcon#read 5, iclass 23, count 0 2006.161.08:13:20.91#ibcon#about to read 6, iclass 23, count 0 2006.161.08:13:20.91#ibcon#read 6, iclass 23, count 0 2006.161.08:13:20.91#ibcon#end of sib2, iclass 23, count 0 2006.161.08:13:20.91#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:13:20.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:13:20.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:13:20.91#ibcon#*before write, iclass 23, count 0 2006.161.08:13:20.91#ibcon#enter sib2, iclass 23, count 0 2006.161.08:13:20.91#ibcon#flushed, iclass 23, count 0 2006.161.08:13:20.91#ibcon#about to write, iclass 23, count 0 2006.161.08:13:20.91#ibcon#wrote, iclass 23, count 0 2006.161.08:13:20.91#ibcon#about to read 3, iclass 23, count 0 2006.161.08:13:20.95#ibcon#read 3, iclass 23, count 0 2006.161.08:13:20.95#ibcon#about to read 4, iclass 23, count 0 2006.161.08:13:20.95#ibcon#read 4, iclass 23, count 0 2006.161.08:13:20.95#ibcon#about to read 5, iclass 23, count 0 2006.161.08:13:20.95#ibcon#read 5, iclass 23, count 0 2006.161.08:13:20.95#ibcon#about to read 6, iclass 23, count 0 2006.161.08:13:20.95#ibcon#read 6, iclass 23, count 0 2006.161.08:13:20.95#ibcon#end of sib2, iclass 23, count 0 2006.161.08:13:20.95#ibcon#*after write, iclass 23, count 0 2006.161.08:13:20.95#ibcon#*before return 0, iclass 23, count 0 2006.161.08:13:20.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:20.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:20.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:13:20.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:13:20.95$vc4f8/va=6,6 2006.161.08:13:20.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.08:13:20.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.08:13:20.95#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:20.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:21.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:21.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:21.01#ibcon#enter wrdev, iclass 25, count 2 2006.161.08:13:21.01#ibcon#first serial, iclass 25, count 2 2006.161.08:13:21.01#ibcon#enter sib2, iclass 25, count 2 2006.161.08:13:21.01#ibcon#flushed, iclass 25, count 2 2006.161.08:13:21.01#ibcon#about to write, iclass 25, count 2 2006.161.08:13:21.01#ibcon#wrote, iclass 25, count 2 2006.161.08:13:21.01#ibcon#about to read 3, iclass 25, count 2 2006.161.08:13:21.03#ibcon#read 3, iclass 25, count 2 2006.161.08:13:21.03#ibcon#about to read 4, iclass 25, count 2 2006.161.08:13:21.03#ibcon#read 4, iclass 25, count 2 2006.161.08:13:21.03#ibcon#about to read 5, iclass 25, count 2 2006.161.08:13:21.03#ibcon#read 5, iclass 25, count 2 2006.161.08:13:21.03#ibcon#about to read 6, iclass 25, count 2 2006.161.08:13:21.03#ibcon#read 6, iclass 25, count 2 2006.161.08:13:21.03#ibcon#end of sib2, iclass 25, count 2 2006.161.08:13:21.03#ibcon#*mode == 0, iclass 25, count 2 2006.161.08:13:21.03#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.08:13:21.03#ibcon#[25=AT06-06\r\n] 2006.161.08:13:21.03#ibcon#*before write, iclass 25, count 2 2006.161.08:13:21.03#ibcon#enter sib2, iclass 25, count 2 2006.161.08:13:21.03#ibcon#flushed, iclass 25, count 2 2006.161.08:13:21.03#ibcon#about to write, iclass 25, count 2 2006.161.08:13:21.03#ibcon#wrote, iclass 25, count 2 2006.161.08:13:21.03#ibcon#about to read 3, iclass 25, count 2 2006.161.08:13:21.06#ibcon#read 3, iclass 25, count 2 2006.161.08:13:21.06#ibcon#about to read 4, iclass 25, count 2 2006.161.08:13:21.06#ibcon#read 4, iclass 25, count 2 2006.161.08:13:21.06#ibcon#about to read 5, iclass 25, count 2 2006.161.08:13:21.06#ibcon#read 5, iclass 25, count 2 2006.161.08:13:21.06#ibcon#about to read 6, iclass 25, count 2 2006.161.08:13:21.06#ibcon#read 6, iclass 25, count 2 2006.161.08:13:21.06#ibcon#end of sib2, iclass 25, count 2 2006.161.08:13:21.06#ibcon#*after write, iclass 25, count 2 2006.161.08:13:21.06#ibcon#*before return 0, iclass 25, count 2 2006.161.08:13:21.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:21.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:21.06#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.08:13:21.06#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:21.06#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:13:21.18#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:13:21.18#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:13:21.18#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:13:21.18#ibcon#first serial, iclass 25, count 0 2006.161.08:13:21.18#ibcon#enter sib2, iclass 25, count 0 2006.161.08:13:21.18#ibcon#flushed, iclass 25, count 0 2006.161.08:13:21.18#ibcon#about to write, iclass 25, count 0 2006.161.08:13:21.18#ibcon#wrote, iclass 25, count 0 2006.161.08:13:21.18#ibcon#about to read 3, iclass 25, count 0 2006.161.08:13:21.20#ibcon#read 3, iclass 25, count 0 2006.161.08:13:21.20#ibcon#about to read 4, iclass 25, count 0 2006.161.08:13:21.20#ibcon#read 4, iclass 25, count 0 2006.161.08:13:21.20#ibcon#about to read 5, iclass 25, count 0 2006.161.08:13:21.20#ibcon#read 5, iclass 25, count 0 2006.161.08:13:21.20#ibcon#about to read 6, iclass 25, count 0 2006.161.08:13:21.20#ibcon#read 6, iclass 25, count 0 2006.161.08:13:21.20#ibcon#end of sib2, iclass 25, count 0 2006.161.08:13:21.20#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:13:21.20#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:13:21.20#ibcon#[25=USB\r\n] 2006.161.08:13:21.20#ibcon#*before write, iclass 25, count 0 2006.161.08:13:21.20#ibcon#enter sib2, iclass 25, count 0 2006.161.08:13:21.20#ibcon#flushed, iclass 25, count 0 2006.161.08:13:21.20#ibcon#about to write, iclass 25, count 0 2006.161.08:13:21.20#ibcon#wrote, iclass 25, count 0 2006.161.08:13:21.20#ibcon#about to read 3, iclass 25, count 0 2006.161.08:13:21.23#ibcon#read 3, iclass 25, count 0 2006.161.08:13:21.23#ibcon#about to read 4, iclass 25, count 0 2006.161.08:13:21.23#ibcon#read 4, iclass 25, count 0 2006.161.08:13:21.23#ibcon#about to read 5, iclass 25, count 0 2006.161.08:13:21.23#ibcon#read 5, iclass 25, count 0 2006.161.08:13:21.23#ibcon#about to read 6, iclass 25, count 0 2006.161.08:13:21.23#ibcon#read 6, iclass 25, count 0 2006.161.08:13:21.23#ibcon#end of sib2, iclass 25, count 0 2006.161.08:13:21.23#ibcon#*after write, iclass 25, count 0 2006.161.08:13:21.23#ibcon#*before return 0, iclass 25, count 0 2006.161.08:13:21.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:13:21.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:13:21.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:13:21.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:13:21.23$vc4f8/valo=7,832.99 2006.161.08:13:21.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.08:13:21.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.08:13:21.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:21.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:13:21.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:13:21.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:13:21.23#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:13:21.23#ibcon#first serial, iclass 27, count 0 2006.161.08:13:21.23#ibcon#enter sib2, iclass 27, count 0 2006.161.08:13:21.23#ibcon#flushed, iclass 27, count 0 2006.161.08:13:21.23#ibcon#about to write, iclass 27, count 0 2006.161.08:13:21.23#ibcon#wrote, iclass 27, count 0 2006.161.08:13:21.23#ibcon#about to read 3, iclass 27, count 0 2006.161.08:13:21.25#ibcon#read 3, iclass 27, count 0 2006.161.08:13:21.25#ibcon#about to read 4, iclass 27, count 0 2006.161.08:13:21.25#ibcon#read 4, iclass 27, count 0 2006.161.08:13:21.25#ibcon#about to read 5, iclass 27, count 0 2006.161.08:13:21.25#ibcon#read 5, iclass 27, count 0 2006.161.08:13:21.25#ibcon#about to read 6, iclass 27, count 0 2006.161.08:13:21.25#ibcon#read 6, iclass 27, count 0 2006.161.08:13:21.25#ibcon#end of sib2, iclass 27, count 0 2006.161.08:13:21.25#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:13:21.25#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:13:21.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:13:21.25#ibcon#*before write, iclass 27, count 0 2006.161.08:13:21.25#ibcon#enter sib2, iclass 27, count 0 2006.161.08:13:21.25#ibcon#flushed, iclass 27, count 0 2006.161.08:13:21.25#ibcon#about to write, iclass 27, count 0 2006.161.08:13:21.25#ibcon#wrote, iclass 27, count 0 2006.161.08:13:21.25#ibcon#about to read 3, iclass 27, count 0 2006.161.08:13:21.29#ibcon#read 3, iclass 27, count 0 2006.161.08:13:21.29#ibcon#about to read 4, iclass 27, count 0 2006.161.08:13:21.29#ibcon#read 4, iclass 27, count 0 2006.161.08:13:21.29#ibcon#about to read 5, iclass 27, count 0 2006.161.08:13:21.29#ibcon#read 5, iclass 27, count 0 2006.161.08:13:21.29#ibcon#about to read 6, iclass 27, count 0 2006.161.08:13:21.29#ibcon#read 6, iclass 27, count 0 2006.161.08:13:21.29#ibcon#end of sib2, iclass 27, count 0 2006.161.08:13:21.29#ibcon#*after write, iclass 27, count 0 2006.161.08:13:21.29#ibcon#*before return 0, iclass 27, count 0 2006.161.08:13:21.29#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:13:21.29#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:13:21.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:13:21.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:13:21.29$vc4f8/va=7,6 2006.161.08:13:21.29#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.08:13:21.29#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.08:13:21.29#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:21.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:13:21.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:13:21.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:13:21.35#ibcon#enter wrdev, iclass 29, count 2 2006.161.08:13:21.35#ibcon#first serial, iclass 29, count 2 2006.161.08:13:21.35#ibcon#enter sib2, iclass 29, count 2 2006.161.08:13:21.35#ibcon#flushed, iclass 29, count 2 2006.161.08:13:21.35#ibcon#about to write, iclass 29, count 2 2006.161.08:13:21.35#ibcon#wrote, iclass 29, count 2 2006.161.08:13:21.35#ibcon#about to read 3, iclass 29, count 2 2006.161.08:13:21.37#ibcon#read 3, iclass 29, count 2 2006.161.08:13:21.37#ibcon#about to read 4, iclass 29, count 2 2006.161.08:13:21.37#ibcon#read 4, iclass 29, count 2 2006.161.08:13:21.37#ibcon#about to read 5, iclass 29, count 2 2006.161.08:13:21.37#ibcon#read 5, iclass 29, count 2 2006.161.08:13:21.37#ibcon#about to read 6, iclass 29, count 2 2006.161.08:13:21.37#ibcon#read 6, iclass 29, count 2 2006.161.08:13:21.37#ibcon#end of sib2, iclass 29, count 2 2006.161.08:13:21.37#ibcon#*mode == 0, iclass 29, count 2 2006.161.08:13:21.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.08:13:21.37#ibcon#[25=AT07-06\r\n] 2006.161.08:13:21.37#ibcon#*before write, iclass 29, count 2 2006.161.08:13:21.37#ibcon#enter sib2, iclass 29, count 2 2006.161.08:13:21.37#ibcon#flushed, iclass 29, count 2 2006.161.08:13:21.37#ibcon#about to write, iclass 29, count 2 2006.161.08:13:21.37#ibcon#wrote, iclass 29, count 2 2006.161.08:13:21.37#ibcon#about to read 3, iclass 29, count 2 2006.161.08:13:21.40#ibcon#read 3, iclass 29, count 2 2006.161.08:13:21.40#ibcon#about to read 4, iclass 29, count 2 2006.161.08:13:21.40#ibcon#read 4, iclass 29, count 2 2006.161.08:13:21.40#ibcon#about to read 5, iclass 29, count 2 2006.161.08:13:21.40#ibcon#read 5, iclass 29, count 2 2006.161.08:13:21.40#ibcon#about to read 6, iclass 29, count 2 2006.161.08:13:21.40#ibcon#read 6, iclass 29, count 2 2006.161.08:13:21.40#ibcon#end of sib2, iclass 29, count 2 2006.161.08:13:21.40#ibcon#*after write, iclass 29, count 2 2006.161.08:13:21.40#ibcon#*before return 0, iclass 29, count 2 2006.161.08:13:21.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:13:21.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:13:21.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.08:13:21.40#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:21.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:13:21.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:13:21.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:13:21.52#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:13:21.52#ibcon#first serial, iclass 29, count 0 2006.161.08:13:21.52#ibcon#enter sib2, iclass 29, count 0 2006.161.08:13:21.52#ibcon#flushed, iclass 29, count 0 2006.161.08:13:21.52#ibcon#about to write, iclass 29, count 0 2006.161.08:13:21.52#ibcon#wrote, iclass 29, count 0 2006.161.08:13:21.52#ibcon#about to read 3, iclass 29, count 0 2006.161.08:13:21.54#ibcon#read 3, iclass 29, count 0 2006.161.08:13:21.54#ibcon#about to read 4, iclass 29, count 0 2006.161.08:13:21.54#ibcon#read 4, iclass 29, count 0 2006.161.08:13:21.54#ibcon#about to read 5, iclass 29, count 0 2006.161.08:13:21.54#ibcon#read 5, iclass 29, count 0 2006.161.08:13:21.54#ibcon#about to read 6, iclass 29, count 0 2006.161.08:13:21.54#ibcon#read 6, iclass 29, count 0 2006.161.08:13:21.54#ibcon#end of sib2, iclass 29, count 0 2006.161.08:13:21.54#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:13:21.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:13:21.54#ibcon#[25=USB\r\n] 2006.161.08:13:21.54#ibcon#*before write, iclass 29, count 0 2006.161.08:13:21.54#ibcon#enter sib2, iclass 29, count 0 2006.161.08:13:21.54#ibcon#flushed, iclass 29, count 0 2006.161.08:13:21.54#ibcon#about to write, iclass 29, count 0 2006.161.08:13:21.54#ibcon#wrote, iclass 29, count 0 2006.161.08:13:21.54#ibcon#about to read 3, iclass 29, count 0 2006.161.08:13:21.57#ibcon#read 3, iclass 29, count 0 2006.161.08:13:21.57#ibcon#about to read 4, iclass 29, count 0 2006.161.08:13:21.57#ibcon#read 4, iclass 29, count 0 2006.161.08:13:21.57#ibcon#about to read 5, iclass 29, count 0 2006.161.08:13:21.57#ibcon#read 5, iclass 29, count 0 2006.161.08:13:21.57#ibcon#about to read 6, iclass 29, count 0 2006.161.08:13:21.57#ibcon#read 6, iclass 29, count 0 2006.161.08:13:21.57#ibcon#end of sib2, iclass 29, count 0 2006.161.08:13:21.57#ibcon#*after write, iclass 29, count 0 2006.161.08:13:21.57#ibcon#*before return 0, iclass 29, count 0 2006.161.08:13:21.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:13:21.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:13:21.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:13:21.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:13:21.57$vc4f8/valo=8,852.99 2006.161.08:13:21.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:13:21.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:13:21.57#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:21.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:13:21.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:13:21.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:13:21.57#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:13:21.57#ibcon#first serial, iclass 31, count 0 2006.161.08:13:21.57#ibcon#enter sib2, iclass 31, count 0 2006.161.08:13:21.57#ibcon#flushed, iclass 31, count 0 2006.161.08:13:21.57#ibcon#about to write, iclass 31, count 0 2006.161.08:13:21.57#ibcon#wrote, iclass 31, count 0 2006.161.08:13:21.57#ibcon#about to read 3, iclass 31, count 0 2006.161.08:13:21.59#ibcon#read 3, iclass 31, count 0 2006.161.08:13:21.59#ibcon#about to read 4, iclass 31, count 0 2006.161.08:13:21.59#ibcon#read 4, iclass 31, count 0 2006.161.08:13:21.59#ibcon#about to read 5, iclass 31, count 0 2006.161.08:13:21.59#ibcon#read 5, iclass 31, count 0 2006.161.08:13:21.59#ibcon#about to read 6, iclass 31, count 0 2006.161.08:13:21.59#ibcon#read 6, iclass 31, count 0 2006.161.08:13:21.59#ibcon#end of sib2, iclass 31, count 0 2006.161.08:13:21.59#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:13:21.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:13:21.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:13:21.59#ibcon#*before write, iclass 31, count 0 2006.161.08:13:21.59#ibcon#enter sib2, iclass 31, count 0 2006.161.08:13:21.59#ibcon#flushed, iclass 31, count 0 2006.161.08:13:21.59#ibcon#about to write, iclass 31, count 0 2006.161.08:13:21.59#ibcon#wrote, iclass 31, count 0 2006.161.08:13:21.59#ibcon#about to read 3, iclass 31, count 0 2006.161.08:13:21.63#ibcon#read 3, iclass 31, count 0 2006.161.08:13:21.63#ibcon#about to read 4, iclass 31, count 0 2006.161.08:13:21.63#ibcon#read 4, iclass 31, count 0 2006.161.08:13:21.63#ibcon#about to read 5, iclass 31, count 0 2006.161.08:13:21.63#ibcon#read 5, iclass 31, count 0 2006.161.08:13:21.63#ibcon#about to read 6, iclass 31, count 0 2006.161.08:13:21.63#ibcon#read 6, iclass 31, count 0 2006.161.08:13:21.63#ibcon#end of sib2, iclass 31, count 0 2006.161.08:13:21.63#ibcon#*after write, iclass 31, count 0 2006.161.08:13:21.63#ibcon#*before return 0, iclass 31, count 0 2006.161.08:13:21.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:13:21.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:13:21.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:13:21.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:13:21.63$vc4f8/va=8,7 2006.161.08:13:21.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.08:13:21.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.08:13:21.63#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:21.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:13:21.69#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:13:21.69#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:13:21.69#ibcon#enter wrdev, iclass 33, count 2 2006.161.08:13:21.69#ibcon#first serial, iclass 33, count 2 2006.161.08:13:21.69#ibcon#enter sib2, iclass 33, count 2 2006.161.08:13:21.69#ibcon#flushed, iclass 33, count 2 2006.161.08:13:21.69#ibcon#about to write, iclass 33, count 2 2006.161.08:13:21.69#ibcon#wrote, iclass 33, count 2 2006.161.08:13:21.69#ibcon#about to read 3, iclass 33, count 2 2006.161.08:13:21.71#ibcon#read 3, iclass 33, count 2 2006.161.08:13:21.71#ibcon#about to read 4, iclass 33, count 2 2006.161.08:13:21.71#ibcon#read 4, iclass 33, count 2 2006.161.08:13:21.71#ibcon#about to read 5, iclass 33, count 2 2006.161.08:13:21.71#ibcon#read 5, iclass 33, count 2 2006.161.08:13:21.71#ibcon#about to read 6, iclass 33, count 2 2006.161.08:13:21.71#ibcon#read 6, iclass 33, count 2 2006.161.08:13:21.71#ibcon#end of sib2, iclass 33, count 2 2006.161.08:13:21.71#ibcon#*mode == 0, iclass 33, count 2 2006.161.08:13:21.71#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.08:13:21.71#ibcon#[25=AT08-07\r\n] 2006.161.08:13:21.71#ibcon#*before write, iclass 33, count 2 2006.161.08:13:21.71#ibcon#enter sib2, iclass 33, count 2 2006.161.08:13:21.71#ibcon#flushed, iclass 33, count 2 2006.161.08:13:21.71#ibcon#about to write, iclass 33, count 2 2006.161.08:13:21.71#ibcon#wrote, iclass 33, count 2 2006.161.08:13:21.71#ibcon#about to read 3, iclass 33, count 2 2006.161.08:13:21.74#ibcon#read 3, iclass 33, count 2 2006.161.08:13:21.74#ibcon#about to read 4, iclass 33, count 2 2006.161.08:13:21.74#ibcon#read 4, iclass 33, count 2 2006.161.08:13:21.74#ibcon#about to read 5, iclass 33, count 2 2006.161.08:13:21.74#ibcon#read 5, iclass 33, count 2 2006.161.08:13:21.74#ibcon#about to read 6, iclass 33, count 2 2006.161.08:13:21.74#ibcon#read 6, iclass 33, count 2 2006.161.08:13:21.74#ibcon#end of sib2, iclass 33, count 2 2006.161.08:13:21.74#ibcon#*after write, iclass 33, count 2 2006.161.08:13:21.74#ibcon#*before return 0, iclass 33, count 2 2006.161.08:13:21.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:13:21.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:13:21.74#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.08:13:21.74#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:21.74#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:13:21.86#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:13:21.86#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:13:21.86#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:13:21.86#ibcon#first serial, iclass 33, count 0 2006.161.08:13:21.86#ibcon#enter sib2, iclass 33, count 0 2006.161.08:13:21.86#ibcon#flushed, iclass 33, count 0 2006.161.08:13:21.86#ibcon#about to write, iclass 33, count 0 2006.161.08:13:21.86#ibcon#wrote, iclass 33, count 0 2006.161.08:13:21.86#ibcon#about to read 3, iclass 33, count 0 2006.161.08:13:21.88#ibcon#read 3, iclass 33, count 0 2006.161.08:13:21.88#ibcon#about to read 4, iclass 33, count 0 2006.161.08:13:21.88#ibcon#read 4, iclass 33, count 0 2006.161.08:13:21.88#ibcon#about to read 5, iclass 33, count 0 2006.161.08:13:21.88#ibcon#read 5, iclass 33, count 0 2006.161.08:13:21.88#ibcon#about to read 6, iclass 33, count 0 2006.161.08:13:21.88#ibcon#read 6, iclass 33, count 0 2006.161.08:13:21.88#ibcon#end of sib2, iclass 33, count 0 2006.161.08:13:21.88#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:13:21.88#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:13:21.88#ibcon#[25=USB\r\n] 2006.161.08:13:21.88#ibcon#*before write, iclass 33, count 0 2006.161.08:13:21.88#ibcon#enter sib2, iclass 33, count 0 2006.161.08:13:21.88#ibcon#flushed, iclass 33, count 0 2006.161.08:13:21.88#ibcon#about to write, iclass 33, count 0 2006.161.08:13:21.88#ibcon#wrote, iclass 33, count 0 2006.161.08:13:21.88#ibcon#about to read 3, iclass 33, count 0 2006.161.08:13:21.91#ibcon#read 3, iclass 33, count 0 2006.161.08:13:21.91#ibcon#about to read 4, iclass 33, count 0 2006.161.08:13:21.91#ibcon#read 4, iclass 33, count 0 2006.161.08:13:21.91#ibcon#about to read 5, iclass 33, count 0 2006.161.08:13:21.91#ibcon#read 5, iclass 33, count 0 2006.161.08:13:21.91#ibcon#about to read 6, iclass 33, count 0 2006.161.08:13:21.91#ibcon#read 6, iclass 33, count 0 2006.161.08:13:21.91#ibcon#end of sib2, iclass 33, count 0 2006.161.08:13:21.91#ibcon#*after write, iclass 33, count 0 2006.161.08:13:21.91#ibcon#*before return 0, iclass 33, count 0 2006.161.08:13:21.91#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:13:21.91#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:13:21.91#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:13:21.91#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:13:21.91$vc4f8/vblo=1,632.99 2006.161.08:13:21.91#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.08:13:21.91#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.08:13:21.91#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:21.91#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:21.91#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:21.91#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:21.91#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:13:21.91#ibcon#first serial, iclass 35, count 0 2006.161.08:13:21.91#ibcon#enter sib2, iclass 35, count 0 2006.161.08:13:21.91#ibcon#flushed, iclass 35, count 0 2006.161.08:13:21.91#ibcon#about to write, iclass 35, count 0 2006.161.08:13:21.91#ibcon#wrote, iclass 35, count 0 2006.161.08:13:21.91#ibcon#about to read 3, iclass 35, count 0 2006.161.08:13:21.93#ibcon#read 3, iclass 35, count 0 2006.161.08:13:21.93#ibcon#about to read 4, iclass 35, count 0 2006.161.08:13:21.93#ibcon#read 4, iclass 35, count 0 2006.161.08:13:21.93#ibcon#about to read 5, iclass 35, count 0 2006.161.08:13:21.93#ibcon#read 5, iclass 35, count 0 2006.161.08:13:21.93#ibcon#about to read 6, iclass 35, count 0 2006.161.08:13:21.93#ibcon#read 6, iclass 35, count 0 2006.161.08:13:21.93#ibcon#end of sib2, iclass 35, count 0 2006.161.08:13:21.93#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:13:21.93#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:13:21.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:13:21.93#ibcon#*before write, iclass 35, count 0 2006.161.08:13:21.93#ibcon#enter sib2, iclass 35, count 0 2006.161.08:13:21.93#ibcon#flushed, iclass 35, count 0 2006.161.08:13:21.93#ibcon#about to write, iclass 35, count 0 2006.161.08:13:21.93#ibcon#wrote, iclass 35, count 0 2006.161.08:13:21.93#ibcon#about to read 3, iclass 35, count 0 2006.161.08:13:21.97#ibcon#read 3, iclass 35, count 0 2006.161.08:13:21.97#ibcon#about to read 4, iclass 35, count 0 2006.161.08:13:21.97#ibcon#read 4, iclass 35, count 0 2006.161.08:13:21.97#ibcon#about to read 5, iclass 35, count 0 2006.161.08:13:21.97#ibcon#read 5, iclass 35, count 0 2006.161.08:13:21.97#ibcon#about to read 6, iclass 35, count 0 2006.161.08:13:21.97#ibcon#read 6, iclass 35, count 0 2006.161.08:13:21.97#ibcon#end of sib2, iclass 35, count 0 2006.161.08:13:21.97#ibcon#*after write, iclass 35, count 0 2006.161.08:13:21.97#ibcon#*before return 0, iclass 35, count 0 2006.161.08:13:21.97#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:21.97#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:13:21.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:13:21.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:13:21.97$vc4f8/vb=1,4 2006.161.08:13:21.97#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.08:13:21.97#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.08:13:21.97#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:21.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:21.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:21.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:21.97#ibcon#enter wrdev, iclass 37, count 2 2006.161.08:13:21.97#ibcon#first serial, iclass 37, count 2 2006.161.08:13:21.97#ibcon#enter sib2, iclass 37, count 2 2006.161.08:13:21.97#ibcon#flushed, iclass 37, count 2 2006.161.08:13:21.97#ibcon#about to write, iclass 37, count 2 2006.161.08:13:21.97#ibcon#wrote, iclass 37, count 2 2006.161.08:13:21.97#ibcon#about to read 3, iclass 37, count 2 2006.161.08:13:21.99#ibcon#read 3, iclass 37, count 2 2006.161.08:13:21.99#ibcon#about to read 4, iclass 37, count 2 2006.161.08:13:21.99#ibcon#read 4, iclass 37, count 2 2006.161.08:13:21.99#ibcon#about to read 5, iclass 37, count 2 2006.161.08:13:21.99#ibcon#read 5, iclass 37, count 2 2006.161.08:13:21.99#ibcon#about to read 6, iclass 37, count 2 2006.161.08:13:21.99#ibcon#read 6, iclass 37, count 2 2006.161.08:13:21.99#ibcon#end of sib2, iclass 37, count 2 2006.161.08:13:21.99#ibcon#*mode == 0, iclass 37, count 2 2006.161.08:13:21.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.08:13:21.99#ibcon#[27=AT01-04\r\n] 2006.161.08:13:21.99#ibcon#*before write, iclass 37, count 2 2006.161.08:13:21.99#ibcon#enter sib2, iclass 37, count 2 2006.161.08:13:21.99#ibcon#flushed, iclass 37, count 2 2006.161.08:13:21.99#ibcon#about to write, iclass 37, count 2 2006.161.08:13:21.99#ibcon#wrote, iclass 37, count 2 2006.161.08:13:21.99#ibcon#about to read 3, iclass 37, count 2 2006.161.08:13:22.02#ibcon#read 3, iclass 37, count 2 2006.161.08:13:22.02#ibcon#about to read 4, iclass 37, count 2 2006.161.08:13:22.02#ibcon#read 4, iclass 37, count 2 2006.161.08:13:22.02#ibcon#about to read 5, iclass 37, count 2 2006.161.08:13:22.02#ibcon#read 5, iclass 37, count 2 2006.161.08:13:22.02#ibcon#about to read 6, iclass 37, count 2 2006.161.08:13:22.02#ibcon#read 6, iclass 37, count 2 2006.161.08:13:22.02#ibcon#end of sib2, iclass 37, count 2 2006.161.08:13:22.02#ibcon#*after write, iclass 37, count 2 2006.161.08:13:22.02#ibcon#*before return 0, iclass 37, count 2 2006.161.08:13:22.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:22.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:13:22.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.08:13:22.02#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:22.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:22.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:22.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:22.14#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:13:22.14#ibcon#first serial, iclass 37, count 0 2006.161.08:13:22.14#ibcon#enter sib2, iclass 37, count 0 2006.161.08:13:22.14#ibcon#flushed, iclass 37, count 0 2006.161.08:13:22.14#ibcon#about to write, iclass 37, count 0 2006.161.08:13:22.14#ibcon#wrote, iclass 37, count 0 2006.161.08:13:22.14#ibcon#about to read 3, iclass 37, count 0 2006.161.08:13:22.16#ibcon#read 3, iclass 37, count 0 2006.161.08:13:22.16#ibcon#about to read 4, iclass 37, count 0 2006.161.08:13:22.16#ibcon#read 4, iclass 37, count 0 2006.161.08:13:22.16#ibcon#about to read 5, iclass 37, count 0 2006.161.08:13:22.16#ibcon#read 5, iclass 37, count 0 2006.161.08:13:22.16#ibcon#about to read 6, iclass 37, count 0 2006.161.08:13:22.16#ibcon#read 6, iclass 37, count 0 2006.161.08:13:22.16#ibcon#end of sib2, iclass 37, count 0 2006.161.08:13:22.16#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:13:22.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:13:22.16#ibcon#[27=USB\r\n] 2006.161.08:13:22.16#ibcon#*before write, iclass 37, count 0 2006.161.08:13:22.16#ibcon#enter sib2, iclass 37, count 0 2006.161.08:13:22.16#ibcon#flushed, iclass 37, count 0 2006.161.08:13:22.16#ibcon#about to write, iclass 37, count 0 2006.161.08:13:22.16#ibcon#wrote, iclass 37, count 0 2006.161.08:13:22.16#ibcon#about to read 3, iclass 37, count 0 2006.161.08:13:22.19#ibcon#read 3, iclass 37, count 0 2006.161.08:13:22.19#ibcon#about to read 4, iclass 37, count 0 2006.161.08:13:22.19#ibcon#read 4, iclass 37, count 0 2006.161.08:13:22.19#ibcon#about to read 5, iclass 37, count 0 2006.161.08:13:22.19#ibcon#read 5, iclass 37, count 0 2006.161.08:13:22.19#ibcon#about to read 6, iclass 37, count 0 2006.161.08:13:22.19#ibcon#read 6, iclass 37, count 0 2006.161.08:13:22.19#ibcon#end of sib2, iclass 37, count 0 2006.161.08:13:22.19#ibcon#*after write, iclass 37, count 0 2006.161.08:13:22.19#ibcon#*before return 0, iclass 37, count 0 2006.161.08:13:22.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:22.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:13:22.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:13:22.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:13:22.19$vc4f8/vblo=2,640.99 2006.161.08:13:22.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.08:13:22.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.08:13:22.19#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:22.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:22.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:22.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:22.19#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:13:22.19#ibcon#first serial, iclass 39, count 0 2006.161.08:13:22.19#ibcon#enter sib2, iclass 39, count 0 2006.161.08:13:22.19#ibcon#flushed, iclass 39, count 0 2006.161.08:13:22.19#ibcon#about to write, iclass 39, count 0 2006.161.08:13:22.19#ibcon#wrote, iclass 39, count 0 2006.161.08:13:22.19#ibcon#about to read 3, iclass 39, count 0 2006.161.08:13:22.21#ibcon#read 3, iclass 39, count 0 2006.161.08:13:22.21#ibcon#about to read 4, iclass 39, count 0 2006.161.08:13:22.21#ibcon#read 4, iclass 39, count 0 2006.161.08:13:22.21#ibcon#about to read 5, iclass 39, count 0 2006.161.08:13:22.21#ibcon#read 5, iclass 39, count 0 2006.161.08:13:22.21#ibcon#about to read 6, iclass 39, count 0 2006.161.08:13:22.21#ibcon#read 6, iclass 39, count 0 2006.161.08:13:22.21#ibcon#end of sib2, iclass 39, count 0 2006.161.08:13:22.21#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:13:22.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:13:22.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:13:22.21#ibcon#*before write, iclass 39, count 0 2006.161.08:13:22.21#ibcon#enter sib2, iclass 39, count 0 2006.161.08:13:22.21#ibcon#flushed, iclass 39, count 0 2006.161.08:13:22.21#ibcon#about to write, iclass 39, count 0 2006.161.08:13:22.21#ibcon#wrote, iclass 39, count 0 2006.161.08:13:22.21#ibcon#about to read 3, iclass 39, count 0 2006.161.08:13:22.25#ibcon#read 3, iclass 39, count 0 2006.161.08:13:22.25#ibcon#about to read 4, iclass 39, count 0 2006.161.08:13:22.25#ibcon#read 4, iclass 39, count 0 2006.161.08:13:22.25#ibcon#about to read 5, iclass 39, count 0 2006.161.08:13:22.25#ibcon#read 5, iclass 39, count 0 2006.161.08:13:22.25#ibcon#about to read 6, iclass 39, count 0 2006.161.08:13:22.25#ibcon#read 6, iclass 39, count 0 2006.161.08:13:22.25#ibcon#end of sib2, iclass 39, count 0 2006.161.08:13:22.25#ibcon#*after write, iclass 39, count 0 2006.161.08:13:22.25#ibcon#*before return 0, iclass 39, count 0 2006.161.08:13:22.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:22.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:13:22.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:13:22.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:13:22.25$vc4f8/vb=2,4 2006.161.08:13:22.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.08:13:22.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.08:13:22.25#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:22.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:22.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:22.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:22.31#ibcon#enter wrdev, iclass 3, count 2 2006.161.08:13:22.31#ibcon#first serial, iclass 3, count 2 2006.161.08:13:22.31#ibcon#enter sib2, iclass 3, count 2 2006.161.08:13:22.31#ibcon#flushed, iclass 3, count 2 2006.161.08:13:22.31#ibcon#about to write, iclass 3, count 2 2006.161.08:13:22.31#ibcon#wrote, iclass 3, count 2 2006.161.08:13:22.31#ibcon#about to read 3, iclass 3, count 2 2006.161.08:13:22.33#ibcon#read 3, iclass 3, count 2 2006.161.08:13:22.33#ibcon#about to read 4, iclass 3, count 2 2006.161.08:13:22.33#ibcon#read 4, iclass 3, count 2 2006.161.08:13:22.33#ibcon#about to read 5, iclass 3, count 2 2006.161.08:13:22.33#ibcon#read 5, iclass 3, count 2 2006.161.08:13:22.33#ibcon#about to read 6, iclass 3, count 2 2006.161.08:13:22.33#ibcon#read 6, iclass 3, count 2 2006.161.08:13:22.33#ibcon#end of sib2, iclass 3, count 2 2006.161.08:13:22.33#ibcon#*mode == 0, iclass 3, count 2 2006.161.08:13:22.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.08:13:22.33#ibcon#[27=AT02-04\r\n] 2006.161.08:13:22.33#ibcon#*before write, iclass 3, count 2 2006.161.08:13:22.33#ibcon#enter sib2, iclass 3, count 2 2006.161.08:13:22.33#ibcon#flushed, iclass 3, count 2 2006.161.08:13:22.33#ibcon#about to write, iclass 3, count 2 2006.161.08:13:22.33#ibcon#wrote, iclass 3, count 2 2006.161.08:13:22.33#ibcon#about to read 3, iclass 3, count 2 2006.161.08:13:22.36#ibcon#read 3, iclass 3, count 2 2006.161.08:13:22.36#ibcon#about to read 4, iclass 3, count 2 2006.161.08:13:22.36#ibcon#read 4, iclass 3, count 2 2006.161.08:13:22.36#ibcon#about to read 5, iclass 3, count 2 2006.161.08:13:22.36#ibcon#read 5, iclass 3, count 2 2006.161.08:13:22.36#ibcon#about to read 6, iclass 3, count 2 2006.161.08:13:22.36#ibcon#read 6, iclass 3, count 2 2006.161.08:13:22.36#ibcon#end of sib2, iclass 3, count 2 2006.161.08:13:22.36#ibcon#*after write, iclass 3, count 2 2006.161.08:13:22.36#ibcon#*before return 0, iclass 3, count 2 2006.161.08:13:22.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:22.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:13:22.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.08:13:22.36#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:22.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:22.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:22.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:22.48#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:13:22.48#ibcon#first serial, iclass 3, count 0 2006.161.08:13:22.48#ibcon#enter sib2, iclass 3, count 0 2006.161.08:13:22.48#ibcon#flushed, iclass 3, count 0 2006.161.08:13:22.48#ibcon#about to write, iclass 3, count 0 2006.161.08:13:22.48#ibcon#wrote, iclass 3, count 0 2006.161.08:13:22.48#ibcon#about to read 3, iclass 3, count 0 2006.161.08:13:22.50#ibcon#read 3, iclass 3, count 0 2006.161.08:13:22.50#ibcon#about to read 4, iclass 3, count 0 2006.161.08:13:22.50#ibcon#read 4, iclass 3, count 0 2006.161.08:13:22.50#ibcon#about to read 5, iclass 3, count 0 2006.161.08:13:22.50#ibcon#read 5, iclass 3, count 0 2006.161.08:13:22.50#ibcon#about to read 6, iclass 3, count 0 2006.161.08:13:22.50#ibcon#read 6, iclass 3, count 0 2006.161.08:13:22.50#ibcon#end of sib2, iclass 3, count 0 2006.161.08:13:22.50#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:13:22.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:13:22.50#ibcon#[27=USB\r\n] 2006.161.08:13:22.50#ibcon#*before write, iclass 3, count 0 2006.161.08:13:22.50#ibcon#enter sib2, iclass 3, count 0 2006.161.08:13:22.50#ibcon#flushed, iclass 3, count 0 2006.161.08:13:22.50#ibcon#about to write, iclass 3, count 0 2006.161.08:13:22.50#ibcon#wrote, iclass 3, count 0 2006.161.08:13:22.50#ibcon#about to read 3, iclass 3, count 0 2006.161.08:13:22.53#ibcon#read 3, iclass 3, count 0 2006.161.08:13:22.53#ibcon#about to read 4, iclass 3, count 0 2006.161.08:13:22.53#ibcon#read 4, iclass 3, count 0 2006.161.08:13:22.53#ibcon#about to read 5, iclass 3, count 0 2006.161.08:13:22.53#ibcon#read 5, iclass 3, count 0 2006.161.08:13:22.53#ibcon#about to read 6, iclass 3, count 0 2006.161.08:13:22.53#ibcon#read 6, iclass 3, count 0 2006.161.08:13:22.53#ibcon#end of sib2, iclass 3, count 0 2006.161.08:13:22.53#ibcon#*after write, iclass 3, count 0 2006.161.08:13:22.53#ibcon#*before return 0, iclass 3, count 0 2006.161.08:13:22.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:22.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:13:22.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:13:22.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:13:22.53$vc4f8/vblo=3,656.99 2006.161.08:13:22.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.08:13:22.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.08:13:22.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:22.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:22.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:22.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:22.53#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:13:22.53#ibcon#first serial, iclass 5, count 0 2006.161.08:13:22.53#ibcon#enter sib2, iclass 5, count 0 2006.161.08:13:22.53#ibcon#flushed, iclass 5, count 0 2006.161.08:13:22.53#ibcon#about to write, iclass 5, count 0 2006.161.08:13:22.53#ibcon#wrote, iclass 5, count 0 2006.161.08:13:22.53#ibcon#about to read 3, iclass 5, count 0 2006.161.08:13:22.55#ibcon#read 3, iclass 5, count 0 2006.161.08:13:22.55#ibcon#about to read 4, iclass 5, count 0 2006.161.08:13:22.55#ibcon#read 4, iclass 5, count 0 2006.161.08:13:22.55#ibcon#about to read 5, iclass 5, count 0 2006.161.08:13:22.55#ibcon#read 5, iclass 5, count 0 2006.161.08:13:22.55#ibcon#about to read 6, iclass 5, count 0 2006.161.08:13:22.55#ibcon#read 6, iclass 5, count 0 2006.161.08:13:22.55#ibcon#end of sib2, iclass 5, count 0 2006.161.08:13:22.55#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:13:22.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:13:22.55#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:13:22.55#ibcon#*before write, iclass 5, count 0 2006.161.08:13:22.55#ibcon#enter sib2, iclass 5, count 0 2006.161.08:13:22.55#ibcon#flushed, iclass 5, count 0 2006.161.08:13:22.55#ibcon#about to write, iclass 5, count 0 2006.161.08:13:22.55#ibcon#wrote, iclass 5, count 0 2006.161.08:13:22.55#ibcon#about to read 3, iclass 5, count 0 2006.161.08:13:22.59#ibcon#read 3, iclass 5, count 0 2006.161.08:13:22.59#ibcon#about to read 4, iclass 5, count 0 2006.161.08:13:22.59#ibcon#read 4, iclass 5, count 0 2006.161.08:13:22.59#ibcon#about to read 5, iclass 5, count 0 2006.161.08:13:22.59#ibcon#read 5, iclass 5, count 0 2006.161.08:13:22.59#ibcon#about to read 6, iclass 5, count 0 2006.161.08:13:22.59#ibcon#read 6, iclass 5, count 0 2006.161.08:13:22.59#ibcon#end of sib2, iclass 5, count 0 2006.161.08:13:22.59#ibcon#*after write, iclass 5, count 0 2006.161.08:13:22.59#ibcon#*before return 0, iclass 5, count 0 2006.161.08:13:22.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:22.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:13:22.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:13:22.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:13:22.59$vc4f8/vb=3,4 2006.161.08:13:22.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.08:13:22.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.08:13:22.59#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:22.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:22.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:22.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:22.65#ibcon#enter wrdev, iclass 7, count 2 2006.161.08:13:22.65#ibcon#first serial, iclass 7, count 2 2006.161.08:13:22.65#ibcon#enter sib2, iclass 7, count 2 2006.161.08:13:22.65#ibcon#flushed, iclass 7, count 2 2006.161.08:13:22.65#ibcon#about to write, iclass 7, count 2 2006.161.08:13:22.65#ibcon#wrote, iclass 7, count 2 2006.161.08:13:22.65#ibcon#about to read 3, iclass 7, count 2 2006.161.08:13:22.67#ibcon#read 3, iclass 7, count 2 2006.161.08:13:22.67#ibcon#about to read 4, iclass 7, count 2 2006.161.08:13:22.67#ibcon#read 4, iclass 7, count 2 2006.161.08:13:22.67#ibcon#about to read 5, iclass 7, count 2 2006.161.08:13:22.67#ibcon#read 5, iclass 7, count 2 2006.161.08:13:22.67#ibcon#about to read 6, iclass 7, count 2 2006.161.08:13:22.67#ibcon#read 6, iclass 7, count 2 2006.161.08:13:22.67#ibcon#end of sib2, iclass 7, count 2 2006.161.08:13:22.67#ibcon#*mode == 0, iclass 7, count 2 2006.161.08:13:22.67#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.08:13:22.67#ibcon#[27=AT03-04\r\n] 2006.161.08:13:22.67#ibcon#*before write, iclass 7, count 2 2006.161.08:13:22.67#ibcon#enter sib2, iclass 7, count 2 2006.161.08:13:22.67#ibcon#flushed, iclass 7, count 2 2006.161.08:13:22.67#ibcon#about to write, iclass 7, count 2 2006.161.08:13:22.67#ibcon#wrote, iclass 7, count 2 2006.161.08:13:22.67#ibcon#about to read 3, iclass 7, count 2 2006.161.08:13:22.70#ibcon#read 3, iclass 7, count 2 2006.161.08:13:22.70#ibcon#about to read 4, iclass 7, count 2 2006.161.08:13:22.70#ibcon#read 4, iclass 7, count 2 2006.161.08:13:22.70#ibcon#about to read 5, iclass 7, count 2 2006.161.08:13:22.70#ibcon#read 5, iclass 7, count 2 2006.161.08:13:22.70#ibcon#about to read 6, iclass 7, count 2 2006.161.08:13:22.70#ibcon#read 6, iclass 7, count 2 2006.161.08:13:22.70#ibcon#end of sib2, iclass 7, count 2 2006.161.08:13:22.70#ibcon#*after write, iclass 7, count 2 2006.161.08:13:22.70#ibcon#*before return 0, iclass 7, count 2 2006.161.08:13:22.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:22.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:13:22.70#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.08:13:22.70#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:22.70#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:22.82#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:22.82#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:22.82#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:13:22.82#ibcon#first serial, iclass 7, count 0 2006.161.08:13:22.82#ibcon#enter sib2, iclass 7, count 0 2006.161.08:13:22.82#ibcon#flushed, iclass 7, count 0 2006.161.08:13:22.82#ibcon#about to write, iclass 7, count 0 2006.161.08:13:22.82#ibcon#wrote, iclass 7, count 0 2006.161.08:13:22.82#ibcon#about to read 3, iclass 7, count 0 2006.161.08:13:22.84#ibcon#read 3, iclass 7, count 0 2006.161.08:13:22.84#ibcon#about to read 4, iclass 7, count 0 2006.161.08:13:22.84#ibcon#read 4, iclass 7, count 0 2006.161.08:13:22.84#ibcon#about to read 5, iclass 7, count 0 2006.161.08:13:22.84#ibcon#read 5, iclass 7, count 0 2006.161.08:13:22.84#ibcon#about to read 6, iclass 7, count 0 2006.161.08:13:22.84#ibcon#read 6, iclass 7, count 0 2006.161.08:13:22.84#ibcon#end of sib2, iclass 7, count 0 2006.161.08:13:22.84#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:13:22.84#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:13:22.84#ibcon#[27=USB\r\n] 2006.161.08:13:22.84#ibcon#*before write, iclass 7, count 0 2006.161.08:13:22.84#ibcon#enter sib2, iclass 7, count 0 2006.161.08:13:22.84#ibcon#flushed, iclass 7, count 0 2006.161.08:13:22.84#ibcon#about to write, iclass 7, count 0 2006.161.08:13:22.84#ibcon#wrote, iclass 7, count 0 2006.161.08:13:22.84#ibcon#about to read 3, iclass 7, count 0 2006.161.08:13:22.87#ibcon#read 3, iclass 7, count 0 2006.161.08:13:22.87#ibcon#about to read 4, iclass 7, count 0 2006.161.08:13:22.87#ibcon#read 4, iclass 7, count 0 2006.161.08:13:22.87#ibcon#about to read 5, iclass 7, count 0 2006.161.08:13:22.87#ibcon#read 5, iclass 7, count 0 2006.161.08:13:22.87#ibcon#about to read 6, iclass 7, count 0 2006.161.08:13:22.87#ibcon#read 6, iclass 7, count 0 2006.161.08:13:22.87#ibcon#end of sib2, iclass 7, count 0 2006.161.08:13:22.87#ibcon#*after write, iclass 7, count 0 2006.161.08:13:22.87#ibcon#*before return 0, iclass 7, count 0 2006.161.08:13:22.87#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:22.87#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:13:22.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:13:22.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:13:22.87$vc4f8/vblo=4,712.99 2006.161.08:13:22.87#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.08:13:22.87#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.08:13:22.87#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:22.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:22.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:22.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:22.87#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:13:22.87#ibcon#first serial, iclass 11, count 0 2006.161.08:13:22.87#ibcon#enter sib2, iclass 11, count 0 2006.161.08:13:22.87#ibcon#flushed, iclass 11, count 0 2006.161.08:13:22.87#ibcon#about to write, iclass 11, count 0 2006.161.08:13:22.87#ibcon#wrote, iclass 11, count 0 2006.161.08:13:22.87#ibcon#about to read 3, iclass 11, count 0 2006.161.08:13:22.89#ibcon#read 3, iclass 11, count 0 2006.161.08:13:22.89#ibcon#about to read 4, iclass 11, count 0 2006.161.08:13:22.89#ibcon#read 4, iclass 11, count 0 2006.161.08:13:22.89#ibcon#about to read 5, iclass 11, count 0 2006.161.08:13:22.89#ibcon#read 5, iclass 11, count 0 2006.161.08:13:22.89#ibcon#about to read 6, iclass 11, count 0 2006.161.08:13:22.89#ibcon#read 6, iclass 11, count 0 2006.161.08:13:22.89#ibcon#end of sib2, iclass 11, count 0 2006.161.08:13:22.89#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:13:22.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:13:22.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:13:22.89#ibcon#*before write, iclass 11, count 0 2006.161.08:13:22.89#ibcon#enter sib2, iclass 11, count 0 2006.161.08:13:22.89#ibcon#flushed, iclass 11, count 0 2006.161.08:13:22.89#ibcon#about to write, iclass 11, count 0 2006.161.08:13:22.89#ibcon#wrote, iclass 11, count 0 2006.161.08:13:22.89#ibcon#about to read 3, iclass 11, count 0 2006.161.08:13:22.93#ibcon#read 3, iclass 11, count 0 2006.161.08:13:22.93#ibcon#about to read 4, iclass 11, count 0 2006.161.08:13:22.93#ibcon#read 4, iclass 11, count 0 2006.161.08:13:22.93#ibcon#about to read 5, iclass 11, count 0 2006.161.08:13:22.93#ibcon#read 5, iclass 11, count 0 2006.161.08:13:22.93#ibcon#about to read 6, iclass 11, count 0 2006.161.08:13:22.93#ibcon#read 6, iclass 11, count 0 2006.161.08:13:22.93#ibcon#end of sib2, iclass 11, count 0 2006.161.08:13:22.93#ibcon#*after write, iclass 11, count 0 2006.161.08:13:22.93#ibcon#*before return 0, iclass 11, count 0 2006.161.08:13:22.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:22.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:13:22.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:13:22.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:13:22.93$vc4f8/vb=4,4 2006.161.08:13:22.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.161.08:13:22.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.161.08:13:22.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:22.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:23.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:23.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:23.00#ibcon#enter wrdev, iclass 13, count 2 2006.161.08:13:23.00#ibcon#first serial, iclass 13, count 2 2006.161.08:13:23.00#ibcon#enter sib2, iclass 13, count 2 2006.161.08:13:23.00#ibcon#flushed, iclass 13, count 2 2006.161.08:13:23.00#ibcon#about to write, iclass 13, count 2 2006.161.08:13:23.00#ibcon#wrote, iclass 13, count 2 2006.161.08:13:23.00#ibcon#about to read 3, iclass 13, count 2 2006.161.08:13:23.01#ibcon#read 3, iclass 13, count 2 2006.161.08:13:23.01#ibcon#about to read 4, iclass 13, count 2 2006.161.08:13:23.01#ibcon#read 4, iclass 13, count 2 2006.161.08:13:23.01#ibcon#about to read 5, iclass 13, count 2 2006.161.08:13:23.01#ibcon#read 5, iclass 13, count 2 2006.161.08:13:23.01#ibcon#about to read 6, iclass 13, count 2 2006.161.08:13:23.01#ibcon#read 6, iclass 13, count 2 2006.161.08:13:23.01#ibcon#end of sib2, iclass 13, count 2 2006.161.08:13:23.01#ibcon#*mode == 0, iclass 13, count 2 2006.161.08:13:23.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.161.08:13:23.01#ibcon#[27=AT04-04\r\n] 2006.161.08:13:23.01#ibcon#*before write, iclass 13, count 2 2006.161.08:13:23.01#ibcon#enter sib2, iclass 13, count 2 2006.161.08:13:23.01#ibcon#flushed, iclass 13, count 2 2006.161.08:13:23.01#ibcon#about to write, iclass 13, count 2 2006.161.08:13:23.01#ibcon#wrote, iclass 13, count 2 2006.161.08:13:23.01#ibcon#about to read 3, iclass 13, count 2 2006.161.08:13:23.04#ibcon#read 3, iclass 13, count 2 2006.161.08:13:23.04#ibcon#about to read 4, iclass 13, count 2 2006.161.08:13:23.04#ibcon#read 4, iclass 13, count 2 2006.161.08:13:23.04#ibcon#about to read 5, iclass 13, count 2 2006.161.08:13:23.04#ibcon#read 5, iclass 13, count 2 2006.161.08:13:23.04#ibcon#about to read 6, iclass 13, count 2 2006.161.08:13:23.04#ibcon#read 6, iclass 13, count 2 2006.161.08:13:23.04#ibcon#end of sib2, iclass 13, count 2 2006.161.08:13:23.04#ibcon#*after write, iclass 13, count 2 2006.161.08:13:23.04#ibcon#*before return 0, iclass 13, count 2 2006.161.08:13:23.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:23.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.161.08:13:23.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.161.08:13:23.04#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:23.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:23.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:23.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:23.16#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:13:23.16#ibcon#first serial, iclass 13, count 0 2006.161.08:13:23.16#ibcon#enter sib2, iclass 13, count 0 2006.161.08:13:23.16#ibcon#flushed, iclass 13, count 0 2006.161.08:13:23.16#ibcon#about to write, iclass 13, count 0 2006.161.08:13:23.16#ibcon#wrote, iclass 13, count 0 2006.161.08:13:23.16#ibcon#about to read 3, iclass 13, count 0 2006.161.08:13:23.18#ibcon#read 3, iclass 13, count 0 2006.161.08:13:23.18#ibcon#about to read 4, iclass 13, count 0 2006.161.08:13:23.18#ibcon#read 4, iclass 13, count 0 2006.161.08:13:23.18#ibcon#about to read 5, iclass 13, count 0 2006.161.08:13:23.18#ibcon#read 5, iclass 13, count 0 2006.161.08:13:23.18#ibcon#about to read 6, iclass 13, count 0 2006.161.08:13:23.18#ibcon#read 6, iclass 13, count 0 2006.161.08:13:23.18#ibcon#end of sib2, iclass 13, count 0 2006.161.08:13:23.18#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:13:23.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:13:23.18#ibcon#[27=USB\r\n] 2006.161.08:13:23.18#ibcon#*before write, iclass 13, count 0 2006.161.08:13:23.18#ibcon#enter sib2, iclass 13, count 0 2006.161.08:13:23.18#ibcon#flushed, iclass 13, count 0 2006.161.08:13:23.18#ibcon#about to write, iclass 13, count 0 2006.161.08:13:23.18#ibcon#wrote, iclass 13, count 0 2006.161.08:13:23.18#ibcon#about to read 3, iclass 13, count 0 2006.161.08:13:23.21#ibcon#read 3, iclass 13, count 0 2006.161.08:13:23.21#ibcon#about to read 4, iclass 13, count 0 2006.161.08:13:23.21#ibcon#read 4, iclass 13, count 0 2006.161.08:13:23.21#ibcon#about to read 5, iclass 13, count 0 2006.161.08:13:23.21#ibcon#read 5, iclass 13, count 0 2006.161.08:13:23.21#ibcon#about to read 6, iclass 13, count 0 2006.161.08:13:23.21#ibcon#read 6, iclass 13, count 0 2006.161.08:13:23.21#ibcon#end of sib2, iclass 13, count 0 2006.161.08:13:23.21#ibcon#*after write, iclass 13, count 0 2006.161.08:13:23.21#ibcon#*before return 0, iclass 13, count 0 2006.161.08:13:23.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:23.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.161.08:13:23.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:13:23.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:13:23.21$vc4f8/vblo=5,744.99 2006.161.08:13:23.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.08:13:23.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.08:13:23.21#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:23.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:13:23.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:13:23.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:13:23.21#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:13:23.21#ibcon#first serial, iclass 15, count 0 2006.161.08:13:23.21#ibcon#enter sib2, iclass 15, count 0 2006.161.08:13:23.21#ibcon#flushed, iclass 15, count 0 2006.161.08:13:23.21#ibcon#about to write, iclass 15, count 0 2006.161.08:13:23.21#ibcon#wrote, iclass 15, count 0 2006.161.08:13:23.21#ibcon#about to read 3, iclass 15, count 0 2006.161.08:13:23.23#ibcon#read 3, iclass 15, count 0 2006.161.08:13:23.23#ibcon#about to read 4, iclass 15, count 0 2006.161.08:13:23.23#ibcon#read 4, iclass 15, count 0 2006.161.08:13:23.23#ibcon#about to read 5, iclass 15, count 0 2006.161.08:13:23.23#ibcon#read 5, iclass 15, count 0 2006.161.08:13:23.23#ibcon#about to read 6, iclass 15, count 0 2006.161.08:13:23.23#ibcon#read 6, iclass 15, count 0 2006.161.08:13:23.23#ibcon#end of sib2, iclass 15, count 0 2006.161.08:13:23.23#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:13:23.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:13:23.23#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:13:23.23#ibcon#*before write, iclass 15, count 0 2006.161.08:13:23.23#ibcon#enter sib2, iclass 15, count 0 2006.161.08:13:23.23#ibcon#flushed, iclass 15, count 0 2006.161.08:13:23.23#ibcon#about to write, iclass 15, count 0 2006.161.08:13:23.23#ibcon#wrote, iclass 15, count 0 2006.161.08:13:23.23#ibcon#about to read 3, iclass 15, count 0 2006.161.08:13:23.27#ibcon#read 3, iclass 15, count 0 2006.161.08:13:23.27#ibcon#about to read 4, iclass 15, count 0 2006.161.08:13:23.27#ibcon#read 4, iclass 15, count 0 2006.161.08:13:23.27#ibcon#about to read 5, iclass 15, count 0 2006.161.08:13:23.27#ibcon#read 5, iclass 15, count 0 2006.161.08:13:23.27#ibcon#about to read 6, iclass 15, count 0 2006.161.08:13:23.27#ibcon#read 6, iclass 15, count 0 2006.161.08:13:23.27#ibcon#end of sib2, iclass 15, count 0 2006.161.08:13:23.27#ibcon#*after write, iclass 15, count 0 2006.161.08:13:23.27#ibcon#*before return 0, iclass 15, count 0 2006.161.08:13:23.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:13:23.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:13:23.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:13:23.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:13:23.27$vc4f8/vb=5,4 2006.161.08:13:23.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.08:13:23.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.08:13:23.27#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:23.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:13:23.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:13:23.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:13:23.33#ibcon#enter wrdev, iclass 17, count 2 2006.161.08:13:23.33#ibcon#first serial, iclass 17, count 2 2006.161.08:13:23.33#ibcon#enter sib2, iclass 17, count 2 2006.161.08:13:23.33#ibcon#flushed, iclass 17, count 2 2006.161.08:13:23.33#ibcon#about to write, iclass 17, count 2 2006.161.08:13:23.33#ibcon#wrote, iclass 17, count 2 2006.161.08:13:23.33#ibcon#about to read 3, iclass 17, count 2 2006.161.08:13:23.35#ibcon#read 3, iclass 17, count 2 2006.161.08:13:23.35#ibcon#about to read 4, iclass 17, count 2 2006.161.08:13:23.35#ibcon#read 4, iclass 17, count 2 2006.161.08:13:23.35#ibcon#about to read 5, iclass 17, count 2 2006.161.08:13:23.35#ibcon#read 5, iclass 17, count 2 2006.161.08:13:23.35#ibcon#about to read 6, iclass 17, count 2 2006.161.08:13:23.35#ibcon#read 6, iclass 17, count 2 2006.161.08:13:23.35#ibcon#end of sib2, iclass 17, count 2 2006.161.08:13:23.35#ibcon#*mode == 0, iclass 17, count 2 2006.161.08:13:23.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.08:13:23.35#ibcon#[27=AT05-04\r\n] 2006.161.08:13:23.35#ibcon#*before write, iclass 17, count 2 2006.161.08:13:23.35#ibcon#enter sib2, iclass 17, count 2 2006.161.08:13:23.35#ibcon#flushed, iclass 17, count 2 2006.161.08:13:23.35#ibcon#about to write, iclass 17, count 2 2006.161.08:13:23.35#ibcon#wrote, iclass 17, count 2 2006.161.08:13:23.35#ibcon#about to read 3, iclass 17, count 2 2006.161.08:13:23.38#ibcon#read 3, iclass 17, count 2 2006.161.08:13:23.38#ibcon#about to read 4, iclass 17, count 2 2006.161.08:13:23.38#ibcon#read 4, iclass 17, count 2 2006.161.08:13:23.38#ibcon#about to read 5, iclass 17, count 2 2006.161.08:13:23.38#ibcon#read 5, iclass 17, count 2 2006.161.08:13:23.38#ibcon#about to read 6, iclass 17, count 2 2006.161.08:13:23.38#ibcon#read 6, iclass 17, count 2 2006.161.08:13:23.38#ibcon#end of sib2, iclass 17, count 2 2006.161.08:13:23.38#ibcon#*after write, iclass 17, count 2 2006.161.08:13:23.38#ibcon#*before return 0, iclass 17, count 2 2006.161.08:13:23.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:13:23.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:13:23.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.08:13:23.38#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:23.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:13:23.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:13:23.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:13:23.50#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:13:23.50#ibcon#first serial, iclass 17, count 0 2006.161.08:13:23.50#ibcon#enter sib2, iclass 17, count 0 2006.161.08:13:23.50#ibcon#flushed, iclass 17, count 0 2006.161.08:13:23.50#ibcon#about to write, iclass 17, count 0 2006.161.08:13:23.50#ibcon#wrote, iclass 17, count 0 2006.161.08:13:23.50#ibcon#about to read 3, iclass 17, count 0 2006.161.08:13:23.52#ibcon#read 3, iclass 17, count 0 2006.161.08:13:23.52#ibcon#about to read 4, iclass 17, count 0 2006.161.08:13:23.52#ibcon#read 4, iclass 17, count 0 2006.161.08:13:23.52#ibcon#about to read 5, iclass 17, count 0 2006.161.08:13:23.52#ibcon#read 5, iclass 17, count 0 2006.161.08:13:23.52#ibcon#about to read 6, iclass 17, count 0 2006.161.08:13:23.52#ibcon#read 6, iclass 17, count 0 2006.161.08:13:23.52#ibcon#end of sib2, iclass 17, count 0 2006.161.08:13:23.52#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:13:23.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:13:23.52#ibcon#[27=USB\r\n] 2006.161.08:13:23.52#ibcon#*before write, iclass 17, count 0 2006.161.08:13:23.52#ibcon#enter sib2, iclass 17, count 0 2006.161.08:13:23.52#ibcon#flushed, iclass 17, count 0 2006.161.08:13:23.52#ibcon#about to write, iclass 17, count 0 2006.161.08:13:23.52#ibcon#wrote, iclass 17, count 0 2006.161.08:13:23.52#ibcon#about to read 3, iclass 17, count 0 2006.161.08:13:23.55#ibcon#read 3, iclass 17, count 0 2006.161.08:13:23.55#ibcon#about to read 4, iclass 17, count 0 2006.161.08:13:23.55#ibcon#read 4, iclass 17, count 0 2006.161.08:13:23.55#ibcon#about to read 5, iclass 17, count 0 2006.161.08:13:23.55#ibcon#read 5, iclass 17, count 0 2006.161.08:13:23.55#ibcon#about to read 6, iclass 17, count 0 2006.161.08:13:23.55#ibcon#read 6, iclass 17, count 0 2006.161.08:13:23.55#ibcon#end of sib2, iclass 17, count 0 2006.161.08:13:23.55#ibcon#*after write, iclass 17, count 0 2006.161.08:13:23.55#ibcon#*before return 0, iclass 17, count 0 2006.161.08:13:23.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:13:23.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:13:23.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:13:23.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:13:23.55$vc4f8/vblo=6,752.99 2006.161.08:13:23.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:13:23.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:13:23.55#ibcon#ireg 17 cls_cnt 0 2006.161.08:13:23.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:23.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:23.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:23.55#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:13:23.55#ibcon#first serial, iclass 19, count 0 2006.161.08:13:23.55#ibcon#enter sib2, iclass 19, count 0 2006.161.08:13:23.55#ibcon#flushed, iclass 19, count 0 2006.161.08:13:23.55#ibcon#about to write, iclass 19, count 0 2006.161.08:13:23.55#ibcon#wrote, iclass 19, count 0 2006.161.08:13:23.55#ibcon#about to read 3, iclass 19, count 0 2006.161.08:13:23.57#ibcon#read 3, iclass 19, count 0 2006.161.08:13:23.57#ibcon#about to read 4, iclass 19, count 0 2006.161.08:13:23.57#ibcon#read 4, iclass 19, count 0 2006.161.08:13:23.57#ibcon#about to read 5, iclass 19, count 0 2006.161.08:13:23.57#ibcon#read 5, iclass 19, count 0 2006.161.08:13:23.57#ibcon#about to read 6, iclass 19, count 0 2006.161.08:13:23.57#ibcon#read 6, iclass 19, count 0 2006.161.08:13:23.57#ibcon#end of sib2, iclass 19, count 0 2006.161.08:13:23.57#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:13:23.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:13:23.57#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:13:23.57#ibcon#*before write, iclass 19, count 0 2006.161.08:13:23.57#ibcon#enter sib2, iclass 19, count 0 2006.161.08:13:23.57#ibcon#flushed, iclass 19, count 0 2006.161.08:13:23.57#ibcon#about to write, iclass 19, count 0 2006.161.08:13:23.57#ibcon#wrote, iclass 19, count 0 2006.161.08:13:23.57#ibcon#about to read 3, iclass 19, count 0 2006.161.08:13:23.61#ibcon#read 3, iclass 19, count 0 2006.161.08:13:23.61#ibcon#about to read 4, iclass 19, count 0 2006.161.08:13:23.61#ibcon#read 4, iclass 19, count 0 2006.161.08:13:23.61#ibcon#about to read 5, iclass 19, count 0 2006.161.08:13:23.61#ibcon#read 5, iclass 19, count 0 2006.161.08:13:23.61#ibcon#about to read 6, iclass 19, count 0 2006.161.08:13:23.61#ibcon#read 6, iclass 19, count 0 2006.161.08:13:23.61#ibcon#end of sib2, iclass 19, count 0 2006.161.08:13:23.61#ibcon#*after write, iclass 19, count 0 2006.161.08:13:23.61#ibcon#*before return 0, iclass 19, count 0 2006.161.08:13:23.61#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:23.61#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:13:23.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:13:23.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:13:23.61$vc4f8/vb=6,4 2006.161.08:13:23.61#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:13:23.61#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:13:23.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:13:23.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:23.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:23.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:23.67#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:13:23.67#ibcon#first serial, iclass 21, count 2 2006.161.08:13:23.67#ibcon#enter sib2, iclass 21, count 2 2006.161.08:13:23.67#ibcon#flushed, iclass 21, count 2 2006.161.08:13:23.67#ibcon#about to write, iclass 21, count 2 2006.161.08:13:23.67#ibcon#wrote, iclass 21, count 2 2006.161.08:13:23.67#ibcon#about to read 3, iclass 21, count 2 2006.161.08:13:23.69#ibcon#read 3, iclass 21, count 2 2006.161.08:13:23.69#ibcon#about to read 4, iclass 21, count 2 2006.161.08:13:23.69#ibcon#read 4, iclass 21, count 2 2006.161.08:13:23.69#ibcon#about to read 5, iclass 21, count 2 2006.161.08:13:23.69#ibcon#read 5, iclass 21, count 2 2006.161.08:13:23.69#ibcon#about to read 6, iclass 21, count 2 2006.161.08:13:23.69#ibcon#read 6, iclass 21, count 2 2006.161.08:13:23.69#ibcon#end of sib2, iclass 21, count 2 2006.161.08:13:23.69#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:13:23.69#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:13:23.69#ibcon#[27=AT06-04\r\n] 2006.161.08:13:23.69#ibcon#*before write, iclass 21, count 2 2006.161.08:13:23.69#ibcon#enter sib2, iclass 21, count 2 2006.161.08:13:23.69#ibcon#flushed, iclass 21, count 2 2006.161.08:13:23.69#ibcon#about to write, iclass 21, count 2 2006.161.08:13:23.69#ibcon#wrote, iclass 21, count 2 2006.161.08:13:23.69#ibcon#about to read 3, iclass 21, count 2 2006.161.08:13:23.72#ibcon#read 3, iclass 21, count 2 2006.161.08:13:23.72#ibcon#about to read 4, iclass 21, count 2 2006.161.08:13:23.72#ibcon#read 4, iclass 21, count 2 2006.161.08:13:23.72#ibcon#about to read 5, iclass 21, count 2 2006.161.08:13:23.72#ibcon#read 5, iclass 21, count 2 2006.161.08:13:23.72#ibcon#about to read 6, iclass 21, count 2 2006.161.08:13:23.72#ibcon#read 6, iclass 21, count 2 2006.161.08:13:23.72#ibcon#end of sib2, iclass 21, count 2 2006.161.08:13:23.72#ibcon#*after write, iclass 21, count 2 2006.161.08:13:23.72#ibcon#*before return 0, iclass 21, count 2 2006.161.08:13:23.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:23.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:13:23.72#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:13:23.72#ibcon#ireg 7 cls_cnt 0 2006.161.08:13:23.72#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:23.84#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:23.84#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:23.84#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:13:23.84#ibcon#first serial, iclass 21, count 0 2006.161.08:13:23.84#ibcon#enter sib2, iclass 21, count 0 2006.161.08:13:23.84#ibcon#flushed, iclass 21, count 0 2006.161.08:13:23.84#ibcon#about to write, iclass 21, count 0 2006.161.08:13:23.84#ibcon#wrote, iclass 21, count 0 2006.161.08:13:23.84#ibcon#about to read 3, iclass 21, count 0 2006.161.08:13:23.86#ibcon#read 3, iclass 21, count 0 2006.161.08:13:23.86#ibcon#about to read 4, iclass 21, count 0 2006.161.08:13:23.86#ibcon#read 4, iclass 21, count 0 2006.161.08:13:23.86#ibcon#about to read 5, iclass 21, count 0 2006.161.08:13:23.86#ibcon#read 5, iclass 21, count 0 2006.161.08:13:23.86#ibcon#about to read 6, iclass 21, count 0 2006.161.08:13:23.86#ibcon#read 6, iclass 21, count 0 2006.161.08:13:23.86#ibcon#end of sib2, iclass 21, count 0 2006.161.08:13:23.86#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:13:23.86#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:13:23.86#ibcon#[27=USB\r\n] 2006.161.08:13:23.86#ibcon#*before write, iclass 21, count 0 2006.161.08:13:23.86#ibcon#enter sib2, iclass 21, count 0 2006.161.08:13:23.86#ibcon#flushed, iclass 21, count 0 2006.161.08:13:23.86#ibcon#about to write, iclass 21, count 0 2006.161.08:13:23.86#ibcon#wrote, iclass 21, count 0 2006.161.08:13:23.86#ibcon#about to read 3, iclass 21, count 0 2006.161.08:13:23.89#ibcon#read 3, iclass 21, count 0 2006.161.08:13:23.89#ibcon#about to read 4, iclass 21, count 0 2006.161.08:13:23.89#ibcon#read 4, iclass 21, count 0 2006.161.08:13:23.89#ibcon#about to read 5, iclass 21, count 0 2006.161.08:13:23.89#ibcon#read 5, iclass 21, count 0 2006.161.08:13:23.89#ibcon#about to read 6, iclass 21, count 0 2006.161.08:13:23.89#ibcon#read 6, iclass 21, count 0 2006.161.08:13:23.89#ibcon#end of sib2, iclass 21, count 0 2006.161.08:13:23.89#ibcon#*after write, iclass 21, count 0 2006.161.08:13:23.89#ibcon#*before return 0, iclass 21, count 0 2006.161.08:13:23.89#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:23.89#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:13:23.89#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:13:23.89#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:13:23.89$vc4f8/vabw=wide 2006.161.08:13:23.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:13:23.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:13:23.89#ibcon#ireg 8 cls_cnt 0 2006.161.08:13:23.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:23.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:23.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:23.89#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:13:23.89#ibcon#first serial, iclass 23, count 0 2006.161.08:13:23.89#ibcon#enter sib2, iclass 23, count 0 2006.161.08:13:23.89#ibcon#flushed, iclass 23, count 0 2006.161.08:13:23.89#ibcon#about to write, iclass 23, count 0 2006.161.08:13:23.89#ibcon#wrote, iclass 23, count 0 2006.161.08:13:23.89#ibcon#about to read 3, iclass 23, count 0 2006.161.08:13:23.91#ibcon#read 3, iclass 23, count 0 2006.161.08:13:23.91#ibcon#about to read 4, iclass 23, count 0 2006.161.08:13:23.91#ibcon#read 4, iclass 23, count 0 2006.161.08:13:23.91#ibcon#about to read 5, iclass 23, count 0 2006.161.08:13:23.91#ibcon#read 5, iclass 23, count 0 2006.161.08:13:23.91#ibcon#about to read 6, iclass 23, count 0 2006.161.08:13:23.91#ibcon#read 6, iclass 23, count 0 2006.161.08:13:23.91#ibcon#end of sib2, iclass 23, count 0 2006.161.08:13:23.91#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:13:23.91#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:13:23.91#ibcon#[25=BW32\r\n] 2006.161.08:13:23.91#ibcon#*before write, iclass 23, count 0 2006.161.08:13:23.91#ibcon#enter sib2, iclass 23, count 0 2006.161.08:13:23.91#ibcon#flushed, iclass 23, count 0 2006.161.08:13:23.91#ibcon#about to write, iclass 23, count 0 2006.161.08:13:23.91#ibcon#wrote, iclass 23, count 0 2006.161.08:13:23.91#ibcon#about to read 3, iclass 23, count 0 2006.161.08:13:23.94#ibcon#read 3, iclass 23, count 0 2006.161.08:13:23.94#ibcon#about to read 4, iclass 23, count 0 2006.161.08:13:23.94#ibcon#read 4, iclass 23, count 0 2006.161.08:13:23.94#ibcon#about to read 5, iclass 23, count 0 2006.161.08:13:23.94#ibcon#read 5, iclass 23, count 0 2006.161.08:13:23.94#ibcon#about to read 6, iclass 23, count 0 2006.161.08:13:23.94#ibcon#read 6, iclass 23, count 0 2006.161.08:13:23.94#ibcon#end of sib2, iclass 23, count 0 2006.161.08:13:23.94#ibcon#*after write, iclass 23, count 0 2006.161.08:13:23.94#ibcon#*before return 0, iclass 23, count 0 2006.161.08:13:23.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:23.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:13:23.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:13:23.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:13:23.94$vc4f8/vbbw=wide 2006.161.08:13:23.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:13:23.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:13:23.94#ibcon#ireg 8 cls_cnt 0 2006.161.08:13:23.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:13:24.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:13:24.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:13:24.01#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:13:24.01#ibcon#first serial, iclass 25, count 0 2006.161.08:13:24.01#ibcon#enter sib2, iclass 25, count 0 2006.161.08:13:24.01#ibcon#flushed, iclass 25, count 0 2006.161.08:13:24.01#ibcon#about to write, iclass 25, count 0 2006.161.08:13:24.01#ibcon#wrote, iclass 25, count 0 2006.161.08:13:24.01#ibcon#about to read 3, iclass 25, count 0 2006.161.08:13:24.03#ibcon#read 3, iclass 25, count 0 2006.161.08:13:24.03#ibcon#about to read 4, iclass 25, count 0 2006.161.08:13:24.03#ibcon#read 4, iclass 25, count 0 2006.161.08:13:24.03#ibcon#about to read 5, iclass 25, count 0 2006.161.08:13:24.03#ibcon#read 5, iclass 25, count 0 2006.161.08:13:24.03#ibcon#about to read 6, iclass 25, count 0 2006.161.08:13:24.03#ibcon#read 6, iclass 25, count 0 2006.161.08:13:24.03#ibcon#end of sib2, iclass 25, count 0 2006.161.08:13:24.03#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:13:24.03#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:13:24.03#ibcon#[27=BW32\r\n] 2006.161.08:13:24.03#ibcon#*before write, iclass 25, count 0 2006.161.08:13:24.03#ibcon#enter sib2, iclass 25, count 0 2006.161.08:13:24.03#ibcon#flushed, iclass 25, count 0 2006.161.08:13:24.03#ibcon#about to write, iclass 25, count 0 2006.161.08:13:24.03#ibcon#wrote, iclass 25, count 0 2006.161.08:13:24.03#ibcon#about to read 3, iclass 25, count 0 2006.161.08:13:24.06#ibcon#read 3, iclass 25, count 0 2006.161.08:13:24.06#ibcon#about to read 4, iclass 25, count 0 2006.161.08:13:24.06#ibcon#read 4, iclass 25, count 0 2006.161.08:13:24.06#ibcon#about to read 5, iclass 25, count 0 2006.161.08:13:24.06#ibcon#read 5, iclass 25, count 0 2006.161.08:13:24.06#ibcon#about to read 6, iclass 25, count 0 2006.161.08:13:24.06#ibcon#read 6, iclass 25, count 0 2006.161.08:13:24.06#ibcon#end of sib2, iclass 25, count 0 2006.161.08:13:24.06#ibcon#*after write, iclass 25, count 0 2006.161.08:13:24.06#ibcon#*before return 0, iclass 25, count 0 2006.161.08:13:24.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:13:24.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:13:24.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:13:24.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:13:24.06$4f8m12a/ifd4f 2006.161.08:13:24.06$ifd4f/lo= 2006.161.08:13:24.06$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:13:24.06$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:13:24.06$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:13:24.06$ifd4f/patch= 2006.161.08:13:24.06$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:13:24.06$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:13:24.06$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:13:24.06$4f8m12a/"form=m,16.000,1:2 2006.161.08:13:24.06$4f8m12a/"tpicd 2006.161.08:13:24.06$4f8m12a/echo=off 2006.161.08:13:24.06$4f8m12a/xlog=off 2006.161.08:13:24.06:!2006.161.08:14:10 2006.161.08:13:48.13#trakl#Source acquired 2006.161.08:13:49.13#flagr#flagr/antenna,acquired 2006.161.08:14:10.00:preob 2006.161.08:14:11.13/onsource/TRACKING 2006.161.08:14:11.13:!2006.161.08:14:20 2006.161.08:14:20.00:data_valid=on 2006.161.08:14:20.00:midob 2006.161.08:14:20.13/onsource/TRACKING 2006.161.08:14:20.13/wx/24.00,1002.5,86 2006.161.08:14:20.36/cable/+6.5030E-03 2006.161.08:14:21.45/va/01,08,usb,yes,35,37 2006.161.08:14:21.45/va/02,07,usb,yes,36,37 2006.161.08:14:21.45/va/03,06,usb,yes,37,38 2006.161.08:14:21.45/va/04,07,usb,yes,36,39 2006.161.08:14:21.45/va/05,07,usb,yes,37,39 2006.161.08:14:21.45/va/06,06,usb,yes,36,35 2006.161.08:14:21.45/va/07,06,usb,yes,36,36 2006.161.08:14:21.45/va/08,07,usb,yes,34,34 2006.161.08:14:21.68/valo/01,532.99,yes,locked 2006.161.08:14:21.68/valo/02,572.99,yes,locked 2006.161.08:14:21.68/valo/03,672.99,yes,locked 2006.161.08:14:21.68/valo/04,832.99,yes,locked 2006.161.08:14:21.68/valo/05,652.99,yes,locked 2006.161.08:14:21.68/valo/06,772.99,yes,locked 2006.161.08:14:21.68/valo/07,832.99,yes,locked 2006.161.08:14:21.68/valo/08,852.99,yes,locked 2006.161.08:14:22.77/vb/01,04,usb,yes,32,31 2006.161.08:14:22.77/vb/02,04,usb,yes,34,36 2006.161.08:14:22.77/vb/03,04,usb,yes,30,35 2006.161.08:14:22.77/vb/04,04,usb,yes,32,32 2006.161.08:14:22.77/vb/05,04,usb,yes,30,34 2006.161.08:14:22.77/vb/06,04,usb,yes,31,34 2006.161.08:14:22.77/vb/07,04,usb,yes,33,33 2006.161.08:14:22.77/vb/08,04,usb,yes,31,34 2006.161.08:14:23.00/vblo/01,632.99,yes,locked 2006.161.08:14:23.00/vblo/02,640.99,yes,locked 2006.161.08:14:23.00/vblo/03,656.99,yes,locked 2006.161.08:14:23.00/vblo/04,712.99,yes,locked 2006.161.08:14:23.00/vblo/05,744.99,yes,locked 2006.161.08:14:23.00/vblo/06,752.99,yes,locked 2006.161.08:14:23.00/vblo/07,734.99,yes,locked 2006.161.08:14:23.00/vblo/08,744.99,yes,locked 2006.161.08:14:23.15/vabw/8 2006.161.08:14:23.30/vbbw/8 2006.161.08:14:23.39/xfe/off,on,15.0 2006.161.08:14:23.76/ifatt/23,28,28,28 2006.161.08:14:24.07/fmout-gps/S +4.49E-07 2006.161.08:14:24.13:!2006.161.08:15:20 2006.161.08:15:20.01:data_valid=off 2006.161.08:15:20.02:postob 2006.161.08:15:20.24/cable/+6.4996E-03 2006.161.08:15:20.24/wx/24.00,1002.5,86 2006.161.08:15:21.07/fmout-gps/S +4.50E-07 2006.161.08:15:21.07:scan_name=161-0816,k06161,60 2006.161.08:15:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.161.08:15:21.14#flagr#flagr/antenna,new-source 2006.161.08:15:22.14:checkk5 2006.161.08:15:22.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:15:23.00/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:15:23.42/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:15:23.88/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:15:24.31/chk_obsdata//k5ts1/T1610814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:15:24.75/chk_obsdata//k5ts2/T1610814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:15:25.19/chk_obsdata//k5ts3/T1610814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:15:25.60/chk_obsdata//k5ts4/T1610814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:15:26.30/k5log//k5ts1_log_newline 2006.161.08:15:27.09/k5log//k5ts2_log_newline 2006.161.08:15:27.90/k5log//k5ts3_log_newline 2006.161.08:15:28.74/k5log//k5ts4_log_newline 2006.161.08:15:28.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:15:28.77:4f8m12a=2 2006.161.08:15:28.77$4f8m12a/echo=on 2006.161.08:15:28.77$4f8m12a/pcalon 2006.161.08:15:28.77$pcalon/"no phase cal control is implemented here 2006.161.08:15:28.77$4f8m12a/"tpicd=stop 2006.161.08:15:28.77$4f8m12a/vc4f8 2006.161.08:15:28.77$vc4f8/valo=1,532.99 2006.161.08:15:28.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.08:15:28.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.08:15:28.77#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:28.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:28.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:28.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:28.77#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:15:28.77#ibcon#first serial, iclass 40, count 0 2006.161.08:15:28.77#ibcon#enter sib2, iclass 40, count 0 2006.161.08:15:28.77#ibcon#flushed, iclass 40, count 0 2006.161.08:15:28.77#ibcon#about to write, iclass 40, count 0 2006.161.08:15:28.77#ibcon#wrote, iclass 40, count 0 2006.161.08:15:28.77#ibcon#about to read 3, iclass 40, count 0 2006.161.08:15:28.82#ibcon#read 3, iclass 40, count 0 2006.161.08:15:28.82#ibcon#about to read 4, iclass 40, count 0 2006.161.08:15:28.82#ibcon#read 4, iclass 40, count 0 2006.161.08:15:28.82#ibcon#about to read 5, iclass 40, count 0 2006.161.08:15:28.82#ibcon#read 5, iclass 40, count 0 2006.161.08:15:28.82#ibcon#about to read 6, iclass 40, count 0 2006.161.08:15:28.82#ibcon#read 6, iclass 40, count 0 2006.161.08:15:28.82#ibcon#end of sib2, iclass 40, count 0 2006.161.08:15:28.82#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:15:28.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:15:28.82#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:15:28.82#ibcon#*before write, iclass 40, count 0 2006.161.08:15:28.82#ibcon#enter sib2, iclass 40, count 0 2006.161.08:15:28.82#ibcon#flushed, iclass 40, count 0 2006.161.08:15:28.82#ibcon#about to write, iclass 40, count 0 2006.161.08:15:28.82#ibcon#wrote, iclass 40, count 0 2006.161.08:15:28.82#ibcon#about to read 3, iclass 40, count 0 2006.161.08:15:28.86#ibcon#read 3, iclass 40, count 0 2006.161.08:15:28.86#ibcon#about to read 4, iclass 40, count 0 2006.161.08:15:28.86#ibcon#read 4, iclass 40, count 0 2006.161.08:15:28.86#ibcon#about to read 5, iclass 40, count 0 2006.161.08:15:28.86#ibcon#read 5, iclass 40, count 0 2006.161.08:15:28.86#ibcon#about to read 6, iclass 40, count 0 2006.161.08:15:28.86#ibcon#read 6, iclass 40, count 0 2006.161.08:15:28.86#ibcon#end of sib2, iclass 40, count 0 2006.161.08:15:28.86#ibcon#*after write, iclass 40, count 0 2006.161.08:15:28.86#ibcon#*before return 0, iclass 40, count 0 2006.161.08:15:28.86#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:28.86#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:28.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:15:28.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:15:28.86$vc4f8/va=1,8 2006.161.08:15:28.86#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.08:15:28.86#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.08:15:28.86#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:28.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:28.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:28.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:28.86#ibcon#enter wrdev, iclass 4, count 2 2006.161.08:15:28.86#ibcon#first serial, iclass 4, count 2 2006.161.08:15:28.86#ibcon#enter sib2, iclass 4, count 2 2006.161.08:15:28.86#ibcon#flushed, iclass 4, count 2 2006.161.08:15:28.86#ibcon#about to write, iclass 4, count 2 2006.161.08:15:28.86#ibcon#wrote, iclass 4, count 2 2006.161.08:15:28.86#ibcon#about to read 3, iclass 4, count 2 2006.161.08:15:28.88#ibcon#read 3, iclass 4, count 2 2006.161.08:15:28.88#ibcon#about to read 4, iclass 4, count 2 2006.161.08:15:28.88#ibcon#read 4, iclass 4, count 2 2006.161.08:15:28.88#ibcon#about to read 5, iclass 4, count 2 2006.161.08:15:28.88#ibcon#read 5, iclass 4, count 2 2006.161.08:15:28.88#ibcon#about to read 6, iclass 4, count 2 2006.161.08:15:28.88#ibcon#read 6, iclass 4, count 2 2006.161.08:15:28.88#ibcon#end of sib2, iclass 4, count 2 2006.161.08:15:28.88#ibcon#*mode == 0, iclass 4, count 2 2006.161.08:15:28.88#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.08:15:28.88#ibcon#[25=AT01-08\r\n] 2006.161.08:15:28.88#ibcon#*before write, iclass 4, count 2 2006.161.08:15:28.88#ibcon#enter sib2, iclass 4, count 2 2006.161.08:15:28.88#ibcon#flushed, iclass 4, count 2 2006.161.08:15:28.88#ibcon#about to write, iclass 4, count 2 2006.161.08:15:28.88#ibcon#wrote, iclass 4, count 2 2006.161.08:15:28.88#ibcon#about to read 3, iclass 4, count 2 2006.161.08:15:28.91#ibcon#read 3, iclass 4, count 2 2006.161.08:15:28.91#ibcon#about to read 4, iclass 4, count 2 2006.161.08:15:28.91#ibcon#read 4, iclass 4, count 2 2006.161.08:15:28.91#ibcon#about to read 5, iclass 4, count 2 2006.161.08:15:28.91#ibcon#read 5, iclass 4, count 2 2006.161.08:15:28.91#ibcon#about to read 6, iclass 4, count 2 2006.161.08:15:28.91#ibcon#read 6, iclass 4, count 2 2006.161.08:15:28.91#ibcon#end of sib2, iclass 4, count 2 2006.161.08:15:28.91#ibcon#*after write, iclass 4, count 2 2006.161.08:15:28.91#ibcon#*before return 0, iclass 4, count 2 2006.161.08:15:28.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:28.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:28.91#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.08:15:28.91#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:28.91#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:29.03#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:29.03#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:29.03#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:15:29.03#ibcon#first serial, iclass 4, count 0 2006.161.08:15:29.03#ibcon#enter sib2, iclass 4, count 0 2006.161.08:15:29.03#ibcon#flushed, iclass 4, count 0 2006.161.08:15:29.03#ibcon#about to write, iclass 4, count 0 2006.161.08:15:29.03#ibcon#wrote, iclass 4, count 0 2006.161.08:15:29.03#ibcon#about to read 3, iclass 4, count 0 2006.161.08:15:29.05#ibcon#read 3, iclass 4, count 0 2006.161.08:15:29.05#ibcon#about to read 4, iclass 4, count 0 2006.161.08:15:29.05#ibcon#read 4, iclass 4, count 0 2006.161.08:15:29.05#ibcon#about to read 5, iclass 4, count 0 2006.161.08:15:29.05#ibcon#read 5, iclass 4, count 0 2006.161.08:15:29.05#ibcon#about to read 6, iclass 4, count 0 2006.161.08:15:29.05#ibcon#read 6, iclass 4, count 0 2006.161.08:15:29.05#ibcon#end of sib2, iclass 4, count 0 2006.161.08:15:29.05#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:15:29.05#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:15:29.05#ibcon#[25=USB\r\n] 2006.161.08:15:29.05#ibcon#*before write, iclass 4, count 0 2006.161.08:15:29.05#ibcon#enter sib2, iclass 4, count 0 2006.161.08:15:29.05#ibcon#flushed, iclass 4, count 0 2006.161.08:15:29.05#ibcon#about to write, iclass 4, count 0 2006.161.08:15:29.05#ibcon#wrote, iclass 4, count 0 2006.161.08:15:29.05#ibcon#about to read 3, iclass 4, count 0 2006.161.08:15:29.08#ibcon#read 3, iclass 4, count 0 2006.161.08:15:29.08#ibcon#about to read 4, iclass 4, count 0 2006.161.08:15:29.08#ibcon#read 4, iclass 4, count 0 2006.161.08:15:29.08#ibcon#about to read 5, iclass 4, count 0 2006.161.08:15:29.08#ibcon#read 5, iclass 4, count 0 2006.161.08:15:29.08#ibcon#about to read 6, iclass 4, count 0 2006.161.08:15:29.08#ibcon#read 6, iclass 4, count 0 2006.161.08:15:29.08#ibcon#end of sib2, iclass 4, count 0 2006.161.08:15:29.08#ibcon#*after write, iclass 4, count 0 2006.161.08:15:29.08#ibcon#*before return 0, iclass 4, count 0 2006.161.08:15:29.08#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:29.08#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:29.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:15:29.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:15:29.08$vc4f8/valo=2,572.99 2006.161.08:15:29.08#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:15:29.08#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:15:29.08#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:29.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:29.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:29.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:29.08#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:15:29.08#ibcon#first serial, iclass 6, count 0 2006.161.08:15:29.08#ibcon#enter sib2, iclass 6, count 0 2006.161.08:15:29.08#ibcon#flushed, iclass 6, count 0 2006.161.08:15:29.08#ibcon#about to write, iclass 6, count 0 2006.161.08:15:29.08#ibcon#wrote, iclass 6, count 0 2006.161.08:15:29.08#ibcon#about to read 3, iclass 6, count 0 2006.161.08:15:29.10#ibcon#read 3, iclass 6, count 0 2006.161.08:15:29.10#ibcon#about to read 4, iclass 6, count 0 2006.161.08:15:29.10#ibcon#read 4, iclass 6, count 0 2006.161.08:15:29.10#ibcon#about to read 5, iclass 6, count 0 2006.161.08:15:29.10#ibcon#read 5, iclass 6, count 0 2006.161.08:15:29.10#ibcon#about to read 6, iclass 6, count 0 2006.161.08:15:29.10#ibcon#read 6, iclass 6, count 0 2006.161.08:15:29.10#ibcon#end of sib2, iclass 6, count 0 2006.161.08:15:29.10#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:15:29.10#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:15:29.10#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:15:29.10#ibcon#*before write, iclass 6, count 0 2006.161.08:15:29.10#ibcon#enter sib2, iclass 6, count 0 2006.161.08:15:29.10#ibcon#flushed, iclass 6, count 0 2006.161.08:15:29.10#ibcon#about to write, iclass 6, count 0 2006.161.08:15:29.10#ibcon#wrote, iclass 6, count 0 2006.161.08:15:29.10#ibcon#about to read 3, iclass 6, count 0 2006.161.08:15:29.14#ibcon#read 3, iclass 6, count 0 2006.161.08:15:29.14#ibcon#about to read 4, iclass 6, count 0 2006.161.08:15:29.14#ibcon#read 4, iclass 6, count 0 2006.161.08:15:29.14#ibcon#about to read 5, iclass 6, count 0 2006.161.08:15:29.14#ibcon#read 5, iclass 6, count 0 2006.161.08:15:29.14#ibcon#about to read 6, iclass 6, count 0 2006.161.08:15:29.14#ibcon#read 6, iclass 6, count 0 2006.161.08:15:29.14#ibcon#end of sib2, iclass 6, count 0 2006.161.08:15:29.14#ibcon#*after write, iclass 6, count 0 2006.161.08:15:29.14#ibcon#*before return 0, iclass 6, count 0 2006.161.08:15:29.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:29.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:29.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:15:29.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:15:29.14$vc4f8/va=2,7 2006.161.08:15:29.14#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.08:15:29.14#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.08:15:29.14#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:29.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:29.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:29.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:29.20#ibcon#enter wrdev, iclass 10, count 2 2006.161.08:15:29.20#ibcon#first serial, iclass 10, count 2 2006.161.08:15:29.20#ibcon#enter sib2, iclass 10, count 2 2006.161.08:15:29.20#ibcon#flushed, iclass 10, count 2 2006.161.08:15:29.20#ibcon#about to write, iclass 10, count 2 2006.161.08:15:29.20#ibcon#wrote, iclass 10, count 2 2006.161.08:15:29.20#ibcon#about to read 3, iclass 10, count 2 2006.161.08:15:29.22#ibcon#read 3, iclass 10, count 2 2006.161.08:15:29.22#ibcon#about to read 4, iclass 10, count 2 2006.161.08:15:29.22#ibcon#read 4, iclass 10, count 2 2006.161.08:15:29.22#ibcon#about to read 5, iclass 10, count 2 2006.161.08:15:29.22#ibcon#read 5, iclass 10, count 2 2006.161.08:15:29.22#ibcon#about to read 6, iclass 10, count 2 2006.161.08:15:29.22#ibcon#read 6, iclass 10, count 2 2006.161.08:15:29.22#ibcon#end of sib2, iclass 10, count 2 2006.161.08:15:29.22#ibcon#*mode == 0, iclass 10, count 2 2006.161.08:15:29.22#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.08:15:29.22#ibcon#[25=AT02-07\r\n] 2006.161.08:15:29.22#ibcon#*before write, iclass 10, count 2 2006.161.08:15:29.22#ibcon#enter sib2, iclass 10, count 2 2006.161.08:15:29.22#ibcon#flushed, iclass 10, count 2 2006.161.08:15:29.22#ibcon#about to write, iclass 10, count 2 2006.161.08:15:29.22#ibcon#wrote, iclass 10, count 2 2006.161.08:15:29.22#ibcon#about to read 3, iclass 10, count 2 2006.161.08:15:29.25#ibcon#read 3, iclass 10, count 2 2006.161.08:15:29.25#ibcon#about to read 4, iclass 10, count 2 2006.161.08:15:29.25#ibcon#read 4, iclass 10, count 2 2006.161.08:15:29.25#ibcon#about to read 5, iclass 10, count 2 2006.161.08:15:29.25#ibcon#read 5, iclass 10, count 2 2006.161.08:15:29.25#ibcon#about to read 6, iclass 10, count 2 2006.161.08:15:29.25#ibcon#read 6, iclass 10, count 2 2006.161.08:15:29.25#ibcon#end of sib2, iclass 10, count 2 2006.161.08:15:29.25#ibcon#*after write, iclass 10, count 2 2006.161.08:15:29.25#ibcon#*before return 0, iclass 10, count 2 2006.161.08:15:29.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:29.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:29.25#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.08:15:29.25#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:29.25#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:29.37#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:29.37#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:29.37#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:15:29.37#ibcon#first serial, iclass 10, count 0 2006.161.08:15:29.37#ibcon#enter sib2, iclass 10, count 0 2006.161.08:15:29.37#ibcon#flushed, iclass 10, count 0 2006.161.08:15:29.37#ibcon#about to write, iclass 10, count 0 2006.161.08:15:29.37#ibcon#wrote, iclass 10, count 0 2006.161.08:15:29.37#ibcon#about to read 3, iclass 10, count 0 2006.161.08:15:29.39#ibcon#read 3, iclass 10, count 0 2006.161.08:15:29.39#ibcon#about to read 4, iclass 10, count 0 2006.161.08:15:29.39#ibcon#read 4, iclass 10, count 0 2006.161.08:15:29.39#ibcon#about to read 5, iclass 10, count 0 2006.161.08:15:29.39#ibcon#read 5, iclass 10, count 0 2006.161.08:15:29.39#ibcon#about to read 6, iclass 10, count 0 2006.161.08:15:29.39#ibcon#read 6, iclass 10, count 0 2006.161.08:15:29.39#ibcon#end of sib2, iclass 10, count 0 2006.161.08:15:29.39#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:15:29.39#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:15:29.39#ibcon#[25=USB\r\n] 2006.161.08:15:29.39#ibcon#*before write, iclass 10, count 0 2006.161.08:15:29.39#ibcon#enter sib2, iclass 10, count 0 2006.161.08:15:29.39#ibcon#flushed, iclass 10, count 0 2006.161.08:15:29.39#ibcon#about to write, iclass 10, count 0 2006.161.08:15:29.39#ibcon#wrote, iclass 10, count 0 2006.161.08:15:29.39#ibcon#about to read 3, iclass 10, count 0 2006.161.08:15:29.42#ibcon#read 3, iclass 10, count 0 2006.161.08:15:29.42#ibcon#about to read 4, iclass 10, count 0 2006.161.08:15:29.42#ibcon#read 4, iclass 10, count 0 2006.161.08:15:29.42#ibcon#about to read 5, iclass 10, count 0 2006.161.08:15:29.42#ibcon#read 5, iclass 10, count 0 2006.161.08:15:29.42#ibcon#about to read 6, iclass 10, count 0 2006.161.08:15:29.42#ibcon#read 6, iclass 10, count 0 2006.161.08:15:29.42#ibcon#end of sib2, iclass 10, count 0 2006.161.08:15:29.42#ibcon#*after write, iclass 10, count 0 2006.161.08:15:29.42#ibcon#*before return 0, iclass 10, count 0 2006.161.08:15:29.42#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:29.42#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:29.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:15:29.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:15:29.42$vc4f8/valo=3,672.99 2006.161.08:15:29.42#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:15:29.42#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:15:29.42#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:29.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:29.42#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:29.42#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:29.42#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:15:29.42#ibcon#first serial, iclass 12, count 0 2006.161.08:15:29.42#ibcon#enter sib2, iclass 12, count 0 2006.161.08:15:29.42#ibcon#flushed, iclass 12, count 0 2006.161.08:15:29.42#ibcon#about to write, iclass 12, count 0 2006.161.08:15:29.42#ibcon#wrote, iclass 12, count 0 2006.161.08:15:29.42#ibcon#about to read 3, iclass 12, count 0 2006.161.08:15:29.44#ibcon#read 3, iclass 12, count 0 2006.161.08:15:29.44#ibcon#about to read 4, iclass 12, count 0 2006.161.08:15:29.44#ibcon#read 4, iclass 12, count 0 2006.161.08:15:29.44#ibcon#about to read 5, iclass 12, count 0 2006.161.08:15:29.44#ibcon#read 5, iclass 12, count 0 2006.161.08:15:29.44#ibcon#about to read 6, iclass 12, count 0 2006.161.08:15:29.44#ibcon#read 6, iclass 12, count 0 2006.161.08:15:29.44#ibcon#end of sib2, iclass 12, count 0 2006.161.08:15:29.44#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:15:29.44#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:15:29.44#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:15:29.44#ibcon#*before write, iclass 12, count 0 2006.161.08:15:29.44#ibcon#enter sib2, iclass 12, count 0 2006.161.08:15:29.44#ibcon#flushed, iclass 12, count 0 2006.161.08:15:29.44#ibcon#about to write, iclass 12, count 0 2006.161.08:15:29.44#ibcon#wrote, iclass 12, count 0 2006.161.08:15:29.44#ibcon#about to read 3, iclass 12, count 0 2006.161.08:15:29.48#ibcon#read 3, iclass 12, count 0 2006.161.08:15:29.48#ibcon#about to read 4, iclass 12, count 0 2006.161.08:15:29.48#ibcon#read 4, iclass 12, count 0 2006.161.08:15:29.48#ibcon#about to read 5, iclass 12, count 0 2006.161.08:15:29.48#ibcon#read 5, iclass 12, count 0 2006.161.08:15:29.48#ibcon#about to read 6, iclass 12, count 0 2006.161.08:15:29.48#ibcon#read 6, iclass 12, count 0 2006.161.08:15:29.48#ibcon#end of sib2, iclass 12, count 0 2006.161.08:15:29.48#ibcon#*after write, iclass 12, count 0 2006.161.08:15:29.48#ibcon#*before return 0, iclass 12, count 0 2006.161.08:15:29.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:29.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:29.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:15:29.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:15:29.48$vc4f8/va=3,6 2006.161.08:15:29.48#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.08:15:29.48#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.08:15:29.48#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:29.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:29.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:29.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:29.54#ibcon#enter wrdev, iclass 14, count 2 2006.161.08:15:29.54#ibcon#first serial, iclass 14, count 2 2006.161.08:15:29.54#ibcon#enter sib2, iclass 14, count 2 2006.161.08:15:29.54#ibcon#flushed, iclass 14, count 2 2006.161.08:15:29.54#ibcon#about to write, iclass 14, count 2 2006.161.08:15:29.54#ibcon#wrote, iclass 14, count 2 2006.161.08:15:29.54#ibcon#about to read 3, iclass 14, count 2 2006.161.08:15:29.57#ibcon#read 3, iclass 14, count 2 2006.161.08:15:29.57#ibcon#about to read 4, iclass 14, count 2 2006.161.08:15:29.57#ibcon#read 4, iclass 14, count 2 2006.161.08:15:29.57#ibcon#about to read 5, iclass 14, count 2 2006.161.08:15:29.57#ibcon#read 5, iclass 14, count 2 2006.161.08:15:29.57#ibcon#about to read 6, iclass 14, count 2 2006.161.08:15:29.57#ibcon#read 6, iclass 14, count 2 2006.161.08:15:29.57#ibcon#end of sib2, iclass 14, count 2 2006.161.08:15:29.57#ibcon#*mode == 0, iclass 14, count 2 2006.161.08:15:29.57#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.08:15:29.57#ibcon#[25=AT03-06\r\n] 2006.161.08:15:29.57#ibcon#*before write, iclass 14, count 2 2006.161.08:15:29.57#ibcon#enter sib2, iclass 14, count 2 2006.161.08:15:29.57#ibcon#flushed, iclass 14, count 2 2006.161.08:15:29.57#ibcon#about to write, iclass 14, count 2 2006.161.08:15:29.57#ibcon#wrote, iclass 14, count 2 2006.161.08:15:29.57#ibcon#about to read 3, iclass 14, count 2 2006.161.08:15:29.60#ibcon#read 3, iclass 14, count 2 2006.161.08:15:29.60#ibcon#about to read 4, iclass 14, count 2 2006.161.08:15:29.60#ibcon#read 4, iclass 14, count 2 2006.161.08:15:29.60#ibcon#about to read 5, iclass 14, count 2 2006.161.08:15:29.60#ibcon#read 5, iclass 14, count 2 2006.161.08:15:29.60#ibcon#about to read 6, iclass 14, count 2 2006.161.08:15:29.60#ibcon#read 6, iclass 14, count 2 2006.161.08:15:29.60#ibcon#end of sib2, iclass 14, count 2 2006.161.08:15:29.60#ibcon#*after write, iclass 14, count 2 2006.161.08:15:29.60#ibcon#*before return 0, iclass 14, count 2 2006.161.08:15:29.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:29.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:29.60#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.08:15:29.60#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:29.60#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:29.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:29.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:29.72#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:15:29.72#ibcon#first serial, iclass 14, count 0 2006.161.08:15:29.72#ibcon#enter sib2, iclass 14, count 0 2006.161.08:15:29.72#ibcon#flushed, iclass 14, count 0 2006.161.08:15:29.72#ibcon#about to write, iclass 14, count 0 2006.161.08:15:29.72#ibcon#wrote, iclass 14, count 0 2006.161.08:15:29.72#ibcon#about to read 3, iclass 14, count 0 2006.161.08:15:29.74#ibcon#read 3, iclass 14, count 0 2006.161.08:15:29.74#ibcon#about to read 4, iclass 14, count 0 2006.161.08:15:29.74#ibcon#read 4, iclass 14, count 0 2006.161.08:15:29.74#ibcon#about to read 5, iclass 14, count 0 2006.161.08:15:29.74#ibcon#read 5, iclass 14, count 0 2006.161.08:15:29.74#ibcon#about to read 6, iclass 14, count 0 2006.161.08:15:29.74#ibcon#read 6, iclass 14, count 0 2006.161.08:15:29.74#ibcon#end of sib2, iclass 14, count 0 2006.161.08:15:29.74#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:15:29.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:15:29.74#ibcon#[25=USB\r\n] 2006.161.08:15:29.74#ibcon#*before write, iclass 14, count 0 2006.161.08:15:29.74#ibcon#enter sib2, iclass 14, count 0 2006.161.08:15:29.74#ibcon#flushed, iclass 14, count 0 2006.161.08:15:29.74#ibcon#about to write, iclass 14, count 0 2006.161.08:15:29.74#ibcon#wrote, iclass 14, count 0 2006.161.08:15:29.74#ibcon#about to read 3, iclass 14, count 0 2006.161.08:15:29.77#ibcon#read 3, iclass 14, count 0 2006.161.08:15:29.77#ibcon#about to read 4, iclass 14, count 0 2006.161.08:15:29.77#ibcon#read 4, iclass 14, count 0 2006.161.08:15:29.77#ibcon#about to read 5, iclass 14, count 0 2006.161.08:15:29.77#ibcon#read 5, iclass 14, count 0 2006.161.08:15:29.77#ibcon#about to read 6, iclass 14, count 0 2006.161.08:15:29.77#ibcon#read 6, iclass 14, count 0 2006.161.08:15:29.77#ibcon#end of sib2, iclass 14, count 0 2006.161.08:15:29.77#ibcon#*after write, iclass 14, count 0 2006.161.08:15:29.77#ibcon#*before return 0, iclass 14, count 0 2006.161.08:15:29.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:29.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:29.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:15:29.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:15:29.77$vc4f8/valo=4,832.99 2006.161.08:15:29.77#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.08:15:29.77#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.08:15:29.77#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:29.77#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:15:29.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:15:29.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:15:29.77#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:15:29.77#ibcon#first serial, iclass 16, count 0 2006.161.08:15:29.77#ibcon#enter sib2, iclass 16, count 0 2006.161.08:15:29.77#ibcon#flushed, iclass 16, count 0 2006.161.08:15:29.77#ibcon#about to write, iclass 16, count 0 2006.161.08:15:29.77#ibcon#wrote, iclass 16, count 0 2006.161.08:15:29.77#ibcon#about to read 3, iclass 16, count 0 2006.161.08:15:29.79#ibcon#read 3, iclass 16, count 0 2006.161.08:15:29.79#ibcon#about to read 4, iclass 16, count 0 2006.161.08:15:29.79#ibcon#read 4, iclass 16, count 0 2006.161.08:15:29.79#ibcon#about to read 5, iclass 16, count 0 2006.161.08:15:29.79#ibcon#read 5, iclass 16, count 0 2006.161.08:15:29.79#ibcon#about to read 6, iclass 16, count 0 2006.161.08:15:29.79#ibcon#read 6, iclass 16, count 0 2006.161.08:15:29.79#ibcon#end of sib2, iclass 16, count 0 2006.161.08:15:29.79#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:15:29.79#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:15:29.79#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:15:29.79#ibcon#*before write, iclass 16, count 0 2006.161.08:15:29.79#ibcon#enter sib2, iclass 16, count 0 2006.161.08:15:29.79#ibcon#flushed, iclass 16, count 0 2006.161.08:15:29.79#ibcon#about to write, iclass 16, count 0 2006.161.08:15:29.79#ibcon#wrote, iclass 16, count 0 2006.161.08:15:29.79#ibcon#about to read 3, iclass 16, count 0 2006.161.08:15:29.83#ibcon#read 3, iclass 16, count 0 2006.161.08:15:29.83#ibcon#about to read 4, iclass 16, count 0 2006.161.08:15:29.83#ibcon#read 4, iclass 16, count 0 2006.161.08:15:29.83#ibcon#about to read 5, iclass 16, count 0 2006.161.08:15:29.83#ibcon#read 5, iclass 16, count 0 2006.161.08:15:29.83#ibcon#about to read 6, iclass 16, count 0 2006.161.08:15:29.83#ibcon#read 6, iclass 16, count 0 2006.161.08:15:29.83#ibcon#end of sib2, iclass 16, count 0 2006.161.08:15:29.83#ibcon#*after write, iclass 16, count 0 2006.161.08:15:29.83#ibcon#*before return 0, iclass 16, count 0 2006.161.08:15:29.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:15:29.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:15:29.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:15:29.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:15:29.83$vc4f8/va=4,7 2006.161.08:15:29.83#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.08:15:29.83#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.08:15:29.83#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:29.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:15:29.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:15:29.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:15:29.89#ibcon#enter wrdev, iclass 18, count 2 2006.161.08:15:29.89#ibcon#first serial, iclass 18, count 2 2006.161.08:15:29.89#ibcon#enter sib2, iclass 18, count 2 2006.161.08:15:29.89#ibcon#flushed, iclass 18, count 2 2006.161.08:15:29.89#ibcon#about to write, iclass 18, count 2 2006.161.08:15:29.89#ibcon#wrote, iclass 18, count 2 2006.161.08:15:29.89#ibcon#about to read 3, iclass 18, count 2 2006.161.08:15:29.91#ibcon#read 3, iclass 18, count 2 2006.161.08:15:29.91#ibcon#about to read 4, iclass 18, count 2 2006.161.08:15:29.91#ibcon#read 4, iclass 18, count 2 2006.161.08:15:29.91#ibcon#about to read 5, iclass 18, count 2 2006.161.08:15:29.91#ibcon#read 5, iclass 18, count 2 2006.161.08:15:29.91#ibcon#about to read 6, iclass 18, count 2 2006.161.08:15:29.91#ibcon#read 6, iclass 18, count 2 2006.161.08:15:29.91#ibcon#end of sib2, iclass 18, count 2 2006.161.08:15:29.91#ibcon#*mode == 0, iclass 18, count 2 2006.161.08:15:29.91#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.08:15:29.91#ibcon#[25=AT04-07\r\n] 2006.161.08:15:29.91#ibcon#*before write, iclass 18, count 2 2006.161.08:15:29.91#ibcon#enter sib2, iclass 18, count 2 2006.161.08:15:29.91#ibcon#flushed, iclass 18, count 2 2006.161.08:15:29.91#ibcon#about to write, iclass 18, count 2 2006.161.08:15:29.91#ibcon#wrote, iclass 18, count 2 2006.161.08:15:29.91#ibcon#about to read 3, iclass 18, count 2 2006.161.08:15:29.94#ibcon#read 3, iclass 18, count 2 2006.161.08:15:29.94#ibcon#about to read 4, iclass 18, count 2 2006.161.08:15:29.94#ibcon#read 4, iclass 18, count 2 2006.161.08:15:29.94#ibcon#about to read 5, iclass 18, count 2 2006.161.08:15:29.94#ibcon#read 5, iclass 18, count 2 2006.161.08:15:29.94#ibcon#about to read 6, iclass 18, count 2 2006.161.08:15:29.94#ibcon#read 6, iclass 18, count 2 2006.161.08:15:29.94#ibcon#end of sib2, iclass 18, count 2 2006.161.08:15:29.94#ibcon#*after write, iclass 18, count 2 2006.161.08:15:29.94#ibcon#*before return 0, iclass 18, count 2 2006.161.08:15:29.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:15:29.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:15:29.94#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.08:15:29.94#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:29.94#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:15:30.06#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:15:30.06#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:15:30.06#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:15:30.06#ibcon#first serial, iclass 18, count 0 2006.161.08:15:30.06#ibcon#enter sib2, iclass 18, count 0 2006.161.08:15:30.06#ibcon#flushed, iclass 18, count 0 2006.161.08:15:30.06#ibcon#about to write, iclass 18, count 0 2006.161.08:15:30.06#ibcon#wrote, iclass 18, count 0 2006.161.08:15:30.06#ibcon#about to read 3, iclass 18, count 0 2006.161.08:15:30.08#ibcon#read 3, iclass 18, count 0 2006.161.08:15:30.08#ibcon#about to read 4, iclass 18, count 0 2006.161.08:15:30.08#ibcon#read 4, iclass 18, count 0 2006.161.08:15:30.08#ibcon#about to read 5, iclass 18, count 0 2006.161.08:15:30.08#ibcon#read 5, iclass 18, count 0 2006.161.08:15:30.08#ibcon#about to read 6, iclass 18, count 0 2006.161.08:15:30.08#ibcon#read 6, iclass 18, count 0 2006.161.08:15:30.08#ibcon#end of sib2, iclass 18, count 0 2006.161.08:15:30.08#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:15:30.08#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:15:30.08#ibcon#[25=USB\r\n] 2006.161.08:15:30.08#ibcon#*before write, iclass 18, count 0 2006.161.08:15:30.08#ibcon#enter sib2, iclass 18, count 0 2006.161.08:15:30.08#ibcon#flushed, iclass 18, count 0 2006.161.08:15:30.08#ibcon#about to write, iclass 18, count 0 2006.161.08:15:30.08#ibcon#wrote, iclass 18, count 0 2006.161.08:15:30.08#ibcon#about to read 3, iclass 18, count 0 2006.161.08:15:30.11#ibcon#read 3, iclass 18, count 0 2006.161.08:15:30.11#ibcon#about to read 4, iclass 18, count 0 2006.161.08:15:30.11#ibcon#read 4, iclass 18, count 0 2006.161.08:15:30.11#ibcon#about to read 5, iclass 18, count 0 2006.161.08:15:30.11#ibcon#read 5, iclass 18, count 0 2006.161.08:15:30.11#ibcon#about to read 6, iclass 18, count 0 2006.161.08:15:30.11#ibcon#read 6, iclass 18, count 0 2006.161.08:15:30.11#ibcon#end of sib2, iclass 18, count 0 2006.161.08:15:30.11#ibcon#*after write, iclass 18, count 0 2006.161.08:15:30.11#ibcon#*before return 0, iclass 18, count 0 2006.161.08:15:30.11#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:15:30.11#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:15:30.11#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:15:30.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:15:30.11$vc4f8/valo=5,652.99 2006.161.08:15:30.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.08:15:30.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.08:15:30.11#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:30.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:30.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:30.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:30.11#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:15:30.11#ibcon#first serial, iclass 20, count 0 2006.161.08:15:30.11#ibcon#enter sib2, iclass 20, count 0 2006.161.08:15:30.11#ibcon#flushed, iclass 20, count 0 2006.161.08:15:30.11#ibcon#about to write, iclass 20, count 0 2006.161.08:15:30.11#ibcon#wrote, iclass 20, count 0 2006.161.08:15:30.11#ibcon#about to read 3, iclass 20, count 0 2006.161.08:15:30.13#ibcon#read 3, iclass 20, count 0 2006.161.08:15:30.13#ibcon#about to read 4, iclass 20, count 0 2006.161.08:15:30.13#ibcon#read 4, iclass 20, count 0 2006.161.08:15:30.13#ibcon#about to read 5, iclass 20, count 0 2006.161.08:15:30.13#ibcon#read 5, iclass 20, count 0 2006.161.08:15:30.13#ibcon#about to read 6, iclass 20, count 0 2006.161.08:15:30.13#ibcon#read 6, iclass 20, count 0 2006.161.08:15:30.13#ibcon#end of sib2, iclass 20, count 0 2006.161.08:15:30.13#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:15:30.13#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:15:30.13#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:15:30.13#ibcon#*before write, iclass 20, count 0 2006.161.08:15:30.13#ibcon#enter sib2, iclass 20, count 0 2006.161.08:15:30.13#ibcon#flushed, iclass 20, count 0 2006.161.08:15:30.13#ibcon#about to write, iclass 20, count 0 2006.161.08:15:30.13#ibcon#wrote, iclass 20, count 0 2006.161.08:15:30.13#ibcon#about to read 3, iclass 20, count 0 2006.161.08:15:30.17#ibcon#read 3, iclass 20, count 0 2006.161.08:15:30.17#ibcon#about to read 4, iclass 20, count 0 2006.161.08:15:30.17#ibcon#read 4, iclass 20, count 0 2006.161.08:15:30.17#ibcon#about to read 5, iclass 20, count 0 2006.161.08:15:30.17#ibcon#read 5, iclass 20, count 0 2006.161.08:15:30.17#ibcon#about to read 6, iclass 20, count 0 2006.161.08:15:30.17#ibcon#read 6, iclass 20, count 0 2006.161.08:15:30.17#ibcon#end of sib2, iclass 20, count 0 2006.161.08:15:30.17#ibcon#*after write, iclass 20, count 0 2006.161.08:15:30.17#ibcon#*before return 0, iclass 20, count 0 2006.161.08:15:30.17#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:30.17#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:30.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:15:30.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:15:30.17$vc4f8/va=5,7 2006.161.08:15:30.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.08:15:30.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.08:15:30.17#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:30.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:30.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:30.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:30.23#ibcon#enter wrdev, iclass 22, count 2 2006.161.08:15:30.23#ibcon#first serial, iclass 22, count 2 2006.161.08:15:30.23#ibcon#enter sib2, iclass 22, count 2 2006.161.08:15:30.23#ibcon#flushed, iclass 22, count 2 2006.161.08:15:30.23#ibcon#about to write, iclass 22, count 2 2006.161.08:15:30.23#ibcon#wrote, iclass 22, count 2 2006.161.08:15:30.23#ibcon#about to read 3, iclass 22, count 2 2006.161.08:15:30.25#ibcon#read 3, iclass 22, count 2 2006.161.08:15:30.25#ibcon#about to read 4, iclass 22, count 2 2006.161.08:15:30.25#ibcon#read 4, iclass 22, count 2 2006.161.08:15:30.25#ibcon#about to read 5, iclass 22, count 2 2006.161.08:15:30.25#ibcon#read 5, iclass 22, count 2 2006.161.08:15:30.25#ibcon#about to read 6, iclass 22, count 2 2006.161.08:15:30.25#ibcon#read 6, iclass 22, count 2 2006.161.08:15:30.25#ibcon#end of sib2, iclass 22, count 2 2006.161.08:15:30.25#ibcon#*mode == 0, iclass 22, count 2 2006.161.08:15:30.25#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.08:15:30.25#ibcon#[25=AT05-07\r\n] 2006.161.08:15:30.25#ibcon#*before write, iclass 22, count 2 2006.161.08:15:30.25#ibcon#enter sib2, iclass 22, count 2 2006.161.08:15:30.25#ibcon#flushed, iclass 22, count 2 2006.161.08:15:30.25#ibcon#about to write, iclass 22, count 2 2006.161.08:15:30.25#ibcon#wrote, iclass 22, count 2 2006.161.08:15:30.25#ibcon#about to read 3, iclass 22, count 2 2006.161.08:15:30.28#ibcon#read 3, iclass 22, count 2 2006.161.08:15:30.28#ibcon#about to read 4, iclass 22, count 2 2006.161.08:15:30.28#ibcon#read 4, iclass 22, count 2 2006.161.08:15:30.28#ibcon#about to read 5, iclass 22, count 2 2006.161.08:15:30.28#ibcon#read 5, iclass 22, count 2 2006.161.08:15:30.28#ibcon#about to read 6, iclass 22, count 2 2006.161.08:15:30.28#ibcon#read 6, iclass 22, count 2 2006.161.08:15:30.28#ibcon#end of sib2, iclass 22, count 2 2006.161.08:15:30.28#ibcon#*after write, iclass 22, count 2 2006.161.08:15:30.28#ibcon#*before return 0, iclass 22, count 2 2006.161.08:15:30.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:30.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:30.28#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.08:15:30.28#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:30.28#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:30.41#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:30.41#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:30.41#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:15:30.41#ibcon#first serial, iclass 22, count 0 2006.161.08:15:30.41#ibcon#enter sib2, iclass 22, count 0 2006.161.08:15:30.41#ibcon#flushed, iclass 22, count 0 2006.161.08:15:30.41#ibcon#about to write, iclass 22, count 0 2006.161.08:15:30.41#ibcon#wrote, iclass 22, count 0 2006.161.08:15:30.41#ibcon#about to read 3, iclass 22, count 0 2006.161.08:15:30.43#ibcon#read 3, iclass 22, count 0 2006.161.08:15:30.43#ibcon#about to read 4, iclass 22, count 0 2006.161.08:15:30.43#ibcon#read 4, iclass 22, count 0 2006.161.08:15:30.43#ibcon#about to read 5, iclass 22, count 0 2006.161.08:15:30.43#ibcon#read 5, iclass 22, count 0 2006.161.08:15:30.43#ibcon#about to read 6, iclass 22, count 0 2006.161.08:15:30.43#ibcon#read 6, iclass 22, count 0 2006.161.08:15:30.43#ibcon#end of sib2, iclass 22, count 0 2006.161.08:15:30.43#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:15:30.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:15:30.43#ibcon#[25=USB\r\n] 2006.161.08:15:30.43#ibcon#*before write, iclass 22, count 0 2006.161.08:15:30.43#ibcon#enter sib2, iclass 22, count 0 2006.161.08:15:30.43#ibcon#flushed, iclass 22, count 0 2006.161.08:15:30.43#ibcon#about to write, iclass 22, count 0 2006.161.08:15:30.43#ibcon#wrote, iclass 22, count 0 2006.161.08:15:30.43#ibcon#about to read 3, iclass 22, count 0 2006.161.08:15:30.46#ibcon#read 3, iclass 22, count 0 2006.161.08:15:30.46#ibcon#about to read 4, iclass 22, count 0 2006.161.08:15:30.46#ibcon#read 4, iclass 22, count 0 2006.161.08:15:30.46#ibcon#about to read 5, iclass 22, count 0 2006.161.08:15:30.46#ibcon#read 5, iclass 22, count 0 2006.161.08:15:30.46#ibcon#about to read 6, iclass 22, count 0 2006.161.08:15:30.46#ibcon#read 6, iclass 22, count 0 2006.161.08:15:30.46#ibcon#end of sib2, iclass 22, count 0 2006.161.08:15:30.46#ibcon#*after write, iclass 22, count 0 2006.161.08:15:30.46#ibcon#*before return 0, iclass 22, count 0 2006.161.08:15:30.46#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:30.46#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:30.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:15:30.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:15:30.46$vc4f8/valo=6,772.99 2006.161.08:15:30.46#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:15:30.46#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:15:30.46#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:30.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:30.46#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:30.46#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:30.46#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:15:30.46#ibcon#first serial, iclass 24, count 0 2006.161.08:15:30.46#ibcon#enter sib2, iclass 24, count 0 2006.161.08:15:30.46#ibcon#flushed, iclass 24, count 0 2006.161.08:15:30.46#ibcon#about to write, iclass 24, count 0 2006.161.08:15:30.46#ibcon#wrote, iclass 24, count 0 2006.161.08:15:30.46#ibcon#about to read 3, iclass 24, count 0 2006.161.08:15:30.48#ibcon#read 3, iclass 24, count 0 2006.161.08:15:30.48#ibcon#about to read 4, iclass 24, count 0 2006.161.08:15:30.48#ibcon#read 4, iclass 24, count 0 2006.161.08:15:30.48#ibcon#about to read 5, iclass 24, count 0 2006.161.08:15:30.48#ibcon#read 5, iclass 24, count 0 2006.161.08:15:30.48#ibcon#about to read 6, iclass 24, count 0 2006.161.08:15:30.48#ibcon#read 6, iclass 24, count 0 2006.161.08:15:30.48#ibcon#end of sib2, iclass 24, count 0 2006.161.08:15:30.48#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:15:30.48#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:15:30.48#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:15:30.48#ibcon#*before write, iclass 24, count 0 2006.161.08:15:30.48#ibcon#enter sib2, iclass 24, count 0 2006.161.08:15:30.48#ibcon#flushed, iclass 24, count 0 2006.161.08:15:30.48#ibcon#about to write, iclass 24, count 0 2006.161.08:15:30.48#ibcon#wrote, iclass 24, count 0 2006.161.08:15:30.48#ibcon#about to read 3, iclass 24, count 0 2006.161.08:15:30.52#ibcon#read 3, iclass 24, count 0 2006.161.08:15:30.52#ibcon#about to read 4, iclass 24, count 0 2006.161.08:15:30.52#ibcon#read 4, iclass 24, count 0 2006.161.08:15:30.52#ibcon#about to read 5, iclass 24, count 0 2006.161.08:15:30.52#ibcon#read 5, iclass 24, count 0 2006.161.08:15:30.52#ibcon#about to read 6, iclass 24, count 0 2006.161.08:15:30.52#ibcon#read 6, iclass 24, count 0 2006.161.08:15:30.52#ibcon#end of sib2, iclass 24, count 0 2006.161.08:15:30.52#ibcon#*after write, iclass 24, count 0 2006.161.08:15:30.52#ibcon#*before return 0, iclass 24, count 0 2006.161.08:15:30.52#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:30.52#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:30.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:15:30.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:15:30.52$vc4f8/va=6,6 2006.161.08:15:30.52#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:15:30.52#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:15:30.52#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:30.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:30.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:30.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:30.58#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:15:30.58#ibcon#first serial, iclass 26, count 2 2006.161.08:15:30.58#ibcon#enter sib2, iclass 26, count 2 2006.161.08:15:30.58#ibcon#flushed, iclass 26, count 2 2006.161.08:15:30.58#ibcon#about to write, iclass 26, count 2 2006.161.08:15:30.58#ibcon#wrote, iclass 26, count 2 2006.161.08:15:30.58#ibcon#about to read 3, iclass 26, count 2 2006.161.08:15:30.60#ibcon#read 3, iclass 26, count 2 2006.161.08:15:30.60#ibcon#about to read 4, iclass 26, count 2 2006.161.08:15:30.60#ibcon#read 4, iclass 26, count 2 2006.161.08:15:30.60#ibcon#about to read 5, iclass 26, count 2 2006.161.08:15:30.60#ibcon#read 5, iclass 26, count 2 2006.161.08:15:30.60#ibcon#about to read 6, iclass 26, count 2 2006.161.08:15:30.60#ibcon#read 6, iclass 26, count 2 2006.161.08:15:30.60#ibcon#end of sib2, iclass 26, count 2 2006.161.08:15:30.60#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:15:30.60#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:15:30.60#ibcon#[25=AT06-06\r\n] 2006.161.08:15:30.60#ibcon#*before write, iclass 26, count 2 2006.161.08:15:30.60#ibcon#enter sib2, iclass 26, count 2 2006.161.08:15:30.60#ibcon#flushed, iclass 26, count 2 2006.161.08:15:30.60#ibcon#about to write, iclass 26, count 2 2006.161.08:15:30.60#ibcon#wrote, iclass 26, count 2 2006.161.08:15:30.60#ibcon#about to read 3, iclass 26, count 2 2006.161.08:15:30.63#ibcon#read 3, iclass 26, count 2 2006.161.08:15:30.63#ibcon#about to read 4, iclass 26, count 2 2006.161.08:15:30.63#ibcon#read 4, iclass 26, count 2 2006.161.08:15:30.63#ibcon#about to read 5, iclass 26, count 2 2006.161.08:15:30.63#ibcon#read 5, iclass 26, count 2 2006.161.08:15:30.63#ibcon#about to read 6, iclass 26, count 2 2006.161.08:15:30.63#ibcon#read 6, iclass 26, count 2 2006.161.08:15:30.63#ibcon#end of sib2, iclass 26, count 2 2006.161.08:15:30.63#ibcon#*after write, iclass 26, count 2 2006.161.08:15:30.63#ibcon#*before return 0, iclass 26, count 2 2006.161.08:15:30.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:30.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:30.63#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:15:30.63#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:30.63#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:30.75#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:30.75#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:30.75#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:15:30.75#ibcon#first serial, iclass 26, count 0 2006.161.08:15:30.75#ibcon#enter sib2, iclass 26, count 0 2006.161.08:15:30.75#ibcon#flushed, iclass 26, count 0 2006.161.08:15:30.75#ibcon#about to write, iclass 26, count 0 2006.161.08:15:30.75#ibcon#wrote, iclass 26, count 0 2006.161.08:15:30.75#ibcon#about to read 3, iclass 26, count 0 2006.161.08:15:30.77#ibcon#read 3, iclass 26, count 0 2006.161.08:15:30.77#ibcon#about to read 4, iclass 26, count 0 2006.161.08:15:30.77#ibcon#read 4, iclass 26, count 0 2006.161.08:15:30.77#ibcon#about to read 5, iclass 26, count 0 2006.161.08:15:30.77#ibcon#read 5, iclass 26, count 0 2006.161.08:15:30.77#ibcon#about to read 6, iclass 26, count 0 2006.161.08:15:30.77#ibcon#read 6, iclass 26, count 0 2006.161.08:15:30.77#ibcon#end of sib2, iclass 26, count 0 2006.161.08:15:30.77#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:15:30.77#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:15:30.77#ibcon#[25=USB\r\n] 2006.161.08:15:30.77#ibcon#*before write, iclass 26, count 0 2006.161.08:15:30.77#ibcon#enter sib2, iclass 26, count 0 2006.161.08:15:30.77#ibcon#flushed, iclass 26, count 0 2006.161.08:15:30.77#ibcon#about to write, iclass 26, count 0 2006.161.08:15:30.77#ibcon#wrote, iclass 26, count 0 2006.161.08:15:30.77#ibcon#about to read 3, iclass 26, count 0 2006.161.08:15:30.80#ibcon#read 3, iclass 26, count 0 2006.161.08:15:30.80#ibcon#about to read 4, iclass 26, count 0 2006.161.08:15:30.80#ibcon#read 4, iclass 26, count 0 2006.161.08:15:30.80#ibcon#about to read 5, iclass 26, count 0 2006.161.08:15:30.80#ibcon#read 5, iclass 26, count 0 2006.161.08:15:30.80#ibcon#about to read 6, iclass 26, count 0 2006.161.08:15:30.80#ibcon#read 6, iclass 26, count 0 2006.161.08:15:30.80#ibcon#end of sib2, iclass 26, count 0 2006.161.08:15:30.80#ibcon#*after write, iclass 26, count 0 2006.161.08:15:30.80#ibcon#*before return 0, iclass 26, count 0 2006.161.08:15:30.80#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:30.80#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:30.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:15:30.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:15:30.80$vc4f8/valo=7,832.99 2006.161.08:15:30.80#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:15:30.80#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:15:30.80#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:30.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:30.80#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:30.80#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:30.80#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:15:30.80#ibcon#first serial, iclass 28, count 0 2006.161.08:15:30.80#ibcon#enter sib2, iclass 28, count 0 2006.161.08:15:30.80#ibcon#flushed, iclass 28, count 0 2006.161.08:15:30.80#ibcon#about to write, iclass 28, count 0 2006.161.08:15:30.80#ibcon#wrote, iclass 28, count 0 2006.161.08:15:30.80#ibcon#about to read 3, iclass 28, count 0 2006.161.08:15:30.82#ibcon#read 3, iclass 28, count 0 2006.161.08:15:30.82#ibcon#about to read 4, iclass 28, count 0 2006.161.08:15:30.82#ibcon#read 4, iclass 28, count 0 2006.161.08:15:30.82#ibcon#about to read 5, iclass 28, count 0 2006.161.08:15:30.82#ibcon#read 5, iclass 28, count 0 2006.161.08:15:30.82#ibcon#about to read 6, iclass 28, count 0 2006.161.08:15:30.82#ibcon#read 6, iclass 28, count 0 2006.161.08:15:30.82#ibcon#end of sib2, iclass 28, count 0 2006.161.08:15:30.82#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:15:30.82#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:15:30.82#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:15:30.82#ibcon#*before write, iclass 28, count 0 2006.161.08:15:30.82#ibcon#enter sib2, iclass 28, count 0 2006.161.08:15:30.82#ibcon#flushed, iclass 28, count 0 2006.161.08:15:30.82#ibcon#about to write, iclass 28, count 0 2006.161.08:15:30.82#ibcon#wrote, iclass 28, count 0 2006.161.08:15:30.82#ibcon#about to read 3, iclass 28, count 0 2006.161.08:15:30.86#ibcon#read 3, iclass 28, count 0 2006.161.08:15:30.86#ibcon#about to read 4, iclass 28, count 0 2006.161.08:15:30.86#ibcon#read 4, iclass 28, count 0 2006.161.08:15:30.86#ibcon#about to read 5, iclass 28, count 0 2006.161.08:15:30.86#ibcon#read 5, iclass 28, count 0 2006.161.08:15:30.86#ibcon#about to read 6, iclass 28, count 0 2006.161.08:15:30.86#ibcon#read 6, iclass 28, count 0 2006.161.08:15:30.86#ibcon#end of sib2, iclass 28, count 0 2006.161.08:15:30.86#ibcon#*after write, iclass 28, count 0 2006.161.08:15:30.86#ibcon#*before return 0, iclass 28, count 0 2006.161.08:15:30.86#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:30.86#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:30.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:15:30.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:15:30.86$vc4f8/va=7,6 2006.161.08:15:30.86#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.08:15:30.86#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.08:15:30.86#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:30.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:30.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:30.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:30.92#ibcon#enter wrdev, iclass 30, count 2 2006.161.08:15:30.92#ibcon#first serial, iclass 30, count 2 2006.161.08:15:30.92#ibcon#enter sib2, iclass 30, count 2 2006.161.08:15:30.92#ibcon#flushed, iclass 30, count 2 2006.161.08:15:30.92#ibcon#about to write, iclass 30, count 2 2006.161.08:15:30.92#ibcon#wrote, iclass 30, count 2 2006.161.08:15:30.92#ibcon#about to read 3, iclass 30, count 2 2006.161.08:15:30.94#ibcon#read 3, iclass 30, count 2 2006.161.08:15:30.94#ibcon#about to read 4, iclass 30, count 2 2006.161.08:15:30.94#ibcon#read 4, iclass 30, count 2 2006.161.08:15:30.94#ibcon#about to read 5, iclass 30, count 2 2006.161.08:15:30.94#ibcon#read 5, iclass 30, count 2 2006.161.08:15:30.94#ibcon#about to read 6, iclass 30, count 2 2006.161.08:15:30.94#ibcon#read 6, iclass 30, count 2 2006.161.08:15:30.94#ibcon#end of sib2, iclass 30, count 2 2006.161.08:15:30.94#ibcon#*mode == 0, iclass 30, count 2 2006.161.08:15:30.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.08:15:30.94#ibcon#[25=AT07-06\r\n] 2006.161.08:15:30.94#ibcon#*before write, iclass 30, count 2 2006.161.08:15:30.94#ibcon#enter sib2, iclass 30, count 2 2006.161.08:15:30.94#ibcon#flushed, iclass 30, count 2 2006.161.08:15:30.94#ibcon#about to write, iclass 30, count 2 2006.161.08:15:30.94#ibcon#wrote, iclass 30, count 2 2006.161.08:15:30.94#ibcon#about to read 3, iclass 30, count 2 2006.161.08:15:30.97#ibcon#read 3, iclass 30, count 2 2006.161.08:15:30.97#ibcon#about to read 4, iclass 30, count 2 2006.161.08:15:30.97#ibcon#read 4, iclass 30, count 2 2006.161.08:15:30.97#ibcon#about to read 5, iclass 30, count 2 2006.161.08:15:30.97#ibcon#read 5, iclass 30, count 2 2006.161.08:15:30.97#ibcon#about to read 6, iclass 30, count 2 2006.161.08:15:30.97#ibcon#read 6, iclass 30, count 2 2006.161.08:15:30.97#ibcon#end of sib2, iclass 30, count 2 2006.161.08:15:30.97#ibcon#*after write, iclass 30, count 2 2006.161.08:15:30.97#ibcon#*before return 0, iclass 30, count 2 2006.161.08:15:30.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:30.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:30.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.08:15:30.97#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:30.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:15:31.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:15:31.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:15:31.09#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:15:31.09#ibcon#first serial, iclass 30, count 0 2006.161.08:15:31.09#ibcon#enter sib2, iclass 30, count 0 2006.161.08:15:31.09#ibcon#flushed, iclass 30, count 0 2006.161.08:15:31.09#ibcon#about to write, iclass 30, count 0 2006.161.08:15:31.09#ibcon#wrote, iclass 30, count 0 2006.161.08:15:31.09#ibcon#about to read 3, iclass 30, count 0 2006.161.08:15:31.11#ibcon#read 3, iclass 30, count 0 2006.161.08:15:31.11#ibcon#about to read 4, iclass 30, count 0 2006.161.08:15:31.11#ibcon#read 4, iclass 30, count 0 2006.161.08:15:31.11#ibcon#about to read 5, iclass 30, count 0 2006.161.08:15:31.11#ibcon#read 5, iclass 30, count 0 2006.161.08:15:31.11#ibcon#about to read 6, iclass 30, count 0 2006.161.08:15:31.11#ibcon#read 6, iclass 30, count 0 2006.161.08:15:31.11#ibcon#end of sib2, iclass 30, count 0 2006.161.08:15:31.11#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:15:31.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:15:31.11#ibcon#[25=USB\r\n] 2006.161.08:15:31.11#ibcon#*before write, iclass 30, count 0 2006.161.08:15:31.11#ibcon#enter sib2, iclass 30, count 0 2006.161.08:15:31.11#ibcon#flushed, iclass 30, count 0 2006.161.08:15:31.11#ibcon#about to write, iclass 30, count 0 2006.161.08:15:31.11#ibcon#wrote, iclass 30, count 0 2006.161.08:15:31.11#ibcon#about to read 3, iclass 30, count 0 2006.161.08:15:31.14#ibcon#read 3, iclass 30, count 0 2006.161.08:15:31.14#ibcon#about to read 4, iclass 30, count 0 2006.161.08:15:31.14#ibcon#read 4, iclass 30, count 0 2006.161.08:15:31.14#ibcon#about to read 5, iclass 30, count 0 2006.161.08:15:31.14#ibcon#read 5, iclass 30, count 0 2006.161.08:15:31.14#ibcon#about to read 6, iclass 30, count 0 2006.161.08:15:31.14#ibcon#read 6, iclass 30, count 0 2006.161.08:15:31.14#ibcon#end of sib2, iclass 30, count 0 2006.161.08:15:31.14#ibcon#*after write, iclass 30, count 0 2006.161.08:15:31.14#ibcon#*before return 0, iclass 30, count 0 2006.161.08:15:31.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:15:31.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:15:31.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:15:31.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:15:31.14$vc4f8/valo=8,852.99 2006.161.08:15:31.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.08:15:31.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.08:15:31.14#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:31.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:15:31.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:15:31.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:15:31.14#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:15:31.14#ibcon#first serial, iclass 32, count 0 2006.161.08:15:31.14#ibcon#enter sib2, iclass 32, count 0 2006.161.08:15:31.14#ibcon#flushed, iclass 32, count 0 2006.161.08:15:31.14#ibcon#about to write, iclass 32, count 0 2006.161.08:15:31.14#ibcon#wrote, iclass 32, count 0 2006.161.08:15:31.14#ibcon#about to read 3, iclass 32, count 0 2006.161.08:15:31.16#ibcon#read 3, iclass 32, count 0 2006.161.08:15:31.16#ibcon#about to read 4, iclass 32, count 0 2006.161.08:15:31.16#ibcon#read 4, iclass 32, count 0 2006.161.08:15:31.16#ibcon#about to read 5, iclass 32, count 0 2006.161.08:15:31.16#ibcon#read 5, iclass 32, count 0 2006.161.08:15:31.16#ibcon#about to read 6, iclass 32, count 0 2006.161.08:15:31.16#ibcon#read 6, iclass 32, count 0 2006.161.08:15:31.16#ibcon#end of sib2, iclass 32, count 0 2006.161.08:15:31.16#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:15:31.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:15:31.16#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:15:31.16#ibcon#*before write, iclass 32, count 0 2006.161.08:15:31.16#ibcon#enter sib2, iclass 32, count 0 2006.161.08:15:31.16#ibcon#flushed, iclass 32, count 0 2006.161.08:15:31.16#ibcon#about to write, iclass 32, count 0 2006.161.08:15:31.16#ibcon#wrote, iclass 32, count 0 2006.161.08:15:31.16#ibcon#about to read 3, iclass 32, count 0 2006.161.08:15:31.20#ibcon#read 3, iclass 32, count 0 2006.161.08:15:31.20#ibcon#about to read 4, iclass 32, count 0 2006.161.08:15:31.20#ibcon#read 4, iclass 32, count 0 2006.161.08:15:31.20#ibcon#about to read 5, iclass 32, count 0 2006.161.08:15:31.20#ibcon#read 5, iclass 32, count 0 2006.161.08:15:31.20#ibcon#about to read 6, iclass 32, count 0 2006.161.08:15:31.20#ibcon#read 6, iclass 32, count 0 2006.161.08:15:31.20#ibcon#end of sib2, iclass 32, count 0 2006.161.08:15:31.20#ibcon#*after write, iclass 32, count 0 2006.161.08:15:31.20#ibcon#*before return 0, iclass 32, count 0 2006.161.08:15:31.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:15:31.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:15:31.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:15:31.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:15:31.20$vc4f8/va=8,7 2006.161.08:15:31.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.08:15:31.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.08:15:31.20#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:31.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:15:31.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:15:31.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:15:31.26#ibcon#enter wrdev, iclass 34, count 2 2006.161.08:15:31.26#ibcon#first serial, iclass 34, count 2 2006.161.08:15:31.26#ibcon#enter sib2, iclass 34, count 2 2006.161.08:15:31.26#ibcon#flushed, iclass 34, count 2 2006.161.08:15:31.26#ibcon#about to write, iclass 34, count 2 2006.161.08:15:31.26#ibcon#wrote, iclass 34, count 2 2006.161.08:15:31.26#ibcon#about to read 3, iclass 34, count 2 2006.161.08:15:31.28#ibcon#read 3, iclass 34, count 2 2006.161.08:15:31.28#ibcon#about to read 4, iclass 34, count 2 2006.161.08:15:31.28#ibcon#read 4, iclass 34, count 2 2006.161.08:15:31.28#ibcon#about to read 5, iclass 34, count 2 2006.161.08:15:31.28#ibcon#read 5, iclass 34, count 2 2006.161.08:15:31.28#ibcon#about to read 6, iclass 34, count 2 2006.161.08:15:31.28#ibcon#read 6, iclass 34, count 2 2006.161.08:15:31.28#ibcon#end of sib2, iclass 34, count 2 2006.161.08:15:31.28#ibcon#*mode == 0, iclass 34, count 2 2006.161.08:15:31.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.08:15:31.28#ibcon#[25=AT08-07\r\n] 2006.161.08:15:31.28#ibcon#*before write, iclass 34, count 2 2006.161.08:15:31.28#ibcon#enter sib2, iclass 34, count 2 2006.161.08:15:31.28#ibcon#flushed, iclass 34, count 2 2006.161.08:15:31.28#ibcon#about to write, iclass 34, count 2 2006.161.08:15:31.28#ibcon#wrote, iclass 34, count 2 2006.161.08:15:31.28#ibcon#about to read 3, iclass 34, count 2 2006.161.08:15:31.31#ibcon#read 3, iclass 34, count 2 2006.161.08:15:31.31#ibcon#about to read 4, iclass 34, count 2 2006.161.08:15:31.31#ibcon#read 4, iclass 34, count 2 2006.161.08:15:31.31#ibcon#about to read 5, iclass 34, count 2 2006.161.08:15:31.31#ibcon#read 5, iclass 34, count 2 2006.161.08:15:31.31#ibcon#about to read 6, iclass 34, count 2 2006.161.08:15:31.31#ibcon#read 6, iclass 34, count 2 2006.161.08:15:31.31#ibcon#end of sib2, iclass 34, count 2 2006.161.08:15:31.31#ibcon#*after write, iclass 34, count 2 2006.161.08:15:31.31#ibcon#*before return 0, iclass 34, count 2 2006.161.08:15:31.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:15:31.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:15:31.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.08:15:31.31#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:31.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:15:31.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:15:31.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:15:31.43#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:15:31.43#ibcon#first serial, iclass 34, count 0 2006.161.08:15:31.43#ibcon#enter sib2, iclass 34, count 0 2006.161.08:15:31.43#ibcon#flushed, iclass 34, count 0 2006.161.08:15:31.43#ibcon#about to write, iclass 34, count 0 2006.161.08:15:31.43#ibcon#wrote, iclass 34, count 0 2006.161.08:15:31.43#ibcon#about to read 3, iclass 34, count 0 2006.161.08:15:31.45#ibcon#read 3, iclass 34, count 0 2006.161.08:15:31.45#ibcon#about to read 4, iclass 34, count 0 2006.161.08:15:31.45#ibcon#read 4, iclass 34, count 0 2006.161.08:15:31.45#ibcon#about to read 5, iclass 34, count 0 2006.161.08:15:31.45#ibcon#read 5, iclass 34, count 0 2006.161.08:15:31.45#ibcon#about to read 6, iclass 34, count 0 2006.161.08:15:31.45#ibcon#read 6, iclass 34, count 0 2006.161.08:15:31.45#ibcon#end of sib2, iclass 34, count 0 2006.161.08:15:31.45#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:15:31.45#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:15:31.45#ibcon#[25=USB\r\n] 2006.161.08:15:31.45#ibcon#*before write, iclass 34, count 0 2006.161.08:15:31.45#ibcon#enter sib2, iclass 34, count 0 2006.161.08:15:31.45#ibcon#flushed, iclass 34, count 0 2006.161.08:15:31.45#ibcon#about to write, iclass 34, count 0 2006.161.08:15:31.45#ibcon#wrote, iclass 34, count 0 2006.161.08:15:31.45#ibcon#about to read 3, iclass 34, count 0 2006.161.08:15:31.48#ibcon#read 3, iclass 34, count 0 2006.161.08:15:31.48#ibcon#about to read 4, iclass 34, count 0 2006.161.08:15:31.48#ibcon#read 4, iclass 34, count 0 2006.161.08:15:31.48#ibcon#about to read 5, iclass 34, count 0 2006.161.08:15:31.48#ibcon#read 5, iclass 34, count 0 2006.161.08:15:31.48#ibcon#about to read 6, iclass 34, count 0 2006.161.08:15:31.48#ibcon#read 6, iclass 34, count 0 2006.161.08:15:31.48#ibcon#end of sib2, iclass 34, count 0 2006.161.08:15:31.48#ibcon#*after write, iclass 34, count 0 2006.161.08:15:31.48#ibcon#*before return 0, iclass 34, count 0 2006.161.08:15:31.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:15:31.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:15:31.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:15:31.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:15:31.48$vc4f8/vblo=1,632.99 2006.161.08:15:31.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:15:31.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:15:31.48#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:31.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:15:31.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:15:31.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:15:31.48#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:15:31.48#ibcon#first serial, iclass 36, count 0 2006.161.08:15:31.48#ibcon#enter sib2, iclass 36, count 0 2006.161.08:15:31.48#ibcon#flushed, iclass 36, count 0 2006.161.08:15:31.48#ibcon#about to write, iclass 36, count 0 2006.161.08:15:31.48#ibcon#wrote, iclass 36, count 0 2006.161.08:15:31.48#ibcon#about to read 3, iclass 36, count 0 2006.161.08:15:31.50#ibcon#read 3, iclass 36, count 0 2006.161.08:15:31.50#ibcon#about to read 4, iclass 36, count 0 2006.161.08:15:31.50#ibcon#read 4, iclass 36, count 0 2006.161.08:15:31.50#ibcon#about to read 5, iclass 36, count 0 2006.161.08:15:31.50#ibcon#read 5, iclass 36, count 0 2006.161.08:15:31.50#ibcon#about to read 6, iclass 36, count 0 2006.161.08:15:31.50#ibcon#read 6, iclass 36, count 0 2006.161.08:15:31.50#ibcon#end of sib2, iclass 36, count 0 2006.161.08:15:31.50#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:15:31.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:15:31.50#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:15:31.50#ibcon#*before write, iclass 36, count 0 2006.161.08:15:31.50#ibcon#enter sib2, iclass 36, count 0 2006.161.08:15:31.50#ibcon#flushed, iclass 36, count 0 2006.161.08:15:31.50#ibcon#about to write, iclass 36, count 0 2006.161.08:15:31.50#ibcon#wrote, iclass 36, count 0 2006.161.08:15:31.50#ibcon#about to read 3, iclass 36, count 0 2006.161.08:15:31.54#ibcon#read 3, iclass 36, count 0 2006.161.08:15:31.54#ibcon#about to read 4, iclass 36, count 0 2006.161.08:15:31.54#ibcon#read 4, iclass 36, count 0 2006.161.08:15:31.54#ibcon#about to read 5, iclass 36, count 0 2006.161.08:15:31.54#ibcon#read 5, iclass 36, count 0 2006.161.08:15:31.54#ibcon#about to read 6, iclass 36, count 0 2006.161.08:15:31.54#ibcon#read 6, iclass 36, count 0 2006.161.08:15:31.54#ibcon#end of sib2, iclass 36, count 0 2006.161.08:15:31.54#ibcon#*after write, iclass 36, count 0 2006.161.08:15:31.54#ibcon#*before return 0, iclass 36, count 0 2006.161.08:15:31.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:15:31.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:15:31.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:15:31.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:15:31.54$vc4f8/vb=1,4 2006.161.08:15:31.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.08:15:31.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.08:15:31.54#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:31.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:15:31.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:15:31.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:15:31.54#ibcon#enter wrdev, iclass 38, count 2 2006.161.08:15:31.54#ibcon#first serial, iclass 38, count 2 2006.161.08:15:31.54#ibcon#enter sib2, iclass 38, count 2 2006.161.08:15:31.54#ibcon#flushed, iclass 38, count 2 2006.161.08:15:31.54#ibcon#about to write, iclass 38, count 2 2006.161.08:15:31.54#ibcon#wrote, iclass 38, count 2 2006.161.08:15:31.54#ibcon#about to read 3, iclass 38, count 2 2006.161.08:15:31.56#ibcon#read 3, iclass 38, count 2 2006.161.08:15:31.56#ibcon#about to read 4, iclass 38, count 2 2006.161.08:15:31.56#ibcon#read 4, iclass 38, count 2 2006.161.08:15:31.56#ibcon#about to read 5, iclass 38, count 2 2006.161.08:15:31.56#ibcon#read 5, iclass 38, count 2 2006.161.08:15:31.56#ibcon#about to read 6, iclass 38, count 2 2006.161.08:15:31.56#ibcon#read 6, iclass 38, count 2 2006.161.08:15:31.56#ibcon#end of sib2, iclass 38, count 2 2006.161.08:15:31.56#ibcon#*mode == 0, iclass 38, count 2 2006.161.08:15:31.56#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.08:15:31.56#ibcon#[27=AT01-04\r\n] 2006.161.08:15:31.56#ibcon#*before write, iclass 38, count 2 2006.161.08:15:31.56#ibcon#enter sib2, iclass 38, count 2 2006.161.08:15:31.56#ibcon#flushed, iclass 38, count 2 2006.161.08:15:31.56#ibcon#about to write, iclass 38, count 2 2006.161.08:15:31.56#ibcon#wrote, iclass 38, count 2 2006.161.08:15:31.56#ibcon#about to read 3, iclass 38, count 2 2006.161.08:15:31.59#ibcon#read 3, iclass 38, count 2 2006.161.08:15:31.59#ibcon#about to read 4, iclass 38, count 2 2006.161.08:15:31.59#ibcon#read 4, iclass 38, count 2 2006.161.08:15:31.59#ibcon#about to read 5, iclass 38, count 2 2006.161.08:15:31.59#ibcon#read 5, iclass 38, count 2 2006.161.08:15:31.59#ibcon#about to read 6, iclass 38, count 2 2006.161.08:15:31.59#ibcon#read 6, iclass 38, count 2 2006.161.08:15:31.59#ibcon#end of sib2, iclass 38, count 2 2006.161.08:15:31.59#ibcon#*after write, iclass 38, count 2 2006.161.08:15:31.59#ibcon#*before return 0, iclass 38, count 2 2006.161.08:15:31.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:15:31.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:15:31.59#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.08:15:31.59#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:31.59#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:15:31.71#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:15:31.71#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:15:31.71#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:15:31.71#ibcon#first serial, iclass 38, count 0 2006.161.08:15:31.71#ibcon#enter sib2, iclass 38, count 0 2006.161.08:15:31.71#ibcon#flushed, iclass 38, count 0 2006.161.08:15:31.71#ibcon#about to write, iclass 38, count 0 2006.161.08:15:31.71#ibcon#wrote, iclass 38, count 0 2006.161.08:15:31.71#ibcon#about to read 3, iclass 38, count 0 2006.161.08:15:31.73#ibcon#read 3, iclass 38, count 0 2006.161.08:15:31.73#ibcon#about to read 4, iclass 38, count 0 2006.161.08:15:31.73#ibcon#read 4, iclass 38, count 0 2006.161.08:15:31.73#ibcon#about to read 5, iclass 38, count 0 2006.161.08:15:31.73#ibcon#read 5, iclass 38, count 0 2006.161.08:15:31.73#ibcon#about to read 6, iclass 38, count 0 2006.161.08:15:31.73#ibcon#read 6, iclass 38, count 0 2006.161.08:15:31.73#ibcon#end of sib2, iclass 38, count 0 2006.161.08:15:31.73#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:15:31.73#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:15:31.73#ibcon#[27=USB\r\n] 2006.161.08:15:31.73#ibcon#*before write, iclass 38, count 0 2006.161.08:15:31.73#ibcon#enter sib2, iclass 38, count 0 2006.161.08:15:31.73#ibcon#flushed, iclass 38, count 0 2006.161.08:15:31.73#ibcon#about to write, iclass 38, count 0 2006.161.08:15:31.73#ibcon#wrote, iclass 38, count 0 2006.161.08:15:31.73#ibcon#about to read 3, iclass 38, count 0 2006.161.08:15:31.76#ibcon#read 3, iclass 38, count 0 2006.161.08:15:31.76#ibcon#about to read 4, iclass 38, count 0 2006.161.08:15:31.76#ibcon#read 4, iclass 38, count 0 2006.161.08:15:31.76#ibcon#about to read 5, iclass 38, count 0 2006.161.08:15:31.76#ibcon#read 5, iclass 38, count 0 2006.161.08:15:31.76#ibcon#about to read 6, iclass 38, count 0 2006.161.08:15:31.76#ibcon#read 6, iclass 38, count 0 2006.161.08:15:31.76#ibcon#end of sib2, iclass 38, count 0 2006.161.08:15:31.76#ibcon#*after write, iclass 38, count 0 2006.161.08:15:31.76#ibcon#*before return 0, iclass 38, count 0 2006.161.08:15:31.76#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:15:31.76#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:15:31.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:15:31.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:15:31.76$vc4f8/vblo=2,640.99 2006.161.08:15:31.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.08:15:31.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.08:15:31.76#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:31.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:31.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:31.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:31.76#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:15:31.76#ibcon#first serial, iclass 40, count 0 2006.161.08:15:31.76#ibcon#enter sib2, iclass 40, count 0 2006.161.08:15:31.76#ibcon#flushed, iclass 40, count 0 2006.161.08:15:31.76#ibcon#about to write, iclass 40, count 0 2006.161.08:15:31.76#ibcon#wrote, iclass 40, count 0 2006.161.08:15:31.76#ibcon#about to read 3, iclass 40, count 0 2006.161.08:15:31.78#ibcon#read 3, iclass 40, count 0 2006.161.08:15:31.78#ibcon#about to read 4, iclass 40, count 0 2006.161.08:15:31.78#ibcon#read 4, iclass 40, count 0 2006.161.08:15:31.78#ibcon#about to read 5, iclass 40, count 0 2006.161.08:15:31.78#ibcon#read 5, iclass 40, count 0 2006.161.08:15:31.78#ibcon#about to read 6, iclass 40, count 0 2006.161.08:15:31.78#ibcon#read 6, iclass 40, count 0 2006.161.08:15:31.78#ibcon#end of sib2, iclass 40, count 0 2006.161.08:15:31.78#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:15:31.78#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:15:31.78#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:15:31.78#ibcon#*before write, iclass 40, count 0 2006.161.08:15:31.78#ibcon#enter sib2, iclass 40, count 0 2006.161.08:15:31.78#ibcon#flushed, iclass 40, count 0 2006.161.08:15:31.78#ibcon#about to write, iclass 40, count 0 2006.161.08:15:31.78#ibcon#wrote, iclass 40, count 0 2006.161.08:15:31.78#ibcon#about to read 3, iclass 40, count 0 2006.161.08:15:31.82#ibcon#read 3, iclass 40, count 0 2006.161.08:15:31.82#ibcon#about to read 4, iclass 40, count 0 2006.161.08:15:31.82#ibcon#read 4, iclass 40, count 0 2006.161.08:15:31.82#ibcon#about to read 5, iclass 40, count 0 2006.161.08:15:31.82#ibcon#read 5, iclass 40, count 0 2006.161.08:15:31.82#ibcon#about to read 6, iclass 40, count 0 2006.161.08:15:31.82#ibcon#read 6, iclass 40, count 0 2006.161.08:15:31.82#ibcon#end of sib2, iclass 40, count 0 2006.161.08:15:31.82#ibcon#*after write, iclass 40, count 0 2006.161.08:15:31.82#ibcon#*before return 0, iclass 40, count 0 2006.161.08:15:31.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:31.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:15:31.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:15:31.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:15:31.82$vc4f8/vb=2,4 2006.161.08:15:31.82#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.08:15:31.82#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.08:15:31.82#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:31.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:31.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:31.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:31.88#ibcon#enter wrdev, iclass 4, count 2 2006.161.08:15:31.88#ibcon#first serial, iclass 4, count 2 2006.161.08:15:31.88#ibcon#enter sib2, iclass 4, count 2 2006.161.08:15:31.88#ibcon#flushed, iclass 4, count 2 2006.161.08:15:31.88#ibcon#about to write, iclass 4, count 2 2006.161.08:15:31.88#ibcon#wrote, iclass 4, count 2 2006.161.08:15:31.88#ibcon#about to read 3, iclass 4, count 2 2006.161.08:15:31.90#ibcon#read 3, iclass 4, count 2 2006.161.08:15:31.90#ibcon#about to read 4, iclass 4, count 2 2006.161.08:15:31.90#ibcon#read 4, iclass 4, count 2 2006.161.08:15:31.90#ibcon#about to read 5, iclass 4, count 2 2006.161.08:15:31.90#ibcon#read 5, iclass 4, count 2 2006.161.08:15:31.90#ibcon#about to read 6, iclass 4, count 2 2006.161.08:15:31.90#ibcon#read 6, iclass 4, count 2 2006.161.08:15:31.90#ibcon#end of sib2, iclass 4, count 2 2006.161.08:15:31.90#ibcon#*mode == 0, iclass 4, count 2 2006.161.08:15:31.90#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.08:15:31.90#ibcon#[27=AT02-04\r\n] 2006.161.08:15:31.90#ibcon#*before write, iclass 4, count 2 2006.161.08:15:31.90#ibcon#enter sib2, iclass 4, count 2 2006.161.08:15:31.90#ibcon#flushed, iclass 4, count 2 2006.161.08:15:31.90#ibcon#about to write, iclass 4, count 2 2006.161.08:15:31.90#ibcon#wrote, iclass 4, count 2 2006.161.08:15:31.90#ibcon#about to read 3, iclass 4, count 2 2006.161.08:15:31.93#ibcon#read 3, iclass 4, count 2 2006.161.08:15:31.93#ibcon#about to read 4, iclass 4, count 2 2006.161.08:15:31.93#ibcon#read 4, iclass 4, count 2 2006.161.08:15:31.93#ibcon#about to read 5, iclass 4, count 2 2006.161.08:15:31.93#ibcon#read 5, iclass 4, count 2 2006.161.08:15:31.93#ibcon#about to read 6, iclass 4, count 2 2006.161.08:15:31.93#ibcon#read 6, iclass 4, count 2 2006.161.08:15:31.93#ibcon#end of sib2, iclass 4, count 2 2006.161.08:15:31.93#ibcon#*after write, iclass 4, count 2 2006.161.08:15:31.93#ibcon#*before return 0, iclass 4, count 2 2006.161.08:15:31.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:31.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:15:31.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.08:15:31.93#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:31.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:32.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:32.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:32.05#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:15:32.05#ibcon#first serial, iclass 4, count 0 2006.161.08:15:32.05#ibcon#enter sib2, iclass 4, count 0 2006.161.08:15:32.05#ibcon#flushed, iclass 4, count 0 2006.161.08:15:32.05#ibcon#about to write, iclass 4, count 0 2006.161.08:15:32.05#ibcon#wrote, iclass 4, count 0 2006.161.08:15:32.05#ibcon#about to read 3, iclass 4, count 0 2006.161.08:15:32.07#ibcon#read 3, iclass 4, count 0 2006.161.08:15:32.07#ibcon#about to read 4, iclass 4, count 0 2006.161.08:15:32.07#ibcon#read 4, iclass 4, count 0 2006.161.08:15:32.07#ibcon#about to read 5, iclass 4, count 0 2006.161.08:15:32.07#ibcon#read 5, iclass 4, count 0 2006.161.08:15:32.07#ibcon#about to read 6, iclass 4, count 0 2006.161.08:15:32.07#ibcon#read 6, iclass 4, count 0 2006.161.08:15:32.07#ibcon#end of sib2, iclass 4, count 0 2006.161.08:15:32.07#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:15:32.07#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:15:32.07#ibcon#[27=USB\r\n] 2006.161.08:15:32.07#ibcon#*before write, iclass 4, count 0 2006.161.08:15:32.07#ibcon#enter sib2, iclass 4, count 0 2006.161.08:15:32.07#ibcon#flushed, iclass 4, count 0 2006.161.08:15:32.07#ibcon#about to write, iclass 4, count 0 2006.161.08:15:32.07#ibcon#wrote, iclass 4, count 0 2006.161.08:15:32.07#ibcon#about to read 3, iclass 4, count 0 2006.161.08:15:32.10#ibcon#read 3, iclass 4, count 0 2006.161.08:15:32.10#ibcon#about to read 4, iclass 4, count 0 2006.161.08:15:32.10#ibcon#read 4, iclass 4, count 0 2006.161.08:15:32.10#ibcon#about to read 5, iclass 4, count 0 2006.161.08:15:32.10#ibcon#read 5, iclass 4, count 0 2006.161.08:15:32.10#ibcon#about to read 6, iclass 4, count 0 2006.161.08:15:32.10#ibcon#read 6, iclass 4, count 0 2006.161.08:15:32.10#ibcon#end of sib2, iclass 4, count 0 2006.161.08:15:32.10#ibcon#*after write, iclass 4, count 0 2006.161.08:15:32.10#ibcon#*before return 0, iclass 4, count 0 2006.161.08:15:32.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:32.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:15:32.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:15:32.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:15:32.10$vc4f8/vblo=3,656.99 2006.161.08:15:32.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:15:32.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:15:32.10#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:32.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:32.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:32.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:32.10#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:15:32.10#ibcon#first serial, iclass 6, count 0 2006.161.08:15:32.10#ibcon#enter sib2, iclass 6, count 0 2006.161.08:15:32.10#ibcon#flushed, iclass 6, count 0 2006.161.08:15:32.10#ibcon#about to write, iclass 6, count 0 2006.161.08:15:32.10#ibcon#wrote, iclass 6, count 0 2006.161.08:15:32.10#ibcon#about to read 3, iclass 6, count 0 2006.161.08:15:32.12#ibcon#read 3, iclass 6, count 0 2006.161.08:15:32.12#ibcon#about to read 4, iclass 6, count 0 2006.161.08:15:32.12#ibcon#read 4, iclass 6, count 0 2006.161.08:15:32.12#ibcon#about to read 5, iclass 6, count 0 2006.161.08:15:32.12#ibcon#read 5, iclass 6, count 0 2006.161.08:15:32.12#ibcon#about to read 6, iclass 6, count 0 2006.161.08:15:32.12#ibcon#read 6, iclass 6, count 0 2006.161.08:15:32.12#ibcon#end of sib2, iclass 6, count 0 2006.161.08:15:32.12#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:15:32.12#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:15:32.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:15:32.12#ibcon#*before write, iclass 6, count 0 2006.161.08:15:32.12#ibcon#enter sib2, iclass 6, count 0 2006.161.08:15:32.12#ibcon#flushed, iclass 6, count 0 2006.161.08:15:32.12#ibcon#about to write, iclass 6, count 0 2006.161.08:15:32.12#ibcon#wrote, iclass 6, count 0 2006.161.08:15:32.12#ibcon#about to read 3, iclass 6, count 0 2006.161.08:15:32.16#ibcon#read 3, iclass 6, count 0 2006.161.08:15:32.16#ibcon#about to read 4, iclass 6, count 0 2006.161.08:15:32.16#ibcon#read 4, iclass 6, count 0 2006.161.08:15:32.16#ibcon#about to read 5, iclass 6, count 0 2006.161.08:15:32.16#ibcon#read 5, iclass 6, count 0 2006.161.08:15:32.16#ibcon#about to read 6, iclass 6, count 0 2006.161.08:15:32.16#ibcon#read 6, iclass 6, count 0 2006.161.08:15:32.16#ibcon#end of sib2, iclass 6, count 0 2006.161.08:15:32.16#ibcon#*after write, iclass 6, count 0 2006.161.08:15:32.16#ibcon#*before return 0, iclass 6, count 0 2006.161.08:15:32.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:32.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:15:32.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:15:32.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:15:32.16$vc4f8/vb=3,4 2006.161.08:15:32.16#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.08:15:32.16#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.08:15:32.16#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:32.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:32.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:32.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:32.22#ibcon#enter wrdev, iclass 10, count 2 2006.161.08:15:32.22#ibcon#first serial, iclass 10, count 2 2006.161.08:15:32.22#ibcon#enter sib2, iclass 10, count 2 2006.161.08:15:32.22#ibcon#flushed, iclass 10, count 2 2006.161.08:15:32.22#ibcon#about to write, iclass 10, count 2 2006.161.08:15:32.22#ibcon#wrote, iclass 10, count 2 2006.161.08:15:32.22#ibcon#about to read 3, iclass 10, count 2 2006.161.08:15:32.24#ibcon#read 3, iclass 10, count 2 2006.161.08:15:32.24#ibcon#about to read 4, iclass 10, count 2 2006.161.08:15:32.24#ibcon#read 4, iclass 10, count 2 2006.161.08:15:32.24#ibcon#about to read 5, iclass 10, count 2 2006.161.08:15:32.24#ibcon#read 5, iclass 10, count 2 2006.161.08:15:32.24#ibcon#about to read 6, iclass 10, count 2 2006.161.08:15:32.24#ibcon#read 6, iclass 10, count 2 2006.161.08:15:32.24#ibcon#end of sib2, iclass 10, count 2 2006.161.08:15:32.24#ibcon#*mode == 0, iclass 10, count 2 2006.161.08:15:32.24#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.08:15:32.24#ibcon#[27=AT03-04\r\n] 2006.161.08:15:32.24#ibcon#*before write, iclass 10, count 2 2006.161.08:15:32.24#ibcon#enter sib2, iclass 10, count 2 2006.161.08:15:32.24#ibcon#flushed, iclass 10, count 2 2006.161.08:15:32.24#ibcon#about to write, iclass 10, count 2 2006.161.08:15:32.24#ibcon#wrote, iclass 10, count 2 2006.161.08:15:32.24#ibcon#about to read 3, iclass 10, count 2 2006.161.08:15:32.27#ibcon#read 3, iclass 10, count 2 2006.161.08:15:32.27#ibcon#about to read 4, iclass 10, count 2 2006.161.08:15:32.27#ibcon#read 4, iclass 10, count 2 2006.161.08:15:32.27#ibcon#about to read 5, iclass 10, count 2 2006.161.08:15:32.27#ibcon#read 5, iclass 10, count 2 2006.161.08:15:32.27#ibcon#about to read 6, iclass 10, count 2 2006.161.08:15:32.27#ibcon#read 6, iclass 10, count 2 2006.161.08:15:32.27#ibcon#end of sib2, iclass 10, count 2 2006.161.08:15:32.27#ibcon#*after write, iclass 10, count 2 2006.161.08:15:32.27#ibcon#*before return 0, iclass 10, count 2 2006.161.08:15:32.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:32.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:15:32.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.08:15:32.27#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:32.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:32.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:32.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:32.39#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:15:32.39#ibcon#first serial, iclass 10, count 0 2006.161.08:15:32.39#ibcon#enter sib2, iclass 10, count 0 2006.161.08:15:32.39#ibcon#flushed, iclass 10, count 0 2006.161.08:15:32.39#ibcon#about to write, iclass 10, count 0 2006.161.08:15:32.39#ibcon#wrote, iclass 10, count 0 2006.161.08:15:32.39#ibcon#about to read 3, iclass 10, count 0 2006.161.08:15:32.41#ibcon#read 3, iclass 10, count 0 2006.161.08:15:32.41#ibcon#about to read 4, iclass 10, count 0 2006.161.08:15:32.41#ibcon#read 4, iclass 10, count 0 2006.161.08:15:32.41#ibcon#about to read 5, iclass 10, count 0 2006.161.08:15:32.41#ibcon#read 5, iclass 10, count 0 2006.161.08:15:32.41#ibcon#about to read 6, iclass 10, count 0 2006.161.08:15:32.41#ibcon#read 6, iclass 10, count 0 2006.161.08:15:32.41#ibcon#end of sib2, iclass 10, count 0 2006.161.08:15:32.41#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:15:32.41#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:15:32.41#ibcon#[27=USB\r\n] 2006.161.08:15:32.41#ibcon#*before write, iclass 10, count 0 2006.161.08:15:32.41#ibcon#enter sib2, iclass 10, count 0 2006.161.08:15:32.41#ibcon#flushed, iclass 10, count 0 2006.161.08:15:32.41#ibcon#about to write, iclass 10, count 0 2006.161.08:15:32.41#ibcon#wrote, iclass 10, count 0 2006.161.08:15:32.41#ibcon#about to read 3, iclass 10, count 0 2006.161.08:15:32.44#ibcon#read 3, iclass 10, count 0 2006.161.08:15:32.44#ibcon#about to read 4, iclass 10, count 0 2006.161.08:15:32.44#ibcon#read 4, iclass 10, count 0 2006.161.08:15:32.44#ibcon#about to read 5, iclass 10, count 0 2006.161.08:15:32.44#ibcon#read 5, iclass 10, count 0 2006.161.08:15:32.44#ibcon#about to read 6, iclass 10, count 0 2006.161.08:15:32.44#ibcon#read 6, iclass 10, count 0 2006.161.08:15:32.44#ibcon#end of sib2, iclass 10, count 0 2006.161.08:15:32.44#ibcon#*after write, iclass 10, count 0 2006.161.08:15:32.44#ibcon#*before return 0, iclass 10, count 0 2006.161.08:15:32.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:32.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:15:32.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:15:32.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:15:32.44$vc4f8/vblo=4,712.99 2006.161.08:15:32.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:15:32.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:15:32.44#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:32.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:32.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:32.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:32.44#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:15:32.44#ibcon#first serial, iclass 12, count 0 2006.161.08:15:32.44#ibcon#enter sib2, iclass 12, count 0 2006.161.08:15:32.44#ibcon#flushed, iclass 12, count 0 2006.161.08:15:32.44#ibcon#about to write, iclass 12, count 0 2006.161.08:15:32.44#ibcon#wrote, iclass 12, count 0 2006.161.08:15:32.44#ibcon#about to read 3, iclass 12, count 0 2006.161.08:15:32.46#ibcon#read 3, iclass 12, count 0 2006.161.08:15:32.46#ibcon#about to read 4, iclass 12, count 0 2006.161.08:15:32.46#ibcon#read 4, iclass 12, count 0 2006.161.08:15:32.46#ibcon#about to read 5, iclass 12, count 0 2006.161.08:15:32.46#ibcon#read 5, iclass 12, count 0 2006.161.08:15:32.46#ibcon#about to read 6, iclass 12, count 0 2006.161.08:15:32.46#ibcon#read 6, iclass 12, count 0 2006.161.08:15:32.46#ibcon#end of sib2, iclass 12, count 0 2006.161.08:15:32.46#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:15:32.46#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:15:32.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:15:32.46#ibcon#*before write, iclass 12, count 0 2006.161.08:15:32.46#ibcon#enter sib2, iclass 12, count 0 2006.161.08:15:32.46#ibcon#flushed, iclass 12, count 0 2006.161.08:15:32.46#ibcon#about to write, iclass 12, count 0 2006.161.08:15:32.46#ibcon#wrote, iclass 12, count 0 2006.161.08:15:32.46#ibcon#about to read 3, iclass 12, count 0 2006.161.08:15:32.50#ibcon#read 3, iclass 12, count 0 2006.161.08:15:32.50#ibcon#about to read 4, iclass 12, count 0 2006.161.08:15:32.50#ibcon#read 4, iclass 12, count 0 2006.161.08:15:32.50#ibcon#about to read 5, iclass 12, count 0 2006.161.08:15:32.50#ibcon#read 5, iclass 12, count 0 2006.161.08:15:32.50#ibcon#about to read 6, iclass 12, count 0 2006.161.08:15:32.50#ibcon#read 6, iclass 12, count 0 2006.161.08:15:32.50#ibcon#end of sib2, iclass 12, count 0 2006.161.08:15:32.50#ibcon#*after write, iclass 12, count 0 2006.161.08:15:32.50#ibcon#*before return 0, iclass 12, count 0 2006.161.08:15:32.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:32.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:15:32.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:15:32.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:15:32.50$vc4f8/vb=4,4 2006.161.08:15:32.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.08:15:32.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.08:15:32.50#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:32.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:32.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:32.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:32.56#ibcon#enter wrdev, iclass 14, count 2 2006.161.08:15:32.56#ibcon#first serial, iclass 14, count 2 2006.161.08:15:32.56#ibcon#enter sib2, iclass 14, count 2 2006.161.08:15:32.56#ibcon#flushed, iclass 14, count 2 2006.161.08:15:32.56#ibcon#about to write, iclass 14, count 2 2006.161.08:15:32.56#ibcon#wrote, iclass 14, count 2 2006.161.08:15:32.56#ibcon#about to read 3, iclass 14, count 2 2006.161.08:15:32.58#ibcon#read 3, iclass 14, count 2 2006.161.08:15:32.58#ibcon#about to read 4, iclass 14, count 2 2006.161.08:15:32.58#ibcon#read 4, iclass 14, count 2 2006.161.08:15:32.58#ibcon#about to read 5, iclass 14, count 2 2006.161.08:15:32.58#ibcon#read 5, iclass 14, count 2 2006.161.08:15:32.58#ibcon#about to read 6, iclass 14, count 2 2006.161.08:15:32.58#ibcon#read 6, iclass 14, count 2 2006.161.08:15:32.58#ibcon#end of sib2, iclass 14, count 2 2006.161.08:15:32.58#ibcon#*mode == 0, iclass 14, count 2 2006.161.08:15:32.58#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.08:15:32.58#ibcon#[27=AT04-04\r\n] 2006.161.08:15:32.58#ibcon#*before write, iclass 14, count 2 2006.161.08:15:32.58#ibcon#enter sib2, iclass 14, count 2 2006.161.08:15:32.58#ibcon#flushed, iclass 14, count 2 2006.161.08:15:32.58#ibcon#about to write, iclass 14, count 2 2006.161.08:15:32.58#ibcon#wrote, iclass 14, count 2 2006.161.08:15:32.58#ibcon#about to read 3, iclass 14, count 2 2006.161.08:15:32.61#ibcon#read 3, iclass 14, count 2 2006.161.08:15:32.61#ibcon#about to read 4, iclass 14, count 2 2006.161.08:15:32.61#ibcon#read 4, iclass 14, count 2 2006.161.08:15:32.61#ibcon#about to read 5, iclass 14, count 2 2006.161.08:15:32.61#ibcon#read 5, iclass 14, count 2 2006.161.08:15:32.61#ibcon#about to read 6, iclass 14, count 2 2006.161.08:15:32.61#ibcon#read 6, iclass 14, count 2 2006.161.08:15:32.61#ibcon#end of sib2, iclass 14, count 2 2006.161.08:15:32.61#ibcon#*after write, iclass 14, count 2 2006.161.08:15:32.61#ibcon#*before return 0, iclass 14, count 2 2006.161.08:15:32.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:32.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:15:32.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.08:15:32.61#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:32.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:32.70#abcon#<5=/05 2.6 4.3 24.00 861002.5\r\n> 2006.161.08:15:32.72#abcon#{5=INTERFACE CLEAR} 2006.161.08:15:32.73#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:32.73#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:32.73#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:15:32.73#ibcon#first serial, iclass 14, count 0 2006.161.08:15:32.73#ibcon#enter sib2, iclass 14, count 0 2006.161.08:15:32.73#ibcon#flushed, iclass 14, count 0 2006.161.08:15:32.73#ibcon#about to write, iclass 14, count 0 2006.161.08:15:32.73#ibcon#wrote, iclass 14, count 0 2006.161.08:15:32.73#ibcon#about to read 3, iclass 14, count 0 2006.161.08:15:32.75#ibcon#read 3, iclass 14, count 0 2006.161.08:15:32.75#ibcon#about to read 4, iclass 14, count 0 2006.161.08:15:32.75#ibcon#read 4, iclass 14, count 0 2006.161.08:15:32.75#ibcon#about to read 5, iclass 14, count 0 2006.161.08:15:32.75#ibcon#read 5, iclass 14, count 0 2006.161.08:15:32.75#ibcon#about to read 6, iclass 14, count 0 2006.161.08:15:32.75#ibcon#read 6, iclass 14, count 0 2006.161.08:15:32.75#ibcon#end of sib2, iclass 14, count 0 2006.161.08:15:32.75#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:15:32.75#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:15:32.75#ibcon#[27=USB\r\n] 2006.161.08:15:32.75#ibcon#*before write, iclass 14, count 0 2006.161.08:15:32.75#ibcon#enter sib2, iclass 14, count 0 2006.161.08:15:32.75#ibcon#flushed, iclass 14, count 0 2006.161.08:15:32.75#ibcon#about to write, iclass 14, count 0 2006.161.08:15:32.75#ibcon#wrote, iclass 14, count 0 2006.161.08:15:32.75#ibcon#about to read 3, iclass 14, count 0 2006.161.08:15:32.78#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:15:32.78#ibcon#read 3, iclass 14, count 0 2006.161.08:15:32.78#ibcon#about to read 4, iclass 14, count 0 2006.161.08:15:32.78#ibcon#read 4, iclass 14, count 0 2006.161.08:15:32.78#ibcon#about to read 5, iclass 14, count 0 2006.161.08:15:32.78#ibcon#read 5, iclass 14, count 0 2006.161.08:15:32.78#ibcon#about to read 6, iclass 14, count 0 2006.161.08:15:32.78#ibcon#read 6, iclass 14, count 0 2006.161.08:15:32.78#ibcon#end of sib2, iclass 14, count 0 2006.161.08:15:32.78#ibcon#*after write, iclass 14, count 0 2006.161.08:15:32.78#ibcon#*before return 0, iclass 14, count 0 2006.161.08:15:32.78#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:32.78#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:15:32.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:15:32.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:15:32.78$vc4f8/vblo=5,744.99 2006.161.08:15:32.78#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.08:15:32.78#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.08:15:32.78#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:32.78#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:32.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:32.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:32.78#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:15:32.78#ibcon#first serial, iclass 20, count 0 2006.161.08:15:32.78#ibcon#enter sib2, iclass 20, count 0 2006.161.08:15:32.78#ibcon#flushed, iclass 20, count 0 2006.161.08:15:32.78#ibcon#about to write, iclass 20, count 0 2006.161.08:15:32.78#ibcon#wrote, iclass 20, count 0 2006.161.08:15:32.78#ibcon#about to read 3, iclass 20, count 0 2006.161.08:15:32.80#ibcon#read 3, iclass 20, count 0 2006.161.08:15:32.80#ibcon#about to read 4, iclass 20, count 0 2006.161.08:15:32.80#ibcon#read 4, iclass 20, count 0 2006.161.08:15:32.80#ibcon#about to read 5, iclass 20, count 0 2006.161.08:15:32.80#ibcon#read 5, iclass 20, count 0 2006.161.08:15:32.80#ibcon#about to read 6, iclass 20, count 0 2006.161.08:15:32.80#ibcon#read 6, iclass 20, count 0 2006.161.08:15:32.80#ibcon#end of sib2, iclass 20, count 0 2006.161.08:15:32.80#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:15:32.80#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:15:32.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:15:32.80#ibcon#*before write, iclass 20, count 0 2006.161.08:15:32.80#ibcon#enter sib2, iclass 20, count 0 2006.161.08:15:32.80#ibcon#flushed, iclass 20, count 0 2006.161.08:15:32.80#ibcon#about to write, iclass 20, count 0 2006.161.08:15:32.80#ibcon#wrote, iclass 20, count 0 2006.161.08:15:32.80#ibcon#about to read 3, iclass 20, count 0 2006.161.08:15:32.84#ibcon#read 3, iclass 20, count 0 2006.161.08:15:32.84#ibcon#about to read 4, iclass 20, count 0 2006.161.08:15:32.84#ibcon#read 4, iclass 20, count 0 2006.161.08:15:32.84#ibcon#about to read 5, iclass 20, count 0 2006.161.08:15:32.84#ibcon#read 5, iclass 20, count 0 2006.161.08:15:32.84#ibcon#about to read 6, iclass 20, count 0 2006.161.08:15:32.84#ibcon#read 6, iclass 20, count 0 2006.161.08:15:32.84#ibcon#end of sib2, iclass 20, count 0 2006.161.08:15:32.84#ibcon#*after write, iclass 20, count 0 2006.161.08:15:32.84#ibcon#*before return 0, iclass 20, count 0 2006.161.08:15:32.84#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:32.84#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:15:32.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:15:32.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:15:32.84$vc4f8/vb=5,4 2006.161.08:15:32.84#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.08:15:32.84#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.08:15:32.84#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:32.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:32.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:32.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:32.90#ibcon#enter wrdev, iclass 22, count 2 2006.161.08:15:32.90#ibcon#first serial, iclass 22, count 2 2006.161.08:15:32.90#ibcon#enter sib2, iclass 22, count 2 2006.161.08:15:32.90#ibcon#flushed, iclass 22, count 2 2006.161.08:15:32.90#ibcon#about to write, iclass 22, count 2 2006.161.08:15:32.90#ibcon#wrote, iclass 22, count 2 2006.161.08:15:32.90#ibcon#about to read 3, iclass 22, count 2 2006.161.08:15:32.92#ibcon#read 3, iclass 22, count 2 2006.161.08:15:32.92#ibcon#about to read 4, iclass 22, count 2 2006.161.08:15:32.92#ibcon#read 4, iclass 22, count 2 2006.161.08:15:32.92#ibcon#about to read 5, iclass 22, count 2 2006.161.08:15:32.92#ibcon#read 5, iclass 22, count 2 2006.161.08:15:32.92#ibcon#about to read 6, iclass 22, count 2 2006.161.08:15:32.92#ibcon#read 6, iclass 22, count 2 2006.161.08:15:32.92#ibcon#end of sib2, iclass 22, count 2 2006.161.08:15:32.92#ibcon#*mode == 0, iclass 22, count 2 2006.161.08:15:32.92#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.08:15:32.92#ibcon#[27=AT05-04\r\n] 2006.161.08:15:32.92#ibcon#*before write, iclass 22, count 2 2006.161.08:15:32.92#ibcon#enter sib2, iclass 22, count 2 2006.161.08:15:32.92#ibcon#flushed, iclass 22, count 2 2006.161.08:15:32.92#ibcon#about to write, iclass 22, count 2 2006.161.08:15:32.92#ibcon#wrote, iclass 22, count 2 2006.161.08:15:32.92#ibcon#about to read 3, iclass 22, count 2 2006.161.08:15:32.95#ibcon#read 3, iclass 22, count 2 2006.161.08:15:32.95#ibcon#about to read 4, iclass 22, count 2 2006.161.08:15:32.95#ibcon#read 4, iclass 22, count 2 2006.161.08:15:32.95#ibcon#about to read 5, iclass 22, count 2 2006.161.08:15:32.95#ibcon#read 5, iclass 22, count 2 2006.161.08:15:32.95#ibcon#about to read 6, iclass 22, count 2 2006.161.08:15:32.95#ibcon#read 6, iclass 22, count 2 2006.161.08:15:32.95#ibcon#end of sib2, iclass 22, count 2 2006.161.08:15:32.95#ibcon#*after write, iclass 22, count 2 2006.161.08:15:32.95#ibcon#*before return 0, iclass 22, count 2 2006.161.08:15:32.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:32.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:15:32.95#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.08:15:32.95#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:32.95#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:33.07#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:33.07#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:33.07#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:15:33.07#ibcon#first serial, iclass 22, count 0 2006.161.08:15:33.07#ibcon#enter sib2, iclass 22, count 0 2006.161.08:15:33.07#ibcon#flushed, iclass 22, count 0 2006.161.08:15:33.07#ibcon#about to write, iclass 22, count 0 2006.161.08:15:33.07#ibcon#wrote, iclass 22, count 0 2006.161.08:15:33.07#ibcon#about to read 3, iclass 22, count 0 2006.161.08:15:33.09#ibcon#read 3, iclass 22, count 0 2006.161.08:15:33.09#ibcon#about to read 4, iclass 22, count 0 2006.161.08:15:33.09#ibcon#read 4, iclass 22, count 0 2006.161.08:15:33.09#ibcon#about to read 5, iclass 22, count 0 2006.161.08:15:33.09#ibcon#read 5, iclass 22, count 0 2006.161.08:15:33.09#ibcon#about to read 6, iclass 22, count 0 2006.161.08:15:33.09#ibcon#read 6, iclass 22, count 0 2006.161.08:15:33.09#ibcon#end of sib2, iclass 22, count 0 2006.161.08:15:33.09#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:15:33.09#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:15:33.09#ibcon#[27=USB\r\n] 2006.161.08:15:33.09#ibcon#*before write, iclass 22, count 0 2006.161.08:15:33.09#ibcon#enter sib2, iclass 22, count 0 2006.161.08:15:33.09#ibcon#flushed, iclass 22, count 0 2006.161.08:15:33.09#ibcon#about to write, iclass 22, count 0 2006.161.08:15:33.09#ibcon#wrote, iclass 22, count 0 2006.161.08:15:33.09#ibcon#about to read 3, iclass 22, count 0 2006.161.08:15:33.12#ibcon#read 3, iclass 22, count 0 2006.161.08:15:33.12#ibcon#about to read 4, iclass 22, count 0 2006.161.08:15:33.12#ibcon#read 4, iclass 22, count 0 2006.161.08:15:33.12#ibcon#about to read 5, iclass 22, count 0 2006.161.08:15:33.12#ibcon#read 5, iclass 22, count 0 2006.161.08:15:33.12#ibcon#about to read 6, iclass 22, count 0 2006.161.08:15:33.12#ibcon#read 6, iclass 22, count 0 2006.161.08:15:33.12#ibcon#end of sib2, iclass 22, count 0 2006.161.08:15:33.12#ibcon#*after write, iclass 22, count 0 2006.161.08:15:33.12#ibcon#*before return 0, iclass 22, count 0 2006.161.08:15:33.12#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:33.12#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:15:33.12#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:15:33.12#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:15:33.12$vc4f8/vblo=6,752.99 2006.161.08:15:33.12#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:15:33.12#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:15:33.12#ibcon#ireg 17 cls_cnt 0 2006.161.08:15:33.12#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:33.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:33.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:33.12#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:15:33.12#ibcon#first serial, iclass 24, count 0 2006.161.08:15:33.12#ibcon#enter sib2, iclass 24, count 0 2006.161.08:15:33.12#ibcon#flushed, iclass 24, count 0 2006.161.08:15:33.12#ibcon#about to write, iclass 24, count 0 2006.161.08:15:33.12#ibcon#wrote, iclass 24, count 0 2006.161.08:15:33.12#ibcon#about to read 3, iclass 24, count 0 2006.161.08:15:33.14#ibcon#read 3, iclass 24, count 0 2006.161.08:15:33.14#ibcon#about to read 4, iclass 24, count 0 2006.161.08:15:33.14#ibcon#read 4, iclass 24, count 0 2006.161.08:15:33.14#ibcon#about to read 5, iclass 24, count 0 2006.161.08:15:33.14#ibcon#read 5, iclass 24, count 0 2006.161.08:15:33.14#ibcon#about to read 6, iclass 24, count 0 2006.161.08:15:33.14#ibcon#read 6, iclass 24, count 0 2006.161.08:15:33.14#ibcon#end of sib2, iclass 24, count 0 2006.161.08:15:33.14#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:15:33.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:15:33.14#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:15:33.14#ibcon#*before write, iclass 24, count 0 2006.161.08:15:33.14#ibcon#enter sib2, iclass 24, count 0 2006.161.08:15:33.14#ibcon#flushed, iclass 24, count 0 2006.161.08:15:33.14#ibcon#about to write, iclass 24, count 0 2006.161.08:15:33.14#ibcon#wrote, iclass 24, count 0 2006.161.08:15:33.14#ibcon#about to read 3, iclass 24, count 0 2006.161.08:15:33.18#ibcon#read 3, iclass 24, count 0 2006.161.08:15:33.18#ibcon#about to read 4, iclass 24, count 0 2006.161.08:15:33.18#ibcon#read 4, iclass 24, count 0 2006.161.08:15:33.18#ibcon#about to read 5, iclass 24, count 0 2006.161.08:15:33.18#ibcon#read 5, iclass 24, count 0 2006.161.08:15:33.18#ibcon#about to read 6, iclass 24, count 0 2006.161.08:15:33.18#ibcon#read 6, iclass 24, count 0 2006.161.08:15:33.18#ibcon#end of sib2, iclass 24, count 0 2006.161.08:15:33.18#ibcon#*after write, iclass 24, count 0 2006.161.08:15:33.18#ibcon#*before return 0, iclass 24, count 0 2006.161.08:15:33.18#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:33.18#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:15:33.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:15:33.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:15:33.18$vc4f8/vb=6,4 2006.161.08:15:33.18#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:15:33.18#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:15:33.18#ibcon#ireg 11 cls_cnt 2 2006.161.08:15:33.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:33.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:33.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:33.24#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:15:33.24#ibcon#first serial, iclass 26, count 2 2006.161.08:15:33.24#ibcon#enter sib2, iclass 26, count 2 2006.161.08:15:33.24#ibcon#flushed, iclass 26, count 2 2006.161.08:15:33.24#ibcon#about to write, iclass 26, count 2 2006.161.08:15:33.24#ibcon#wrote, iclass 26, count 2 2006.161.08:15:33.24#ibcon#about to read 3, iclass 26, count 2 2006.161.08:15:33.26#ibcon#read 3, iclass 26, count 2 2006.161.08:15:33.26#ibcon#about to read 4, iclass 26, count 2 2006.161.08:15:33.26#ibcon#read 4, iclass 26, count 2 2006.161.08:15:33.26#ibcon#about to read 5, iclass 26, count 2 2006.161.08:15:33.26#ibcon#read 5, iclass 26, count 2 2006.161.08:15:33.26#ibcon#about to read 6, iclass 26, count 2 2006.161.08:15:33.26#ibcon#read 6, iclass 26, count 2 2006.161.08:15:33.26#ibcon#end of sib2, iclass 26, count 2 2006.161.08:15:33.26#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:15:33.26#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:15:33.26#ibcon#[27=AT06-04\r\n] 2006.161.08:15:33.26#ibcon#*before write, iclass 26, count 2 2006.161.08:15:33.26#ibcon#enter sib2, iclass 26, count 2 2006.161.08:15:33.26#ibcon#flushed, iclass 26, count 2 2006.161.08:15:33.26#ibcon#about to write, iclass 26, count 2 2006.161.08:15:33.26#ibcon#wrote, iclass 26, count 2 2006.161.08:15:33.26#ibcon#about to read 3, iclass 26, count 2 2006.161.08:15:33.29#ibcon#read 3, iclass 26, count 2 2006.161.08:15:33.29#ibcon#about to read 4, iclass 26, count 2 2006.161.08:15:33.29#ibcon#read 4, iclass 26, count 2 2006.161.08:15:33.29#ibcon#about to read 5, iclass 26, count 2 2006.161.08:15:33.29#ibcon#read 5, iclass 26, count 2 2006.161.08:15:33.29#ibcon#about to read 6, iclass 26, count 2 2006.161.08:15:33.29#ibcon#read 6, iclass 26, count 2 2006.161.08:15:33.29#ibcon#end of sib2, iclass 26, count 2 2006.161.08:15:33.29#ibcon#*after write, iclass 26, count 2 2006.161.08:15:33.29#ibcon#*before return 0, iclass 26, count 2 2006.161.08:15:33.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:33.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:15:33.29#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:15:33.29#ibcon#ireg 7 cls_cnt 0 2006.161.08:15:33.29#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:33.41#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:33.41#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:33.41#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:15:33.41#ibcon#first serial, iclass 26, count 0 2006.161.08:15:33.41#ibcon#enter sib2, iclass 26, count 0 2006.161.08:15:33.41#ibcon#flushed, iclass 26, count 0 2006.161.08:15:33.41#ibcon#about to write, iclass 26, count 0 2006.161.08:15:33.41#ibcon#wrote, iclass 26, count 0 2006.161.08:15:33.41#ibcon#about to read 3, iclass 26, count 0 2006.161.08:15:33.43#ibcon#read 3, iclass 26, count 0 2006.161.08:15:33.43#ibcon#about to read 4, iclass 26, count 0 2006.161.08:15:33.43#ibcon#read 4, iclass 26, count 0 2006.161.08:15:33.43#ibcon#about to read 5, iclass 26, count 0 2006.161.08:15:33.43#ibcon#read 5, iclass 26, count 0 2006.161.08:15:33.43#ibcon#about to read 6, iclass 26, count 0 2006.161.08:15:33.43#ibcon#read 6, iclass 26, count 0 2006.161.08:15:33.43#ibcon#end of sib2, iclass 26, count 0 2006.161.08:15:33.43#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:15:33.43#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:15:33.43#ibcon#[27=USB\r\n] 2006.161.08:15:33.43#ibcon#*before write, iclass 26, count 0 2006.161.08:15:33.43#ibcon#enter sib2, iclass 26, count 0 2006.161.08:15:33.43#ibcon#flushed, iclass 26, count 0 2006.161.08:15:33.43#ibcon#about to write, iclass 26, count 0 2006.161.08:15:33.43#ibcon#wrote, iclass 26, count 0 2006.161.08:15:33.43#ibcon#about to read 3, iclass 26, count 0 2006.161.08:15:33.46#ibcon#read 3, iclass 26, count 0 2006.161.08:15:33.46#ibcon#about to read 4, iclass 26, count 0 2006.161.08:15:33.46#ibcon#read 4, iclass 26, count 0 2006.161.08:15:33.46#ibcon#about to read 5, iclass 26, count 0 2006.161.08:15:33.46#ibcon#read 5, iclass 26, count 0 2006.161.08:15:33.46#ibcon#about to read 6, iclass 26, count 0 2006.161.08:15:33.46#ibcon#read 6, iclass 26, count 0 2006.161.08:15:33.46#ibcon#end of sib2, iclass 26, count 0 2006.161.08:15:33.46#ibcon#*after write, iclass 26, count 0 2006.161.08:15:33.46#ibcon#*before return 0, iclass 26, count 0 2006.161.08:15:33.46#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:33.46#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:15:33.46#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:15:33.46#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:15:33.46$vc4f8/vabw=wide 2006.161.08:15:33.46#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:15:33.46#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:15:33.46#ibcon#ireg 8 cls_cnt 0 2006.161.08:15:33.46#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:33.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:33.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:33.46#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:15:33.46#ibcon#first serial, iclass 28, count 0 2006.161.08:15:33.46#ibcon#enter sib2, iclass 28, count 0 2006.161.08:15:33.46#ibcon#flushed, iclass 28, count 0 2006.161.08:15:33.46#ibcon#about to write, iclass 28, count 0 2006.161.08:15:33.46#ibcon#wrote, iclass 28, count 0 2006.161.08:15:33.46#ibcon#about to read 3, iclass 28, count 0 2006.161.08:15:33.48#ibcon#read 3, iclass 28, count 0 2006.161.08:15:33.48#ibcon#about to read 4, iclass 28, count 0 2006.161.08:15:33.48#ibcon#read 4, iclass 28, count 0 2006.161.08:15:33.48#ibcon#about to read 5, iclass 28, count 0 2006.161.08:15:33.48#ibcon#read 5, iclass 28, count 0 2006.161.08:15:33.48#ibcon#about to read 6, iclass 28, count 0 2006.161.08:15:33.48#ibcon#read 6, iclass 28, count 0 2006.161.08:15:33.48#ibcon#end of sib2, iclass 28, count 0 2006.161.08:15:33.48#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:15:33.48#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:15:33.48#ibcon#[25=BW32\r\n] 2006.161.08:15:33.48#ibcon#*before write, iclass 28, count 0 2006.161.08:15:33.48#ibcon#enter sib2, iclass 28, count 0 2006.161.08:15:33.48#ibcon#flushed, iclass 28, count 0 2006.161.08:15:33.48#ibcon#about to write, iclass 28, count 0 2006.161.08:15:33.48#ibcon#wrote, iclass 28, count 0 2006.161.08:15:33.48#ibcon#about to read 3, iclass 28, count 0 2006.161.08:15:33.51#ibcon#read 3, iclass 28, count 0 2006.161.08:15:33.51#ibcon#about to read 4, iclass 28, count 0 2006.161.08:15:33.51#ibcon#read 4, iclass 28, count 0 2006.161.08:15:33.51#ibcon#about to read 5, iclass 28, count 0 2006.161.08:15:33.51#ibcon#read 5, iclass 28, count 0 2006.161.08:15:33.51#ibcon#about to read 6, iclass 28, count 0 2006.161.08:15:33.51#ibcon#read 6, iclass 28, count 0 2006.161.08:15:33.51#ibcon#end of sib2, iclass 28, count 0 2006.161.08:15:33.51#ibcon#*after write, iclass 28, count 0 2006.161.08:15:33.51#ibcon#*before return 0, iclass 28, count 0 2006.161.08:15:33.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:33.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:15:33.51#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:15:33.51#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:15:33.51$vc4f8/vbbw=wide 2006.161.08:15:33.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:15:33.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:15:33.51#ibcon#ireg 8 cls_cnt 0 2006.161.08:15:33.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:15:33.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:15:33.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:15:33.58#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:15:33.58#ibcon#first serial, iclass 30, count 0 2006.161.08:15:33.58#ibcon#enter sib2, iclass 30, count 0 2006.161.08:15:33.58#ibcon#flushed, iclass 30, count 0 2006.161.08:15:33.58#ibcon#about to write, iclass 30, count 0 2006.161.08:15:33.58#ibcon#wrote, iclass 30, count 0 2006.161.08:15:33.58#ibcon#about to read 3, iclass 30, count 0 2006.161.08:15:33.60#ibcon#read 3, iclass 30, count 0 2006.161.08:15:33.60#ibcon#about to read 4, iclass 30, count 0 2006.161.08:15:33.60#ibcon#read 4, iclass 30, count 0 2006.161.08:15:33.60#ibcon#about to read 5, iclass 30, count 0 2006.161.08:15:33.60#ibcon#read 5, iclass 30, count 0 2006.161.08:15:33.60#ibcon#about to read 6, iclass 30, count 0 2006.161.08:15:33.60#ibcon#read 6, iclass 30, count 0 2006.161.08:15:33.60#ibcon#end of sib2, iclass 30, count 0 2006.161.08:15:33.60#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:15:33.60#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:15:33.60#ibcon#[27=BW32\r\n] 2006.161.08:15:33.60#ibcon#*before write, iclass 30, count 0 2006.161.08:15:33.60#ibcon#enter sib2, iclass 30, count 0 2006.161.08:15:33.60#ibcon#flushed, iclass 30, count 0 2006.161.08:15:33.60#ibcon#about to write, iclass 30, count 0 2006.161.08:15:33.60#ibcon#wrote, iclass 30, count 0 2006.161.08:15:33.60#ibcon#about to read 3, iclass 30, count 0 2006.161.08:15:33.63#ibcon#read 3, iclass 30, count 0 2006.161.08:15:33.63#ibcon#about to read 4, iclass 30, count 0 2006.161.08:15:33.63#ibcon#read 4, iclass 30, count 0 2006.161.08:15:33.63#ibcon#about to read 5, iclass 30, count 0 2006.161.08:15:33.63#ibcon#read 5, iclass 30, count 0 2006.161.08:15:33.63#ibcon#about to read 6, iclass 30, count 0 2006.161.08:15:33.63#ibcon#read 6, iclass 30, count 0 2006.161.08:15:33.63#ibcon#end of sib2, iclass 30, count 0 2006.161.08:15:33.63#ibcon#*after write, iclass 30, count 0 2006.161.08:15:33.63#ibcon#*before return 0, iclass 30, count 0 2006.161.08:15:33.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:15:33.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:15:33.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:15:33.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:15:33.63$4f8m12a/ifd4f 2006.161.08:15:33.63$ifd4f/lo= 2006.161.08:15:33.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:15:33.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:15:33.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:15:33.63$ifd4f/patch= 2006.161.08:15:33.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:15:33.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:15:33.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:15:33.63$4f8m12a/"form=m,16.000,1:2 2006.161.08:15:33.63$4f8m12a/"tpicd 2006.161.08:15:33.63$4f8m12a/echo=off 2006.161.08:15:33.63$4f8m12a/xlog=off 2006.161.08:15:33.63:!2006.161.08:16:00 2006.161.08:15:43.14#trakl#Source acquired 2006.161.08:15:45.14#flagr#flagr/antenna,acquired 2006.161.08:16:00.00:preob 2006.161.08:16:01.14/onsource/TRACKING 2006.161.08:16:01.14:!2006.161.08:16:10 2006.161.08:16:10.00:data_valid=on 2006.161.08:16:10.00:midob 2006.161.08:16:10.14/onsource/TRACKING 2006.161.08:16:10.14/wx/24.00,1002.5,85 2006.161.08:16:10.29/cable/+6.4996E-03 2006.161.08:16:11.38/va/01,08,usb,yes,30,31 2006.161.08:16:11.38/va/02,07,usb,yes,30,31 2006.161.08:16:11.38/va/03,06,usb,yes,32,32 2006.161.08:16:11.38/va/04,07,usb,yes,31,33 2006.161.08:16:11.38/va/05,07,usb,yes,31,33 2006.161.08:16:11.38/va/06,06,usb,yes,30,30 2006.161.08:16:11.38/va/07,06,usb,yes,30,30 2006.161.08:16:11.38/va/08,07,usb,yes,29,28 2006.161.08:16:11.61/valo/01,532.99,yes,locked 2006.161.08:16:11.61/valo/02,572.99,yes,locked 2006.161.08:16:11.61/valo/03,672.99,yes,locked 2006.161.08:16:11.61/valo/04,832.99,yes,locked 2006.161.08:16:11.61/valo/05,652.99,yes,locked 2006.161.08:16:11.61/valo/06,772.99,yes,locked 2006.161.08:16:11.61/valo/07,832.99,yes,locked 2006.161.08:16:11.61/valo/08,852.99,yes,locked 2006.161.08:16:12.70/vb/01,04,usb,yes,29,28 2006.161.08:16:12.70/vb/02,04,usb,yes,31,33 2006.161.08:16:12.70/vb/03,04,usb,yes,28,31 2006.161.08:16:12.70/vb/04,04,usb,yes,28,29 2006.161.08:16:12.70/vb/05,04,usb,yes,27,31 2006.161.08:16:12.70/vb/06,04,usb,yes,28,31 2006.161.08:16:12.70/vb/07,04,usb,yes,30,30 2006.161.08:16:12.70/vb/08,04,usb,yes,28,31 2006.161.08:16:12.93/vblo/01,632.99,yes,locked 2006.161.08:16:12.93/vblo/02,640.99,yes,locked 2006.161.08:16:12.93/vblo/03,656.99,yes,locked 2006.161.08:16:12.93/vblo/04,712.99,yes,locked 2006.161.08:16:12.93/vblo/05,744.99,yes,locked 2006.161.08:16:12.93/vblo/06,752.99,yes,locked 2006.161.08:16:12.93/vblo/07,734.99,yes,locked 2006.161.08:16:12.93/vblo/08,744.99,yes,locked 2006.161.08:16:13.08/vabw/8 2006.161.08:16:13.23/vbbw/8 2006.161.08:16:13.32/xfe/off,on,14.2 2006.161.08:16:13.70/ifatt/23,28,28,28 2006.161.08:16:14.08/fmout-gps/S +4.49E-07 2006.161.08:16:14.12:!2006.161.08:17:10 2006.161.08:17:10.00:data_valid=off 2006.161.08:17:10.00:postob 2006.161.08:17:10.08/cable/+6.4997E-03 2006.161.08:17:10.08/wx/23.99,1002.5,86 2006.161.08:17:11.08/fmout-gps/S +4.50E-07 2006.161.08:17:11.08:scan_name=161-0819,k06161,60 2006.161.08:17:11.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.161.08:17:11.14#flagr#flagr/antenna,new-source 2006.161.08:17:12.14:checkk5 2006.161.08:17:12.58/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:17:13.07/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:17:13.50/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:17:13.91/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:17:14.34/chk_obsdata//k5ts1/T1610816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:17:14.77/chk_obsdata//k5ts2/T1610816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:17:15.40/chk_obsdata//k5ts3/T1610816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:17:15.89/chk_obsdata//k5ts4/T1610816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:17:16.68/k5log//k5ts1_log_newline 2006.161.08:17:17.43/k5log//k5ts2_log_newline 2006.161.08:17:18.22/k5log//k5ts3_log_newline 2006.161.08:17:19.49/k5log//k5ts4_log_newline 2006.161.08:17:19.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:17:19.51:4f8m12a=3 2006.161.08:17:19.51$4f8m12a/echo=on 2006.161.08:17:19.52$4f8m12a/pcalon 2006.161.08:17:19.52$pcalon/"no phase cal control is implemented here 2006.161.08:17:19.52$4f8m12a/"tpicd=stop 2006.161.08:17:19.52$4f8m12a/vc4f8 2006.161.08:17:19.52$vc4f8/valo=1,532.99 2006.161.08:17:19.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:17:19.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:17:19.52#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:19.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:19.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:19.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:19.52#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:17:19.52#ibcon#first serial, iclass 37, count 0 2006.161.08:17:19.52#ibcon#enter sib2, iclass 37, count 0 2006.161.08:17:19.52#ibcon#flushed, iclass 37, count 0 2006.161.08:17:19.52#ibcon#about to write, iclass 37, count 0 2006.161.08:17:19.52#ibcon#wrote, iclass 37, count 0 2006.161.08:17:19.52#ibcon#about to read 3, iclass 37, count 0 2006.161.08:17:19.56#ibcon#read 3, iclass 37, count 0 2006.161.08:17:19.56#ibcon#about to read 4, iclass 37, count 0 2006.161.08:17:19.56#ibcon#read 4, iclass 37, count 0 2006.161.08:17:19.56#ibcon#about to read 5, iclass 37, count 0 2006.161.08:17:19.56#ibcon#read 5, iclass 37, count 0 2006.161.08:17:19.56#ibcon#about to read 6, iclass 37, count 0 2006.161.08:17:19.56#ibcon#read 6, iclass 37, count 0 2006.161.08:17:19.56#ibcon#end of sib2, iclass 37, count 0 2006.161.08:17:19.56#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:17:19.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:17:19.56#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:17:19.56#ibcon#*before write, iclass 37, count 0 2006.161.08:17:19.56#ibcon#enter sib2, iclass 37, count 0 2006.161.08:17:19.56#ibcon#flushed, iclass 37, count 0 2006.161.08:17:19.56#ibcon#about to write, iclass 37, count 0 2006.161.08:17:19.56#ibcon#wrote, iclass 37, count 0 2006.161.08:17:19.56#ibcon#about to read 3, iclass 37, count 0 2006.161.08:17:19.61#ibcon#read 3, iclass 37, count 0 2006.161.08:17:19.61#ibcon#about to read 4, iclass 37, count 0 2006.161.08:17:19.61#ibcon#read 4, iclass 37, count 0 2006.161.08:17:19.61#ibcon#about to read 5, iclass 37, count 0 2006.161.08:17:19.61#ibcon#read 5, iclass 37, count 0 2006.161.08:17:19.61#ibcon#about to read 6, iclass 37, count 0 2006.161.08:17:19.61#ibcon#read 6, iclass 37, count 0 2006.161.08:17:19.61#ibcon#end of sib2, iclass 37, count 0 2006.161.08:17:19.61#ibcon#*after write, iclass 37, count 0 2006.161.08:17:19.61#ibcon#*before return 0, iclass 37, count 0 2006.161.08:17:19.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:19.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:19.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:17:19.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:17:19.61$vc4f8/va=1,8 2006.161.08:17:19.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:17:19.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:17:19.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:19.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:19.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:19.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:19.61#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:17:19.61#ibcon#first serial, iclass 39, count 2 2006.161.08:17:19.61#ibcon#enter sib2, iclass 39, count 2 2006.161.08:17:19.61#ibcon#flushed, iclass 39, count 2 2006.161.08:17:19.61#ibcon#about to write, iclass 39, count 2 2006.161.08:17:19.61#ibcon#wrote, iclass 39, count 2 2006.161.08:17:19.61#ibcon#about to read 3, iclass 39, count 2 2006.161.08:17:19.63#ibcon#read 3, iclass 39, count 2 2006.161.08:17:19.63#ibcon#about to read 4, iclass 39, count 2 2006.161.08:17:19.63#ibcon#read 4, iclass 39, count 2 2006.161.08:17:19.63#ibcon#about to read 5, iclass 39, count 2 2006.161.08:17:19.63#ibcon#read 5, iclass 39, count 2 2006.161.08:17:19.63#ibcon#about to read 6, iclass 39, count 2 2006.161.08:17:19.63#ibcon#read 6, iclass 39, count 2 2006.161.08:17:19.63#ibcon#end of sib2, iclass 39, count 2 2006.161.08:17:19.63#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:17:19.63#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:17:19.63#ibcon#[25=AT01-08\r\n] 2006.161.08:17:19.63#ibcon#*before write, iclass 39, count 2 2006.161.08:17:19.63#ibcon#enter sib2, iclass 39, count 2 2006.161.08:17:19.63#ibcon#flushed, iclass 39, count 2 2006.161.08:17:19.63#ibcon#about to write, iclass 39, count 2 2006.161.08:17:19.63#ibcon#wrote, iclass 39, count 2 2006.161.08:17:19.63#ibcon#about to read 3, iclass 39, count 2 2006.161.08:17:19.66#ibcon#read 3, iclass 39, count 2 2006.161.08:17:19.66#ibcon#about to read 4, iclass 39, count 2 2006.161.08:17:19.66#ibcon#read 4, iclass 39, count 2 2006.161.08:17:19.66#ibcon#about to read 5, iclass 39, count 2 2006.161.08:17:19.66#ibcon#read 5, iclass 39, count 2 2006.161.08:17:19.66#ibcon#about to read 6, iclass 39, count 2 2006.161.08:17:19.66#ibcon#read 6, iclass 39, count 2 2006.161.08:17:19.66#ibcon#end of sib2, iclass 39, count 2 2006.161.08:17:19.66#ibcon#*after write, iclass 39, count 2 2006.161.08:17:19.66#ibcon#*before return 0, iclass 39, count 2 2006.161.08:17:19.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:19.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:19.66#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:17:19.66#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:19.66#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:19.78#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:19.78#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:19.78#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:17:19.78#ibcon#first serial, iclass 39, count 0 2006.161.08:17:19.78#ibcon#enter sib2, iclass 39, count 0 2006.161.08:17:19.78#ibcon#flushed, iclass 39, count 0 2006.161.08:17:19.78#ibcon#about to write, iclass 39, count 0 2006.161.08:17:19.78#ibcon#wrote, iclass 39, count 0 2006.161.08:17:19.78#ibcon#about to read 3, iclass 39, count 0 2006.161.08:17:19.80#ibcon#read 3, iclass 39, count 0 2006.161.08:17:19.80#ibcon#about to read 4, iclass 39, count 0 2006.161.08:17:19.80#ibcon#read 4, iclass 39, count 0 2006.161.08:17:19.80#ibcon#about to read 5, iclass 39, count 0 2006.161.08:17:19.80#ibcon#read 5, iclass 39, count 0 2006.161.08:17:19.80#ibcon#about to read 6, iclass 39, count 0 2006.161.08:17:19.80#ibcon#read 6, iclass 39, count 0 2006.161.08:17:19.80#ibcon#end of sib2, iclass 39, count 0 2006.161.08:17:19.80#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:17:19.80#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:17:19.80#ibcon#[25=USB\r\n] 2006.161.08:17:19.80#ibcon#*before write, iclass 39, count 0 2006.161.08:17:19.80#ibcon#enter sib2, iclass 39, count 0 2006.161.08:17:19.80#ibcon#flushed, iclass 39, count 0 2006.161.08:17:19.80#ibcon#about to write, iclass 39, count 0 2006.161.08:17:19.80#ibcon#wrote, iclass 39, count 0 2006.161.08:17:19.80#ibcon#about to read 3, iclass 39, count 0 2006.161.08:17:19.83#ibcon#read 3, iclass 39, count 0 2006.161.08:17:19.83#ibcon#about to read 4, iclass 39, count 0 2006.161.08:17:19.83#ibcon#read 4, iclass 39, count 0 2006.161.08:17:19.83#ibcon#about to read 5, iclass 39, count 0 2006.161.08:17:19.83#ibcon#read 5, iclass 39, count 0 2006.161.08:17:19.83#ibcon#about to read 6, iclass 39, count 0 2006.161.08:17:19.83#ibcon#read 6, iclass 39, count 0 2006.161.08:17:19.83#ibcon#end of sib2, iclass 39, count 0 2006.161.08:17:19.83#ibcon#*after write, iclass 39, count 0 2006.161.08:17:19.83#ibcon#*before return 0, iclass 39, count 0 2006.161.08:17:19.83#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:19.83#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:19.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:17:19.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:17:19.83$vc4f8/valo=2,572.99 2006.161.08:17:19.83#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:17:19.83#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:17:19.83#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:19.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:19.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:19.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:19.83#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:17:19.83#ibcon#first serial, iclass 3, count 0 2006.161.08:17:19.83#ibcon#enter sib2, iclass 3, count 0 2006.161.08:17:19.83#ibcon#flushed, iclass 3, count 0 2006.161.08:17:19.83#ibcon#about to write, iclass 3, count 0 2006.161.08:17:19.83#ibcon#wrote, iclass 3, count 0 2006.161.08:17:19.83#ibcon#about to read 3, iclass 3, count 0 2006.161.08:17:19.86#ibcon#read 3, iclass 3, count 0 2006.161.08:17:19.86#ibcon#about to read 4, iclass 3, count 0 2006.161.08:17:19.86#ibcon#read 4, iclass 3, count 0 2006.161.08:17:19.86#ibcon#about to read 5, iclass 3, count 0 2006.161.08:17:19.86#ibcon#read 5, iclass 3, count 0 2006.161.08:17:19.86#ibcon#about to read 6, iclass 3, count 0 2006.161.08:17:19.86#ibcon#read 6, iclass 3, count 0 2006.161.08:17:19.86#ibcon#end of sib2, iclass 3, count 0 2006.161.08:17:19.86#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:17:19.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:17:19.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:17:19.86#ibcon#*before write, iclass 3, count 0 2006.161.08:17:19.86#ibcon#enter sib2, iclass 3, count 0 2006.161.08:17:19.86#ibcon#flushed, iclass 3, count 0 2006.161.08:17:19.86#ibcon#about to write, iclass 3, count 0 2006.161.08:17:19.86#ibcon#wrote, iclass 3, count 0 2006.161.08:17:19.86#ibcon#about to read 3, iclass 3, count 0 2006.161.08:17:19.90#ibcon#read 3, iclass 3, count 0 2006.161.08:17:19.90#ibcon#about to read 4, iclass 3, count 0 2006.161.08:17:19.90#ibcon#read 4, iclass 3, count 0 2006.161.08:17:19.90#ibcon#about to read 5, iclass 3, count 0 2006.161.08:17:19.90#ibcon#read 5, iclass 3, count 0 2006.161.08:17:19.90#ibcon#about to read 6, iclass 3, count 0 2006.161.08:17:19.90#ibcon#read 6, iclass 3, count 0 2006.161.08:17:19.90#ibcon#end of sib2, iclass 3, count 0 2006.161.08:17:19.90#ibcon#*after write, iclass 3, count 0 2006.161.08:17:19.90#ibcon#*before return 0, iclass 3, count 0 2006.161.08:17:19.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:19.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:19.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:17:19.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:17:19.90$vc4f8/va=2,7 2006.161.08:17:19.90#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:17:19.90#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:17:19.90#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:19.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:19.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:19.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:19.95#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:17:19.95#ibcon#first serial, iclass 5, count 2 2006.161.08:17:19.95#ibcon#enter sib2, iclass 5, count 2 2006.161.08:17:19.95#ibcon#flushed, iclass 5, count 2 2006.161.08:17:19.95#ibcon#about to write, iclass 5, count 2 2006.161.08:17:19.95#ibcon#wrote, iclass 5, count 2 2006.161.08:17:19.95#ibcon#about to read 3, iclass 5, count 2 2006.161.08:17:19.98#ibcon#read 3, iclass 5, count 2 2006.161.08:17:19.98#ibcon#about to read 4, iclass 5, count 2 2006.161.08:17:19.98#ibcon#read 4, iclass 5, count 2 2006.161.08:17:19.98#ibcon#about to read 5, iclass 5, count 2 2006.161.08:17:19.98#ibcon#read 5, iclass 5, count 2 2006.161.08:17:19.98#ibcon#about to read 6, iclass 5, count 2 2006.161.08:17:19.98#ibcon#read 6, iclass 5, count 2 2006.161.08:17:19.98#ibcon#end of sib2, iclass 5, count 2 2006.161.08:17:19.98#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:17:19.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:17:19.98#ibcon#[25=AT02-07\r\n] 2006.161.08:17:19.98#ibcon#*before write, iclass 5, count 2 2006.161.08:17:19.98#ibcon#enter sib2, iclass 5, count 2 2006.161.08:17:19.98#ibcon#flushed, iclass 5, count 2 2006.161.08:17:19.98#ibcon#about to write, iclass 5, count 2 2006.161.08:17:19.98#ibcon#wrote, iclass 5, count 2 2006.161.08:17:19.98#ibcon#about to read 3, iclass 5, count 2 2006.161.08:17:20.01#ibcon#read 3, iclass 5, count 2 2006.161.08:17:20.01#ibcon#about to read 4, iclass 5, count 2 2006.161.08:17:20.01#ibcon#read 4, iclass 5, count 2 2006.161.08:17:20.01#ibcon#about to read 5, iclass 5, count 2 2006.161.08:17:20.01#ibcon#read 5, iclass 5, count 2 2006.161.08:17:20.01#ibcon#about to read 6, iclass 5, count 2 2006.161.08:17:20.01#ibcon#read 6, iclass 5, count 2 2006.161.08:17:20.01#ibcon#end of sib2, iclass 5, count 2 2006.161.08:17:20.01#ibcon#*after write, iclass 5, count 2 2006.161.08:17:20.01#ibcon#*before return 0, iclass 5, count 2 2006.161.08:17:20.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:20.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:20.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:17:20.01#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:20.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:20.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:20.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:20.13#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:17:20.13#ibcon#first serial, iclass 5, count 0 2006.161.08:17:20.13#ibcon#enter sib2, iclass 5, count 0 2006.161.08:17:20.13#ibcon#flushed, iclass 5, count 0 2006.161.08:17:20.13#ibcon#about to write, iclass 5, count 0 2006.161.08:17:20.13#ibcon#wrote, iclass 5, count 0 2006.161.08:17:20.13#ibcon#about to read 3, iclass 5, count 0 2006.161.08:17:20.15#ibcon#read 3, iclass 5, count 0 2006.161.08:17:20.15#ibcon#about to read 4, iclass 5, count 0 2006.161.08:17:20.15#ibcon#read 4, iclass 5, count 0 2006.161.08:17:20.15#ibcon#about to read 5, iclass 5, count 0 2006.161.08:17:20.15#ibcon#read 5, iclass 5, count 0 2006.161.08:17:20.15#ibcon#about to read 6, iclass 5, count 0 2006.161.08:17:20.15#ibcon#read 6, iclass 5, count 0 2006.161.08:17:20.15#ibcon#end of sib2, iclass 5, count 0 2006.161.08:17:20.15#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:17:20.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:17:20.15#ibcon#[25=USB\r\n] 2006.161.08:17:20.15#ibcon#*before write, iclass 5, count 0 2006.161.08:17:20.15#ibcon#enter sib2, iclass 5, count 0 2006.161.08:17:20.15#ibcon#flushed, iclass 5, count 0 2006.161.08:17:20.15#ibcon#about to write, iclass 5, count 0 2006.161.08:17:20.15#ibcon#wrote, iclass 5, count 0 2006.161.08:17:20.15#ibcon#about to read 3, iclass 5, count 0 2006.161.08:17:20.18#ibcon#read 3, iclass 5, count 0 2006.161.08:17:20.18#ibcon#about to read 4, iclass 5, count 0 2006.161.08:17:20.18#ibcon#read 4, iclass 5, count 0 2006.161.08:17:20.18#ibcon#about to read 5, iclass 5, count 0 2006.161.08:17:20.18#ibcon#read 5, iclass 5, count 0 2006.161.08:17:20.18#ibcon#about to read 6, iclass 5, count 0 2006.161.08:17:20.18#ibcon#read 6, iclass 5, count 0 2006.161.08:17:20.18#ibcon#end of sib2, iclass 5, count 0 2006.161.08:17:20.18#ibcon#*after write, iclass 5, count 0 2006.161.08:17:20.18#ibcon#*before return 0, iclass 5, count 0 2006.161.08:17:20.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:20.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:20.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:17:20.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:17:20.18$vc4f8/valo=3,672.99 2006.161.08:17:20.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:17:20.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:17:20.18#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:20.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:20.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:20.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:20.18#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:17:20.18#ibcon#first serial, iclass 7, count 0 2006.161.08:17:20.18#ibcon#enter sib2, iclass 7, count 0 2006.161.08:17:20.18#ibcon#flushed, iclass 7, count 0 2006.161.08:17:20.18#ibcon#about to write, iclass 7, count 0 2006.161.08:17:20.18#ibcon#wrote, iclass 7, count 0 2006.161.08:17:20.18#ibcon#about to read 3, iclass 7, count 0 2006.161.08:17:20.21#ibcon#read 3, iclass 7, count 0 2006.161.08:17:20.21#ibcon#about to read 4, iclass 7, count 0 2006.161.08:17:20.21#ibcon#read 4, iclass 7, count 0 2006.161.08:17:20.21#ibcon#about to read 5, iclass 7, count 0 2006.161.08:17:20.21#ibcon#read 5, iclass 7, count 0 2006.161.08:17:20.21#ibcon#about to read 6, iclass 7, count 0 2006.161.08:17:20.21#ibcon#read 6, iclass 7, count 0 2006.161.08:17:20.21#ibcon#end of sib2, iclass 7, count 0 2006.161.08:17:20.21#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:17:20.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:17:20.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:17:20.21#ibcon#*before write, iclass 7, count 0 2006.161.08:17:20.21#ibcon#enter sib2, iclass 7, count 0 2006.161.08:17:20.21#ibcon#flushed, iclass 7, count 0 2006.161.08:17:20.21#ibcon#about to write, iclass 7, count 0 2006.161.08:17:20.21#ibcon#wrote, iclass 7, count 0 2006.161.08:17:20.21#ibcon#about to read 3, iclass 7, count 0 2006.161.08:17:20.25#ibcon#read 3, iclass 7, count 0 2006.161.08:17:20.25#ibcon#about to read 4, iclass 7, count 0 2006.161.08:17:20.25#ibcon#read 4, iclass 7, count 0 2006.161.08:17:20.25#ibcon#about to read 5, iclass 7, count 0 2006.161.08:17:20.25#ibcon#read 5, iclass 7, count 0 2006.161.08:17:20.25#ibcon#about to read 6, iclass 7, count 0 2006.161.08:17:20.25#ibcon#read 6, iclass 7, count 0 2006.161.08:17:20.25#ibcon#end of sib2, iclass 7, count 0 2006.161.08:17:20.25#ibcon#*after write, iclass 7, count 0 2006.161.08:17:20.25#ibcon#*before return 0, iclass 7, count 0 2006.161.08:17:20.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:20.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:20.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:17:20.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:17:20.25$vc4f8/va=3,6 2006.161.08:17:20.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:17:20.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:17:20.25#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:20.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:20.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:20.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:20.30#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:17:20.30#ibcon#first serial, iclass 11, count 2 2006.161.08:17:20.30#ibcon#enter sib2, iclass 11, count 2 2006.161.08:17:20.30#ibcon#flushed, iclass 11, count 2 2006.161.08:17:20.30#ibcon#about to write, iclass 11, count 2 2006.161.08:17:20.30#ibcon#wrote, iclass 11, count 2 2006.161.08:17:20.30#ibcon#about to read 3, iclass 11, count 2 2006.161.08:17:20.33#ibcon#read 3, iclass 11, count 2 2006.161.08:17:20.33#ibcon#about to read 4, iclass 11, count 2 2006.161.08:17:20.33#ibcon#read 4, iclass 11, count 2 2006.161.08:17:20.33#ibcon#about to read 5, iclass 11, count 2 2006.161.08:17:20.33#ibcon#read 5, iclass 11, count 2 2006.161.08:17:20.33#ibcon#about to read 6, iclass 11, count 2 2006.161.08:17:20.33#ibcon#read 6, iclass 11, count 2 2006.161.08:17:20.33#ibcon#end of sib2, iclass 11, count 2 2006.161.08:17:20.33#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:17:20.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:17:20.33#ibcon#[25=AT03-06\r\n] 2006.161.08:17:20.33#ibcon#*before write, iclass 11, count 2 2006.161.08:17:20.33#ibcon#enter sib2, iclass 11, count 2 2006.161.08:17:20.33#ibcon#flushed, iclass 11, count 2 2006.161.08:17:20.33#ibcon#about to write, iclass 11, count 2 2006.161.08:17:20.33#ibcon#wrote, iclass 11, count 2 2006.161.08:17:20.33#ibcon#about to read 3, iclass 11, count 2 2006.161.08:17:20.36#ibcon#read 3, iclass 11, count 2 2006.161.08:17:20.36#ibcon#about to read 4, iclass 11, count 2 2006.161.08:17:20.36#ibcon#read 4, iclass 11, count 2 2006.161.08:17:20.36#ibcon#about to read 5, iclass 11, count 2 2006.161.08:17:20.36#ibcon#read 5, iclass 11, count 2 2006.161.08:17:20.36#ibcon#about to read 6, iclass 11, count 2 2006.161.08:17:20.36#ibcon#read 6, iclass 11, count 2 2006.161.08:17:20.36#ibcon#end of sib2, iclass 11, count 2 2006.161.08:17:20.36#ibcon#*after write, iclass 11, count 2 2006.161.08:17:20.36#ibcon#*before return 0, iclass 11, count 2 2006.161.08:17:20.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:20.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:20.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:17:20.36#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:20.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:20.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:20.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:20.48#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:17:20.48#ibcon#first serial, iclass 11, count 0 2006.161.08:17:20.48#ibcon#enter sib2, iclass 11, count 0 2006.161.08:17:20.48#ibcon#flushed, iclass 11, count 0 2006.161.08:17:20.48#ibcon#about to write, iclass 11, count 0 2006.161.08:17:20.48#ibcon#wrote, iclass 11, count 0 2006.161.08:17:20.48#ibcon#about to read 3, iclass 11, count 0 2006.161.08:17:20.50#ibcon#read 3, iclass 11, count 0 2006.161.08:17:20.50#ibcon#about to read 4, iclass 11, count 0 2006.161.08:17:20.50#ibcon#read 4, iclass 11, count 0 2006.161.08:17:20.50#ibcon#about to read 5, iclass 11, count 0 2006.161.08:17:20.50#ibcon#read 5, iclass 11, count 0 2006.161.08:17:20.50#ibcon#about to read 6, iclass 11, count 0 2006.161.08:17:20.50#ibcon#read 6, iclass 11, count 0 2006.161.08:17:20.50#ibcon#end of sib2, iclass 11, count 0 2006.161.08:17:20.50#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:17:20.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:17:20.50#ibcon#[25=USB\r\n] 2006.161.08:17:20.50#ibcon#*before write, iclass 11, count 0 2006.161.08:17:20.50#ibcon#enter sib2, iclass 11, count 0 2006.161.08:17:20.50#ibcon#flushed, iclass 11, count 0 2006.161.08:17:20.50#ibcon#about to write, iclass 11, count 0 2006.161.08:17:20.50#ibcon#wrote, iclass 11, count 0 2006.161.08:17:20.50#ibcon#about to read 3, iclass 11, count 0 2006.161.08:17:20.53#ibcon#read 3, iclass 11, count 0 2006.161.08:17:20.53#ibcon#about to read 4, iclass 11, count 0 2006.161.08:17:20.53#ibcon#read 4, iclass 11, count 0 2006.161.08:17:20.53#ibcon#about to read 5, iclass 11, count 0 2006.161.08:17:20.53#ibcon#read 5, iclass 11, count 0 2006.161.08:17:20.53#ibcon#about to read 6, iclass 11, count 0 2006.161.08:17:20.53#ibcon#read 6, iclass 11, count 0 2006.161.08:17:20.53#ibcon#end of sib2, iclass 11, count 0 2006.161.08:17:20.53#ibcon#*after write, iclass 11, count 0 2006.161.08:17:20.53#ibcon#*before return 0, iclass 11, count 0 2006.161.08:17:20.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:20.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:20.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:17:20.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:17:20.53$vc4f8/valo=4,832.99 2006.161.08:17:20.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:17:20.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:17:20.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:20.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:20.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:20.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:20.53#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:17:20.53#ibcon#first serial, iclass 13, count 0 2006.161.08:17:20.53#ibcon#enter sib2, iclass 13, count 0 2006.161.08:17:20.53#ibcon#flushed, iclass 13, count 0 2006.161.08:17:20.53#ibcon#about to write, iclass 13, count 0 2006.161.08:17:20.53#ibcon#wrote, iclass 13, count 0 2006.161.08:17:20.53#ibcon#about to read 3, iclass 13, count 0 2006.161.08:17:20.55#ibcon#read 3, iclass 13, count 0 2006.161.08:17:20.55#ibcon#about to read 4, iclass 13, count 0 2006.161.08:17:20.55#ibcon#read 4, iclass 13, count 0 2006.161.08:17:20.55#ibcon#about to read 5, iclass 13, count 0 2006.161.08:17:20.55#ibcon#read 5, iclass 13, count 0 2006.161.08:17:20.55#ibcon#about to read 6, iclass 13, count 0 2006.161.08:17:20.55#ibcon#read 6, iclass 13, count 0 2006.161.08:17:20.55#ibcon#end of sib2, iclass 13, count 0 2006.161.08:17:20.55#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:17:20.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:17:20.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:17:20.55#ibcon#*before write, iclass 13, count 0 2006.161.08:17:20.55#ibcon#enter sib2, iclass 13, count 0 2006.161.08:17:20.55#ibcon#flushed, iclass 13, count 0 2006.161.08:17:20.55#ibcon#about to write, iclass 13, count 0 2006.161.08:17:20.55#ibcon#wrote, iclass 13, count 0 2006.161.08:17:20.55#ibcon#about to read 3, iclass 13, count 0 2006.161.08:17:20.59#ibcon#read 3, iclass 13, count 0 2006.161.08:17:20.59#ibcon#about to read 4, iclass 13, count 0 2006.161.08:17:20.59#ibcon#read 4, iclass 13, count 0 2006.161.08:17:20.59#ibcon#about to read 5, iclass 13, count 0 2006.161.08:17:20.59#ibcon#read 5, iclass 13, count 0 2006.161.08:17:20.59#ibcon#about to read 6, iclass 13, count 0 2006.161.08:17:20.59#ibcon#read 6, iclass 13, count 0 2006.161.08:17:20.59#ibcon#end of sib2, iclass 13, count 0 2006.161.08:17:20.59#ibcon#*after write, iclass 13, count 0 2006.161.08:17:20.59#ibcon#*before return 0, iclass 13, count 0 2006.161.08:17:20.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:20.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:20.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:17:20.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:17:20.59$vc4f8/va=4,7 2006.161.08:17:20.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:17:20.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:17:20.59#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:20.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:20.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:20.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:20.65#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:17:20.65#ibcon#first serial, iclass 15, count 2 2006.161.08:17:20.65#ibcon#enter sib2, iclass 15, count 2 2006.161.08:17:20.65#ibcon#flushed, iclass 15, count 2 2006.161.08:17:20.65#ibcon#about to write, iclass 15, count 2 2006.161.08:17:20.65#ibcon#wrote, iclass 15, count 2 2006.161.08:17:20.65#ibcon#about to read 3, iclass 15, count 2 2006.161.08:17:20.67#ibcon#read 3, iclass 15, count 2 2006.161.08:17:20.67#ibcon#about to read 4, iclass 15, count 2 2006.161.08:17:20.67#ibcon#read 4, iclass 15, count 2 2006.161.08:17:20.67#ibcon#about to read 5, iclass 15, count 2 2006.161.08:17:20.67#ibcon#read 5, iclass 15, count 2 2006.161.08:17:20.67#ibcon#about to read 6, iclass 15, count 2 2006.161.08:17:20.67#ibcon#read 6, iclass 15, count 2 2006.161.08:17:20.67#ibcon#end of sib2, iclass 15, count 2 2006.161.08:17:20.67#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:17:20.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:17:20.67#ibcon#[25=AT04-07\r\n] 2006.161.08:17:20.67#ibcon#*before write, iclass 15, count 2 2006.161.08:17:20.67#ibcon#enter sib2, iclass 15, count 2 2006.161.08:17:20.67#ibcon#flushed, iclass 15, count 2 2006.161.08:17:20.67#ibcon#about to write, iclass 15, count 2 2006.161.08:17:20.67#ibcon#wrote, iclass 15, count 2 2006.161.08:17:20.67#ibcon#about to read 3, iclass 15, count 2 2006.161.08:17:20.70#ibcon#read 3, iclass 15, count 2 2006.161.08:17:20.70#ibcon#about to read 4, iclass 15, count 2 2006.161.08:17:20.70#ibcon#read 4, iclass 15, count 2 2006.161.08:17:20.70#ibcon#about to read 5, iclass 15, count 2 2006.161.08:17:20.70#ibcon#read 5, iclass 15, count 2 2006.161.08:17:20.70#ibcon#about to read 6, iclass 15, count 2 2006.161.08:17:20.70#ibcon#read 6, iclass 15, count 2 2006.161.08:17:20.70#ibcon#end of sib2, iclass 15, count 2 2006.161.08:17:20.70#ibcon#*after write, iclass 15, count 2 2006.161.08:17:20.70#ibcon#*before return 0, iclass 15, count 2 2006.161.08:17:20.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:20.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:20.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:17:20.70#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:20.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:20.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:20.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:20.82#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:17:20.82#ibcon#first serial, iclass 15, count 0 2006.161.08:17:20.82#ibcon#enter sib2, iclass 15, count 0 2006.161.08:17:20.82#ibcon#flushed, iclass 15, count 0 2006.161.08:17:20.82#ibcon#about to write, iclass 15, count 0 2006.161.08:17:20.82#ibcon#wrote, iclass 15, count 0 2006.161.08:17:20.82#ibcon#about to read 3, iclass 15, count 0 2006.161.08:17:20.84#ibcon#read 3, iclass 15, count 0 2006.161.08:17:20.84#ibcon#about to read 4, iclass 15, count 0 2006.161.08:17:20.84#ibcon#read 4, iclass 15, count 0 2006.161.08:17:20.84#ibcon#about to read 5, iclass 15, count 0 2006.161.08:17:20.84#ibcon#read 5, iclass 15, count 0 2006.161.08:17:20.84#ibcon#about to read 6, iclass 15, count 0 2006.161.08:17:20.84#ibcon#read 6, iclass 15, count 0 2006.161.08:17:20.84#ibcon#end of sib2, iclass 15, count 0 2006.161.08:17:20.84#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:17:20.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:17:20.84#ibcon#[25=USB\r\n] 2006.161.08:17:20.84#ibcon#*before write, iclass 15, count 0 2006.161.08:17:20.84#ibcon#enter sib2, iclass 15, count 0 2006.161.08:17:20.84#ibcon#flushed, iclass 15, count 0 2006.161.08:17:20.84#ibcon#about to write, iclass 15, count 0 2006.161.08:17:20.84#ibcon#wrote, iclass 15, count 0 2006.161.08:17:20.84#ibcon#about to read 3, iclass 15, count 0 2006.161.08:17:20.87#ibcon#read 3, iclass 15, count 0 2006.161.08:17:20.87#ibcon#about to read 4, iclass 15, count 0 2006.161.08:17:20.87#ibcon#read 4, iclass 15, count 0 2006.161.08:17:20.87#ibcon#about to read 5, iclass 15, count 0 2006.161.08:17:20.87#ibcon#read 5, iclass 15, count 0 2006.161.08:17:20.87#ibcon#about to read 6, iclass 15, count 0 2006.161.08:17:20.87#ibcon#read 6, iclass 15, count 0 2006.161.08:17:20.87#ibcon#end of sib2, iclass 15, count 0 2006.161.08:17:20.87#ibcon#*after write, iclass 15, count 0 2006.161.08:17:20.87#ibcon#*before return 0, iclass 15, count 0 2006.161.08:17:20.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:20.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:20.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:17:20.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:17:20.87$vc4f8/valo=5,652.99 2006.161.08:17:20.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:17:20.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:17:20.87#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:20.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:20.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:20.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:20.87#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:17:20.87#ibcon#first serial, iclass 17, count 0 2006.161.08:17:20.87#ibcon#enter sib2, iclass 17, count 0 2006.161.08:17:20.87#ibcon#flushed, iclass 17, count 0 2006.161.08:17:20.87#ibcon#about to write, iclass 17, count 0 2006.161.08:17:20.87#ibcon#wrote, iclass 17, count 0 2006.161.08:17:20.87#ibcon#about to read 3, iclass 17, count 0 2006.161.08:17:20.89#ibcon#read 3, iclass 17, count 0 2006.161.08:17:20.89#ibcon#about to read 4, iclass 17, count 0 2006.161.08:17:20.89#ibcon#read 4, iclass 17, count 0 2006.161.08:17:20.89#ibcon#about to read 5, iclass 17, count 0 2006.161.08:17:20.89#ibcon#read 5, iclass 17, count 0 2006.161.08:17:20.89#ibcon#about to read 6, iclass 17, count 0 2006.161.08:17:20.89#ibcon#read 6, iclass 17, count 0 2006.161.08:17:20.89#ibcon#end of sib2, iclass 17, count 0 2006.161.08:17:20.89#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:17:20.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:17:20.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:17:20.89#ibcon#*before write, iclass 17, count 0 2006.161.08:17:20.89#ibcon#enter sib2, iclass 17, count 0 2006.161.08:17:20.89#ibcon#flushed, iclass 17, count 0 2006.161.08:17:20.89#ibcon#about to write, iclass 17, count 0 2006.161.08:17:20.89#ibcon#wrote, iclass 17, count 0 2006.161.08:17:20.89#ibcon#about to read 3, iclass 17, count 0 2006.161.08:17:20.93#ibcon#read 3, iclass 17, count 0 2006.161.08:17:20.93#ibcon#about to read 4, iclass 17, count 0 2006.161.08:17:20.93#ibcon#read 4, iclass 17, count 0 2006.161.08:17:20.93#ibcon#about to read 5, iclass 17, count 0 2006.161.08:17:20.93#ibcon#read 5, iclass 17, count 0 2006.161.08:17:20.93#ibcon#about to read 6, iclass 17, count 0 2006.161.08:17:20.93#ibcon#read 6, iclass 17, count 0 2006.161.08:17:20.93#ibcon#end of sib2, iclass 17, count 0 2006.161.08:17:20.93#ibcon#*after write, iclass 17, count 0 2006.161.08:17:20.93#ibcon#*before return 0, iclass 17, count 0 2006.161.08:17:20.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:20.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:20.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:17:20.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:17:20.93$vc4f8/va=5,7 2006.161.08:17:20.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:17:20.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:17:20.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:20.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:20.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:20.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:20.99#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:17:20.99#ibcon#first serial, iclass 19, count 2 2006.161.08:17:20.99#ibcon#enter sib2, iclass 19, count 2 2006.161.08:17:20.99#ibcon#flushed, iclass 19, count 2 2006.161.08:17:20.99#ibcon#about to write, iclass 19, count 2 2006.161.08:17:20.99#ibcon#wrote, iclass 19, count 2 2006.161.08:17:20.99#ibcon#about to read 3, iclass 19, count 2 2006.161.08:17:21.01#ibcon#read 3, iclass 19, count 2 2006.161.08:17:21.01#ibcon#about to read 4, iclass 19, count 2 2006.161.08:17:21.01#ibcon#read 4, iclass 19, count 2 2006.161.08:17:21.01#ibcon#about to read 5, iclass 19, count 2 2006.161.08:17:21.01#ibcon#read 5, iclass 19, count 2 2006.161.08:17:21.01#ibcon#about to read 6, iclass 19, count 2 2006.161.08:17:21.01#ibcon#read 6, iclass 19, count 2 2006.161.08:17:21.01#ibcon#end of sib2, iclass 19, count 2 2006.161.08:17:21.01#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:17:21.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:17:21.01#ibcon#[25=AT05-07\r\n] 2006.161.08:17:21.01#ibcon#*before write, iclass 19, count 2 2006.161.08:17:21.01#ibcon#enter sib2, iclass 19, count 2 2006.161.08:17:21.01#ibcon#flushed, iclass 19, count 2 2006.161.08:17:21.01#ibcon#about to write, iclass 19, count 2 2006.161.08:17:21.01#ibcon#wrote, iclass 19, count 2 2006.161.08:17:21.01#ibcon#about to read 3, iclass 19, count 2 2006.161.08:17:21.04#ibcon#read 3, iclass 19, count 2 2006.161.08:17:21.04#ibcon#about to read 4, iclass 19, count 2 2006.161.08:17:21.04#ibcon#read 4, iclass 19, count 2 2006.161.08:17:21.04#ibcon#about to read 5, iclass 19, count 2 2006.161.08:17:21.04#ibcon#read 5, iclass 19, count 2 2006.161.08:17:21.04#ibcon#about to read 6, iclass 19, count 2 2006.161.08:17:21.04#ibcon#read 6, iclass 19, count 2 2006.161.08:17:21.04#ibcon#end of sib2, iclass 19, count 2 2006.161.08:17:21.04#ibcon#*after write, iclass 19, count 2 2006.161.08:17:21.04#ibcon#*before return 0, iclass 19, count 2 2006.161.08:17:21.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:21.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:21.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:17:21.04#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:21.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:21.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:21.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:21.16#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:17:21.16#ibcon#first serial, iclass 19, count 0 2006.161.08:17:21.16#ibcon#enter sib2, iclass 19, count 0 2006.161.08:17:21.16#ibcon#flushed, iclass 19, count 0 2006.161.08:17:21.16#ibcon#about to write, iclass 19, count 0 2006.161.08:17:21.16#ibcon#wrote, iclass 19, count 0 2006.161.08:17:21.16#ibcon#about to read 3, iclass 19, count 0 2006.161.08:17:21.18#ibcon#read 3, iclass 19, count 0 2006.161.08:17:21.18#ibcon#about to read 4, iclass 19, count 0 2006.161.08:17:21.18#ibcon#read 4, iclass 19, count 0 2006.161.08:17:21.18#ibcon#about to read 5, iclass 19, count 0 2006.161.08:17:21.18#ibcon#read 5, iclass 19, count 0 2006.161.08:17:21.18#ibcon#about to read 6, iclass 19, count 0 2006.161.08:17:21.18#ibcon#read 6, iclass 19, count 0 2006.161.08:17:21.18#ibcon#end of sib2, iclass 19, count 0 2006.161.08:17:21.18#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:17:21.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:17:21.18#ibcon#[25=USB\r\n] 2006.161.08:17:21.18#ibcon#*before write, iclass 19, count 0 2006.161.08:17:21.18#ibcon#enter sib2, iclass 19, count 0 2006.161.08:17:21.18#ibcon#flushed, iclass 19, count 0 2006.161.08:17:21.18#ibcon#about to write, iclass 19, count 0 2006.161.08:17:21.18#ibcon#wrote, iclass 19, count 0 2006.161.08:17:21.18#ibcon#about to read 3, iclass 19, count 0 2006.161.08:17:21.21#ibcon#read 3, iclass 19, count 0 2006.161.08:17:21.21#ibcon#about to read 4, iclass 19, count 0 2006.161.08:17:21.21#ibcon#read 4, iclass 19, count 0 2006.161.08:17:21.21#ibcon#about to read 5, iclass 19, count 0 2006.161.08:17:21.21#ibcon#read 5, iclass 19, count 0 2006.161.08:17:21.21#ibcon#about to read 6, iclass 19, count 0 2006.161.08:17:21.21#ibcon#read 6, iclass 19, count 0 2006.161.08:17:21.21#ibcon#end of sib2, iclass 19, count 0 2006.161.08:17:21.21#ibcon#*after write, iclass 19, count 0 2006.161.08:17:21.21#ibcon#*before return 0, iclass 19, count 0 2006.161.08:17:21.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:21.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:21.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:17:21.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:17:21.21$vc4f8/valo=6,772.99 2006.161.08:17:21.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:17:21.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:17:21.21#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:21.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:21.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:21.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:21.21#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:17:21.21#ibcon#first serial, iclass 21, count 0 2006.161.08:17:21.21#ibcon#enter sib2, iclass 21, count 0 2006.161.08:17:21.21#ibcon#flushed, iclass 21, count 0 2006.161.08:17:21.21#ibcon#about to write, iclass 21, count 0 2006.161.08:17:21.21#ibcon#wrote, iclass 21, count 0 2006.161.08:17:21.21#ibcon#about to read 3, iclass 21, count 0 2006.161.08:17:21.23#ibcon#read 3, iclass 21, count 0 2006.161.08:17:21.23#ibcon#about to read 4, iclass 21, count 0 2006.161.08:17:21.23#ibcon#read 4, iclass 21, count 0 2006.161.08:17:21.23#ibcon#about to read 5, iclass 21, count 0 2006.161.08:17:21.23#ibcon#read 5, iclass 21, count 0 2006.161.08:17:21.23#ibcon#about to read 6, iclass 21, count 0 2006.161.08:17:21.23#ibcon#read 6, iclass 21, count 0 2006.161.08:17:21.23#ibcon#end of sib2, iclass 21, count 0 2006.161.08:17:21.23#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:17:21.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:17:21.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:17:21.23#ibcon#*before write, iclass 21, count 0 2006.161.08:17:21.23#ibcon#enter sib2, iclass 21, count 0 2006.161.08:17:21.23#ibcon#flushed, iclass 21, count 0 2006.161.08:17:21.23#ibcon#about to write, iclass 21, count 0 2006.161.08:17:21.23#ibcon#wrote, iclass 21, count 0 2006.161.08:17:21.23#ibcon#about to read 3, iclass 21, count 0 2006.161.08:17:21.27#ibcon#read 3, iclass 21, count 0 2006.161.08:17:21.27#ibcon#about to read 4, iclass 21, count 0 2006.161.08:17:21.27#ibcon#read 4, iclass 21, count 0 2006.161.08:17:21.27#ibcon#about to read 5, iclass 21, count 0 2006.161.08:17:21.27#ibcon#read 5, iclass 21, count 0 2006.161.08:17:21.27#ibcon#about to read 6, iclass 21, count 0 2006.161.08:17:21.27#ibcon#read 6, iclass 21, count 0 2006.161.08:17:21.27#ibcon#end of sib2, iclass 21, count 0 2006.161.08:17:21.27#ibcon#*after write, iclass 21, count 0 2006.161.08:17:21.27#ibcon#*before return 0, iclass 21, count 0 2006.161.08:17:21.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:21.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:21.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:17:21.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:17:21.27$vc4f8/va=6,6 2006.161.08:17:21.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:17:21.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:17:21.27#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:21.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:21.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:21.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:21.33#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:17:21.33#ibcon#first serial, iclass 23, count 2 2006.161.08:17:21.33#ibcon#enter sib2, iclass 23, count 2 2006.161.08:17:21.33#ibcon#flushed, iclass 23, count 2 2006.161.08:17:21.33#ibcon#about to write, iclass 23, count 2 2006.161.08:17:21.33#ibcon#wrote, iclass 23, count 2 2006.161.08:17:21.33#ibcon#about to read 3, iclass 23, count 2 2006.161.08:17:21.35#ibcon#read 3, iclass 23, count 2 2006.161.08:17:21.35#ibcon#about to read 4, iclass 23, count 2 2006.161.08:17:21.35#ibcon#read 4, iclass 23, count 2 2006.161.08:17:21.35#ibcon#about to read 5, iclass 23, count 2 2006.161.08:17:21.35#ibcon#read 5, iclass 23, count 2 2006.161.08:17:21.35#ibcon#about to read 6, iclass 23, count 2 2006.161.08:17:21.35#ibcon#read 6, iclass 23, count 2 2006.161.08:17:21.35#ibcon#end of sib2, iclass 23, count 2 2006.161.08:17:21.35#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:17:21.35#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:17:21.35#ibcon#[25=AT06-06\r\n] 2006.161.08:17:21.35#ibcon#*before write, iclass 23, count 2 2006.161.08:17:21.35#ibcon#enter sib2, iclass 23, count 2 2006.161.08:17:21.35#ibcon#flushed, iclass 23, count 2 2006.161.08:17:21.35#ibcon#about to write, iclass 23, count 2 2006.161.08:17:21.35#ibcon#wrote, iclass 23, count 2 2006.161.08:17:21.35#ibcon#about to read 3, iclass 23, count 2 2006.161.08:17:21.38#ibcon#read 3, iclass 23, count 2 2006.161.08:17:21.38#ibcon#about to read 4, iclass 23, count 2 2006.161.08:17:21.38#ibcon#read 4, iclass 23, count 2 2006.161.08:17:21.38#ibcon#about to read 5, iclass 23, count 2 2006.161.08:17:21.38#ibcon#read 5, iclass 23, count 2 2006.161.08:17:21.38#ibcon#about to read 6, iclass 23, count 2 2006.161.08:17:21.38#ibcon#read 6, iclass 23, count 2 2006.161.08:17:21.38#ibcon#end of sib2, iclass 23, count 2 2006.161.08:17:21.38#ibcon#*after write, iclass 23, count 2 2006.161.08:17:21.38#ibcon#*before return 0, iclass 23, count 2 2006.161.08:17:21.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:21.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:21.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:17:21.38#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:21.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:17:21.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:17:21.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:17:21.50#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:17:21.50#ibcon#first serial, iclass 23, count 0 2006.161.08:17:21.50#ibcon#enter sib2, iclass 23, count 0 2006.161.08:17:21.50#ibcon#flushed, iclass 23, count 0 2006.161.08:17:21.50#ibcon#about to write, iclass 23, count 0 2006.161.08:17:21.50#ibcon#wrote, iclass 23, count 0 2006.161.08:17:21.50#ibcon#about to read 3, iclass 23, count 0 2006.161.08:17:21.52#ibcon#read 3, iclass 23, count 0 2006.161.08:17:21.52#ibcon#about to read 4, iclass 23, count 0 2006.161.08:17:21.52#ibcon#read 4, iclass 23, count 0 2006.161.08:17:21.52#ibcon#about to read 5, iclass 23, count 0 2006.161.08:17:21.52#ibcon#read 5, iclass 23, count 0 2006.161.08:17:21.52#ibcon#about to read 6, iclass 23, count 0 2006.161.08:17:21.52#ibcon#read 6, iclass 23, count 0 2006.161.08:17:21.52#ibcon#end of sib2, iclass 23, count 0 2006.161.08:17:21.52#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:17:21.52#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:17:21.52#ibcon#[25=USB\r\n] 2006.161.08:17:21.52#ibcon#*before write, iclass 23, count 0 2006.161.08:17:21.52#ibcon#enter sib2, iclass 23, count 0 2006.161.08:17:21.52#ibcon#flushed, iclass 23, count 0 2006.161.08:17:21.52#ibcon#about to write, iclass 23, count 0 2006.161.08:17:21.52#ibcon#wrote, iclass 23, count 0 2006.161.08:17:21.52#ibcon#about to read 3, iclass 23, count 0 2006.161.08:17:21.55#ibcon#read 3, iclass 23, count 0 2006.161.08:17:21.55#ibcon#about to read 4, iclass 23, count 0 2006.161.08:17:21.55#ibcon#read 4, iclass 23, count 0 2006.161.08:17:21.55#ibcon#about to read 5, iclass 23, count 0 2006.161.08:17:21.55#ibcon#read 5, iclass 23, count 0 2006.161.08:17:21.55#ibcon#about to read 6, iclass 23, count 0 2006.161.08:17:21.55#ibcon#read 6, iclass 23, count 0 2006.161.08:17:21.55#ibcon#end of sib2, iclass 23, count 0 2006.161.08:17:21.55#ibcon#*after write, iclass 23, count 0 2006.161.08:17:21.55#ibcon#*before return 0, iclass 23, count 0 2006.161.08:17:21.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:17:21.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:17:21.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:17:21.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:17:21.55$vc4f8/valo=7,832.99 2006.161.08:17:21.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:17:21.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:17:21.55#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:21.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:17:21.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:17:21.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:17:21.55#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:17:21.55#ibcon#first serial, iclass 25, count 0 2006.161.08:17:21.55#ibcon#enter sib2, iclass 25, count 0 2006.161.08:17:21.55#ibcon#flushed, iclass 25, count 0 2006.161.08:17:21.55#ibcon#about to write, iclass 25, count 0 2006.161.08:17:21.55#ibcon#wrote, iclass 25, count 0 2006.161.08:17:21.55#ibcon#about to read 3, iclass 25, count 0 2006.161.08:17:21.57#ibcon#read 3, iclass 25, count 0 2006.161.08:17:21.57#ibcon#about to read 4, iclass 25, count 0 2006.161.08:17:21.57#ibcon#read 4, iclass 25, count 0 2006.161.08:17:21.57#ibcon#about to read 5, iclass 25, count 0 2006.161.08:17:21.57#ibcon#read 5, iclass 25, count 0 2006.161.08:17:21.57#ibcon#about to read 6, iclass 25, count 0 2006.161.08:17:21.57#ibcon#read 6, iclass 25, count 0 2006.161.08:17:21.57#ibcon#end of sib2, iclass 25, count 0 2006.161.08:17:21.57#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:17:21.57#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:17:21.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:17:21.57#ibcon#*before write, iclass 25, count 0 2006.161.08:17:21.57#ibcon#enter sib2, iclass 25, count 0 2006.161.08:17:21.57#ibcon#flushed, iclass 25, count 0 2006.161.08:17:21.57#ibcon#about to write, iclass 25, count 0 2006.161.08:17:21.57#ibcon#wrote, iclass 25, count 0 2006.161.08:17:21.57#ibcon#about to read 3, iclass 25, count 0 2006.161.08:17:21.61#ibcon#read 3, iclass 25, count 0 2006.161.08:17:21.61#ibcon#about to read 4, iclass 25, count 0 2006.161.08:17:21.61#ibcon#read 4, iclass 25, count 0 2006.161.08:17:21.61#ibcon#about to read 5, iclass 25, count 0 2006.161.08:17:21.61#ibcon#read 5, iclass 25, count 0 2006.161.08:17:21.61#ibcon#about to read 6, iclass 25, count 0 2006.161.08:17:21.61#ibcon#read 6, iclass 25, count 0 2006.161.08:17:21.61#ibcon#end of sib2, iclass 25, count 0 2006.161.08:17:21.61#ibcon#*after write, iclass 25, count 0 2006.161.08:17:21.61#ibcon#*before return 0, iclass 25, count 0 2006.161.08:17:21.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:17:21.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:17:21.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:17:21.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:17:21.61$vc4f8/va=7,6 2006.161.08:17:21.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:17:21.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:17:21.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:21.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:17:21.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:17:21.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:17:21.67#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:17:21.67#ibcon#first serial, iclass 27, count 2 2006.161.08:17:21.67#ibcon#enter sib2, iclass 27, count 2 2006.161.08:17:21.67#ibcon#flushed, iclass 27, count 2 2006.161.08:17:21.67#ibcon#about to write, iclass 27, count 2 2006.161.08:17:21.67#ibcon#wrote, iclass 27, count 2 2006.161.08:17:21.67#ibcon#about to read 3, iclass 27, count 2 2006.161.08:17:21.69#ibcon#read 3, iclass 27, count 2 2006.161.08:17:21.69#ibcon#about to read 4, iclass 27, count 2 2006.161.08:17:21.69#ibcon#read 4, iclass 27, count 2 2006.161.08:17:21.69#ibcon#about to read 5, iclass 27, count 2 2006.161.08:17:21.69#ibcon#read 5, iclass 27, count 2 2006.161.08:17:21.69#ibcon#about to read 6, iclass 27, count 2 2006.161.08:17:21.69#ibcon#read 6, iclass 27, count 2 2006.161.08:17:21.69#ibcon#end of sib2, iclass 27, count 2 2006.161.08:17:21.69#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:17:21.69#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:17:21.69#ibcon#[25=AT07-06\r\n] 2006.161.08:17:21.69#ibcon#*before write, iclass 27, count 2 2006.161.08:17:21.69#ibcon#enter sib2, iclass 27, count 2 2006.161.08:17:21.69#ibcon#flushed, iclass 27, count 2 2006.161.08:17:21.69#ibcon#about to write, iclass 27, count 2 2006.161.08:17:21.69#ibcon#wrote, iclass 27, count 2 2006.161.08:17:21.69#ibcon#about to read 3, iclass 27, count 2 2006.161.08:17:21.72#ibcon#read 3, iclass 27, count 2 2006.161.08:17:21.72#ibcon#about to read 4, iclass 27, count 2 2006.161.08:17:21.72#ibcon#read 4, iclass 27, count 2 2006.161.08:17:21.72#ibcon#about to read 5, iclass 27, count 2 2006.161.08:17:21.72#ibcon#read 5, iclass 27, count 2 2006.161.08:17:21.72#ibcon#about to read 6, iclass 27, count 2 2006.161.08:17:21.72#ibcon#read 6, iclass 27, count 2 2006.161.08:17:21.72#ibcon#end of sib2, iclass 27, count 2 2006.161.08:17:21.72#ibcon#*after write, iclass 27, count 2 2006.161.08:17:21.72#ibcon#*before return 0, iclass 27, count 2 2006.161.08:17:21.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:17:21.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:17:21.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:17:21.72#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:21.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:17:21.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:17:21.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:17:21.84#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:17:21.84#ibcon#first serial, iclass 27, count 0 2006.161.08:17:21.84#ibcon#enter sib2, iclass 27, count 0 2006.161.08:17:21.84#ibcon#flushed, iclass 27, count 0 2006.161.08:17:21.84#ibcon#about to write, iclass 27, count 0 2006.161.08:17:21.84#ibcon#wrote, iclass 27, count 0 2006.161.08:17:21.84#ibcon#about to read 3, iclass 27, count 0 2006.161.08:17:21.86#ibcon#read 3, iclass 27, count 0 2006.161.08:17:21.86#ibcon#about to read 4, iclass 27, count 0 2006.161.08:17:21.86#ibcon#read 4, iclass 27, count 0 2006.161.08:17:21.86#ibcon#about to read 5, iclass 27, count 0 2006.161.08:17:21.86#ibcon#read 5, iclass 27, count 0 2006.161.08:17:21.86#ibcon#about to read 6, iclass 27, count 0 2006.161.08:17:21.86#ibcon#read 6, iclass 27, count 0 2006.161.08:17:21.86#ibcon#end of sib2, iclass 27, count 0 2006.161.08:17:21.86#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:17:21.86#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:17:21.86#ibcon#[25=USB\r\n] 2006.161.08:17:21.86#ibcon#*before write, iclass 27, count 0 2006.161.08:17:21.86#ibcon#enter sib2, iclass 27, count 0 2006.161.08:17:21.86#ibcon#flushed, iclass 27, count 0 2006.161.08:17:21.86#ibcon#about to write, iclass 27, count 0 2006.161.08:17:21.86#ibcon#wrote, iclass 27, count 0 2006.161.08:17:21.86#ibcon#about to read 3, iclass 27, count 0 2006.161.08:17:21.89#ibcon#read 3, iclass 27, count 0 2006.161.08:17:21.89#ibcon#about to read 4, iclass 27, count 0 2006.161.08:17:21.89#ibcon#read 4, iclass 27, count 0 2006.161.08:17:21.89#ibcon#about to read 5, iclass 27, count 0 2006.161.08:17:21.89#ibcon#read 5, iclass 27, count 0 2006.161.08:17:21.89#ibcon#about to read 6, iclass 27, count 0 2006.161.08:17:21.89#ibcon#read 6, iclass 27, count 0 2006.161.08:17:21.89#ibcon#end of sib2, iclass 27, count 0 2006.161.08:17:21.89#ibcon#*after write, iclass 27, count 0 2006.161.08:17:21.89#ibcon#*before return 0, iclass 27, count 0 2006.161.08:17:21.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:17:21.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:17:21.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:17:21.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:17:21.89$vc4f8/valo=8,852.99 2006.161.08:17:21.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:17:21.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:17:21.89#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:21.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:17:21.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:17:21.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:17:21.89#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:17:21.89#ibcon#first serial, iclass 29, count 0 2006.161.08:17:21.89#ibcon#enter sib2, iclass 29, count 0 2006.161.08:17:21.89#ibcon#flushed, iclass 29, count 0 2006.161.08:17:21.89#ibcon#about to write, iclass 29, count 0 2006.161.08:17:21.89#ibcon#wrote, iclass 29, count 0 2006.161.08:17:21.89#ibcon#about to read 3, iclass 29, count 0 2006.161.08:17:21.91#ibcon#read 3, iclass 29, count 0 2006.161.08:17:21.91#ibcon#about to read 4, iclass 29, count 0 2006.161.08:17:21.91#ibcon#read 4, iclass 29, count 0 2006.161.08:17:21.91#ibcon#about to read 5, iclass 29, count 0 2006.161.08:17:21.91#ibcon#read 5, iclass 29, count 0 2006.161.08:17:21.91#ibcon#about to read 6, iclass 29, count 0 2006.161.08:17:21.91#ibcon#read 6, iclass 29, count 0 2006.161.08:17:21.91#ibcon#end of sib2, iclass 29, count 0 2006.161.08:17:21.91#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:17:21.91#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:17:21.91#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:17:21.91#ibcon#*before write, iclass 29, count 0 2006.161.08:17:21.91#ibcon#enter sib2, iclass 29, count 0 2006.161.08:17:21.91#ibcon#flushed, iclass 29, count 0 2006.161.08:17:21.91#ibcon#about to write, iclass 29, count 0 2006.161.08:17:21.91#ibcon#wrote, iclass 29, count 0 2006.161.08:17:21.91#ibcon#about to read 3, iclass 29, count 0 2006.161.08:17:21.95#ibcon#read 3, iclass 29, count 0 2006.161.08:17:21.95#ibcon#about to read 4, iclass 29, count 0 2006.161.08:17:21.95#ibcon#read 4, iclass 29, count 0 2006.161.08:17:21.95#ibcon#about to read 5, iclass 29, count 0 2006.161.08:17:21.95#ibcon#read 5, iclass 29, count 0 2006.161.08:17:21.95#ibcon#about to read 6, iclass 29, count 0 2006.161.08:17:21.95#ibcon#read 6, iclass 29, count 0 2006.161.08:17:21.95#ibcon#end of sib2, iclass 29, count 0 2006.161.08:17:21.95#ibcon#*after write, iclass 29, count 0 2006.161.08:17:21.95#ibcon#*before return 0, iclass 29, count 0 2006.161.08:17:21.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:17:21.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:17:21.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:17:21.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:17:21.95$vc4f8/va=8,7 2006.161.08:17:21.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.08:17:21.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.08:17:21.95#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:21.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:17:22.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:17:22.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:17:22.01#ibcon#enter wrdev, iclass 31, count 2 2006.161.08:17:22.01#ibcon#first serial, iclass 31, count 2 2006.161.08:17:22.01#ibcon#enter sib2, iclass 31, count 2 2006.161.08:17:22.01#ibcon#flushed, iclass 31, count 2 2006.161.08:17:22.01#ibcon#about to write, iclass 31, count 2 2006.161.08:17:22.01#ibcon#wrote, iclass 31, count 2 2006.161.08:17:22.01#ibcon#about to read 3, iclass 31, count 2 2006.161.08:17:22.03#ibcon#read 3, iclass 31, count 2 2006.161.08:17:22.03#ibcon#about to read 4, iclass 31, count 2 2006.161.08:17:22.03#ibcon#read 4, iclass 31, count 2 2006.161.08:17:22.03#ibcon#about to read 5, iclass 31, count 2 2006.161.08:17:22.03#ibcon#read 5, iclass 31, count 2 2006.161.08:17:22.03#ibcon#about to read 6, iclass 31, count 2 2006.161.08:17:22.03#ibcon#read 6, iclass 31, count 2 2006.161.08:17:22.03#ibcon#end of sib2, iclass 31, count 2 2006.161.08:17:22.03#ibcon#*mode == 0, iclass 31, count 2 2006.161.08:17:22.03#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.08:17:22.03#ibcon#[25=AT08-07\r\n] 2006.161.08:17:22.03#ibcon#*before write, iclass 31, count 2 2006.161.08:17:22.03#ibcon#enter sib2, iclass 31, count 2 2006.161.08:17:22.03#ibcon#flushed, iclass 31, count 2 2006.161.08:17:22.03#ibcon#about to write, iclass 31, count 2 2006.161.08:17:22.03#ibcon#wrote, iclass 31, count 2 2006.161.08:17:22.03#ibcon#about to read 3, iclass 31, count 2 2006.161.08:17:22.06#ibcon#read 3, iclass 31, count 2 2006.161.08:17:22.06#ibcon#about to read 4, iclass 31, count 2 2006.161.08:17:22.06#ibcon#read 4, iclass 31, count 2 2006.161.08:17:22.06#ibcon#about to read 5, iclass 31, count 2 2006.161.08:17:22.06#ibcon#read 5, iclass 31, count 2 2006.161.08:17:22.06#ibcon#about to read 6, iclass 31, count 2 2006.161.08:17:22.06#ibcon#read 6, iclass 31, count 2 2006.161.08:17:22.06#ibcon#end of sib2, iclass 31, count 2 2006.161.08:17:22.06#ibcon#*after write, iclass 31, count 2 2006.161.08:17:22.06#ibcon#*before return 0, iclass 31, count 2 2006.161.08:17:22.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:17:22.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:17:22.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.08:17:22.06#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:22.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:17:22.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:17:22.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:17:22.18#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:17:22.18#ibcon#first serial, iclass 31, count 0 2006.161.08:17:22.18#ibcon#enter sib2, iclass 31, count 0 2006.161.08:17:22.18#ibcon#flushed, iclass 31, count 0 2006.161.08:17:22.18#ibcon#about to write, iclass 31, count 0 2006.161.08:17:22.18#ibcon#wrote, iclass 31, count 0 2006.161.08:17:22.18#ibcon#about to read 3, iclass 31, count 0 2006.161.08:17:22.20#ibcon#read 3, iclass 31, count 0 2006.161.08:17:22.20#ibcon#about to read 4, iclass 31, count 0 2006.161.08:17:22.20#ibcon#read 4, iclass 31, count 0 2006.161.08:17:22.20#ibcon#about to read 5, iclass 31, count 0 2006.161.08:17:22.20#ibcon#read 5, iclass 31, count 0 2006.161.08:17:22.20#ibcon#about to read 6, iclass 31, count 0 2006.161.08:17:22.20#ibcon#read 6, iclass 31, count 0 2006.161.08:17:22.20#ibcon#end of sib2, iclass 31, count 0 2006.161.08:17:22.20#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:17:22.20#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:17:22.20#ibcon#[25=USB\r\n] 2006.161.08:17:22.20#ibcon#*before write, iclass 31, count 0 2006.161.08:17:22.20#ibcon#enter sib2, iclass 31, count 0 2006.161.08:17:22.20#ibcon#flushed, iclass 31, count 0 2006.161.08:17:22.20#ibcon#about to write, iclass 31, count 0 2006.161.08:17:22.20#ibcon#wrote, iclass 31, count 0 2006.161.08:17:22.20#ibcon#about to read 3, iclass 31, count 0 2006.161.08:17:22.23#ibcon#read 3, iclass 31, count 0 2006.161.08:17:22.23#ibcon#about to read 4, iclass 31, count 0 2006.161.08:17:22.23#ibcon#read 4, iclass 31, count 0 2006.161.08:17:22.23#ibcon#about to read 5, iclass 31, count 0 2006.161.08:17:22.23#ibcon#read 5, iclass 31, count 0 2006.161.08:17:22.23#ibcon#about to read 6, iclass 31, count 0 2006.161.08:17:22.23#ibcon#read 6, iclass 31, count 0 2006.161.08:17:22.23#ibcon#end of sib2, iclass 31, count 0 2006.161.08:17:22.23#ibcon#*after write, iclass 31, count 0 2006.161.08:17:22.23#ibcon#*before return 0, iclass 31, count 0 2006.161.08:17:22.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:17:22.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:17:22.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:17:22.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:17:22.23$vc4f8/vblo=1,632.99 2006.161.08:17:22.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.08:17:22.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.08:17:22.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:22.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:17:22.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:17:22.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:17:22.23#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:17:22.23#ibcon#first serial, iclass 33, count 0 2006.161.08:17:22.23#ibcon#enter sib2, iclass 33, count 0 2006.161.08:17:22.23#ibcon#flushed, iclass 33, count 0 2006.161.08:17:22.23#ibcon#about to write, iclass 33, count 0 2006.161.08:17:22.23#ibcon#wrote, iclass 33, count 0 2006.161.08:17:22.23#ibcon#about to read 3, iclass 33, count 0 2006.161.08:17:22.25#ibcon#read 3, iclass 33, count 0 2006.161.08:17:22.25#ibcon#about to read 4, iclass 33, count 0 2006.161.08:17:22.25#ibcon#read 4, iclass 33, count 0 2006.161.08:17:22.25#ibcon#about to read 5, iclass 33, count 0 2006.161.08:17:22.25#ibcon#read 5, iclass 33, count 0 2006.161.08:17:22.25#ibcon#about to read 6, iclass 33, count 0 2006.161.08:17:22.25#ibcon#read 6, iclass 33, count 0 2006.161.08:17:22.25#ibcon#end of sib2, iclass 33, count 0 2006.161.08:17:22.25#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:17:22.25#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:17:22.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:17:22.25#ibcon#*before write, iclass 33, count 0 2006.161.08:17:22.25#ibcon#enter sib2, iclass 33, count 0 2006.161.08:17:22.25#ibcon#flushed, iclass 33, count 0 2006.161.08:17:22.25#ibcon#about to write, iclass 33, count 0 2006.161.08:17:22.25#ibcon#wrote, iclass 33, count 0 2006.161.08:17:22.25#ibcon#about to read 3, iclass 33, count 0 2006.161.08:17:22.29#ibcon#read 3, iclass 33, count 0 2006.161.08:17:22.29#ibcon#about to read 4, iclass 33, count 0 2006.161.08:17:22.29#ibcon#read 4, iclass 33, count 0 2006.161.08:17:22.29#ibcon#about to read 5, iclass 33, count 0 2006.161.08:17:22.29#ibcon#read 5, iclass 33, count 0 2006.161.08:17:22.29#ibcon#about to read 6, iclass 33, count 0 2006.161.08:17:22.29#ibcon#read 6, iclass 33, count 0 2006.161.08:17:22.29#ibcon#end of sib2, iclass 33, count 0 2006.161.08:17:22.29#ibcon#*after write, iclass 33, count 0 2006.161.08:17:22.29#ibcon#*before return 0, iclass 33, count 0 2006.161.08:17:22.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:17:22.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:17:22.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:17:22.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:17:22.29$vc4f8/vb=1,4 2006.161.08:17:22.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.08:17:22.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.08:17:22.29#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:22.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:17:22.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:17:22.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:17:22.29#ibcon#enter wrdev, iclass 35, count 2 2006.161.08:17:22.29#ibcon#first serial, iclass 35, count 2 2006.161.08:17:22.29#ibcon#enter sib2, iclass 35, count 2 2006.161.08:17:22.29#ibcon#flushed, iclass 35, count 2 2006.161.08:17:22.29#ibcon#about to write, iclass 35, count 2 2006.161.08:17:22.29#ibcon#wrote, iclass 35, count 2 2006.161.08:17:22.29#ibcon#about to read 3, iclass 35, count 2 2006.161.08:17:22.31#ibcon#read 3, iclass 35, count 2 2006.161.08:17:22.31#ibcon#about to read 4, iclass 35, count 2 2006.161.08:17:22.31#ibcon#read 4, iclass 35, count 2 2006.161.08:17:22.31#ibcon#about to read 5, iclass 35, count 2 2006.161.08:17:22.31#ibcon#read 5, iclass 35, count 2 2006.161.08:17:22.31#ibcon#about to read 6, iclass 35, count 2 2006.161.08:17:22.31#ibcon#read 6, iclass 35, count 2 2006.161.08:17:22.31#ibcon#end of sib2, iclass 35, count 2 2006.161.08:17:22.31#ibcon#*mode == 0, iclass 35, count 2 2006.161.08:17:22.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.08:17:22.31#ibcon#[27=AT01-04\r\n] 2006.161.08:17:22.31#ibcon#*before write, iclass 35, count 2 2006.161.08:17:22.31#ibcon#enter sib2, iclass 35, count 2 2006.161.08:17:22.31#ibcon#flushed, iclass 35, count 2 2006.161.08:17:22.31#ibcon#about to write, iclass 35, count 2 2006.161.08:17:22.31#ibcon#wrote, iclass 35, count 2 2006.161.08:17:22.31#ibcon#about to read 3, iclass 35, count 2 2006.161.08:17:22.34#ibcon#read 3, iclass 35, count 2 2006.161.08:17:22.34#ibcon#about to read 4, iclass 35, count 2 2006.161.08:17:22.34#ibcon#read 4, iclass 35, count 2 2006.161.08:17:22.34#ibcon#about to read 5, iclass 35, count 2 2006.161.08:17:22.34#ibcon#read 5, iclass 35, count 2 2006.161.08:17:22.34#ibcon#about to read 6, iclass 35, count 2 2006.161.08:17:22.34#ibcon#read 6, iclass 35, count 2 2006.161.08:17:22.34#ibcon#end of sib2, iclass 35, count 2 2006.161.08:17:22.34#ibcon#*after write, iclass 35, count 2 2006.161.08:17:22.34#ibcon#*before return 0, iclass 35, count 2 2006.161.08:17:22.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:17:22.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:17:22.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.08:17:22.34#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:22.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:17:22.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:17:22.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:17:22.46#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:17:22.46#ibcon#first serial, iclass 35, count 0 2006.161.08:17:22.46#ibcon#enter sib2, iclass 35, count 0 2006.161.08:17:22.46#ibcon#flushed, iclass 35, count 0 2006.161.08:17:22.46#ibcon#about to write, iclass 35, count 0 2006.161.08:17:22.46#ibcon#wrote, iclass 35, count 0 2006.161.08:17:22.46#ibcon#about to read 3, iclass 35, count 0 2006.161.08:17:22.48#ibcon#read 3, iclass 35, count 0 2006.161.08:17:22.48#ibcon#about to read 4, iclass 35, count 0 2006.161.08:17:22.48#ibcon#read 4, iclass 35, count 0 2006.161.08:17:22.48#ibcon#about to read 5, iclass 35, count 0 2006.161.08:17:22.48#ibcon#read 5, iclass 35, count 0 2006.161.08:17:22.48#ibcon#about to read 6, iclass 35, count 0 2006.161.08:17:22.48#ibcon#read 6, iclass 35, count 0 2006.161.08:17:22.48#ibcon#end of sib2, iclass 35, count 0 2006.161.08:17:22.48#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:17:22.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:17:22.48#ibcon#[27=USB\r\n] 2006.161.08:17:22.48#ibcon#*before write, iclass 35, count 0 2006.161.08:17:22.48#ibcon#enter sib2, iclass 35, count 0 2006.161.08:17:22.48#ibcon#flushed, iclass 35, count 0 2006.161.08:17:22.48#ibcon#about to write, iclass 35, count 0 2006.161.08:17:22.48#ibcon#wrote, iclass 35, count 0 2006.161.08:17:22.48#ibcon#about to read 3, iclass 35, count 0 2006.161.08:17:22.51#ibcon#read 3, iclass 35, count 0 2006.161.08:17:22.51#ibcon#about to read 4, iclass 35, count 0 2006.161.08:17:22.51#ibcon#read 4, iclass 35, count 0 2006.161.08:17:22.51#ibcon#about to read 5, iclass 35, count 0 2006.161.08:17:22.51#ibcon#read 5, iclass 35, count 0 2006.161.08:17:22.51#ibcon#about to read 6, iclass 35, count 0 2006.161.08:17:22.51#ibcon#read 6, iclass 35, count 0 2006.161.08:17:22.51#ibcon#end of sib2, iclass 35, count 0 2006.161.08:17:22.51#ibcon#*after write, iclass 35, count 0 2006.161.08:17:22.51#ibcon#*before return 0, iclass 35, count 0 2006.161.08:17:22.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:17:22.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:17:22.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:17:22.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:17:22.51$vc4f8/vblo=2,640.99 2006.161.08:17:22.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:17:22.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:17:22.51#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:22.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:22.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:22.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:22.51#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:17:22.51#ibcon#first serial, iclass 37, count 0 2006.161.08:17:22.51#ibcon#enter sib2, iclass 37, count 0 2006.161.08:17:22.51#ibcon#flushed, iclass 37, count 0 2006.161.08:17:22.51#ibcon#about to write, iclass 37, count 0 2006.161.08:17:22.51#ibcon#wrote, iclass 37, count 0 2006.161.08:17:22.51#ibcon#about to read 3, iclass 37, count 0 2006.161.08:17:22.53#ibcon#read 3, iclass 37, count 0 2006.161.08:17:22.53#ibcon#about to read 4, iclass 37, count 0 2006.161.08:17:22.53#ibcon#read 4, iclass 37, count 0 2006.161.08:17:22.53#ibcon#about to read 5, iclass 37, count 0 2006.161.08:17:22.53#ibcon#read 5, iclass 37, count 0 2006.161.08:17:22.53#ibcon#about to read 6, iclass 37, count 0 2006.161.08:17:22.53#ibcon#read 6, iclass 37, count 0 2006.161.08:17:22.53#ibcon#end of sib2, iclass 37, count 0 2006.161.08:17:22.53#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:17:22.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:17:22.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:17:22.53#ibcon#*before write, iclass 37, count 0 2006.161.08:17:22.53#ibcon#enter sib2, iclass 37, count 0 2006.161.08:17:22.53#ibcon#flushed, iclass 37, count 0 2006.161.08:17:22.53#ibcon#about to write, iclass 37, count 0 2006.161.08:17:22.53#ibcon#wrote, iclass 37, count 0 2006.161.08:17:22.53#ibcon#about to read 3, iclass 37, count 0 2006.161.08:17:22.57#ibcon#read 3, iclass 37, count 0 2006.161.08:17:22.57#ibcon#about to read 4, iclass 37, count 0 2006.161.08:17:22.57#ibcon#read 4, iclass 37, count 0 2006.161.08:17:22.57#ibcon#about to read 5, iclass 37, count 0 2006.161.08:17:22.57#ibcon#read 5, iclass 37, count 0 2006.161.08:17:22.57#ibcon#about to read 6, iclass 37, count 0 2006.161.08:17:22.57#ibcon#read 6, iclass 37, count 0 2006.161.08:17:22.57#ibcon#end of sib2, iclass 37, count 0 2006.161.08:17:22.57#ibcon#*after write, iclass 37, count 0 2006.161.08:17:22.57#ibcon#*before return 0, iclass 37, count 0 2006.161.08:17:22.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:22.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:17:22.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:17:22.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:17:22.57$vc4f8/vb=2,4 2006.161.08:17:22.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:17:22.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:17:22.57#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:22.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:22.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:22.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:22.63#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:17:22.63#ibcon#first serial, iclass 39, count 2 2006.161.08:17:22.63#ibcon#enter sib2, iclass 39, count 2 2006.161.08:17:22.63#ibcon#flushed, iclass 39, count 2 2006.161.08:17:22.63#ibcon#about to write, iclass 39, count 2 2006.161.08:17:22.63#ibcon#wrote, iclass 39, count 2 2006.161.08:17:22.63#ibcon#about to read 3, iclass 39, count 2 2006.161.08:17:22.65#ibcon#read 3, iclass 39, count 2 2006.161.08:17:22.65#ibcon#about to read 4, iclass 39, count 2 2006.161.08:17:22.65#ibcon#read 4, iclass 39, count 2 2006.161.08:17:22.65#ibcon#about to read 5, iclass 39, count 2 2006.161.08:17:22.65#ibcon#read 5, iclass 39, count 2 2006.161.08:17:22.65#ibcon#about to read 6, iclass 39, count 2 2006.161.08:17:22.65#ibcon#read 6, iclass 39, count 2 2006.161.08:17:22.65#ibcon#end of sib2, iclass 39, count 2 2006.161.08:17:22.65#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:17:22.65#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:17:22.65#ibcon#[27=AT02-04\r\n] 2006.161.08:17:22.65#ibcon#*before write, iclass 39, count 2 2006.161.08:17:22.65#ibcon#enter sib2, iclass 39, count 2 2006.161.08:17:22.65#ibcon#flushed, iclass 39, count 2 2006.161.08:17:22.65#ibcon#about to write, iclass 39, count 2 2006.161.08:17:22.65#ibcon#wrote, iclass 39, count 2 2006.161.08:17:22.65#ibcon#about to read 3, iclass 39, count 2 2006.161.08:17:22.68#ibcon#read 3, iclass 39, count 2 2006.161.08:17:22.68#ibcon#about to read 4, iclass 39, count 2 2006.161.08:17:22.68#ibcon#read 4, iclass 39, count 2 2006.161.08:17:22.68#ibcon#about to read 5, iclass 39, count 2 2006.161.08:17:22.68#ibcon#read 5, iclass 39, count 2 2006.161.08:17:22.68#ibcon#about to read 6, iclass 39, count 2 2006.161.08:17:22.68#ibcon#read 6, iclass 39, count 2 2006.161.08:17:22.68#ibcon#end of sib2, iclass 39, count 2 2006.161.08:17:22.68#ibcon#*after write, iclass 39, count 2 2006.161.08:17:22.68#ibcon#*before return 0, iclass 39, count 2 2006.161.08:17:22.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:22.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:17:22.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:17:22.68#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:22.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:22.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:22.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:22.80#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:17:22.80#ibcon#first serial, iclass 39, count 0 2006.161.08:17:22.80#ibcon#enter sib2, iclass 39, count 0 2006.161.08:17:22.80#ibcon#flushed, iclass 39, count 0 2006.161.08:17:22.80#ibcon#about to write, iclass 39, count 0 2006.161.08:17:22.80#ibcon#wrote, iclass 39, count 0 2006.161.08:17:22.80#ibcon#about to read 3, iclass 39, count 0 2006.161.08:17:22.82#ibcon#read 3, iclass 39, count 0 2006.161.08:17:22.82#ibcon#about to read 4, iclass 39, count 0 2006.161.08:17:22.82#ibcon#read 4, iclass 39, count 0 2006.161.08:17:22.82#ibcon#about to read 5, iclass 39, count 0 2006.161.08:17:22.82#ibcon#read 5, iclass 39, count 0 2006.161.08:17:22.82#ibcon#about to read 6, iclass 39, count 0 2006.161.08:17:22.82#ibcon#read 6, iclass 39, count 0 2006.161.08:17:22.82#ibcon#end of sib2, iclass 39, count 0 2006.161.08:17:22.82#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:17:22.82#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:17:22.82#ibcon#[27=USB\r\n] 2006.161.08:17:22.82#ibcon#*before write, iclass 39, count 0 2006.161.08:17:22.82#ibcon#enter sib2, iclass 39, count 0 2006.161.08:17:22.82#ibcon#flushed, iclass 39, count 0 2006.161.08:17:22.82#ibcon#about to write, iclass 39, count 0 2006.161.08:17:22.82#ibcon#wrote, iclass 39, count 0 2006.161.08:17:22.82#ibcon#about to read 3, iclass 39, count 0 2006.161.08:17:22.85#ibcon#read 3, iclass 39, count 0 2006.161.08:17:22.85#ibcon#about to read 4, iclass 39, count 0 2006.161.08:17:22.85#ibcon#read 4, iclass 39, count 0 2006.161.08:17:22.85#ibcon#about to read 5, iclass 39, count 0 2006.161.08:17:22.85#ibcon#read 5, iclass 39, count 0 2006.161.08:17:22.85#ibcon#about to read 6, iclass 39, count 0 2006.161.08:17:22.85#ibcon#read 6, iclass 39, count 0 2006.161.08:17:22.85#ibcon#end of sib2, iclass 39, count 0 2006.161.08:17:22.85#ibcon#*after write, iclass 39, count 0 2006.161.08:17:22.85#ibcon#*before return 0, iclass 39, count 0 2006.161.08:17:22.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:22.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:17:22.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:17:22.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:17:22.85$vc4f8/vblo=3,656.99 2006.161.08:17:22.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:17:22.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:17:22.85#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:22.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:22.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:22.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:22.85#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:17:22.85#ibcon#first serial, iclass 3, count 0 2006.161.08:17:22.85#ibcon#enter sib2, iclass 3, count 0 2006.161.08:17:22.85#ibcon#flushed, iclass 3, count 0 2006.161.08:17:22.85#ibcon#about to write, iclass 3, count 0 2006.161.08:17:22.85#ibcon#wrote, iclass 3, count 0 2006.161.08:17:22.85#ibcon#about to read 3, iclass 3, count 0 2006.161.08:17:22.88#ibcon#read 3, iclass 3, count 0 2006.161.08:17:22.88#ibcon#about to read 4, iclass 3, count 0 2006.161.08:17:22.88#ibcon#read 4, iclass 3, count 0 2006.161.08:17:22.88#ibcon#about to read 5, iclass 3, count 0 2006.161.08:17:22.88#ibcon#read 5, iclass 3, count 0 2006.161.08:17:22.88#ibcon#about to read 6, iclass 3, count 0 2006.161.08:17:22.88#ibcon#read 6, iclass 3, count 0 2006.161.08:17:22.88#ibcon#end of sib2, iclass 3, count 0 2006.161.08:17:22.88#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:17:22.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:17:22.88#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:17:22.88#ibcon#*before write, iclass 3, count 0 2006.161.08:17:22.88#ibcon#enter sib2, iclass 3, count 0 2006.161.08:17:22.88#ibcon#flushed, iclass 3, count 0 2006.161.08:17:22.88#ibcon#about to write, iclass 3, count 0 2006.161.08:17:22.88#ibcon#wrote, iclass 3, count 0 2006.161.08:17:22.88#ibcon#about to read 3, iclass 3, count 0 2006.161.08:17:22.92#ibcon#read 3, iclass 3, count 0 2006.161.08:17:22.92#ibcon#about to read 4, iclass 3, count 0 2006.161.08:17:22.92#ibcon#read 4, iclass 3, count 0 2006.161.08:17:22.92#ibcon#about to read 5, iclass 3, count 0 2006.161.08:17:22.92#ibcon#read 5, iclass 3, count 0 2006.161.08:17:22.92#ibcon#about to read 6, iclass 3, count 0 2006.161.08:17:22.92#ibcon#read 6, iclass 3, count 0 2006.161.08:17:22.92#ibcon#end of sib2, iclass 3, count 0 2006.161.08:17:22.92#ibcon#*after write, iclass 3, count 0 2006.161.08:17:22.92#ibcon#*before return 0, iclass 3, count 0 2006.161.08:17:22.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:22.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:17:22.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:17:22.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:17:22.92$vc4f8/vb=3,4 2006.161.08:17:22.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:17:22.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:17:22.92#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:22.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:22.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:22.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:22.97#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:17:22.97#ibcon#first serial, iclass 5, count 2 2006.161.08:17:22.97#ibcon#enter sib2, iclass 5, count 2 2006.161.08:17:22.97#ibcon#flushed, iclass 5, count 2 2006.161.08:17:22.97#ibcon#about to write, iclass 5, count 2 2006.161.08:17:22.97#ibcon#wrote, iclass 5, count 2 2006.161.08:17:22.97#ibcon#about to read 3, iclass 5, count 2 2006.161.08:17:22.99#ibcon#read 3, iclass 5, count 2 2006.161.08:17:22.99#ibcon#about to read 4, iclass 5, count 2 2006.161.08:17:22.99#ibcon#read 4, iclass 5, count 2 2006.161.08:17:22.99#ibcon#about to read 5, iclass 5, count 2 2006.161.08:17:22.99#ibcon#read 5, iclass 5, count 2 2006.161.08:17:22.99#ibcon#about to read 6, iclass 5, count 2 2006.161.08:17:22.99#ibcon#read 6, iclass 5, count 2 2006.161.08:17:22.99#ibcon#end of sib2, iclass 5, count 2 2006.161.08:17:22.99#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:17:22.99#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:17:22.99#ibcon#[27=AT03-04\r\n] 2006.161.08:17:22.99#ibcon#*before write, iclass 5, count 2 2006.161.08:17:22.99#ibcon#enter sib2, iclass 5, count 2 2006.161.08:17:22.99#ibcon#flushed, iclass 5, count 2 2006.161.08:17:22.99#ibcon#about to write, iclass 5, count 2 2006.161.08:17:22.99#ibcon#wrote, iclass 5, count 2 2006.161.08:17:22.99#ibcon#about to read 3, iclass 5, count 2 2006.161.08:17:23.02#ibcon#read 3, iclass 5, count 2 2006.161.08:17:23.02#ibcon#about to read 4, iclass 5, count 2 2006.161.08:17:23.02#ibcon#read 4, iclass 5, count 2 2006.161.08:17:23.02#ibcon#about to read 5, iclass 5, count 2 2006.161.08:17:23.02#ibcon#read 5, iclass 5, count 2 2006.161.08:17:23.02#ibcon#about to read 6, iclass 5, count 2 2006.161.08:17:23.02#ibcon#read 6, iclass 5, count 2 2006.161.08:17:23.02#ibcon#end of sib2, iclass 5, count 2 2006.161.08:17:23.02#ibcon#*after write, iclass 5, count 2 2006.161.08:17:23.02#ibcon#*before return 0, iclass 5, count 2 2006.161.08:17:23.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:23.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:17:23.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:17:23.02#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:23.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:23.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:23.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:23.14#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:17:23.14#ibcon#first serial, iclass 5, count 0 2006.161.08:17:23.14#ibcon#enter sib2, iclass 5, count 0 2006.161.08:17:23.14#ibcon#flushed, iclass 5, count 0 2006.161.08:17:23.14#ibcon#about to write, iclass 5, count 0 2006.161.08:17:23.14#ibcon#wrote, iclass 5, count 0 2006.161.08:17:23.14#ibcon#about to read 3, iclass 5, count 0 2006.161.08:17:23.16#ibcon#read 3, iclass 5, count 0 2006.161.08:17:23.16#ibcon#about to read 4, iclass 5, count 0 2006.161.08:17:23.16#ibcon#read 4, iclass 5, count 0 2006.161.08:17:23.16#ibcon#about to read 5, iclass 5, count 0 2006.161.08:17:23.16#ibcon#read 5, iclass 5, count 0 2006.161.08:17:23.16#ibcon#about to read 6, iclass 5, count 0 2006.161.08:17:23.16#ibcon#read 6, iclass 5, count 0 2006.161.08:17:23.16#ibcon#end of sib2, iclass 5, count 0 2006.161.08:17:23.16#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:17:23.16#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:17:23.16#ibcon#[27=USB\r\n] 2006.161.08:17:23.16#ibcon#*before write, iclass 5, count 0 2006.161.08:17:23.16#ibcon#enter sib2, iclass 5, count 0 2006.161.08:17:23.16#ibcon#flushed, iclass 5, count 0 2006.161.08:17:23.16#ibcon#about to write, iclass 5, count 0 2006.161.08:17:23.16#ibcon#wrote, iclass 5, count 0 2006.161.08:17:23.16#ibcon#about to read 3, iclass 5, count 0 2006.161.08:17:23.19#ibcon#read 3, iclass 5, count 0 2006.161.08:17:23.19#ibcon#about to read 4, iclass 5, count 0 2006.161.08:17:23.19#ibcon#read 4, iclass 5, count 0 2006.161.08:17:23.19#ibcon#about to read 5, iclass 5, count 0 2006.161.08:17:23.19#ibcon#read 5, iclass 5, count 0 2006.161.08:17:23.19#ibcon#about to read 6, iclass 5, count 0 2006.161.08:17:23.19#ibcon#read 6, iclass 5, count 0 2006.161.08:17:23.19#ibcon#end of sib2, iclass 5, count 0 2006.161.08:17:23.19#ibcon#*after write, iclass 5, count 0 2006.161.08:17:23.19#ibcon#*before return 0, iclass 5, count 0 2006.161.08:17:23.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:23.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:17:23.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:17:23.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:17:23.19$vc4f8/vblo=4,712.99 2006.161.08:17:23.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:17:23.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:17:23.19#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:23.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:23.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:23.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:23.19#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:17:23.19#ibcon#first serial, iclass 7, count 0 2006.161.08:17:23.19#ibcon#enter sib2, iclass 7, count 0 2006.161.08:17:23.19#ibcon#flushed, iclass 7, count 0 2006.161.08:17:23.19#ibcon#about to write, iclass 7, count 0 2006.161.08:17:23.19#ibcon#wrote, iclass 7, count 0 2006.161.08:17:23.19#ibcon#about to read 3, iclass 7, count 0 2006.161.08:17:23.21#ibcon#read 3, iclass 7, count 0 2006.161.08:17:23.21#ibcon#about to read 4, iclass 7, count 0 2006.161.08:17:23.21#ibcon#read 4, iclass 7, count 0 2006.161.08:17:23.21#ibcon#about to read 5, iclass 7, count 0 2006.161.08:17:23.21#ibcon#read 5, iclass 7, count 0 2006.161.08:17:23.21#ibcon#about to read 6, iclass 7, count 0 2006.161.08:17:23.21#ibcon#read 6, iclass 7, count 0 2006.161.08:17:23.21#ibcon#end of sib2, iclass 7, count 0 2006.161.08:17:23.21#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:17:23.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:17:23.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:17:23.21#ibcon#*before write, iclass 7, count 0 2006.161.08:17:23.21#ibcon#enter sib2, iclass 7, count 0 2006.161.08:17:23.21#ibcon#flushed, iclass 7, count 0 2006.161.08:17:23.21#ibcon#about to write, iclass 7, count 0 2006.161.08:17:23.21#ibcon#wrote, iclass 7, count 0 2006.161.08:17:23.21#ibcon#about to read 3, iclass 7, count 0 2006.161.08:17:23.25#ibcon#read 3, iclass 7, count 0 2006.161.08:17:23.25#ibcon#about to read 4, iclass 7, count 0 2006.161.08:17:23.25#ibcon#read 4, iclass 7, count 0 2006.161.08:17:23.25#ibcon#about to read 5, iclass 7, count 0 2006.161.08:17:23.25#ibcon#read 5, iclass 7, count 0 2006.161.08:17:23.25#ibcon#about to read 6, iclass 7, count 0 2006.161.08:17:23.25#ibcon#read 6, iclass 7, count 0 2006.161.08:17:23.25#ibcon#end of sib2, iclass 7, count 0 2006.161.08:17:23.25#ibcon#*after write, iclass 7, count 0 2006.161.08:17:23.25#ibcon#*before return 0, iclass 7, count 0 2006.161.08:17:23.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:23.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:17:23.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:17:23.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:17:23.25$vc4f8/vb=4,4 2006.161.08:17:23.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:17:23.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:17:23.25#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:23.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:23.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:23.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:23.31#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:17:23.31#ibcon#first serial, iclass 11, count 2 2006.161.08:17:23.31#ibcon#enter sib2, iclass 11, count 2 2006.161.08:17:23.31#ibcon#flushed, iclass 11, count 2 2006.161.08:17:23.31#ibcon#about to write, iclass 11, count 2 2006.161.08:17:23.31#ibcon#wrote, iclass 11, count 2 2006.161.08:17:23.31#ibcon#about to read 3, iclass 11, count 2 2006.161.08:17:23.33#ibcon#read 3, iclass 11, count 2 2006.161.08:17:23.33#ibcon#about to read 4, iclass 11, count 2 2006.161.08:17:23.33#ibcon#read 4, iclass 11, count 2 2006.161.08:17:23.33#ibcon#about to read 5, iclass 11, count 2 2006.161.08:17:23.33#ibcon#read 5, iclass 11, count 2 2006.161.08:17:23.33#ibcon#about to read 6, iclass 11, count 2 2006.161.08:17:23.33#ibcon#read 6, iclass 11, count 2 2006.161.08:17:23.33#ibcon#end of sib2, iclass 11, count 2 2006.161.08:17:23.33#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:17:23.33#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:17:23.33#ibcon#[27=AT04-04\r\n] 2006.161.08:17:23.33#ibcon#*before write, iclass 11, count 2 2006.161.08:17:23.33#ibcon#enter sib2, iclass 11, count 2 2006.161.08:17:23.33#ibcon#flushed, iclass 11, count 2 2006.161.08:17:23.33#ibcon#about to write, iclass 11, count 2 2006.161.08:17:23.33#ibcon#wrote, iclass 11, count 2 2006.161.08:17:23.33#ibcon#about to read 3, iclass 11, count 2 2006.161.08:17:23.36#ibcon#read 3, iclass 11, count 2 2006.161.08:17:23.36#ibcon#about to read 4, iclass 11, count 2 2006.161.08:17:23.36#ibcon#read 4, iclass 11, count 2 2006.161.08:17:23.36#ibcon#about to read 5, iclass 11, count 2 2006.161.08:17:23.36#ibcon#read 5, iclass 11, count 2 2006.161.08:17:23.36#ibcon#about to read 6, iclass 11, count 2 2006.161.08:17:23.36#ibcon#read 6, iclass 11, count 2 2006.161.08:17:23.36#ibcon#end of sib2, iclass 11, count 2 2006.161.08:17:23.36#ibcon#*after write, iclass 11, count 2 2006.161.08:17:23.36#ibcon#*before return 0, iclass 11, count 2 2006.161.08:17:23.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:23.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:17:23.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:17:23.36#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:23.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:23.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:23.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:23.48#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:17:23.48#ibcon#first serial, iclass 11, count 0 2006.161.08:17:23.48#ibcon#enter sib2, iclass 11, count 0 2006.161.08:17:23.48#ibcon#flushed, iclass 11, count 0 2006.161.08:17:23.48#ibcon#about to write, iclass 11, count 0 2006.161.08:17:23.48#ibcon#wrote, iclass 11, count 0 2006.161.08:17:23.48#ibcon#about to read 3, iclass 11, count 0 2006.161.08:17:23.50#ibcon#read 3, iclass 11, count 0 2006.161.08:17:23.50#ibcon#about to read 4, iclass 11, count 0 2006.161.08:17:23.50#ibcon#read 4, iclass 11, count 0 2006.161.08:17:23.50#ibcon#about to read 5, iclass 11, count 0 2006.161.08:17:23.50#ibcon#read 5, iclass 11, count 0 2006.161.08:17:23.50#ibcon#about to read 6, iclass 11, count 0 2006.161.08:17:23.50#ibcon#read 6, iclass 11, count 0 2006.161.08:17:23.50#ibcon#end of sib2, iclass 11, count 0 2006.161.08:17:23.50#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:17:23.50#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:17:23.50#ibcon#[27=USB\r\n] 2006.161.08:17:23.50#ibcon#*before write, iclass 11, count 0 2006.161.08:17:23.50#ibcon#enter sib2, iclass 11, count 0 2006.161.08:17:23.50#ibcon#flushed, iclass 11, count 0 2006.161.08:17:23.50#ibcon#about to write, iclass 11, count 0 2006.161.08:17:23.50#ibcon#wrote, iclass 11, count 0 2006.161.08:17:23.50#ibcon#about to read 3, iclass 11, count 0 2006.161.08:17:23.53#ibcon#read 3, iclass 11, count 0 2006.161.08:17:23.53#ibcon#about to read 4, iclass 11, count 0 2006.161.08:17:23.53#ibcon#read 4, iclass 11, count 0 2006.161.08:17:23.53#ibcon#about to read 5, iclass 11, count 0 2006.161.08:17:23.53#ibcon#read 5, iclass 11, count 0 2006.161.08:17:23.53#ibcon#about to read 6, iclass 11, count 0 2006.161.08:17:23.53#ibcon#read 6, iclass 11, count 0 2006.161.08:17:23.53#ibcon#end of sib2, iclass 11, count 0 2006.161.08:17:23.53#ibcon#*after write, iclass 11, count 0 2006.161.08:17:23.53#ibcon#*before return 0, iclass 11, count 0 2006.161.08:17:23.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:23.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:17:23.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:17:23.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:17:23.53$vc4f8/vblo=5,744.99 2006.161.08:17:23.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:17:23.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:17:23.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:23.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:23.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:23.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:23.53#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:17:23.53#ibcon#first serial, iclass 13, count 0 2006.161.08:17:23.53#ibcon#enter sib2, iclass 13, count 0 2006.161.08:17:23.53#ibcon#flushed, iclass 13, count 0 2006.161.08:17:23.53#ibcon#about to write, iclass 13, count 0 2006.161.08:17:23.53#ibcon#wrote, iclass 13, count 0 2006.161.08:17:23.53#ibcon#about to read 3, iclass 13, count 0 2006.161.08:17:23.55#ibcon#read 3, iclass 13, count 0 2006.161.08:17:23.55#ibcon#about to read 4, iclass 13, count 0 2006.161.08:17:23.55#ibcon#read 4, iclass 13, count 0 2006.161.08:17:23.55#ibcon#about to read 5, iclass 13, count 0 2006.161.08:17:23.55#ibcon#read 5, iclass 13, count 0 2006.161.08:17:23.55#ibcon#about to read 6, iclass 13, count 0 2006.161.08:17:23.55#ibcon#read 6, iclass 13, count 0 2006.161.08:17:23.55#ibcon#end of sib2, iclass 13, count 0 2006.161.08:17:23.55#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:17:23.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:17:23.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:17:23.55#ibcon#*before write, iclass 13, count 0 2006.161.08:17:23.55#ibcon#enter sib2, iclass 13, count 0 2006.161.08:17:23.55#ibcon#flushed, iclass 13, count 0 2006.161.08:17:23.55#ibcon#about to write, iclass 13, count 0 2006.161.08:17:23.55#ibcon#wrote, iclass 13, count 0 2006.161.08:17:23.55#ibcon#about to read 3, iclass 13, count 0 2006.161.08:17:23.59#ibcon#read 3, iclass 13, count 0 2006.161.08:17:23.59#ibcon#about to read 4, iclass 13, count 0 2006.161.08:17:23.59#ibcon#read 4, iclass 13, count 0 2006.161.08:17:23.59#ibcon#about to read 5, iclass 13, count 0 2006.161.08:17:23.59#ibcon#read 5, iclass 13, count 0 2006.161.08:17:23.59#ibcon#about to read 6, iclass 13, count 0 2006.161.08:17:23.59#ibcon#read 6, iclass 13, count 0 2006.161.08:17:23.59#ibcon#end of sib2, iclass 13, count 0 2006.161.08:17:23.59#ibcon#*after write, iclass 13, count 0 2006.161.08:17:23.59#ibcon#*before return 0, iclass 13, count 0 2006.161.08:17:23.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:23.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:17:23.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:17:23.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:17:23.59$vc4f8/vb=5,4 2006.161.08:17:23.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:17:23.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:17:23.59#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:23.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:23.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:23.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:23.65#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:17:23.65#ibcon#first serial, iclass 15, count 2 2006.161.08:17:23.65#ibcon#enter sib2, iclass 15, count 2 2006.161.08:17:23.65#ibcon#flushed, iclass 15, count 2 2006.161.08:17:23.65#ibcon#about to write, iclass 15, count 2 2006.161.08:17:23.65#ibcon#wrote, iclass 15, count 2 2006.161.08:17:23.65#ibcon#about to read 3, iclass 15, count 2 2006.161.08:17:23.67#ibcon#read 3, iclass 15, count 2 2006.161.08:17:23.67#ibcon#about to read 4, iclass 15, count 2 2006.161.08:17:23.67#ibcon#read 4, iclass 15, count 2 2006.161.08:17:23.67#ibcon#about to read 5, iclass 15, count 2 2006.161.08:17:23.67#ibcon#read 5, iclass 15, count 2 2006.161.08:17:23.67#ibcon#about to read 6, iclass 15, count 2 2006.161.08:17:23.67#ibcon#read 6, iclass 15, count 2 2006.161.08:17:23.67#ibcon#end of sib2, iclass 15, count 2 2006.161.08:17:23.67#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:17:23.67#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:17:23.67#ibcon#[27=AT05-04\r\n] 2006.161.08:17:23.67#ibcon#*before write, iclass 15, count 2 2006.161.08:17:23.67#ibcon#enter sib2, iclass 15, count 2 2006.161.08:17:23.67#ibcon#flushed, iclass 15, count 2 2006.161.08:17:23.67#ibcon#about to write, iclass 15, count 2 2006.161.08:17:23.67#ibcon#wrote, iclass 15, count 2 2006.161.08:17:23.67#ibcon#about to read 3, iclass 15, count 2 2006.161.08:17:23.70#ibcon#read 3, iclass 15, count 2 2006.161.08:17:23.70#ibcon#about to read 4, iclass 15, count 2 2006.161.08:17:23.70#ibcon#read 4, iclass 15, count 2 2006.161.08:17:23.70#ibcon#about to read 5, iclass 15, count 2 2006.161.08:17:23.70#ibcon#read 5, iclass 15, count 2 2006.161.08:17:23.70#ibcon#about to read 6, iclass 15, count 2 2006.161.08:17:23.70#ibcon#read 6, iclass 15, count 2 2006.161.08:17:23.70#ibcon#end of sib2, iclass 15, count 2 2006.161.08:17:23.70#ibcon#*after write, iclass 15, count 2 2006.161.08:17:23.70#ibcon#*before return 0, iclass 15, count 2 2006.161.08:17:23.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:23.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:17:23.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:17:23.70#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:23.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:23.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:23.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:23.82#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:17:23.82#ibcon#first serial, iclass 15, count 0 2006.161.08:17:23.82#ibcon#enter sib2, iclass 15, count 0 2006.161.08:17:23.82#ibcon#flushed, iclass 15, count 0 2006.161.08:17:23.82#ibcon#about to write, iclass 15, count 0 2006.161.08:17:23.82#ibcon#wrote, iclass 15, count 0 2006.161.08:17:23.82#ibcon#about to read 3, iclass 15, count 0 2006.161.08:17:23.84#ibcon#read 3, iclass 15, count 0 2006.161.08:17:23.84#ibcon#about to read 4, iclass 15, count 0 2006.161.08:17:23.84#ibcon#read 4, iclass 15, count 0 2006.161.08:17:23.84#ibcon#about to read 5, iclass 15, count 0 2006.161.08:17:23.84#ibcon#read 5, iclass 15, count 0 2006.161.08:17:23.84#ibcon#about to read 6, iclass 15, count 0 2006.161.08:17:23.84#ibcon#read 6, iclass 15, count 0 2006.161.08:17:23.84#ibcon#end of sib2, iclass 15, count 0 2006.161.08:17:23.84#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:17:23.84#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:17:23.84#ibcon#[27=USB\r\n] 2006.161.08:17:23.84#ibcon#*before write, iclass 15, count 0 2006.161.08:17:23.84#ibcon#enter sib2, iclass 15, count 0 2006.161.08:17:23.84#ibcon#flushed, iclass 15, count 0 2006.161.08:17:23.84#ibcon#about to write, iclass 15, count 0 2006.161.08:17:23.84#ibcon#wrote, iclass 15, count 0 2006.161.08:17:23.84#ibcon#about to read 3, iclass 15, count 0 2006.161.08:17:23.87#ibcon#read 3, iclass 15, count 0 2006.161.08:17:23.87#ibcon#about to read 4, iclass 15, count 0 2006.161.08:17:23.87#ibcon#read 4, iclass 15, count 0 2006.161.08:17:23.87#ibcon#about to read 5, iclass 15, count 0 2006.161.08:17:23.87#ibcon#read 5, iclass 15, count 0 2006.161.08:17:23.87#ibcon#about to read 6, iclass 15, count 0 2006.161.08:17:23.87#ibcon#read 6, iclass 15, count 0 2006.161.08:17:23.87#ibcon#end of sib2, iclass 15, count 0 2006.161.08:17:23.87#ibcon#*after write, iclass 15, count 0 2006.161.08:17:23.87#ibcon#*before return 0, iclass 15, count 0 2006.161.08:17:23.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:23.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:17:23.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:17:23.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:17:23.87$vc4f8/vblo=6,752.99 2006.161.08:17:23.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:17:23.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:17:23.87#ibcon#ireg 17 cls_cnt 0 2006.161.08:17:23.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:23.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:23.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:23.87#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:17:23.87#ibcon#first serial, iclass 17, count 0 2006.161.08:17:23.87#ibcon#enter sib2, iclass 17, count 0 2006.161.08:17:23.87#ibcon#flushed, iclass 17, count 0 2006.161.08:17:23.87#ibcon#about to write, iclass 17, count 0 2006.161.08:17:23.87#ibcon#wrote, iclass 17, count 0 2006.161.08:17:23.87#ibcon#about to read 3, iclass 17, count 0 2006.161.08:17:23.89#ibcon#read 3, iclass 17, count 0 2006.161.08:17:23.89#ibcon#about to read 4, iclass 17, count 0 2006.161.08:17:23.89#ibcon#read 4, iclass 17, count 0 2006.161.08:17:23.89#ibcon#about to read 5, iclass 17, count 0 2006.161.08:17:23.89#ibcon#read 5, iclass 17, count 0 2006.161.08:17:23.89#ibcon#about to read 6, iclass 17, count 0 2006.161.08:17:23.89#ibcon#read 6, iclass 17, count 0 2006.161.08:17:23.89#ibcon#end of sib2, iclass 17, count 0 2006.161.08:17:23.89#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:17:23.89#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:17:23.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:17:23.89#ibcon#*before write, iclass 17, count 0 2006.161.08:17:23.89#ibcon#enter sib2, iclass 17, count 0 2006.161.08:17:23.89#ibcon#flushed, iclass 17, count 0 2006.161.08:17:23.89#ibcon#about to write, iclass 17, count 0 2006.161.08:17:23.89#ibcon#wrote, iclass 17, count 0 2006.161.08:17:23.89#ibcon#about to read 3, iclass 17, count 0 2006.161.08:17:23.93#ibcon#read 3, iclass 17, count 0 2006.161.08:17:23.93#ibcon#about to read 4, iclass 17, count 0 2006.161.08:17:23.93#ibcon#read 4, iclass 17, count 0 2006.161.08:17:23.93#ibcon#about to read 5, iclass 17, count 0 2006.161.08:17:23.93#ibcon#read 5, iclass 17, count 0 2006.161.08:17:23.93#ibcon#about to read 6, iclass 17, count 0 2006.161.08:17:23.93#ibcon#read 6, iclass 17, count 0 2006.161.08:17:23.93#ibcon#end of sib2, iclass 17, count 0 2006.161.08:17:23.93#ibcon#*after write, iclass 17, count 0 2006.161.08:17:23.93#ibcon#*before return 0, iclass 17, count 0 2006.161.08:17:23.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:23.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:17:23.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:17:23.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:17:23.93$vc4f8/vb=6,4 2006.161.08:17:23.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:17:23.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:17:23.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:17:23.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:23.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:23.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:23.99#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:17:23.99#ibcon#first serial, iclass 19, count 2 2006.161.08:17:23.99#ibcon#enter sib2, iclass 19, count 2 2006.161.08:17:23.99#ibcon#flushed, iclass 19, count 2 2006.161.08:17:23.99#ibcon#about to write, iclass 19, count 2 2006.161.08:17:23.99#ibcon#wrote, iclass 19, count 2 2006.161.08:17:23.99#ibcon#about to read 3, iclass 19, count 2 2006.161.08:17:24.01#ibcon#read 3, iclass 19, count 2 2006.161.08:17:24.01#ibcon#about to read 4, iclass 19, count 2 2006.161.08:17:24.01#ibcon#read 4, iclass 19, count 2 2006.161.08:17:24.01#ibcon#about to read 5, iclass 19, count 2 2006.161.08:17:24.01#ibcon#read 5, iclass 19, count 2 2006.161.08:17:24.01#ibcon#about to read 6, iclass 19, count 2 2006.161.08:17:24.01#ibcon#read 6, iclass 19, count 2 2006.161.08:17:24.01#ibcon#end of sib2, iclass 19, count 2 2006.161.08:17:24.01#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:17:24.01#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:17:24.01#ibcon#[27=AT06-04\r\n] 2006.161.08:17:24.01#ibcon#*before write, iclass 19, count 2 2006.161.08:17:24.01#ibcon#enter sib2, iclass 19, count 2 2006.161.08:17:24.01#ibcon#flushed, iclass 19, count 2 2006.161.08:17:24.01#ibcon#about to write, iclass 19, count 2 2006.161.08:17:24.01#ibcon#wrote, iclass 19, count 2 2006.161.08:17:24.01#ibcon#about to read 3, iclass 19, count 2 2006.161.08:17:24.04#ibcon#read 3, iclass 19, count 2 2006.161.08:17:24.04#ibcon#about to read 4, iclass 19, count 2 2006.161.08:17:24.04#ibcon#read 4, iclass 19, count 2 2006.161.08:17:24.04#ibcon#about to read 5, iclass 19, count 2 2006.161.08:17:24.04#ibcon#read 5, iclass 19, count 2 2006.161.08:17:24.04#ibcon#about to read 6, iclass 19, count 2 2006.161.08:17:24.04#ibcon#read 6, iclass 19, count 2 2006.161.08:17:24.04#ibcon#end of sib2, iclass 19, count 2 2006.161.08:17:24.04#ibcon#*after write, iclass 19, count 2 2006.161.08:17:24.04#ibcon#*before return 0, iclass 19, count 2 2006.161.08:17:24.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:24.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:17:24.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:17:24.04#ibcon#ireg 7 cls_cnt 0 2006.161.08:17:24.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:24.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:24.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:24.16#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:17:24.16#ibcon#first serial, iclass 19, count 0 2006.161.08:17:24.16#ibcon#enter sib2, iclass 19, count 0 2006.161.08:17:24.16#ibcon#flushed, iclass 19, count 0 2006.161.08:17:24.16#ibcon#about to write, iclass 19, count 0 2006.161.08:17:24.16#ibcon#wrote, iclass 19, count 0 2006.161.08:17:24.16#ibcon#about to read 3, iclass 19, count 0 2006.161.08:17:24.18#ibcon#read 3, iclass 19, count 0 2006.161.08:17:24.18#ibcon#about to read 4, iclass 19, count 0 2006.161.08:17:24.18#ibcon#read 4, iclass 19, count 0 2006.161.08:17:24.18#ibcon#about to read 5, iclass 19, count 0 2006.161.08:17:24.18#ibcon#read 5, iclass 19, count 0 2006.161.08:17:24.18#ibcon#about to read 6, iclass 19, count 0 2006.161.08:17:24.18#ibcon#read 6, iclass 19, count 0 2006.161.08:17:24.18#ibcon#end of sib2, iclass 19, count 0 2006.161.08:17:24.18#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:17:24.18#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:17:24.18#ibcon#[27=USB\r\n] 2006.161.08:17:24.18#ibcon#*before write, iclass 19, count 0 2006.161.08:17:24.18#ibcon#enter sib2, iclass 19, count 0 2006.161.08:17:24.18#ibcon#flushed, iclass 19, count 0 2006.161.08:17:24.18#ibcon#about to write, iclass 19, count 0 2006.161.08:17:24.18#ibcon#wrote, iclass 19, count 0 2006.161.08:17:24.18#ibcon#about to read 3, iclass 19, count 0 2006.161.08:17:24.21#ibcon#read 3, iclass 19, count 0 2006.161.08:17:24.21#ibcon#about to read 4, iclass 19, count 0 2006.161.08:17:24.21#ibcon#read 4, iclass 19, count 0 2006.161.08:17:24.21#ibcon#about to read 5, iclass 19, count 0 2006.161.08:17:24.21#ibcon#read 5, iclass 19, count 0 2006.161.08:17:24.21#ibcon#about to read 6, iclass 19, count 0 2006.161.08:17:24.21#ibcon#read 6, iclass 19, count 0 2006.161.08:17:24.21#ibcon#end of sib2, iclass 19, count 0 2006.161.08:17:24.21#ibcon#*after write, iclass 19, count 0 2006.161.08:17:24.21#ibcon#*before return 0, iclass 19, count 0 2006.161.08:17:24.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:24.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:17:24.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:17:24.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:17:24.21$vc4f8/vabw=wide 2006.161.08:17:24.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:17:24.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:17:24.21#ibcon#ireg 8 cls_cnt 0 2006.161.08:17:24.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:24.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:24.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:24.21#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:17:24.21#ibcon#first serial, iclass 21, count 0 2006.161.08:17:24.21#ibcon#enter sib2, iclass 21, count 0 2006.161.08:17:24.21#ibcon#flushed, iclass 21, count 0 2006.161.08:17:24.21#ibcon#about to write, iclass 21, count 0 2006.161.08:17:24.21#ibcon#wrote, iclass 21, count 0 2006.161.08:17:24.21#ibcon#about to read 3, iclass 21, count 0 2006.161.08:17:24.23#ibcon#read 3, iclass 21, count 0 2006.161.08:17:24.23#ibcon#about to read 4, iclass 21, count 0 2006.161.08:17:24.23#ibcon#read 4, iclass 21, count 0 2006.161.08:17:24.23#ibcon#about to read 5, iclass 21, count 0 2006.161.08:17:24.23#ibcon#read 5, iclass 21, count 0 2006.161.08:17:24.23#ibcon#about to read 6, iclass 21, count 0 2006.161.08:17:24.23#ibcon#read 6, iclass 21, count 0 2006.161.08:17:24.23#ibcon#end of sib2, iclass 21, count 0 2006.161.08:17:24.23#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:17:24.23#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:17:24.23#ibcon#[25=BW32\r\n] 2006.161.08:17:24.23#ibcon#*before write, iclass 21, count 0 2006.161.08:17:24.23#ibcon#enter sib2, iclass 21, count 0 2006.161.08:17:24.23#ibcon#flushed, iclass 21, count 0 2006.161.08:17:24.23#ibcon#about to write, iclass 21, count 0 2006.161.08:17:24.23#ibcon#wrote, iclass 21, count 0 2006.161.08:17:24.23#ibcon#about to read 3, iclass 21, count 0 2006.161.08:17:24.26#ibcon#read 3, iclass 21, count 0 2006.161.08:17:24.26#ibcon#about to read 4, iclass 21, count 0 2006.161.08:17:24.26#ibcon#read 4, iclass 21, count 0 2006.161.08:17:24.26#ibcon#about to read 5, iclass 21, count 0 2006.161.08:17:24.26#ibcon#read 5, iclass 21, count 0 2006.161.08:17:24.26#ibcon#about to read 6, iclass 21, count 0 2006.161.08:17:24.26#ibcon#read 6, iclass 21, count 0 2006.161.08:17:24.26#ibcon#end of sib2, iclass 21, count 0 2006.161.08:17:24.26#ibcon#*after write, iclass 21, count 0 2006.161.08:17:24.26#ibcon#*before return 0, iclass 21, count 0 2006.161.08:17:24.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:24.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:17:24.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:17:24.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:17:24.26$vc4f8/vbbw=wide 2006.161.08:17:24.26#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:17:24.26#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:17:24.26#ibcon#ireg 8 cls_cnt 0 2006.161.08:17:24.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:17:24.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:17:24.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:17:24.33#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:17:24.33#ibcon#first serial, iclass 23, count 0 2006.161.08:17:24.33#ibcon#enter sib2, iclass 23, count 0 2006.161.08:17:24.33#ibcon#flushed, iclass 23, count 0 2006.161.08:17:24.33#ibcon#about to write, iclass 23, count 0 2006.161.08:17:24.33#ibcon#wrote, iclass 23, count 0 2006.161.08:17:24.33#ibcon#about to read 3, iclass 23, count 0 2006.161.08:17:24.35#ibcon#read 3, iclass 23, count 0 2006.161.08:17:24.35#ibcon#about to read 4, iclass 23, count 0 2006.161.08:17:24.35#ibcon#read 4, iclass 23, count 0 2006.161.08:17:24.35#ibcon#about to read 5, iclass 23, count 0 2006.161.08:17:24.35#ibcon#read 5, iclass 23, count 0 2006.161.08:17:24.35#ibcon#about to read 6, iclass 23, count 0 2006.161.08:17:24.35#ibcon#read 6, iclass 23, count 0 2006.161.08:17:24.35#ibcon#end of sib2, iclass 23, count 0 2006.161.08:17:24.35#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:17:24.35#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:17:24.35#ibcon#[27=BW32\r\n] 2006.161.08:17:24.35#ibcon#*before write, iclass 23, count 0 2006.161.08:17:24.35#ibcon#enter sib2, iclass 23, count 0 2006.161.08:17:24.35#ibcon#flushed, iclass 23, count 0 2006.161.08:17:24.35#ibcon#about to write, iclass 23, count 0 2006.161.08:17:24.35#ibcon#wrote, iclass 23, count 0 2006.161.08:17:24.35#ibcon#about to read 3, iclass 23, count 0 2006.161.08:17:24.38#ibcon#read 3, iclass 23, count 0 2006.161.08:17:24.38#ibcon#about to read 4, iclass 23, count 0 2006.161.08:17:24.38#ibcon#read 4, iclass 23, count 0 2006.161.08:17:24.38#ibcon#about to read 5, iclass 23, count 0 2006.161.08:17:24.38#ibcon#read 5, iclass 23, count 0 2006.161.08:17:24.38#ibcon#about to read 6, iclass 23, count 0 2006.161.08:17:24.38#ibcon#read 6, iclass 23, count 0 2006.161.08:17:24.38#ibcon#end of sib2, iclass 23, count 0 2006.161.08:17:24.38#ibcon#*after write, iclass 23, count 0 2006.161.08:17:24.38#ibcon#*before return 0, iclass 23, count 0 2006.161.08:17:24.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:17:24.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:17:24.38#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:17:24.38#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:17:24.38$4f8m12a/ifd4f 2006.161.08:17:24.38$ifd4f/lo= 2006.161.08:17:24.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:17:24.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:17:24.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:17:24.38$ifd4f/patch= 2006.161.08:17:24.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:17:24.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:17:24.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:17:24.38$4f8m12a/"form=m,16.000,1:2 2006.161.08:17:24.38$4f8m12a/"tpicd 2006.161.08:17:24.38$4f8m12a/echo=off 2006.161.08:17:24.38$4f8m12a/xlog=off 2006.161.08:17:24.38:!2006.161.08:18:50 2006.161.08:17:27.14#trakl#Source acquired 2006.161.08:17:29.14#flagr#flagr/antenna,acquired 2006.161.08:18:50.00:preob 2006.161.08:18:51.14/onsource/TRACKING 2006.161.08:18:51.14:!2006.161.08:19:00 2006.161.08:19:00.00:data_valid=on 2006.161.08:19:00.00:midob 2006.161.08:19:00.14/onsource/TRACKING 2006.161.08:19:00.14/wx/23.98,1002.5,86 2006.161.08:19:00.32/cable/+6.4998E-03 2006.161.08:19:01.41/va/01,08,usb,yes,30,32 2006.161.08:19:01.41/va/02,07,usb,yes,31,32 2006.161.08:19:01.41/va/03,06,usb,yes,32,32 2006.161.08:19:01.41/va/04,07,usb,yes,31,34 2006.161.08:19:01.41/va/05,07,usb,yes,32,34 2006.161.08:19:01.41/va/06,06,usb,yes,31,31 2006.161.08:19:01.41/va/07,06,usb,yes,31,31 2006.161.08:19:01.41/va/08,07,usb,yes,30,29 2006.161.08:19:01.64/valo/01,532.99,yes,locked 2006.161.08:19:01.64/valo/02,572.99,yes,locked 2006.161.08:19:01.64/valo/03,672.99,yes,locked 2006.161.08:19:01.64/valo/04,832.99,yes,locked 2006.161.08:19:01.64/valo/05,652.99,yes,locked 2006.161.08:19:01.64/valo/06,772.99,yes,locked 2006.161.08:19:01.64/valo/07,832.99,yes,locked 2006.161.08:19:01.64/valo/08,852.99,yes,locked 2006.161.08:19:02.73/vb/01,04,usb,yes,30,28 2006.161.08:19:02.73/vb/02,04,usb,yes,32,33 2006.161.08:19:02.73/vb/03,04,usb,yes,28,32 2006.161.08:19:02.73/vb/04,04,usb,yes,29,29 2006.161.08:19:02.73/vb/05,04,usb,yes,27,31 2006.161.08:19:02.73/vb/06,04,usb,yes,28,31 2006.161.08:19:02.73/vb/07,04,usb,yes,30,30 2006.161.08:19:02.73/vb/08,04,usb,yes,28,31 2006.161.08:19:02.97/vblo/01,632.99,yes,locked 2006.161.08:19:02.97/vblo/02,640.99,yes,locked 2006.161.08:19:02.97/vblo/03,656.99,yes,locked 2006.161.08:19:02.97/vblo/04,712.99,yes,locked 2006.161.08:19:02.97/vblo/05,744.99,yes,locked 2006.161.08:19:02.97/vblo/06,752.99,yes,locked 2006.161.08:19:02.97/vblo/07,734.99,yes,locked 2006.161.08:19:02.97/vblo/08,744.99,yes,locked 2006.161.08:19:03.12/vabw/8 2006.161.08:19:03.27/vbbw/8 2006.161.08:19:03.36/xfe/off,on,14.2 2006.161.08:19:03.75/ifatt/23,28,28,28 2006.161.08:19:04.08/fmout-gps/S +4.50E-07 2006.161.08:19:04.12:!2006.161.08:20:00 2006.161.08:20:00.00:data_valid=off 2006.161.08:20:00.00:postob 2006.161.08:20:00.21/cable/+6.4994E-03 2006.161.08:20:00.21/wx/23.98,1002.5,87 2006.161.08:20:01.08/fmout-gps/S +4.50E-07 2006.161.08:20:01.08:scan_name=161-0822,k06161,60 2006.161.08:20:01.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.161.08:20:01.15#flagr#flagr/antenna,new-source 2006.161.08:20:02.14:checkk5 2006.161.08:20:02.56/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:20:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:20:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:20:03.81/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:20:04.25/chk_obsdata//k5ts1/T1610819??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:20:04.65/chk_obsdata//k5ts2/T1610819??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:20:05.12/chk_obsdata//k5ts3/T1610819??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:20:05.62/chk_obsdata//k5ts4/T1610819??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:20:06.43/k5log//k5ts1_log_newline 2006.161.08:20:07.38/k5log//k5ts2_log_newline 2006.161.08:20:08.15/k5log//k5ts3_log_newline 2006.161.08:20:09.54/k5log//k5ts4_log_newline 2006.161.08:20:09.57/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:20:09.57:4f8m12a=3 2006.161.08:20:09.57$4f8m12a/echo=on 2006.161.08:20:09.57$4f8m12a/pcalon 2006.161.08:20:09.57$pcalon/"no phase cal control is implemented here 2006.161.08:20:09.57$4f8m12a/"tpicd=stop 2006.161.08:20:09.57$4f8m12a/vc4f8 2006.161.08:20:09.57$vc4f8/valo=1,532.99 2006.161.08:20:09.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:20:09.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:20:09.58#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:09.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:09.58#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:09.58#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:09.58#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:20:09.58#ibcon#first serial, iclass 22, count 0 2006.161.08:20:09.58#ibcon#enter sib2, iclass 22, count 0 2006.161.08:20:09.58#ibcon#flushed, iclass 22, count 0 2006.161.08:20:09.58#ibcon#about to write, iclass 22, count 0 2006.161.08:20:09.58#ibcon#wrote, iclass 22, count 0 2006.161.08:20:09.58#ibcon#about to read 3, iclass 22, count 0 2006.161.08:20:09.62#ibcon#read 3, iclass 22, count 0 2006.161.08:20:09.62#ibcon#about to read 4, iclass 22, count 0 2006.161.08:20:09.62#ibcon#read 4, iclass 22, count 0 2006.161.08:20:09.62#ibcon#about to read 5, iclass 22, count 0 2006.161.08:20:09.62#ibcon#read 5, iclass 22, count 0 2006.161.08:20:09.62#ibcon#about to read 6, iclass 22, count 0 2006.161.08:20:09.62#ibcon#read 6, iclass 22, count 0 2006.161.08:20:09.62#ibcon#end of sib2, iclass 22, count 0 2006.161.08:20:09.62#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:20:09.62#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:20:09.62#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:20:09.62#ibcon#*before write, iclass 22, count 0 2006.161.08:20:09.62#ibcon#enter sib2, iclass 22, count 0 2006.161.08:20:09.62#ibcon#flushed, iclass 22, count 0 2006.161.08:20:09.62#ibcon#about to write, iclass 22, count 0 2006.161.08:20:09.62#ibcon#wrote, iclass 22, count 0 2006.161.08:20:09.62#ibcon#about to read 3, iclass 22, count 0 2006.161.08:20:09.66#ibcon#read 3, iclass 22, count 0 2006.161.08:20:09.66#ibcon#about to read 4, iclass 22, count 0 2006.161.08:20:09.66#ibcon#read 4, iclass 22, count 0 2006.161.08:20:09.66#ibcon#about to read 5, iclass 22, count 0 2006.161.08:20:09.66#ibcon#read 5, iclass 22, count 0 2006.161.08:20:09.66#ibcon#about to read 6, iclass 22, count 0 2006.161.08:20:09.66#ibcon#read 6, iclass 22, count 0 2006.161.08:20:09.66#ibcon#end of sib2, iclass 22, count 0 2006.161.08:20:09.66#ibcon#*after write, iclass 22, count 0 2006.161.08:20:09.66#ibcon#*before return 0, iclass 22, count 0 2006.161.08:20:09.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:09.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:09.66#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:20:09.66#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:20:09.66$vc4f8/va=1,8 2006.161.08:20:09.66#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:20:09.66#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:20:09.66#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:09.66#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:09.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:09.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:09.66#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:20:09.66#ibcon#first serial, iclass 24, count 2 2006.161.08:20:09.66#ibcon#enter sib2, iclass 24, count 2 2006.161.08:20:09.66#ibcon#flushed, iclass 24, count 2 2006.161.08:20:09.66#ibcon#about to write, iclass 24, count 2 2006.161.08:20:09.66#ibcon#wrote, iclass 24, count 2 2006.161.08:20:09.66#ibcon#about to read 3, iclass 24, count 2 2006.161.08:20:09.68#ibcon#read 3, iclass 24, count 2 2006.161.08:20:09.68#ibcon#about to read 4, iclass 24, count 2 2006.161.08:20:09.68#ibcon#read 4, iclass 24, count 2 2006.161.08:20:09.68#ibcon#about to read 5, iclass 24, count 2 2006.161.08:20:09.68#ibcon#read 5, iclass 24, count 2 2006.161.08:20:09.68#ibcon#about to read 6, iclass 24, count 2 2006.161.08:20:09.68#ibcon#read 6, iclass 24, count 2 2006.161.08:20:09.68#ibcon#end of sib2, iclass 24, count 2 2006.161.08:20:09.68#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:20:09.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:20:09.68#ibcon#[25=AT01-08\r\n] 2006.161.08:20:09.68#ibcon#*before write, iclass 24, count 2 2006.161.08:20:09.68#ibcon#enter sib2, iclass 24, count 2 2006.161.08:20:09.68#ibcon#flushed, iclass 24, count 2 2006.161.08:20:09.68#ibcon#about to write, iclass 24, count 2 2006.161.08:20:09.68#ibcon#wrote, iclass 24, count 2 2006.161.08:20:09.68#ibcon#about to read 3, iclass 24, count 2 2006.161.08:20:09.71#ibcon#read 3, iclass 24, count 2 2006.161.08:20:09.71#ibcon#about to read 4, iclass 24, count 2 2006.161.08:20:09.71#ibcon#read 4, iclass 24, count 2 2006.161.08:20:09.71#ibcon#about to read 5, iclass 24, count 2 2006.161.08:20:09.71#ibcon#read 5, iclass 24, count 2 2006.161.08:20:09.71#ibcon#about to read 6, iclass 24, count 2 2006.161.08:20:09.71#ibcon#read 6, iclass 24, count 2 2006.161.08:20:09.71#ibcon#end of sib2, iclass 24, count 2 2006.161.08:20:09.71#ibcon#*after write, iclass 24, count 2 2006.161.08:20:09.71#ibcon#*before return 0, iclass 24, count 2 2006.161.08:20:09.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:09.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:09.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:20:09.71#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:09.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:09.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:09.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:09.83#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:20:09.83#ibcon#first serial, iclass 24, count 0 2006.161.08:20:09.83#ibcon#enter sib2, iclass 24, count 0 2006.161.08:20:09.83#ibcon#flushed, iclass 24, count 0 2006.161.08:20:09.83#ibcon#about to write, iclass 24, count 0 2006.161.08:20:09.83#ibcon#wrote, iclass 24, count 0 2006.161.08:20:09.83#ibcon#about to read 3, iclass 24, count 0 2006.161.08:20:09.85#ibcon#read 3, iclass 24, count 0 2006.161.08:20:09.85#ibcon#about to read 4, iclass 24, count 0 2006.161.08:20:09.85#ibcon#read 4, iclass 24, count 0 2006.161.08:20:09.85#ibcon#about to read 5, iclass 24, count 0 2006.161.08:20:09.85#ibcon#read 5, iclass 24, count 0 2006.161.08:20:09.85#ibcon#about to read 6, iclass 24, count 0 2006.161.08:20:09.85#ibcon#read 6, iclass 24, count 0 2006.161.08:20:09.85#ibcon#end of sib2, iclass 24, count 0 2006.161.08:20:09.85#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:20:09.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:20:09.85#ibcon#[25=USB\r\n] 2006.161.08:20:09.85#ibcon#*before write, iclass 24, count 0 2006.161.08:20:09.85#ibcon#enter sib2, iclass 24, count 0 2006.161.08:20:09.85#ibcon#flushed, iclass 24, count 0 2006.161.08:20:09.85#ibcon#about to write, iclass 24, count 0 2006.161.08:20:09.85#ibcon#wrote, iclass 24, count 0 2006.161.08:20:09.85#ibcon#about to read 3, iclass 24, count 0 2006.161.08:20:09.88#ibcon#read 3, iclass 24, count 0 2006.161.08:20:09.88#ibcon#about to read 4, iclass 24, count 0 2006.161.08:20:09.88#ibcon#read 4, iclass 24, count 0 2006.161.08:20:09.88#ibcon#about to read 5, iclass 24, count 0 2006.161.08:20:09.88#ibcon#read 5, iclass 24, count 0 2006.161.08:20:09.88#ibcon#about to read 6, iclass 24, count 0 2006.161.08:20:09.88#ibcon#read 6, iclass 24, count 0 2006.161.08:20:09.88#ibcon#end of sib2, iclass 24, count 0 2006.161.08:20:09.88#ibcon#*after write, iclass 24, count 0 2006.161.08:20:09.88#ibcon#*before return 0, iclass 24, count 0 2006.161.08:20:09.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:09.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:09.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:20:09.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:20:09.88$vc4f8/valo=2,572.99 2006.161.08:20:09.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:20:09.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:20:09.88#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:09.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:09.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:09.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:09.88#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:20:09.88#ibcon#first serial, iclass 26, count 0 2006.161.08:20:09.88#ibcon#enter sib2, iclass 26, count 0 2006.161.08:20:09.88#ibcon#flushed, iclass 26, count 0 2006.161.08:20:09.88#ibcon#about to write, iclass 26, count 0 2006.161.08:20:09.88#ibcon#wrote, iclass 26, count 0 2006.161.08:20:09.88#ibcon#about to read 3, iclass 26, count 0 2006.161.08:20:09.90#ibcon#read 3, iclass 26, count 0 2006.161.08:20:09.90#ibcon#about to read 4, iclass 26, count 0 2006.161.08:20:09.90#ibcon#read 4, iclass 26, count 0 2006.161.08:20:09.90#ibcon#about to read 5, iclass 26, count 0 2006.161.08:20:09.90#ibcon#read 5, iclass 26, count 0 2006.161.08:20:09.90#ibcon#about to read 6, iclass 26, count 0 2006.161.08:20:09.90#ibcon#read 6, iclass 26, count 0 2006.161.08:20:09.90#ibcon#end of sib2, iclass 26, count 0 2006.161.08:20:09.90#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:20:09.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:20:09.90#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:20:09.90#ibcon#*before write, iclass 26, count 0 2006.161.08:20:09.90#ibcon#enter sib2, iclass 26, count 0 2006.161.08:20:09.90#ibcon#flushed, iclass 26, count 0 2006.161.08:20:09.90#ibcon#about to write, iclass 26, count 0 2006.161.08:20:09.90#ibcon#wrote, iclass 26, count 0 2006.161.08:20:09.90#ibcon#about to read 3, iclass 26, count 0 2006.161.08:20:09.94#ibcon#read 3, iclass 26, count 0 2006.161.08:20:09.94#ibcon#about to read 4, iclass 26, count 0 2006.161.08:20:09.94#ibcon#read 4, iclass 26, count 0 2006.161.08:20:09.94#ibcon#about to read 5, iclass 26, count 0 2006.161.08:20:09.94#ibcon#read 5, iclass 26, count 0 2006.161.08:20:09.94#ibcon#about to read 6, iclass 26, count 0 2006.161.08:20:09.94#ibcon#read 6, iclass 26, count 0 2006.161.08:20:09.94#ibcon#end of sib2, iclass 26, count 0 2006.161.08:20:09.94#ibcon#*after write, iclass 26, count 0 2006.161.08:20:09.94#ibcon#*before return 0, iclass 26, count 0 2006.161.08:20:09.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:09.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:09.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:20:09.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:20:09.94$vc4f8/va=2,7 2006.161.08:20:09.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:20:09.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:20:09.94#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:09.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:10.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:10.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:10.00#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:20:10.00#ibcon#first serial, iclass 28, count 2 2006.161.08:20:10.00#ibcon#enter sib2, iclass 28, count 2 2006.161.08:20:10.00#ibcon#flushed, iclass 28, count 2 2006.161.08:20:10.00#ibcon#about to write, iclass 28, count 2 2006.161.08:20:10.00#ibcon#wrote, iclass 28, count 2 2006.161.08:20:10.00#ibcon#about to read 3, iclass 28, count 2 2006.161.08:20:10.02#ibcon#read 3, iclass 28, count 2 2006.161.08:20:10.02#ibcon#about to read 4, iclass 28, count 2 2006.161.08:20:10.02#ibcon#read 4, iclass 28, count 2 2006.161.08:20:10.02#ibcon#about to read 5, iclass 28, count 2 2006.161.08:20:10.02#ibcon#read 5, iclass 28, count 2 2006.161.08:20:10.02#ibcon#about to read 6, iclass 28, count 2 2006.161.08:20:10.02#ibcon#read 6, iclass 28, count 2 2006.161.08:20:10.02#ibcon#end of sib2, iclass 28, count 2 2006.161.08:20:10.02#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:20:10.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:20:10.02#ibcon#[25=AT02-07\r\n] 2006.161.08:20:10.02#ibcon#*before write, iclass 28, count 2 2006.161.08:20:10.02#ibcon#enter sib2, iclass 28, count 2 2006.161.08:20:10.02#ibcon#flushed, iclass 28, count 2 2006.161.08:20:10.02#ibcon#about to write, iclass 28, count 2 2006.161.08:20:10.02#ibcon#wrote, iclass 28, count 2 2006.161.08:20:10.02#ibcon#about to read 3, iclass 28, count 2 2006.161.08:20:10.05#ibcon#read 3, iclass 28, count 2 2006.161.08:20:10.05#ibcon#about to read 4, iclass 28, count 2 2006.161.08:20:10.05#ibcon#read 4, iclass 28, count 2 2006.161.08:20:10.05#ibcon#about to read 5, iclass 28, count 2 2006.161.08:20:10.05#ibcon#read 5, iclass 28, count 2 2006.161.08:20:10.05#ibcon#about to read 6, iclass 28, count 2 2006.161.08:20:10.05#ibcon#read 6, iclass 28, count 2 2006.161.08:20:10.05#ibcon#end of sib2, iclass 28, count 2 2006.161.08:20:10.05#ibcon#*after write, iclass 28, count 2 2006.161.08:20:10.05#ibcon#*before return 0, iclass 28, count 2 2006.161.08:20:10.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:10.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:10.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:20:10.05#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:10.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:10.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:10.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:10.17#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:20:10.17#ibcon#first serial, iclass 28, count 0 2006.161.08:20:10.17#ibcon#enter sib2, iclass 28, count 0 2006.161.08:20:10.17#ibcon#flushed, iclass 28, count 0 2006.161.08:20:10.17#ibcon#about to write, iclass 28, count 0 2006.161.08:20:10.17#ibcon#wrote, iclass 28, count 0 2006.161.08:20:10.17#ibcon#about to read 3, iclass 28, count 0 2006.161.08:20:10.19#ibcon#read 3, iclass 28, count 0 2006.161.08:20:10.19#ibcon#about to read 4, iclass 28, count 0 2006.161.08:20:10.19#ibcon#read 4, iclass 28, count 0 2006.161.08:20:10.19#ibcon#about to read 5, iclass 28, count 0 2006.161.08:20:10.19#ibcon#read 5, iclass 28, count 0 2006.161.08:20:10.19#ibcon#about to read 6, iclass 28, count 0 2006.161.08:20:10.19#ibcon#read 6, iclass 28, count 0 2006.161.08:20:10.19#ibcon#end of sib2, iclass 28, count 0 2006.161.08:20:10.19#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:20:10.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:20:10.19#ibcon#[25=USB\r\n] 2006.161.08:20:10.19#ibcon#*before write, iclass 28, count 0 2006.161.08:20:10.19#ibcon#enter sib2, iclass 28, count 0 2006.161.08:20:10.19#ibcon#flushed, iclass 28, count 0 2006.161.08:20:10.19#ibcon#about to write, iclass 28, count 0 2006.161.08:20:10.19#ibcon#wrote, iclass 28, count 0 2006.161.08:20:10.19#ibcon#about to read 3, iclass 28, count 0 2006.161.08:20:10.22#ibcon#read 3, iclass 28, count 0 2006.161.08:20:10.22#ibcon#about to read 4, iclass 28, count 0 2006.161.08:20:10.22#ibcon#read 4, iclass 28, count 0 2006.161.08:20:10.22#ibcon#about to read 5, iclass 28, count 0 2006.161.08:20:10.22#ibcon#read 5, iclass 28, count 0 2006.161.08:20:10.22#ibcon#about to read 6, iclass 28, count 0 2006.161.08:20:10.22#ibcon#read 6, iclass 28, count 0 2006.161.08:20:10.22#ibcon#end of sib2, iclass 28, count 0 2006.161.08:20:10.22#ibcon#*after write, iclass 28, count 0 2006.161.08:20:10.22#ibcon#*before return 0, iclass 28, count 0 2006.161.08:20:10.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:10.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:10.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:20:10.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:20:10.22$vc4f8/valo=3,672.99 2006.161.08:20:10.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:20:10.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:20:10.22#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:10.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:10.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:10.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:10.22#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:20:10.22#ibcon#first serial, iclass 30, count 0 2006.161.08:20:10.22#ibcon#enter sib2, iclass 30, count 0 2006.161.08:20:10.22#ibcon#flushed, iclass 30, count 0 2006.161.08:20:10.22#ibcon#about to write, iclass 30, count 0 2006.161.08:20:10.22#ibcon#wrote, iclass 30, count 0 2006.161.08:20:10.22#ibcon#about to read 3, iclass 30, count 0 2006.161.08:20:10.24#ibcon#read 3, iclass 30, count 0 2006.161.08:20:10.24#ibcon#about to read 4, iclass 30, count 0 2006.161.08:20:10.24#ibcon#read 4, iclass 30, count 0 2006.161.08:20:10.24#ibcon#about to read 5, iclass 30, count 0 2006.161.08:20:10.24#ibcon#read 5, iclass 30, count 0 2006.161.08:20:10.24#ibcon#about to read 6, iclass 30, count 0 2006.161.08:20:10.24#ibcon#read 6, iclass 30, count 0 2006.161.08:20:10.24#ibcon#end of sib2, iclass 30, count 0 2006.161.08:20:10.24#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:20:10.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:20:10.24#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:20:10.24#ibcon#*before write, iclass 30, count 0 2006.161.08:20:10.24#ibcon#enter sib2, iclass 30, count 0 2006.161.08:20:10.24#ibcon#flushed, iclass 30, count 0 2006.161.08:20:10.24#ibcon#about to write, iclass 30, count 0 2006.161.08:20:10.24#ibcon#wrote, iclass 30, count 0 2006.161.08:20:10.24#ibcon#about to read 3, iclass 30, count 0 2006.161.08:20:10.28#ibcon#read 3, iclass 30, count 0 2006.161.08:20:10.28#ibcon#about to read 4, iclass 30, count 0 2006.161.08:20:10.28#ibcon#read 4, iclass 30, count 0 2006.161.08:20:10.28#ibcon#about to read 5, iclass 30, count 0 2006.161.08:20:10.28#ibcon#read 5, iclass 30, count 0 2006.161.08:20:10.28#ibcon#about to read 6, iclass 30, count 0 2006.161.08:20:10.28#ibcon#read 6, iclass 30, count 0 2006.161.08:20:10.28#ibcon#end of sib2, iclass 30, count 0 2006.161.08:20:10.28#ibcon#*after write, iclass 30, count 0 2006.161.08:20:10.28#ibcon#*before return 0, iclass 30, count 0 2006.161.08:20:10.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:10.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:10.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:20:10.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:20:10.28$vc4f8/va=3,6 2006.161.08:20:10.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:20:10.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:20:10.28#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:10.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:10.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:10.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:10.34#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:20:10.34#ibcon#first serial, iclass 32, count 2 2006.161.08:20:10.34#ibcon#enter sib2, iclass 32, count 2 2006.161.08:20:10.34#ibcon#flushed, iclass 32, count 2 2006.161.08:20:10.34#ibcon#about to write, iclass 32, count 2 2006.161.08:20:10.34#ibcon#wrote, iclass 32, count 2 2006.161.08:20:10.34#ibcon#about to read 3, iclass 32, count 2 2006.161.08:20:10.36#ibcon#read 3, iclass 32, count 2 2006.161.08:20:10.36#ibcon#about to read 4, iclass 32, count 2 2006.161.08:20:10.36#ibcon#read 4, iclass 32, count 2 2006.161.08:20:10.36#ibcon#about to read 5, iclass 32, count 2 2006.161.08:20:10.36#ibcon#read 5, iclass 32, count 2 2006.161.08:20:10.36#ibcon#about to read 6, iclass 32, count 2 2006.161.08:20:10.36#ibcon#read 6, iclass 32, count 2 2006.161.08:20:10.36#ibcon#end of sib2, iclass 32, count 2 2006.161.08:20:10.36#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:20:10.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:20:10.36#ibcon#[25=AT03-06\r\n] 2006.161.08:20:10.36#ibcon#*before write, iclass 32, count 2 2006.161.08:20:10.36#ibcon#enter sib2, iclass 32, count 2 2006.161.08:20:10.36#ibcon#flushed, iclass 32, count 2 2006.161.08:20:10.36#ibcon#about to write, iclass 32, count 2 2006.161.08:20:10.36#ibcon#wrote, iclass 32, count 2 2006.161.08:20:10.36#ibcon#about to read 3, iclass 32, count 2 2006.161.08:20:10.39#ibcon#read 3, iclass 32, count 2 2006.161.08:20:10.39#ibcon#about to read 4, iclass 32, count 2 2006.161.08:20:10.39#ibcon#read 4, iclass 32, count 2 2006.161.08:20:10.39#ibcon#about to read 5, iclass 32, count 2 2006.161.08:20:10.39#ibcon#read 5, iclass 32, count 2 2006.161.08:20:10.39#ibcon#about to read 6, iclass 32, count 2 2006.161.08:20:10.39#ibcon#read 6, iclass 32, count 2 2006.161.08:20:10.39#ibcon#end of sib2, iclass 32, count 2 2006.161.08:20:10.39#ibcon#*after write, iclass 32, count 2 2006.161.08:20:10.39#ibcon#*before return 0, iclass 32, count 2 2006.161.08:20:10.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:10.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:10.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:20:10.39#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:10.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:10.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:10.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:10.51#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:20:10.51#ibcon#first serial, iclass 32, count 0 2006.161.08:20:10.51#ibcon#enter sib2, iclass 32, count 0 2006.161.08:20:10.51#ibcon#flushed, iclass 32, count 0 2006.161.08:20:10.51#ibcon#about to write, iclass 32, count 0 2006.161.08:20:10.51#ibcon#wrote, iclass 32, count 0 2006.161.08:20:10.51#ibcon#about to read 3, iclass 32, count 0 2006.161.08:20:10.53#ibcon#read 3, iclass 32, count 0 2006.161.08:20:10.53#ibcon#about to read 4, iclass 32, count 0 2006.161.08:20:10.53#ibcon#read 4, iclass 32, count 0 2006.161.08:20:10.53#ibcon#about to read 5, iclass 32, count 0 2006.161.08:20:10.53#ibcon#read 5, iclass 32, count 0 2006.161.08:20:10.53#ibcon#about to read 6, iclass 32, count 0 2006.161.08:20:10.53#ibcon#read 6, iclass 32, count 0 2006.161.08:20:10.53#ibcon#end of sib2, iclass 32, count 0 2006.161.08:20:10.53#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:20:10.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:20:10.53#ibcon#[25=USB\r\n] 2006.161.08:20:10.53#ibcon#*before write, iclass 32, count 0 2006.161.08:20:10.53#ibcon#enter sib2, iclass 32, count 0 2006.161.08:20:10.53#ibcon#flushed, iclass 32, count 0 2006.161.08:20:10.53#ibcon#about to write, iclass 32, count 0 2006.161.08:20:10.53#ibcon#wrote, iclass 32, count 0 2006.161.08:20:10.53#ibcon#about to read 3, iclass 32, count 0 2006.161.08:20:10.56#ibcon#read 3, iclass 32, count 0 2006.161.08:20:10.56#ibcon#about to read 4, iclass 32, count 0 2006.161.08:20:10.56#ibcon#read 4, iclass 32, count 0 2006.161.08:20:10.56#ibcon#about to read 5, iclass 32, count 0 2006.161.08:20:10.56#ibcon#read 5, iclass 32, count 0 2006.161.08:20:10.56#ibcon#about to read 6, iclass 32, count 0 2006.161.08:20:10.56#ibcon#read 6, iclass 32, count 0 2006.161.08:20:10.56#ibcon#end of sib2, iclass 32, count 0 2006.161.08:20:10.56#ibcon#*after write, iclass 32, count 0 2006.161.08:20:10.56#ibcon#*before return 0, iclass 32, count 0 2006.161.08:20:10.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:10.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:10.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:20:10.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:20:10.56$vc4f8/valo=4,832.99 2006.161.08:20:10.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:20:10.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:20:10.56#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:10.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:10.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:10.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:10.56#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:20:10.56#ibcon#first serial, iclass 34, count 0 2006.161.08:20:10.56#ibcon#enter sib2, iclass 34, count 0 2006.161.08:20:10.56#ibcon#flushed, iclass 34, count 0 2006.161.08:20:10.56#ibcon#about to write, iclass 34, count 0 2006.161.08:20:10.56#ibcon#wrote, iclass 34, count 0 2006.161.08:20:10.56#ibcon#about to read 3, iclass 34, count 0 2006.161.08:20:10.58#ibcon#read 3, iclass 34, count 0 2006.161.08:20:10.58#ibcon#about to read 4, iclass 34, count 0 2006.161.08:20:10.58#ibcon#read 4, iclass 34, count 0 2006.161.08:20:10.58#ibcon#about to read 5, iclass 34, count 0 2006.161.08:20:10.58#ibcon#read 5, iclass 34, count 0 2006.161.08:20:10.58#ibcon#about to read 6, iclass 34, count 0 2006.161.08:20:10.58#ibcon#read 6, iclass 34, count 0 2006.161.08:20:10.58#ibcon#end of sib2, iclass 34, count 0 2006.161.08:20:10.58#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:20:10.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:20:10.58#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:20:10.58#ibcon#*before write, iclass 34, count 0 2006.161.08:20:10.58#ibcon#enter sib2, iclass 34, count 0 2006.161.08:20:10.58#ibcon#flushed, iclass 34, count 0 2006.161.08:20:10.58#ibcon#about to write, iclass 34, count 0 2006.161.08:20:10.58#ibcon#wrote, iclass 34, count 0 2006.161.08:20:10.58#ibcon#about to read 3, iclass 34, count 0 2006.161.08:20:10.62#ibcon#read 3, iclass 34, count 0 2006.161.08:20:10.62#ibcon#about to read 4, iclass 34, count 0 2006.161.08:20:10.62#ibcon#read 4, iclass 34, count 0 2006.161.08:20:10.62#ibcon#about to read 5, iclass 34, count 0 2006.161.08:20:10.62#ibcon#read 5, iclass 34, count 0 2006.161.08:20:10.62#ibcon#about to read 6, iclass 34, count 0 2006.161.08:20:10.62#ibcon#read 6, iclass 34, count 0 2006.161.08:20:10.62#ibcon#end of sib2, iclass 34, count 0 2006.161.08:20:10.62#ibcon#*after write, iclass 34, count 0 2006.161.08:20:10.62#ibcon#*before return 0, iclass 34, count 0 2006.161.08:20:10.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:10.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:10.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:20:10.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:20:10.62$vc4f8/va=4,7 2006.161.08:20:10.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:20:10.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:20:10.62#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:10.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:10.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:10.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:10.68#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:20:10.68#ibcon#first serial, iclass 36, count 2 2006.161.08:20:10.68#ibcon#enter sib2, iclass 36, count 2 2006.161.08:20:10.68#ibcon#flushed, iclass 36, count 2 2006.161.08:20:10.68#ibcon#about to write, iclass 36, count 2 2006.161.08:20:10.68#ibcon#wrote, iclass 36, count 2 2006.161.08:20:10.68#ibcon#about to read 3, iclass 36, count 2 2006.161.08:20:10.70#ibcon#read 3, iclass 36, count 2 2006.161.08:20:10.70#ibcon#about to read 4, iclass 36, count 2 2006.161.08:20:10.70#ibcon#read 4, iclass 36, count 2 2006.161.08:20:10.70#ibcon#about to read 5, iclass 36, count 2 2006.161.08:20:10.70#ibcon#read 5, iclass 36, count 2 2006.161.08:20:10.70#ibcon#about to read 6, iclass 36, count 2 2006.161.08:20:10.70#ibcon#read 6, iclass 36, count 2 2006.161.08:20:10.70#ibcon#end of sib2, iclass 36, count 2 2006.161.08:20:10.70#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:20:10.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:20:10.70#ibcon#[25=AT04-07\r\n] 2006.161.08:20:10.70#ibcon#*before write, iclass 36, count 2 2006.161.08:20:10.70#ibcon#enter sib2, iclass 36, count 2 2006.161.08:20:10.70#ibcon#flushed, iclass 36, count 2 2006.161.08:20:10.70#ibcon#about to write, iclass 36, count 2 2006.161.08:20:10.70#ibcon#wrote, iclass 36, count 2 2006.161.08:20:10.70#ibcon#about to read 3, iclass 36, count 2 2006.161.08:20:10.73#ibcon#read 3, iclass 36, count 2 2006.161.08:20:10.73#ibcon#about to read 4, iclass 36, count 2 2006.161.08:20:10.73#ibcon#read 4, iclass 36, count 2 2006.161.08:20:10.73#ibcon#about to read 5, iclass 36, count 2 2006.161.08:20:10.73#ibcon#read 5, iclass 36, count 2 2006.161.08:20:10.73#ibcon#about to read 6, iclass 36, count 2 2006.161.08:20:10.73#ibcon#read 6, iclass 36, count 2 2006.161.08:20:10.73#ibcon#end of sib2, iclass 36, count 2 2006.161.08:20:10.73#ibcon#*after write, iclass 36, count 2 2006.161.08:20:10.73#ibcon#*before return 0, iclass 36, count 2 2006.161.08:20:10.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:10.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:10.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:20:10.73#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:10.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:10.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:10.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:10.85#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:20:10.85#ibcon#first serial, iclass 36, count 0 2006.161.08:20:10.85#ibcon#enter sib2, iclass 36, count 0 2006.161.08:20:10.85#ibcon#flushed, iclass 36, count 0 2006.161.08:20:10.85#ibcon#about to write, iclass 36, count 0 2006.161.08:20:10.85#ibcon#wrote, iclass 36, count 0 2006.161.08:20:10.85#ibcon#about to read 3, iclass 36, count 0 2006.161.08:20:10.87#ibcon#read 3, iclass 36, count 0 2006.161.08:20:10.87#ibcon#about to read 4, iclass 36, count 0 2006.161.08:20:10.87#ibcon#read 4, iclass 36, count 0 2006.161.08:20:10.87#ibcon#about to read 5, iclass 36, count 0 2006.161.08:20:10.87#ibcon#read 5, iclass 36, count 0 2006.161.08:20:10.87#ibcon#about to read 6, iclass 36, count 0 2006.161.08:20:10.87#ibcon#read 6, iclass 36, count 0 2006.161.08:20:10.87#ibcon#end of sib2, iclass 36, count 0 2006.161.08:20:10.87#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:20:10.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:20:10.87#ibcon#[25=USB\r\n] 2006.161.08:20:10.87#ibcon#*before write, iclass 36, count 0 2006.161.08:20:10.87#ibcon#enter sib2, iclass 36, count 0 2006.161.08:20:10.87#ibcon#flushed, iclass 36, count 0 2006.161.08:20:10.87#ibcon#about to write, iclass 36, count 0 2006.161.08:20:10.87#ibcon#wrote, iclass 36, count 0 2006.161.08:20:10.87#ibcon#about to read 3, iclass 36, count 0 2006.161.08:20:10.90#ibcon#read 3, iclass 36, count 0 2006.161.08:20:10.90#ibcon#about to read 4, iclass 36, count 0 2006.161.08:20:10.90#ibcon#read 4, iclass 36, count 0 2006.161.08:20:10.90#ibcon#about to read 5, iclass 36, count 0 2006.161.08:20:10.90#ibcon#read 5, iclass 36, count 0 2006.161.08:20:10.90#ibcon#about to read 6, iclass 36, count 0 2006.161.08:20:10.90#ibcon#read 6, iclass 36, count 0 2006.161.08:20:10.90#ibcon#end of sib2, iclass 36, count 0 2006.161.08:20:10.90#ibcon#*after write, iclass 36, count 0 2006.161.08:20:10.90#ibcon#*before return 0, iclass 36, count 0 2006.161.08:20:10.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:10.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:10.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:20:10.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:20:10.90$vc4f8/valo=5,652.99 2006.161.08:20:10.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:20:10.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:20:10.90#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:10.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:10.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:10.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:10.90#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:20:10.90#ibcon#first serial, iclass 38, count 0 2006.161.08:20:10.90#ibcon#enter sib2, iclass 38, count 0 2006.161.08:20:10.90#ibcon#flushed, iclass 38, count 0 2006.161.08:20:10.90#ibcon#about to write, iclass 38, count 0 2006.161.08:20:10.90#ibcon#wrote, iclass 38, count 0 2006.161.08:20:10.90#ibcon#about to read 3, iclass 38, count 0 2006.161.08:20:10.92#ibcon#read 3, iclass 38, count 0 2006.161.08:20:10.92#ibcon#about to read 4, iclass 38, count 0 2006.161.08:20:10.92#ibcon#read 4, iclass 38, count 0 2006.161.08:20:10.92#ibcon#about to read 5, iclass 38, count 0 2006.161.08:20:10.92#ibcon#read 5, iclass 38, count 0 2006.161.08:20:10.92#ibcon#about to read 6, iclass 38, count 0 2006.161.08:20:10.92#ibcon#read 6, iclass 38, count 0 2006.161.08:20:10.92#ibcon#end of sib2, iclass 38, count 0 2006.161.08:20:10.92#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:20:10.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:20:10.92#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:20:10.92#ibcon#*before write, iclass 38, count 0 2006.161.08:20:10.92#ibcon#enter sib2, iclass 38, count 0 2006.161.08:20:10.92#ibcon#flushed, iclass 38, count 0 2006.161.08:20:10.92#ibcon#about to write, iclass 38, count 0 2006.161.08:20:10.92#ibcon#wrote, iclass 38, count 0 2006.161.08:20:10.92#ibcon#about to read 3, iclass 38, count 0 2006.161.08:20:10.96#ibcon#read 3, iclass 38, count 0 2006.161.08:20:10.96#ibcon#about to read 4, iclass 38, count 0 2006.161.08:20:10.96#ibcon#read 4, iclass 38, count 0 2006.161.08:20:10.96#ibcon#about to read 5, iclass 38, count 0 2006.161.08:20:10.96#ibcon#read 5, iclass 38, count 0 2006.161.08:20:10.96#ibcon#about to read 6, iclass 38, count 0 2006.161.08:20:10.96#ibcon#read 6, iclass 38, count 0 2006.161.08:20:10.96#ibcon#end of sib2, iclass 38, count 0 2006.161.08:20:10.96#ibcon#*after write, iclass 38, count 0 2006.161.08:20:10.96#ibcon#*before return 0, iclass 38, count 0 2006.161.08:20:10.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:10.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:10.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:20:10.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:20:10.96$vc4f8/va=5,7 2006.161.08:20:10.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:20:10.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:20:10.96#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:10.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:11.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:11.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:11.02#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:20:11.02#ibcon#first serial, iclass 40, count 2 2006.161.08:20:11.02#ibcon#enter sib2, iclass 40, count 2 2006.161.08:20:11.02#ibcon#flushed, iclass 40, count 2 2006.161.08:20:11.02#ibcon#about to write, iclass 40, count 2 2006.161.08:20:11.02#ibcon#wrote, iclass 40, count 2 2006.161.08:20:11.02#ibcon#about to read 3, iclass 40, count 2 2006.161.08:20:11.04#ibcon#read 3, iclass 40, count 2 2006.161.08:20:11.04#ibcon#about to read 4, iclass 40, count 2 2006.161.08:20:11.04#ibcon#read 4, iclass 40, count 2 2006.161.08:20:11.04#ibcon#about to read 5, iclass 40, count 2 2006.161.08:20:11.04#ibcon#read 5, iclass 40, count 2 2006.161.08:20:11.04#ibcon#about to read 6, iclass 40, count 2 2006.161.08:20:11.04#ibcon#read 6, iclass 40, count 2 2006.161.08:20:11.04#ibcon#end of sib2, iclass 40, count 2 2006.161.08:20:11.04#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:20:11.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:20:11.04#ibcon#[25=AT05-07\r\n] 2006.161.08:20:11.04#ibcon#*before write, iclass 40, count 2 2006.161.08:20:11.04#ibcon#enter sib2, iclass 40, count 2 2006.161.08:20:11.04#ibcon#flushed, iclass 40, count 2 2006.161.08:20:11.04#ibcon#about to write, iclass 40, count 2 2006.161.08:20:11.04#ibcon#wrote, iclass 40, count 2 2006.161.08:20:11.04#ibcon#about to read 3, iclass 40, count 2 2006.161.08:20:11.07#ibcon#read 3, iclass 40, count 2 2006.161.08:20:11.07#ibcon#about to read 4, iclass 40, count 2 2006.161.08:20:11.07#ibcon#read 4, iclass 40, count 2 2006.161.08:20:11.07#ibcon#about to read 5, iclass 40, count 2 2006.161.08:20:11.07#ibcon#read 5, iclass 40, count 2 2006.161.08:20:11.07#ibcon#about to read 6, iclass 40, count 2 2006.161.08:20:11.07#ibcon#read 6, iclass 40, count 2 2006.161.08:20:11.07#ibcon#end of sib2, iclass 40, count 2 2006.161.08:20:11.07#ibcon#*after write, iclass 40, count 2 2006.161.08:20:11.07#ibcon#*before return 0, iclass 40, count 2 2006.161.08:20:11.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:11.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:11.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:20:11.07#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:11.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:11.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:11.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:11.19#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:20:11.19#ibcon#first serial, iclass 40, count 0 2006.161.08:20:11.19#ibcon#enter sib2, iclass 40, count 0 2006.161.08:20:11.19#ibcon#flushed, iclass 40, count 0 2006.161.08:20:11.19#ibcon#about to write, iclass 40, count 0 2006.161.08:20:11.19#ibcon#wrote, iclass 40, count 0 2006.161.08:20:11.19#ibcon#about to read 3, iclass 40, count 0 2006.161.08:20:11.21#ibcon#read 3, iclass 40, count 0 2006.161.08:20:11.21#ibcon#about to read 4, iclass 40, count 0 2006.161.08:20:11.21#ibcon#read 4, iclass 40, count 0 2006.161.08:20:11.21#ibcon#about to read 5, iclass 40, count 0 2006.161.08:20:11.21#ibcon#read 5, iclass 40, count 0 2006.161.08:20:11.21#ibcon#about to read 6, iclass 40, count 0 2006.161.08:20:11.21#ibcon#read 6, iclass 40, count 0 2006.161.08:20:11.21#ibcon#end of sib2, iclass 40, count 0 2006.161.08:20:11.21#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:20:11.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:20:11.21#ibcon#[25=USB\r\n] 2006.161.08:20:11.21#ibcon#*before write, iclass 40, count 0 2006.161.08:20:11.21#ibcon#enter sib2, iclass 40, count 0 2006.161.08:20:11.21#ibcon#flushed, iclass 40, count 0 2006.161.08:20:11.21#ibcon#about to write, iclass 40, count 0 2006.161.08:20:11.21#ibcon#wrote, iclass 40, count 0 2006.161.08:20:11.21#ibcon#about to read 3, iclass 40, count 0 2006.161.08:20:11.24#ibcon#read 3, iclass 40, count 0 2006.161.08:20:11.24#ibcon#about to read 4, iclass 40, count 0 2006.161.08:20:11.24#ibcon#read 4, iclass 40, count 0 2006.161.08:20:11.24#ibcon#about to read 5, iclass 40, count 0 2006.161.08:20:11.24#ibcon#read 5, iclass 40, count 0 2006.161.08:20:11.24#ibcon#about to read 6, iclass 40, count 0 2006.161.08:20:11.24#ibcon#read 6, iclass 40, count 0 2006.161.08:20:11.24#ibcon#end of sib2, iclass 40, count 0 2006.161.08:20:11.24#ibcon#*after write, iclass 40, count 0 2006.161.08:20:11.24#ibcon#*before return 0, iclass 40, count 0 2006.161.08:20:11.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:11.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:11.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:20:11.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:20:11.24$vc4f8/valo=6,772.99 2006.161.08:20:11.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:20:11.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:20:11.24#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:11.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:11.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:11.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:11.24#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:20:11.24#ibcon#first serial, iclass 4, count 0 2006.161.08:20:11.24#ibcon#enter sib2, iclass 4, count 0 2006.161.08:20:11.24#ibcon#flushed, iclass 4, count 0 2006.161.08:20:11.24#ibcon#about to write, iclass 4, count 0 2006.161.08:20:11.24#ibcon#wrote, iclass 4, count 0 2006.161.08:20:11.24#ibcon#about to read 3, iclass 4, count 0 2006.161.08:20:11.26#ibcon#read 3, iclass 4, count 0 2006.161.08:20:11.26#ibcon#about to read 4, iclass 4, count 0 2006.161.08:20:11.26#ibcon#read 4, iclass 4, count 0 2006.161.08:20:11.26#ibcon#about to read 5, iclass 4, count 0 2006.161.08:20:11.26#ibcon#read 5, iclass 4, count 0 2006.161.08:20:11.26#ibcon#about to read 6, iclass 4, count 0 2006.161.08:20:11.26#ibcon#read 6, iclass 4, count 0 2006.161.08:20:11.26#ibcon#end of sib2, iclass 4, count 0 2006.161.08:20:11.26#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:20:11.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:20:11.26#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:20:11.26#ibcon#*before write, iclass 4, count 0 2006.161.08:20:11.26#ibcon#enter sib2, iclass 4, count 0 2006.161.08:20:11.26#ibcon#flushed, iclass 4, count 0 2006.161.08:20:11.26#ibcon#about to write, iclass 4, count 0 2006.161.08:20:11.26#ibcon#wrote, iclass 4, count 0 2006.161.08:20:11.26#ibcon#about to read 3, iclass 4, count 0 2006.161.08:20:11.30#ibcon#read 3, iclass 4, count 0 2006.161.08:20:11.30#ibcon#about to read 4, iclass 4, count 0 2006.161.08:20:11.30#ibcon#read 4, iclass 4, count 0 2006.161.08:20:11.30#ibcon#about to read 5, iclass 4, count 0 2006.161.08:20:11.30#ibcon#read 5, iclass 4, count 0 2006.161.08:20:11.30#ibcon#about to read 6, iclass 4, count 0 2006.161.08:20:11.30#ibcon#read 6, iclass 4, count 0 2006.161.08:20:11.30#ibcon#end of sib2, iclass 4, count 0 2006.161.08:20:11.30#ibcon#*after write, iclass 4, count 0 2006.161.08:20:11.30#ibcon#*before return 0, iclass 4, count 0 2006.161.08:20:11.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:11.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:11.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:20:11.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:20:11.30$vc4f8/va=6,6 2006.161.08:20:11.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:20:11.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:20:11.30#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:11.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:11.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:11.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:11.36#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:20:11.36#ibcon#first serial, iclass 6, count 2 2006.161.08:20:11.36#ibcon#enter sib2, iclass 6, count 2 2006.161.08:20:11.36#ibcon#flushed, iclass 6, count 2 2006.161.08:20:11.36#ibcon#about to write, iclass 6, count 2 2006.161.08:20:11.36#ibcon#wrote, iclass 6, count 2 2006.161.08:20:11.36#ibcon#about to read 3, iclass 6, count 2 2006.161.08:20:11.38#ibcon#read 3, iclass 6, count 2 2006.161.08:20:11.38#ibcon#about to read 4, iclass 6, count 2 2006.161.08:20:11.38#ibcon#read 4, iclass 6, count 2 2006.161.08:20:11.38#ibcon#about to read 5, iclass 6, count 2 2006.161.08:20:11.38#ibcon#read 5, iclass 6, count 2 2006.161.08:20:11.38#ibcon#about to read 6, iclass 6, count 2 2006.161.08:20:11.38#ibcon#read 6, iclass 6, count 2 2006.161.08:20:11.38#ibcon#end of sib2, iclass 6, count 2 2006.161.08:20:11.38#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:20:11.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:20:11.38#ibcon#[25=AT06-06\r\n] 2006.161.08:20:11.38#ibcon#*before write, iclass 6, count 2 2006.161.08:20:11.38#ibcon#enter sib2, iclass 6, count 2 2006.161.08:20:11.38#ibcon#flushed, iclass 6, count 2 2006.161.08:20:11.38#ibcon#about to write, iclass 6, count 2 2006.161.08:20:11.38#ibcon#wrote, iclass 6, count 2 2006.161.08:20:11.38#ibcon#about to read 3, iclass 6, count 2 2006.161.08:20:11.41#ibcon#read 3, iclass 6, count 2 2006.161.08:20:11.41#ibcon#about to read 4, iclass 6, count 2 2006.161.08:20:11.41#ibcon#read 4, iclass 6, count 2 2006.161.08:20:11.41#ibcon#about to read 5, iclass 6, count 2 2006.161.08:20:11.41#ibcon#read 5, iclass 6, count 2 2006.161.08:20:11.41#ibcon#about to read 6, iclass 6, count 2 2006.161.08:20:11.41#ibcon#read 6, iclass 6, count 2 2006.161.08:20:11.41#ibcon#end of sib2, iclass 6, count 2 2006.161.08:20:11.41#ibcon#*after write, iclass 6, count 2 2006.161.08:20:11.41#ibcon#*before return 0, iclass 6, count 2 2006.161.08:20:11.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:11.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:11.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:20:11.41#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:11.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:20:11.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:20:11.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:20:11.53#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:20:11.53#ibcon#first serial, iclass 6, count 0 2006.161.08:20:11.53#ibcon#enter sib2, iclass 6, count 0 2006.161.08:20:11.53#ibcon#flushed, iclass 6, count 0 2006.161.08:20:11.53#ibcon#about to write, iclass 6, count 0 2006.161.08:20:11.53#ibcon#wrote, iclass 6, count 0 2006.161.08:20:11.53#ibcon#about to read 3, iclass 6, count 0 2006.161.08:20:11.55#ibcon#read 3, iclass 6, count 0 2006.161.08:20:11.55#ibcon#about to read 4, iclass 6, count 0 2006.161.08:20:11.55#ibcon#read 4, iclass 6, count 0 2006.161.08:20:11.55#ibcon#about to read 5, iclass 6, count 0 2006.161.08:20:11.55#ibcon#read 5, iclass 6, count 0 2006.161.08:20:11.55#ibcon#about to read 6, iclass 6, count 0 2006.161.08:20:11.55#ibcon#read 6, iclass 6, count 0 2006.161.08:20:11.55#ibcon#end of sib2, iclass 6, count 0 2006.161.08:20:11.55#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:20:11.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:20:11.55#ibcon#[25=USB\r\n] 2006.161.08:20:11.55#ibcon#*before write, iclass 6, count 0 2006.161.08:20:11.55#ibcon#enter sib2, iclass 6, count 0 2006.161.08:20:11.55#ibcon#flushed, iclass 6, count 0 2006.161.08:20:11.55#ibcon#about to write, iclass 6, count 0 2006.161.08:20:11.55#ibcon#wrote, iclass 6, count 0 2006.161.08:20:11.55#ibcon#about to read 3, iclass 6, count 0 2006.161.08:20:11.58#ibcon#read 3, iclass 6, count 0 2006.161.08:20:11.58#ibcon#about to read 4, iclass 6, count 0 2006.161.08:20:11.58#ibcon#read 4, iclass 6, count 0 2006.161.08:20:11.58#ibcon#about to read 5, iclass 6, count 0 2006.161.08:20:11.58#ibcon#read 5, iclass 6, count 0 2006.161.08:20:11.58#ibcon#about to read 6, iclass 6, count 0 2006.161.08:20:11.58#ibcon#read 6, iclass 6, count 0 2006.161.08:20:11.58#ibcon#end of sib2, iclass 6, count 0 2006.161.08:20:11.58#ibcon#*after write, iclass 6, count 0 2006.161.08:20:11.58#ibcon#*before return 0, iclass 6, count 0 2006.161.08:20:11.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:20:11.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:20:11.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:20:11.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:20:11.58$vc4f8/valo=7,832.99 2006.161.08:20:11.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:20:11.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:20:11.58#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:11.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:20:11.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:20:11.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:20:11.58#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:20:11.58#ibcon#first serial, iclass 10, count 0 2006.161.08:20:11.58#ibcon#enter sib2, iclass 10, count 0 2006.161.08:20:11.58#ibcon#flushed, iclass 10, count 0 2006.161.08:20:11.58#ibcon#about to write, iclass 10, count 0 2006.161.08:20:11.58#ibcon#wrote, iclass 10, count 0 2006.161.08:20:11.58#ibcon#about to read 3, iclass 10, count 0 2006.161.08:20:11.60#ibcon#read 3, iclass 10, count 0 2006.161.08:20:11.60#ibcon#about to read 4, iclass 10, count 0 2006.161.08:20:11.60#ibcon#read 4, iclass 10, count 0 2006.161.08:20:11.60#ibcon#about to read 5, iclass 10, count 0 2006.161.08:20:11.60#ibcon#read 5, iclass 10, count 0 2006.161.08:20:11.60#ibcon#about to read 6, iclass 10, count 0 2006.161.08:20:11.60#ibcon#read 6, iclass 10, count 0 2006.161.08:20:11.60#ibcon#end of sib2, iclass 10, count 0 2006.161.08:20:11.60#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:20:11.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:20:11.60#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:20:11.60#ibcon#*before write, iclass 10, count 0 2006.161.08:20:11.60#ibcon#enter sib2, iclass 10, count 0 2006.161.08:20:11.60#ibcon#flushed, iclass 10, count 0 2006.161.08:20:11.60#ibcon#about to write, iclass 10, count 0 2006.161.08:20:11.60#ibcon#wrote, iclass 10, count 0 2006.161.08:20:11.60#ibcon#about to read 3, iclass 10, count 0 2006.161.08:20:11.64#ibcon#read 3, iclass 10, count 0 2006.161.08:20:11.64#ibcon#about to read 4, iclass 10, count 0 2006.161.08:20:11.64#ibcon#read 4, iclass 10, count 0 2006.161.08:20:11.64#ibcon#about to read 5, iclass 10, count 0 2006.161.08:20:11.64#ibcon#read 5, iclass 10, count 0 2006.161.08:20:11.64#ibcon#about to read 6, iclass 10, count 0 2006.161.08:20:11.64#ibcon#read 6, iclass 10, count 0 2006.161.08:20:11.64#ibcon#end of sib2, iclass 10, count 0 2006.161.08:20:11.64#ibcon#*after write, iclass 10, count 0 2006.161.08:20:11.64#ibcon#*before return 0, iclass 10, count 0 2006.161.08:20:11.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:20:11.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:20:11.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:20:11.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:20:11.64$vc4f8/va=7,6 2006.161.08:20:11.64#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.08:20:11.64#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.08:20:11.64#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:11.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:20:11.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:20:11.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:20:11.70#ibcon#enter wrdev, iclass 12, count 2 2006.161.08:20:11.70#ibcon#first serial, iclass 12, count 2 2006.161.08:20:11.70#ibcon#enter sib2, iclass 12, count 2 2006.161.08:20:11.70#ibcon#flushed, iclass 12, count 2 2006.161.08:20:11.70#ibcon#about to write, iclass 12, count 2 2006.161.08:20:11.70#ibcon#wrote, iclass 12, count 2 2006.161.08:20:11.70#ibcon#about to read 3, iclass 12, count 2 2006.161.08:20:11.72#ibcon#read 3, iclass 12, count 2 2006.161.08:20:11.72#ibcon#about to read 4, iclass 12, count 2 2006.161.08:20:11.72#ibcon#read 4, iclass 12, count 2 2006.161.08:20:11.72#ibcon#about to read 5, iclass 12, count 2 2006.161.08:20:11.72#ibcon#read 5, iclass 12, count 2 2006.161.08:20:11.72#ibcon#about to read 6, iclass 12, count 2 2006.161.08:20:11.72#ibcon#read 6, iclass 12, count 2 2006.161.08:20:11.72#ibcon#end of sib2, iclass 12, count 2 2006.161.08:20:11.72#ibcon#*mode == 0, iclass 12, count 2 2006.161.08:20:11.72#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.08:20:11.72#ibcon#[25=AT07-06\r\n] 2006.161.08:20:11.72#ibcon#*before write, iclass 12, count 2 2006.161.08:20:11.72#ibcon#enter sib2, iclass 12, count 2 2006.161.08:20:11.72#ibcon#flushed, iclass 12, count 2 2006.161.08:20:11.72#ibcon#about to write, iclass 12, count 2 2006.161.08:20:11.72#ibcon#wrote, iclass 12, count 2 2006.161.08:20:11.72#ibcon#about to read 3, iclass 12, count 2 2006.161.08:20:11.75#ibcon#read 3, iclass 12, count 2 2006.161.08:20:11.75#ibcon#about to read 4, iclass 12, count 2 2006.161.08:20:11.75#ibcon#read 4, iclass 12, count 2 2006.161.08:20:11.75#ibcon#about to read 5, iclass 12, count 2 2006.161.08:20:11.75#ibcon#read 5, iclass 12, count 2 2006.161.08:20:11.75#ibcon#about to read 6, iclass 12, count 2 2006.161.08:20:11.75#ibcon#read 6, iclass 12, count 2 2006.161.08:20:11.75#ibcon#end of sib2, iclass 12, count 2 2006.161.08:20:11.75#ibcon#*after write, iclass 12, count 2 2006.161.08:20:11.75#ibcon#*before return 0, iclass 12, count 2 2006.161.08:20:11.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:20:11.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:20:11.75#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.08:20:11.75#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:11.75#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:20:11.87#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:20:11.87#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:20:11.87#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:20:11.87#ibcon#first serial, iclass 12, count 0 2006.161.08:20:11.87#ibcon#enter sib2, iclass 12, count 0 2006.161.08:20:11.87#ibcon#flushed, iclass 12, count 0 2006.161.08:20:11.87#ibcon#about to write, iclass 12, count 0 2006.161.08:20:11.87#ibcon#wrote, iclass 12, count 0 2006.161.08:20:11.87#ibcon#about to read 3, iclass 12, count 0 2006.161.08:20:11.89#ibcon#read 3, iclass 12, count 0 2006.161.08:20:11.89#ibcon#about to read 4, iclass 12, count 0 2006.161.08:20:11.89#ibcon#read 4, iclass 12, count 0 2006.161.08:20:11.89#ibcon#about to read 5, iclass 12, count 0 2006.161.08:20:11.89#ibcon#read 5, iclass 12, count 0 2006.161.08:20:11.89#ibcon#about to read 6, iclass 12, count 0 2006.161.08:20:11.89#ibcon#read 6, iclass 12, count 0 2006.161.08:20:11.89#ibcon#end of sib2, iclass 12, count 0 2006.161.08:20:11.89#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:20:11.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:20:11.89#ibcon#[25=USB\r\n] 2006.161.08:20:11.89#ibcon#*before write, iclass 12, count 0 2006.161.08:20:11.89#ibcon#enter sib2, iclass 12, count 0 2006.161.08:20:11.89#ibcon#flushed, iclass 12, count 0 2006.161.08:20:11.89#ibcon#about to write, iclass 12, count 0 2006.161.08:20:11.89#ibcon#wrote, iclass 12, count 0 2006.161.08:20:11.89#ibcon#about to read 3, iclass 12, count 0 2006.161.08:20:11.92#ibcon#read 3, iclass 12, count 0 2006.161.08:20:11.92#ibcon#about to read 4, iclass 12, count 0 2006.161.08:20:11.92#ibcon#read 4, iclass 12, count 0 2006.161.08:20:11.92#ibcon#about to read 5, iclass 12, count 0 2006.161.08:20:11.92#ibcon#read 5, iclass 12, count 0 2006.161.08:20:11.92#ibcon#about to read 6, iclass 12, count 0 2006.161.08:20:11.92#ibcon#read 6, iclass 12, count 0 2006.161.08:20:11.92#ibcon#end of sib2, iclass 12, count 0 2006.161.08:20:11.92#ibcon#*after write, iclass 12, count 0 2006.161.08:20:11.92#ibcon#*before return 0, iclass 12, count 0 2006.161.08:20:11.92#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:20:11.92#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:20:11.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:20:11.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:20:11.92$vc4f8/valo=8,852.99 2006.161.08:20:11.92#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:20:11.92#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:20:11.92#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:11.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:20:11.92#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:20:11.92#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:20:11.92#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:20:11.92#ibcon#first serial, iclass 14, count 0 2006.161.08:20:11.92#ibcon#enter sib2, iclass 14, count 0 2006.161.08:20:11.92#ibcon#flushed, iclass 14, count 0 2006.161.08:20:11.92#ibcon#about to write, iclass 14, count 0 2006.161.08:20:11.92#ibcon#wrote, iclass 14, count 0 2006.161.08:20:11.92#ibcon#about to read 3, iclass 14, count 0 2006.161.08:20:11.94#ibcon#read 3, iclass 14, count 0 2006.161.08:20:11.94#ibcon#about to read 4, iclass 14, count 0 2006.161.08:20:11.94#ibcon#read 4, iclass 14, count 0 2006.161.08:20:11.94#ibcon#about to read 5, iclass 14, count 0 2006.161.08:20:11.94#ibcon#read 5, iclass 14, count 0 2006.161.08:20:11.94#ibcon#about to read 6, iclass 14, count 0 2006.161.08:20:11.94#ibcon#read 6, iclass 14, count 0 2006.161.08:20:11.94#ibcon#end of sib2, iclass 14, count 0 2006.161.08:20:11.94#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:20:11.94#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:20:11.94#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:20:11.94#ibcon#*before write, iclass 14, count 0 2006.161.08:20:11.94#ibcon#enter sib2, iclass 14, count 0 2006.161.08:20:11.94#ibcon#flushed, iclass 14, count 0 2006.161.08:20:11.94#ibcon#about to write, iclass 14, count 0 2006.161.08:20:11.94#ibcon#wrote, iclass 14, count 0 2006.161.08:20:11.94#ibcon#about to read 3, iclass 14, count 0 2006.161.08:20:11.98#ibcon#read 3, iclass 14, count 0 2006.161.08:20:11.98#ibcon#about to read 4, iclass 14, count 0 2006.161.08:20:11.98#ibcon#read 4, iclass 14, count 0 2006.161.08:20:11.98#ibcon#about to read 5, iclass 14, count 0 2006.161.08:20:11.98#ibcon#read 5, iclass 14, count 0 2006.161.08:20:11.98#ibcon#about to read 6, iclass 14, count 0 2006.161.08:20:11.98#ibcon#read 6, iclass 14, count 0 2006.161.08:20:11.98#ibcon#end of sib2, iclass 14, count 0 2006.161.08:20:11.98#ibcon#*after write, iclass 14, count 0 2006.161.08:20:11.98#ibcon#*before return 0, iclass 14, count 0 2006.161.08:20:11.98#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:20:11.98#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:20:11.98#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:20:11.98#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:20:11.98$vc4f8/va=8,7 2006.161.08:20:11.98#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.08:20:11.98#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.08:20:11.98#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:11.98#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:20:12.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:20:12.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:20:12.04#ibcon#enter wrdev, iclass 16, count 2 2006.161.08:20:12.04#ibcon#first serial, iclass 16, count 2 2006.161.08:20:12.04#ibcon#enter sib2, iclass 16, count 2 2006.161.08:20:12.04#ibcon#flushed, iclass 16, count 2 2006.161.08:20:12.04#ibcon#about to write, iclass 16, count 2 2006.161.08:20:12.04#ibcon#wrote, iclass 16, count 2 2006.161.08:20:12.04#ibcon#about to read 3, iclass 16, count 2 2006.161.08:20:12.06#ibcon#read 3, iclass 16, count 2 2006.161.08:20:12.06#ibcon#about to read 4, iclass 16, count 2 2006.161.08:20:12.06#ibcon#read 4, iclass 16, count 2 2006.161.08:20:12.06#ibcon#about to read 5, iclass 16, count 2 2006.161.08:20:12.06#ibcon#read 5, iclass 16, count 2 2006.161.08:20:12.06#ibcon#about to read 6, iclass 16, count 2 2006.161.08:20:12.06#ibcon#read 6, iclass 16, count 2 2006.161.08:20:12.06#ibcon#end of sib2, iclass 16, count 2 2006.161.08:20:12.06#ibcon#*mode == 0, iclass 16, count 2 2006.161.08:20:12.06#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.08:20:12.06#ibcon#[25=AT08-07\r\n] 2006.161.08:20:12.06#ibcon#*before write, iclass 16, count 2 2006.161.08:20:12.06#ibcon#enter sib2, iclass 16, count 2 2006.161.08:20:12.06#ibcon#flushed, iclass 16, count 2 2006.161.08:20:12.06#ibcon#about to write, iclass 16, count 2 2006.161.08:20:12.06#ibcon#wrote, iclass 16, count 2 2006.161.08:20:12.06#ibcon#about to read 3, iclass 16, count 2 2006.161.08:20:12.09#ibcon#read 3, iclass 16, count 2 2006.161.08:20:12.09#ibcon#about to read 4, iclass 16, count 2 2006.161.08:20:12.09#ibcon#read 4, iclass 16, count 2 2006.161.08:20:12.09#ibcon#about to read 5, iclass 16, count 2 2006.161.08:20:12.09#ibcon#read 5, iclass 16, count 2 2006.161.08:20:12.09#ibcon#about to read 6, iclass 16, count 2 2006.161.08:20:12.09#ibcon#read 6, iclass 16, count 2 2006.161.08:20:12.09#ibcon#end of sib2, iclass 16, count 2 2006.161.08:20:12.09#ibcon#*after write, iclass 16, count 2 2006.161.08:20:12.09#ibcon#*before return 0, iclass 16, count 2 2006.161.08:20:12.09#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:20:12.09#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:20:12.09#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.08:20:12.09#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:12.09#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:20:12.21#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:20:12.21#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:20:12.21#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:20:12.21#ibcon#first serial, iclass 16, count 0 2006.161.08:20:12.21#ibcon#enter sib2, iclass 16, count 0 2006.161.08:20:12.21#ibcon#flushed, iclass 16, count 0 2006.161.08:20:12.21#ibcon#about to write, iclass 16, count 0 2006.161.08:20:12.21#ibcon#wrote, iclass 16, count 0 2006.161.08:20:12.21#ibcon#about to read 3, iclass 16, count 0 2006.161.08:20:12.23#ibcon#read 3, iclass 16, count 0 2006.161.08:20:12.23#ibcon#about to read 4, iclass 16, count 0 2006.161.08:20:12.23#ibcon#read 4, iclass 16, count 0 2006.161.08:20:12.23#ibcon#about to read 5, iclass 16, count 0 2006.161.08:20:12.23#ibcon#read 5, iclass 16, count 0 2006.161.08:20:12.23#ibcon#about to read 6, iclass 16, count 0 2006.161.08:20:12.23#ibcon#read 6, iclass 16, count 0 2006.161.08:20:12.23#ibcon#end of sib2, iclass 16, count 0 2006.161.08:20:12.23#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:20:12.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:20:12.23#ibcon#[25=USB\r\n] 2006.161.08:20:12.23#ibcon#*before write, iclass 16, count 0 2006.161.08:20:12.23#ibcon#enter sib2, iclass 16, count 0 2006.161.08:20:12.23#ibcon#flushed, iclass 16, count 0 2006.161.08:20:12.23#ibcon#about to write, iclass 16, count 0 2006.161.08:20:12.23#ibcon#wrote, iclass 16, count 0 2006.161.08:20:12.23#ibcon#about to read 3, iclass 16, count 0 2006.161.08:20:12.26#ibcon#read 3, iclass 16, count 0 2006.161.08:20:12.26#ibcon#about to read 4, iclass 16, count 0 2006.161.08:20:12.26#ibcon#read 4, iclass 16, count 0 2006.161.08:20:12.26#ibcon#about to read 5, iclass 16, count 0 2006.161.08:20:12.26#ibcon#read 5, iclass 16, count 0 2006.161.08:20:12.26#ibcon#about to read 6, iclass 16, count 0 2006.161.08:20:12.26#ibcon#read 6, iclass 16, count 0 2006.161.08:20:12.26#ibcon#end of sib2, iclass 16, count 0 2006.161.08:20:12.26#ibcon#*after write, iclass 16, count 0 2006.161.08:20:12.26#ibcon#*before return 0, iclass 16, count 0 2006.161.08:20:12.26#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:20:12.26#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:20:12.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:20:12.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:20:12.26$vc4f8/vblo=1,632.99 2006.161.08:20:12.26#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.08:20:12.26#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.08:20:12.26#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:12.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:20:12.26#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:20:12.26#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:20:12.26#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:20:12.26#ibcon#first serial, iclass 18, count 0 2006.161.08:20:12.26#ibcon#enter sib2, iclass 18, count 0 2006.161.08:20:12.26#ibcon#flushed, iclass 18, count 0 2006.161.08:20:12.26#ibcon#about to write, iclass 18, count 0 2006.161.08:20:12.26#ibcon#wrote, iclass 18, count 0 2006.161.08:20:12.26#ibcon#about to read 3, iclass 18, count 0 2006.161.08:20:12.28#ibcon#read 3, iclass 18, count 0 2006.161.08:20:12.28#ibcon#about to read 4, iclass 18, count 0 2006.161.08:20:12.28#ibcon#read 4, iclass 18, count 0 2006.161.08:20:12.28#ibcon#about to read 5, iclass 18, count 0 2006.161.08:20:12.28#ibcon#read 5, iclass 18, count 0 2006.161.08:20:12.28#ibcon#about to read 6, iclass 18, count 0 2006.161.08:20:12.28#ibcon#read 6, iclass 18, count 0 2006.161.08:20:12.28#ibcon#end of sib2, iclass 18, count 0 2006.161.08:20:12.28#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:20:12.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:20:12.28#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:20:12.28#ibcon#*before write, iclass 18, count 0 2006.161.08:20:12.28#ibcon#enter sib2, iclass 18, count 0 2006.161.08:20:12.28#ibcon#flushed, iclass 18, count 0 2006.161.08:20:12.28#ibcon#about to write, iclass 18, count 0 2006.161.08:20:12.28#ibcon#wrote, iclass 18, count 0 2006.161.08:20:12.28#ibcon#about to read 3, iclass 18, count 0 2006.161.08:20:12.32#ibcon#read 3, iclass 18, count 0 2006.161.08:20:12.32#ibcon#about to read 4, iclass 18, count 0 2006.161.08:20:12.32#ibcon#read 4, iclass 18, count 0 2006.161.08:20:12.32#ibcon#about to read 5, iclass 18, count 0 2006.161.08:20:12.32#ibcon#read 5, iclass 18, count 0 2006.161.08:20:12.32#ibcon#about to read 6, iclass 18, count 0 2006.161.08:20:12.32#ibcon#read 6, iclass 18, count 0 2006.161.08:20:12.32#ibcon#end of sib2, iclass 18, count 0 2006.161.08:20:12.32#ibcon#*after write, iclass 18, count 0 2006.161.08:20:12.32#ibcon#*before return 0, iclass 18, count 0 2006.161.08:20:12.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:20:12.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:20:12.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:20:12.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:20:12.32$vc4f8/vb=1,4 2006.161.08:20:12.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.08:20:12.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.08:20:12.32#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:12.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:20:12.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:20:12.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:20:12.32#ibcon#enter wrdev, iclass 20, count 2 2006.161.08:20:12.32#ibcon#first serial, iclass 20, count 2 2006.161.08:20:12.32#ibcon#enter sib2, iclass 20, count 2 2006.161.08:20:12.32#ibcon#flushed, iclass 20, count 2 2006.161.08:20:12.32#ibcon#about to write, iclass 20, count 2 2006.161.08:20:12.32#ibcon#wrote, iclass 20, count 2 2006.161.08:20:12.32#ibcon#about to read 3, iclass 20, count 2 2006.161.08:20:12.34#ibcon#read 3, iclass 20, count 2 2006.161.08:20:12.34#ibcon#about to read 4, iclass 20, count 2 2006.161.08:20:12.34#ibcon#read 4, iclass 20, count 2 2006.161.08:20:12.34#ibcon#about to read 5, iclass 20, count 2 2006.161.08:20:12.34#ibcon#read 5, iclass 20, count 2 2006.161.08:20:12.34#ibcon#about to read 6, iclass 20, count 2 2006.161.08:20:12.34#ibcon#read 6, iclass 20, count 2 2006.161.08:20:12.34#ibcon#end of sib2, iclass 20, count 2 2006.161.08:20:12.34#ibcon#*mode == 0, iclass 20, count 2 2006.161.08:20:12.34#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.08:20:12.34#ibcon#[27=AT01-04\r\n] 2006.161.08:20:12.34#ibcon#*before write, iclass 20, count 2 2006.161.08:20:12.34#ibcon#enter sib2, iclass 20, count 2 2006.161.08:20:12.34#ibcon#flushed, iclass 20, count 2 2006.161.08:20:12.34#ibcon#about to write, iclass 20, count 2 2006.161.08:20:12.34#ibcon#wrote, iclass 20, count 2 2006.161.08:20:12.34#ibcon#about to read 3, iclass 20, count 2 2006.161.08:20:12.37#ibcon#read 3, iclass 20, count 2 2006.161.08:20:12.37#ibcon#about to read 4, iclass 20, count 2 2006.161.08:20:12.37#ibcon#read 4, iclass 20, count 2 2006.161.08:20:12.37#ibcon#about to read 5, iclass 20, count 2 2006.161.08:20:12.37#ibcon#read 5, iclass 20, count 2 2006.161.08:20:12.37#ibcon#about to read 6, iclass 20, count 2 2006.161.08:20:12.37#ibcon#read 6, iclass 20, count 2 2006.161.08:20:12.37#ibcon#end of sib2, iclass 20, count 2 2006.161.08:20:12.37#ibcon#*after write, iclass 20, count 2 2006.161.08:20:12.37#ibcon#*before return 0, iclass 20, count 2 2006.161.08:20:12.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:20:12.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:20:12.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.08:20:12.37#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:12.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:20:12.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:20:12.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:20:12.49#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:20:12.49#ibcon#first serial, iclass 20, count 0 2006.161.08:20:12.49#ibcon#enter sib2, iclass 20, count 0 2006.161.08:20:12.49#ibcon#flushed, iclass 20, count 0 2006.161.08:20:12.49#ibcon#about to write, iclass 20, count 0 2006.161.08:20:12.49#ibcon#wrote, iclass 20, count 0 2006.161.08:20:12.49#ibcon#about to read 3, iclass 20, count 0 2006.161.08:20:12.51#ibcon#read 3, iclass 20, count 0 2006.161.08:20:12.51#ibcon#about to read 4, iclass 20, count 0 2006.161.08:20:12.51#ibcon#read 4, iclass 20, count 0 2006.161.08:20:12.51#ibcon#about to read 5, iclass 20, count 0 2006.161.08:20:12.51#ibcon#read 5, iclass 20, count 0 2006.161.08:20:12.51#ibcon#about to read 6, iclass 20, count 0 2006.161.08:20:12.51#ibcon#read 6, iclass 20, count 0 2006.161.08:20:12.51#ibcon#end of sib2, iclass 20, count 0 2006.161.08:20:12.51#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:20:12.51#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:20:12.51#ibcon#[27=USB\r\n] 2006.161.08:20:12.51#ibcon#*before write, iclass 20, count 0 2006.161.08:20:12.51#ibcon#enter sib2, iclass 20, count 0 2006.161.08:20:12.51#ibcon#flushed, iclass 20, count 0 2006.161.08:20:12.51#ibcon#about to write, iclass 20, count 0 2006.161.08:20:12.51#ibcon#wrote, iclass 20, count 0 2006.161.08:20:12.51#ibcon#about to read 3, iclass 20, count 0 2006.161.08:20:12.54#ibcon#read 3, iclass 20, count 0 2006.161.08:20:12.54#ibcon#about to read 4, iclass 20, count 0 2006.161.08:20:12.54#ibcon#read 4, iclass 20, count 0 2006.161.08:20:12.54#ibcon#about to read 5, iclass 20, count 0 2006.161.08:20:12.54#ibcon#read 5, iclass 20, count 0 2006.161.08:20:12.54#ibcon#about to read 6, iclass 20, count 0 2006.161.08:20:12.54#ibcon#read 6, iclass 20, count 0 2006.161.08:20:12.54#ibcon#end of sib2, iclass 20, count 0 2006.161.08:20:12.54#ibcon#*after write, iclass 20, count 0 2006.161.08:20:12.54#ibcon#*before return 0, iclass 20, count 0 2006.161.08:20:12.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:20:12.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:20:12.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:20:12.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:20:12.54$vc4f8/vblo=2,640.99 2006.161.08:20:12.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:20:12.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:20:12.54#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:12.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:12.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:12.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:12.54#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:20:12.54#ibcon#first serial, iclass 22, count 0 2006.161.08:20:12.54#ibcon#enter sib2, iclass 22, count 0 2006.161.08:20:12.54#ibcon#flushed, iclass 22, count 0 2006.161.08:20:12.54#ibcon#about to write, iclass 22, count 0 2006.161.08:20:12.54#ibcon#wrote, iclass 22, count 0 2006.161.08:20:12.54#ibcon#about to read 3, iclass 22, count 0 2006.161.08:20:12.56#ibcon#read 3, iclass 22, count 0 2006.161.08:20:12.56#ibcon#about to read 4, iclass 22, count 0 2006.161.08:20:12.56#ibcon#read 4, iclass 22, count 0 2006.161.08:20:12.56#ibcon#about to read 5, iclass 22, count 0 2006.161.08:20:12.56#ibcon#read 5, iclass 22, count 0 2006.161.08:20:12.56#ibcon#about to read 6, iclass 22, count 0 2006.161.08:20:12.56#ibcon#read 6, iclass 22, count 0 2006.161.08:20:12.56#ibcon#end of sib2, iclass 22, count 0 2006.161.08:20:12.56#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:20:12.56#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:20:12.56#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:20:12.56#ibcon#*before write, iclass 22, count 0 2006.161.08:20:12.56#ibcon#enter sib2, iclass 22, count 0 2006.161.08:20:12.56#ibcon#flushed, iclass 22, count 0 2006.161.08:20:12.56#ibcon#about to write, iclass 22, count 0 2006.161.08:20:12.56#ibcon#wrote, iclass 22, count 0 2006.161.08:20:12.56#ibcon#about to read 3, iclass 22, count 0 2006.161.08:20:12.60#ibcon#read 3, iclass 22, count 0 2006.161.08:20:12.60#ibcon#about to read 4, iclass 22, count 0 2006.161.08:20:12.60#ibcon#read 4, iclass 22, count 0 2006.161.08:20:12.60#ibcon#about to read 5, iclass 22, count 0 2006.161.08:20:12.60#ibcon#read 5, iclass 22, count 0 2006.161.08:20:12.60#ibcon#about to read 6, iclass 22, count 0 2006.161.08:20:12.60#ibcon#read 6, iclass 22, count 0 2006.161.08:20:12.60#ibcon#end of sib2, iclass 22, count 0 2006.161.08:20:12.60#ibcon#*after write, iclass 22, count 0 2006.161.08:20:12.60#ibcon#*before return 0, iclass 22, count 0 2006.161.08:20:12.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:12.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:20:12.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:20:12.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:20:12.60$vc4f8/vb=2,4 2006.161.08:20:12.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:20:12.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:20:12.60#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:12.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:12.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:12.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:12.66#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:20:12.66#ibcon#first serial, iclass 24, count 2 2006.161.08:20:12.66#ibcon#enter sib2, iclass 24, count 2 2006.161.08:20:12.66#ibcon#flushed, iclass 24, count 2 2006.161.08:20:12.66#ibcon#about to write, iclass 24, count 2 2006.161.08:20:12.66#ibcon#wrote, iclass 24, count 2 2006.161.08:20:12.66#ibcon#about to read 3, iclass 24, count 2 2006.161.08:20:12.68#ibcon#read 3, iclass 24, count 2 2006.161.08:20:12.68#ibcon#about to read 4, iclass 24, count 2 2006.161.08:20:12.68#ibcon#read 4, iclass 24, count 2 2006.161.08:20:12.68#ibcon#about to read 5, iclass 24, count 2 2006.161.08:20:12.68#ibcon#read 5, iclass 24, count 2 2006.161.08:20:12.68#ibcon#about to read 6, iclass 24, count 2 2006.161.08:20:12.68#ibcon#read 6, iclass 24, count 2 2006.161.08:20:12.68#ibcon#end of sib2, iclass 24, count 2 2006.161.08:20:12.68#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:20:12.68#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:20:12.68#ibcon#[27=AT02-04\r\n] 2006.161.08:20:12.68#ibcon#*before write, iclass 24, count 2 2006.161.08:20:12.68#ibcon#enter sib2, iclass 24, count 2 2006.161.08:20:12.68#ibcon#flushed, iclass 24, count 2 2006.161.08:20:12.68#ibcon#about to write, iclass 24, count 2 2006.161.08:20:12.68#ibcon#wrote, iclass 24, count 2 2006.161.08:20:12.68#ibcon#about to read 3, iclass 24, count 2 2006.161.08:20:12.71#ibcon#read 3, iclass 24, count 2 2006.161.08:20:12.71#ibcon#about to read 4, iclass 24, count 2 2006.161.08:20:12.71#ibcon#read 4, iclass 24, count 2 2006.161.08:20:12.71#ibcon#about to read 5, iclass 24, count 2 2006.161.08:20:12.71#ibcon#read 5, iclass 24, count 2 2006.161.08:20:12.71#ibcon#about to read 6, iclass 24, count 2 2006.161.08:20:12.71#ibcon#read 6, iclass 24, count 2 2006.161.08:20:12.71#ibcon#end of sib2, iclass 24, count 2 2006.161.08:20:12.71#ibcon#*after write, iclass 24, count 2 2006.161.08:20:12.71#ibcon#*before return 0, iclass 24, count 2 2006.161.08:20:12.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:12.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:20:12.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:20:12.71#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:12.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:12.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:12.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:12.83#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:20:12.83#ibcon#first serial, iclass 24, count 0 2006.161.08:20:12.83#ibcon#enter sib2, iclass 24, count 0 2006.161.08:20:12.83#ibcon#flushed, iclass 24, count 0 2006.161.08:20:12.83#ibcon#about to write, iclass 24, count 0 2006.161.08:20:12.83#ibcon#wrote, iclass 24, count 0 2006.161.08:20:12.83#ibcon#about to read 3, iclass 24, count 0 2006.161.08:20:12.85#ibcon#read 3, iclass 24, count 0 2006.161.08:20:12.85#ibcon#about to read 4, iclass 24, count 0 2006.161.08:20:12.85#ibcon#read 4, iclass 24, count 0 2006.161.08:20:12.85#ibcon#about to read 5, iclass 24, count 0 2006.161.08:20:12.85#ibcon#read 5, iclass 24, count 0 2006.161.08:20:12.85#ibcon#about to read 6, iclass 24, count 0 2006.161.08:20:12.85#ibcon#read 6, iclass 24, count 0 2006.161.08:20:12.85#ibcon#end of sib2, iclass 24, count 0 2006.161.08:20:12.85#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:20:12.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:20:12.85#ibcon#[27=USB\r\n] 2006.161.08:20:12.85#ibcon#*before write, iclass 24, count 0 2006.161.08:20:12.85#ibcon#enter sib2, iclass 24, count 0 2006.161.08:20:12.85#ibcon#flushed, iclass 24, count 0 2006.161.08:20:12.85#ibcon#about to write, iclass 24, count 0 2006.161.08:20:12.85#ibcon#wrote, iclass 24, count 0 2006.161.08:20:12.85#ibcon#about to read 3, iclass 24, count 0 2006.161.08:20:12.88#ibcon#read 3, iclass 24, count 0 2006.161.08:20:12.88#ibcon#about to read 4, iclass 24, count 0 2006.161.08:20:12.88#ibcon#read 4, iclass 24, count 0 2006.161.08:20:12.88#ibcon#about to read 5, iclass 24, count 0 2006.161.08:20:12.88#ibcon#read 5, iclass 24, count 0 2006.161.08:20:12.88#ibcon#about to read 6, iclass 24, count 0 2006.161.08:20:12.88#ibcon#read 6, iclass 24, count 0 2006.161.08:20:12.88#ibcon#end of sib2, iclass 24, count 0 2006.161.08:20:12.88#ibcon#*after write, iclass 24, count 0 2006.161.08:20:12.88#ibcon#*before return 0, iclass 24, count 0 2006.161.08:20:12.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:12.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:20:12.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:20:12.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:20:12.88$vc4f8/vblo=3,656.99 2006.161.08:20:12.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:20:12.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:20:12.88#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:12.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:12.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:12.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:12.88#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:20:12.88#ibcon#first serial, iclass 26, count 0 2006.161.08:20:12.88#ibcon#enter sib2, iclass 26, count 0 2006.161.08:20:12.88#ibcon#flushed, iclass 26, count 0 2006.161.08:20:12.88#ibcon#about to write, iclass 26, count 0 2006.161.08:20:12.88#ibcon#wrote, iclass 26, count 0 2006.161.08:20:12.88#ibcon#about to read 3, iclass 26, count 0 2006.161.08:20:12.90#ibcon#read 3, iclass 26, count 0 2006.161.08:20:12.90#ibcon#about to read 4, iclass 26, count 0 2006.161.08:20:12.90#ibcon#read 4, iclass 26, count 0 2006.161.08:20:12.90#ibcon#about to read 5, iclass 26, count 0 2006.161.08:20:12.90#ibcon#read 5, iclass 26, count 0 2006.161.08:20:12.90#ibcon#about to read 6, iclass 26, count 0 2006.161.08:20:12.90#ibcon#read 6, iclass 26, count 0 2006.161.08:20:12.90#ibcon#end of sib2, iclass 26, count 0 2006.161.08:20:12.90#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:20:12.90#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:20:12.90#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:20:12.90#ibcon#*before write, iclass 26, count 0 2006.161.08:20:12.90#ibcon#enter sib2, iclass 26, count 0 2006.161.08:20:12.90#ibcon#flushed, iclass 26, count 0 2006.161.08:20:12.90#ibcon#about to write, iclass 26, count 0 2006.161.08:20:12.90#ibcon#wrote, iclass 26, count 0 2006.161.08:20:12.90#ibcon#about to read 3, iclass 26, count 0 2006.161.08:20:12.94#ibcon#read 3, iclass 26, count 0 2006.161.08:20:12.94#ibcon#about to read 4, iclass 26, count 0 2006.161.08:20:12.94#ibcon#read 4, iclass 26, count 0 2006.161.08:20:12.94#ibcon#about to read 5, iclass 26, count 0 2006.161.08:20:12.94#ibcon#read 5, iclass 26, count 0 2006.161.08:20:12.94#ibcon#about to read 6, iclass 26, count 0 2006.161.08:20:12.94#ibcon#read 6, iclass 26, count 0 2006.161.08:20:12.94#ibcon#end of sib2, iclass 26, count 0 2006.161.08:20:12.94#ibcon#*after write, iclass 26, count 0 2006.161.08:20:12.94#ibcon#*before return 0, iclass 26, count 0 2006.161.08:20:12.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:12.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:20:12.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:20:12.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:20:12.94$vc4f8/vb=3,4 2006.161.08:20:12.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:20:12.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:20:12.94#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:12.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:13.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:13.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:13.00#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:20:13.00#ibcon#first serial, iclass 28, count 2 2006.161.08:20:13.00#ibcon#enter sib2, iclass 28, count 2 2006.161.08:20:13.00#ibcon#flushed, iclass 28, count 2 2006.161.08:20:13.00#ibcon#about to write, iclass 28, count 2 2006.161.08:20:13.00#ibcon#wrote, iclass 28, count 2 2006.161.08:20:13.00#ibcon#about to read 3, iclass 28, count 2 2006.161.08:20:13.02#ibcon#read 3, iclass 28, count 2 2006.161.08:20:13.02#ibcon#about to read 4, iclass 28, count 2 2006.161.08:20:13.02#ibcon#read 4, iclass 28, count 2 2006.161.08:20:13.02#ibcon#about to read 5, iclass 28, count 2 2006.161.08:20:13.02#ibcon#read 5, iclass 28, count 2 2006.161.08:20:13.02#ibcon#about to read 6, iclass 28, count 2 2006.161.08:20:13.02#ibcon#read 6, iclass 28, count 2 2006.161.08:20:13.02#ibcon#end of sib2, iclass 28, count 2 2006.161.08:20:13.02#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:20:13.02#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:20:13.02#ibcon#[27=AT03-04\r\n] 2006.161.08:20:13.02#ibcon#*before write, iclass 28, count 2 2006.161.08:20:13.02#ibcon#enter sib2, iclass 28, count 2 2006.161.08:20:13.02#ibcon#flushed, iclass 28, count 2 2006.161.08:20:13.02#ibcon#about to write, iclass 28, count 2 2006.161.08:20:13.02#ibcon#wrote, iclass 28, count 2 2006.161.08:20:13.02#ibcon#about to read 3, iclass 28, count 2 2006.161.08:20:13.05#ibcon#read 3, iclass 28, count 2 2006.161.08:20:13.05#ibcon#about to read 4, iclass 28, count 2 2006.161.08:20:13.05#ibcon#read 4, iclass 28, count 2 2006.161.08:20:13.05#ibcon#about to read 5, iclass 28, count 2 2006.161.08:20:13.05#ibcon#read 5, iclass 28, count 2 2006.161.08:20:13.05#ibcon#about to read 6, iclass 28, count 2 2006.161.08:20:13.05#ibcon#read 6, iclass 28, count 2 2006.161.08:20:13.05#ibcon#end of sib2, iclass 28, count 2 2006.161.08:20:13.05#ibcon#*after write, iclass 28, count 2 2006.161.08:20:13.05#ibcon#*before return 0, iclass 28, count 2 2006.161.08:20:13.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:13.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:20:13.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:20:13.05#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:13.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:13.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:13.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:13.17#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:20:13.17#ibcon#first serial, iclass 28, count 0 2006.161.08:20:13.17#ibcon#enter sib2, iclass 28, count 0 2006.161.08:20:13.17#ibcon#flushed, iclass 28, count 0 2006.161.08:20:13.17#ibcon#about to write, iclass 28, count 0 2006.161.08:20:13.17#ibcon#wrote, iclass 28, count 0 2006.161.08:20:13.17#ibcon#about to read 3, iclass 28, count 0 2006.161.08:20:13.19#ibcon#read 3, iclass 28, count 0 2006.161.08:20:13.19#ibcon#about to read 4, iclass 28, count 0 2006.161.08:20:13.19#ibcon#read 4, iclass 28, count 0 2006.161.08:20:13.19#ibcon#about to read 5, iclass 28, count 0 2006.161.08:20:13.19#ibcon#read 5, iclass 28, count 0 2006.161.08:20:13.19#ibcon#about to read 6, iclass 28, count 0 2006.161.08:20:13.19#ibcon#read 6, iclass 28, count 0 2006.161.08:20:13.19#ibcon#end of sib2, iclass 28, count 0 2006.161.08:20:13.19#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:20:13.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:20:13.19#ibcon#[27=USB\r\n] 2006.161.08:20:13.19#ibcon#*before write, iclass 28, count 0 2006.161.08:20:13.19#ibcon#enter sib2, iclass 28, count 0 2006.161.08:20:13.19#ibcon#flushed, iclass 28, count 0 2006.161.08:20:13.19#ibcon#about to write, iclass 28, count 0 2006.161.08:20:13.19#ibcon#wrote, iclass 28, count 0 2006.161.08:20:13.19#ibcon#about to read 3, iclass 28, count 0 2006.161.08:20:13.22#ibcon#read 3, iclass 28, count 0 2006.161.08:20:13.22#ibcon#about to read 4, iclass 28, count 0 2006.161.08:20:13.22#ibcon#read 4, iclass 28, count 0 2006.161.08:20:13.22#ibcon#about to read 5, iclass 28, count 0 2006.161.08:20:13.22#ibcon#read 5, iclass 28, count 0 2006.161.08:20:13.22#ibcon#about to read 6, iclass 28, count 0 2006.161.08:20:13.22#ibcon#read 6, iclass 28, count 0 2006.161.08:20:13.22#ibcon#end of sib2, iclass 28, count 0 2006.161.08:20:13.22#ibcon#*after write, iclass 28, count 0 2006.161.08:20:13.22#ibcon#*before return 0, iclass 28, count 0 2006.161.08:20:13.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:13.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:20:13.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:20:13.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:20:13.22$vc4f8/vblo=4,712.99 2006.161.08:20:13.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:20:13.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:20:13.22#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:13.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:13.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:13.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:13.22#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:20:13.22#ibcon#first serial, iclass 30, count 0 2006.161.08:20:13.22#ibcon#enter sib2, iclass 30, count 0 2006.161.08:20:13.22#ibcon#flushed, iclass 30, count 0 2006.161.08:20:13.22#ibcon#about to write, iclass 30, count 0 2006.161.08:20:13.22#ibcon#wrote, iclass 30, count 0 2006.161.08:20:13.22#ibcon#about to read 3, iclass 30, count 0 2006.161.08:20:13.24#ibcon#read 3, iclass 30, count 0 2006.161.08:20:13.24#ibcon#about to read 4, iclass 30, count 0 2006.161.08:20:13.24#ibcon#read 4, iclass 30, count 0 2006.161.08:20:13.24#ibcon#about to read 5, iclass 30, count 0 2006.161.08:20:13.24#ibcon#read 5, iclass 30, count 0 2006.161.08:20:13.24#ibcon#about to read 6, iclass 30, count 0 2006.161.08:20:13.24#ibcon#read 6, iclass 30, count 0 2006.161.08:20:13.24#ibcon#end of sib2, iclass 30, count 0 2006.161.08:20:13.24#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:20:13.24#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:20:13.24#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:20:13.24#ibcon#*before write, iclass 30, count 0 2006.161.08:20:13.24#ibcon#enter sib2, iclass 30, count 0 2006.161.08:20:13.24#ibcon#flushed, iclass 30, count 0 2006.161.08:20:13.24#ibcon#about to write, iclass 30, count 0 2006.161.08:20:13.24#ibcon#wrote, iclass 30, count 0 2006.161.08:20:13.24#ibcon#about to read 3, iclass 30, count 0 2006.161.08:20:13.28#ibcon#read 3, iclass 30, count 0 2006.161.08:20:13.28#ibcon#about to read 4, iclass 30, count 0 2006.161.08:20:13.28#ibcon#read 4, iclass 30, count 0 2006.161.08:20:13.28#ibcon#about to read 5, iclass 30, count 0 2006.161.08:20:13.28#ibcon#read 5, iclass 30, count 0 2006.161.08:20:13.28#ibcon#about to read 6, iclass 30, count 0 2006.161.08:20:13.28#ibcon#read 6, iclass 30, count 0 2006.161.08:20:13.28#ibcon#end of sib2, iclass 30, count 0 2006.161.08:20:13.28#ibcon#*after write, iclass 30, count 0 2006.161.08:20:13.28#ibcon#*before return 0, iclass 30, count 0 2006.161.08:20:13.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:13.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:20:13.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:20:13.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:20:13.28$vc4f8/vb=4,4 2006.161.08:20:13.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:20:13.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:20:13.28#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:13.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:13.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:13.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:13.34#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:20:13.34#ibcon#first serial, iclass 32, count 2 2006.161.08:20:13.34#ibcon#enter sib2, iclass 32, count 2 2006.161.08:20:13.34#ibcon#flushed, iclass 32, count 2 2006.161.08:20:13.34#ibcon#about to write, iclass 32, count 2 2006.161.08:20:13.34#ibcon#wrote, iclass 32, count 2 2006.161.08:20:13.34#ibcon#about to read 3, iclass 32, count 2 2006.161.08:20:13.36#ibcon#read 3, iclass 32, count 2 2006.161.08:20:13.36#ibcon#about to read 4, iclass 32, count 2 2006.161.08:20:13.36#ibcon#read 4, iclass 32, count 2 2006.161.08:20:13.36#ibcon#about to read 5, iclass 32, count 2 2006.161.08:20:13.36#ibcon#read 5, iclass 32, count 2 2006.161.08:20:13.36#ibcon#about to read 6, iclass 32, count 2 2006.161.08:20:13.36#ibcon#read 6, iclass 32, count 2 2006.161.08:20:13.36#ibcon#end of sib2, iclass 32, count 2 2006.161.08:20:13.36#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:20:13.36#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:20:13.36#ibcon#[27=AT04-04\r\n] 2006.161.08:20:13.36#ibcon#*before write, iclass 32, count 2 2006.161.08:20:13.36#ibcon#enter sib2, iclass 32, count 2 2006.161.08:20:13.36#ibcon#flushed, iclass 32, count 2 2006.161.08:20:13.36#ibcon#about to write, iclass 32, count 2 2006.161.08:20:13.36#ibcon#wrote, iclass 32, count 2 2006.161.08:20:13.36#ibcon#about to read 3, iclass 32, count 2 2006.161.08:20:13.39#ibcon#read 3, iclass 32, count 2 2006.161.08:20:13.39#ibcon#about to read 4, iclass 32, count 2 2006.161.08:20:13.39#ibcon#read 4, iclass 32, count 2 2006.161.08:20:13.39#ibcon#about to read 5, iclass 32, count 2 2006.161.08:20:13.39#ibcon#read 5, iclass 32, count 2 2006.161.08:20:13.39#ibcon#about to read 6, iclass 32, count 2 2006.161.08:20:13.39#ibcon#read 6, iclass 32, count 2 2006.161.08:20:13.39#ibcon#end of sib2, iclass 32, count 2 2006.161.08:20:13.39#ibcon#*after write, iclass 32, count 2 2006.161.08:20:13.39#ibcon#*before return 0, iclass 32, count 2 2006.161.08:20:13.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:13.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:20:13.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:20:13.39#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:13.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:13.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:13.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:13.51#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:20:13.51#ibcon#first serial, iclass 32, count 0 2006.161.08:20:13.51#ibcon#enter sib2, iclass 32, count 0 2006.161.08:20:13.51#ibcon#flushed, iclass 32, count 0 2006.161.08:20:13.51#ibcon#about to write, iclass 32, count 0 2006.161.08:20:13.51#ibcon#wrote, iclass 32, count 0 2006.161.08:20:13.51#ibcon#about to read 3, iclass 32, count 0 2006.161.08:20:13.53#ibcon#read 3, iclass 32, count 0 2006.161.08:20:13.53#ibcon#about to read 4, iclass 32, count 0 2006.161.08:20:13.53#ibcon#read 4, iclass 32, count 0 2006.161.08:20:13.53#ibcon#about to read 5, iclass 32, count 0 2006.161.08:20:13.53#ibcon#read 5, iclass 32, count 0 2006.161.08:20:13.53#ibcon#about to read 6, iclass 32, count 0 2006.161.08:20:13.53#ibcon#read 6, iclass 32, count 0 2006.161.08:20:13.53#ibcon#end of sib2, iclass 32, count 0 2006.161.08:20:13.53#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:20:13.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:20:13.53#ibcon#[27=USB\r\n] 2006.161.08:20:13.53#ibcon#*before write, iclass 32, count 0 2006.161.08:20:13.53#ibcon#enter sib2, iclass 32, count 0 2006.161.08:20:13.53#ibcon#flushed, iclass 32, count 0 2006.161.08:20:13.53#ibcon#about to write, iclass 32, count 0 2006.161.08:20:13.53#ibcon#wrote, iclass 32, count 0 2006.161.08:20:13.53#ibcon#about to read 3, iclass 32, count 0 2006.161.08:20:13.56#ibcon#read 3, iclass 32, count 0 2006.161.08:20:13.56#ibcon#about to read 4, iclass 32, count 0 2006.161.08:20:13.56#ibcon#read 4, iclass 32, count 0 2006.161.08:20:13.56#ibcon#about to read 5, iclass 32, count 0 2006.161.08:20:13.56#ibcon#read 5, iclass 32, count 0 2006.161.08:20:13.56#ibcon#about to read 6, iclass 32, count 0 2006.161.08:20:13.56#ibcon#read 6, iclass 32, count 0 2006.161.08:20:13.56#ibcon#end of sib2, iclass 32, count 0 2006.161.08:20:13.56#ibcon#*after write, iclass 32, count 0 2006.161.08:20:13.56#ibcon#*before return 0, iclass 32, count 0 2006.161.08:20:13.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:13.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:20:13.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:20:13.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:20:13.56$vc4f8/vblo=5,744.99 2006.161.08:20:13.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:20:13.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:20:13.56#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:13.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:13.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:13.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:13.56#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:20:13.56#ibcon#first serial, iclass 34, count 0 2006.161.08:20:13.56#ibcon#enter sib2, iclass 34, count 0 2006.161.08:20:13.56#ibcon#flushed, iclass 34, count 0 2006.161.08:20:13.56#ibcon#about to write, iclass 34, count 0 2006.161.08:20:13.56#ibcon#wrote, iclass 34, count 0 2006.161.08:20:13.56#ibcon#about to read 3, iclass 34, count 0 2006.161.08:20:13.58#ibcon#read 3, iclass 34, count 0 2006.161.08:20:13.58#ibcon#about to read 4, iclass 34, count 0 2006.161.08:20:13.58#ibcon#read 4, iclass 34, count 0 2006.161.08:20:13.58#ibcon#about to read 5, iclass 34, count 0 2006.161.08:20:13.58#ibcon#read 5, iclass 34, count 0 2006.161.08:20:13.58#ibcon#about to read 6, iclass 34, count 0 2006.161.08:20:13.58#ibcon#read 6, iclass 34, count 0 2006.161.08:20:13.58#ibcon#end of sib2, iclass 34, count 0 2006.161.08:20:13.58#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:20:13.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:20:13.58#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:20:13.58#ibcon#*before write, iclass 34, count 0 2006.161.08:20:13.58#ibcon#enter sib2, iclass 34, count 0 2006.161.08:20:13.58#ibcon#flushed, iclass 34, count 0 2006.161.08:20:13.58#ibcon#about to write, iclass 34, count 0 2006.161.08:20:13.58#ibcon#wrote, iclass 34, count 0 2006.161.08:20:13.58#ibcon#about to read 3, iclass 34, count 0 2006.161.08:20:13.62#ibcon#read 3, iclass 34, count 0 2006.161.08:20:13.62#ibcon#about to read 4, iclass 34, count 0 2006.161.08:20:13.62#ibcon#read 4, iclass 34, count 0 2006.161.08:20:13.62#ibcon#about to read 5, iclass 34, count 0 2006.161.08:20:13.62#ibcon#read 5, iclass 34, count 0 2006.161.08:20:13.62#ibcon#about to read 6, iclass 34, count 0 2006.161.08:20:13.62#ibcon#read 6, iclass 34, count 0 2006.161.08:20:13.62#ibcon#end of sib2, iclass 34, count 0 2006.161.08:20:13.62#ibcon#*after write, iclass 34, count 0 2006.161.08:20:13.62#ibcon#*before return 0, iclass 34, count 0 2006.161.08:20:13.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:13.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:20:13.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:20:13.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:20:13.62$vc4f8/vb=5,4 2006.161.08:20:13.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:20:13.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:20:13.62#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:13.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:13.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:13.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:13.68#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:20:13.68#ibcon#first serial, iclass 36, count 2 2006.161.08:20:13.68#ibcon#enter sib2, iclass 36, count 2 2006.161.08:20:13.68#ibcon#flushed, iclass 36, count 2 2006.161.08:20:13.68#ibcon#about to write, iclass 36, count 2 2006.161.08:20:13.68#ibcon#wrote, iclass 36, count 2 2006.161.08:20:13.68#ibcon#about to read 3, iclass 36, count 2 2006.161.08:20:13.70#ibcon#read 3, iclass 36, count 2 2006.161.08:20:13.70#ibcon#about to read 4, iclass 36, count 2 2006.161.08:20:13.70#ibcon#read 4, iclass 36, count 2 2006.161.08:20:13.70#ibcon#about to read 5, iclass 36, count 2 2006.161.08:20:13.70#ibcon#read 5, iclass 36, count 2 2006.161.08:20:13.70#ibcon#about to read 6, iclass 36, count 2 2006.161.08:20:13.70#ibcon#read 6, iclass 36, count 2 2006.161.08:20:13.70#ibcon#end of sib2, iclass 36, count 2 2006.161.08:20:13.70#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:20:13.70#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:20:13.70#ibcon#[27=AT05-04\r\n] 2006.161.08:20:13.70#ibcon#*before write, iclass 36, count 2 2006.161.08:20:13.70#ibcon#enter sib2, iclass 36, count 2 2006.161.08:20:13.70#ibcon#flushed, iclass 36, count 2 2006.161.08:20:13.70#ibcon#about to write, iclass 36, count 2 2006.161.08:20:13.70#ibcon#wrote, iclass 36, count 2 2006.161.08:20:13.70#ibcon#about to read 3, iclass 36, count 2 2006.161.08:20:13.73#ibcon#read 3, iclass 36, count 2 2006.161.08:20:13.73#ibcon#about to read 4, iclass 36, count 2 2006.161.08:20:13.73#ibcon#read 4, iclass 36, count 2 2006.161.08:20:13.73#ibcon#about to read 5, iclass 36, count 2 2006.161.08:20:13.73#ibcon#read 5, iclass 36, count 2 2006.161.08:20:13.73#ibcon#about to read 6, iclass 36, count 2 2006.161.08:20:13.73#ibcon#read 6, iclass 36, count 2 2006.161.08:20:13.73#ibcon#end of sib2, iclass 36, count 2 2006.161.08:20:13.73#ibcon#*after write, iclass 36, count 2 2006.161.08:20:13.73#ibcon#*before return 0, iclass 36, count 2 2006.161.08:20:13.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:13.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:20:13.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:20:13.73#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:13.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:13.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:13.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:13.85#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:20:13.85#ibcon#first serial, iclass 36, count 0 2006.161.08:20:13.85#ibcon#enter sib2, iclass 36, count 0 2006.161.08:20:13.85#ibcon#flushed, iclass 36, count 0 2006.161.08:20:13.85#ibcon#about to write, iclass 36, count 0 2006.161.08:20:13.85#ibcon#wrote, iclass 36, count 0 2006.161.08:20:13.85#ibcon#about to read 3, iclass 36, count 0 2006.161.08:20:13.87#ibcon#read 3, iclass 36, count 0 2006.161.08:20:13.87#ibcon#about to read 4, iclass 36, count 0 2006.161.08:20:13.87#ibcon#read 4, iclass 36, count 0 2006.161.08:20:13.87#ibcon#about to read 5, iclass 36, count 0 2006.161.08:20:13.87#ibcon#read 5, iclass 36, count 0 2006.161.08:20:13.87#ibcon#about to read 6, iclass 36, count 0 2006.161.08:20:13.87#ibcon#read 6, iclass 36, count 0 2006.161.08:20:13.87#ibcon#end of sib2, iclass 36, count 0 2006.161.08:20:13.87#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:20:13.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:20:13.87#ibcon#[27=USB\r\n] 2006.161.08:20:13.87#ibcon#*before write, iclass 36, count 0 2006.161.08:20:13.87#ibcon#enter sib2, iclass 36, count 0 2006.161.08:20:13.87#ibcon#flushed, iclass 36, count 0 2006.161.08:20:13.87#ibcon#about to write, iclass 36, count 0 2006.161.08:20:13.87#ibcon#wrote, iclass 36, count 0 2006.161.08:20:13.87#ibcon#about to read 3, iclass 36, count 0 2006.161.08:20:13.90#ibcon#read 3, iclass 36, count 0 2006.161.08:20:13.90#ibcon#about to read 4, iclass 36, count 0 2006.161.08:20:13.90#ibcon#read 4, iclass 36, count 0 2006.161.08:20:13.90#ibcon#about to read 5, iclass 36, count 0 2006.161.08:20:13.90#ibcon#read 5, iclass 36, count 0 2006.161.08:20:13.90#ibcon#about to read 6, iclass 36, count 0 2006.161.08:20:13.90#ibcon#read 6, iclass 36, count 0 2006.161.08:20:13.90#ibcon#end of sib2, iclass 36, count 0 2006.161.08:20:13.90#ibcon#*after write, iclass 36, count 0 2006.161.08:20:13.90#ibcon#*before return 0, iclass 36, count 0 2006.161.08:20:13.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:13.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:20:13.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:20:13.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:20:13.90$vc4f8/vblo=6,752.99 2006.161.08:20:13.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:20:13.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:20:13.90#ibcon#ireg 17 cls_cnt 0 2006.161.08:20:13.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:13.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:13.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:13.90#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:20:13.90#ibcon#first serial, iclass 38, count 0 2006.161.08:20:13.90#ibcon#enter sib2, iclass 38, count 0 2006.161.08:20:13.90#ibcon#flushed, iclass 38, count 0 2006.161.08:20:13.90#ibcon#about to write, iclass 38, count 0 2006.161.08:20:13.90#ibcon#wrote, iclass 38, count 0 2006.161.08:20:13.90#ibcon#about to read 3, iclass 38, count 0 2006.161.08:20:13.92#ibcon#read 3, iclass 38, count 0 2006.161.08:20:13.92#ibcon#about to read 4, iclass 38, count 0 2006.161.08:20:13.92#ibcon#read 4, iclass 38, count 0 2006.161.08:20:13.92#ibcon#about to read 5, iclass 38, count 0 2006.161.08:20:13.92#ibcon#read 5, iclass 38, count 0 2006.161.08:20:13.92#ibcon#about to read 6, iclass 38, count 0 2006.161.08:20:13.92#ibcon#read 6, iclass 38, count 0 2006.161.08:20:13.92#ibcon#end of sib2, iclass 38, count 0 2006.161.08:20:13.92#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:20:13.92#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:20:13.92#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:20:13.92#ibcon#*before write, iclass 38, count 0 2006.161.08:20:13.92#ibcon#enter sib2, iclass 38, count 0 2006.161.08:20:13.92#ibcon#flushed, iclass 38, count 0 2006.161.08:20:13.92#ibcon#about to write, iclass 38, count 0 2006.161.08:20:13.92#ibcon#wrote, iclass 38, count 0 2006.161.08:20:13.92#ibcon#about to read 3, iclass 38, count 0 2006.161.08:20:13.96#ibcon#read 3, iclass 38, count 0 2006.161.08:20:13.96#ibcon#about to read 4, iclass 38, count 0 2006.161.08:20:13.96#ibcon#read 4, iclass 38, count 0 2006.161.08:20:13.96#ibcon#about to read 5, iclass 38, count 0 2006.161.08:20:13.96#ibcon#read 5, iclass 38, count 0 2006.161.08:20:13.96#ibcon#about to read 6, iclass 38, count 0 2006.161.08:20:13.96#ibcon#read 6, iclass 38, count 0 2006.161.08:20:13.96#ibcon#end of sib2, iclass 38, count 0 2006.161.08:20:13.96#ibcon#*after write, iclass 38, count 0 2006.161.08:20:13.96#ibcon#*before return 0, iclass 38, count 0 2006.161.08:20:13.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:13.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:20:13.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:20:13.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:20:13.96$vc4f8/vb=6,4 2006.161.08:20:13.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:20:13.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:20:13.96#ibcon#ireg 11 cls_cnt 2 2006.161.08:20:13.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:14.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:14.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:14.02#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:20:14.02#ibcon#first serial, iclass 40, count 2 2006.161.08:20:14.02#ibcon#enter sib2, iclass 40, count 2 2006.161.08:20:14.02#ibcon#flushed, iclass 40, count 2 2006.161.08:20:14.02#ibcon#about to write, iclass 40, count 2 2006.161.08:20:14.02#ibcon#wrote, iclass 40, count 2 2006.161.08:20:14.02#ibcon#about to read 3, iclass 40, count 2 2006.161.08:20:14.04#ibcon#read 3, iclass 40, count 2 2006.161.08:20:14.04#ibcon#about to read 4, iclass 40, count 2 2006.161.08:20:14.04#ibcon#read 4, iclass 40, count 2 2006.161.08:20:14.04#ibcon#about to read 5, iclass 40, count 2 2006.161.08:20:14.04#ibcon#read 5, iclass 40, count 2 2006.161.08:20:14.04#ibcon#about to read 6, iclass 40, count 2 2006.161.08:20:14.04#ibcon#read 6, iclass 40, count 2 2006.161.08:20:14.04#ibcon#end of sib2, iclass 40, count 2 2006.161.08:20:14.04#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:20:14.04#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:20:14.04#ibcon#[27=AT06-04\r\n] 2006.161.08:20:14.04#ibcon#*before write, iclass 40, count 2 2006.161.08:20:14.04#ibcon#enter sib2, iclass 40, count 2 2006.161.08:20:14.04#ibcon#flushed, iclass 40, count 2 2006.161.08:20:14.04#ibcon#about to write, iclass 40, count 2 2006.161.08:20:14.04#ibcon#wrote, iclass 40, count 2 2006.161.08:20:14.04#ibcon#about to read 3, iclass 40, count 2 2006.161.08:20:14.07#ibcon#read 3, iclass 40, count 2 2006.161.08:20:14.07#ibcon#about to read 4, iclass 40, count 2 2006.161.08:20:14.07#ibcon#read 4, iclass 40, count 2 2006.161.08:20:14.07#ibcon#about to read 5, iclass 40, count 2 2006.161.08:20:14.07#ibcon#read 5, iclass 40, count 2 2006.161.08:20:14.07#ibcon#about to read 6, iclass 40, count 2 2006.161.08:20:14.07#ibcon#read 6, iclass 40, count 2 2006.161.08:20:14.07#ibcon#end of sib2, iclass 40, count 2 2006.161.08:20:14.07#ibcon#*after write, iclass 40, count 2 2006.161.08:20:14.07#ibcon#*before return 0, iclass 40, count 2 2006.161.08:20:14.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:14.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:20:14.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:20:14.07#ibcon#ireg 7 cls_cnt 0 2006.161.08:20:14.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:14.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:14.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:14.19#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:20:14.19#ibcon#first serial, iclass 40, count 0 2006.161.08:20:14.19#ibcon#enter sib2, iclass 40, count 0 2006.161.08:20:14.19#ibcon#flushed, iclass 40, count 0 2006.161.08:20:14.19#ibcon#about to write, iclass 40, count 0 2006.161.08:20:14.19#ibcon#wrote, iclass 40, count 0 2006.161.08:20:14.19#ibcon#about to read 3, iclass 40, count 0 2006.161.08:20:14.23#ibcon#read 3, iclass 40, count 0 2006.161.08:20:14.23#ibcon#about to read 4, iclass 40, count 0 2006.161.08:20:14.23#ibcon#read 4, iclass 40, count 0 2006.161.08:20:14.23#ibcon#about to read 5, iclass 40, count 0 2006.161.08:20:14.23#ibcon#read 5, iclass 40, count 0 2006.161.08:20:14.23#ibcon#about to read 6, iclass 40, count 0 2006.161.08:20:14.23#ibcon#read 6, iclass 40, count 0 2006.161.08:20:14.23#ibcon#end of sib2, iclass 40, count 0 2006.161.08:20:14.23#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:20:14.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:20:14.23#ibcon#[27=USB\r\n] 2006.161.08:20:14.23#ibcon#*before write, iclass 40, count 0 2006.161.08:20:14.23#ibcon#enter sib2, iclass 40, count 0 2006.161.08:20:14.23#ibcon#flushed, iclass 40, count 0 2006.161.08:20:14.23#ibcon#about to write, iclass 40, count 0 2006.161.08:20:14.23#ibcon#wrote, iclass 40, count 0 2006.161.08:20:14.23#ibcon#about to read 3, iclass 40, count 0 2006.161.08:20:14.26#ibcon#read 3, iclass 40, count 0 2006.161.08:20:14.26#ibcon#about to read 4, iclass 40, count 0 2006.161.08:20:14.26#ibcon#read 4, iclass 40, count 0 2006.161.08:20:14.26#ibcon#about to read 5, iclass 40, count 0 2006.161.08:20:14.26#ibcon#read 5, iclass 40, count 0 2006.161.08:20:14.26#ibcon#about to read 6, iclass 40, count 0 2006.161.08:20:14.26#ibcon#read 6, iclass 40, count 0 2006.161.08:20:14.26#ibcon#end of sib2, iclass 40, count 0 2006.161.08:20:14.26#ibcon#*after write, iclass 40, count 0 2006.161.08:20:14.26#ibcon#*before return 0, iclass 40, count 0 2006.161.08:20:14.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:14.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:20:14.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:20:14.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:20:14.26$vc4f8/vabw=wide 2006.161.08:20:14.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:20:14.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:20:14.26#ibcon#ireg 8 cls_cnt 0 2006.161.08:20:14.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:14.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:14.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:14.26#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:20:14.26#ibcon#first serial, iclass 4, count 0 2006.161.08:20:14.26#ibcon#enter sib2, iclass 4, count 0 2006.161.08:20:14.26#ibcon#flushed, iclass 4, count 0 2006.161.08:20:14.26#ibcon#about to write, iclass 4, count 0 2006.161.08:20:14.26#ibcon#wrote, iclass 4, count 0 2006.161.08:20:14.26#ibcon#about to read 3, iclass 4, count 0 2006.161.08:20:14.28#ibcon#read 3, iclass 4, count 0 2006.161.08:20:14.28#ibcon#about to read 4, iclass 4, count 0 2006.161.08:20:14.28#ibcon#read 4, iclass 4, count 0 2006.161.08:20:14.28#ibcon#about to read 5, iclass 4, count 0 2006.161.08:20:14.28#ibcon#read 5, iclass 4, count 0 2006.161.08:20:14.28#ibcon#about to read 6, iclass 4, count 0 2006.161.08:20:14.28#ibcon#read 6, iclass 4, count 0 2006.161.08:20:14.28#ibcon#end of sib2, iclass 4, count 0 2006.161.08:20:14.28#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:20:14.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:20:14.28#ibcon#[25=BW32\r\n] 2006.161.08:20:14.28#ibcon#*before write, iclass 4, count 0 2006.161.08:20:14.28#ibcon#enter sib2, iclass 4, count 0 2006.161.08:20:14.28#ibcon#flushed, iclass 4, count 0 2006.161.08:20:14.28#ibcon#about to write, iclass 4, count 0 2006.161.08:20:14.28#ibcon#wrote, iclass 4, count 0 2006.161.08:20:14.28#ibcon#about to read 3, iclass 4, count 0 2006.161.08:20:14.31#ibcon#read 3, iclass 4, count 0 2006.161.08:20:14.31#ibcon#about to read 4, iclass 4, count 0 2006.161.08:20:14.31#ibcon#read 4, iclass 4, count 0 2006.161.08:20:14.31#ibcon#about to read 5, iclass 4, count 0 2006.161.08:20:14.31#ibcon#read 5, iclass 4, count 0 2006.161.08:20:14.31#ibcon#about to read 6, iclass 4, count 0 2006.161.08:20:14.31#ibcon#read 6, iclass 4, count 0 2006.161.08:20:14.31#ibcon#end of sib2, iclass 4, count 0 2006.161.08:20:14.31#ibcon#*after write, iclass 4, count 0 2006.161.08:20:14.31#ibcon#*before return 0, iclass 4, count 0 2006.161.08:20:14.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:14.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:20:14.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:20:14.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:20:14.31$vc4f8/vbbw=wide 2006.161.08:20:14.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:20:14.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:20:14.31#ibcon#ireg 8 cls_cnt 0 2006.161.08:20:14.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:20:14.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:20:14.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:20:14.38#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:20:14.38#ibcon#first serial, iclass 6, count 0 2006.161.08:20:14.38#ibcon#enter sib2, iclass 6, count 0 2006.161.08:20:14.38#ibcon#flushed, iclass 6, count 0 2006.161.08:20:14.38#ibcon#about to write, iclass 6, count 0 2006.161.08:20:14.38#ibcon#wrote, iclass 6, count 0 2006.161.08:20:14.38#ibcon#about to read 3, iclass 6, count 0 2006.161.08:20:14.40#ibcon#read 3, iclass 6, count 0 2006.161.08:20:14.40#ibcon#about to read 4, iclass 6, count 0 2006.161.08:20:14.40#ibcon#read 4, iclass 6, count 0 2006.161.08:20:14.40#ibcon#about to read 5, iclass 6, count 0 2006.161.08:20:14.40#ibcon#read 5, iclass 6, count 0 2006.161.08:20:14.40#ibcon#about to read 6, iclass 6, count 0 2006.161.08:20:14.40#ibcon#read 6, iclass 6, count 0 2006.161.08:20:14.40#ibcon#end of sib2, iclass 6, count 0 2006.161.08:20:14.40#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:20:14.40#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:20:14.40#ibcon#[27=BW32\r\n] 2006.161.08:20:14.40#ibcon#*before write, iclass 6, count 0 2006.161.08:20:14.40#ibcon#enter sib2, iclass 6, count 0 2006.161.08:20:14.40#ibcon#flushed, iclass 6, count 0 2006.161.08:20:14.40#ibcon#about to write, iclass 6, count 0 2006.161.08:20:14.40#ibcon#wrote, iclass 6, count 0 2006.161.08:20:14.40#ibcon#about to read 3, iclass 6, count 0 2006.161.08:20:14.43#ibcon#read 3, iclass 6, count 0 2006.161.08:20:14.43#ibcon#about to read 4, iclass 6, count 0 2006.161.08:20:14.43#ibcon#read 4, iclass 6, count 0 2006.161.08:20:14.43#ibcon#about to read 5, iclass 6, count 0 2006.161.08:20:14.43#ibcon#read 5, iclass 6, count 0 2006.161.08:20:14.43#ibcon#about to read 6, iclass 6, count 0 2006.161.08:20:14.43#ibcon#read 6, iclass 6, count 0 2006.161.08:20:14.43#ibcon#end of sib2, iclass 6, count 0 2006.161.08:20:14.43#ibcon#*after write, iclass 6, count 0 2006.161.08:20:14.43#ibcon#*before return 0, iclass 6, count 0 2006.161.08:20:14.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:20:14.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:20:14.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:20:14.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:20:14.43$4f8m12a/ifd4f 2006.161.08:20:14.43$ifd4f/lo= 2006.161.08:20:14.43$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:20:14.43$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:20:14.43$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:20:14.43$ifd4f/patch= 2006.161.08:20:14.43$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:20:14.43$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:20:14.43$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:20:14.43$4f8m12a/"form=m,16.000,1:2 2006.161.08:20:14.43$4f8m12a/"tpicd 2006.161.08:20:14.43$4f8m12a/echo=off 2006.161.08:20:14.43$4f8m12a/xlog=off 2006.161.08:20:14.43:!2006.161.08:22:20 2006.161.08:20:25.14#trakl#Source acquired 2006.161.08:20:25.14#flagr#flagr/antenna,acquired 2006.161.08:22:20.00:preob 2006.161.08:22:20.13/onsource/TRACKING 2006.161.08:22:20.13:!2006.161.08:22:30 2006.161.08:22:30.00:data_valid=on 2006.161.08:22:30.00:midob 2006.161.08:22:31.13/onsource/TRACKING 2006.161.08:22:31.13/wx/23.99,1002.5,87 2006.161.08:22:31.30/cable/+6.4994E-03 2006.161.08:22:32.39/va/01,08,usb,yes,28,30 2006.161.08:22:32.39/va/02,07,usb,yes,28,30 2006.161.08:22:32.39/va/03,06,usb,yes,30,30 2006.161.08:22:32.39/va/04,07,usb,yes,29,31 2006.161.08:22:32.39/va/05,07,usb,yes,29,31 2006.161.08:22:32.39/va/06,06,usb,yes,29,28 2006.161.08:22:32.39/va/07,06,usb,yes,29,29 2006.161.08:22:32.39/va/08,07,usb,yes,27,27 2006.161.08:22:32.62/valo/01,532.99,yes,locked 2006.161.08:22:32.62/valo/02,572.99,yes,locked 2006.161.08:22:32.62/valo/03,672.99,yes,locked 2006.161.08:22:32.62/valo/04,832.99,yes,locked 2006.161.08:22:32.62/valo/05,652.99,yes,locked 2006.161.08:22:32.62/valo/06,772.99,yes,locked 2006.161.08:22:32.62/valo/07,832.99,yes,locked 2006.161.08:22:32.62/valo/08,852.99,yes,locked 2006.161.08:22:33.71/vb/01,04,usb,yes,28,27 2006.161.08:22:33.71/vb/02,04,usb,yes,30,31 2006.161.08:22:33.71/vb/03,04,usb,yes,26,30 2006.161.08:22:33.71/vb/04,04,usb,yes,27,27 2006.161.08:22:33.71/vb/05,04,usb,yes,26,29 2006.161.08:22:33.71/vb/06,04,usb,yes,27,29 2006.161.08:22:33.71/vb/07,04,usb,yes,29,28 2006.161.08:22:33.71/vb/08,04,usb,yes,26,29 2006.161.08:22:33.95/vblo/01,632.99,yes,locked 2006.161.08:22:33.95/vblo/02,640.99,yes,locked 2006.161.08:22:33.95/vblo/03,656.99,yes,locked 2006.161.08:22:33.95/vblo/04,712.99,yes,locked 2006.161.08:22:33.95/vblo/05,744.99,yes,locked 2006.161.08:22:33.95/vblo/06,752.99,yes,locked 2006.161.08:22:33.95/vblo/07,734.99,yes,locked 2006.161.08:22:33.95/vblo/08,744.99,yes,locked 2006.161.08:22:34.10/vabw/8 2006.161.08:22:34.25/vbbw/8 2006.161.08:22:34.34/xfe/off,on,15.2 2006.161.08:22:34.72/ifatt/23,28,28,28 2006.161.08:22:35.08/fmout-gps/S +4.52E-07 2006.161.08:22:35.12:!2006.161.08:23:30 2006.161.08:23:30.01:data_valid=off 2006.161.08:23:30.01:postob 2006.161.08:23:30.18/cable/+6.4992E-03 2006.161.08:23:30.18/wx/23.99,1002.5,87 2006.161.08:23:31.08/fmout-gps/S +4.52E-07 2006.161.08:23:31.08:scan_name=161-0824,k06161,60 2006.161.08:23:31.09:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.161.08:23:31.14#flagr#flagr/antenna,new-source 2006.161.08:23:32.14:checkk5 2006.161.08:23:32.82/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:23:33.21/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:23:33.60/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:23:34.07/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:23:34.47/chk_obsdata//k5ts1/T1610822??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:23:34.90/chk_obsdata//k5ts2/T1610822??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:23:35.33/chk_obsdata//k5ts3/T1610822??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:23:35.76/chk_obsdata//k5ts4/T1610822??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:23:36.56/k5log//k5ts1_log_newline 2006.161.08:23:37.51/k5log//k5ts2_log_newline 2006.161.08:23:38.27/k5log//k5ts3_log_newline 2006.161.08:23:39.12/k5log//k5ts4_log_newline 2006.161.08:23:39.14/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:23:39.14:4f8m12a=3 2006.161.08:23:39.14$4f8m12a/echo=on 2006.161.08:23:39.14$4f8m12a/pcalon 2006.161.08:23:39.14$pcalon/"no phase cal control is implemented here 2006.161.08:23:39.14$4f8m12a/"tpicd=stop 2006.161.08:23:39.14$4f8m12a/vc4f8 2006.161.08:23:39.14$vc4f8/valo=1,532.99 2006.161.08:23:39.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:23:39.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:23:39.14#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:39.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:39.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:39.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:39.14#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:23:39.14#ibcon#first serial, iclass 19, count 0 2006.161.08:23:39.14#ibcon#enter sib2, iclass 19, count 0 2006.161.08:23:39.14#ibcon#flushed, iclass 19, count 0 2006.161.08:23:39.14#ibcon#about to write, iclass 19, count 0 2006.161.08:23:39.14#ibcon#wrote, iclass 19, count 0 2006.161.08:23:39.14#ibcon#about to read 3, iclass 19, count 0 2006.161.08:23:39.16#ibcon#read 3, iclass 19, count 0 2006.161.08:23:39.16#ibcon#about to read 4, iclass 19, count 0 2006.161.08:23:39.16#ibcon#read 4, iclass 19, count 0 2006.161.08:23:39.16#ibcon#about to read 5, iclass 19, count 0 2006.161.08:23:39.16#ibcon#read 5, iclass 19, count 0 2006.161.08:23:39.16#ibcon#about to read 6, iclass 19, count 0 2006.161.08:23:39.16#ibcon#read 6, iclass 19, count 0 2006.161.08:23:39.16#ibcon#end of sib2, iclass 19, count 0 2006.161.08:23:39.16#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:23:39.16#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:23:39.16#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:23:39.16#ibcon#*before write, iclass 19, count 0 2006.161.08:23:39.16#ibcon#enter sib2, iclass 19, count 0 2006.161.08:23:39.16#ibcon#flushed, iclass 19, count 0 2006.161.08:23:39.16#ibcon#about to write, iclass 19, count 0 2006.161.08:23:39.16#ibcon#wrote, iclass 19, count 0 2006.161.08:23:39.16#ibcon#about to read 3, iclass 19, count 0 2006.161.08:23:39.21#ibcon#read 3, iclass 19, count 0 2006.161.08:23:39.21#ibcon#about to read 4, iclass 19, count 0 2006.161.08:23:39.21#ibcon#read 4, iclass 19, count 0 2006.161.08:23:39.21#ibcon#about to read 5, iclass 19, count 0 2006.161.08:23:39.21#ibcon#read 5, iclass 19, count 0 2006.161.08:23:39.21#ibcon#about to read 6, iclass 19, count 0 2006.161.08:23:39.21#ibcon#read 6, iclass 19, count 0 2006.161.08:23:39.21#ibcon#end of sib2, iclass 19, count 0 2006.161.08:23:39.21#ibcon#*after write, iclass 19, count 0 2006.161.08:23:39.21#ibcon#*before return 0, iclass 19, count 0 2006.161.08:23:39.21#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:39.21#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:39.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:23:39.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:23:39.21$vc4f8/va=1,8 2006.161.08:23:39.21#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:23:39.21#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:23:39.21#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:39.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:39.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:39.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:39.21#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:23:39.21#ibcon#first serial, iclass 21, count 2 2006.161.08:23:39.21#ibcon#enter sib2, iclass 21, count 2 2006.161.08:23:39.21#ibcon#flushed, iclass 21, count 2 2006.161.08:23:39.21#ibcon#about to write, iclass 21, count 2 2006.161.08:23:39.21#ibcon#wrote, iclass 21, count 2 2006.161.08:23:39.21#ibcon#about to read 3, iclass 21, count 2 2006.161.08:23:39.23#ibcon#read 3, iclass 21, count 2 2006.161.08:23:39.23#ibcon#about to read 4, iclass 21, count 2 2006.161.08:23:39.23#ibcon#read 4, iclass 21, count 2 2006.161.08:23:39.23#ibcon#about to read 5, iclass 21, count 2 2006.161.08:23:39.23#ibcon#read 5, iclass 21, count 2 2006.161.08:23:39.23#ibcon#about to read 6, iclass 21, count 2 2006.161.08:23:39.23#ibcon#read 6, iclass 21, count 2 2006.161.08:23:39.23#ibcon#end of sib2, iclass 21, count 2 2006.161.08:23:39.23#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:23:39.23#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:23:39.23#ibcon#[25=AT01-08\r\n] 2006.161.08:23:39.23#ibcon#*before write, iclass 21, count 2 2006.161.08:23:39.23#ibcon#enter sib2, iclass 21, count 2 2006.161.08:23:39.23#ibcon#flushed, iclass 21, count 2 2006.161.08:23:39.23#ibcon#about to write, iclass 21, count 2 2006.161.08:23:39.23#ibcon#wrote, iclass 21, count 2 2006.161.08:23:39.23#ibcon#about to read 3, iclass 21, count 2 2006.161.08:23:39.26#ibcon#read 3, iclass 21, count 2 2006.161.08:23:39.26#ibcon#about to read 4, iclass 21, count 2 2006.161.08:23:39.26#ibcon#read 4, iclass 21, count 2 2006.161.08:23:39.26#ibcon#about to read 5, iclass 21, count 2 2006.161.08:23:39.26#ibcon#read 5, iclass 21, count 2 2006.161.08:23:39.26#ibcon#about to read 6, iclass 21, count 2 2006.161.08:23:39.26#ibcon#read 6, iclass 21, count 2 2006.161.08:23:39.26#ibcon#end of sib2, iclass 21, count 2 2006.161.08:23:39.26#ibcon#*after write, iclass 21, count 2 2006.161.08:23:39.26#ibcon#*before return 0, iclass 21, count 2 2006.161.08:23:39.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:39.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:39.26#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:23:39.26#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:39.26#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:39.38#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:39.38#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:39.38#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:23:39.38#ibcon#first serial, iclass 21, count 0 2006.161.08:23:39.38#ibcon#enter sib2, iclass 21, count 0 2006.161.08:23:39.38#ibcon#flushed, iclass 21, count 0 2006.161.08:23:39.38#ibcon#about to write, iclass 21, count 0 2006.161.08:23:39.38#ibcon#wrote, iclass 21, count 0 2006.161.08:23:39.38#ibcon#about to read 3, iclass 21, count 0 2006.161.08:23:39.40#ibcon#read 3, iclass 21, count 0 2006.161.08:23:39.40#ibcon#about to read 4, iclass 21, count 0 2006.161.08:23:39.40#ibcon#read 4, iclass 21, count 0 2006.161.08:23:39.40#ibcon#about to read 5, iclass 21, count 0 2006.161.08:23:39.40#ibcon#read 5, iclass 21, count 0 2006.161.08:23:39.40#ibcon#about to read 6, iclass 21, count 0 2006.161.08:23:39.40#ibcon#read 6, iclass 21, count 0 2006.161.08:23:39.40#ibcon#end of sib2, iclass 21, count 0 2006.161.08:23:39.40#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:23:39.40#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:23:39.40#ibcon#[25=USB\r\n] 2006.161.08:23:39.40#ibcon#*before write, iclass 21, count 0 2006.161.08:23:39.40#ibcon#enter sib2, iclass 21, count 0 2006.161.08:23:39.40#ibcon#flushed, iclass 21, count 0 2006.161.08:23:39.40#ibcon#about to write, iclass 21, count 0 2006.161.08:23:39.40#ibcon#wrote, iclass 21, count 0 2006.161.08:23:39.40#ibcon#about to read 3, iclass 21, count 0 2006.161.08:23:39.43#ibcon#read 3, iclass 21, count 0 2006.161.08:23:39.43#ibcon#about to read 4, iclass 21, count 0 2006.161.08:23:39.43#ibcon#read 4, iclass 21, count 0 2006.161.08:23:39.43#ibcon#about to read 5, iclass 21, count 0 2006.161.08:23:39.43#ibcon#read 5, iclass 21, count 0 2006.161.08:23:39.43#ibcon#about to read 6, iclass 21, count 0 2006.161.08:23:39.43#ibcon#read 6, iclass 21, count 0 2006.161.08:23:39.43#ibcon#end of sib2, iclass 21, count 0 2006.161.08:23:39.43#ibcon#*after write, iclass 21, count 0 2006.161.08:23:39.43#ibcon#*before return 0, iclass 21, count 0 2006.161.08:23:39.43#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:39.43#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:39.43#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:23:39.43#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:23:39.43$vc4f8/valo=2,572.99 2006.161.08:23:39.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:23:39.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:23:39.43#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:39.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:39.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:39.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:39.43#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:23:39.43#ibcon#first serial, iclass 23, count 0 2006.161.08:23:39.43#ibcon#enter sib2, iclass 23, count 0 2006.161.08:23:39.43#ibcon#flushed, iclass 23, count 0 2006.161.08:23:39.43#ibcon#about to write, iclass 23, count 0 2006.161.08:23:39.43#ibcon#wrote, iclass 23, count 0 2006.161.08:23:39.43#ibcon#about to read 3, iclass 23, count 0 2006.161.08:23:39.45#ibcon#read 3, iclass 23, count 0 2006.161.08:23:39.45#ibcon#about to read 4, iclass 23, count 0 2006.161.08:23:39.45#ibcon#read 4, iclass 23, count 0 2006.161.08:23:39.45#ibcon#about to read 5, iclass 23, count 0 2006.161.08:23:39.45#ibcon#read 5, iclass 23, count 0 2006.161.08:23:39.45#ibcon#about to read 6, iclass 23, count 0 2006.161.08:23:39.45#ibcon#read 6, iclass 23, count 0 2006.161.08:23:39.45#ibcon#end of sib2, iclass 23, count 0 2006.161.08:23:39.45#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:23:39.45#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:23:39.45#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:23:39.45#ibcon#*before write, iclass 23, count 0 2006.161.08:23:39.45#ibcon#enter sib2, iclass 23, count 0 2006.161.08:23:39.45#ibcon#flushed, iclass 23, count 0 2006.161.08:23:39.45#ibcon#about to write, iclass 23, count 0 2006.161.08:23:39.45#ibcon#wrote, iclass 23, count 0 2006.161.08:23:39.45#ibcon#about to read 3, iclass 23, count 0 2006.161.08:23:39.49#ibcon#read 3, iclass 23, count 0 2006.161.08:23:39.49#ibcon#about to read 4, iclass 23, count 0 2006.161.08:23:39.49#ibcon#read 4, iclass 23, count 0 2006.161.08:23:39.49#ibcon#about to read 5, iclass 23, count 0 2006.161.08:23:39.49#ibcon#read 5, iclass 23, count 0 2006.161.08:23:39.49#ibcon#about to read 6, iclass 23, count 0 2006.161.08:23:39.49#ibcon#read 6, iclass 23, count 0 2006.161.08:23:39.49#ibcon#end of sib2, iclass 23, count 0 2006.161.08:23:39.49#ibcon#*after write, iclass 23, count 0 2006.161.08:23:39.49#ibcon#*before return 0, iclass 23, count 0 2006.161.08:23:39.49#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:39.49#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:39.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:23:39.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:23:39.49$vc4f8/va=2,7 2006.161.08:23:39.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.08:23:39.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.08:23:39.49#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:39.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:39.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:39.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:39.55#ibcon#enter wrdev, iclass 25, count 2 2006.161.08:23:39.55#ibcon#first serial, iclass 25, count 2 2006.161.08:23:39.55#ibcon#enter sib2, iclass 25, count 2 2006.161.08:23:39.55#ibcon#flushed, iclass 25, count 2 2006.161.08:23:39.55#ibcon#about to write, iclass 25, count 2 2006.161.08:23:39.55#ibcon#wrote, iclass 25, count 2 2006.161.08:23:39.55#ibcon#about to read 3, iclass 25, count 2 2006.161.08:23:39.58#ibcon#read 3, iclass 25, count 2 2006.161.08:23:39.58#ibcon#about to read 4, iclass 25, count 2 2006.161.08:23:39.58#ibcon#read 4, iclass 25, count 2 2006.161.08:23:39.58#ibcon#about to read 5, iclass 25, count 2 2006.161.08:23:39.58#ibcon#read 5, iclass 25, count 2 2006.161.08:23:39.58#ibcon#about to read 6, iclass 25, count 2 2006.161.08:23:39.58#ibcon#read 6, iclass 25, count 2 2006.161.08:23:39.58#ibcon#end of sib2, iclass 25, count 2 2006.161.08:23:39.58#ibcon#*mode == 0, iclass 25, count 2 2006.161.08:23:39.58#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.08:23:39.58#ibcon#[25=AT02-07\r\n] 2006.161.08:23:39.58#ibcon#*before write, iclass 25, count 2 2006.161.08:23:39.58#ibcon#enter sib2, iclass 25, count 2 2006.161.08:23:39.58#ibcon#flushed, iclass 25, count 2 2006.161.08:23:39.58#ibcon#about to write, iclass 25, count 2 2006.161.08:23:39.58#ibcon#wrote, iclass 25, count 2 2006.161.08:23:39.58#ibcon#about to read 3, iclass 25, count 2 2006.161.08:23:39.61#ibcon#read 3, iclass 25, count 2 2006.161.08:23:39.61#ibcon#about to read 4, iclass 25, count 2 2006.161.08:23:39.61#ibcon#read 4, iclass 25, count 2 2006.161.08:23:39.61#ibcon#about to read 5, iclass 25, count 2 2006.161.08:23:39.61#ibcon#read 5, iclass 25, count 2 2006.161.08:23:39.61#ibcon#about to read 6, iclass 25, count 2 2006.161.08:23:39.61#ibcon#read 6, iclass 25, count 2 2006.161.08:23:39.61#ibcon#end of sib2, iclass 25, count 2 2006.161.08:23:39.61#ibcon#*after write, iclass 25, count 2 2006.161.08:23:39.61#ibcon#*before return 0, iclass 25, count 2 2006.161.08:23:39.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:39.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:39.61#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.08:23:39.61#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:39.61#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:39.73#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:39.73#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:39.73#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:23:39.73#ibcon#first serial, iclass 25, count 0 2006.161.08:23:39.73#ibcon#enter sib2, iclass 25, count 0 2006.161.08:23:39.73#ibcon#flushed, iclass 25, count 0 2006.161.08:23:39.73#ibcon#about to write, iclass 25, count 0 2006.161.08:23:39.73#ibcon#wrote, iclass 25, count 0 2006.161.08:23:39.73#ibcon#about to read 3, iclass 25, count 0 2006.161.08:23:39.75#ibcon#read 3, iclass 25, count 0 2006.161.08:23:39.75#ibcon#about to read 4, iclass 25, count 0 2006.161.08:23:39.75#ibcon#read 4, iclass 25, count 0 2006.161.08:23:39.75#ibcon#about to read 5, iclass 25, count 0 2006.161.08:23:39.75#ibcon#read 5, iclass 25, count 0 2006.161.08:23:39.75#ibcon#about to read 6, iclass 25, count 0 2006.161.08:23:39.75#ibcon#read 6, iclass 25, count 0 2006.161.08:23:39.75#ibcon#end of sib2, iclass 25, count 0 2006.161.08:23:39.75#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:23:39.75#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:23:39.75#ibcon#[25=USB\r\n] 2006.161.08:23:39.75#ibcon#*before write, iclass 25, count 0 2006.161.08:23:39.75#ibcon#enter sib2, iclass 25, count 0 2006.161.08:23:39.75#ibcon#flushed, iclass 25, count 0 2006.161.08:23:39.75#ibcon#about to write, iclass 25, count 0 2006.161.08:23:39.75#ibcon#wrote, iclass 25, count 0 2006.161.08:23:39.75#ibcon#about to read 3, iclass 25, count 0 2006.161.08:23:39.78#ibcon#read 3, iclass 25, count 0 2006.161.08:23:39.78#ibcon#about to read 4, iclass 25, count 0 2006.161.08:23:39.78#ibcon#read 4, iclass 25, count 0 2006.161.08:23:39.78#ibcon#about to read 5, iclass 25, count 0 2006.161.08:23:39.78#ibcon#read 5, iclass 25, count 0 2006.161.08:23:39.78#ibcon#about to read 6, iclass 25, count 0 2006.161.08:23:39.78#ibcon#read 6, iclass 25, count 0 2006.161.08:23:39.78#ibcon#end of sib2, iclass 25, count 0 2006.161.08:23:39.78#ibcon#*after write, iclass 25, count 0 2006.161.08:23:39.78#ibcon#*before return 0, iclass 25, count 0 2006.161.08:23:39.78#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:39.78#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:39.78#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:23:39.78#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:23:39.78$vc4f8/valo=3,672.99 2006.161.08:23:39.78#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.08:23:39.78#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.08:23:39.78#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:39.78#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:39.78#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:39.78#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:39.78#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:23:39.78#ibcon#first serial, iclass 27, count 0 2006.161.08:23:39.78#ibcon#enter sib2, iclass 27, count 0 2006.161.08:23:39.78#ibcon#flushed, iclass 27, count 0 2006.161.08:23:39.78#ibcon#about to write, iclass 27, count 0 2006.161.08:23:39.78#ibcon#wrote, iclass 27, count 0 2006.161.08:23:39.78#ibcon#about to read 3, iclass 27, count 0 2006.161.08:23:39.80#ibcon#read 3, iclass 27, count 0 2006.161.08:23:39.80#ibcon#about to read 4, iclass 27, count 0 2006.161.08:23:39.80#ibcon#read 4, iclass 27, count 0 2006.161.08:23:39.80#ibcon#about to read 5, iclass 27, count 0 2006.161.08:23:39.80#ibcon#read 5, iclass 27, count 0 2006.161.08:23:39.80#ibcon#about to read 6, iclass 27, count 0 2006.161.08:23:39.80#ibcon#read 6, iclass 27, count 0 2006.161.08:23:39.80#ibcon#end of sib2, iclass 27, count 0 2006.161.08:23:39.80#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:23:39.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:23:39.80#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:23:39.80#ibcon#*before write, iclass 27, count 0 2006.161.08:23:39.80#ibcon#enter sib2, iclass 27, count 0 2006.161.08:23:39.80#ibcon#flushed, iclass 27, count 0 2006.161.08:23:39.80#ibcon#about to write, iclass 27, count 0 2006.161.08:23:39.80#ibcon#wrote, iclass 27, count 0 2006.161.08:23:39.80#ibcon#about to read 3, iclass 27, count 0 2006.161.08:23:39.84#ibcon#read 3, iclass 27, count 0 2006.161.08:23:39.84#ibcon#about to read 4, iclass 27, count 0 2006.161.08:23:39.84#ibcon#read 4, iclass 27, count 0 2006.161.08:23:39.84#ibcon#about to read 5, iclass 27, count 0 2006.161.08:23:39.84#ibcon#read 5, iclass 27, count 0 2006.161.08:23:39.84#ibcon#about to read 6, iclass 27, count 0 2006.161.08:23:39.84#ibcon#read 6, iclass 27, count 0 2006.161.08:23:39.84#ibcon#end of sib2, iclass 27, count 0 2006.161.08:23:39.84#ibcon#*after write, iclass 27, count 0 2006.161.08:23:39.84#ibcon#*before return 0, iclass 27, count 0 2006.161.08:23:39.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:39.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:39.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:23:39.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:23:39.84$vc4f8/va=3,6 2006.161.08:23:39.84#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.08:23:39.84#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.08:23:39.84#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:39.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:39.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:39.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:39.90#ibcon#enter wrdev, iclass 29, count 2 2006.161.08:23:39.90#ibcon#first serial, iclass 29, count 2 2006.161.08:23:39.90#ibcon#enter sib2, iclass 29, count 2 2006.161.08:23:39.90#ibcon#flushed, iclass 29, count 2 2006.161.08:23:39.90#ibcon#about to write, iclass 29, count 2 2006.161.08:23:39.90#ibcon#wrote, iclass 29, count 2 2006.161.08:23:39.90#ibcon#about to read 3, iclass 29, count 2 2006.161.08:23:39.92#ibcon#read 3, iclass 29, count 2 2006.161.08:23:39.92#ibcon#about to read 4, iclass 29, count 2 2006.161.08:23:39.92#ibcon#read 4, iclass 29, count 2 2006.161.08:23:39.92#ibcon#about to read 5, iclass 29, count 2 2006.161.08:23:39.92#ibcon#read 5, iclass 29, count 2 2006.161.08:23:39.92#ibcon#about to read 6, iclass 29, count 2 2006.161.08:23:39.92#ibcon#read 6, iclass 29, count 2 2006.161.08:23:39.92#ibcon#end of sib2, iclass 29, count 2 2006.161.08:23:39.92#ibcon#*mode == 0, iclass 29, count 2 2006.161.08:23:39.92#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.08:23:39.92#ibcon#[25=AT03-06\r\n] 2006.161.08:23:39.92#ibcon#*before write, iclass 29, count 2 2006.161.08:23:39.92#ibcon#enter sib2, iclass 29, count 2 2006.161.08:23:39.92#ibcon#flushed, iclass 29, count 2 2006.161.08:23:39.92#ibcon#about to write, iclass 29, count 2 2006.161.08:23:39.92#ibcon#wrote, iclass 29, count 2 2006.161.08:23:39.92#ibcon#about to read 3, iclass 29, count 2 2006.161.08:23:39.95#ibcon#read 3, iclass 29, count 2 2006.161.08:23:39.95#ibcon#about to read 4, iclass 29, count 2 2006.161.08:23:39.95#ibcon#read 4, iclass 29, count 2 2006.161.08:23:39.95#ibcon#about to read 5, iclass 29, count 2 2006.161.08:23:39.95#ibcon#read 5, iclass 29, count 2 2006.161.08:23:39.95#ibcon#about to read 6, iclass 29, count 2 2006.161.08:23:39.95#ibcon#read 6, iclass 29, count 2 2006.161.08:23:39.95#ibcon#end of sib2, iclass 29, count 2 2006.161.08:23:39.95#ibcon#*after write, iclass 29, count 2 2006.161.08:23:39.95#ibcon#*before return 0, iclass 29, count 2 2006.161.08:23:39.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:39.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:39.95#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.08:23:39.95#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:39.95#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:40.07#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:40.07#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:40.07#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:23:40.07#ibcon#first serial, iclass 29, count 0 2006.161.08:23:40.07#ibcon#enter sib2, iclass 29, count 0 2006.161.08:23:40.07#ibcon#flushed, iclass 29, count 0 2006.161.08:23:40.07#ibcon#about to write, iclass 29, count 0 2006.161.08:23:40.07#ibcon#wrote, iclass 29, count 0 2006.161.08:23:40.07#ibcon#about to read 3, iclass 29, count 0 2006.161.08:23:40.09#ibcon#read 3, iclass 29, count 0 2006.161.08:23:40.09#ibcon#about to read 4, iclass 29, count 0 2006.161.08:23:40.09#ibcon#read 4, iclass 29, count 0 2006.161.08:23:40.09#ibcon#about to read 5, iclass 29, count 0 2006.161.08:23:40.09#ibcon#read 5, iclass 29, count 0 2006.161.08:23:40.09#ibcon#about to read 6, iclass 29, count 0 2006.161.08:23:40.09#ibcon#read 6, iclass 29, count 0 2006.161.08:23:40.09#ibcon#end of sib2, iclass 29, count 0 2006.161.08:23:40.09#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:23:40.09#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:23:40.09#ibcon#[25=USB\r\n] 2006.161.08:23:40.09#ibcon#*before write, iclass 29, count 0 2006.161.08:23:40.09#ibcon#enter sib2, iclass 29, count 0 2006.161.08:23:40.09#ibcon#flushed, iclass 29, count 0 2006.161.08:23:40.09#ibcon#about to write, iclass 29, count 0 2006.161.08:23:40.09#ibcon#wrote, iclass 29, count 0 2006.161.08:23:40.09#ibcon#about to read 3, iclass 29, count 0 2006.161.08:23:40.12#ibcon#read 3, iclass 29, count 0 2006.161.08:23:40.12#ibcon#about to read 4, iclass 29, count 0 2006.161.08:23:40.12#ibcon#read 4, iclass 29, count 0 2006.161.08:23:40.12#ibcon#about to read 5, iclass 29, count 0 2006.161.08:23:40.12#ibcon#read 5, iclass 29, count 0 2006.161.08:23:40.12#ibcon#about to read 6, iclass 29, count 0 2006.161.08:23:40.12#ibcon#read 6, iclass 29, count 0 2006.161.08:23:40.12#ibcon#end of sib2, iclass 29, count 0 2006.161.08:23:40.12#ibcon#*after write, iclass 29, count 0 2006.161.08:23:40.12#ibcon#*before return 0, iclass 29, count 0 2006.161.08:23:40.12#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:40.12#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:40.12#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:23:40.12#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:23:40.12$vc4f8/valo=4,832.99 2006.161.08:23:40.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:23:40.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:23:40.12#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:40.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:40.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:40.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:40.12#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:23:40.12#ibcon#first serial, iclass 31, count 0 2006.161.08:23:40.12#ibcon#enter sib2, iclass 31, count 0 2006.161.08:23:40.12#ibcon#flushed, iclass 31, count 0 2006.161.08:23:40.12#ibcon#about to write, iclass 31, count 0 2006.161.08:23:40.12#ibcon#wrote, iclass 31, count 0 2006.161.08:23:40.12#ibcon#about to read 3, iclass 31, count 0 2006.161.08:23:40.14#ibcon#read 3, iclass 31, count 0 2006.161.08:23:40.14#ibcon#about to read 4, iclass 31, count 0 2006.161.08:23:40.14#ibcon#read 4, iclass 31, count 0 2006.161.08:23:40.14#ibcon#about to read 5, iclass 31, count 0 2006.161.08:23:40.14#ibcon#read 5, iclass 31, count 0 2006.161.08:23:40.14#ibcon#about to read 6, iclass 31, count 0 2006.161.08:23:40.14#ibcon#read 6, iclass 31, count 0 2006.161.08:23:40.14#ibcon#end of sib2, iclass 31, count 0 2006.161.08:23:40.14#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:23:40.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:23:40.14#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:23:40.14#ibcon#*before write, iclass 31, count 0 2006.161.08:23:40.14#ibcon#enter sib2, iclass 31, count 0 2006.161.08:23:40.14#ibcon#flushed, iclass 31, count 0 2006.161.08:23:40.14#ibcon#about to write, iclass 31, count 0 2006.161.08:23:40.14#ibcon#wrote, iclass 31, count 0 2006.161.08:23:40.14#ibcon#about to read 3, iclass 31, count 0 2006.161.08:23:40.18#ibcon#read 3, iclass 31, count 0 2006.161.08:23:40.18#ibcon#about to read 4, iclass 31, count 0 2006.161.08:23:40.18#ibcon#read 4, iclass 31, count 0 2006.161.08:23:40.18#ibcon#about to read 5, iclass 31, count 0 2006.161.08:23:40.18#ibcon#read 5, iclass 31, count 0 2006.161.08:23:40.18#ibcon#about to read 6, iclass 31, count 0 2006.161.08:23:40.18#ibcon#read 6, iclass 31, count 0 2006.161.08:23:40.18#ibcon#end of sib2, iclass 31, count 0 2006.161.08:23:40.18#ibcon#*after write, iclass 31, count 0 2006.161.08:23:40.18#ibcon#*before return 0, iclass 31, count 0 2006.161.08:23:40.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:40.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:40.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:23:40.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:23:40.18$vc4f8/va=4,7 2006.161.08:23:40.18#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.08:23:40.18#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.08:23:40.18#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:40.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:40.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:40.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:40.24#ibcon#enter wrdev, iclass 33, count 2 2006.161.08:23:40.24#ibcon#first serial, iclass 33, count 2 2006.161.08:23:40.24#ibcon#enter sib2, iclass 33, count 2 2006.161.08:23:40.24#ibcon#flushed, iclass 33, count 2 2006.161.08:23:40.24#ibcon#about to write, iclass 33, count 2 2006.161.08:23:40.24#ibcon#wrote, iclass 33, count 2 2006.161.08:23:40.24#ibcon#about to read 3, iclass 33, count 2 2006.161.08:23:40.26#ibcon#read 3, iclass 33, count 2 2006.161.08:23:40.26#ibcon#about to read 4, iclass 33, count 2 2006.161.08:23:40.26#ibcon#read 4, iclass 33, count 2 2006.161.08:23:40.26#ibcon#about to read 5, iclass 33, count 2 2006.161.08:23:40.26#ibcon#read 5, iclass 33, count 2 2006.161.08:23:40.26#ibcon#about to read 6, iclass 33, count 2 2006.161.08:23:40.26#ibcon#read 6, iclass 33, count 2 2006.161.08:23:40.26#ibcon#end of sib2, iclass 33, count 2 2006.161.08:23:40.26#ibcon#*mode == 0, iclass 33, count 2 2006.161.08:23:40.26#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.08:23:40.26#ibcon#[25=AT04-07\r\n] 2006.161.08:23:40.26#ibcon#*before write, iclass 33, count 2 2006.161.08:23:40.26#ibcon#enter sib2, iclass 33, count 2 2006.161.08:23:40.26#ibcon#flushed, iclass 33, count 2 2006.161.08:23:40.26#ibcon#about to write, iclass 33, count 2 2006.161.08:23:40.26#ibcon#wrote, iclass 33, count 2 2006.161.08:23:40.26#ibcon#about to read 3, iclass 33, count 2 2006.161.08:23:40.29#ibcon#read 3, iclass 33, count 2 2006.161.08:23:40.29#ibcon#about to read 4, iclass 33, count 2 2006.161.08:23:40.29#ibcon#read 4, iclass 33, count 2 2006.161.08:23:40.29#ibcon#about to read 5, iclass 33, count 2 2006.161.08:23:40.29#ibcon#read 5, iclass 33, count 2 2006.161.08:23:40.29#ibcon#about to read 6, iclass 33, count 2 2006.161.08:23:40.29#ibcon#read 6, iclass 33, count 2 2006.161.08:23:40.29#ibcon#end of sib2, iclass 33, count 2 2006.161.08:23:40.29#ibcon#*after write, iclass 33, count 2 2006.161.08:23:40.29#ibcon#*before return 0, iclass 33, count 2 2006.161.08:23:40.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:40.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:40.29#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.08:23:40.29#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:40.29#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:40.41#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:40.41#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:40.41#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:23:40.41#ibcon#first serial, iclass 33, count 0 2006.161.08:23:40.41#ibcon#enter sib2, iclass 33, count 0 2006.161.08:23:40.41#ibcon#flushed, iclass 33, count 0 2006.161.08:23:40.41#ibcon#about to write, iclass 33, count 0 2006.161.08:23:40.41#ibcon#wrote, iclass 33, count 0 2006.161.08:23:40.41#ibcon#about to read 3, iclass 33, count 0 2006.161.08:23:40.43#ibcon#read 3, iclass 33, count 0 2006.161.08:23:40.43#ibcon#about to read 4, iclass 33, count 0 2006.161.08:23:40.43#ibcon#read 4, iclass 33, count 0 2006.161.08:23:40.43#ibcon#about to read 5, iclass 33, count 0 2006.161.08:23:40.43#ibcon#read 5, iclass 33, count 0 2006.161.08:23:40.43#ibcon#about to read 6, iclass 33, count 0 2006.161.08:23:40.43#ibcon#read 6, iclass 33, count 0 2006.161.08:23:40.43#ibcon#end of sib2, iclass 33, count 0 2006.161.08:23:40.43#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:23:40.43#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:23:40.43#ibcon#[25=USB\r\n] 2006.161.08:23:40.43#ibcon#*before write, iclass 33, count 0 2006.161.08:23:40.43#ibcon#enter sib2, iclass 33, count 0 2006.161.08:23:40.43#ibcon#flushed, iclass 33, count 0 2006.161.08:23:40.43#ibcon#about to write, iclass 33, count 0 2006.161.08:23:40.43#ibcon#wrote, iclass 33, count 0 2006.161.08:23:40.43#ibcon#about to read 3, iclass 33, count 0 2006.161.08:23:40.46#ibcon#read 3, iclass 33, count 0 2006.161.08:23:40.46#ibcon#about to read 4, iclass 33, count 0 2006.161.08:23:40.46#ibcon#read 4, iclass 33, count 0 2006.161.08:23:40.46#ibcon#about to read 5, iclass 33, count 0 2006.161.08:23:40.46#ibcon#read 5, iclass 33, count 0 2006.161.08:23:40.46#ibcon#about to read 6, iclass 33, count 0 2006.161.08:23:40.46#ibcon#read 6, iclass 33, count 0 2006.161.08:23:40.46#ibcon#end of sib2, iclass 33, count 0 2006.161.08:23:40.46#ibcon#*after write, iclass 33, count 0 2006.161.08:23:40.46#ibcon#*before return 0, iclass 33, count 0 2006.161.08:23:40.46#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:40.46#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:40.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:23:40.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:23:40.46$vc4f8/valo=5,652.99 2006.161.08:23:40.46#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.08:23:40.46#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.08:23:40.46#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:40.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:40.46#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:40.46#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:40.46#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:23:40.46#ibcon#first serial, iclass 35, count 0 2006.161.08:23:40.46#ibcon#enter sib2, iclass 35, count 0 2006.161.08:23:40.46#ibcon#flushed, iclass 35, count 0 2006.161.08:23:40.46#ibcon#about to write, iclass 35, count 0 2006.161.08:23:40.46#ibcon#wrote, iclass 35, count 0 2006.161.08:23:40.46#ibcon#about to read 3, iclass 35, count 0 2006.161.08:23:40.48#ibcon#read 3, iclass 35, count 0 2006.161.08:23:40.48#ibcon#about to read 4, iclass 35, count 0 2006.161.08:23:40.48#ibcon#read 4, iclass 35, count 0 2006.161.08:23:40.48#ibcon#about to read 5, iclass 35, count 0 2006.161.08:23:40.48#ibcon#read 5, iclass 35, count 0 2006.161.08:23:40.48#ibcon#about to read 6, iclass 35, count 0 2006.161.08:23:40.48#ibcon#read 6, iclass 35, count 0 2006.161.08:23:40.48#ibcon#end of sib2, iclass 35, count 0 2006.161.08:23:40.48#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:23:40.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:23:40.48#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:23:40.48#ibcon#*before write, iclass 35, count 0 2006.161.08:23:40.48#ibcon#enter sib2, iclass 35, count 0 2006.161.08:23:40.48#ibcon#flushed, iclass 35, count 0 2006.161.08:23:40.48#ibcon#about to write, iclass 35, count 0 2006.161.08:23:40.48#ibcon#wrote, iclass 35, count 0 2006.161.08:23:40.48#ibcon#about to read 3, iclass 35, count 0 2006.161.08:23:40.52#ibcon#read 3, iclass 35, count 0 2006.161.08:23:40.52#ibcon#about to read 4, iclass 35, count 0 2006.161.08:23:40.52#ibcon#read 4, iclass 35, count 0 2006.161.08:23:40.52#ibcon#about to read 5, iclass 35, count 0 2006.161.08:23:40.52#ibcon#read 5, iclass 35, count 0 2006.161.08:23:40.52#ibcon#about to read 6, iclass 35, count 0 2006.161.08:23:40.52#ibcon#read 6, iclass 35, count 0 2006.161.08:23:40.52#ibcon#end of sib2, iclass 35, count 0 2006.161.08:23:40.52#ibcon#*after write, iclass 35, count 0 2006.161.08:23:40.52#ibcon#*before return 0, iclass 35, count 0 2006.161.08:23:40.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:40.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:40.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:23:40.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:23:40.52$vc4f8/va=5,7 2006.161.08:23:40.52#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.08:23:40.52#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.08:23:40.52#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:40.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:40.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:40.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:40.58#ibcon#enter wrdev, iclass 37, count 2 2006.161.08:23:40.58#ibcon#first serial, iclass 37, count 2 2006.161.08:23:40.58#ibcon#enter sib2, iclass 37, count 2 2006.161.08:23:40.58#ibcon#flushed, iclass 37, count 2 2006.161.08:23:40.58#ibcon#about to write, iclass 37, count 2 2006.161.08:23:40.58#ibcon#wrote, iclass 37, count 2 2006.161.08:23:40.58#ibcon#about to read 3, iclass 37, count 2 2006.161.08:23:40.61#ibcon#read 3, iclass 37, count 2 2006.161.08:23:40.61#ibcon#about to read 4, iclass 37, count 2 2006.161.08:23:40.61#ibcon#read 4, iclass 37, count 2 2006.161.08:23:40.61#ibcon#about to read 5, iclass 37, count 2 2006.161.08:23:40.61#ibcon#read 5, iclass 37, count 2 2006.161.08:23:40.61#ibcon#about to read 6, iclass 37, count 2 2006.161.08:23:40.61#ibcon#read 6, iclass 37, count 2 2006.161.08:23:40.61#ibcon#end of sib2, iclass 37, count 2 2006.161.08:23:40.61#ibcon#*mode == 0, iclass 37, count 2 2006.161.08:23:40.61#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.08:23:40.61#ibcon#[25=AT05-07\r\n] 2006.161.08:23:40.61#ibcon#*before write, iclass 37, count 2 2006.161.08:23:40.61#ibcon#enter sib2, iclass 37, count 2 2006.161.08:23:40.61#ibcon#flushed, iclass 37, count 2 2006.161.08:23:40.61#ibcon#about to write, iclass 37, count 2 2006.161.08:23:40.61#ibcon#wrote, iclass 37, count 2 2006.161.08:23:40.61#ibcon#about to read 3, iclass 37, count 2 2006.161.08:23:40.64#ibcon#read 3, iclass 37, count 2 2006.161.08:23:40.64#ibcon#about to read 4, iclass 37, count 2 2006.161.08:23:40.64#ibcon#read 4, iclass 37, count 2 2006.161.08:23:40.64#ibcon#about to read 5, iclass 37, count 2 2006.161.08:23:40.64#ibcon#read 5, iclass 37, count 2 2006.161.08:23:40.64#ibcon#about to read 6, iclass 37, count 2 2006.161.08:23:40.64#ibcon#read 6, iclass 37, count 2 2006.161.08:23:40.64#ibcon#end of sib2, iclass 37, count 2 2006.161.08:23:40.64#ibcon#*after write, iclass 37, count 2 2006.161.08:23:40.64#ibcon#*before return 0, iclass 37, count 2 2006.161.08:23:40.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:40.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:40.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.08:23:40.64#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:40.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:40.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:40.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:40.76#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:23:40.76#ibcon#first serial, iclass 37, count 0 2006.161.08:23:40.76#ibcon#enter sib2, iclass 37, count 0 2006.161.08:23:40.76#ibcon#flushed, iclass 37, count 0 2006.161.08:23:40.76#ibcon#about to write, iclass 37, count 0 2006.161.08:23:40.76#ibcon#wrote, iclass 37, count 0 2006.161.08:23:40.76#ibcon#about to read 3, iclass 37, count 0 2006.161.08:23:40.78#ibcon#read 3, iclass 37, count 0 2006.161.08:23:40.78#ibcon#about to read 4, iclass 37, count 0 2006.161.08:23:40.78#ibcon#read 4, iclass 37, count 0 2006.161.08:23:40.78#ibcon#about to read 5, iclass 37, count 0 2006.161.08:23:40.78#ibcon#read 5, iclass 37, count 0 2006.161.08:23:40.78#ibcon#about to read 6, iclass 37, count 0 2006.161.08:23:40.78#ibcon#read 6, iclass 37, count 0 2006.161.08:23:40.78#ibcon#end of sib2, iclass 37, count 0 2006.161.08:23:40.78#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:23:40.78#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:23:40.78#ibcon#[25=USB\r\n] 2006.161.08:23:40.78#ibcon#*before write, iclass 37, count 0 2006.161.08:23:40.78#ibcon#enter sib2, iclass 37, count 0 2006.161.08:23:40.78#ibcon#flushed, iclass 37, count 0 2006.161.08:23:40.78#ibcon#about to write, iclass 37, count 0 2006.161.08:23:40.78#ibcon#wrote, iclass 37, count 0 2006.161.08:23:40.78#ibcon#about to read 3, iclass 37, count 0 2006.161.08:23:40.81#ibcon#read 3, iclass 37, count 0 2006.161.08:23:40.81#ibcon#about to read 4, iclass 37, count 0 2006.161.08:23:40.81#ibcon#read 4, iclass 37, count 0 2006.161.08:23:40.81#ibcon#about to read 5, iclass 37, count 0 2006.161.08:23:40.81#ibcon#read 5, iclass 37, count 0 2006.161.08:23:40.81#ibcon#about to read 6, iclass 37, count 0 2006.161.08:23:40.81#ibcon#read 6, iclass 37, count 0 2006.161.08:23:40.81#ibcon#end of sib2, iclass 37, count 0 2006.161.08:23:40.81#ibcon#*after write, iclass 37, count 0 2006.161.08:23:40.81#ibcon#*before return 0, iclass 37, count 0 2006.161.08:23:40.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:40.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:40.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:23:40.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:23:40.81$vc4f8/valo=6,772.99 2006.161.08:23:40.81#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.08:23:40.81#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.08:23:40.81#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:40.81#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:40.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:40.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:40.81#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:23:40.81#ibcon#first serial, iclass 39, count 0 2006.161.08:23:40.81#ibcon#enter sib2, iclass 39, count 0 2006.161.08:23:40.81#ibcon#flushed, iclass 39, count 0 2006.161.08:23:40.81#ibcon#about to write, iclass 39, count 0 2006.161.08:23:40.81#ibcon#wrote, iclass 39, count 0 2006.161.08:23:40.81#ibcon#about to read 3, iclass 39, count 0 2006.161.08:23:40.83#ibcon#read 3, iclass 39, count 0 2006.161.08:23:40.83#ibcon#about to read 4, iclass 39, count 0 2006.161.08:23:40.83#ibcon#read 4, iclass 39, count 0 2006.161.08:23:40.83#ibcon#about to read 5, iclass 39, count 0 2006.161.08:23:40.83#ibcon#read 5, iclass 39, count 0 2006.161.08:23:40.83#ibcon#about to read 6, iclass 39, count 0 2006.161.08:23:40.83#ibcon#read 6, iclass 39, count 0 2006.161.08:23:40.83#ibcon#end of sib2, iclass 39, count 0 2006.161.08:23:40.83#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:23:40.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:23:40.83#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:23:40.83#ibcon#*before write, iclass 39, count 0 2006.161.08:23:40.83#ibcon#enter sib2, iclass 39, count 0 2006.161.08:23:40.83#ibcon#flushed, iclass 39, count 0 2006.161.08:23:40.83#ibcon#about to write, iclass 39, count 0 2006.161.08:23:40.83#ibcon#wrote, iclass 39, count 0 2006.161.08:23:40.83#ibcon#about to read 3, iclass 39, count 0 2006.161.08:23:40.87#ibcon#read 3, iclass 39, count 0 2006.161.08:23:40.87#ibcon#about to read 4, iclass 39, count 0 2006.161.08:23:40.87#ibcon#read 4, iclass 39, count 0 2006.161.08:23:40.87#ibcon#about to read 5, iclass 39, count 0 2006.161.08:23:40.87#ibcon#read 5, iclass 39, count 0 2006.161.08:23:40.87#ibcon#about to read 6, iclass 39, count 0 2006.161.08:23:40.87#ibcon#read 6, iclass 39, count 0 2006.161.08:23:40.87#ibcon#end of sib2, iclass 39, count 0 2006.161.08:23:40.87#ibcon#*after write, iclass 39, count 0 2006.161.08:23:40.87#ibcon#*before return 0, iclass 39, count 0 2006.161.08:23:40.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:40.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:40.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:23:40.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:23:40.87$vc4f8/va=6,6 2006.161.08:23:40.87#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.08:23:40.87#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.08:23:40.87#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:40.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:40.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:40.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:40.93#ibcon#enter wrdev, iclass 3, count 2 2006.161.08:23:40.93#ibcon#first serial, iclass 3, count 2 2006.161.08:23:40.93#ibcon#enter sib2, iclass 3, count 2 2006.161.08:23:40.93#ibcon#flushed, iclass 3, count 2 2006.161.08:23:40.93#ibcon#about to write, iclass 3, count 2 2006.161.08:23:40.93#ibcon#wrote, iclass 3, count 2 2006.161.08:23:40.93#ibcon#about to read 3, iclass 3, count 2 2006.161.08:23:40.95#ibcon#read 3, iclass 3, count 2 2006.161.08:23:40.95#ibcon#about to read 4, iclass 3, count 2 2006.161.08:23:40.95#ibcon#read 4, iclass 3, count 2 2006.161.08:23:40.95#ibcon#about to read 5, iclass 3, count 2 2006.161.08:23:40.95#ibcon#read 5, iclass 3, count 2 2006.161.08:23:40.95#ibcon#about to read 6, iclass 3, count 2 2006.161.08:23:40.95#ibcon#read 6, iclass 3, count 2 2006.161.08:23:40.95#ibcon#end of sib2, iclass 3, count 2 2006.161.08:23:40.95#ibcon#*mode == 0, iclass 3, count 2 2006.161.08:23:40.95#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.08:23:40.95#ibcon#[25=AT06-06\r\n] 2006.161.08:23:40.95#ibcon#*before write, iclass 3, count 2 2006.161.08:23:40.95#ibcon#enter sib2, iclass 3, count 2 2006.161.08:23:40.95#ibcon#flushed, iclass 3, count 2 2006.161.08:23:40.95#ibcon#about to write, iclass 3, count 2 2006.161.08:23:40.95#ibcon#wrote, iclass 3, count 2 2006.161.08:23:40.95#ibcon#about to read 3, iclass 3, count 2 2006.161.08:23:40.98#ibcon#read 3, iclass 3, count 2 2006.161.08:23:40.98#ibcon#about to read 4, iclass 3, count 2 2006.161.08:23:40.98#ibcon#read 4, iclass 3, count 2 2006.161.08:23:40.98#ibcon#about to read 5, iclass 3, count 2 2006.161.08:23:40.98#ibcon#read 5, iclass 3, count 2 2006.161.08:23:40.98#ibcon#about to read 6, iclass 3, count 2 2006.161.08:23:40.98#ibcon#read 6, iclass 3, count 2 2006.161.08:23:40.98#ibcon#end of sib2, iclass 3, count 2 2006.161.08:23:40.98#ibcon#*after write, iclass 3, count 2 2006.161.08:23:40.98#ibcon#*before return 0, iclass 3, count 2 2006.161.08:23:40.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:40.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:40.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.08:23:40.98#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:40.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:41.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:41.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:41.10#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:23:41.10#ibcon#first serial, iclass 3, count 0 2006.161.08:23:41.10#ibcon#enter sib2, iclass 3, count 0 2006.161.08:23:41.10#ibcon#flushed, iclass 3, count 0 2006.161.08:23:41.10#ibcon#about to write, iclass 3, count 0 2006.161.08:23:41.10#ibcon#wrote, iclass 3, count 0 2006.161.08:23:41.10#ibcon#about to read 3, iclass 3, count 0 2006.161.08:23:41.12#ibcon#read 3, iclass 3, count 0 2006.161.08:23:41.12#ibcon#about to read 4, iclass 3, count 0 2006.161.08:23:41.12#ibcon#read 4, iclass 3, count 0 2006.161.08:23:41.12#ibcon#about to read 5, iclass 3, count 0 2006.161.08:23:41.12#ibcon#read 5, iclass 3, count 0 2006.161.08:23:41.12#ibcon#about to read 6, iclass 3, count 0 2006.161.08:23:41.12#ibcon#read 6, iclass 3, count 0 2006.161.08:23:41.12#ibcon#end of sib2, iclass 3, count 0 2006.161.08:23:41.12#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:23:41.12#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:23:41.12#ibcon#[25=USB\r\n] 2006.161.08:23:41.12#ibcon#*before write, iclass 3, count 0 2006.161.08:23:41.12#ibcon#enter sib2, iclass 3, count 0 2006.161.08:23:41.12#ibcon#flushed, iclass 3, count 0 2006.161.08:23:41.12#ibcon#about to write, iclass 3, count 0 2006.161.08:23:41.12#ibcon#wrote, iclass 3, count 0 2006.161.08:23:41.12#ibcon#about to read 3, iclass 3, count 0 2006.161.08:23:41.15#ibcon#read 3, iclass 3, count 0 2006.161.08:23:41.15#ibcon#about to read 4, iclass 3, count 0 2006.161.08:23:41.15#ibcon#read 4, iclass 3, count 0 2006.161.08:23:41.15#ibcon#about to read 5, iclass 3, count 0 2006.161.08:23:41.15#ibcon#read 5, iclass 3, count 0 2006.161.08:23:41.15#ibcon#about to read 6, iclass 3, count 0 2006.161.08:23:41.15#ibcon#read 6, iclass 3, count 0 2006.161.08:23:41.15#ibcon#end of sib2, iclass 3, count 0 2006.161.08:23:41.15#ibcon#*after write, iclass 3, count 0 2006.161.08:23:41.15#ibcon#*before return 0, iclass 3, count 0 2006.161.08:23:41.15#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:41.15#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:41.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:23:41.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:23:41.15$vc4f8/valo=7,832.99 2006.161.08:23:41.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.08:23:41.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.08:23:41.15#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:41.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:41.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:41.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:41.15#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:23:41.15#ibcon#first serial, iclass 5, count 0 2006.161.08:23:41.15#ibcon#enter sib2, iclass 5, count 0 2006.161.08:23:41.15#ibcon#flushed, iclass 5, count 0 2006.161.08:23:41.15#ibcon#about to write, iclass 5, count 0 2006.161.08:23:41.15#ibcon#wrote, iclass 5, count 0 2006.161.08:23:41.15#ibcon#about to read 3, iclass 5, count 0 2006.161.08:23:41.17#ibcon#read 3, iclass 5, count 0 2006.161.08:23:41.17#ibcon#about to read 4, iclass 5, count 0 2006.161.08:23:41.17#ibcon#read 4, iclass 5, count 0 2006.161.08:23:41.17#ibcon#about to read 5, iclass 5, count 0 2006.161.08:23:41.17#ibcon#read 5, iclass 5, count 0 2006.161.08:23:41.17#ibcon#about to read 6, iclass 5, count 0 2006.161.08:23:41.17#ibcon#read 6, iclass 5, count 0 2006.161.08:23:41.17#ibcon#end of sib2, iclass 5, count 0 2006.161.08:23:41.17#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:23:41.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:23:41.17#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:23:41.17#ibcon#*before write, iclass 5, count 0 2006.161.08:23:41.17#ibcon#enter sib2, iclass 5, count 0 2006.161.08:23:41.17#ibcon#flushed, iclass 5, count 0 2006.161.08:23:41.17#ibcon#about to write, iclass 5, count 0 2006.161.08:23:41.17#ibcon#wrote, iclass 5, count 0 2006.161.08:23:41.17#ibcon#about to read 3, iclass 5, count 0 2006.161.08:23:41.21#ibcon#read 3, iclass 5, count 0 2006.161.08:23:41.21#ibcon#about to read 4, iclass 5, count 0 2006.161.08:23:41.21#ibcon#read 4, iclass 5, count 0 2006.161.08:23:41.21#ibcon#about to read 5, iclass 5, count 0 2006.161.08:23:41.21#ibcon#read 5, iclass 5, count 0 2006.161.08:23:41.21#ibcon#about to read 6, iclass 5, count 0 2006.161.08:23:41.21#ibcon#read 6, iclass 5, count 0 2006.161.08:23:41.21#ibcon#end of sib2, iclass 5, count 0 2006.161.08:23:41.21#ibcon#*after write, iclass 5, count 0 2006.161.08:23:41.21#ibcon#*before return 0, iclass 5, count 0 2006.161.08:23:41.21#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:41.21#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:41.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:23:41.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:23:41.21$vc4f8/va=7,6 2006.161.08:23:41.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.161.08:23:41.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.161.08:23:41.21#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:41.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:41.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:41.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:41.27#ibcon#enter wrdev, iclass 7, count 2 2006.161.08:23:41.27#ibcon#first serial, iclass 7, count 2 2006.161.08:23:41.27#ibcon#enter sib2, iclass 7, count 2 2006.161.08:23:41.27#ibcon#flushed, iclass 7, count 2 2006.161.08:23:41.27#ibcon#about to write, iclass 7, count 2 2006.161.08:23:41.27#ibcon#wrote, iclass 7, count 2 2006.161.08:23:41.27#ibcon#about to read 3, iclass 7, count 2 2006.161.08:23:41.29#ibcon#read 3, iclass 7, count 2 2006.161.08:23:41.29#ibcon#about to read 4, iclass 7, count 2 2006.161.08:23:41.29#ibcon#read 4, iclass 7, count 2 2006.161.08:23:41.29#ibcon#about to read 5, iclass 7, count 2 2006.161.08:23:41.29#ibcon#read 5, iclass 7, count 2 2006.161.08:23:41.29#ibcon#about to read 6, iclass 7, count 2 2006.161.08:23:41.29#ibcon#read 6, iclass 7, count 2 2006.161.08:23:41.29#ibcon#end of sib2, iclass 7, count 2 2006.161.08:23:41.29#ibcon#*mode == 0, iclass 7, count 2 2006.161.08:23:41.29#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.161.08:23:41.29#ibcon#[25=AT07-06\r\n] 2006.161.08:23:41.29#ibcon#*before write, iclass 7, count 2 2006.161.08:23:41.29#ibcon#enter sib2, iclass 7, count 2 2006.161.08:23:41.29#ibcon#flushed, iclass 7, count 2 2006.161.08:23:41.29#ibcon#about to write, iclass 7, count 2 2006.161.08:23:41.29#ibcon#wrote, iclass 7, count 2 2006.161.08:23:41.29#ibcon#about to read 3, iclass 7, count 2 2006.161.08:23:41.31#abcon#<5=/05 3.3 5.6 23.99 871002.5\r\n> 2006.161.08:23:41.32#ibcon#read 3, iclass 7, count 2 2006.161.08:23:41.32#ibcon#about to read 4, iclass 7, count 2 2006.161.08:23:41.32#ibcon#read 4, iclass 7, count 2 2006.161.08:23:41.32#ibcon#about to read 5, iclass 7, count 2 2006.161.08:23:41.32#ibcon#read 5, iclass 7, count 2 2006.161.08:23:41.32#ibcon#about to read 6, iclass 7, count 2 2006.161.08:23:41.32#ibcon#read 6, iclass 7, count 2 2006.161.08:23:41.32#ibcon#end of sib2, iclass 7, count 2 2006.161.08:23:41.32#ibcon#*after write, iclass 7, count 2 2006.161.08:23:41.32#ibcon#*before return 0, iclass 7, count 2 2006.161.08:23:41.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:41.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:41.32#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.161.08:23:41.32#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:41.32#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:23:41.33#abcon#{5=INTERFACE CLEAR} 2006.161.08:23:41.39#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:23:41.44#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:23:41.44#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:23:41.44#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:23:41.44#ibcon#first serial, iclass 7, count 0 2006.161.08:23:41.44#ibcon#enter sib2, iclass 7, count 0 2006.161.08:23:41.44#ibcon#flushed, iclass 7, count 0 2006.161.08:23:41.44#ibcon#about to write, iclass 7, count 0 2006.161.08:23:41.44#ibcon#wrote, iclass 7, count 0 2006.161.08:23:41.44#ibcon#about to read 3, iclass 7, count 0 2006.161.08:23:41.46#ibcon#read 3, iclass 7, count 0 2006.161.08:23:41.46#ibcon#about to read 4, iclass 7, count 0 2006.161.08:23:41.46#ibcon#read 4, iclass 7, count 0 2006.161.08:23:41.46#ibcon#about to read 5, iclass 7, count 0 2006.161.08:23:41.46#ibcon#read 5, iclass 7, count 0 2006.161.08:23:41.46#ibcon#about to read 6, iclass 7, count 0 2006.161.08:23:41.46#ibcon#read 6, iclass 7, count 0 2006.161.08:23:41.46#ibcon#end of sib2, iclass 7, count 0 2006.161.08:23:41.46#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:23:41.46#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:23:41.46#ibcon#[25=USB\r\n] 2006.161.08:23:41.46#ibcon#*before write, iclass 7, count 0 2006.161.08:23:41.46#ibcon#enter sib2, iclass 7, count 0 2006.161.08:23:41.46#ibcon#flushed, iclass 7, count 0 2006.161.08:23:41.46#ibcon#about to write, iclass 7, count 0 2006.161.08:23:41.46#ibcon#wrote, iclass 7, count 0 2006.161.08:23:41.46#ibcon#about to read 3, iclass 7, count 0 2006.161.08:23:41.49#ibcon#read 3, iclass 7, count 0 2006.161.08:23:41.49#ibcon#about to read 4, iclass 7, count 0 2006.161.08:23:41.49#ibcon#read 4, iclass 7, count 0 2006.161.08:23:41.49#ibcon#about to read 5, iclass 7, count 0 2006.161.08:23:41.49#ibcon#read 5, iclass 7, count 0 2006.161.08:23:41.49#ibcon#about to read 6, iclass 7, count 0 2006.161.08:23:41.49#ibcon#read 6, iclass 7, count 0 2006.161.08:23:41.49#ibcon#end of sib2, iclass 7, count 0 2006.161.08:23:41.49#ibcon#*after write, iclass 7, count 0 2006.161.08:23:41.49#ibcon#*before return 0, iclass 7, count 0 2006.161.08:23:41.49#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:23:41.49#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.161.08:23:41.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:23:41.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:23:41.49$vc4f8/valo=8,852.99 2006.161.08:23:41.49#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.08:23:41.49#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.08:23:41.49#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:41.49#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:23:41.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:23:41.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:23:41.49#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:23:41.49#ibcon#first serial, iclass 15, count 0 2006.161.08:23:41.49#ibcon#enter sib2, iclass 15, count 0 2006.161.08:23:41.49#ibcon#flushed, iclass 15, count 0 2006.161.08:23:41.49#ibcon#about to write, iclass 15, count 0 2006.161.08:23:41.49#ibcon#wrote, iclass 15, count 0 2006.161.08:23:41.49#ibcon#about to read 3, iclass 15, count 0 2006.161.08:23:41.51#ibcon#read 3, iclass 15, count 0 2006.161.08:23:41.51#ibcon#about to read 4, iclass 15, count 0 2006.161.08:23:41.51#ibcon#read 4, iclass 15, count 0 2006.161.08:23:41.51#ibcon#about to read 5, iclass 15, count 0 2006.161.08:23:41.51#ibcon#read 5, iclass 15, count 0 2006.161.08:23:41.51#ibcon#about to read 6, iclass 15, count 0 2006.161.08:23:41.51#ibcon#read 6, iclass 15, count 0 2006.161.08:23:41.51#ibcon#end of sib2, iclass 15, count 0 2006.161.08:23:41.51#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:23:41.51#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:23:41.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:23:41.51#ibcon#*before write, iclass 15, count 0 2006.161.08:23:41.51#ibcon#enter sib2, iclass 15, count 0 2006.161.08:23:41.51#ibcon#flushed, iclass 15, count 0 2006.161.08:23:41.51#ibcon#about to write, iclass 15, count 0 2006.161.08:23:41.51#ibcon#wrote, iclass 15, count 0 2006.161.08:23:41.51#ibcon#about to read 3, iclass 15, count 0 2006.161.08:23:41.55#ibcon#read 3, iclass 15, count 0 2006.161.08:23:41.55#ibcon#about to read 4, iclass 15, count 0 2006.161.08:23:41.55#ibcon#read 4, iclass 15, count 0 2006.161.08:23:41.55#ibcon#about to read 5, iclass 15, count 0 2006.161.08:23:41.55#ibcon#read 5, iclass 15, count 0 2006.161.08:23:41.55#ibcon#about to read 6, iclass 15, count 0 2006.161.08:23:41.55#ibcon#read 6, iclass 15, count 0 2006.161.08:23:41.55#ibcon#end of sib2, iclass 15, count 0 2006.161.08:23:41.55#ibcon#*after write, iclass 15, count 0 2006.161.08:23:41.55#ibcon#*before return 0, iclass 15, count 0 2006.161.08:23:41.55#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:23:41.55#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:23:41.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:23:41.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:23:41.55$vc4f8/va=8,7 2006.161.08:23:41.55#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.161.08:23:41.55#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.161.08:23:41.55#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:41.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:23:41.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:23:41.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:23:41.61#ibcon#enter wrdev, iclass 17, count 2 2006.161.08:23:41.61#ibcon#first serial, iclass 17, count 2 2006.161.08:23:41.61#ibcon#enter sib2, iclass 17, count 2 2006.161.08:23:41.61#ibcon#flushed, iclass 17, count 2 2006.161.08:23:41.61#ibcon#about to write, iclass 17, count 2 2006.161.08:23:41.61#ibcon#wrote, iclass 17, count 2 2006.161.08:23:41.61#ibcon#about to read 3, iclass 17, count 2 2006.161.08:23:41.63#ibcon#read 3, iclass 17, count 2 2006.161.08:23:41.63#ibcon#about to read 4, iclass 17, count 2 2006.161.08:23:41.63#ibcon#read 4, iclass 17, count 2 2006.161.08:23:41.63#ibcon#about to read 5, iclass 17, count 2 2006.161.08:23:41.63#ibcon#read 5, iclass 17, count 2 2006.161.08:23:41.63#ibcon#about to read 6, iclass 17, count 2 2006.161.08:23:41.63#ibcon#read 6, iclass 17, count 2 2006.161.08:23:41.63#ibcon#end of sib2, iclass 17, count 2 2006.161.08:23:41.63#ibcon#*mode == 0, iclass 17, count 2 2006.161.08:23:41.63#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.161.08:23:41.63#ibcon#[25=AT08-07\r\n] 2006.161.08:23:41.63#ibcon#*before write, iclass 17, count 2 2006.161.08:23:41.63#ibcon#enter sib2, iclass 17, count 2 2006.161.08:23:41.63#ibcon#flushed, iclass 17, count 2 2006.161.08:23:41.63#ibcon#about to write, iclass 17, count 2 2006.161.08:23:41.63#ibcon#wrote, iclass 17, count 2 2006.161.08:23:41.63#ibcon#about to read 3, iclass 17, count 2 2006.161.08:23:41.66#ibcon#read 3, iclass 17, count 2 2006.161.08:23:41.66#ibcon#about to read 4, iclass 17, count 2 2006.161.08:23:41.66#ibcon#read 4, iclass 17, count 2 2006.161.08:23:41.66#ibcon#about to read 5, iclass 17, count 2 2006.161.08:23:41.66#ibcon#read 5, iclass 17, count 2 2006.161.08:23:41.66#ibcon#about to read 6, iclass 17, count 2 2006.161.08:23:41.66#ibcon#read 6, iclass 17, count 2 2006.161.08:23:41.66#ibcon#end of sib2, iclass 17, count 2 2006.161.08:23:41.66#ibcon#*after write, iclass 17, count 2 2006.161.08:23:41.66#ibcon#*before return 0, iclass 17, count 2 2006.161.08:23:41.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:23:41.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.161.08:23:41.66#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.161.08:23:41.66#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:41.66#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:23:41.78#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:23:41.78#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:23:41.78#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:23:41.78#ibcon#first serial, iclass 17, count 0 2006.161.08:23:41.78#ibcon#enter sib2, iclass 17, count 0 2006.161.08:23:41.78#ibcon#flushed, iclass 17, count 0 2006.161.08:23:41.78#ibcon#about to write, iclass 17, count 0 2006.161.08:23:41.78#ibcon#wrote, iclass 17, count 0 2006.161.08:23:41.78#ibcon#about to read 3, iclass 17, count 0 2006.161.08:23:41.80#ibcon#read 3, iclass 17, count 0 2006.161.08:23:41.80#ibcon#about to read 4, iclass 17, count 0 2006.161.08:23:41.80#ibcon#read 4, iclass 17, count 0 2006.161.08:23:41.80#ibcon#about to read 5, iclass 17, count 0 2006.161.08:23:41.80#ibcon#read 5, iclass 17, count 0 2006.161.08:23:41.80#ibcon#about to read 6, iclass 17, count 0 2006.161.08:23:41.80#ibcon#read 6, iclass 17, count 0 2006.161.08:23:41.80#ibcon#end of sib2, iclass 17, count 0 2006.161.08:23:41.80#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:23:41.80#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:23:41.80#ibcon#[25=USB\r\n] 2006.161.08:23:41.80#ibcon#*before write, iclass 17, count 0 2006.161.08:23:41.80#ibcon#enter sib2, iclass 17, count 0 2006.161.08:23:41.80#ibcon#flushed, iclass 17, count 0 2006.161.08:23:41.80#ibcon#about to write, iclass 17, count 0 2006.161.08:23:41.80#ibcon#wrote, iclass 17, count 0 2006.161.08:23:41.80#ibcon#about to read 3, iclass 17, count 0 2006.161.08:23:41.83#ibcon#read 3, iclass 17, count 0 2006.161.08:23:41.83#ibcon#about to read 4, iclass 17, count 0 2006.161.08:23:41.83#ibcon#read 4, iclass 17, count 0 2006.161.08:23:41.83#ibcon#about to read 5, iclass 17, count 0 2006.161.08:23:41.83#ibcon#read 5, iclass 17, count 0 2006.161.08:23:41.83#ibcon#about to read 6, iclass 17, count 0 2006.161.08:23:41.83#ibcon#read 6, iclass 17, count 0 2006.161.08:23:41.83#ibcon#end of sib2, iclass 17, count 0 2006.161.08:23:41.83#ibcon#*after write, iclass 17, count 0 2006.161.08:23:41.83#ibcon#*before return 0, iclass 17, count 0 2006.161.08:23:41.83#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:23:41.83#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.161.08:23:41.83#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:23:41.83#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:23:41.83$vc4f8/vblo=1,632.99 2006.161.08:23:41.83#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.161.08:23:41.83#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.161.08:23:41.83#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:41.83#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:41.83#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:41.83#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:41.83#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:23:41.83#ibcon#first serial, iclass 19, count 0 2006.161.08:23:41.83#ibcon#enter sib2, iclass 19, count 0 2006.161.08:23:41.83#ibcon#flushed, iclass 19, count 0 2006.161.08:23:41.83#ibcon#about to write, iclass 19, count 0 2006.161.08:23:41.83#ibcon#wrote, iclass 19, count 0 2006.161.08:23:41.83#ibcon#about to read 3, iclass 19, count 0 2006.161.08:23:41.85#ibcon#read 3, iclass 19, count 0 2006.161.08:23:41.85#ibcon#about to read 4, iclass 19, count 0 2006.161.08:23:41.85#ibcon#read 4, iclass 19, count 0 2006.161.08:23:41.85#ibcon#about to read 5, iclass 19, count 0 2006.161.08:23:41.85#ibcon#read 5, iclass 19, count 0 2006.161.08:23:41.85#ibcon#about to read 6, iclass 19, count 0 2006.161.08:23:41.85#ibcon#read 6, iclass 19, count 0 2006.161.08:23:41.85#ibcon#end of sib2, iclass 19, count 0 2006.161.08:23:41.85#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:23:41.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:23:41.85#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:23:41.85#ibcon#*before write, iclass 19, count 0 2006.161.08:23:41.85#ibcon#enter sib2, iclass 19, count 0 2006.161.08:23:41.85#ibcon#flushed, iclass 19, count 0 2006.161.08:23:41.85#ibcon#about to write, iclass 19, count 0 2006.161.08:23:41.85#ibcon#wrote, iclass 19, count 0 2006.161.08:23:41.85#ibcon#about to read 3, iclass 19, count 0 2006.161.08:23:41.89#ibcon#read 3, iclass 19, count 0 2006.161.08:23:41.89#ibcon#about to read 4, iclass 19, count 0 2006.161.08:23:41.89#ibcon#read 4, iclass 19, count 0 2006.161.08:23:41.89#ibcon#about to read 5, iclass 19, count 0 2006.161.08:23:41.89#ibcon#read 5, iclass 19, count 0 2006.161.08:23:41.89#ibcon#about to read 6, iclass 19, count 0 2006.161.08:23:41.89#ibcon#read 6, iclass 19, count 0 2006.161.08:23:41.89#ibcon#end of sib2, iclass 19, count 0 2006.161.08:23:41.89#ibcon#*after write, iclass 19, count 0 2006.161.08:23:41.89#ibcon#*before return 0, iclass 19, count 0 2006.161.08:23:41.89#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:41.89#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.161.08:23:41.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:23:41.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:23:41.89$vc4f8/vb=1,4 2006.161.08:23:41.89#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.161.08:23:41.89#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.161.08:23:41.89#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:41.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:41.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:41.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:41.89#ibcon#enter wrdev, iclass 21, count 2 2006.161.08:23:41.89#ibcon#first serial, iclass 21, count 2 2006.161.08:23:41.89#ibcon#enter sib2, iclass 21, count 2 2006.161.08:23:41.89#ibcon#flushed, iclass 21, count 2 2006.161.08:23:41.89#ibcon#about to write, iclass 21, count 2 2006.161.08:23:41.89#ibcon#wrote, iclass 21, count 2 2006.161.08:23:41.89#ibcon#about to read 3, iclass 21, count 2 2006.161.08:23:41.91#ibcon#read 3, iclass 21, count 2 2006.161.08:23:41.91#ibcon#about to read 4, iclass 21, count 2 2006.161.08:23:41.91#ibcon#read 4, iclass 21, count 2 2006.161.08:23:41.91#ibcon#about to read 5, iclass 21, count 2 2006.161.08:23:41.91#ibcon#read 5, iclass 21, count 2 2006.161.08:23:41.91#ibcon#about to read 6, iclass 21, count 2 2006.161.08:23:41.91#ibcon#read 6, iclass 21, count 2 2006.161.08:23:41.91#ibcon#end of sib2, iclass 21, count 2 2006.161.08:23:41.91#ibcon#*mode == 0, iclass 21, count 2 2006.161.08:23:41.91#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.161.08:23:41.91#ibcon#[27=AT01-04\r\n] 2006.161.08:23:41.91#ibcon#*before write, iclass 21, count 2 2006.161.08:23:41.91#ibcon#enter sib2, iclass 21, count 2 2006.161.08:23:41.91#ibcon#flushed, iclass 21, count 2 2006.161.08:23:41.91#ibcon#about to write, iclass 21, count 2 2006.161.08:23:41.91#ibcon#wrote, iclass 21, count 2 2006.161.08:23:41.91#ibcon#about to read 3, iclass 21, count 2 2006.161.08:23:41.94#ibcon#read 3, iclass 21, count 2 2006.161.08:23:41.94#ibcon#about to read 4, iclass 21, count 2 2006.161.08:23:41.94#ibcon#read 4, iclass 21, count 2 2006.161.08:23:41.94#ibcon#about to read 5, iclass 21, count 2 2006.161.08:23:41.94#ibcon#read 5, iclass 21, count 2 2006.161.08:23:41.94#ibcon#about to read 6, iclass 21, count 2 2006.161.08:23:41.94#ibcon#read 6, iclass 21, count 2 2006.161.08:23:41.94#ibcon#end of sib2, iclass 21, count 2 2006.161.08:23:41.94#ibcon#*after write, iclass 21, count 2 2006.161.08:23:41.94#ibcon#*before return 0, iclass 21, count 2 2006.161.08:23:41.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:41.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.161.08:23:41.94#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.161.08:23:41.94#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:41.94#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:42.06#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:42.06#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:42.06#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:23:42.06#ibcon#first serial, iclass 21, count 0 2006.161.08:23:42.06#ibcon#enter sib2, iclass 21, count 0 2006.161.08:23:42.06#ibcon#flushed, iclass 21, count 0 2006.161.08:23:42.06#ibcon#about to write, iclass 21, count 0 2006.161.08:23:42.06#ibcon#wrote, iclass 21, count 0 2006.161.08:23:42.06#ibcon#about to read 3, iclass 21, count 0 2006.161.08:23:42.08#ibcon#read 3, iclass 21, count 0 2006.161.08:23:42.08#ibcon#about to read 4, iclass 21, count 0 2006.161.08:23:42.08#ibcon#read 4, iclass 21, count 0 2006.161.08:23:42.08#ibcon#about to read 5, iclass 21, count 0 2006.161.08:23:42.08#ibcon#read 5, iclass 21, count 0 2006.161.08:23:42.08#ibcon#about to read 6, iclass 21, count 0 2006.161.08:23:42.08#ibcon#read 6, iclass 21, count 0 2006.161.08:23:42.08#ibcon#end of sib2, iclass 21, count 0 2006.161.08:23:42.08#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:23:42.08#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:23:42.08#ibcon#[27=USB\r\n] 2006.161.08:23:42.08#ibcon#*before write, iclass 21, count 0 2006.161.08:23:42.08#ibcon#enter sib2, iclass 21, count 0 2006.161.08:23:42.08#ibcon#flushed, iclass 21, count 0 2006.161.08:23:42.08#ibcon#about to write, iclass 21, count 0 2006.161.08:23:42.08#ibcon#wrote, iclass 21, count 0 2006.161.08:23:42.08#ibcon#about to read 3, iclass 21, count 0 2006.161.08:23:42.11#ibcon#read 3, iclass 21, count 0 2006.161.08:23:42.11#ibcon#about to read 4, iclass 21, count 0 2006.161.08:23:42.11#ibcon#read 4, iclass 21, count 0 2006.161.08:23:42.11#ibcon#about to read 5, iclass 21, count 0 2006.161.08:23:42.11#ibcon#read 5, iclass 21, count 0 2006.161.08:23:42.11#ibcon#about to read 6, iclass 21, count 0 2006.161.08:23:42.11#ibcon#read 6, iclass 21, count 0 2006.161.08:23:42.11#ibcon#end of sib2, iclass 21, count 0 2006.161.08:23:42.11#ibcon#*after write, iclass 21, count 0 2006.161.08:23:42.11#ibcon#*before return 0, iclass 21, count 0 2006.161.08:23:42.11#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:42.11#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.161.08:23:42.11#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:23:42.11#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:23:42.11$vc4f8/vblo=2,640.99 2006.161.08:23:42.11#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.161.08:23:42.11#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.161.08:23:42.11#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:42.11#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:42.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:42.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:42.11#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:23:42.11#ibcon#first serial, iclass 23, count 0 2006.161.08:23:42.11#ibcon#enter sib2, iclass 23, count 0 2006.161.08:23:42.11#ibcon#flushed, iclass 23, count 0 2006.161.08:23:42.11#ibcon#about to write, iclass 23, count 0 2006.161.08:23:42.11#ibcon#wrote, iclass 23, count 0 2006.161.08:23:42.11#ibcon#about to read 3, iclass 23, count 0 2006.161.08:23:42.13#ibcon#read 3, iclass 23, count 0 2006.161.08:23:42.13#ibcon#about to read 4, iclass 23, count 0 2006.161.08:23:42.13#ibcon#read 4, iclass 23, count 0 2006.161.08:23:42.13#ibcon#about to read 5, iclass 23, count 0 2006.161.08:23:42.13#ibcon#read 5, iclass 23, count 0 2006.161.08:23:42.13#ibcon#about to read 6, iclass 23, count 0 2006.161.08:23:42.13#ibcon#read 6, iclass 23, count 0 2006.161.08:23:42.13#ibcon#end of sib2, iclass 23, count 0 2006.161.08:23:42.13#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:23:42.13#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:23:42.13#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:23:42.13#ibcon#*before write, iclass 23, count 0 2006.161.08:23:42.13#ibcon#enter sib2, iclass 23, count 0 2006.161.08:23:42.13#ibcon#flushed, iclass 23, count 0 2006.161.08:23:42.13#ibcon#about to write, iclass 23, count 0 2006.161.08:23:42.13#ibcon#wrote, iclass 23, count 0 2006.161.08:23:42.13#ibcon#about to read 3, iclass 23, count 0 2006.161.08:23:42.17#ibcon#read 3, iclass 23, count 0 2006.161.08:23:42.17#ibcon#about to read 4, iclass 23, count 0 2006.161.08:23:42.17#ibcon#read 4, iclass 23, count 0 2006.161.08:23:42.17#ibcon#about to read 5, iclass 23, count 0 2006.161.08:23:42.17#ibcon#read 5, iclass 23, count 0 2006.161.08:23:42.17#ibcon#about to read 6, iclass 23, count 0 2006.161.08:23:42.17#ibcon#read 6, iclass 23, count 0 2006.161.08:23:42.17#ibcon#end of sib2, iclass 23, count 0 2006.161.08:23:42.17#ibcon#*after write, iclass 23, count 0 2006.161.08:23:42.17#ibcon#*before return 0, iclass 23, count 0 2006.161.08:23:42.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:42.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.161.08:23:42.17#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:23:42.17#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:23:42.17$vc4f8/vb=2,4 2006.161.08:23:42.17#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.161.08:23:42.17#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.161.08:23:42.17#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:42.17#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:42.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:42.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:42.23#ibcon#enter wrdev, iclass 25, count 2 2006.161.08:23:42.23#ibcon#first serial, iclass 25, count 2 2006.161.08:23:42.23#ibcon#enter sib2, iclass 25, count 2 2006.161.08:23:42.23#ibcon#flushed, iclass 25, count 2 2006.161.08:23:42.23#ibcon#about to write, iclass 25, count 2 2006.161.08:23:42.23#ibcon#wrote, iclass 25, count 2 2006.161.08:23:42.23#ibcon#about to read 3, iclass 25, count 2 2006.161.08:23:42.25#ibcon#read 3, iclass 25, count 2 2006.161.08:23:42.25#ibcon#about to read 4, iclass 25, count 2 2006.161.08:23:42.25#ibcon#read 4, iclass 25, count 2 2006.161.08:23:42.25#ibcon#about to read 5, iclass 25, count 2 2006.161.08:23:42.25#ibcon#read 5, iclass 25, count 2 2006.161.08:23:42.25#ibcon#about to read 6, iclass 25, count 2 2006.161.08:23:42.25#ibcon#read 6, iclass 25, count 2 2006.161.08:23:42.25#ibcon#end of sib2, iclass 25, count 2 2006.161.08:23:42.25#ibcon#*mode == 0, iclass 25, count 2 2006.161.08:23:42.25#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.161.08:23:42.25#ibcon#[27=AT02-04\r\n] 2006.161.08:23:42.25#ibcon#*before write, iclass 25, count 2 2006.161.08:23:42.25#ibcon#enter sib2, iclass 25, count 2 2006.161.08:23:42.25#ibcon#flushed, iclass 25, count 2 2006.161.08:23:42.25#ibcon#about to write, iclass 25, count 2 2006.161.08:23:42.25#ibcon#wrote, iclass 25, count 2 2006.161.08:23:42.25#ibcon#about to read 3, iclass 25, count 2 2006.161.08:23:42.28#ibcon#read 3, iclass 25, count 2 2006.161.08:23:42.28#ibcon#about to read 4, iclass 25, count 2 2006.161.08:23:42.28#ibcon#read 4, iclass 25, count 2 2006.161.08:23:42.28#ibcon#about to read 5, iclass 25, count 2 2006.161.08:23:42.28#ibcon#read 5, iclass 25, count 2 2006.161.08:23:42.28#ibcon#about to read 6, iclass 25, count 2 2006.161.08:23:42.28#ibcon#read 6, iclass 25, count 2 2006.161.08:23:42.28#ibcon#end of sib2, iclass 25, count 2 2006.161.08:23:42.28#ibcon#*after write, iclass 25, count 2 2006.161.08:23:42.28#ibcon#*before return 0, iclass 25, count 2 2006.161.08:23:42.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:42.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.161.08:23:42.28#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.161.08:23:42.28#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:42.28#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:42.40#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:42.40#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:42.40#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:23:42.40#ibcon#first serial, iclass 25, count 0 2006.161.08:23:42.40#ibcon#enter sib2, iclass 25, count 0 2006.161.08:23:42.40#ibcon#flushed, iclass 25, count 0 2006.161.08:23:42.40#ibcon#about to write, iclass 25, count 0 2006.161.08:23:42.40#ibcon#wrote, iclass 25, count 0 2006.161.08:23:42.40#ibcon#about to read 3, iclass 25, count 0 2006.161.08:23:42.42#ibcon#read 3, iclass 25, count 0 2006.161.08:23:42.42#ibcon#about to read 4, iclass 25, count 0 2006.161.08:23:42.42#ibcon#read 4, iclass 25, count 0 2006.161.08:23:42.42#ibcon#about to read 5, iclass 25, count 0 2006.161.08:23:42.42#ibcon#read 5, iclass 25, count 0 2006.161.08:23:42.42#ibcon#about to read 6, iclass 25, count 0 2006.161.08:23:42.42#ibcon#read 6, iclass 25, count 0 2006.161.08:23:42.42#ibcon#end of sib2, iclass 25, count 0 2006.161.08:23:42.42#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:23:42.42#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:23:42.42#ibcon#[27=USB\r\n] 2006.161.08:23:42.42#ibcon#*before write, iclass 25, count 0 2006.161.08:23:42.42#ibcon#enter sib2, iclass 25, count 0 2006.161.08:23:42.42#ibcon#flushed, iclass 25, count 0 2006.161.08:23:42.42#ibcon#about to write, iclass 25, count 0 2006.161.08:23:42.42#ibcon#wrote, iclass 25, count 0 2006.161.08:23:42.42#ibcon#about to read 3, iclass 25, count 0 2006.161.08:23:42.45#ibcon#read 3, iclass 25, count 0 2006.161.08:23:42.45#ibcon#about to read 4, iclass 25, count 0 2006.161.08:23:42.45#ibcon#read 4, iclass 25, count 0 2006.161.08:23:42.45#ibcon#about to read 5, iclass 25, count 0 2006.161.08:23:42.45#ibcon#read 5, iclass 25, count 0 2006.161.08:23:42.45#ibcon#about to read 6, iclass 25, count 0 2006.161.08:23:42.45#ibcon#read 6, iclass 25, count 0 2006.161.08:23:42.45#ibcon#end of sib2, iclass 25, count 0 2006.161.08:23:42.45#ibcon#*after write, iclass 25, count 0 2006.161.08:23:42.45#ibcon#*before return 0, iclass 25, count 0 2006.161.08:23:42.45#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:42.45#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.161.08:23:42.45#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:23:42.45#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:23:42.45$vc4f8/vblo=3,656.99 2006.161.08:23:42.45#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.161.08:23:42.45#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.161.08:23:42.45#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:42.45#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:42.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:42.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:42.45#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:23:42.45#ibcon#first serial, iclass 27, count 0 2006.161.08:23:42.45#ibcon#enter sib2, iclass 27, count 0 2006.161.08:23:42.45#ibcon#flushed, iclass 27, count 0 2006.161.08:23:42.45#ibcon#about to write, iclass 27, count 0 2006.161.08:23:42.45#ibcon#wrote, iclass 27, count 0 2006.161.08:23:42.45#ibcon#about to read 3, iclass 27, count 0 2006.161.08:23:42.47#ibcon#read 3, iclass 27, count 0 2006.161.08:23:42.47#ibcon#about to read 4, iclass 27, count 0 2006.161.08:23:42.47#ibcon#read 4, iclass 27, count 0 2006.161.08:23:42.47#ibcon#about to read 5, iclass 27, count 0 2006.161.08:23:42.47#ibcon#read 5, iclass 27, count 0 2006.161.08:23:42.47#ibcon#about to read 6, iclass 27, count 0 2006.161.08:23:42.47#ibcon#read 6, iclass 27, count 0 2006.161.08:23:42.47#ibcon#end of sib2, iclass 27, count 0 2006.161.08:23:42.47#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:23:42.47#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:23:42.47#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:23:42.47#ibcon#*before write, iclass 27, count 0 2006.161.08:23:42.47#ibcon#enter sib2, iclass 27, count 0 2006.161.08:23:42.47#ibcon#flushed, iclass 27, count 0 2006.161.08:23:42.47#ibcon#about to write, iclass 27, count 0 2006.161.08:23:42.47#ibcon#wrote, iclass 27, count 0 2006.161.08:23:42.47#ibcon#about to read 3, iclass 27, count 0 2006.161.08:23:42.51#ibcon#read 3, iclass 27, count 0 2006.161.08:23:42.51#ibcon#about to read 4, iclass 27, count 0 2006.161.08:23:42.51#ibcon#read 4, iclass 27, count 0 2006.161.08:23:42.51#ibcon#about to read 5, iclass 27, count 0 2006.161.08:23:42.51#ibcon#read 5, iclass 27, count 0 2006.161.08:23:42.51#ibcon#about to read 6, iclass 27, count 0 2006.161.08:23:42.51#ibcon#read 6, iclass 27, count 0 2006.161.08:23:42.51#ibcon#end of sib2, iclass 27, count 0 2006.161.08:23:42.51#ibcon#*after write, iclass 27, count 0 2006.161.08:23:42.51#ibcon#*before return 0, iclass 27, count 0 2006.161.08:23:42.51#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:42.51#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.161.08:23:42.51#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:23:42.51#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:23:42.51$vc4f8/vb=3,4 2006.161.08:23:42.51#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.161.08:23:42.51#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.161.08:23:42.51#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:42.51#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:42.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:42.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:42.57#ibcon#enter wrdev, iclass 29, count 2 2006.161.08:23:42.57#ibcon#first serial, iclass 29, count 2 2006.161.08:23:42.57#ibcon#enter sib2, iclass 29, count 2 2006.161.08:23:42.57#ibcon#flushed, iclass 29, count 2 2006.161.08:23:42.57#ibcon#about to write, iclass 29, count 2 2006.161.08:23:42.57#ibcon#wrote, iclass 29, count 2 2006.161.08:23:42.57#ibcon#about to read 3, iclass 29, count 2 2006.161.08:23:42.59#ibcon#read 3, iclass 29, count 2 2006.161.08:23:42.59#ibcon#about to read 4, iclass 29, count 2 2006.161.08:23:42.59#ibcon#read 4, iclass 29, count 2 2006.161.08:23:42.59#ibcon#about to read 5, iclass 29, count 2 2006.161.08:23:42.59#ibcon#read 5, iclass 29, count 2 2006.161.08:23:42.59#ibcon#about to read 6, iclass 29, count 2 2006.161.08:23:42.59#ibcon#read 6, iclass 29, count 2 2006.161.08:23:42.59#ibcon#end of sib2, iclass 29, count 2 2006.161.08:23:42.59#ibcon#*mode == 0, iclass 29, count 2 2006.161.08:23:42.59#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.161.08:23:42.59#ibcon#[27=AT03-04\r\n] 2006.161.08:23:42.59#ibcon#*before write, iclass 29, count 2 2006.161.08:23:42.59#ibcon#enter sib2, iclass 29, count 2 2006.161.08:23:42.59#ibcon#flushed, iclass 29, count 2 2006.161.08:23:42.59#ibcon#about to write, iclass 29, count 2 2006.161.08:23:42.59#ibcon#wrote, iclass 29, count 2 2006.161.08:23:42.59#ibcon#about to read 3, iclass 29, count 2 2006.161.08:23:42.62#ibcon#read 3, iclass 29, count 2 2006.161.08:23:42.62#ibcon#about to read 4, iclass 29, count 2 2006.161.08:23:42.62#ibcon#read 4, iclass 29, count 2 2006.161.08:23:42.62#ibcon#about to read 5, iclass 29, count 2 2006.161.08:23:42.62#ibcon#read 5, iclass 29, count 2 2006.161.08:23:42.62#ibcon#about to read 6, iclass 29, count 2 2006.161.08:23:42.62#ibcon#read 6, iclass 29, count 2 2006.161.08:23:42.62#ibcon#end of sib2, iclass 29, count 2 2006.161.08:23:42.62#ibcon#*after write, iclass 29, count 2 2006.161.08:23:42.62#ibcon#*before return 0, iclass 29, count 2 2006.161.08:23:42.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:42.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.161.08:23:42.62#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.161.08:23:42.62#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:42.62#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:42.74#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:42.74#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:42.74#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:23:42.74#ibcon#first serial, iclass 29, count 0 2006.161.08:23:42.74#ibcon#enter sib2, iclass 29, count 0 2006.161.08:23:42.74#ibcon#flushed, iclass 29, count 0 2006.161.08:23:42.74#ibcon#about to write, iclass 29, count 0 2006.161.08:23:42.74#ibcon#wrote, iclass 29, count 0 2006.161.08:23:42.74#ibcon#about to read 3, iclass 29, count 0 2006.161.08:23:42.76#ibcon#read 3, iclass 29, count 0 2006.161.08:23:42.76#ibcon#about to read 4, iclass 29, count 0 2006.161.08:23:42.76#ibcon#read 4, iclass 29, count 0 2006.161.08:23:42.76#ibcon#about to read 5, iclass 29, count 0 2006.161.08:23:42.76#ibcon#read 5, iclass 29, count 0 2006.161.08:23:42.76#ibcon#about to read 6, iclass 29, count 0 2006.161.08:23:42.76#ibcon#read 6, iclass 29, count 0 2006.161.08:23:42.76#ibcon#end of sib2, iclass 29, count 0 2006.161.08:23:42.76#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:23:42.76#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:23:42.76#ibcon#[27=USB\r\n] 2006.161.08:23:42.76#ibcon#*before write, iclass 29, count 0 2006.161.08:23:42.76#ibcon#enter sib2, iclass 29, count 0 2006.161.08:23:42.76#ibcon#flushed, iclass 29, count 0 2006.161.08:23:42.76#ibcon#about to write, iclass 29, count 0 2006.161.08:23:42.76#ibcon#wrote, iclass 29, count 0 2006.161.08:23:42.76#ibcon#about to read 3, iclass 29, count 0 2006.161.08:23:42.79#ibcon#read 3, iclass 29, count 0 2006.161.08:23:42.79#ibcon#about to read 4, iclass 29, count 0 2006.161.08:23:42.79#ibcon#read 4, iclass 29, count 0 2006.161.08:23:42.79#ibcon#about to read 5, iclass 29, count 0 2006.161.08:23:42.79#ibcon#read 5, iclass 29, count 0 2006.161.08:23:42.79#ibcon#about to read 6, iclass 29, count 0 2006.161.08:23:42.79#ibcon#read 6, iclass 29, count 0 2006.161.08:23:42.79#ibcon#end of sib2, iclass 29, count 0 2006.161.08:23:42.79#ibcon#*after write, iclass 29, count 0 2006.161.08:23:42.79#ibcon#*before return 0, iclass 29, count 0 2006.161.08:23:42.79#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:42.79#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.161.08:23:42.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:23:42.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:23:42.79$vc4f8/vblo=4,712.99 2006.161.08:23:42.79#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.161.08:23:42.79#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.161.08:23:42.79#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:42.79#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:42.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:42.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:42.79#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:23:42.79#ibcon#first serial, iclass 31, count 0 2006.161.08:23:42.79#ibcon#enter sib2, iclass 31, count 0 2006.161.08:23:42.79#ibcon#flushed, iclass 31, count 0 2006.161.08:23:42.79#ibcon#about to write, iclass 31, count 0 2006.161.08:23:42.79#ibcon#wrote, iclass 31, count 0 2006.161.08:23:42.79#ibcon#about to read 3, iclass 31, count 0 2006.161.08:23:42.81#ibcon#read 3, iclass 31, count 0 2006.161.08:23:42.81#ibcon#about to read 4, iclass 31, count 0 2006.161.08:23:42.81#ibcon#read 4, iclass 31, count 0 2006.161.08:23:42.81#ibcon#about to read 5, iclass 31, count 0 2006.161.08:23:42.81#ibcon#read 5, iclass 31, count 0 2006.161.08:23:42.81#ibcon#about to read 6, iclass 31, count 0 2006.161.08:23:42.81#ibcon#read 6, iclass 31, count 0 2006.161.08:23:42.81#ibcon#end of sib2, iclass 31, count 0 2006.161.08:23:42.81#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:23:42.81#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:23:42.81#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:23:42.81#ibcon#*before write, iclass 31, count 0 2006.161.08:23:42.81#ibcon#enter sib2, iclass 31, count 0 2006.161.08:23:42.81#ibcon#flushed, iclass 31, count 0 2006.161.08:23:42.81#ibcon#about to write, iclass 31, count 0 2006.161.08:23:42.81#ibcon#wrote, iclass 31, count 0 2006.161.08:23:42.81#ibcon#about to read 3, iclass 31, count 0 2006.161.08:23:42.85#ibcon#read 3, iclass 31, count 0 2006.161.08:23:42.85#ibcon#about to read 4, iclass 31, count 0 2006.161.08:23:42.85#ibcon#read 4, iclass 31, count 0 2006.161.08:23:42.85#ibcon#about to read 5, iclass 31, count 0 2006.161.08:23:42.85#ibcon#read 5, iclass 31, count 0 2006.161.08:23:42.85#ibcon#about to read 6, iclass 31, count 0 2006.161.08:23:42.85#ibcon#read 6, iclass 31, count 0 2006.161.08:23:42.85#ibcon#end of sib2, iclass 31, count 0 2006.161.08:23:42.85#ibcon#*after write, iclass 31, count 0 2006.161.08:23:42.85#ibcon#*before return 0, iclass 31, count 0 2006.161.08:23:42.85#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:42.85#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.161.08:23:42.85#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:23:42.85#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:23:42.85$vc4f8/vb=4,4 2006.161.08:23:42.85#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.161.08:23:42.85#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.161.08:23:42.85#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:42.85#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:42.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:42.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:42.91#ibcon#enter wrdev, iclass 33, count 2 2006.161.08:23:42.91#ibcon#first serial, iclass 33, count 2 2006.161.08:23:42.91#ibcon#enter sib2, iclass 33, count 2 2006.161.08:23:42.91#ibcon#flushed, iclass 33, count 2 2006.161.08:23:42.91#ibcon#about to write, iclass 33, count 2 2006.161.08:23:42.91#ibcon#wrote, iclass 33, count 2 2006.161.08:23:42.91#ibcon#about to read 3, iclass 33, count 2 2006.161.08:23:42.93#ibcon#read 3, iclass 33, count 2 2006.161.08:23:42.93#ibcon#about to read 4, iclass 33, count 2 2006.161.08:23:42.93#ibcon#read 4, iclass 33, count 2 2006.161.08:23:42.93#ibcon#about to read 5, iclass 33, count 2 2006.161.08:23:42.93#ibcon#read 5, iclass 33, count 2 2006.161.08:23:42.93#ibcon#about to read 6, iclass 33, count 2 2006.161.08:23:42.93#ibcon#read 6, iclass 33, count 2 2006.161.08:23:42.93#ibcon#end of sib2, iclass 33, count 2 2006.161.08:23:42.93#ibcon#*mode == 0, iclass 33, count 2 2006.161.08:23:42.93#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.161.08:23:42.93#ibcon#[27=AT04-04\r\n] 2006.161.08:23:42.93#ibcon#*before write, iclass 33, count 2 2006.161.08:23:42.93#ibcon#enter sib2, iclass 33, count 2 2006.161.08:23:42.93#ibcon#flushed, iclass 33, count 2 2006.161.08:23:42.93#ibcon#about to write, iclass 33, count 2 2006.161.08:23:42.93#ibcon#wrote, iclass 33, count 2 2006.161.08:23:42.93#ibcon#about to read 3, iclass 33, count 2 2006.161.08:23:42.96#ibcon#read 3, iclass 33, count 2 2006.161.08:23:42.96#ibcon#about to read 4, iclass 33, count 2 2006.161.08:23:42.96#ibcon#read 4, iclass 33, count 2 2006.161.08:23:42.96#ibcon#about to read 5, iclass 33, count 2 2006.161.08:23:42.96#ibcon#read 5, iclass 33, count 2 2006.161.08:23:42.96#ibcon#about to read 6, iclass 33, count 2 2006.161.08:23:42.96#ibcon#read 6, iclass 33, count 2 2006.161.08:23:42.96#ibcon#end of sib2, iclass 33, count 2 2006.161.08:23:42.96#ibcon#*after write, iclass 33, count 2 2006.161.08:23:42.96#ibcon#*before return 0, iclass 33, count 2 2006.161.08:23:42.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:42.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.161.08:23:42.96#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.161.08:23:42.96#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:42.96#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:43.08#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:43.08#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:43.08#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:23:43.08#ibcon#first serial, iclass 33, count 0 2006.161.08:23:43.08#ibcon#enter sib2, iclass 33, count 0 2006.161.08:23:43.08#ibcon#flushed, iclass 33, count 0 2006.161.08:23:43.08#ibcon#about to write, iclass 33, count 0 2006.161.08:23:43.08#ibcon#wrote, iclass 33, count 0 2006.161.08:23:43.08#ibcon#about to read 3, iclass 33, count 0 2006.161.08:23:43.12#ibcon#read 3, iclass 33, count 0 2006.161.08:23:43.12#ibcon#about to read 4, iclass 33, count 0 2006.161.08:23:43.12#ibcon#read 4, iclass 33, count 0 2006.161.08:23:43.12#ibcon#about to read 5, iclass 33, count 0 2006.161.08:23:43.12#ibcon#read 5, iclass 33, count 0 2006.161.08:23:43.12#ibcon#about to read 6, iclass 33, count 0 2006.161.08:23:43.12#ibcon#read 6, iclass 33, count 0 2006.161.08:23:43.12#ibcon#end of sib2, iclass 33, count 0 2006.161.08:23:43.12#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:23:43.12#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:23:43.12#ibcon#[27=USB\r\n] 2006.161.08:23:43.12#ibcon#*before write, iclass 33, count 0 2006.161.08:23:43.12#ibcon#enter sib2, iclass 33, count 0 2006.161.08:23:43.12#ibcon#flushed, iclass 33, count 0 2006.161.08:23:43.12#ibcon#about to write, iclass 33, count 0 2006.161.08:23:43.12#ibcon#wrote, iclass 33, count 0 2006.161.08:23:43.12#ibcon#about to read 3, iclass 33, count 0 2006.161.08:23:43.15#ibcon#read 3, iclass 33, count 0 2006.161.08:23:43.15#ibcon#about to read 4, iclass 33, count 0 2006.161.08:23:43.15#ibcon#read 4, iclass 33, count 0 2006.161.08:23:43.15#ibcon#about to read 5, iclass 33, count 0 2006.161.08:23:43.15#ibcon#read 5, iclass 33, count 0 2006.161.08:23:43.15#ibcon#about to read 6, iclass 33, count 0 2006.161.08:23:43.15#ibcon#read 6, iclass 33, count 0 2006.161.08:23:43.15#ibcon#end of sib2, iclass 33, count 0 2006.161.08:23:43.15#ibcon#*after write, iclass 33, count 0 2006.161.08:23:43.15#ibcon#*before return 0, iclass 33, count 0 2006.161.08:23:43.15#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:43.15#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.161.08:23:43.15#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:23:43.15#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:23:43.15$vc4f8/vblo=5,744.99 2006.161.08:23:43.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.161.08:23:43.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.161.08:23:43.15#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:43.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:43.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:43.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:43.15#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:23:43.15#ibcon#first serial, iclass 35, count 0 2006.161.08:23:43.15#ibcon#enter sib2, iclass 35, count 0 2006.161.08:23:43.15#ibcon#flushed, iclass 35, count 0 2006.161.08:23:43.15#ibcon#about to write, iclass 35, count 0 2006.161.08:23:43.15#ibcon#wrote, iclass 35, count 0 2006.161.08:23:43.15#ibcon#about to read 3, iclass 35, count 0 2006.161.08:23:43.17#ibcon#read 3, iclass 35, count 0 2006.161.08:23:43.17#ibcon#about to read 4, iclass 35, count 0 2006.161.08:23:43.17#ibcon#read 4, iclass 35, count 0 2006.161.08:23:43.17#ibcon#about to read 5, iclass 35, count 0 2006.161.08:23:43.17#ibcon#read 5, iclass 35, count 0 2006.161.08:23:43.17#ibcon#about to read 6, iclass 35, count 0 2006.161.08:23:43.17#ibcon#read 6, iclass 35, count 0 2006.161.08:23:43.17#ibcon#end of sib2, iclass 35, count 0 2006.161.08:23:43.17#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:23:43.17#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:23:43.17#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:23:43.17#ibcon#*before write, iclass 35, count 0 2006.161.08:23:43.17#ibcon#enter sib2, iclass 35, count 0 2006.161.08:23:43.17#ibcon#flushed, iclass 35, count 0 2006.161.08:23:43.17#ibcon#about to write, iclass 35, count 0 2006.161.08:23:43.17#ibcon#wrote, iclass 35, count 0 2006.161.08:23:43.17#ibcon#about to read 3, iclass 35, count 0 2006.161.08:23:43.21#ibcon#read 3, iclass 35, count 0 2006.161.08:23:43.21#ibcon#about to read 4, iclass 35, count 0 2006.161.08:23:43.21#ibcon#read 4, iclass 35, count 0 2006.161.08:23:43.21#ibcon#about to read 5, iclass 35, count 0 2006.161.08:23:43.21#ibcon#read 5, iclass 35, count 0 2006.161.08:23:43.21#ibcon#about to read 6, iclass 35, count 0 2006.161.08:23:43.21#ibcon#read 6, iclass 35, count 0 2006.161.08:23:43.21#ibcon#end of sib2, iclass 35, count 0 2006.161.08:23:43.21#ibcon#*after write, iclass 35, count 0 2006.161.08:23:43.21#ibcon#*before return 0, iclass 35, count 0 2006.161.08:23:43.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:43.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.161.08:23:43.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:23:43.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:23:43.21$vc4f8/vb=5,4 2006.161.08:23:43.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.161.08:23:43.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.161.08:23:43.21#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:43.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:43.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:43.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:43.27#ibcon#enter wrdev, iclass 37, count 2 2006.161.08:23:43.27#ibcon#first serial, iclass 37, count 2 2006.161.08:23:43.27#ibcon#enter sib2, iclass 37, count 2 2006.161.08:23:43.27#ibcon#flushed, iclass 37, count 2 2006.161.08:23:43.27#ibcon#about to write, iclass 37, count 2 2006.161.08:23:43.27#ibcon#wrote, iclass 37, count 2 2006.161.08:23:43.27#ibcon#about to read 3, iclass 37, count 2 2006.161.08:23:43.29#ibcon#read 3, iclass 37, count 2 2006.161.08:23:43.29#ibcon#about to read 4, iclass 37, count 2 2006.161.08:23:43.29#ibcon#read 4, iclass 37, count 2 2006.161.08:23:43.29#ibcon#about to read 5, iclass 37, count 2 2006.161.08:23:43.29#ibcon#read 5, iclass 37, count 2 2006.161.08:23:43.29#ibcon#about to read 6, iclass 37, count 2 2006.161.08:23:43.29#ibcon#read 6, iclass 37, count 2 2006.161.08:23:43.29#ibcon#end of sib2, iclass 37, count 2 2006.161.08:23:43.29#ibcon#*mode == 0, iclass 37, count 2 2006.161.08:23:43.29#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.161.08:23:43.29#ibcon#[27=AT05-04\r\n] 2006.161.08:23:43.29#ibcon#*before write, iclass 37, count 2 2006.161.08:23:43.29#ibcon#enter sib2, iclass 37, count 2 2006.161.08:23:43.29#ibcon#flushed, iclass 37, count 2 2006.161.08:23:43.29#ibcon#about to write, iclass 37, count 2 2006.161.08:23:43.29#ibcon#wrote, iclass 37, count 2 2006.161.08:23:43.29#ibcon#about to read 3, iclass 37, count 2 2006.161.08:23:43.32#ibcon#read 3, iclass 37, count 2 2006.161.08:23:43.32#ibcon#about to read 4, iclass 37, count 2 2006.161.08:23:43.32#ibcon#read 4, iclass 37, count 2 2006.161.08:23:43.32#ibcon#about to read 5, iclass 37, count 2 2006.161.08:23:43.32#ibcon#read 5, iclass 37, count 2 2006.161.08:23:43.32#ibcon#about to read 6, iclass 37, count 2 2006.161.08:23:43.32#ibcon#read 6, iclass 37, count 2 2006.161.08:23:43.32#ibcon#end of sib2, iclass 37, count 2 2006.161.08:23:43.32#ibcon#*after write, iclass 37, count 2 2006.161.08:23:43.32#ibcon#*before return 0, iclass 37, count 2 2006.161.08:23:43.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:43.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.161.08:23:43.32#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.161.08:23:43.32#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:43.32#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:43.44#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:43.44#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:43.44#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:23:43.44#ibcon#first serial, iclass 37, count 0 2006.161.08:23:43.44#ibcon#enter sib2, iclass 37, count 0 2006.161.08:23:43.44#ibcon#flushed, iclass 37, count 0 2006.161.08:23:43.44#ibcon#about to write, iclass 37, count 0 2006.161.08:23:43.44#ibcon#wrote, iclass 37, count 0 2006.161.08:23:43.44#ibcon#about to read 3, iclass 37, count 0 2006.161.08:23:43.46#ibcon#read 3, iclass 37, count 0 2006.161.08:23:43.46#ibcon#about to read 4, iclass 37, count 0 2006.161.08:23:43.46#ibcon#read 4, iclass 37, count 0 2006.161.08:23:43.46#ibcon#about to read 5, iclass 37, count 0 2006.161.08:23:43.46#ibcon#read 5, iclass 37, count 0 2006.161.08:23:43.46#ibcon#about to read 6, iclass 37, count 0 2006.161.08:23:43.46#ibcon#read 6, iclass 37, count 0 2006.161.08:23:43.46#ibcon#end of sib2, iclass 37, count 0 2006.161.08:23:43.46#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:23:43.46#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:23:43.46#ibcon#[27=USB\r\n] 2006.161.08:23:43.46#ibcon#*before write, iclass 37, count 0 2006.161.08:23:43.46#ibcon#enter sib2, iclass 37, count 0 2006.161.08:23:43.46#ibcon#flushed, iclass 37, count 0 2006.161.08:23:43.46#ibcon#about to write, iclass 37, count 0 2006.161.08:23:43.46#ibcon#wrote, iclass 37, count 0 2006.161.08:23:43.46#ibcon#about to read 3, iclass 37, count 0 2006.161.08:23:43.49#ibcon#read 3, iclass 37, count 0 2006.161.08:23:43.49#ibcon#about to read 4, iclass 37, count 0 2006.161.08:23:43.49#ibcon#read 4, iclass 37, count 0 2006.161.08:23:43.49#ibcon#about to read 5, iclass 37, count 0 2006.161.08:23:43.49#ibcon#read 5, iclass 37, count 0 2006.161.08:23:43.49#ibcon#about to read 6, iclass 37, count 0 2006.161.08:23:43.49#ibcon#read 6, iclass 37, count 0 2006.161.08:23:43.49#ibcon#end of sib2, iclass 37, count 0 2006.161.08:23:43.49#ibcon#*after write, iclass 37, count 0 2006.161.08:23:43.49#ibcon#*before return 0, iclass 37, count 0 2006.161.08:23:43.49#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:43.49#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.161.08:23:43.49#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:23:43.49#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:23:43.49$vc4f8/vblo=6,752.99 2006.161.08:23:43.49#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.161.08:23:43.49#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.161.08:23:43.49#ibcon#ireg 17 cls_cnt 0 2006.161.08:23:43.49#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:43.49#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:43.49#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:43.49#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:23:43.49#ibcon#first serial, iclass 39, count 0 2006.161.08:23:43.49#ibcon#enter sib2, iclass 39, count 0 2006.161.08:23:43.49#ibcon#flushed, iclass 39, count 0 2006.161.08:23:43.49#ibcon#about to write, iclass 39, count 0 2006.161.08:23:43.49#ibcon#wrote, iclass 39, count 0 2006.161.08:23:43.49#ibcon#about to read 3, iclass 39, count 0 2006.161.08:23:43.51#ibcon#read 3, iclass 39, count 0 2006.161.08:23:43.51#ibcon#about to read 4, iclass 39, count 0 2006.161.08:23:43.51#ibcon#read 4, iclass 39, count 0 2006.161.08:23:43.51#ibcon#about to read 5, iclass 39, count 0 2006.161.08:23:43.51#ibcon#read 5, iclass 39, count 0 2006.161.08:23:43.51#ibcon#about to read 6, iclass 39, count 0 2006.161.08:23:43.51#ibcon#read 6, iclass 39, count 0 2006.161.08:23:43.51#ibcon#end of sib2, iclass 39, count 0 2006.161.08:23:43.51#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:23:43.51#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:23:43.51#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:23:43.51#ibcon#*before write, iclass 39, count 0 2006.161.08:23:43.51#ibcon#enter sib2, iclass 39, count 0 2006.161.08:23:43.51#ibcon#flushed, iclass 39, count 0 2006.161.08:23:43.51#ibcon#about to write, iclass 39, count 0 2006.161.08:23:43.51#ibcon#wrote, iclass 39, count 0 2006.161.08:23:43.51#ibcon#about to read 3, iclass 39, count 0 2006.161.08:23:43.55#ibcon#read 3, iclass 39, count 0 2006.161.08:23:43.55#ibcon#about to read 4, iclass 39, count 0 2006.161.08:23:43.55#ibcon#read 4, iclass 39, count 0 2006.161.08:23:43.55#ibcon#about to read 5, iclass 39, count 0 2006.161.08:23:43.55#ibcon#read 5, iclass 39, count 0 2006.161.08:23:43.55#ibcon#about to read 6, iclass 39, count 0 2006.161.08:23:43.55#ibcon#read 6, iclass 39, count 0 2006.161.08:23:43.55#ibcon#end of sib2, iclass 39, count 0 2006.161.08:23:43.55#ibcon#*after write, iclass 39, count 0 2006.161.08:23:43.55#ibcon#*before return 0, iclass 39, count 0 2006.161.08:23:43.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:43.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.161.08:23:43.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:23:43.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:23:43.55$vc4f8/vb=6,4 2006.161.08:23:43.55#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.161.08:23:43.55#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.161.08:23:43.55#ibcon#ireg 11 cls_cnt 2 2006.161.08:23:43.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:43.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:43.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:43.61#ibcon#enter wrdev, iclass 3, count 2 2006.161.08:23:43.61#ibcon#first serial, iclass 3, count 2 2006.161.08:23:43.61#ibcon#enter sib2, iclass 3, count 2 2006.161.08:23:43.61#ibcon#flushed, iclass 3, count 2 2006.161.08:23:43.61#ibcon#about to write, iclass 3, count 2 2006.161.08:23:43.61#ibcon#wrote, iclass 3, count 2 2006.161.08:23:43.61#ibcon#about to read 3, iclass 3, count 2 2006.161.08:23:43.63#ibcon#read 3, iclass 3, count 2 2006.161.08:23:43.63#ibcon#about to read 4, iclass 3, count 2 2006.161.08:23:43.63#ibcon#read 4, iclass 3, count 2 2006.161.08:23:43.63#ibcon#about to read 5, iclass 3, count 2 2006.161.08:23:43.63#ibcon#read 5, iclass 3, count 2 2006.161.08:23:43.63#ibcon#about to read 6, iclass 3, count 2 2006.161.08:23:43.63#ibcon#read 6, iclass 3, count 2 2006.161.08:23:43.63#ibcon#end of sib2, iclass 3, count 2 2006.161.08:23:43.63#ibcon#*mode == 0, iclass 3, count 2 2006.161.08:23:43.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.161.08:23:43.63#ibcon#[27=AT06-04\r\n] 2006.161.08:23:43.63#ibcon#*before write, iclass 3, count 2 2006.161.08:23:43.63#ibcon#enter sib2, iclass 3, count 2 2006.161.08:23:43.63#ibcon#flushed, iclass 3, count 2 2006.161.08:23:43.63#ibcon#about to write, iclass 3, count 2 2006.161.08:23:43.63#ibcon#wrote, iclass 3, count 2 2006.161.08:23:43.63#ibcon#about to read 3, iclass 3, count 2 2006.161.08:23:43.66#ibcon#read 3, iclass 3, count 2 2006.161.08:23:43.66#ibcon#about to read 4, iclass 3, count 2 2006.161.08:23:43.66#ibcon#read 4, iclass 3, count 2 2006.161.08:23:43.66#ibcon#about to read 5, iclass 3, count 2 2006.161.08:23:43.66#ibcon#read 5, iclass 3, count 2 2006.161.08:23:43.66#ibcon#about to read 6, iclass 3, count 2 2006.161.08:23:43.66#ibcon#read 6, iclass 3, count 2 2006.161.08:23:43.66#ibcon#end of sib2, iclass 3, count 2 2006.161.08:23:43.66#ibcon#*after write, iclass 3, count 2 2006.161.08:23:43.66#ibcon#*before return 0, iclass 3, count 2 2006.161.08:23:43.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:43.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.161.08:23:43.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.161.08:23:43.66#ibcon#ireg 7 cls_cnt 0 2006.161.08:23:43.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:43.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:43.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:43.78#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:23:43.78#ibcon#first serial, iclass 3, count 0 2006.161.08:23:43.78#ibcon#enter sib2, iclass 3, count 0 2006.161.08:23:43.78#ibcon#flushed, iclass 3, count 0 2006.161.08:23:43.78#ibcon#about to write, iclass 3, count 0 2006.161.08:23:43.78#ibcon#wrote, iclass 3, count 0 2006.161.08:23:43.78#ibcon#about to read 3, iclass 3, count 0 2006.161.08:23:43.80#ibcon#read 3, iclass 3, count 0 2006.161.08:23:43.80#ibcon#about to read 4, iclass 3, count 0 2006.161.08:23:43.80#ibcon#read 4, iclass 3, count 0 2006.161.08:23:43.80#ibcon#about to read 5, iclass 3, count 0 2006.161.08:23:43.80#ibcon#read 5, iclass 3, count 0 2006.161.08:23:43.80#ibcon#about to read 6, iclass 3, count 0 2006.161.08:23:43.80#ibcon#read 6, iclass 3, count 0 2006.161.08:23:43.80#ibcon#end of sib2, iclass 3, count 0 2006.161.08:23:43.80#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:23:43.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:23:43.80#ibcon#[27=USB\r\n] 2006.161.08:23:43.80#ibcon#*before write, iclass 3, count 0 2006.161.08:23:43.80#ibcon#enter sib2, iclass 3, count 0 2006.161.08:23:43.80#ibcon#flushed, iclass 3, count 0 2006.161.08:23:43.80#ibcon#about to write, iclass 3, count 0 2006.161.08:23:43.80#ibcon#wrote, iclass 3, count 0 2006.161.08:23:43.80#ibcon#about to read 3, iclass 3, count 0 2006.161.08:23:43.83#ibcon#read 3, iclass 3, count 0 2006.161.08:23:43.83#ibcon#about to read 4, iclass 3, count 0 2006.161.08:23:43.83#ibcon#read 4, iclass 3, count 0 2006.161.08:23:43.83#ibcon#about to read 5, iclass 3, count 0 2006.161.08:23:43.83#ibcon#read 5, iclass 3, count 0 2006.161.08:23:43.83#ibcon#about to read 6, iclass 3, count 0 2006.161.08:23:43.83#ibcon#read 6, iclass 3, count 0 2006.161.08:23:43.83#ibcon#end of sib2, iclass 3, count 0 2006.161.08:23:43.83#ibcon#*after write, iclass 3, count 0 2006.161.08:23:43.83#ibcon#*before return 0, iclass 3, count 0 2006.161.08:23:43.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:43.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.161.08:23:43.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:23:43.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:23:43.83$vc4f8/vabw=wide 2006.161.08:23:43.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.161.08:23:43.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.161.08:23:43.83#ibcon#ireg 8 cls_cnt 0 2006.161.08:23:43.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:43.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:43.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:43.83#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:23:43.83#ibcon#first serial, iclass 5, count 0 2006.161.08:23:43.83#ibcon#enter sib2, iclass 5, count 0 2006.161.08:23:43.83#ibcon#flushed, iclass 5, count 0 2006.161.08:23:43.83#ibcon#about to write, iclass 5, count 0 2006.161.08:23:43.83#ibcon#wrote, iclass 5, count 0 2006.161.08:23:43.83#ibcon#about to read 3, iclass 5, count 0 2006.161.08:23:43.85#ibcon#read 3, iclass 5, count 0 2006.161.08:23:43.85#ibcon#about to read 4, iclass 5, count 0 2006.161.08:23:43.85#ibcon#read 4, iclass 5, count 0 2006.161.08:23:43.85#ibcon#about to read 5, iclass 5, count 0 2006.161.08:23:43.85#ibcon#read 5, iclass 5, count 0 2006.161.08:23:43.85#ibcon#about to read 6, iclass 5, count 0 2006.161.08:23:43.85#ibcon#read 6, iclass 5, count 0 2006.161.08:23:43.85#ibcon#end of sib2, iclass 5, count 0 2006.161.08:23:43.85#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:23:43.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:23:43.85#ibcon#[25=BW32\r\n] 2006.161.08:23:43.85#ibcon#*before write, iclass 5, count 0 2006.161.08:23:43.85#ibcon#enter sib2, iclass 5, count 0 2006.161.08:23:43.85#ibcon#flushed, iclass 5, count 0 2006.161.08:23:43.85#ibcon#about to write, iclass 5, count 0 2006.161.08:23:43.85#ibcon#wrote, iclass 5, count 0 2006.161.08:23:43.85#ibcon#about to read 3, iclass 5, count 0 2006.161.08:23:43.88#ibcon#read 3, iclass 5, count 0 2006.161.08:23:43.88#ibcon#about to read 4, iclass 5, count 0 2006.161.08:23:43.88#ibcon#read 4, iclass 5, count 0 2006.161.08:23:43.88#ibcon#about to read 5, iclass 5, count 0 2006.161.08:23:43.88#ibcon#read 5, iclass 5, count 0 2006.161.08:23:43.88#ibcon#about to read 6, iclass 5, count 0 2006.161.08:23:43.88#ibcon#read 6, iclass 5, count 0 2006.161.08:23:43.88#ibcon#end of sib2, iclass 5, count 0 2006.161.08:23:43.88#ibcon#*after write, iclass 5, count 0 2006.161.08:23:43.88#ibcon#*before return 0, iclass 5, count 0 2006.161.08:23:43.88#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:43.88#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.161.08:23:43.88#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:23:43.88#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:23:43.88$vc4f8/vbbw=wide 2006.161.08:23:43.88#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:23:43.88#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:23:43.88#ibcon#ireg 8 cls_cnt 0 2006.161.08:23:43.88#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:23:43.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:23:43.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:23:43.95#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:23:43.95#ibcon#first serial, iclass 7, count 0 2006.161.08:23:43.95#ibcon#enter sib2, iclass 7, count 0 2006.161.08:23:43.95#ibcon#flushed, iclass 7, count 0 2006.161.08:23:43.95#ibcon#about to write, iclass 7, count 0 2006.161.08:23:43.95#ibcon#wrote, iclass 7, count 0 2006.161.08:23:43.95#ibcon#about to read 3, iclass 7, count 0 2006.161.08:23:43.97#ibcon#read 3, iclass 7, count 0 2006.161.08:23:43.97#ibcon#about to read 4, iclass 7, count 0 2006.161.08:23:43.97#ibcon#read 4, iclass 7, count 0 2006.161.08:23:43.97#ibcon#about to read 5, iclass 7, count 0 2006.161.08:23:43.97#ibcon#read 5, iclass 7, count 0 2006.161.08:23:43.97#ibcon#about to read 6, iclass 7, count 0 2006.161.08:23:43.97#ibcon#read 6, iclass 7, count 0 2006.161.08:23:43.97#ibcon#end of sib2, iclass 7, count 0 2006.161.08:23:43.97#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:23:43.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:23:43.97#ibcon#[27=BW32\r\n] 2006.161.08:23:43.97#ibcon#*before write, iclass 7, count 0 2006.161.08:23:43.97#ibcon#enter sib2, iclass 7, count 0 2006.161.08:23:43.97#ibcon#flushed, iclass 7, count 0 2006.161.08:23:43.97#ibcon#about to write, iclass 7, count 0 2006.161.08:23:43.97#ibcon#wrote, iclass 7, count 0 2006.161.08:23:43.97#ibcon#about to read 3, iclass 7, count 0 2006.161.08:23:44.00#ibcon#read 3, iclass 7, count 0 2006.161.08:23:44.00#ibcon#about to read 4, iclass 7, count 0 2006.161.08:23:44.00#ibcon#read 4, iclass 7, count 0 2006.161.08:23:44.00#ibcon#about to read 5, iclass 7, count 0 2006.161.08:23:44.00#ibcon#read 5, iclass 7, count 0 2006.161.08:23:44.00#ibcon#about to read 6, iclass 7, count 0 2006.161.08:23:44.00#ibcon#read 6, iclass 7, count 0 2006.161.08:23:44.00#ibcon#end of sib2, iclass 7, count 0 2006.161.08:23:44.00#ibcon#*after write, iclass 7, count 0 2006.161.08:23:44.00#ibcon#*before return 0, iclass 7, count 0 2006.161.08:23:44.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:23:44.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:23:44.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:23:44.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:23:44.00$4f8m12a/ifd4f 2006.161.08:23:44.00$ifd4f/lo= 2006.161.08:23:44.00$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:23:44.00$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:23:44.00$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:23:44.00$ifd4f/patch= 2006.161.08:23:44.00$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:23:44.00$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:23:44.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:23:44.00$4f8m12a/"form=m,16.000,1:2 2006.161.08:23:44.00$4f8m12a/"tpicd 2006.161.08:23:44.00$4f8m12a/echo=off 2006.161.08:23:44.00$4f8m12a/xlog=off 2006.161.08:23:44.00:!2006.161.08:24:30 2006.161.08:24:04.14#trakl#Source acquired 2006.161.08:24:04.14#flagr#flagr/antenna,acquired 2006.161.08:24:30.00:preob 2006.161.08:24:30.14/onsource/TRACKING 2006.161.08:24:30.14:!2006.161.08:24:40 2006.161.08:24:40.00:data_valid=on 2006.161.08:24:40.00:midob 2006.161.08:24:40.14/onsource/TRACKING 2006.161.08:24:40.14/wx/23.99,1002.6,87 2006.161.08:24:40.24/cable/+6.4991E-03 2006.161.08:24:41.33/va/01,08,usb,yes,28,30 2006.161.08:24:41.33/va/02,07,usb,yes,28,30 2006.161.08:24:41.33/va/03,06,usb,yes,30,30 2006.161.08:24:41.33/va/04,07,usb,yes,29,31 2006.161.08:24:41.33/va/05,07,usb,yes,29,31 2006.161.08:24:41.33/va/06,06,usb,yes,29,28 2006.161.08:24:41.33/va/07,06,usb,yes,29,29 2006.161.08:24:41.33/va/08,07,usb,yes,27,27 2006.161.08:24:41.56/valo/01,532.99,yes,locked 2006.161.08:24:41.56/valo/02,572.99,yes,locked 2006.161.08:24:41.56/valo/03,672.99,yes,locked 2006.161.08:24:41.56/valo/04,832.99,yes,locked 2006.161.08:24:41.56/valo/05,652.99,yes,locked 2006.161.08:24:41.56/valo/06,772.99,yes,locked 2006.161.08:24:41.56/valo/07,832.99,yes,locked 2006.161.08:24:41.56/valo/08,852.99,yes,locked 2006.161.08:24:42.65/vb/01,04,usb,yes,29,27 2006.161.08:24:42.65/vb/02,04,usb,yes,30,32 2006.161.08:24:42.65/vb/03,04,usb,yes,27,30 2006.161.08:24:42.65/vb/04,04,usb,yes,28,28 2006.161.08:24:42.65/vb/05,04,usb,yes,26,30 2006.161.08:24:42.65/vb/06,04,usb,yes,27,30 2006.161.08:24:42.65/vb/07,04,usb,yes,29,29 2006.161.08:24:42.65/vb/08,04,usb,yes,27,30 2006.161.08:24:42.88/vblo/01,632.99,yes,locked 2006.161.08:24:42.88/vblo/02,640.99,yes,locked 2006.161.08:24:42.88/vblo/03,656.99,yes,locked 2006.161.08:24:42.88/vblo/04,712.99,yes,locked 2006.161.08:24:42.88/vblo/05,744.99,yes,locked 2006.161.08:24:42.88/vblo/06,752.99,yes,locked 2006.161.08:24:42.88/vblo/07,734.99,yes,locked 2006.161.08:24:42.88/vblo/08,744.99,yes,locked 2006.161.08:24:43.03/vabw/8 2006.161.08:24:43.18/vbbw/8 2006.161.08:24:43.27/xfe/off,on,15.2 2006.161.08:24:43.66/ifatt/23,28,28,28 2006.161.08:24:44.08/fmout-gps/S +4.52E-07 2006.161.08:24:44.12:!2006.161.08:25:40 2006.161.08:25:40.00:data_valid=off 2006.161.08:25:40.00:postob 2006.161.08:25:40.08/cable/+6.4994E-03 2006.161.08:25:40.08/wx/23.99,1002.6,87 2006.161.08:25:41.08/fmout-gps/S +4.51E-07 2006.161.08:25:41.08:scan_name=161-0826,k06161,60 2006.161.08:25:41.08:source=0748+126,075052.05,123104.8,2000.0,ccw 2006.161.08:25:41.16#flagr#flagr/antenna,new-source 2006.161.08:25:42.14:checkk5 2006.161.08:25:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:25:42.92/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:25:43.33/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:25:43.75/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:25:44.47/chk_obsdata//k5ts1/T1610824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:25:45.11/chk_obsdata//k5ts2/T1610824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:25:45.48/chk_obsdata//k5ts3/T1610824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:25:46.07/chk_obsdata//k5ts4/T1610824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.161.08:25:46.79/k5log//k5ts1_log_newline 2006.161.08:25:47.61/k5log//k5ts2_log_newline 2006.161.08:25:48.68/k5log//k5ts3_log_newline 2006.161.08:25:49.50/k5log//k5ts4_log_newline 2006.161.08:25:49.52/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:25:49.52:4f8m12a=3 2006.161.08:25:49.52$4f8m12a/echo=on 2006.161.08:25:49.52$4f8m12a/pcalon 2006.161.08:25:49.52$pcalon/"no phase cal control is implemented here 2006.161.08:25:49.52$4f8m12a/"tpicd=stop 2006.161.08:25:49.52$4f8m12a/vc4f8 2006.161.08:25:49.52$vc4f8/valo=1,532.99 2006.161.08:25:49.52#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:25:49.52#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:25:49.52#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:49.52#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:49.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:49.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:49.52#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:25:49.52#ibcon#first serial, iclass 24, count 0 2006.161.08:25:49.52#ibcon#enter sib2, iclass 24, count 0 2006.161.08:25:49.52#ibcon#flushed, iclass 24, count 0 2006.161.08:25:49.52#ibcon#about to write, iclass 24, count 0 2006.161.08:25:49.52#ibcon#wrote, iclass 24, count 0 2006.161.08:25:49.52#ibcon#about to read 3, iclass 24, count 0 2006.161.08:25:49.57#ibcon#read 3, iclass 24, count 0 2006.161.08:25:49.57#ibcon#about to read 4, iclass 24, count 0 2006.161.08:25:49.57#ibcon#read 4, iclass 24, count 0 2006.161.08:25:49.57#ibcon#about to read 5, iclass 24, count 0 2006.161.08:25:49.57#ibcon#read 5, iclass 24, count 0 2006.161.08:25:49.57#ibcon#about to read 6, iclass 24, count 0 2006.161.08:25:49.57#ibcon#read 6, iclass 24, count 0 2006.161.08:25:49.57#ibcon#end of sib2, iclass 24, count 0 2006.161.08:25:49.57#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:25:49.57#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:25:49.57#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:25:49.57#ibcon#*before write, iclass 24, count 0 2006.161.08:25:49.57#ibcon#enter sib2, iclass 24, count 0 2006.161.08:25:49.57#ibcon#flushed, iclass 24, count 0 2006.161.08:25:49.57#ibcon#about to write, iclass 24, count 0 2006.161.08:25:49.57#ibcon#wrote, iclass 24, count 0 2006.161.08:25:49.57#ibcon#about to read 3, iclass 24, count 0 2006.161.08:25:49.62#ibcon#read 3, iclass 24, count 0 2006.161.08:25:49.62#ibcon#about to read 4, iclass 24, count 0 2006.161.08:25:49.62#ibcon#read 4, iclass 24, count 0 2006.161.08:25:49.62#ibcon#about to read 5, iclass 24, count 0 2006.161.08:25:49.62#ibcon#read 5, iclass 24, count 0 2006.161.08:25:49.62#ibcon#about to read 6, iclass 24, count 0 2006.161.08:25:49.62#ibcon#read 6, iclass 24, count 0 2006.161.08:25:49.62#ibcon#end of sib2, iclass 24, count 0 2006.161.08:25:49.62#ibcon#*after write, iclass 24, count 0 2006.161.08:25:49.62#ibcon#*before return 0, iclass 24, count 0 2006.161.08:25:49.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:49.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:49.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:25:49.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:25:49.62$vc4f8/va=1,8 2006.161.08:25:49.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:25:49.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:25:49.62#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:49.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:49.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:49.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:49.62#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:25:49.62#ibcon#first serial, iclass 26, count 2 2006.161.08:25:49.62#ibcon#enter sib2, iclass 26, count 2 2006.161.08:25:49.62#ibcon#flushed, iclass 26, count 2 2006.161.08:25:49.62#ibcon#about to write, iclass 26, count 2 2006.161.08:25:49.62#ibcon#wrote, iclass 26, count 2 2006.161.08:25:49.62#ibcon#about to read 3, iclass 26, count 2 2006.161.08:25:49.64#ibcon#read 3, iclass 26, count 2 2006.161.08:25:49.64#ibcon#about to read 4, iclass 26, count 2 2006.161.08:25:49.64#ibcon#read 4, iclass 26, count 2 2006.161.08:25:49.64#ibcon#about to read 5, iclass 26, count 2 2006.161.08:25:49.64#ibcon#read 5, iclass 26, count 2 2006.161.08:25:49.64#ibcon#about to read 6, iclass 26, count 2 2006.161.08:25:49.64#ibcon#read 6, iclass 26, count 2 2006.161.08:25:49.64#ibcon#end of sib2, iclass 26, count 2 2006.161.08:25:49.64#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:25:49.64#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:25:49.64#ibcon#[25=AT01-08\r\n] 2006.161.08:25:49.64#ibcon#*before write, iclass 26, count 2 2006.161.08:25:49.64#ibcon#enter sib2, iclass 26, count 2 2006.161.08:25:49.64#ibcon#flushed, iclass 26, count 2 2006.161.08:25:49.64#ibcon#about to write, iclass 26, count 2 2006.161.08:25:49.64#ibcon#wrote, iclass 26, count 2 2006.161.08:25:49.64#ibcon#about to read 3, iclass 26, count 2 2006.161.08:25:49.67#ibcon#read 3, iclass 26, count 2 2006.161.08:25:49.67#ibcon#about to read 4, iclass 26, count 2 2006.161.08:25:49.67#ibcon#read 4, iclass 26, count 2 2006.161.08:25:49.67#ibcon#about to read 5, iclass 26, count 2 2006.161.08:25:49.67#ibcon#read 5, iclass 26, count 2 2006.161.08:25:49.67#ibcon#about to read 6, iclass 26, count 2 2006.161.08:25:49.67#ibcon#read 6, iclass 26, count 2 2006.161.08:25:49.67#ibcon#end of sib2, iclass 26, count 2 2006.161.08:25:49.67#ibcon#*after write, iclass 26, count 2 2006.161.08:25:49.67#ibcon#*before return 0, iclass 26, count 2 2006.161.08:25:49.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:49.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:49.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:25:49.67#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:49.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:49.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:49.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:49.79#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:25:49.79#ibcon#first serial, iclass 26, count 0 2006.161.08:25:49.79#ibcon#enter sib2, iclass 26, count 0 2006.161.08:25:49.79#ibcon#flushed, iclass 26, count 0 2006.161.08:25:49.79#ibcon#about to write, iclass 26, count 0 2006.161.08:25:49.79#ibcon#wrote, iclass 26, count 0 2006.161.08:25:49.79#ibcon#about to read 3, iclass 26, count 0 2006.161.08:25:49.81#ibcon#read 3, iclass 26, count 0 2006.161.08:25:49.81#ibcon#about to read 4, iclass 26, count 0 2006.161.08:25:49.81#ibcon#read 4, iclass 26, count 0 2006.161.08:25:49.81#ibcon#about to read 5, iclass 26, count 0 2006.161.08:25:49.81#ibcon#read 5, iclass 26, count 0 2006.161.08:25:49.81#ibcon#about to read 6, iclass 26, count 0 2006.161.08:25:49.81#ibcon#read 6, iclass 26, count 0 2006.161.08:25:49.81#ibcon#end of sib2, iclass 26, count 0 2006.161.08:25:49.81#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:25:49.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:25:49.81#ibcon#[25=USB\r\n] 2006.161.08:25:49.81#ibcon#*before write, iclass 26, count 0 2006.161.08:25:49.81#ibcon#enter sib2, iclass 26, count 0 2006.161.08:25:49.81#ibcon#flushed, iclass 26, count 0 2006.161.08:25:49.81#ibcon#about to write, iclass 26, count 0 2006.161.08:25:49.81#ibcon#wrote, iclass 26, count 0 2006.161.08:25:49.81#ibcon#about to read 3, iclass 26, count 0 2006.161.08:25:49.84#ibcon#read 3, iclass 26, count 0 2006.161.08:25:49.84#ibcon#about to read 4, iclass 26, count 0 2006.161.08:25:49.84#ibcon#read 4, iclass 26, count 0 2006.161.08:25:49.84#ibcon#about to read 5, iclass 26, count 0 2006.161.08:25:49.84#ibcon#read 5, iclass 26, count 0 2006.161.08:25:49.84#ibcon#about to read 6, iclass 26, count 0 2006.161.08:25:49.84#ibcon#read 6, iclass 26, count 0 2006.161.08:25:49.84#ibcon#end of sib2, iclass 26, count 0 2006.161.08:25:49.84#ibcon#*after write, iclass 26, count 0 2006.161.08:25:49.84#ibcon#*before return 0, iclass 26, count 0 2006.161.08:25:49.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:49.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:49.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:25:49.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:25:49.84$vc4f8/valo=2,572.99 2006.161.08:25:49.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:25:49.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:25:49.84#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:49.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:49.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:49.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:49.84#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:25:49.84#ibcon#first serial, iclass 28, count 0 2006.161.08:25:49.84#ibcon#enter sib2, iclass 28, count 0 2006.161.08:25:49.84#ibcon#flushed, iclass 28, count 0 2006.161.08:25:49.84#ibcon#about to write, iclass 28, count 0 2006.161.08:25:49.84#ibcon#wrote, iclass 28, count 0 2006.161.08:25:49.84#ibcon#about to read 3, iclass 28, count 0 2006.161.08:25:49.86#ibcon#read 3, iclass 28, count 0 2006.161.08:25:49.86#ibcon#about to read 4, iclass 28, count 0 2006.161.08:25:49.86#ibcon#read 4, iclass 28, count 0 2006.161.08:25:49.86#ibcon#about to read 5, iclass 28, count 0 2006.161.08:25:49.86#ibcon#read 5, iclass 28, count 0 2006.161.08:25:49.86#ibcon#about to read 6, iclass 28, count 0 2006.161.08:25:49.86#ibcon#read 6, iclass 28, count 0 2006.161.08:25:49.86#ibcon#end of sib2, iclass 28, count 0 2006.161.08:25:49.86#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:25:49.86#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:25:49.86#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:25:49.86#ibcon#*before write, iclass 28, count 0 2006.161.08:25:49.86#ibcon#enter sib2, iclass 28, count 0 2006.161.08:25:49.86#ibcon#flushed, iclass 28, count 0 2006.161.08:25:49.86#ibcon#about to write, iclass 28, count 0 2006.161.08:25:49.86#ibcon#wrote, iclass 28, count 0 2006.161.08:25:49.86#ibcon#about to read 3, iclass 28, count 0 2006.161.08:25:49.90#ibcon#read 3, iclass 28, count 0 2006.161.08:25:49.90#ibcon#about to read 4, iclass 28, count 0 2006.161.08:25:49.90#ibcon#read 4, iclass 28, count 0 2006.161.08:25:49.90#ibcon#about to read 5, iclass 28, count 0 2006.161.08:25:49.90#ibcon#read 5, iclass 28, count 0 2006.161.08:25:49.90#ibcon#about to read 6, iclass 28, count 0 2006.161.08:25:49.90#ibcon#read 6, iclass 28, count 0 2006.161.08:25:49.90#ibcon#end of sib2, iclass 28, count 0 2006.161.08:25:49.90#ibcon#*after write, iclass 28, count 0 2006.161.08:25:49.90#ibcon#*before return 0, iclass 28, count 0 2006.161.08:25:49.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:49.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:49.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:25:49.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:25:49.90$vc4f8/va=2,7 2006.161.08:25:49.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.08:25:49.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.08:25:49.90#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:49.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:49.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:49.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:49.96#ibcon#enter wrdev, iclass 30, count 2 2006.161.08:25:49.96#ibcon#first serial, iclass 30, count 2 2006.161.08:25:49.96#ibcon#enter sib2, iclass 30, count 2 2006.161.08:25:49.96#ibcon#flushed, iclass 30, count 2 2006.161.08:25:49.96#ibcon#about to write, iclass 30, count 2 2006.161.08:25:49.96#ibcon#wrote, iclass 30, count 2 2006.161.08:25:49.96#ibcon#about to read 3, iclass 30, count 2 2006.161.08:25:49.99#ibcon#read 3, iclass 30, count 2 2006.161.08:25:49.99#ibcon#about to read 4, iclass 30, count 2 2006.161.08:25:49.99#ibcon#read 4, iclass 30, count 2 2006.161.08:25:49.99#ibcon#about to read 5, iclass 30, count 2 2006.161.08:25:49.99#ibcon#read 5, iclass 30, count 2 2006.161.08:25:49.99#ibcon#about to read 6, iclass 30, count 2 2006.161.08:25:49.99#ibcon#read 6, iclass 30, count 2 2006.161.08:25:49.99#ibcon#end of sib2, iclass 30, count 2 2006.161.08:25:49.99#ibcon#*mode == 0, iclass 30, count 2 2006.161.08:25:49.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.08:25:49.99#ibcon#[25=AT02-07\r\n] 2006.161.08:25:49.99#ibcon#*before write, iclass 30, count 2 2006.161.08:25:49.99#ibcon#enter sib2, iclass 30, count 2 2006.161.08:25:49.99#ibcon#flushed, iclass 30, count 2 2006.161.08:25:49.99#ibcon#about to write, iclass 30, count 2 2006.161.08:25:49.99#ibcon#wrote, iclass 30, count 2 2006.161.08:25:49.99#ibcon#about to read 3, iclass 30, count 2 2006.161.08:25:50.02#ibcon#read 3, iclass 30, count 2 2006.161.08:25:50.02#ibcon#about to read 4, iclass 30, count 2 2006.161.08:25:50.02#ibcon#read 4, iclass 30, count 2 2006.161.08:25:50.02#ibcon#about to read 5, iclass 30, count 2 2006.161.08:25:50.02#ibcon#read 5, iclass 30, count 2 2006.161.08:25:50.02#ibcon#about to read 6, iclass 30, count 2 2006.161.08:25:50.02#ibcon#read 6, iclass 30, count 2 2006.161.08:25:50.02#ibcon#end of sib2, iclass 30, count 2 2006.161.08:25:50.02#ibcon#*after write, iclass 30, count 2 2006.161.08:25:50.02#ibcon#*before return 0, iclass 30, count 2 2006.161.08:25:50.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:50.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:50.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.08:25:50.02#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:50.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:50.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:50.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:50.14#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:25:50.14#ibcon#first serial, iclass 30, count 0 2006.161.08:25:50.14#ibcon#enter sib2, iclass 30, count 0 2006.161.08:25:50.14#ibcon#flushed, iclass 30, count 0 2006.161.08:25:50.14#ibcon#about to write, iclass 30, count 0 2006.161.08:25:50.14#ibcon#wrote, iclass 30, count 0 2006.161.08:25:50.14#ibcon#about to read 3, iclass 30, count 0 2006.161.08:25:50.16#ibcon#read 3, iclass 30, count 0 2006.161.08:25:50.16#ibcon#about to read 4, iclass 30, count 0 2006.161.08:25:50.16#ibcon#read 4, iclass 30, count 0 2006.161.08:25:50.16#ibcon#about to read 5, iclass 30, count 0 2006.161.08:25:50.16#ibcon#read 5, iclass 30, count 0 2006.161.08:25:50.16#ibcon#about to read 6, iclass 30, count 0 2006.161.08:25:50.16#ibcon#read 6, iclass 30, count 0 2006.161.08:25:50.16#ibcon#end of sib2, iclass 30, count 0 2006.161.08:25:50.16#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:25:50.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:25:50.16#ibcon#[25=USB\r\n] 2006.161.08:25:50.16#ibcon#*before write, iclass 30, count 0 2006.161.08:25:50.16#ibcon#enter sib2, iclass 30, count 0 2006.161.08:25:50.16#ibcon#flushed, iclass 30, count 0 2006.161.08:25:50.16#ibcon#about to write, iclass 30, count 0 2006.161.08:25:50.16#ibcon#wrote, iclass 30, count 0 2006.161.08:25:50.16#ibcon#about to read 3, iclass 30, count 0 2006.161.08:25:50.19#ibcon#read 3, iclass 30, count 0 2006.161.08:25:50.19#ibcon#about to read 4, iclass 30, count 0 2006.161.08:25:50.19#ibcon#read 4, iclass 30, count 0 2006.161.08:25:50.19#ibcon#about to read 5, iclass 30, count 0 2006.161.08:25:50.19#ibcon#read 5, iclass 30, count 0 2006.161.08:25:50.19#ibcon#about to read 6, iclass 30, count 0 2006.161.08:25:50.19#ibcon#read 6, iclass 30, count 0 2006.161.08:25:50.19#ibcon#end of sib2, iclass 30, count 0 2006.161.08:25:50.19#ibcon#*after write, iclass 30, count 0 2006.161.08:25:50.19#ibcon#*before return 0, iclass 30, count 0 2006.161.08:25:50.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:50.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:50.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:25:50.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:25:50.19$vc4f8/valo=3,672.99 2006.161.08:25:50.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.08:25:50.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.08:25:50.19#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:50.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:50.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:50.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:50.19#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:25:50.19#ibcon#first serial, iclass 32, count 0 2006.161.08:25:50.19#ibcon#enter sib2, iclass 32, count 0 2006.161.08:25:50.19#ibcon#flushed, iclass 32, count 0 2006.161.08:25:50.19#ibcon#about to write, iclass 32, count 0 2006.161.08:25:50.19#ibcon#wrote, iclass 32, count 0 2006.161.08:25:50.19#ibcon#about to read 3, iclass 32, count 0 2006.161.08:25:50.22#ibcon#read 3, iclass 32, count 0 2006.161.08:25:50.22#ibcon#about to read 4, iclass 32, count 0 2006.161.08:25:50.22#ibcon#read 4, iclass 32, count 0 2006.161.08:25:50.22#ibcon#about to read 5, iclass 32, count 0 2006.161.08:25:50.22#ibcon#read 5, iclass 32, count 0 2006.161.08:25:50.22#ibcon#about to read 6, iclass 32, count 0 2006.161.08:25:50.22#ibcon#read 6, iclass 32, count 0 2006.161.08:25:50.22#ibcon#end of sib2, iclass 32, count 0 2006.161.08:25:50.22#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:25:50.22#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:25:50.22#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:25:50.22#ibcon#*before write, iclass 32, count 0 2006.161.08:25:50.22#ibcon#enter sib2, iclass 32, count 0 2006.161.08:25:50.22#ibcon#flushed, iclass 32, count 0 2006.161.08:25:50.22#ibcon#about to write, iclass 32, count 0 2006.161.08:25:50.22#ibcon#wrote, iclass 32, count 0 2006.161.08:25:50.22#ibcon#about to read 3, iclass 32, count 0 2006.161.08:25:50.26#ibcon#read 3, iclass 32, count 0 2006.161.08:25:50.26#ibcon#about to read 4, iclass 32, count 0 2006.161.08:25:50.26#ibcon#read 4, iclass 32, count 0 2006.161.08:25:50.26#ibcon#about to read 5, iclass 32, count 0 2006.161.08:25:50.26#ibcon#read 5, iclass 32, count 0 2006.161.08:25:50.26#ibcon#about to read 6, iclass 32, count 0 2006.161.08:25:50.26#ibcon#read 6, iclass 32, count 0 2006.161.08:25:50.26#ibcon#end of sib2, iclass 32, count 0 2006.161.08:25:50.26#ibcon#*after write, iclass 32, count 0 2006.161.08:25:50.26#ibcon#*before return 0, iclass 32, count 0 2006.161.08:25:50.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:50.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:50.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:25:50.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:25:50.26$vc4f8/va=3,6 2006.161.08:25:50.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.08:25:50.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.08:25:50.26#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:50.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:50.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:50.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:50.31#ibcon#enter wrdev, iclass 34, count 2 2006.161.08:25:50.31#ibcon#first serial, iclass 34, count 2 2006.161.08:25:50.31#ibcon#enter sib2, iclass 34, count 2 2006.161.08:25:50.31#ibcon#flushed, iclass 34, count 2 2006.161.08:25:50.31#ibcon#about to write, iclass 34, count 2 2006.161.08:25:50.31#ibcon#wrote, iclass 34, count 2 2006.161.08:25:50.31#ibcon#about to read 3, iclass 34, count 2 2006.161.08:25:50.33#ibcon#read 3, iclass 34, count 2 2006.161.08:25:50.33#ibcon#about to read 4, iclass 34, count 2 2006.161.08:25:50.33#ibcon#read 4, iclass 34, count 2 2006.161.08:25:50.33#ibcon#about to read 5, iclass 34, count 2 2006.161.08:25:50.33#ibcon#read 5, iclass 34, count 2 2006.161.08:25:50.33#ibcon#about to read 6, iclass 34, count 2 2006.161.08:25:50.33#ibcon#read 6, iclass 34, count 2 2006.161.08:25:50.33#ibcon#end of sib2, iclass 34, count 2 2006.161.08:25:50.33#ibcon#*mode == 0, iclass 34, count 2 2006.161.08:25:50.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.08:25:50.33#ibcon#[25=AT03-06\r\n] 2006.161.08:25:50.33#ibcon#*before write, iclass 34, count 2 2006.161.08:25:50.33#ibcon#enter sib2, iclass 34, count 2 2006.161.08:25:50.33#ibcon#flushed, iclass 34, count 2 2006.161.08:25:50.33#ibcon#about to write, iclass 34, count 2 2006.161.08:25:50.33#ibcon#wrote, iclass 34, count 2 2006.161.08:25:50.33#ibcon#about to read 3, iclass 34, count 2 2006.161.08:25:50.36#ibcon#read 3, iclass 34, count 2 2006.161.08:25:50.36#ibcon#about to read 4, iclass 34, count 2 2006.161.08:25:50.36#ibcon#read 4, iclass 34, count 2 2006.161.08:25:50.36#ibcon#about to read 5, iclass 34, count 2 2006.161.08:25:50.36#ibcon#read 5, iclass 34, count 2 2006.161.08:25:50.36#ibcon#about to read 6, iclass 34, count 2 2006.161.08:25:50.36#ibcon#read 6, iclass 34, count 2 2006.161.08:25:50.36#ibcon#end of sib2, iclass 34, count 2 2006.161.08:25:50.36#ibcon#*after write, iclass 34, count 2 2006.161.08:25:50.36#ibcon#*before return 0, iclass 34, count 2 2006.161.08:25:50.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:50.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:50.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.08:25:50.36#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:50.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:50.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:50.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:50.48#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:25:50.48#ibcon#first serial, iclass 34, count 0 2006.161.08:25:50.48#ibcon#enter sib2, iclass 34, count 0 2006.161.08:25:50.48#ibcon#flushed, iclass 34, count 0 2006.161.08:25:50.48#ibcon#about to write, iclass 34, count 0 2006.161.08:25:50.48#ibcon#wrote, iclass 34, count 0 2006.161.08:25:50.48#ibcon#about to read 3, iclass 34, count 0 2006.161.08:25:50.50#ibcon#read 3, iclass 34, count 0 2006.161.08:25:50.50#ibcon#about to read 4, iclass 34, count 0 2006.161.08:25:50.50#ibcon#read 4, iclass 34, count 0 2006.161.08:25:50.50#ibcon#about to read 5, iclass 34, count 0 2006.161.08:25:50.50#ibcon#read 5, iclass 34, count 0 2006.161.08:25:50.50#ibcon#about to read 6, iclass 34, count 0 2006.161.08:25:50.50#ibcon#read 6, iclass 34, count 0 2006.161.08:25:50.50#ibcon#end of sib2, iclass 34, count 0 2006.161.08:25:50.50#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:25:50.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:25:50.50#ibcon#[25=USB\r\n] 2006.161.08:25:50.50#ibcon#*before write, iclass 34, count 0 2006.161.08:25:50.50#ibcon#enter sib2, iclass 34, count 0 2006.161.08:25:50.50#ibcon#flushed, iclass 34, count 0 2006.161.08:25:50.50#ibcon#about to write, iclass 34, count 0 2006.161.08:25:50.50#ibcon#wrote, iclass 34, count 0 2006.161.08:25:50.50#ibcon#about to read 3, iclass 34, count 0 2006.161.08:25:50.53#ibcon#read 3, iclass 34, count 0 2006.161.08:25:50.53#ibcon#about to read 4, iclass 34, count 0 2006.161.08:25:50.53#ibcon#read 4, iclass 34, count 0 2006.161.08:25:50.53#ibcon#about to read 5, iclass 34, count 0 2006.161.08:25:50.53#ibcon#read 5, iclass 34, count 0 2006.161.08:25:50.53#ibcon#about to read 6, iclass 34, count 0 2006.161.08:25:50.53#ibcon#read 6, iclass 34, count 0 2006.161.08:25:50.53#ibcon#end of sib2, iclass 34, count 0 2006.161.08:25:50.53#ibcon#*after write, iclass 34, count 0 2006.161.08:25:50.53#ibcon#*before return 0, iclass 34, count 0 2006.161.08:25:50.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:50.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:50.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:25:50.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:25:50.53$vc4f8/valo=4,832.99 2006.161.08:25:50.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:25:50.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:25:50.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:50.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:50.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:50.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:50.53#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:25:50.53#ibcon#first serial, iclass 36, count 0 2006.161.08:25:50.53#ibcon#enter sib2, iclass 36, count 0 2006.161.08:25:50.53#ibcon#flushed, iclass 36, count 0 2006.161.08:25:50.53#ibcon#about to write, iclass 36, count 0 2006.161.08:25:50.53#ibcon#wrote, iclass 36, count 0 2006.161.08:25:50.53#ibcon#about to read 3, iclass 36, count 0 2006.161.08:25:50.55#ibcon#read 3, iclass 36, count 0 2006.161.08:25:50.55#ibcon#about to read 4, iclass 36, count 0 2006.161.08:25:50.55#ibcon#read 4, iclass 36, count 0 2006.161.08:25:50.55#ibcon#about to read 5, iclass 36, count 0 2006.161.08:25:50.55#ibcon#read 5, iclass 36, count 0 2006.161.08:25:50.55#ibcon#about to read 6, iclass 36, count 0 2006.161.08:25:50.55#ibcon#read 6, iclass 36, count 0 2006.161.08:25:50.55#ibcon#end of sib2, iclass 36, count 0 2006.161.08:25:50.55#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:25:50.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:25:50.55#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:25:50.55#ibcon#*before write, iclass 36, count 0 2006.161.08:25:50.55#ibcon#enter sib2, iclass 36, count 0 2006.161.08:25:50.55#ibcon#flushed, iclass 36, count 0 2006.161.08:25:50.55#ibcon#about to write, iclass 36, count 0 2006.161.08:25:50.55#ibcon#wrote, iclass 36, count 0 2006.161.08:25:50.55#ibcon#about to read 3, iclass 36, count 0 2006.161.08:25:50.59#ibcon#read 3, iclass 36, count 0 2006.161.08:25:50.59#ibcon#about to read 4, iclass 36, count 0 2006.161.08:25:50.59#ibcon#read 4, iclass 36, count 0 2006.161.08:25:50.59#ibcon#about to read 5, iclass 36, count 0 2006.161.08:25:50.59#ibcon#read 5, iclass 36, count 0 2006.161.08:25:50.59#ibcon#about to read 6, iclass 36, count 0 2006.161.08:25:50.59#ibcon#read 6, iclass 36, count 0 2006.161.08:25:50.59#ibcon#end of sib2, iclass 36, count 0 2006.161.08:25:50.59#ibcon#*after write, iclass 36, count 0 2006.161.08:25:50.59#ibcon#*before return 0, iclass 36, count 0 2006.161.08:25:50.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:50.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:50.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:25:50.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:25:50.59$vc4f8/va=4,7 2006.161.08:25:50.59#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.161.08:25:50.59#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.161.08:25:50.59#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:50.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:25:50.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:25:50.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:25:50.65#ibcon#enter wrdev, iclass 38, count 2 2006.161.08:25:50.65#ibcon#first serial, iclass 38, count 2 2006.161.08:25:50.65#ibcon#enter sib2, iclass 38, count 2 2006.161.08:25:50.65#ibcon#flushed, iclass 38, count 2 2006.161.08:25:50.65#ibcon#about to write, iclass 38, count 2 2006.161.08:25:50.65#ibcon#wrote, iclass 38, count 2 2006.161.08:25:50.65#ibcon#about to read 3, iclass 38, count 2 2006.161.08:25:50.67#ibcon#read 3, iclass 38, count 2 2006.161.08:25:50.67#ibcon#about to read 4, iclass 38, count 2 2006.161.08:25:50.67#ibcon#read 4, iclass 38, count 2 2006.161.08:25:50.67#ibcon#about to read 5, iclass 38, count 2 2006.161.08:25:50.67#ibcon#read 5, iclass 38, count 2 2006.161.08:25:50.67#ibcon#about to read 6, iclass 38, count 2 2006.161.08:25:50.67#ibcon#read 6, iclass 38, count 2 2006.161.08:25:50.67#ibcon#end of sib2, iclass 38, count 2 2006.161.08:25:50.67#ibcon#*mode == 0, iclass 38, count 2 2006.161.08:25:50.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.161.08:25:50.67#ibcon#[25=AT04-07\r\n] 2006.161.08:25:50.67#ibcon#*before write, iclass 38, count 2 2006.161.08:25:50.67#ibcon#enter sib2, iclass 38, count 2 2006.161.08:25:50.67#ibcon#flushed, iclass 38, count 2 2006.161.08:25:50.67#ibcon#about to write, iclass 38, count 2 2006.161.08:25:50.67#ibcon#wrote, iclass 38, count 2 2006.161.08:25:50.67#ibcon#about to read 3, iclass 38, count 2 2006.161.08:25:50.70#ibcon#read 3, iclass 38, count 2 2006.161.08:25:50.70#ibcon#about to read 4, iclass 38, count 2 2006.161.08:25:50.70#ibcon#read 4, iclass 38, count 2 2006.161.08:25:50.70#ibcon#about to read 5, iclass 38, count 2 2006.161.08:25:50.70#ibcon#read 5, iclass 38, count 2 2006.161.08:25:50.70#ibcon#about to read 6, iclass 38, count 2 2006.161.08:25:50.70#ibcon#read 6, iclass 38, count 2 2006.161.08:25:50.70#ibcon#end of sib2, iclass 38, count 2 2006.161.08:25:50.70#ibcon#*after write, iclass 38, count 2 2006.161.08:25:50.70#ibcon#*before return 0, iclass 38, count 2 2006.161.08:25:50.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:25:50.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.161.08:25:50.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.161.08:25:50.70#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:50.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:25:50.82#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:25:50.82#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:25:50.82#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:25:50.82#ibcon#first serial, iclass 38, count 0 2006.161.08:25:50.82#ibcon#enter sib2, iclass 38, count 0 2006.161.08:25:50.82#ibcon#flushed, iclass 38, count 0 2006.161.08:25:50.82#ibcon#about to write, iclass 38, count 0 2006.161.08:25:50.82#ibcon#wrote, iclass 38, count 0 2006.161.08:25:50.82#ibcon#about to read 3, iclass 38, count 0 2006.161.08:25:50.84#ibcon#read 3, iclass 38, count 0 2006.161.08:25:50.84#ibcon#about to read 4, iclass 38, count 0 2006.161.08:25:50.84#ibcon#read 4, iclass 38, count 0 2006.161.08:25:50.84#ibcon#about to read 5, iclass 38, count 0 2006.161.08:25:50.84#ibcon#read 5, iclass 38, count 0 2006.161.08:25:50.84#ibcon#about to read 6, iclass 38, count 0 2006.161.08:25:50.84#ibcon#read 6, iclass 38, count 0 2006.161.08:25:50.84#ibcon#end of sib2, iclass 38, count 0 2006.161.08:25:50.84#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:25:50.84#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:25:50.84#ibcon#[25=USB\r\n] 2006.161.08:25:50.84#ibcon#*before write, iclass 38, count 0 2006.161.08:25:50.84#ibcon#enter sib2, iclass 38, count 0 2006.161.08:25:50.84#ibcon#flushed, iclass 38, count 0 2006.161.08:25:50.84#ibcon#about to write, iclass 38, count 0 2006.161.08:25:50.84#ibcon#wrote, iclass 38, count 0 2006.161.08:25:50.84#ibcon#about to read 3, iclass 38, count 0 2006.161.08:25:50.87#ibcon#read 3, iclass 38, count 0 2006.161.08:25:50.87#ibcon#about to read 4, iclass 38, count 0 2006.161.08:25:50.87#ibcon#read 4, iclass 38, count 0 2006.161.08:25:50.87#ibcon#about to read 5, iclass 38, count 0 2006.161.08:25:50.87#ibcon#read 5, iclass 38, count 0 2006.161.08:25:50.87#ibcon#about to read 6, iclass 38, count 0 2006.161.08:25:50.87#ibcon#read 6, iclass 38, count 0 2006.161.08:25:50.87#ibcon#end of sib2, iclass 38, count 0 2006.161.08:25:50.87#ibcon#*after write, iclass 38, count 0 2006.161.08:25:50.87#ibcon#*before return 0, iclass 38, count 0 2006.161.08:25:50.87#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:25:50.87#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.161.08:25:50.87#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:25:50.87#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:25:50.87$vc4f8/valo=5,652.99 2006.161.08:25:50.87#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.161.08:25:50.87#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.161.08:25:50.87#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:50.87#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:25:50.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:25:50.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:25:50.87#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:25:50.87#ibcon#first serial, iclass 40, count 0 2006.161.08:25:50.87#ibcon#enter sib2, iclass 40, count 0 2006.161.08:25:50.87#ibcon#flushed, iclass 40, count 0 2006.161.08:25:50.87#ibcon#about to write, iclass 40, count 0 2006.161.08:25:50.87#ibcon#wrote, iclass 40, count 0 2006.161.08:25:50.87#ibcon#about to read 3, iclass 40, count 0 2006.161.08:25:50.89#ibcon#read 3, iclass 40, count 0 2006.161.08:25:50.89#ibcon#about to read 4, iclass 40, count 0 2006.161.08:25:50.89#ibcon#read 4, iclass 40, count 0 2006.161.08:25:50.89#ibcon#about to read 5, iclass 40, count 0 2006.161.08:25:50.89#ibcon#read 5, iclass 40, count 0 2006.161.08:25:50.89#ibcon#about to read 6, iclass 40, count 0 2006.161.08:25:50.89#ibcon#read 6, iclass 40, count 0 2006.161.08:25:50.89#ibcon#end of sib2, iclass 40, count 0 2006.161.08:25:50.89#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:25:50.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:25:50.89#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:25:50.89#ibcon#*before write, iclass 40, count 0 2006.161.08:25:50.89#ibcon#enter sib2, iclass 40, count 0 2006.161.08:25:50.89#ibcon#flushed, iclass 40, count 0 2006.161.08:25:50.89#ibcon#about to write, iclass 40, count 0 2006.161.08:25:50.89#ibcon#wrote, iclass 40, count 0 2006.161.08:25:50.89#ibcon#about to read 3, iclass 40, count 0 2006.161.08:25:50.93#ibcon#read 3, iclass 40, count 0 2006.161.08:25:50.93#ibcon#about to read 4, iclass 40, count 0 2006.161.08:25:50.93#ibcon#read 4, iclass 40, count 0 2006.161.08:25:50.93#ibcon#about to read 5, iclass 40, count 0 2006.161.08:25:50.93#ibcon#read 5, iclass 40, count 0 2006.161.08:25:50.93#ibcon#about to read 6, iclass 40, count 0 2006.161.08:25:50.93#ibcon#read 6, iclass 40, count 0 2006.161.08:25:50.93#ibcon#end of sib2, iclass 40, count 0 2006.161.08:25:50.93#ibcon#*after write, iclass 40, count 0 2006.161.08:25:50.93#ibcon#*before return 0, iclass 40, count 0 2006.161.08:25:50.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:25:50.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.161.08:25:50.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:25:50.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:25:50.93$vc4f8/va=5,7 2006.161.08:25:50.93#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.161.08:25:50.93#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.161.08:25:50.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:50.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:25:50.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:25:50.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:25:50.99#ibcon#enter wrdev, iclass 4, count 2 2006.161.08:25:50.99#ibcon#first serial, iclass 4, count 2 2006.161.08:25:50.99#ibcon#enter sib2, iclass 4, count 2 2006.161.08:25:50.99#ibcon#flushed, iclass 4, count 2 2006.161.08:25:50.99#ibcon#about to write, iclass 4, count 2 2006.161.08:25:50.99#ibcon#wrote, iclass 4, count 2 2006.161.08:25:50.99#ibcon#about to read 3, iclass 4, count 2 2006.161.08:25:51.01#ibcon#read 3, iclass 4, count 2 2006.161.08:25:51.01#ibcon#about to read 4, iclass 4, count 2 2006.161.08:25:51.01#ibcon#read 4, iclass 4, count 2 2006.161.08:25:51.01#ibcon#about to read 5, iclass 4, count 2 2006.161.08:25:51.01#ibcon#read 5, iclass 4, count 2 2006.161.08:25:51.01#ibcon#about to read 6, iclass 4, count 2 2006.161.08:25:51.01#ibcon#read 6, iclass 4, count 2 2006.161.08:25:51.01#ibcon#end of sib2, iclass 4, count 2 2006.161.08:25:51.01#ibcon#*mode == 0, iclass 4, count 2 2006.161.08:25:51.01#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.161.08:25:51.01#ibcon#[25=AT05-07\r\n] 2006.161.08:25:51.01#ibcon#*before write, iclass 4, count 2 2006.161.08:25:51.01#ibcon#enter sib2, iclass 4, count 2 2006.161.08:25:51.01#ibcon#flushed, iclass 4, count 2 2006.161.08:25:51.01#ibcon#about to write, iclass 4, count 2 2006.161.08:25:51.01#ibcon#wrote, iclass 4, count 2 2006.161.08:25:51.01#ibcon#about to read 3, iclass 4, count 2 2006.161.08:25:51.04#ibcon#read 3, iclass 4, count 2 2006.161.08:25:51.04#ibcon#about to read 4, iclass 4, count 2 2006.161.08:25:51.04#ibcon#read 4, iclass 4, count 2 2006.161.08:25:51.04#ibcon#about to read 5, iclass 4, count 2 2006.161.08:25:51.04#ibcon#read 5, iclass 4, count 2 2006.161.08:25:51.04#ibcon#about to read 6, iclass 4, count 2 2006.161.08:25:51.04#ibcon#read 6, iclass 4, count 2 2006.161.08:25:51.04#ibcon#end of sib2, iclass 4, count 2 2006.161.08:25:51.04#ibcon#*after write, iclass 4, count 2 2006.161.08:25:51.04#ibcon#*before return 0, iclass 4, count 2 2006.161.08:25:51.04#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:25:51.04#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.161.08:25:51.04#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.161.08:25:51.04#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:51.04#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:25:51.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:25:51.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:25:51.16#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:25:51.16#ibcon#first serial, iclass 4, count 0 2006.161.08:25:51.16#ibcon#enter sib2, iclass 4, count 0 2006.161.08:25:51.16#ibcon#flushed, iclass 4, count 0 2006.161.08:25:51.16#ibcon#about to write, iclass 4, count 0 2006.161.08:25:51.16#ibcon#wrote, iclass 4, count 0 2006.161.08:25:51.16#ibcon#about to read 3, iclass 4, count 0 2006.161.08:25:51.18#ibcon#read 3, iclass 4, count 0 2006.161.08:25:51.18#ibcon#about to read 4, iclass 4, count 0 2006.161.08:25:51.18#ibcon#read 4, iclass 4, count 0 2006.161.08:25:51.18#ibcon#about to read 5, iclass 4, count 0 2006.161.08:25:51.18#ibcon#read 5, iclass 4, count 0 2006.161.08:25:51.18#ibcon#about to read 6, iclass 4, count 0 2006.161.08:25:51.18#ibcon#read 6, iclass 4, count 0 2006.161.08:25:51.18#ibcon#end of sib2, iclass 4, count 0 2006.161.08:25:51.18#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:25:51.18#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:25:51.18#ibcon#[25=USB\r\n] 2006.161.08:25:51.18#ibcon#*before write, iclass 4, count 0 2006.161.08:25:51.18#ibcon#enter sib2, iclass 4, count 0 2006.161.08:25:51.18#ibcon#flushed, iclass 4, count 0 2006.161.08:25:51.18#ibcon#about to write, iclass 4, count 0 2006.161.08:25:51.18#ibcon#wrote, iclass 4, count 0 2006.161.08:25:51.18#ibcon#about to read 3, iclass 4, count 0 2006.161.08:25:51.21#ibcon#read 3, iclass 4, count 0 2006.161.08:25:51.21#ibcon#about to read 4, iclass 4, count 0 2006.161.08:25:51.21#ibcon#read 4, iclass 4, count 0 2006.161.08:25:51.21#ibcon#about to read 5, iclass 4, count 0 2006.161.08:25:51.21#ibcon#read 5, iclass 4, count 0 2006.161.08:25:51.21#ibcon#about to read 6, iclass 4, count 0 2006.161.08:25:51.21#ibcon#read 6, iclass 4, count 0 2006.161.08:25:51.21#ibcon#end of sib2, iclass 4, count 0 2006.161.08:25:51.21#ibcon#*after write, iclass 4, count 0 2006.161.08:25:51.21#ibcon#*before return 0, iclass 4, count 0 2006.161.08:25:51.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:25:51.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.161.08:25:51.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:25:51.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:25:51.21$vc4f8/valo=6,772.99 2006.161.08:25:51.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:25:51.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:25:51.21#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:51.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:51.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:51.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:51.21#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:25:51.21#ibcon#first serial, iclass 6, count 0 2006.161.08:25:51.21#ibcon#enter sib2, iclass 6, count 0 2006.161.08:25:51.21#ibcon#flushed, iclass 6, count 0 2006.161.08:25:51.21#ibcon#about to write, iclass 6, count 0 2006.161.08:25:51.21#ibcon#wrote, iclass 6, count 0 2006.161.08:25:51.21#ibcon#about to read 3, iclass 6, count 0 2006.161.08:25:51.23#ibcon#read 3, iclass 6, count 0 2006.161.08:25:51.23#ibcon#about to read 4, iclass 6, count 0 2006.161.08:25:51.23#ibcon#read 4, iclass 6, count 0 2006.161.08:25:51.23#ibcon#about to read 5, iclass 6, count 0 2006.161.08:25:51.23#ibcon#read 5, iclass 6, count 0 2006.161.08:25:51.23#ibcon#about to read 6, iclass 6, count 0 2006.161.08:25:51.23#ibcon#read 6, iclass 6, count 0 2006.161.08:25:51.23#ibcon#end of sib2, iclass 6, count 0 2006.161.08:25:51.23#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:25:51.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:25:51.23#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:25:51.23#ibcon#*before write, iclass 6, count 0 2006.161.08:25:51.23#ibcon#enter sib2, iclass 6, count 0 2006.161.08:25:51.23#ibcon#flushed, iclass 6, count 0 2006.161.08:25:51.23#ibcon#about to write, iclass 6, count 0 2006.161.08:25:51.23#ibcon#wrote, iclass 6, count 0 2006.161.08:25:51.23#ibcon#about to read 3, iclass 6, count 0 2006.161.08:25:51.27#ibcon#read 3, iclass 6, count 0 2006.161.08:25:51.27#ibcon#about to read 4, iclass 6, count 0 2006.161.08:25:51.27#ibcon#read 4, iclass 6, count 0 2006.161.08:25:51.27#ibcon#about to read 5, iclass 6, count 0 2006.161.08:25:51.27#ibcon#read 5, iclass 6, count 0 2006.161.08:25:51.27#ibcon#about to read 6, iclass 6, count 0 2006.161.08:25:51.27#ibcon#read 6, iclass 6, count 0 2006.161.08:25:51.27#ibcon#end of sib2, iclass 6, count 0 2006.161.08:25:51.27#ibcon#*after write, iclass 6, count 0 2006.161.08:25:51.27#ibcon#*before return 0, iclass 6, count 0 2006.161.08:25:51.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:51.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:51.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:25:51.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:25:51.27$vc4f8/va=6,6 2006.161.08:25:51.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.08:25:51.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.08:25:51.27#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:51.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:51.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:51.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:51.33#ibcon#enter wrdev, iclass 10, count 2 2006.161.08:25:51.33#ibcon#first serial, iclass 10, count 2 2006.161.08:25:51.33#ibcon#enter sib2, iclass 10, count 2 2006.161.08:25:51.33#ibcon#flushed, iclass 10, count 2 2006.161.08:25:51.33#ibcon#about to write, iclass 10, count 2 2006.161.08:25:51.33#ibcon#wrote, iclass 10, count 2 2006.161.08:25:51.33#ibcon#about to read 3, iclass 10, count 2 2006.161.08:25:51.35#ibcon#read 3, iclass 10, count 2 2006.161.08:25:51.35#ibcon#about to read 4, iclass 10, count 2 2006.161.08:25:51.35#ibcon#read 4, iclass 10, count 2 2006.161.08:25:51.35#ibcon#about to read 5, iclass 10, count 2 2006.161.08:25:51.35#ibcon#read 5, iclass 10, count 2 2006.161.08:25:51.35#ibcon#about to read 6, iclass 10, count 2 2006.161.08:25:51.35#ibcon#read 6, iclass 10, count 2 2006.161.08:25:51.35#ibcon#end of sib2, iclass 10, count 2 2006.161.08:25:51.35#ibcon#*mode == 0, iclass 10, count 2 2006.161.08:25:51.35#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.08:25:51.35#ibcon#[25=AT06-06\r\n] 2006.161.08:25:51.35#ibcon#*before write, iclass 10, count 2 2006.161.08:25:51.35#ibcon#enter sib2, iclass 10, count 2 2006.161.08:25:51.35#ibcon#flushed, iclass 10, count 2 2006.161.08:25:51.35#ibcon#about to write, iclass 10, count 2 2006.161.08:25:51.35#ibcon#wrote, iclass 10, count 2 2006.161.08:25:51.35#ibcon#about to read 3, iclass 10, count 2 2006.161.08:25:51.38#ibcon#read 3, iclass 10, count 2 2006.161.08:25:51.38#ibcon#about to read 4, iclass 10, count 2 2006.161.08:25:51.38#ibcon#read 4, iclass 10, count 2 2006.161.08:25:51.38#ibcon#about to read 5, iclass 10, count 2 2006.161.08:25:51.38#ibcon#read 5, iclass 10, count 2 2006.161.08:25:51.38#ibcon#about to read 6, iclass 10, count 2 2006.161.08:25:51.38#ibcon#read 6, iclass 10, count 2 2006.161.08:25:51.38#ibcon#end of sib2, iclass 10, count 2 2006.161.08:25:51.38#ibcon#*after write, iclass 10, count 2 2006.161.08:25:51.38#ibcon#*before return 0, iclass 10, count 2 2006.161.08:25:51.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:51.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:51.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.08:25:51.38#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:51.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:51.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:51.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:51.50#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:25:51.50#ibcon#first serial, iclass 10, count 0 2006.161.08:25:51.50#ibcon#enter sib2, iclass 10, count 0 2006.161.08:25:51.50#ibcon#flushed, iclass 10, count 0 2006.161.08:25:51.50#ibcon#about to write, iclass 10, count 0 2006.161.08:25:51.50#ibcon#wrote, iclass 10, count 0 2006.161.08:25:51.50#ibcon#about to read 3, iclass 10, count 0 2006.161.08:25:51.52#ibcon#read 3, iclass 10, count 0 2006.161.08:25:51.52#ibcon#about to read 4, iclass 10, count 0 2006.161.08:25:51.52#ibcon#read 4, iclass 10, count 0 2006.161.08:25:51.52#ibcon#about to read 5, iclass 10, count 0 2006.161.08:25:51.52#ibcon#read 5, iclass 10, count 0 2006.161.08:25:51.52#ibcon#about to read 6, iclass 10, count 0 2006.161.08:25:51.52#ibcon#read 6, iclass 10, count 0 2006.161.08:25:51.52#ibcon#end of sib2, iclass 10, count 0 2006.161.08:25:51.52#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:25:51.52#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:25:51.52#ibcon#[25=USB\r\n] 2006.161.08:25:51.52#ibcon#*before write, iclass 10, count 0 2006.161.08:25:51.52#ibcon#enter sib2, iclass 10, count 0 2006.161.08:25:51.52#ibcon#flushed, iclass 10, count 0 2006.161.08:25:51.52#ibcon#about to write, iclass 10, count 0 2006.161.08:25:51.52#ibcon#wrote, iclass 10, count 0 2006.161.08:25:51.52#ibcon#about to read 3, iclass 10, count 0 2006.161.08:25:51.55#ibcon#read 3, iclass 10, count 0 2006.161.08:25:51.55#ibcon#about to read 4, iclass 10, count 0 2006.161.08:25:51.55#ibcon#read 4, iclass 10, count 0 2006.161.08:25:51.55#ibcon#about to read 5, iclass 10, count 0 2006.161.08:25:51.55#ibcon#read 5, iclass 10, count 0 2006.161.08:25:51.55#ibcon#about to read 6, iclass 10, count 0 2006.161.08:25:51.55#ibcon#read 6, iclass 10, count 0 2006.161.08:25:51.55#ibcon#end of sib2, iclass 10, count 0 2006.161.08:25:51.55#ibcon#*after write, iclass 10, count 0 2006.161.08:25:51.55#ibcon#*before return 0, iclass 10, count 0 2006.161.08:25:51.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:51.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:51.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:25:51.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:25:51.55$vc4f8/valo=7,832.99 2006.161.08:25:51.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:25:51.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:25:51.55#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:51.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:51.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:51.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:51.55#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:25:51.55#ibcon#first serial, iclass 12, count 0 2006.161.08:25:51.55#ibcon#enter sib2, iclass 12, count 0 2006.161.08:25:51.55#ibcon#flushed, iclass 12, count 0 2006.161.08:25:51.55#ibcon#about to write, iclass 12, count 0 2006.161.08:25:51.55#ibcon#wrote, iclass 12, count 0 2006.161.08:25:51.55#ibcon#about to read 3, iclass 12, count 0 2006.161.08:25:51.57#ibcon#read 3, iclass 12, count 0 2006.161.08:25:51.57#ibcon#about to read 4, iclass 12, count 0 2006.161.08:25:51.57#ibcon#read 4, iclass 12, count 0 2006.161.08:25:51.57#ibcon#about to read 5, iclass 12, count 0 2006.161.08:25:51.57#ibcon#read 5, iclass 12, count 0 2006.161.08:25:51.57#ibcon#about to read 6, iclass 12, count 0 2006.161.08:25:51.57#ibcon#read 6, iclass 12, count 0 2006.161.08:25:51.57#ibcon#end of sib2, iclass 12, count 0 2006.161.08:25:51.57#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:25:51.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:25:51.57#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:25:51.57#ibcon#*before write, iclass 12, count 0 2006.161.08:25:51.57#ibcon#enter sib2, iclass 12, count 0 2006.161.08:25:51.57#ibcon#flushed, iclass 12, count 0 2006.161.08:25:51.57#ibcon#about to write, iclass 12, count 0 2006.161.08:25:51.57#ibcon#wrote, iclass 12, count 0 2006.161.08:25:51.57#ibcon#about to read 3, iclass 12, count 0 2006.161.08:25:51.61#ibcon#read 3, iclass 12, count 0 2006.161.08:25:51.61#ibcon#about to read 4, iclass 12, count 0 2006.161.08:25:51.61#ibcon#read 4, iclass 12, count 0 2006.161.08:25:51.61#ibcon#about to read 5, iclass 12, count 0 2006.161.08:25:51.61#ibcon#read 5, iclass 12, count 0 2006.161.08:25:51.61#ibcon#about to read 6, iclass 12, count 0 2006.161.08:25:51.61#ibcon#read 6, iclass 12, count 0 2006.161.08:25:51.61#ibcon#end of sib2, iclass 12, count 0 2006.161.08:25:51.61#ibcon#*after write, iclass 12, count 0 2006.161.08:25:51.61#ibcon#*before return 0, iclass 12, count 0 2006.161.08:25:51.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:51.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:51.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:25:51.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:25:51.61$vc4f8/va=7,6 2006.161.08:25:51.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.161.08:25:51.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.161.08:25:51.61#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:51.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:51.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:51.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:51.67#ibcon#enter wrdev, iclass 14, count 2 2006.161.08:25:51.67#ibcon#first serial, iclass 14, count 2 2006.161.08:25:51.67#ibcon#enter sib2, iclass 14, count 2 2006.161.08:25:51.67#ibcon#flushed, iclass 14, count 2 2006.161.08:25:51.67#ibcon#about to write, iclass 14, count 2 2006.161.08:25:51.67#ibcon#wrote, iclass 14, count 2 2006.161.08:25:51.67#ibcon#about to read 3, iclass 14, count 2 2006.161.08:25:51.69#ibcon#read 3, iclass 14, count 2 2006.161.08:25:51.69#ibcon#about to read 4, iclass 14, count 2 2006.161.08:25:51.69#ibcon#read 4, iclass 14, count 2 2006.161.08:25:51.69#ibcon#about to read 5, iclass 14, count 2 2006.161.08:25:51.69#ibcon#read 5, iclass 14, count 2 2006.161.08:25:51.69#ibcon#about to read 6, iclass 14, count 2 2006.161.08:25:51.69#ibcon#read 6, iclass 14, count 2 2006.161.08:25:51.69#ibcon#end of sib2, iclass 14, count 2 2006.161.08:25:51.69#ibcon#*mode == 0, iclass 14, count 2 2006.161.08:25:51.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.161.08:25:51.69#ibcon#[25=AT07-06\r\n] 2006.161.08:25:51.69#ibcon#*before write, iclass 14, count 2 2006.161.08:25:51.69#ibcon#enter sib2, iclass 14, count 2 2006.161.08:25:51.69#ibcon#flushed, iclass 14, count 2 2006.161.08:25:51.69#ibcon#about to write, iclass 14, count 2 2006.161.08:25:51.69#ibcon#wrote, iclass 14, count 2 2006.161.08:25:51.69#ibcon#about to read 3, iclass 14, count 2 2006.161.08:25:51.72#ibcon#read 3, iclass 14, count 2 2006.161.08:25:51.72#ibcon#about to read 4, iclass 14, count 2 2006.161.08:25:51.72#ibcon#read 4, iclass 14, count 2 2006.161.08:25:51.72#ibcon#about to read 5, iclass 14, count 2 2006.161.08:25:51.72#ibcon#read 5, iclass 14, count 2 2006.161.08:25:51.72#ibcon#about to read 6, iclass 14, count 2 2006.161.08:25:51.72#ibcon#read 6, iclass 14, count 2 2006.161.08:25:51.72#ibcon#end of sib2, iclass 14, count 2 2006.161.08:25:51.72#ibcon#*after write, iclass 14, count 2 2006.161.08:25:51.72#ibcon#*before return 0, iclass 14, count 2 2006.161.08:25:51.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:51.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:51.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.161.08:25:51.72#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:51.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:25:51.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:25:51.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:25:51.84#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:25:51.84#ibcon#first serial, iclass 14, count 0 2006.161.08:25:51.84#ibcon#enter sib2, iclass 14, count 0 2006.161.08:25:51.84#ibcon#flushed, iclass 14, count 0 2006.161.08:25:51.84#ibcon#about to write, iclass 14, count 0 2006.161.08:25:51.84#ibcon#wrote, iclass 14, count 0 2006.161.08:25:51.84#ibcon#about to read 3, iclass 14, count 0 2006.161.08:25:51.86#ibcon#read 3, iclass 14, count 0 2006.161.08:25:51.86#ibcon#about to read 4, iclass 14, count 0 2006.161.08:25:51.86#ibcon#read 4, iclass 14, count 0 2006.161.08:25:51.86#ibcon#about to read 5, iclass 14, count 0 2006.161.08:25:51.86#ibcon#read 5, iclass 14, count 0 2006.161.08:25:51.86#ibcon#about to read 6, iclass 14, count 0 2006.161.08:25:51.86#ibcon#read 6, iclass 14, count 0 2006.161.08:25:51.86#ibcon#end of sib2, iclass 14, count 0 2006.161.08:25:51.86#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:25:51.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:25:51.86#ibcon#[25=USB\r\n] 2006.161.08:25:51.86#ibcon#*before write, iclass 14, count 0 2006.161.08:25:51.86#ibcon#enter sib2, iclass 14, count 0 2006.161.08:25:51.86#ibcon#flushed, iclass 14, count 0 2006.161.08:25:51.86#ibcon#about to write, iclass 14, count 0 2006.161.08:25:51.86#ibcon#wrote, iclass 14, count 0 2006.161.08:25:51.86#ibcon#about to read 3, iclass 14, count 0 2006.161.08:25:51.89#ibcon#read 3, iclass 14, count 0 2006.161.08:25:51.89#ibcon#about to read 4, iclass 14, count 0 2006.161.08:25:51.89#ibcon#read 4, iclass 14, count 0 2006.161.08:25:51.89#ibcon#about to read 5, iclass 14, count 0 2006.161.08:25:51.89#ibcon#read 5, iclass 14, count 0 2006.161.08:25:51.89#ibcon#about to read 6, iclass 14, count 0 2006.161.08:25:51.89#ibcon#read 6, iclass 14, count 0 2006.161.08:25:51.89#ibcon#end of sib2, iclass 14, count 0 2006.161.08:25:51.89#ibcon#*after write, iclass 14, count 0 2006.161.08:25:51.89#ibcon#*before return 0, iclass 14, count 0 2006.161.08:25:51.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:25:51.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.161.08:25:51.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:25:51.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:25:51.89$vc4f8/valo=8,852.99 2006.161.08:25:51.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.161.08:25:51.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.161.08:25:51.89#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:51.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:25:51.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:25:51.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:25:51.89#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:25:51.89#ibcon#first serial, iclass 16, count 0 2006.161.08:25:51.89#ibcon#enter sib2, iclass 16, count 0 2006.161.08:25:51.89#ibcon#flushed, iclass 16, count 0 2006.161.08:25:51.89#ibcon#about to write, iclass 16, count 0 2006.161.08:25:51.89#ibcon#wrote, iclass 16, count 0 2006.161.08:25:51.89#ibcon#about to read 3, iclass 16, count 0 2006.161.08:25:51.92#ibcon#read 3, iclass 16, count 0 2006.161.08:25:51.92#ibcon#about to read 4, iclass 16, count 0 2006.161.08:25:51.92#ibcon#read 4, iclass 16, count 0 2006.161.08:25:51.92#ibcon#about to read 5, iclass 16, count 0 2006.161.08:25:51.92#ibcon#read 5, iclass 16, count 0 2006.161.08:25:51.92#ibcon#about to read 6, iclass 16, count 0 2006.161.08:25:51.92#ibcon#read 6, iclass 16, count 0 2006.161.08:25:51.92#ibcon#end of sib2, iclass 16, count 0 2006.161.08:25:51.92#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:25:51.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:25:51.92#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:25:51.92#ibcon#*before write, iclass 16, count 0 2006.161.08:25:51.92#ibcon#enter sib2, iclass 16, count 0 2006.161.08:25:51.92#ibcon#flushed, iclass 16, count 0 2006.161.08:25:51.92#ibcon#about to write, iclass 16, count 0 2006.161.08:25:51.92#ibcon#wrote, iclass 16, count 0 2006.161.08:25:51.92#ibcon#about to read 3, iclass 16, count 0 2006.161.08:25:51.96#ibcon#read 3, iclass 16, count 0 2006.161.08:25:51.96#ibcon#about to read 4, iclass 16, count 0 2006.161.08:25:51.96#ibcon#read 4, iclass 16, count 0 2006.161.08:25:51.96#ibcon#about to read 5, iclass 16, count 0 2006.161.08:25:51.96#ibcon#read 5, iclass 16, count 0 2006.161.08:25:51.96#ibcon#about to read 6, iclass 16, count 0 2006.161.08:25:51.96#ibcon#read 6, iclass 16, count 0 2006.161.08:25:51.96#ibcon#end of sib2, iclass 16, count 0 2006.161.08:25:51.96#ibcon#*after write, iclass 16, count 0 2006.161.08:25:51.96#ibcon#*before return 0, iclass 16, count 0 2006.161.08:25:51.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:25:51.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.161.08:25:51.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:25:51.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:25:51.96$vc4f8/va=8,7 2006.161.08:25:51.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.161.08:25:51.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.161.08:25:51.96#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:51.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:25:52.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:25:52.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:25:52.01#ibcon#enter wrdev, iclass 18, count 2 2006.161.08:25:52.01#ibcon#first serial, iclass 18, count 2 2006.161.08:25:52.01#ibcon#enter sib2, iclass 18, count 2 2006.161.08:25:52.01#ibcon#flushed, iclass 18, count 2 2006.161.08:25:52.01#ibcon#about to write, iclass 18, count 2 2006.161.08:25:52.01#ibcon#wrote, iclass 18, count 2 2006.161.08:25:52.01#ibcon#about to read 3, iclass 18, count 2 2006.161.08:25:52.03#ibcon#read 3, iclass 18, count 2 2006.161.08:25:52.03#ibcon#about to read 4, iclass 18, count 2 2006.161.08:25:52.03#ibcon#read 4, iclass 18, count 2 2006.161.08:25:52.03#ibcon#about to read 5, iclass 18, count 2 2006.161.08:25:52.03#ibcon#read 5, iclass 18, count 2 2006.161.08:25:52.03#ibcon#about to read 6, iclass 18, count 2 2006.161.08:25:52.03#ibcon#read 6, iclass 18, count 2 2006.161.08:25:52.03#ibcon#end of sib2, iclass 18, count 2 2006.161.08:25:52.03#ibcon#*mode == 0, iclass 18, count 2 2006.161.08:25:52.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.161.08:25:52.03#ibcon#[25=AT08-07\r\n] 2006.161.08:25:52.03#ibcon#*before write, iclass 18, count 2 2006.161.08:25:52.03#ibcon#enter sib2, iclass 18, count 2 2006.161.08:25:52.03#ibcon#flushed, iclass 18, count 2 2006.161.08:25:52.03#ibcon#about to write, iclass 18, count 2 2006.161.08:25:52.03#ibcon#wrote, iclass 18, count 2 2006.161.08:25:52.03#ibcon#about to read 3, iclass 18, count 2 2006.161.08:25:52.06#ibcon#read 3, iclass 18, count 2 2006.161.08:25:52.06#ibcon#about to read 4, iclass 18, count 2 2006.161.08:25:52.06#ibcon#read 4, iclass 18, count 2 2006.161.08:25:52.06#ibcon#about to read 5, iclass 18, count 2 2006.161.08:25:52.06#ibcon#read 5, iclass 18, count 2 2006.161.08:25:52.06#ibcon#about to read 6, iclass 18, count 2 2006.161.08:25:52.06#ibcon#read 6, iclass 18, count 2 2006.161.08:25:52.06#ibcon#end of sib2, iclass 18, count 2 2006.161.08:25:52.06#ibcon#*after write, iclass 18, count 2 2006.161.08:25:52.06#ibcon#*before return 0, iclass 18, count 2 2006.161.08:25:52.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:25:52.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.161.08:25:52.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.161.08:25:52.06#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:52.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:25:52.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:25:52.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:25:52.18#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:25:52.18#ibcon#first serial, iclass 18, count 0 2006.161.08:25:52.18#ibcon#enter sib2, iclass 18, count 0 2006.161.08:25:52.18#ibcon#flushed, iclass 18, count 0 2006.161.08:25:52.18#ibcon#about to write, iclass 18, count 0 2006.161.08:25:52.18#ibcon#wrote, iclass 18, count 0 2006.161.08:25:52.18#ibcon#about to read 3, iclass 18, count 0 2006.161.08:25:52.20#ibcon#read 3, iclass 18, count 0 2006.161.08:25:52.20#ibcon#about to read 4, iclass 18, count 0 2006.161.08:25:52.20#ibcon#read 4, iclass 18, count 0 2006.161.08:25:52.20#ibcon#about to read 5, iclass 18, count 0 2006.161.08:25:52.20#ibcon#read 5, iclass 18, count 0 2006.161.08:25:52.20#ibcon#about to read 6, iclass 18, count 0 2006.161.08:25:52.20#ibcon#read 6, iclass 18, count 0 2006.161.08:25:52.20#ibcon#end of sib2, iclass 18, count 0 2006.161.08:25:52.20#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:25:52.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:25:52.20#ibcon#[25=USB\r\n] 2006.161.08:25:52.20#ibcon#*before write, iclass 18, count 0 2006.161.08:25:52.20#ibcon#enter sib2, iclass 18, count 0 2006.161.08:25:52.20#ibcon#flushed, iclass 18, count 0 2006.161.08:25:52.20#ibcon#about to write, iclass 18, count 0 2006.161.08:25:52.20#ibcon#wrote, iclass 18, count 0 2006.161.08:25:52.20#ibcon#about to read 3, iclass 18, count 0 2006.161.08:25:52.23#ibcon#read 3, iclass 18, count 0 2006.161.08:25:52.23#ibcon#about to read 4, iclass 18, count 0 2006.161.08:25:52.23#ibcon#read 4, iclass 18, count 0 2006.161.08:25:52.23#ibcon#about to read 5, iclass 18, count 0 2006.161.08:25:52.23#ibcon#read 5, iclass 18, count 0 2006.161.08:25:52.23#ibcon#about to read 6, iclass 18, count 0 2006.161.08:25:52.23#ibcon#read 6, iclass 18, count 0 2006.161.08:25:52.23#ibcon#end of sib2, iclass 18, count 0 2006.161.08:25:52.23#ibcon#*after write, iclass 18, count 0 2006.161.08:25:52.23#ibcon#*before return 0, iclass 18, count 0 2006.161.08:25:52.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:25:52.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.161.08:25:52.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:25:52.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:25:52.23$vc4f8/vblo=1,632.99 2006.161.08:25:52.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.161.08:25:52.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.161.08:25:52.23#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:52.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:25:52.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:25:52.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:25:52.23#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:25:52.23#ibcon#first serial, iclass 20, count 0 2006.161.08:25:52.23#ibcon#enter sib2, iclass 20, count 0 2006.161.08:25:52.23#ibcon#flushed, iclass 20, count 0 2006.161.08:25:52.23#ibcon#about to write, iclass 20, count 0 2006.161.08:25:52.23#ibcon#wrote, iclass 20, count 0 2006.161.08:25:52.23#ibcon#about to read 3, iclass 20, count 0 2006.161.08:25:52.25#ibcon#read 3, iclass 20, count 0 2006.161.08:25:52.25#ibcon#about to read 4, iclass 20, count 0 2006.161.08:25:52.25#ibcon#read 4, iclass 20, count 0 2006.161.08:25:52.25#ibcon#about to read 5, iclass 20, count 0 2006.161.08:25:52.25#ibcon#read 5, iclass 20, count 0 2006.161.08:25:52.25#ibcon#about to read 6, iclass 20, count 0 2006.161.08:25:52.25#ibcon#read 6, iclass 20, count 0 2006.161.08:25:52.25#ibcon#end of sib2, iclass 20, count 0 2006.161.08:25:52.25#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:25:52.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:25:52.25#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:25:52.25#ibcon#*before write, iclass 20, count 0 2006.161.08:25:52.25#ibcon#enter sib2, iclass 20, count 0 2006.161.08:25:52.25#ibcon#flushed, iclass 20, count 0 2006.161.08:25:52.25#ibcon#about to write, iclass 20, count 0 2006.161.08:25:52.25#ibcon#wrote, iclass 20, count 0 2006.161.08:25:52.25#ibcon#about to read 3, iclass 20, count 0 2006.161.08:25:52.29#ibcon#read 3, iclass 20, count 0 2006.161.08:25:52.29#ibcon#about to read 4, iclass 20, count 0 2006.161.08:25:52.29#ibcon#read 4, iclass 20, count 0 2006.161.08:25:52.29#ibcon#about to read 5, iclass 20, count 0 2006.161.08:25:52.29#ibcon#read 5, iclass 20, count 0 2006.161.08:25:52.29#ibcon#about to read 6, iclass 20, count 0 2006.161.08:25:52.29#ibcon#read 6, iclass 20, count 0 2006.161.08:25:52.29#ibcon#end of sib2, iclass 20, count 0 2006.161.08:25:52.29#ibcon#*after write, iclass 20, count 0 2006.161.08:25:52.29#ibcon#*before return 0, iclass 20, count 0 2006.161.08:25:52.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:25:52.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.161.08:25:52.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:25:52.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:25:52.29$vc4f8/vb=1,4 2006.161.08:25:52.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.161.08:25:52.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.161.08:25:52.29#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:52.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:25:52.29#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:25:52.29#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:25:52.29#ibcon#enter wrdev, iclass 22, count 2 2006.161.08:25:52.29#ibcon#first serial, iclass 22, count 2 2006.161.08:25:52.29#ibcon#enter sib2, iclass 22, count 2 2006.161.08:25:52.29#ibcon#flushed, iclass 22, count 2 2006.161.08:25:52.29#ibcon#about to write, iclass 22, count 2 2006.161.08:25:52.29#ibcon#wrote, iclass 22, count 2 2006.161.08:25:52.29#ibcon#about to read 3, iclass 22, count 2 2006.161.08:25:52.31#ibcon#read 3, iclass 22, count 2 2006.161.08:25:52.31#ibcon#about to read 4, iclass 22, count 2 2006.161.08:25:52.31#ibcon#read 4, iclass 22, count 2 2006.161.08:25:52.31#ibcon#about to read 5, iclass 22, count 2 2006.161.08:25:52.31#ibcon#read 5, iclass 22, count 2 2006.161.08:25:52.31#ibcon#about to read 6, iclass 22, count 2 2006.161.08:25:52.31#ibcon#read 6, iclass 22, count 2 2006.161.08:25:52.31#ibcon#end of sib2, iclass 22, count 2 2006.161.08:25:52.31#ibcon#*mode == 0, iclass 22, count 2 2006.161.08:25:52.31#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.161.08:25:52.31#ibcon#[27=AT01-04\r\n] 2006.161.08:25:52.31#ibcon#*before write, iclass 22, count 2 2006.161.08:25:52.31#ibcon#enter sib2, iclass 22, count 2 2006.161.08:25:52.31#ibcon#flushed, iclass 22, count 2 2006.161.08:25:52.31#ibcon#about to write, iclass 22, count 2 2006.161.08:25:52.31#ibcon#wrote, iclass 22, count 2 2006.161.08:25:52.31#ibcon#about to read 3, iclass 22, count 2 2006.161.08:25:52.34#ibcon#read 3, iclass 22, count 2 2006.161.08:25:52.34#ibcon#about to read 4, iclass 22, count 2 2006.161.08:25:52.34#ibcon#read 4, iclass 22, count 2 2006.161.08:25:52.34#ibcon#about to read 5, iclass 22, count 2 2006.161.08:25:52.34#ibcon#read 5, iclass 22, count 2 2006.161.08:25:52.34#ibcon#about to read 6, iclass 22, count 2 2006.161.08:25:52.34#ibcon#read 6, iclass 22, count 2 2006.161.08:25:52.34#ibcon#end of sib2, iclass 22, count 2 2006.161.08:25:52.34#ibcon#*after write, iclass 22, count 2 2006.161.08:25:52.34#ibcon#*before return 0, iclass 22, count 2 2006.161.08:25:52.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:25:52.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.161.08:25:52.34#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.161.08:25:52.34#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:52.34#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:25:52.46#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:25:52.46#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:25:52.46#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:25:52.46#ibcon#first serial, iclass 22, count 0 2006.161.08:25:52.46#ibcon#enter sib2, iclass 22, count 0 2006.161.08:25:52.46#ibcon#flushed, iclass 22, count 0 2006.161.08:25:52.46#ibcon#about to write, iclass 22, count 0 2006.161.08:25:52.46#ibcon#wrote, iclass 22, count 0 2006.161.08:25:52.46#ibcon#about to read 3, iclass 22, count 0 2006.161.08:25:52.48#ibcon#read 3, iclass 22, count 0 2006.161.08:25:52.48#ibcon#about to read 4, iclass 22, count 0 2006.161.08:25:52.48#ibcon#read 4, iclass 22, count 0 2006.161.08:25:52.48#ibcon#about to read 5, iclass 22, count 0 2006.161.08:25:52.48#ibcon#read 5, iclass 22, count 0 2006.161.08:25:52.48#ibcon#about to read 6, iclass 22, count 0 2006.161.08:25:52.48#ibcon#read 6, iclass 22, count 0 2006.161.08:25:52.48#ibcon#end of sib2, iclass 22, count 0 2006.161.08:25:52.48#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:25:52.48#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:25:52.48#ibcon#[27=USB\r\n] 2006.161.08:25:52.48#ibcon#*before write, iclass 22, count 0 2006.161.08:25:52.48#ibcon#enter sib2, iclass 22, count 0 2006.161.08:25:52.48#ibcon#flushed, iclass 22, count 0 2006.161.08:25:52.48#ibcon#about to write, iclass 22, count 0 2006.161.08:25:52.48#ibcon#wrote, iclass 22, count 0 2006.161.08:25:52.48#ibcon#about to read 3, iclass 22, count 0 2006.161.08:25:52.51#ibcon#read 3, iclass 22, count 0 2006.161.08:25:52.51#ibcon#about to read 4, iclass 22, count 0 2006.161.08:25:52.51#ibcon#read 4, iclass 22, count 0 2006.161.08:25:52.51#ibcon#about to read 5, iclass 22, count 0 2006.161.08:25:52.51#ibcon#read 5, iclass 22, count 0 2006.161.08:25:52.51#ibcon#about to read 6, iclass 22, count 0 2006.161.08:25:52.51#ibcon#read 6, iclass 22, count 0 2006.161.08:25:52.51#ibcon#end of sib2, iclass 22, count 0 2006.161.08:25:52.51#ibcon#*after write, iclass 22, count 0 2006.161.08:25:52.51#ibcon#*before return 0, iclass 22, count 0 2006.161.08:25:52.51#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:25:52.51#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.161.08:25:52.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:25:52.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:25:52.51$vc4f8/vblo=2,640.99 2006.161.08:25:52.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.161.08:25:52.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.161.08:25:52.51#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:52.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:52.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:52.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:52.51#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:25:52.51#ibcon#first serial, iclass 24, count 0 2006.161.08:25:52.51#ibcon#enter sib2, iclass 24, count 0 2006.161.08:25:52.51#ibcon#flushed, iclass 24, count 0 2006.161.08:25:52.51#ibcon#about to write, iclass 24, count 0 2006.161.08:25:52.51#ibcon#wrote, iclass 24, count 0 2006.161.08:25:52.51#ibcon#about to read 3, iclass 24, count 0 2006.161.08:25:52.53#ibcon#read 3, iclass 24, count 0 2006.161.08:25:52.53#ibcon#about to read 4, iclass 24, count 0 2006.161.08:25:52.53#ibcon#read 4, iclass 24, count 0 2006.161.08:25:52.53#ibcon#about to read 5, iclass 24, count 0 2006.161.08:25:52.53#ibcon#read 5, iclass 24, count 0 2006.161.08:25:52.53#ibcon#about to read 6, iclass 24, count 0 2006.161.08:25:52.53#ibcon#read 6, iclass 24, count 0 2006.161.08:25:52.53#ibcon#end of sib2, iclass 24, count 0 2006.161.08:25:52.53#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:25:52.53#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:25:52.53#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:25:52.53#ibcon#*before write, iclass 24, count 0 2006.161.08:25:52.53#ibcon#enter sib2, iclass 24, count 0 2006.161.08:25:52.53#ibcon#flushed, iclass 24, count 0 2006.161.08:25:52.53#ibcon#about to write, iclass 24, count 0 2006.161.08:25:52.53#ibcon#wrote, iclass 24, count 0 2006.161.08:25:52.53#ibcon#about to read 3, iclass 24, count 0 2006.161.08:25:52.57#ibcon#read 3, iclass 24, count 0 2006.161.08:25:52.57#ibcon#about to read 4, iclass 24, count 0 2006.161.08:25:52.57#ibcon#read 4, iclass 24, count 0 2006.161.08:25:52.57#ibcon#about to read 5, iclass 24, count 0 2006.161.08:25:52.57#ibcon#read 5, iclass 24, count 0 2006.161.08:25:52.57#ibcon#about to read 6, iclass 24, count 0 2006.161.08:25:52.57#ibcon#read 6, iclass 24, count 0 2006.161.08:25:52.57#ibcon#end of sib2, iclass 24, count 0 2006.161.08:25:52.57#ibcon#*after write, iclass 24, count 0 2006.161.08:25:52.57#ibcon#*before return 0, iclass 24, count 0 2006.161.08:25:52.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:52.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.161.08:25:52.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:25:52.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:25:52.57$vc4f8/vb=2,4 2006.161.08:25:52.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.161.08:25:52.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.161.08:25:52.57#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:52.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:52.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:52.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:52.63#ibcon#enter wrdev, iclass 26, count 2 2006.161.08:25:52.63#ibcon#first serial, iclass 26, count 2 2006.161.08:25:52.63#ibcon#enter sib2, iclass 26, count 2 2006.161.08:25:52.63#ibcon#flushed, iclass 26, count 2 2006.161.08:25:52.63#ibcon#about to write, iclass 26, count 2 2006.161.08:25:52.63#ibcon#wrote, iclass 26, count 2 2006.161.08:25:52.63#ibcon#about to read 3, iclass 26, count 2 2006.161.08:25:52.65#ibcon#read 3, iclass 26, count 2 2006.161.08:25:52.65#ibcon#about to read 4, iclass 26, count 2 2006.161.08:25:52.65#ibcon#read 4, iclass 26, count 2 2006.161.08:25:52.65#ibcon#about to read 5, iclass 26, count 2 2006.161.08:25:52.65#ibcon#read 5, iclass 26, count 2 2006.161.08:25:52.65#ibcon#about to read 6, iclass 26, count 2 2006.161.08:25:52.65#ibcon#read 6, iclass 26, count 2 2006.161.08:25:52.65#ibcon#end of sib2, iclass 26, count 2 2006.161.08:25:52.65#ibcon#*mode == 0, iclass 26, count 2 2006.161.08:25:52.65#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.161.08:25:52.65#ibcon#[27=AT02-04\r\n] 2006.161.08:25:52.65#ibcon#*before write, iclass 26, count 2 2006.161.08:25:52.65#ibcon#enter sib2, iclass 26, count 2 2006.161.08:25:52.65#ibcon#flushed, iclass 26, count 2 2006.161.08:25:52.65#ibcon#about to write, iclass 26, count 2 2006.161.08:25:52.65#ibcon#wrote, iclass 26, count 2 2006.161.08:25:52.65#ibcon#about to read 3, iclass 26, count 2 2006.161.08:25:52.68#ibcon#read 3, iclass 26, count 2 2006.161.08:25:52.68#ibcon#about to read 4, iclass 26, count 2 2006.161.08:25:52.68#ibcon#read 4, iclass 26, count 2 2006.161.08:25:52.68#ibcon#about to read 5, iclass 26, count 2 2006.161.08:25:52.68#ibcon#read 5, iclass 26, count 2 2006.161.08:25:52.68#ibcon#about to read 6, iclass 26, count 2 2006.161.08:25:52.68#ibcon#read 6, iclass 26, count 2 2006.161.08:25:52.68#ibcon#end of sib2, iclass 26, count 2 2006.161.08:25:52.68#ibcon#*after write, iclass 26, count 2 2006.161.08:25:52.68#ibcon#*before return 0, iclass 26, count 2 2006.161.08:25:52.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:52.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.161.08:25:52.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.161.08:25:52.68#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:52.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:52.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:52.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:52.80#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:25:52.80#ibcon#first serial, iclass 26, count 0 2006.161.08:25:52.80#ibcon#enter sib2, iclass 26, count 0 2006.161.08:25:52.80#ibcon#flushed, iclass 26, count 0 2006.161.08:25:52.80#ibcon#about to write, iclass 26, count 0 2006.161.08:25:52.80#ibcon#wrote, iclass 26, count 0 2006.161.08:25:52.80#ibcon#about to read 3, iclass 26, count 0 2006.161.08:25:52.82#ibcon#read 3, iclass 26, count 0 2006.161.08:25:52.82#ibcon#about to read 4, iclass 26, count 0 2006.161.08:25:52.82#ibcon#read 4, iclass 26, count 0 2006.161.08:25:52.82#ibcon#about to read 5, iclass 26, count 0 2006.161.08:25:52.82#ibcon#read 5, iclass 26, count 0 2006.161.08:25:52.82#ibcon#about to read 6, iclass 26, count 0 2006.161.08:25:52.82#ibcon#read 6, iclass 26, count 0 2006.161.08:25:52.82#ibcon#end of sib2, iclass 26, count 0 2006.161.08:25:52.82#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:25:52.82#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:25:52.82#ibcon#[27=USB\r\n] 2006.161.08:25:52.82#ibcon#*before write, iclass 26, count 0 2006.161.08:25:52.82#ibcon#enter sib2, iclass 26, count 0 2006.161.08:25:52.82#ibcon#flushed, iclass 26, count 0 2006.161.08:25:52.82#ibcon#about to write, iclass 26, count 0 2006.161.08:25:52.82#ibcon#wrote, iclass 26, count 0 2006.161.08:25:52.82#ibcon#about to read 3, iclass 26, count 0 2006.161.08:25:52.85#ibcon#read 3, iclass 26, count 0 2006.161.08:25:52.85#ibcon#about to read 4, iclass 26, count 0 2006.161.08:25:52.85#ibcon#read 4, iclass 26, count 0 2006.161.08:25:52.85#ibcon#about to read 5, iclass 26, count 0 2006.161.08:25:52.85#ibcon#read 5, iclass 26, count 0 2006.161.08:25:52.85#ibcon#about to read 6, iclass 26, count 0 2006.161.08:25:52.85#ibcon#read 6, iclass 26, count 0 2006.161.08:25:52.85#ibcon#end of sib2, iclass 26, count 0 2006.161.08:25:52.85#ibcon#*after write, iclass 26, count 0 2006.161.08:25:52.85#ibcon#*before return 0, iclass 26, count 0 2006.161.08:25:52.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:52.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.161.08:25:52.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:25:52.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:25:52.85$vc4f8/vblo=3,656.99 2006.161.08:25:52.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.161.08:25:52.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.161.08:25:52.85#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:52.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:52.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:52.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:52.85#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:25:52.85#ibcon#first serial, iclass 28, count 0 2006.161.08:25:52.85#ibcon#enter sib2, iclass 28, count 0 2006.161.08:25:52.85#ibcon#flushed, iclass 28, count 0 2006.161.08:25:52.85#ibcon#about to write, iclass 28, count 0 2006.161.08:25:52.85#ibcon#wrote, iclass 28, count 0 2006.161.08:25:52.85#ibcon#about to read 3, iclass 28, count 0 2006.161.08:25:52.87#ibcon#read 3, iclass 28, count 0 2006.161.08:25:52.87#ibcon#about to read 4, iclass 28, count 0 2006.161.08:25:52.87#ibcon#read 4, iclass 28, count 0 2006.161.08:25:52.87#ibcon#about to read 5, iclass 28, count 0 2006.161.08:25:52.87#ibcon#read 5, iclass 28, count 0 2006.161.08:25:52.87#ibcon#about to read 6, iclass 28, count 0 2006.161.08:25:52.87#ibcon#read 6, iclass 28, count 0 2006.161.08:25:52.87#ibcon#end of sib2, iclass 28, count 0 2006.161.08:25:52.87#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:25:52.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:25:52.87#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:25:52.87#ibcon#*before write, iclass 28, count 0 2006.161.08:25:52.87#ibcon#enter sib2, iclass 28, count 0 2006.161.08:25:52.87#ibcon#flushed, iclass 28, count 0 2006.161.08:25:52.87#ibcon#about to write, iclass 28, count 0 2006.161.08:25:52.87#ibcon#wrote, iclass 28, count 0 2006.161.08:25:52.87#ibcon#about to read 3, iclass 28, count 0 2006.161.08:25:52.91#ibcon#read 3, iclass 28, count 0 2006.161.08:25:52.91#ibcon#about to read 4, iclass 28, count 0 2006.161.08:25:52.91#ibcon#read 4, iclass 28, count 0 2006.161.08:25:52.91#ibcon#about to read 5, iclass 28, count 0 2006.161.08:25:52.91#ibcon#read 5, iclass 28, count 0 2006.161.08:25:52.91#ibcon#about to read 6, iclass 28, count 0 2006.161.08:25:52.91#ibcon#read 6, iclass 28, count 0 2006.161.08:25:52.91#ibcon#end of sib2, iclass 28, count 0 2006.161.08:25:52.91#ibcon#*after write, iclass 28, count 0 2006.161.08:25:52.91#ibcon#*before return 0, iclass 28, count 0 2006.161.08:25:52.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:52.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.161.08:25:52.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:25:52.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:25:52.91$vc4f8/vb=3,4 2006.161.08:25:52.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.161.08:25:52.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.161.08:25:52.91#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:52.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:52.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:52.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:52.97#ibcon#enter wrdev, iclass 30, count 2 2006.161.08:25:52.97#ibcon#first serial, iclass 30, count 2 2006.161.08:25:52.97#ibcon#enter sib2, iclass 30, count 2 2006.161.08:25:52.97#ibcon#flushed, iclass 30, count 2 2006.161.08:25:52.97#ibcon#about to write, iclass 30, count 2 2006.161.08:25:52.97#ibcon#wrote, iclass 30, count 2 2006.161.08:25:52.97#ibcon#about to read 3, iclass 30, count 2 2006.161.08:25:52.99#ibcon#read 3, iclass 30, count 2 2006.161.08:25:52.99#ibcon#about to read 4, iclass 30, count 2 2006.161.08:25:52.99#ibcon#read 4, iclass 30, count 2 2006.161.08:25:52.99#ibcon#about to read 5, iclass 30, count 2 2006.161.08:25:52.99#ibcon#read 5, iclass 30, count 2 2006.161.08:25:52.99#ibcon#about to read 6, iclass 30, count 2 2006.161.08:25:52.99#ibcon#read 6, iclass 30, count 2 2006.161.08:25:52.99#ibcon#end of sib2, iclass 30, count 2 2006.161.08:25:52.99#ibcon#*mode == 0, iclass 30, count 2 2006.161.08:25:52.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.161.08:25:52.99#ibcon#[27=AT03-04\r\n] 2006.161.08:25:52.99#ibcon#*before write, iclass 30, count 2 2006.161.08:25:52.99#ibcon#enter sib2, iclass 30, count 2 2006.161.08:25:52.99#ibcon#flushed, iclass 30, count 2 2006.161.08:25:52.99#ibcon#about to write, iclass 30, count 2 2006.161.08:25:52.99#ibcon#wrote, iclass 30, count 2 2006.161.08:25:52.99#ibcon#about to read 3, iclass 30, count 2 2006.161.08:25:53.02#ibcon#read 3, iclass 30, count 2 2006.161.08:25:53.02#ibcon#about to read 4, iclass 30, count 2 2006.161.08:25:53.02#ibcon#read 4, iclass 30, count 2 2006.161.08:25:53.02#ibcon#about to read 5, iclass 30, count 2 2006.161.08:25:53.02#ibcon#read 5, iclass 30, count 2 2006.161.08:25:53.02#ibcon#about to read 6, iclass 30, count 2 2006.161.08:25:53.02#ibcon#read 6, iclass 30, count 2 2006.161.08:25:53.02#ibcon#end of sib2, iclass 30, count 2 2006.161.08:25:53.02#ibcon#*after write, iclass 30, count 2 2006.161.08:25:53.02#ibcon#*before return 0, iclass 30, count 2 2006.161.08:25:53.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:53.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.161.08:25:53.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.161.08:25:53.02#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:53.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:53.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:53.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:53.14#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:25:53.14#ibcon#first serial, iclass 30, count 0 2006.161.08:25:53.14#ibcon#enter sib2, iclass 30, count 0 2006.161.08:25:53.14#ibcon#flushed, iclass 30, count 0 2006.161.08:25:53.14#ibcon#about to write, iclass 30, count 0 2006.161.08:25:53.14#ibcon#wrote, iclass 30, count 0 2006.161.08:25:53.14#ibcon#about to read 3, iclass 30, count 0 2006.161.08:25:53.16#ibcon#read 3, iclass 30, count 0 2006.161.08:25:53.16#ibcon#about to read 4, iclass 30, count 0 2006.161.08:25:53.16#ibcon#read 4, iclass 30, count 0 2006.161.08:25:53.16#ibcon#about to read 5, iclass 30, count 0 2006.161.08:25:53.16#ibcon#read 5, iclass 30, count 0 2006.161.08:25:53.16#ibcon#about to read 6, iclass 30, count 0 2006.161.08:25:53.16#ibcon#read 6, iclass 30, count 0 2006.161.08:25:53.16#ibcon#end of sib2, iclass 30, count 0 2006.161.08:25:53.16#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:25:53.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:25:53.16#ibcon#[27=USB\r\n] 2006.161.08:25:53.16#ibcon#*before write, iclass 30, count 0 2006.161.08:25:53.16#ibcon#enter sib2, iclass 30, count 0 2006.161.08:25:53.16#ibcon#flushed, iclass 30, count 0 2006.161.08:25:53.16#ibcon#about to write, iclass 30, count 0 2006.161.08:25:53.16#ibcon#wrote, iclass 30, count 0 2006.161.08:25:53.16#ibcon#about to read 3, iclass 30, count 0 2006.161.08:25:53.19#ibcon#read 3, iclass 30, count 0 2006.161.08:25:53.19#ibcon#about to read 4, iclass 30, count 0 2006.161.08:25:53.19#ibcon#read 4, iclass 30, count 0 2006.161.08:25:53.19#ibcon#about to read 5, iclass 30, count 0 2006.161.08:25:53.19#ibcon#read 5, iclass 30, count 0 2006.161.08:25:53.19#ibcon#about to read 6, iclass 30, count 0 2006.161.08:25:53.19#ibcon#read 6, iclass 30, count 0 2006.161.08:25:53.19#ibcon#end of sib2, iclass 30, count 0 2006.161.08:25:53.19#ibcon#*after write, iclass 30, count 0 2006.161.08:25:53.19#ibcon#*before return 0, iclass 30, count 0 2006.161.08:25:53.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:53.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.161.08:25:53.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:25:53.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:25:53.19$vc4f8/vblo=4,712.99 2006.161.08:25:53.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.161.08:25:53.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.161.08:25:53.19#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:53.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:53.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:53.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:53.19#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:25:53.19#ibcon#first serial, iclass 32, count 0 2006.161.08:25:53.19#ibcon#enter sib2, iclass 32, count 0 2006.161.08:25:53.19#ibcon#flushed, iclass 32, count 0 2006.161.08:25:53.19#ibcon#about to write, iclass 32, count 0 2006.161.08:25:53.19#ibcon#wrote, iclass 32, count 0 2006.161.08:25:53.19#ibcon#about to read 3, iclass 32, count 0 2006.161.08:25:53.21#ibcon#read 3, iclass 32, count 0 2006.161.08:25:53.21#ibcon#about to read 4, iclass 32, count 0 2006.161.08:25:53.21#ibcon#read 4, iclass 32, count 0 2006.161.08:25:53.21#ibcon#about to read 5, iclass 32, count 0 2006.161.08:25:53.21#ibcon#read 5, iclass 32, count 0 2006.161.08:25:53.21#ibcon#about to read 6, iclass 32, count 0 2006.161.08:25:53.21#ibcon#read 6, iclass 32, count 0 2006.161.08:25:53.21#ibcon#end of sib2, iclass 32, count 0 2006.161.08:25:53.21#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:25:53.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:25:53.21#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:25:53.21#ibcon#*before write, iclass 32, count 0 2006.161.08:25:53.21#ibcon#enter sib2, iclass 32, count 0 2006.161.08:25:53.21#ibcon#flushed, iclass 32, count 0 2006.161.08:25:53.21#ibcon#about to write, iclass 32, count 0 2006.161.08:25:53.21#ibcon#wrote, iclass 32, count 0 2006.161.08:25:53.21#ibcon#about to read 3, iclass 32, count 0 2006.161.08:25:53.25#ibcon#read 3, iclass 32, count 0 2006.161.08:25:53.25#ibcon#about to read 4, iclass 32, count 0 2006.161.08:25:53.25#ibcon#read 4, iclass 32, count 0 2006.161.08:25:53.25#ibcon#about to read 5, iclass 32, count 0 2006.161.08:25:53.25#ibcon#read 5, iclass 32, count 0 2006.161.08:25:53.25#ibcon#about to read 6, iclass 32, count 0 2006.161.08:25:53.25#ibcon#read 6, iclass 32, count 0 2006.161.08:25:53.25#ibcon#end of sib2, iclass 32, count 0 2006.161.08:25:53.25#ibcon#*after write, iclass 32, count 0 2006.161.08:25:53.25#ibcon#*before return 0, iclass 32, count 0 2006.161.08:25:53.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:53.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.161.08:25:53.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:25:53.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:25:53.25$vc4f8/vb=4,4 2006.161.08:25:53.25#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.161.08:25:53.25#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.161.08:25:53.25#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:53.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:53.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:53.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:53.31#ibcon#enter wrdev, iclass 34, count 2 2006.161.08:25:53.31#ibcon#first serial, iclass 34, count 2 2006.161.08:25:53.31#ibcon#enter sib2, iclass 34, count 2 2006.161.08:25:53.31#ibcon#flushed, iclass 34, count 2 2006.161.08:25:53.31#ibcon#about to write, iclass 34, count 2 2006.161.08:25:53.31#ibcon#wrote, iclass 34, count 2 2006.161.08:25:53.31#ibcon#about to read 3, iclass 34, count 2 2006.161.08:25:53.33#ibcon#read 3, iclass 34, count 2 2006.161.08:25:53.33#ibcon#about to read 4, iclass 34, count 2 2006.161.08:25:53.33#ibcon#read 4, iclass 34, count 2 2006.161.08:25:53.33#ibcon#about to read 5, iclass 34, count 2 2006.161.08:25:53.33#ibcon#read 5, iclass 34, count 2 2006.161.08:25:53.33#ibcon#about to read 6, iclass 34, count 2 2006.161.08:25:53.33#ibcon#read 6, iclass 34, count 2 2006.161.08:25:53.33#ibcon#end of sib2, iclass 34, count 2 2006.161.08:25:53.33#ibcon#*mode == 0, iclass 34, count 2 2006.161.08:25:53.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.161.08:25:53.33#ibcon#[27=AT04-04\r\n] 2006.161.08:25:53.33#ibcon#*before write, iclass 34, count 2 2006.161.08:25:53.33#ibcon#enter sib2, iclass 34, count 2 2006.161.08:25:53.33#ibcon#flushed, iclass 34, count 2 2006.161.08:25:53.33#ibcon#about to write, iclass 34, count 2 2006.161.08:25:53.33#ibcon#wrote, iclass 34, count 2 2006.161.08:25:53.33#ibcon#about to read 3, iclass 34, count 2 2006.161.08:25:53.36#ibcon#read 3, iclass 34, count 2 2006.161.08:25:53.36#ibcon#about to read 4, iclass 34, count 2 2006.161.08:25:53.36#ibcon#read 4, iclass 34, count 2 2006.161.08:25:53.36#ibcon#about to read 5, iclass 34, count 2 2006.161.08:25:53.36#ibcon#read 5, iclass 34, count 2 2006.161.08:25:53.36#ibcon#about to read 6, iclass 34, count 2 2006.161.08:25:53.36#ibcon#read 6, iclass 34, count 2 2006.161.08:25:53.36#ibcon#end of sib2, iclass 34, count 2 2006.161.08:25:53.36#ibcon#*after write, iclass 34, count 2 2006.161.08:25:53.36#ibcon#*before return 0, iclass 34, count 2 2006.161.08:25:53.36#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:53.36#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.161.08:25:53.36#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.161.08:25:53.36#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:53.36#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:53.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:53.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:53.48#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:25:53.48#ibcon#first serial, iclass 34, count 0 2006.161.08:25:53.48#ibcon#enter sib2, iclass 34, count 0 2006.161.08:25:53.48#ibcon#flushed, iclass 34, count 0 2006.161.08:25:53.48#ibcon#about to write, iclass 34, count 0 2006.161.08:25:53.48#ibcon#wrote, iclass 34, count 0 2006.161.08:25:53.48#ibcon#about to read 3, iclass 34, count 0 2006.161.08:25:53.50#ibcon#read 3, iclass 34, count 0 2006.161.08:25:53.50#ibcon#about to read 4, iclass 34, count 0 2006.161.08:25:53.50#ibcon#read 4, iclass 34, count 0 2006.161.08:25:53.50#ibcon#about to read 5, iclass 34, count 0 2006.161.08:25:53.50#ibcon#read 5, iclass 34, count 0 2006.161.08:25:53.50#ibcon#about to read 6, iclass 34, count 0 2006.161.08:25:53.50#ibcon#read 6, iclass 34, count 0 2006.161.08:25:53.50#ibcon#end of sib2, iclass 34, count 0 2006.161.08:25:53.50#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:25:53.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:25:53.50#ibcon#[27=USB\r\n] 2006.161.08:25:53.50#ibcon#*before write, iclass 34, count 0 2006.161.08:25:53.50#ibcon#enter sib2, iclass 34, count 0 2006.161.08:25:53.50#ibcon#flushed, iclass 34, count 0 2006.161.08:25:53.50#ibcon#about to write, iclass 34, count 0 2006.161.08:25:53.50#ibcon#wrote, iclass 34, count 0 2006.161.08:25:53.50#ibcon#about to read 3, iclass 34, count 0 2006.161.08:25:53.53#ibcon#read 3, iclass 34, count 0 2006.161.08:25:53.53#ibcon#about to read 4, iclass 34, count 0 2006.161.08:25:53.53#ibcon#read 4, iclass 34, count 0 2006.161.08:25:53.53#ibcon#about to read 5, iclass 34, count 0 2006.161.08:25:53.53#ibcon#read 5, iclass 34, count 0 2006.161.08:25:53.53#ibcon#about to read 6, iclass 34, count 0 2006.161.08:25:53.53#ibcon#read 6, iclass 34, count 0 2006.161.08:25:53.53#ibcon#end of sib2, iclass 34, count 0 2006.161.08:25:53.53#ibcon#*after write, iclass 34, count 0 2006.161.08:25:53.53#ibcon#*before return 0, iclass 34, count 0 2006.161.08:25:53.53#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:53.53#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.161.08:25:53.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:25:53.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:25:53.53$vc4f8/vblo=5,744.99 2006.161.08:25:53.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.161.08:25:53.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.161.08:25:53.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:53.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:53.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:53.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:53.53#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:25:53.53#ibcon#first serial, iclass 36, count 0 2006.161.08:25:53.53#ibcon#enter sib2, iclass 36, count 0 2006.161.08:25:53.53#ibcon#flushed, iclass 36, count 0 2006.161.08:25:53.53#ibcon#about to write, iclass 36, count 0 2006.161.08:25:53.53#ibcon#wrote, iclass 36, count 0 2006.161.08:25:53.53#ibcon#about to read 3, iclass 36, count 0 2006.161.08:25:53.55#ibcon#read 3, iclass 36, count 0 2006.161.08:25:53.55#ibcon#about to read 4, iclass 36, count 0 2006.161.08:25:53.55#ibcon#read 4, iclass 36, count 0 2006.161.08:25:53.55#ibcon#about to read 5, iclass 36, count 0 2006.161.08:25:53.55#ibcon#read 5, iclass 36, count 0 2006.161.08:25:53.55#ibcon#about to read 6, iclass 36, count 0 2006.161.08:25:53.55#ibcon#read 6, iclass 36, count 0 2006.161.08:25:53.55#ibcon#end of sib2, iclass 36, count 0 2006.161.08:25:53.55#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:25:53.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:25:53.55#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:25:53.55#ibcon#*before write, iclass 36, count 0 2006.161.08:25:53.55#ibcon#enter sib2, iclass 36, count 0 2006.161.08:25:53.55#ibcon#flushed, iclass 36, count 0 2006.161.08:25:53.55#ibcon#about to write, iclass 36, count 0 2006.161.08:25:53.55#ibcon#wrote, iclass 36, count 0 2006.161.08:25:53.55#ibcon#about to read 3, iclass 36, count 0 2006.161.08:25:53.59#ibcon#read 3, iclass 36, count 0 2006.161.08:25:53.59#ibcon#about to read 4, iclass 36, count 0 2006.161.08:25:53.59#ibcon#read 4, iclass 36, count 0 2006.161.08:25:53.59#ibcon#about to read 5, iclass 36, count 0 2006.161.08:25:53.59#ibcon#read 5, iclass 36, count 0 2006.161.08:25:53.59#ibcon#about to read 6, iclass 36, count 0 2006.161.08:25:53.59#ibcon#read 6, iclass 36, count 0 2006.161.08:25:53.59#ibcon#end of sib2, iclass 36, count 0 2006.161.08:25:53.59#ibcon#*after write, iclass 36, count 0 2006.161.08:25:53.59#ibcon#*before return 0, iclass 36, count 0 2006.161.08:25:53.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:53.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.161.08:25:53.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:25:53.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:25:53.59$vc4f8/vb=5,4 2006.161.08:25:53.59#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:25:53.59#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:25:53.59#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:53.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:25:53.62#abcon#<5=/06 3.1 5.6 23.99 871002.6\r\n> 2006.161.08:25:53.64#abcon#{5=INTERFACE CLEAR} 2006.161.08:25:53.65#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:25:53.65#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:25:53.65#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:25:53.65#ibcon#first serial, iclass 39, count 2 2006.161.08:25:53.65#ibcon#enter sib2, iclass 39, count 2 2006.161.08:25:53.65#ibcon#flushed, iclass 39, count 2 2006.161.08:25:53.65#ibcon#about to write, iclass 39, count 2 2006.161.08:25:53.65#ibcon#wrote, iclass 39, count 2 2006.161.08:25:53.65#ibcon#about to read 3, iclass 39, count 2 2006.161.08:25:53.67#ibcon#read 3, iclass 39, count 2 2006.161.08:25:53.67#ibcon#about to read 4, iclass 39, count 2 2006.161.08:25:53.67#ibcon#read 4, iclass 39, count 2 2006.161.08:25:53.67#ibcon#about to read 5, iclass 39, count 2 2006.161.08:25:53.67#ibcon#read 5, iclass 39, count 2 2006.161.08:25:53.67#ibcon#about to read 6, iclass 39, count 2 2006.161.08:25:53.67#ibcon#read 6, iclass 39, count 2 2006.161.08:25:53.67#ibcon#end of sib2, iclass 39, count 2 2006.161.08:25:53.67#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:25:53.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:25:53.67#ibcon#[27=AT05-04\r\n] 2006.161.08:25:53.67#ibcon#*before write, iclass 39, count 2 2006.161.08:25:53.67#ibcon#enter sib2, iclass 39, count 2 2006.161.08:25:53.67#ibcon#flushed, iclass 39, count 2 2006.161.08:25:53.67#ibcon#about to write, iclass 39, count 2 2006.161.08:25:53.67#ibcon#wrote, iclass 39, count 2 2006.161.08:25:53.67#ibcon#about to read 3, iclass 39, count 2 2006.161.08:25:53.70#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:25:53.70#ibcon#read 3, iclass 39, count 2 2006.161.08:25:53.70#ibcon#about to read 4, iclass 39, count 2 2006.161.08:25:53.70#ibcon#read 4, iclass 39, count 2 2006.161.08:25:53.70#ibcon#about to read 5, iclass 39, count 2 2006.161.08:25:53.70#ibcon#read 5, iclass 39, count 2 2006.161.08:25:53.70#ibcon#about to read 6, iclass 39, count 2 2006.161.08:25:53.70#ibcon#read 6, iclass 39, count 2 2006.161.08:25:53.70#ibcon#end of sib2, iclass 39, count 2 2006.161.08:25:53.70#ibcon#*after write, iclass 39, count 2 2006.161.08:25:53.70#ibcon#*before return 0, iclass 39, count 2 2006.161.08:25:53.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:25:53.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:25:53.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:25:53.70#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:53.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:25:53.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:25:53.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:25:53.82#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:25:53.82#ibcon#first serial, iclass 39, count 0 2006.161.08:25:53.82#ibcon#enter sib2, iclass 39, count 0 2006.161.08:25:53.82#ibcon#flushed, iclass 39, count 0 2006.161.08:25:53.82#ibcon#about to write, iclass 39, count 0 2006.161.08:25:53.82#ibcon#wrote, iclass 39, count 0 2006.161.08:25:53.82#ibcon#about to read 3, iclass 39, count 0 2006.161.08:25:53.84#ibcon#read 3, iclass 39, count 0 2006.161.08:25:53.84#ibcon#about to read 4, iclass 39, count 0 2006.161.08:25:53.84#ibcon#read 4, iclass 39, count 0 2006.161.08:25:53.84#ibcon#about to read 5, iclass 39, count 0 2006.161.08:25:53.84#ibcon#read 5, iclass 39, count 0 2006.161.08:25:53.84#ibcon#about to read 6, iclass 39, count 0 2006.161.08:25:53.84#ibcon#read 6, iclass 39, count 0 2006.161.08:25:53.84#ibcon#end of sib2, iclass 39, count 0 2006.161.08:25:53.84#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:25:53.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:25:53.84#ibcon#[27=USB\r\n] 2006.161.08:25:53.84#ibcon#*before write, iclass 39, count 0 2006.161.08:25:53.84#ibcon#enter sib2, iclass 39, count 0 2006.161.08:25:53.84#ibcon#flushed, iclass 39, count 0 2006.161.08:25:53.84#ibcon#about to write, iclass 39, count 0 2006.161.08:25:53.84#ibcon#wrote, iclass 39, count 0 2006.161.08:25:53.84#ibcon#about to read 3, iclass 39, count 0 2006.161.08:25:53.87#ibcon#read 3, iclass 39, count 0 2006.161.08:25:53.87#ibcon#about to read 4, iclass 39, count 0 2006.161.08:25:53.87#ibcon#read 4, iclass 39, count 0 2006.161.08:25:53.87#ibcon#about to read 5, iclass 39, count 0 2006.161.08:25:53.87#ibcon#read 5, iclass 39, count 0 2006.161.08:25:53.87#ibcon#about to read 6, iclass 39, count 0 2006.161.08:25:53.87#ibcon#read 6, iclass 39, count 0 2006.161.08:25:53.87#ibcon#end of sib2, iclass 39, count 0 2006.161.08:25:53.87#ibcon#*after write, iclass 39, count 0 2006.161.08:25:53.87#ibcon#*before return 0, iclass 39, count 0 2006.161.08:25:53.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:25:53.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:25:53.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:25:53.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:25:53.87$vc4f8/vblo=6,752.99 2006.161.08:25:53.87#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.161.08:25:53.87#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.161.08:25:53.87#ibcon#ireg 17 cls_cnt 0 2006.161.08:25:53.87#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:53.87#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:53.87#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:53.87#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:25:53.87#ibcon#first serial, iclass 6, count 0 2006.161.08:25:53.87#ibcon#enter sib2, iclass 6, count 0 2006.161.08:25:53.87#ibcon#flushed, iclass 6, count 0 2006.161.08:25:53.87#ibcon#about to write, iclass 6, count 0 2006.161.08:25:53.87#ibcon#wrote, iclass 6, count 0 2006.161.08:25:53.87#ibcon#about to read 3, iclass 6, count 0 2006.161.08:25:53.89#ibcon#read 3, iclass 6, count 0 2006.161.08:25:53.89#ibcon#about to read 4, iclass 6, count 0 2006.161.08:25:53.89#ibcon#read 4, iclass 6, count 0 2006.161.08:25:53.89#ibcon#about to read 5, iclass 6, count 0 2006.161.08:25:53.89#ibcon#read 5, iclass 6, count 0 2006.161.08:25:53.89#ibcon#about to read 6, iclass 6, count 0 2006.161.08:25:53.89#ibcon#read 6, iclass 6, count 0 2006.161.08:25:53.89#ibcon#end of sib2, iclass 6, count 0 2006.161.08:25:53.89#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:25:53.89#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:25:53.89#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:25:53.89#ibcon#*before write, iclass 6, count 0 2006.161.08:25:53.89#ibcon#enter sib2, iclass 6, count 0 2006.161.08:25:53.89#ibcon#flushed, iclass 6, count 0 2006.161.08:25:53.89#ibcon#about to write, iclass 6, count 0 2006.161.08:25:53.89#ibcon#wrote, iclass 6, count 0 2006.161.08:25:53.89#ibcon#about to read 3, iclass 6, count 0 2006.161.08:25:53.93#ibcon#read 3, iclass 6, count 0 2006.161.08:25:53.93#ibcon#about to read 4, iclass 6, count 0 2006.161.08:25:53.93#ibcon#read 4, iclass 6, count 0 2006.161.08:25:53.93#ibcon#about to read 5, iclass 6, count 0 2006.161.08:25:53.93#ibcon#read 5, iclass 6, count 0 2006.161.08:25:53.93#ibcon#about to read 6, iclass 6, count 0 2006.161.08:25:53.93#ibcon#read 6, iclass 6, count 0 2006.161.08:25:53.93#ibcon#end of sib2, iclass 6, count 0 2006.161.08:25:53.93#ibcon#*after write, iclass 6, count 0 2006.161.08:25:53.93#ibcon#*before return 0, iclass 6, count 0 2006.161.08:25:53.93#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:53.93#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.161.08:25:53.93#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:25:53.93#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:25:53.93$vc4f8/vb=6,4 2006.161.08:25:53.93#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.161.08:25:53.93#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.161.08:25:53.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:25:53.93#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:53.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:53.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:53.99#ibcon#enter wrdev, iclass 10, count 2 2006.161.08:25:53.99#ibcon#first serial, iclass 10, count 2 2006.161.08:25:53.99#ibcon#enter sib2, iclass 10, count 2 2006.161.08:25:53.99#ibcon#flushed, iclass 10, count 2 2006.161.08:25:53.99#ibcon#about to write, iclass 10, count 2 2006.161.08:25:53.99#ibcon#wrote, iclass 10, count 2 2006.161.08:25:53.99#ibcon#about to read 3, iclass 10, count 2 2006.161.08:25:54.01#ibcon#read 3, iclass 10, count 2 2006.161.08:25:54.01#ibcon#about to read 4, iclass 10, count 2 2006.161.08:25:54.01#ibcon#read 4, iclass 10, count 2 2006.161.08:25:54.01#ibcon#about to read 5, iclass 10, count 2 2006.161.08:25:54.01#ibcon#read 5, iclass 10, count 2 2006.161.08:25:54.01#ibcon#about to read 6, iclass 10, count 2 2006.161.08:25:54.01#ibcon#read 6, iclass 10, count 2 2006.161.08:25:54.01#ibcon#end of sib2, iclass 10, count 2 2006.161.08:25:54.01#ibcon#*mode == 0, iclass 10, count 2 2006.161.08:25:54.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.161.08:25:54.01#ibcon#[27=AT06-04\r\n] 2006.161.08:25:54.01#ibcon#*before write, iclass 10, count 2 2006.161.08:25:54.01#ibcon#enter sib2, iclass 10, count 2 2006.161.08:25:54.01#ibcon#flushed, iclass 10, count 2 2006.161.08:25:54.01#ibcon#about to write, iclass 10, count 2 2006.161.08:25:54.01#ibcon#wrote, iclass 10, count 2 2006.161.08:25:54.01#ibcon#about to read 3, iclass 10, count 2 2006.161.08:25:54.04#ibcon#read 3, iclass 10, count 2 2006.161.08:25:54.04#ibcon#about to read 4, iclass 10, count 2 2006.161.08:25:54.04#ibcon#read 4, iclass 10, count 2 2006.161.08:25:54.04#ibcon#about to read 5, iclass 10, count 2 2006.161.08:25:54.04#ibcon#read 5, iclass 10, count 2 2006.161.08:25:54.04#ibcon#about to read 6, iclass 10, count 2 2006.161.08:25:54.04#ibcon#read 6, iclass 10, count 2 2006.161.08:25:54.04#ibcon#end of sib2, iclass 10, count 2 2006.161.08:25:54.04#ibcon#*after write, iclass 10, count 2 2006.161.08:25:54.04#ibcon#*before return 0, iclass 10, count 2 2006.161.08:25:54.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:54.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.161.08:25:54.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.161.08:25:54.04#ibcon#ireg 7 cls_cnt 0 2006.161.08:25:54.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:54.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:54.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:54.16#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:25:54.16#ibcon#first serial, iclass 10, count 0 2006.161.08:25:54.16#ibcon#enter sib2, iclass 10, count 0 2006.161.08:25:54.16#ibcon#flushed, iclass 10, count 0 2006.161.08:25:54.16#ibcon#about to write, iclass 10, count 0 2006.161.08:25:54.16#ibcon#wrote, iclass 10, count 0 2006.161.08:25:54.16#ibcon#about to read 3, iclass 10, count 0 2006.161.08:25:54.18#ibcon#read 3, iclass 10, count 0 2006.161.08:25:54.18#ibcon#about to read 4, iclass 10, count 0 2006.161.08:25:54.18#ibcon#read 4, iclass 10, count 0 2006.161.08:25:54.18#ibcon#about to read 5, iclass 10, count 0 2006.161.08:25:54.18#ibcon#read 5, iclass 10, count 0 2006.161.08:25:54.18#ibcon#about to read 6, iclass 10, count 0 2006.161.08:25:54.18#ibcon#read 6, iclass 10, count 0 2006.161.08:25:54.18#ibcon#end of sib2, iclass 10, count 0 2006.161.08:25:54.18#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:25:54.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:25:54.18#ibcon#[27=USB\r\n] 2006.161.08:25:54.18#ibcon#*before write, iclass 10, count 0 2006.161.08:25:54.18#ibcon#enter sib2, iclass 10, count 0 2006.161.08:25:54.18#ibcon#flushed, iclass 10, count 0 2006.161.08:25:54.18#ibcon#about to write, iclass 10, count 0 2006.161.08:25:54.18#ibcon#wrote, iclass 10, count 0 2006.161.08:25:54.18#ibcon#about to read 3, iclass 10, count 0 2006.161.08:25:54.21#ibcon#read 3, iclass 10, count 0 2006.161.08:25:54.21#ibcon#about to read 4, iclass 10, count 0 2006.161.08:25:54.21#ibcon#read 4, iclass 10, count 0 2006.161.08:25:54.21#ibcon#about to read 5, iclass 10, count 0 2006.161.08:25:54.21#ibcon#read 5, iclass 10, count 0 2006.161.08:25:54.21#ibcon#about to read 6, iclass 10, count 0 2006.161.08:25:54.21#ibcon#read 6, iclass 10, count 0 2006.161.08:25:54.21#ibcon#end of sib2, iclass 10, count 0 2006.161.08:25:54.21#ibcon#*after write, iclass 10, count 0 2006.161.08:25:54.21#ibcon#*before return 0, iclass 10, count 0 2006.161.08:25:54.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:54.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.161.08:25:54.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:25:54.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:25:54.21$vc4f8/vabw=wide 2006.161.08:25:54.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.161.08:25:54.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.161.08:25:54.21#ibcon#ireg 8 cls_cnt 0 2006.161.08:25:54.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:54.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:54.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:54.21#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:25:54.21#ibcon#first serial, iclass 12, count 0 2006.161.08:25:54.21#ibcon#enter sib2, iclass 12, count 0 2006.161.08:25:54.21#ibcon#flushed, iclass 12, count 0 2006.161.08:25:54.21#ibcon#about to write, iclass 12, count 0 2006.161.08:25:54.21#ibcon#wrote, iclass 12, count 0 2006.161.08:25:54.21#ibcon#about to read 3, iclass 12, count 0 2006.161.08:25:54.23#ibcon#read 3, iclass 12, count 0 2006.161.08:25:54.23#ibcon#about to read 4, iclass 12, count 0 2006.161.08:25:54.23#ibcon#read 4, iclass 12, count 0 2006.161.08:25:54.23#ibcon#about to read 5, iclass 12, count 0 2006.161.08:25:54.23#ibcon#read 5, iclass 12, count 0 2006.161.08:25:54.23#ibcon#about to read 6, iclass 12, count 0 2006.161.08:25:54.23#ibcon#read 6, iclass 12, count 0 2006.161.08:25:54.23#ibcon#end of sib2, iclass 12, count 0 2006.161.08:25:54.23#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:25:54.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:25:54.23#ibcon#[25=BW32\r\n] 2006.161.08:25:54.23#ibcon#*before write, iclass 12, count 0 2006.161.08:25:54.23#ibcon#enter sib2, iclass 12, count 0 2006.161.08:25:54.23#ibcon#flushed, iclass 12, count 0 2006.161.08:25:54.23#ibcon#about to write, iclass 12, count 0 2006.161.08:25:54.23#ibcon#wrote, iclass 12, count 0 2006.161.08:25:54.23#ibcon#about to read 3, iclass 12, count 0 2006.161.08:25:54.26#ibcon#read 3, iclass 12, count 0 2006.161.08:25:54.26#ibcon#about to read 4, iclass 12, count 0 2006.161.08:25:54.26#ibcon#read 4, iclass 12, count 0 2006.161.08:25:54.26#ibcon#about to read 5, iclass 12, count 0 2006.161.08:25:54.26#ibcon#read 5, iclass 12, count 0 2006.161.08:25:54.26#ibcon#about to read 6, iclass 12, count 0 2006.161.08:25:54.26#ibcon#read 6, iclass 12, count 0 2006.161.08:25:54.26#ibcon#end of sib2, iclass 12, count 0 2006.161.08:25:54.26#ibcon#*after write, iclass 12, count 0 2006.161.08:25:54.26#ibcon#*before return 0, iclass 12, count 0 2006.161.08:25:54.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:54.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.161.08:25:54.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:25:54.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:25:54.26$vc4f8/vbbw=wide 2006.161.08:25:54.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:25:54.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:25:54.26#ibcon#ireg 8 cls_cnt 0 2006.161.08:25:54.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:25:54.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:25:54.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:25:54.33#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:25:54.33#ibcon#first serial, iclass 14, count 0 2006.161.08:25:54.33#ibcon#enter sib2, iclass 14, count 0 2006.161.08:25:54.33#ibcon#flushed, iclass 14, count 0 2006.161.08:25:54.33#ibcon#about to write, iclass 14, count 0 2006.161.08:25:54.33#ibcon#wrote, iclass 14, count 0 2006.161.08:25:54.33#ibcon#about to read 3, iclass 14, count 0 2006.161.08:25:54.35#ibcon#read 3, iclass 14, count 0 2006.161.08:25:54.35#ibcon#about to read 4, iclass 14, count 0 2006.161.08:25:54.35#ibcon#read 4, iclass 14, count 0 2006.161.08:25:54.35#ibcon#about to read 5, iclass 14, count 0 2006.161.08:25:54.35#ibcon#read 5, iclass 14, count 0 2006.161.08:25:54.35#ibcon#about to read 6, iclass 14, count 0 2006.161.08:25:54.35#ibcon#read 6, iclass 14, count 0 2006.161.08:25:54.35#ibcon#end of sib2, iclass 14, count 0 2006.161.08:25:54.35#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:25:54.35#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:25:54.35#ibcon#[27=BW32\r\n] 2006.161.08:25:54.35#ibcon#*before write, iclass 14, count 0 2006.161.08:25:54.35#ibcon#enter sib2, iclass 14, count 0 2006.161.08:25:54.35#ibcon#flushed, iclass 14, count 0 2006.161.08:25:54.35#ibcon#about to write, iclass 14, count 0 2006.161.08:25:54.35#ibcon#wrote, iclass 14, count 0 2006.161.08:25:54.35#ibcon#about to read 3, iclass 14, count 0 2006.161.08:25:54.38#ibcon#read 3, iclass 14, count 0 2006.161.08:25:54.38#ibcon#about to read 4, iclass 14, count 0 2006.161.08:25:54.38#ibcon#read 4, iclass 14, count 0 2006.161.08:25:54.38#ibcon#about to read 5, iclass 14, count 0 2006.161.08:25:54.38#ibcon#read 5, iclass 14, count 0 2006.161.08:25:54.38#ibcon#about to read 6, iclass 14, count 0 2006.161.08:25:54.38#ibcon#read 6, iclass 14, count 0 2006.161.08:25:54.38#ibcon#end of sib2, iclass 14, count 0 2006.161.08:25:54.38#ibcon#*after write, iclass 14, count 0 2006.161.08:25:54.38#ibcon#*before return 0, iclass 14, count 0 2006.161.08:25:54.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:25:54.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:25:54.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:25:54.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:25:54.38$4f8m12a/ifd4f 2006.161.08:25:54.38$ifd4f/lo= 2006.161.08:25:54.38$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:25:54.38$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:25:54.38$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:25:54.38$ifd4f/patch= 2006.161.08:25:54.38$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:25:54.38$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:25:54.38$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:25:54.38$4f8m12a/"form=m,16.000,1:2 2006.161.08:25:54.38$4f8m12a/"tpicd 2006.161.08:25:54.38$4f8m12a/echo=off 2006.161.08:25:54.38$4f8m12a/xlog=off 2006.161.08:25:54.38:!2006.161.08:26:30 2006.161.08:26:12.14#trakl#Source acquired 2006.161.08:26:14.14#flagr#flagr/antenna,acquired 2006.161.08:26:30.00:preob 2006.161.08:26:30.14/onsource/TRACKING 2006.161.08:26:30.14:!2006.161.08:26:40 2006.161.08:26:40.00:data_valid=on 2006.161.08:26:40.00:midob 2006.161.08:26:41.14/onsource/TRACKING 2006.161.08:26:41.14/wx/23.99,1002.6,87 2006.161.08:26:41.33/cable/+6.5002E-03 2006.161.08:26:42.42/va/01,08,usb,yes,29,30 2006.161.08:26:42.42/va/02,07,usb,yes,29,30 2006.161.08:26:42.42/va/03,06,usb,yes,30,31 2006.161.08:26:42.42/va/04,07,usb,yes,30,32 2006.161.08:26:42.42/va/05,07,usb,yes,29,31 2006.161.08:26:42.42/va/06,06,usb,yes,29,28 2006.161.08:26:42.42/va/07,06,usb,yes,29,29 2006.161.08:26:42.42/va/08,07,usb,yes,27,27 2006.161.08:26:42.65/valo/01,532.99,yes,locked 2006.161.08:26:42.65/valo/02,572.99,yes,locked 2006.161.08:26:42.65/valo/03,672.99,yes,locked 2006.161.08:26:42.65/valo/04,832.99,yes,locked 2006.161.08:26:42.65/valo/05,652.99,yes,locked 2006.161.08:26:42.65/valo/06,772.99,yes,locked 2006.161.08:26:42.65/valo/07,832.99,yes,locked 2006.161.08:26:42.65/valo/08,852.99,yes,locked 2006.161.08:26:43.74/vb/01,04,usb,yes,29,28 2006.161.08:26:43.74/vb/02,04,usb,yes,31,32 2006.161.08:26:43.74/vb/03,04,usb,yes,27,31 2006.161.08:26:43.74/vb/04,04,usb,yes,28,28 2006.161.08:26:43.74/vb/05,04,usb,yes,27,30 2006.161.08:26:43.74/vb/06,04,usb,yes,27,30 2006.161.08:26:43.74/vb/07,04,usb,yes,29,29 2006.161.08:26:43.74/vb/08,04,usb,yes,27,30 2006.161.08:26:43.97/vblo/01,632.99,yes,locked 2006.161.08:26:43.97/vblo/02,640.99,yes,locked 2006.161.08:26:43.97/vblo/03,656.99,yes,locked 2006.161.08:26:43.97/vblo/04,712.99,yes,locked 2006.161.08:26:43.97/vblo/05,744.99,yes,locked 2006.161.08:26:43.97/vblo/06,752.99,yes,locked 2006.161.08:26:43.97/vblo/07,734.99,yes,locked 2006.161.08:26:43.97/vblo/08,744.99,yes,locked 2006.161.08:26:44.12/vabw/8 2006.161.08:26:44.27/vbbw/8 2006.161.08:26:44.36/xfe/off,on,15.7 2006.161.08:26:44.75/ifatt/23,28,28,28 2006.161.08:26:45.08/fmout-gps/S +4.51E-07 2006.161.08:26:45.12:!2006.161.08:27:40 2006.161.08:27:40.00:data_valid=off 2006.161.08:27:40.00:postob 2006.161.08:27:40.12/cable/+6.5005E-03 2006.161.08:27:40.12/wx/23.98,1002.6,87 2006.161.08:27:41.08/fmout-gps/S +4.52E-07 2006.161.08:27:41.08:scan_name=161-0828,k06161,60 2006.161.08:27:41.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.161.08:27:41.15#flagr#flagr/antenna,new-source 2006.161.08:27:42.14:checkk5 2006.161.08:27:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:27:42.96/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:27:43.52/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:27:44.17/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:27:44.57/chk_obsdata//k5ts1/T1610826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:27:45.00/chk_obsdata//k5ts2/T1610826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:27:45.43/chk_obsdata//k5ts3/T1610826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:27:45.84/chk_obsdata//k5ts4/T1610826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:27:46.66/k5log//k5ts1_log_newline 2006.161.08:27:47.62/k5log//k5ts2_log_newline 2006.161.08:27:48.47/k5log//k5ts3_log_newline 2006.161.08:27:49.50/k5log//k5ts4_log_newline 2006.161.08:27:49.53/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:27:49.53:4f8m12a=3 2006.161.08:27:49.53$4f8m12a/echo=on 2006.161.08:27:49.53$4f8m12a/pcalon 2006.161.08:27:49.53$pcalon/"no phase cal control is implemented here 2006.161.08:27:49.53$4f8m12a/"tpicd=stop 2006.161.08:27:49.53$4f8m12a/vc4f8 2006.161.08:27:49.53$vc4f8/valo=1,532.99 2006.161.08:27:49.53#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:27:49.53#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:27:49.53#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:49.53#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:49.53#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:49.53#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:49.53#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:27:49.53#ibcon#first serial, iclass 25, count 0 2006.161.08:27:49.53#ibcon#enter sib2, iclass 25, count 0 2006.161.08:27:49.53#ibcon#flushed, iclass 25, count 0 2006.161.08:27:49.53#ibcon#about to write, iclass 25, count 0 2006.161.08:27:49.53#ibcon#wrote, iclass 25, count 0 2006.161.08:27:49.53#ibcon#about to read 3, iclass 25, count 0 2006.161.08:27:49.58#ibcon#read 3, iclass 25, count 0 2006.161.08:27:49.58#ibcon#about to read 4, iclass 25, count 0 2006.161.08:27:49.58#ibcon#read 4, iclass 25, count 0 2006.161.08:27:49.58#ibcon#about to read 5, iclass 25, count 0 2006.161.08:27:49.58#ibcon#read 5, iclass 25, count 0 2006.161.08:27:49.58#ibcon#about to read 6, iclass 25, count 0 2006.161.08:27:49.58#ibcon#read 6, iclass 25, count 0 2006.161.08:27:49.58#ibcon#end of sib2, iclass 25, count 0 2006.161.08:27:49.58#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:27:49.58#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:27:49.58#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:27:49.58#ibcon#*before write, iclass 25, count 0 2006.161.08:27:49.58#ibcon#enter sib2, iclass 25, count 0 2006.161.08:27:49.58#ibcon#flushed, iclass 25, count 0 2006.161.08:27:49.58#ibcon#about to write, iclass 25, count 0 2006.161.08:27:49.58#ibcon#wrote, iclass 25, count 0 2006.161.08:27:49.58#ibcon#about to read 3, iclass 25, count 0 2006.161.08:27:49.62#ibcon#read 3, iclass 25, count 0 2006.161.08:27:49.62#ibcon#about to read 4, iclass 25, count 0 2006.161.08:27:49.62#ibcon#read 4, iclass 25, count 0 2006.161.08:27:49.62#ibcon#about to read 5, iclass 25, count 0 2006.161.08:27:49.62#ibcon#read 5, iclass 25, count 0 2006.161.08:27:49.62#ibcon#about to read 6, iclass 25, count 0 2006.161.08:27:49.62#ibcon#read 6, iclass 25, count 0 2006.161.08:27:49.62#ibcon#end of sib2, iclass 25, count 0 2006.161.08:27:49.62#ibcon#*after write, iclass 25, count 0 2006.161.08:27:49.62#ibcon#*before return 0, iclass 25, count 0 2006.161.08:27:49.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:49.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:49.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:27:49.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:27:49.62$vc4f8/va=1,8 2006.161.08:27:49.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:27:49.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:27:49.62#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:49.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:49.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:49.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:49.62#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:27:49.62#ibcon#first serial, iclass 27, count 2 2006.161.08:27:49.62#ibcon#enter sib2, iclass 27, count 2 2006.161.08:27:49.62#ibcon#flushed, iclass 27, count 2 2006.161.08:27:49.62#ibcon#about to write, iclass 27, count 2 2006.161.08:27:49.62#ibcon#wrote, iclass 27, count 2 2006.161.08:27:49.62#ibcon#about to read 3, iclass 27, count 2 2006.161.08:27:49.64#ibcon#read 3, iclass 27, count 2 2006.161.08:27:49.64#ibcon#about to read 4, iclass 27, count 2 2006.161.08:27:49.64#ibcon#read 4, iclass 27, count 2 2006.161.08:27:49.64#ibcon#about to read 5, iclass 27, count 2 2006.161.08:27:49.64#ibcon#read 5, iclass 27, count 2 2006.161.08:27:49.64#ibcon#about to read 6, iclass 27, count 2 2006.161.08:27:49.64#ibcon#read 6, iclass 27, count 2 2006.161.08:27:49.64#ibcon#end of sib2, iclass 27, count 2 2006.161.08:27:49.64#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:27:49.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:27:49.64#ibcon#[25=AT01-08\r\n] 2006.161.08:27:49.64#ibcon#*before write, iclass 27, count 2 2006.161.08:27:49.64#ibcon#enter sib2, iclass 27, count 2 2006.161.08:27:49.64#ibcon#flushed, iclass 27, count 2 2006.161.08:27:49.64#ibcon#about to write, iclass 27, count 2 2006.161.08:27:49.64#ibcon#wrote, iclass 27, count 2 2006.161.08:27:49.64#ibcon#about to read 3, iclass 27, count 2 2006.161.08:27:49.67#ibcon#read 3, iclass 27, count 2 2006.161.08:27:49.67#ibcon#about to read 4, iclass 27, count 2 2006.161.08:27:49.67#ibcon#read 4, iclass 27, count 2 2006.161.08:27:49.67#ibcon#about to read 5, iclass 27, count 2 2006.161.08:27:49.67#ibcon#read 5, iclass 27, count 2 2006.161.08:27:49.67#ibcon#about to read 6, iclass 27, count 2 2006.161.08:27:49.67#ibcon#read 6, iclass 27, count 2 2006.161.08:27:49.67#ibcon#end of sib2, iclass 27, count 2 2006.161.08:27:49.67#ibcon#*after write, iclass 27, count 2 2006.161.08:27:49.67#ibcon#*before return 0, iclass 27, count 2 2006.161.08:27:49.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:49.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:49.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:27:49.67#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:49.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:49.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:49.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:49.79#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:27:49.79#ibcon#first serial, iclass 27, count 0 2006.161.08:27:49.79#ibcon#enter sib2, iclass 27, count 0 2006.161.08:27:49.79#ibcon#flushed, iclass 27, count 0 2006.161.08:27:49.79#ibcon#about to write, iclass 27, count 0 2006.161.08:27:49.79#ibcon#wrote, iclass 27, count 0 2006.161.08:27:49.79#ibcon#about to read 3, iclass 27, count 0 2006.161.08:27:49.81#ibcon#read 3, iclass 27, count 0 2006.161.08:27:49.81#ibcon#about to read 4, iclass 27, count 0 2006.161.08:27:49.81#ibcon#read 4, iclass 27, count 0 2006.161.08:27:49.81#ibcon#about to read 5, iclass 27, count 0 2006.161.08:27:49.81#ibcon#read 5, iclass 27, count 0 2006.161.08:27:49.81#ibcon#about to read 6, iclass 27, count 0 2006.161.08:27:49.81#ibcon#read 6, iclass 27, count 0 2006.161.08:27:49.81#ibcon#end of sib2, iclass 27, count 0 2006.161.08:27:49.81#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:27:49.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:27:49.81#ibcon#[25=USB\r\n] 2006.161.08:27:49.81#ibcon#*before write, iclass 27, count 0 2006.161.08:27:49.81#ibcon#enter sib2, iclass 27, count 0 2006.161.08:27:49.81#ibcon#flushed, iclass 27, count 0 2006.161.08:27:49.81#ibcon#about to write, iclass 27, count 0 2006.161.08:27:49.81#ibcon#wrote, iclass 27, count 0 2006.161.08:27:49.81#ibcon#about to read 3, iclass 27, count 0 2006.161.08:27:49.84#ibcon#read 3, iclass 27, count 0 2006.161.08:27:49.84#ibcon#about to read 4, iclass 27, count 0 2006.161.08:27:49.84#ibcon#read 4, iclass 27, count 0 2006.161.08:27:49.84#ibcon#about to read 5, iclass 27, count 0 2006.161.08:27:49.84#ibcon#read 5, iclass 27, count 0 2006.161.08:27:49.84#ibcon#about to read 6, iclass 27, count 0 2006.161.08:27:49.84#ibcon#read 6, iclass 27, count 0 2006.161.08:27:49.84#ibcon#end of sib2, iclass 27, count 0 2006.161.08:27:49.84#ibcon#*after write, iclass 27, count 0 2006.161.08:27:49.84#ibcon#*before return 0, iclass 27, count 0 2006.161.08:27:49.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:49.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:49.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:27:49.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:27:49.84$vc4f8/valo=2,572.99 2006.161.08:27:49.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:27:49.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:27:49.84#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:49.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:49.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:49.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:49.84#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:27:49.84#ibcon#first serial, iclass 29, count 0 2006.161.08:27:49.84#ibcon#enter sib2, iclass 29, count 0 2006.161.08:27:49.84#ibcon#flushed, iclass 29, count 0 2006.161.08:27:49.84#ibcon#about to write, iclass 29, count 0 2006.161.08:27:49.84#ibcon#wrote, iclass 29, count 0 2006.161.08:27:49.84#ibcon#about to read 3, iclass 29, count 0 2006.161.08:27:49.86#ibcon#read 3, iclass 29, count 0 2006.161.08:27:49.87#ibcon#about to read 4, iclass 29, count 0 2006.161.08:27:49.87#ibcon#read 4, iclass 29, count 0 2006.161.08:27:49.87#ibcon#about to read 5, iclass 29, count 0 2006.161.08:27:49.87#ibcon#read 5, iclass 29, count 0 2006.161.08:27:49.87#ibcon#about to read 6, iclass 29, count 0 2006.161.08:27:49.87#ibcon#read 6, iclass 29, count 0 2006.161.08:27:49.87#ibcon#end of sib2, iclass 29, count 0 2006.161.08:27:49.87#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:27:49.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:27:49.87#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:27:49.87#ibcon#*before write, iclass 29, count 0 2006.161.08:27:49.87#ibcon#enter sib2, iclass 29, count 0 2006.161.08:27:49.87#ibcon#flushed, iclass 29, count 0 2006.161.08:27:49.87#ibcon#about to write, iclass 29, count 0 2006.161.08:27:49.87#ibcon#wrote, iclass 29, count 0 2006.161.08:27:49.87#ibcon#about to read 3, iclass 29, count 0 2006.161.08:27:49.91#ibcon#read 3, iclass 29, count 0 2006.161.08:27:49.91#ibcon#about to read 4, iclass 29, count 0 2006.161.08:27:49.91#ibcon#read 4, iclass 29, count 0 2006.161.08:27:49.91#ibcon#about to read 5, iclass 29, count 0 2006.161.08:27:49.91#ibcon#read 5, iclass 29, count 0 2006.161.08:27:49.91#ibcon#about to read 6, iclass 29, count 0 2006.161.08:27:49.91#ibcon#read 6, iclass 29, count 0 2006.161.08:27:49.91#ibcon#end of sib2, iclass 29, count 0 2006.161.08:27:49.91#ibcon#*after write, iclass 29, count 0 2006.161.08:27:49.91#ibcon#*before return 0, iclass 29, count 0 2006.161.08:27:49.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:49.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:49.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:27:49.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:27:49.91$vc4f8/va=2,7 2006.161.08:27:49.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.08:27:49.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.08:27:49.91#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:49.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:49.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:49.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:49.96#ibcon#enter wrdev, iclass 31, count 2 2006.161.08:27:49.96#ibcon#first serial, iclass 31, count 2 2006.161.08:27:49.96#ibcon#enter sib2, iclass 31, count 2 2006.161.08:27:49.96#ibcon#flushed, iclass 31, count 2 2006.161.08:27:49.96#ibcon#about to write, iclass 31, count 2 2006.161.08:27:49.96#ibcon#wrote, iclass 31, count 2 2006.161.08:27:49.96#ibcon#about to read 3, iclass 31, count 2 2006.161.08:27:49.98#ibcon#read 3, iclass 31, count 2 2006.161.08:27:49.98#ibcon#about to read 4, iclass 31, count 2 2006.161.08:27:49.98#ibcon#read 4, iclass 31, count 2 2006.161.08:27:49.98#ibcon#about to read 5, iclass 31, count 2 2006.161.08:27:49.98#ibcon#read 5, iclass 31, count 2 2006.161.08:27:49.98#ibcon#about to read 6, iclass 31, count 2 2006.161.08:27:49.98#ibcon#read 6, iclass 31, count 2 2006.161.08:27:49.98#ibcon#end of sib2, iclass 31, count 2 2006.161.08:27:49.98#ibcon#*mode == 0, iclass 31, count 2 2006.161.08:27:49.98#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.08:27:49.98#ibcon#[25=AT02-07\r\n] 2006.161.08:27:49.98#ibcon#*before write, iclass 31, count 2 2006.161.08:27:49.98#ibcon#enter sib2, iclass 31, count 2 2006.161.08:27:49.98#ibcon#flushed, iclass 31, count 2 2006.161.08:27:49.98#ibcon#about to write, iclass 31, count 2 2006.161.08:27:49.98#ibcon#wrote, iclass 31, count 2 2006.161.08:27:49.99#ibcon#about to read 3, iclass 31, count 2 2006.161.08:27:50.02#ibcon#read 3, iclass 31, count 2 2006.161.08:27:50.02#ibcon#about to read 4, iclass 31, count 2 2006.161.08:27:50.02#ibcon#read 4, iclass 31, count 2 2006.161.08:27:50.02#ibcon#about to read 5, iclass 31, count 2 2006.161.08:27:50.02#ibcon#read 5, iclass 31, count 2 2006.161.08:27:50.02#ibcon#about to read 6, iclass 31, count 2 2006.161.08:27:50.02#ibcon#read 6, iclass 31, count 2 2006.161.08:27:50.02#ibcon#end of sib2, iclass 31, count 2 2006.161.08:27:50.02#ibcon#*after write, iclass 31, count 2 2006.161.08:27:50.02#ibcon#*before return 0, iclass 31, count 2 2006.161.08:27:50.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:50.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:50.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.08:27:50.02#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:50.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:50.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:50.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:50.14#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:27:50.14#ibcon#first serial, iclass 31, count 0 2006.161.08:27:50.14#ibcon#enter sib2, iclass 31, count 0 2006.161.08:27:50.14#ibcon#flushed, iclass 31, count 0 2006.161.08:27:50.14#ibcon#about to write, iclass 31, count 0 2006.161.08:27:50.14#ibcon#wrote, iclass 31, count 0 2006.161.08:27:50.14#ibcon#about to read 3, iclass 31, count 0 2006.161.08:27:50.16#ibcon#read 3, iclass 31, count 0 2006.161.08:27:50.16#ibcon#about to read 4, iclass 31, count 0 2006.161.08:27:50.16#ibcon#read 4, iclass 31, count 0 2006.161.08:27:50.16#ibcon#about to read 5, iclass 31, count 0 2006.161.08:27:50.16#ibcon#read 5, iclass 31, count 0 2006.161.08:27:50.16#ibcon#about to read 6, iclass 31, count 0 2006.161.08:27:50.16#ibcon#read 6, iclass 31, count 0 2006.161.08:27:50.16#ibcon#end of sib2, iclass 31, count 0 2006.161.08:27:50.16#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:27:50.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:27:50.16#ibcon#[25=USB\r\n] 2006.161.08:27:50.16#ibcon#*before write, iclass 31, count 0 2006.161.08:27:50.16#ibcon#enter sib2, iclass 31, count 0 2006.161.08:27:50.16#ibcon#flushed, iclass 31, count 0 2006.161.08:27:50.16#ibcon#about to write, iclass 31, count 0 2006.161.08:27:50.16#ibcon#wrote, iclass 31, count 0 2006.161.08:27:50.16#ibcon#about to read 3, iclass 31, count 0 2006.161.08:27:50.19#ibcon#read 3, iclass 31, count 0 2006.161.08:27:50.19#ibcon#about to read 4, iclass 31, count 0 2006.161.08:27:50.19#ibcon#read 4, iclass 31, count 0 2006.161.08:27:50.19#ibcon#about to read 5, iclass 31, count 0 2006.161.08:27:50.19#ibcon#read 5, iclass 31, count 0 2006.161.08:27:50.19#ibcon#about to read 6, iclass 31, count 0 2006.161.08:27:50.19#ibcon#read 6, iclass 31, count 0 2006.161.08:27:50.19#ibcon#end of sib2, iclass 31, count 0 2006.161.08:27:50.19#ibcon#*after write, iclass 31, count 0 2006.161.08:27:50.19#ibcon#*before return 0, iclass 31, count 0 2006.161.08:27:50.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:50.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:50.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:27:50.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:27:50.19$vc4f8/valo=3,672.99 2006.161.08:27:50.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.08:27:50.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.08:27:50.19#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:50.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:50.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:50.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:50.19#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:27:50.19#ibcon#first serial, iclass 33, count 0 2006.161.08:27:50.19#ibcon#enter sib2, iclass 33, count 0 2006.161.08:27:50.19#ibcon#flushed, iclass 33, count 0 2006.161.08:27:50.19#ibcon#about to write, iclass 33, count 0 2006.161.08:27:50.19#ibcon#wrote, iclass 33, count 0 2006.161.08:27:50.19#ibcon#about to read 3, iclass 33, count 0 2006.161.08:27:50.21#ibcon#read 3, iclass 33, count 0 2006.161.08:27:50.21#ibcon#about to read 4, iclass 33, count 0 2006.161.08:27:50.21#ibcon#read 4, iclass 33, count 0 2006.161.08:27:50.21#ibcon#about to read 5, iclass 33, count 0 2006.161.08:27:50.21#ibcon#read 5, iclass 33, count 0 2006.161.08:27:50.21#ibcon#about to read 6, iclass 33, count 0 2006.161.08:27:50.21#ibcon#read 6, iclass 33, count 0 2006.161.08:27:50.21#ibcon#end of sib2, iclass 33, count 0 2006.161.08:27:50.21#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:27:50.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:27:50.21#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:27:50.21#ibcon#*before write, iclass 33, count 0 2006.161.08:27:50.21#ibcon#enter sib2, iclass 33, count 0 2006.161.08:27:50.21#ibcon#flushed, iclass 33, count 0 2006.161.08:27:50.21#ibcon#about to write, iclass 33, count 0 2006.161.08:27:50.21#ibcon#wrote, iclass 33, count 0 2006.161.08:27:50.21#ibcon#about to read 3, iclass 33, count 0 2006.161.08:27:50.26#ibcon#read 3, iclass 33, count 0 2006.161.08:27:50.26#ibcon#about to read 4, iclass 33, count 0 2006.161.08:27:50.26#ibcon#read 4, iclass 33, count 0 2006.161.08:27:50.26#ibcon#about to read 5, iclass 33, count 0 2006.161.08:27:50.26#ibcon#read 5, iclass 33, count 0 2006.161.08:27:50.26#ibcon#about to read 6, iclass 33, count 0 2006.161.08:27:50.26#ibcon#read 6, iclass 33, count 0 2006.161.08:27:50.26#ibcon#end of sib2, iclass 33, count 0 2006.161.08:27:50.26#ibcon#*after write, iclass 33, count 0 2006.161.08:27:50.26#ibcon#*before return 0, iclass 33, count 0 2006.161.08:27:50.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:50.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:50.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:27:50.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:27:50.26$vc4f8/va=3,6 2006.161.08:27:50.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.08:27:50.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.08:27:50.26#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:50.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:50.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:50.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:50.31#ibcon#enter wrdev, iclass 35, count 2 2006.161.08:27:50.31#ibcon#first serial, iclass 35, count 2 2006.161.08:27:50.31#ibcon#enter sib2, iclass 35, count 2 2006.161.08:27:50.31#ibcon#flushed, iclass 35, count 2 2006.161.08:27:50.31#ibcon#about to write, iclass 35, count 2 2006.161.08:27:50.31#ibcon#wrote, iclass 35, count 2 2006.161.08:27:50.31#ibcon#about to read 3, iclass 35, count 2 2006.161.08:27:50.33#ibcon#read 3, iclass 35, count 2 2006.161.08:27:50.33#ibcon#about to read 4, iclass 35, count 2 2006.161.08:27:50.33#ibcon#read 4, iclass 35, count 2 2006.161.08:27:50.33#ibcon#about to read 5, iclass 35, count 2 2006.161.08:27:50.33#ibcon#read 5, iclass 35, count 2 2006.161.08:27:50.33#ibcon#about to read 6, iclass 35, count 2 2006.161.08:27:50.33#ibcon#read 6, iclass 35, count 2 2006.161.08:27:50.33#ibcon#end of sib2, iclass 35, count 2 2006.161.08:27:50.33#ibcon#*mode == 0, iclass 35, count 2 2006.161.08:27:50.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.08:27:50.33#ibcon#[25=AT03-06\r\n] 2006.161.08:27:50.33#ibcon#*before write, iclass 35, count 2 2006.161.08:27:50.33#ibcon#enter sib2, iclass 35, count 2 2006.161.08:27:50.33#ibcon#flushed, iclass 35, count 2 2006.161.08:27:50.33#ibcon#about to write, iclass 35, count 2 2006.161.08:27:50.33#ibcon#wrote, iclass 35, count 2 2006.161.08:27:50.34#ibcon#about to read 3, iclass 35, count 2 2006.161.08:27:50.37#ibcon#read 3, iclass 35, count 2 2006.161.08:27:50.37#ibcon#about to read 4, iclass 35, count 2 2006.161.08:27:50.37#ibcon#read 4, iclass 35, count 2 2006.161.08:27:50.37#ibcon#about to read 5, iclass 35, count 2 2006.161.08:27:50.37#ibcon#read 5, iclass 35, count 2 2006.161.08:27:50.37#ibcon#about to read 6, iclass 35, count 2 2006.161.08:27:50.37#ibcon#read 6, iclass 35, count 2 2006.161.08:27:50.37#ibcon#end of sib2, iclass 35, count 2 2006.161.08:27:50.37#ibcon#*after write, iclass 35, count 2 2006.161.08:27:50.37#ibcon#*before return 0, iclass 35, count 2 2006.161.08:27:50.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:50.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:50.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.08:27:50.37#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:50.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:50.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:50.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:50.49#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:27:50.49#ibcon#first serial, iclass 35, count 0 2006.161.08:27:50.49#ibcon#enter sib2, iclass 35, count 0 2006.161.08:27:50.49#ibcon#flushed, iclass 35, count 0 2006.161.08:27:50.49#ibcon#about to write, iclass 35, count 0 2006.161.08:27:50.49#ibcon#wrote, iclass 35, count 0 2006.161.08:27:50.49#ibcon#about to read 3, iclass 35, count 0 2006.161.08:27:50.51#ibcon#read 3, iclass 35, count 0 2006.161.08:27:50.51#ibcon#about to read 4, iclass 35, count 0 2006.161.08:27:50.51#ibcon#read 4, iclass 35, count 0 2006.161.08:27:50.51#ibcon#about to read 5, iclass 35, count 0 2006.161.08:27:50.51#ibcon#read 5, iclass 35, count 0 2006.161.08:27:50.51#ibcon#about to read 6, iclass 35, count 0 2006.161.08:27:50.51#ibcon#read 6, iclass 35, count 0 2006.161.08:27:50.51#ibcon#end of sib2, iclass 35, count 0 2006.161.08:27:50.51#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:27:50.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:27:50.51#ibcon#[25=USB\r\n] 2006.161.08:27:50.51#ibcon#*before write, iclass 35, count 0 2006.161.08:27:50.51#ibcon#enter sib2, iclass 35, count 0 2006.161.08:27:50.51#ibcon#flushed, iclass 35, count 0 2006.161.08:27:50.51#ibcon#about to write, iclass 35, count 0 2006.161.08:27:50.51#ibcon#wrote, iclass 35, count 0 2006.161.08:27:50.51#ibcon#about to read 3, iclass 35, count 0 2006.161.08:27:50.54#ibcon#read 3, iclass 35, count 0 2006.161.08:27:50.54#ibcon#about to read 4, iclass 35, count 0 2006.161.08:27:50.54#ibcon#read 4, iclass 35, count 0 2006.161.08:27:50.54#ibcon#about to read 5, iclass 35, count 0 2006.161.08:27:50.54#ibcon#read 5, iclass 35, count 0 2006.161.08:27:50.54#ibcon#about to read 6, iclass 35, count 0 2006.161.08:27:50.54#ibcon#read 6, iclass 35, count 0 2006.161.08:27:50.54#ibcon#end of sib2, iclass 35, count 0 2006.161.08:27:50.54#ibcon#*after write, iclass 35, count 0 2006.161.08:27:50.54#ibcon#*before return 0, iclass 35, count 0 2006.161.08:27:50.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:50.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:50.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:27:50.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:27:50.54$vc4f8/valo=4,832.99 2006.161.08:27:50.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:27:50.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:27:50.54#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:50.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:50.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:50.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:50.54#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:27:50.54#ibcon#first serial, iclass 37, count 0 2006.161.08:27:50.54#ibcon#enter sib2, iclass 37, count 0 2006.161.08:27:50.54#ibcon#flushed, iclass 37, count 0 2006.161.08:27:50.54#ibcon#about to write, iclass 37, count 0 2006.161.08:27:50.54#ibcon#wrote, iclass 37, count 0 2006.161.08:27:50.54#ibcon#about to read 3, iclass 37, count 0 2006.161.08:27:50.56#ibcon#read 3, iclass 37, count 0 2006.161.08:27:50.56#ibcon#about to read 4, iclass 37, count 0 2006.161.08:27:50.56#ibcon#read 4, iclass 37, count 0 2006.161.08:27:50.56#ibcon#about to read 5, iclass 37, count 0 2006.161.08:27:50.56#ibcon#read 5, iclass 37, count 0 2006.161.08:27:50.56#ibcon#about to read 6, iclass 37, count 0 2006.161.08:27:50.56#ibcon#read 6, iclass 37, count 0 2006.161.08:27:50.56#ibcon#end of sib2, iclass 37, count 0 2006.161.08:27:50.56#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:27:50.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:27:50.56#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:27:50.56#ibcon#*before write, iclass 37, count 0 2006.161.08:27:50.56#ibcon#enter sib2, iclass 37, count 0 2006.161.08:27:50.56#ibcon#flushed, iclass 37, count 0 2006.161.08:27:50.56#ibcon#about to write, iclass 37, count 0 2006.161.08:27:50.56#ibcon#wrote, iclass 37, count 0 2006.161.08:27:50.56#ibcon#about to read 3, iclass 37, count 0 2006.161.08:27:50.60#ibcon#read 3, iclass 37, count 0 2006.161.08:27:50.60#ibcon#about to read 4, iclass 37, count 0 2006.161.08:27:50.60#ibcon#read 4, iclass 37, count 0 2006.161.08:27:50.60#ibcon#about to read 5, iclass 37, count 0 2006.161.08:27:50.60#ibcon#read 5, iclass 37, count 0 2006.161.08:27:50.60#ibcon#about to read 6, iclass 37, count 0 2006.161.08:27:50.60#ibcon#read 6, iclass 37, count 0 2006.161.08:27:50.60#ibcon#end of sib2, iclass 37, count 0 2006.161.08:27:50.60#ibcon#*after write, iclass 37, count 0 2006.161.08:27:50.60#ibcon#*before return 0, iclass 37, count 0 2006.161.08:27:50.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:50.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:50.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:27:50.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:27:50.60$vc4f8/va=4,7 2006.161.08:27:50.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:27:50.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:27:50.60#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:50.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:50.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:50.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:50.66#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:27:50.66#ibcon#first serial, iclass 39, count 2 2006.161.08:27:50.66#ibcon#enter sib2, iclass 39, count 2 2006.161.08:27:50.66#ibcon#flushed, iclass 39, count 2 2006.161.08:27:50.66#ibcon#about to write, iclass 39, count 2 2006.161.08:27:50.66#ibcon#wrote, iclass 39, count 2 2006.161.08:27:50.66#ibcon#about to read 3, iclass 39, count 2 2006.161.08:27:50.68#ibcon#read 3, iclass 39, count 2 2006.161.08:27:50.68#ibcon#about to read 4, iclass 39, count 2 2006.161.08:27:50.68#ibcon#read 4, iclass 39, count 2 2006.161.08:27:50.68#ibcon#about to read 5, iclass 39, count 2 2006.161.08:27:50.68#ibcon#read 5, iclass 39, count 2 2006.161.08:27:50.68#ibcon#about to read 6, iclass 39, count 2 2006.161.08:27:50.68#ibcon#read 6, iclass 39, count 2 2006.161.08:27:50.68#ibcon#end of sib2, iclass 39, count 2 2006.161.08:27:50.68#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:27:50.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:27:50.68#ibcon#[25=AT04-07\r\n] 2006.161.08:27:50.68#ibcon#*before write, iclass 39, count 2 2006.161.08:27:50.68#ibcon#enter sib2, iclass 39, count 2 2006.161.08:27:50.68#ibcon#flushed, iclass 39, count 2 2006.161.08:27:50.68#ibcon#about to write, iclass 39, count 2 2006.161.08:27:50.68#ibcon#wrote, iclass 39, count 2 2006.161.08:27:50.68#ibcon#about to read 3, iclass 39, count 2 2006.161.08:27:50.71#ibcon#read 3, iclass 39, count 2 2006.161.08:27:50.71#ibcon#about to read 4, iclass 39, count 2 2006.161.08:27:50.71#ibcon#read 4, iclass 39, count 2 2006.161.08:27:50.71#ibcon#about to read 5, iclass 39, count 2 2006.161.08:27:50.71#ibcon#read 5, iclass 39, count 2 2006.161.08:27:50.71#ibcon#about to read 6, iclass 39, count 2 2006.161.08:27:50.71#ibcon#read 6, iclass 39, count 2 2006.161.08:27:50.71#ibcon#end of sib2, iclass 39, count 2 2006.161.08:27:50.71#ibcon#*after write, iclass 39, count 2 2006.161.08:27:50.71#ibcon#*before return 0, iclass 39, count 2 2006.161.08:27:50.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:50.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:50.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:27:50.71#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:50.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:50.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:50.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:50.83#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:27:50.83#ibcon#first serial, iclass 39, count 0 2006.161.08:27:50.83#ibcon#enter sib2, iclass 39, count 0 2006.161.08:27:50.83#ibcon#flushed, iclass 39, count 0 2006.161.08:27:50.83#ibcon#about to write, iclass 39, count 0 2006.161.08:27:50.83#ibcon#wrote, iclass 39, count 0 2006.161.08:27:50.83#ibcon#about to read 3, iclass 39, count 0 2006.161.08:27:50.85#ibcon#read 3, iclass 39, count 0 2006.161.08:27:50.85#ibcon#about to read 4, iclass 39, count 0 2006.161.08:27:50.85#ibcon#read 4, iclass 39, count 0 2006.161.08:27:50.85#ibcon#about to read 5, iclass 39, count 0 2006.161.08:27:50.85#ibcon#read 5, iclass 39, count 0 2006.161.08:27:50.85#ibcon#about to read 6, iclass 39, count 0 2006.161.08:27:50.85#ibcon#read 6, iclass 39, count 0 2006.161.08:27:50.85#ibcon#end of sib2, iclass 39, count 0 2006.161.08:27:50.85#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:27:50.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:27:50.85#ibcon#[25=USB\r\n] 2006.161.08:27:50.85#ibcon#*before write, iclass 39, count 0 2006.161.08:27:50.85#ibcon#enter sib2, iclass 39, count 0 2006.161.08:27:50.85#ibcon#flushed, iclass 39, count 0 2006.161.08:27:50.85#ibcon#about to write, iclass 39, count 0 2006.161.08:27:50.85#ibcon#wrote, iclass 39, count 0 2006.161.08:27:50.85#ibcon#about to read 3, iclass 39, count 0 2006.161.08:27:50.88#ibcon#read 3, iclass 39, count 0 2006.161.08:27:50.88#ibcon#about to read 4, iclass 39, count 0 2006.161.08:27:50.88#ibcon#read 4, iclass 39, count 0 2006.161.08:27:50.88#ibcon#about to read 5, iclass 39, count 0 2006.161.08:27:50.88#ibcon#read 5, iclass 39, count 0 2006.161.08:27:50.88#ibcon#about to read 6, iclass 39, count 0 2006.161.08:27:50.88#ibcon#read 6, iclass 39, count 0 2006.161.08:27:50.88#ibcon#end of sib2, iclass 39, count 0 2006.161.08:27:50.88#ibcon#*after write, iclass 39, count 0 2006.161.08:27:50.88#ibcon#*before return 0, iclass 39, count 0 2006.161.08:27:50.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:50.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:50.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:27:50.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:27:50.88$vc4f8/valo=5,652.99 2006.161.08:27:50.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:27:50.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:27:50.88#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:50.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:50.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:50.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:50.88#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:27:50.88#ibcon#first serial, iclass 3, count 0 2006.161.08:27:50.88#ibcon#enter sib2, iclass 3, count 0 2006.161.08:27:50.88#ibcon#flushed, iclass 3, count 0 2006.161.08:27:50.88#ibcon#about to write, iclass 3, count 0 2006.161.08:27:50.88#ibcon#wrote, iclass 3, count 0 2006.161.08:27:50.88#ibcon#about to read 3, iclass 3, count 0 2006.161.08:27:50.90#ibcon#read 3, iclass 3, count 0 2006.161.08:27:50.90#ibcon#about to read 4, iclass 3, count 0 2006.161.08:27:50.90#ibcon#read 4, iclass 3, count 0 2006.161.08:27:50.90#ibcon#about to read 5, iclass 3, count 0 2006.161.08:27:50.90#ibcon#read 5, iclass 3, count 0 2006.161.08:27:50.90#ibcon#about to read 6, iclass 3, count 0 2006.161.08:27:50.90#ibcon#read 6, iclass 3, count 0 2006.161.08:27:50.90#ibcon#end of sib2, iclass 3, count 0 2006.161.08:27:50.90#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:27:50.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:27:50.90#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:27:50.90#ibcon#*before write, iclass 3, count 0 2006.161.08:27:50.90#ibcon#enter sib2, iclass 3, count 0 2006.161.08:27:50.90#ibcon#flushed, iclass 3, count 0 2006.161.08:27:50.90#ibcon#about to write, iclass 3, count 0 2006.161.08:27:50.90#ibcon#wrote, iclass 3, count 0 2006.161.08:27:50.90#ibcon#about to read 3, iclass 3, count 0 2006.161.08:27:50.94#ibcon#read 3, iclass 3, count 0 2006.161.08:27:50.94#ibcon#about to read 4, iclass 3, count 0 2006.161.08:27:50.94#ibcon#read 4, iclass 3, count 0 2006.161.08:27:50.94#ibcon#about to read 5, iclass 3, count 0 2006.161.08:27:50.94#ibcon#read 5, iclass 3, count 0 2006.161.08:27:50.94#ibcon#about to read 6, iclass 3, count 0 2006.161.08:27:50.94#ibcon#read 6, iclass 3, count 0 2006.161.08:27:50.94#ibcon#end of sib2, iclass 3, count 0 2006.161.08:27:50.94#ibcon#*after write, iclass 3, count 0 2006.161.08:27:50.94#ibcon#*before return 0, iclass 3, count 0 2006.161.08:27:50.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:50.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:50.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:27:50.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:27:50.94$vc4f8/va=5,7 2006.161.08:27:50.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:27:50.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:27:50.94#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:50.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:51.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:51.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:51.00#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:27:51.00#ibcon#first serial, iclass 5, count 2 2006.161.08:27:51.00#ibcon#enter sib2, iclass 5, count 2 2006.161.08:27:51.00#ibcon#flushed, iclass 5, count 2 2006.161.08:27:51.00#ibcon#about to write, iclass 5, count 2 2006.161.08:27:51.00#ibcon#wrote, iclass 5, count 2 2006.161.08:27:51.00#ibcon#about to read 3, iclass 5, count 2 2006.161.08:27:51.02#ibcon#read 3, iclass 5, count 2 2006.161.08:27:51.02#ibcon#about to read 4, iclass 5, count 2 2006.161.08:27:51.02#ibcon#read 4, iclass 5, count 2 2006.161.08:27:51.02#ibcon#about to read 5, iclass 5, count 2 2006.161.08:27:51.02#ibcon#read 5, iclass 5, count 2 2006.161.08:27:51.02#ibcon#about to read 6, iclass 5, count 2 2006.161.08:27:51.02#ibcon#read 6, iclass 5, count 2 2006.161.08:27:51.02#ibcon#end of sib2, iclass 5, count 2 2006.161.08:27:51.02#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:27:51.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:27:51.02#ibcon#[25=AT05-07\r\n] 2006.161.08:27:51.02#ibcon#*before write, iclass 5, count 2 2006.161.08:27:51.02#ibcon#enter sib2, iclass 5, count 2 2006.161.08:27:51.02#ibcon#flushed, iclass 5, count 2 2006.161.08:27:51.02#ibcon#about to write, iclass 5, count 2 2006.161.08:27:51.02#ibcon#wrote, iclass 5, count 2 2006.161.08:27:51.02#ibcon#about to read 3, iclass 5, count 2 2006.161.08:27:51.05#ibcon#read 3, iclass 5, count 2 2006.161.08:27:51.05#ibcon#about to read 4, iclass 5, count 2 2006.161.08:27:51.05#ibcon#read 4, iclass 5, count 2 2006.161.08:27:51.05#ibcon#about to read 5, iclass 5, count 2 2006.161.08:27:51.05#ibcon#read 5, iclass 5, count 2 2006.161.08:27:51.05#ibcon#about to read 6, iclass 5, count 2 2006.161.08:27:51.05#ibcon#read 6, iclass 5, count 2 2006.161.08:27:51.05#ibcon#end of sib2, iclass 5, count 2 2006.161.08:27:51.05#ibcon#*after write, iclass 5, count 2 2006.161.08:27:51.05#ibcon#*before return 0, iclass 5, count 2 2006.161.08:27:51.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:51.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:51.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:27:51.05#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:51.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:51.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:51.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:51.17#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:27:51.17#ibcon#first serial, iclass 5, count 0 2006.161.08:27:51.17#ibcon#enter sib2, iclass 5, count 0 2006.161.08:27:51.17#ibcon#flushed, iclass 5, count 0 2006.161.08:27:51.17#ibcon#about to write, iclass 5, count 0 2006.161.08:27:51.17#ibcon#wrote, iclass 5, count 0 2006.161.08:27:51.17#ibcon#about to read 3, iclass 5, count 0 2006.161.08:27:51.19#ibcon#read 3, iclass 5, count 0 2006.161.08:27:51.19#ibcon#about to read 4, iclass 5, count 0 2006.161.08:27:51.19#ibcon#read 4, iclass 5, count 0 2006.161.08:27:51.19#ibcon#about to read 5, iclass 5, count 0 2006.161.08:27:51.19#ibcon#read 5, iclass 5, count 0 2006.161.08:27:51.19#ibcon#about to read 6, iclass 5, count 0 2006.161.08:27:51.19#ibcon#read 6, iclass 5, count 0 2006.161.08:27:51.19#ibcon#end of sib2, iclass 5, count 0 2006.161.08:27:51.19#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:27:51.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:27:51.19#ibcon#[25=USB\r\n] 2006.161.08:27:51.19#ibcon#*before write, iclass 5, count 0 2006.161.08:27:51.19#ibcon#enter sib2, iclass 5, count 0 2006.161.08:27:51.19#ibcon#flushed, iclass 5, count 0 2006.161.08:27:51.19#ibcon#about to write, iclass 5, count 0 2006.161.08:27:51.19#ibcon#wrote, iclass 5, count 0 2006.161.08:27:51.19#ibcon#about to read 3, iclass 5, count 0 2006.161.08:27:51.22#ibcon#read 3, iclass 5, count 0 2006.161.08:27:51.22#ibcon#about to read 4, iclass 5, count 0 2006.161.08:27:51.22#ibcon#read 4, iclass 5, count 0 2006.161.08:27:51.22#ibcon#about to read 5, iclass 5, count 0 2006.161.08:27:51.22#ibcon#read 5, iclass 5, count 0 2006.161.08:27:51.22#ibcon#about to read 6, iclass 5, count 0 2006.161.08:27:51.22#ibcon#read 6, iclass 5, count 0 2006.161.08:27:51.22#ibcon#end of sib2, iclass 5, count 0 2006.161.08:27:51.22#ibcon#*after write, iclass 5, count 0 2006.161.08:27:51.22#ibcon#*before return 0, iclass 5, count 0 2006.161.08:27:51.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:51.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:51.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:27:51.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:27:51.22$vc4f8/valo=6,772.99 2006.161.08:27:51.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:27:51.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:27:51.22#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:51.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:51.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:51.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:51.22#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:27:51.22#ibcon#first serial, iclass 7, count 0 2006.161.08:27:51.22#ibcon#enter sib2, iclass 7, count 0 2006.161.08:27:51.22#ibcon#flushed, iclass 7, count 0 2006.161.08:27:51.22#ibcon#about to write, iclass 7, count 0 2006.161.08:27:51.22#ibcon#wrote, iclass 7, count 0 2006.161.08:27:51.22#ibcon#about to read 3, iclass 7, count 0 2006.161.08:27:51.24#ibcon#read 3, iclass 7, count 0 2006.161.08:27:51.24#ibcon#about to read 4, iclass 7, count 0 2006.161.08:27:51.24#ibcon#read 4, iclass 7, count 0 2006.161.08:27:51.24#ibcon#about to read 5, iclass 7, count 0 2006.161.08:27:51.24#ibcon#read 5, iclass 7, count 0 2006.161.08:27:51.24#ibcon#about to read 6, iclass 7, count 0 2006.161.08:27:51.24#ibcon#read 6, iclass 7, count 0 2006.161.08:27:51.24#ibcon#end of sib2, iclass 7, count 0 2006.161.08:27:51.24#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:27:51.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:27:51.24#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:27:51.24#ibcon#*before write, iclass 7, count 0 2006.161.08:27:51.24#ibcon#enter sib2, iclass 7, count 0 2006.161.08:27:51.24#ibcon#flushed, iclass 7, count 0 2006.161.08:27:51.24#ibcon#about to write, iclass 7, count 0 2006.161.08:27:51.24#ibcon#wrote, iclass 7, count 0 2006.161.08:27:51.24#ibcon#about to read 3, iclass 7, count 0 2006.161.08:27:51.28#ibcon#read 3, iclass 7, count 0 2006.161.08:27:51.28#ibcon#about to read 4, iclass 7, count 0 2006.161.08:27:51.28#ibcon#read 4, iclass 7, count 0 2006.161.08:27:51.28#ibcon#about to read 5, iclass 7, count 0 2006.161.08:27:51.28#ibcon#read 5, iclass 7, count 0 2006.161.08:27:51.28#ibcon#about to read 6, iclass 7, count 0 2006.161.08:27:51.28#ibcon#read 6, iclass 7, count 0 2006.161.08:27:51.28#ibcon#end of sib2, iclass 7, count 0 2006.161.08:27:51.28#ibcon#*after write, iclass 7, count 0 2006.161.08:27:51.28#ibcon#*before return 0, iclass 7, count 0 2006.161.08:27:51.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:51.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:51.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:27:51.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:27:51.28$vc4f8/va=6,6 2006.161.08:27:51.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.161.08:27:51.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.161.08:27:51.28#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:51.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:51.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:51.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:51.34#ibcon#enter wrdev, iclass 11, count 2 2006.161.08:27:51.34#ibcon#first serial, iclass 11, count 2 2006.161.08:27:51.34#ibcon#enter sib2, iclass 11, count 2 2006.161.08:27:51.34#ibcon#flushed, iclass 11, count 2 2006.161.08:27:51.34#ibcon#about to write, iclass 11, count 2 2006.161.08:27:51.34#ibcon#wrote, iclass 11, count 2 2006.161.08:27:51.34#ibcon#about to read 3, iclass 11, count 2 2006.161.08:27:51.36#ibcon#read 3, iclass 11, count 2 2006.161.08:27:51.36#ibcon#about to read 4, iclass 11, count 2 2006.161.08:27:51.36#ibcon#read 4, iclass 11, count 2 2006.161.08:27:51.36#ibcon#about to read 5, iclass 11, count 2 2006.161.08:27:51.36#ibcon#read 5, iclass 11, count 2 2006.161.08:27:51.36#ibcon#about to read 6, iclass 11, count 2 2006.161.08:27:51.36#ibcon#read 6, iclass 11, count 2 2006.161.08:27:51.36#ibcon#end of sib2, iclass 11, count 2 2006.161.08:27:51.36#ibcon#*mode == 0, iclass 11, count 2 2006.161.08:27:51.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.161.08:27:51.36#ibcon#[25=AT06-06\r\n] 2006.161.08:27:51.36#ibcon#*before write, iclass 11, count 2 2006.161.08:27:51.36#ibcon#enter sib2, iclass 11, count 2 2006.161.08:27:51.36#ibcon#flushed, iclass 11, count 2 2006.161.08:27:51.36#ibcon#about to write, iclass 11, count 2 2006.161.08:27:51.36#ibcon#wrote, iclass 11, count 2 2006.161.08:27:51.36#ibcon#about to read 3, iclass 11, count 2 2006.161.08:27:51.39#ibcon#read 3, iclass 11, count 2 2006.161.08:27:51.39#ibcon#about to read 4, iclass 11, count 2 2006.161.08:27:51.39#ibcon#read 4, iclass 11, count 2 2006.161.08:27:51.39#ibcon#about to read 5, iclass 11, count 2 2006.161.08:27:51.39#ibcon#read 5, iclass 11, count 2 2006.161.08:27:51.39#ibcon#about to read 6, iclass 11, count 2 2006.161.08:27:51.39#ibcon#read 6, iclass 11, count 2 2006.161.08:27:51.39#ibcon#end of sib2, iclass 11, count 2 2006.161.08:27:51.39#ibcon#*after write, iclass 11, count 2 2006.161.08:27:51.39#ibcon#*before return 0, iclass 11, count 2 2006.161.08:27:51.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:51.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:51.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.161.08:27:51.39#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:51.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:27:51.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:27:51.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:27:51.51#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:27:51.51#ibcon#first serial, iclass 11, count 0 2006.161.08:27:51.51#ibcon#enter sib2, iclass 11, count 0 2006.161.08:27:51.51#ibcon#flushed, iclass 11, count 0 2006.161.08:27:51.51#ibcon#about to write, iclass 11, count 0 2006.161.08:27:51.51#ibcon#wrote, iclass 11, count 0 2006.161.08:27:51.51#ibcon#about to read 3, iclass 11, count 0 2006.161.08:27:51.53#ibcon#read 3, iclass 11, count 0 2006.161.08:27:51.53#ibcon#about to read 4, iclass 11, count 0 2006.161.08:27:51.53#ibcon#read 4, iclass 11, count 0 2006.161.08:27:51.53#ibcon#about to read 5, iclass 11, count 0 2006.161.08:27:51.53#ibcon#read 5, iclass 11, count 0 2006.161.08:27:51.53#ibcon#about to read 6, iclass 11, count 0 2006.161.08:27:51.53#ibcon#read 6, iclass 11, count 0 2006.161.08:27:51.53#ibcon#end of sib2, iclass 11, count 0 2006.161.08:27:51.53#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:27:51.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:27:51.53#ibcon#[25=USB\r\n] 2006.161.08:27:51.53#ibcon#*before write, iclass 11, count 0 2006.161.08:27:51.53#ibcon#enter sib2, iclass 11, count 0 2006.161.08:27:51.53#ibcon#flushed, iclass 11, count 0 2006.161.08:27:51.53#ibcon#about to write, iclass 11, count 0 2006.161.08:27:51.53#ibcon#wrote, iclass 11, count 0 2006.161.08:27:51.53#ibcon#about to read 3, iclass 11, count 0 2006.161.08:27:51.56#ibcon#read 3, iclass 11, count 0 2006.161.08:27:51.56#ibcon#about to read 4, iclass 11, count 0 2006.161.08:27:51.56#ibcon#read 4, iclass 11, count 0 2006.161.08:27:51.56#ibcon#about to read 5, iclass 11, count 0 2006.161.08:27:51.56#ibcon#read 5, iclass 11, count 0 2006.161.08:27:51.56#ibcon#about to read 6, iclass 11, count 0 2006.161.08:27:51.56#ibcon#read 6, iclass 11, count 0 2006.161.08:27:51.56#ibcon#end of sib2, iclass 11, count 0 2006.161.08:27:51.56#ibcon#*after write, iclass 11, count 0 2006.161.08:27:51.56#ibcon#*before return 0, iclass 11, count 0 2006.161.08:27:51.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:27:51.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.161.08:27:51.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:27:51.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:27:51.56$vc4f8/valo=7,832.99 2006.161.08:27:51.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.161.08:27:51.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.161.08:27:51.56#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:51.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:27:51.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:27:51.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:27:51.56#ibcon#enter wrdev, iclass 13, count 0 2006.161.08:27:51.56#ibcon#first serial, iclass 13, count 0 2006.161.08:27:51.56#ibcon#enter sib2, iclass 13, count 0 2006.161.08:27:51.56#ibcon#flushed, iclass 13, count 0 2006.161.08:27:51.56#ibcon#about to write, iclass 13, count 0 2006.161.08:27:51.56#ibcon#wrote, iclass 13, count 0 2006.161.08:27:51.56#ibcon#about to read 3, iclass 13, count 0 2006.161.08:27:51.58#ibcon#read 3, iclass 13, count 0 2006.161.08:27:51.58#ibcon#about to read 4, iclass 13, count 0 2006.161.08:27:51.58#ibcon#read 4, iclass 13, count 0 2006.161.08:27:51.58#ibcon#about to read 5, iclass 13, count 0 2006.161.08:27:51.58#ibcon#read 5, iclass 13, count 0 2006.161.08:27:51.58#ibcon#about to read 6, iclass 13, count 0 2006.161.08:27:51.58#ibcon#read 6, iclass 13, count 0 2006.161.08:27:51.58#ibcon#end of sib2, iclass 13, count 0 2006.161.08:27:51.58#ibcon#*mode == 0, iclass 13, count 0 2006.161.08:27:51.58#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.161.08:27:51.58#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:27:51.58#ibcon#*before write, iclass 13, count 0 2006.161.08:27:51.58#ibcon#enter sib2, iclass 13, count 0 2006.161.08:27:51.58#ibcon#flushed, iclass 13, count 0 2006.161.08:27:51.58#ibcon#about to write, iclass 13, count 0 2006.161.08:27:51.58#ibcon#wrote, iclass 13, count 0 2006.161.08:27:51.58#ibcon#about to read 3, iclass 13, count 0 2006.161.08:27:51.62#ibcon#read 3, iclass 13, count 0 2006.161.08:27:51.62#ibcon#about to read 4, iclass 13, count 0 2006.161.08:27:51.62#ibcon#read 4, iclass 13, count 0 2006.161.08:27:51.62#ibcon#about to read 5, iclass 13, count 0 2006.161.08:27:51.62#ibcon#read 5, iclass 13, count 0 2006.161.08:27:51.62#ibcon#about to read 6, iclass 13, count 0 2006.161.08:27:51.62#ibcon#read 6, iclass 13, count 0 2006.161.08:27:51.62#ibcon#end of sib2, iclass 13, count 0 2006.161.08:27:51.62#ibcon#*after write, iclass 13, count 0 2006.161.08:27:51.62#ibcon#*before return 0, iclass 13, count 0 2006.161.08:27:51.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:27:51.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.161.08:27:51.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.161.08:27:51.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.161.08:27:51.62$vc4f8/va=7,6 2006.161.08:27:51.62#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.161.08:27:51.62#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.161.08:27:51.62#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:51.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:27:51.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:27:51.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:27:51.68#ibcon#enter wrdev, iclass 15, count 2 2006.161.08:27:51.68#ibcon#first serial, iclass 15, count 2 2006.161.08:27:51.68#ibcon#enter sib2, iclass 15, count 2 2006.161.08:27:51.68#ibcon#flushed, iclass 15, count 2 2006.161.08:27:51.68#ibcon#about to write, iclass 15, count 2 2006.161.08:27:51.68#ibcon#wrote, iclass 15, count 2 2006.161.08:27:51.68#ibcon#about to read 3, iclass 15, count 2 2006.161.08:27:51.70#ibcon#read 3, iclass 15, count 2 2006.161.08:27:51.70#ibcon#about to read 4, iclass 15, count 2 2006.161.08:27:51.70#ibcon#read 4, iclass 15, count 2 2006.161.08:27:51.70#ibcon#about to read 5, iclass 15, count 2 2006.161.08:27:51.70#ibcon#read 5, iclass 15, count 2 2006.161.08:27:51.70#ibcon#about to read 6, iclass 15, count 2 2006.161.08:27:51.70#ibcon#read 6, iclass 15, count 2 2006.161.08:27:51.70#ibcon#end of sib2, iclass 15, count 2 2006.161.08:27:51.70#ibcon#*mode == 0, iclass 15, count 2 2006.161.08:27:51.70#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.161.08:27:51.70#ibcon#[25=AT07-06\r\n] 2006.161.08:27:51.70#ibcon#*before write, iclass 15, count 2 2006.161.08:27:51.70#ibcon#enter sib2, iclass 15, count 2 2006.161.08:27:51.70#ibcon#flushed, iclass 15, count 2 2006.161.08:27:51.70#ibcon#about to write, iclass 15, count 2 2006.161.08:27:51.70#ibcon#wrote, iclass 15, count 2 2006.161.08:27:51.70#ibcon#about to read 3, iclass 15, count 2 2006.161.08:27:51.73#ibcon#read 3, iclass 15, count 2 2006.161.08:27:51.73#ibcon#about to read 4, iclass 15, count 2 2006.161.08:27:51.73#ibcon#read 4, iclass 15, count 2 2006.161.08:27:51.73#ibcon#about to read 5, iclass 15, count 2 2006.161.08:27:51.73#ibcon#read 5, iclass 15, count 2 2006.161.08:27:51.73#ibcon#about to read 6, iclass 15, count 2 2006.161.08:27:51.73#ibcon#read 6, iclass 15, count 2 2006.161.08:27:51.73#ibcon#end of sib2, iclass 15, count 2 2006.161.08:27:51.73#ibcon#*after write, iclass 15, count 2 2006.161.08:27:51.73#ibcon#*before return 0, iclass 15, count 2 2006.161.08:27:51.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:27:51.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.161.08:27:51.73#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.161.08:27:51.73#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:51.73#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:27:51.85#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:27:51.85#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:27:51.85#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:27:51.85#ibcon#first serial, iclass 15, count 0 2006.161.08:27:51.85#ibcon#enter sib2, iclass 15, count 0 2006.161.08:27:51.85#ibcon#flushed, iclass 15, count 0 2006.161.08:27:51.85#ibcon#about to write, iclass 15, count 0 2006.161.08:27:51.85#ibcon#wrote, iclass 15, count 0 2006.161.08:27:51.85#ibcon#about to read 3, iclass 15, count 0 2006.161.08:27:51.87#ibcon#read 3, iclass 15, count 0 2006.161.08:27:51.87#ibcon#about to read 4, iclass 15, count 0 2006.161.08:27:51.87#ibcon#read 4, iclass 15, count 0 2006.161.08:27:51.87#ibcon#about to read 5, iclass 15, count 0 2006.161.08:27:51.87#ibcon#read 5, iclass 15, count 0 2006.161.08:27:51.87#ibcon#about to read 6, iclass 15, count 0 2006.161.08:27:51.87#ibcon#read 6, iclass 15, count 0 2006.161.08:27:51.87#ibcon#end of sib2, iclass 15, count 0 2006.161.08:27:51.87#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:27:51.87#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:27:51.87#ibcon#[25=USB\r\n] 2006.161.08:27:51.87#ibcon#*before write, iclass 15, count 0 2006.161.08:27:51.87#ibcon#enter sib2, iclass 15, count 0 2006.161.08:27:51.87#ibcon#flushed, iclass 15, count 0 2006.161.08:27:51.87#ibcon#about to write, iclass 15, count 0 2006.161.08:27:51.87#ibcon#wrote, iclass 15, count 0 2006.161.08:27:51.87#ibcon#about to read 3, iclass 15, count 0 2006.161.08:27:51.90#ibcon#read 3, iclass 15, count 0 2006.161.08:27:51.90#ibcon#about to read 4, iclass 15, count 0 2006.161.08:27:51.90#ibcon#read 4, iclass 15, count 0 2006.161.08:27:51.90#ibcon#about to read 5, iclass 15, count 0 2006.161.08:27:51.90#ibcon#read 5, iclass 15, count 0 2006.161.08:27:51.90#ibcon#about to read 6, iclass 15, count 0 2006.161.08:27:51.90#ibcon#read 6, iclass 15, count 0 2006.161.08:27:51.90#ibcon#end of sib2, iclass 15, count 0 2006.161.08:27:51.90#ibcon#*after write, iclass 15, count 0 2006.161.08:27:51.90#ibcon#*before return 0, iclass 15, count 0 2006.161.08:27:51.90#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:27:51.90#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.161.08:27:51.90#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:27:51.90#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:27:51.90$vc4f8/valo=8,852.99 2006.161.08:27:51.90#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.161.08:27:51.90#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.161.08:27:51.90#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:51.90#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:27:51.90#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:27:51.90#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:27:51.90#ibcon#enter wrdev, iclass 17, count 0 2006.161.08:27:51.90#ibcon#first serial, iclass 17, count 0 2006.161.08:27:51.90#ibcon#enter sib2, iclass 17, count 0 2006.161.08:27:51.90#ibcon#flushed, iclass 17, count 0 2006.161.08:27:51.90#ibcon#about to write, iclass 17, count 0 2006.161.08:27:51.90#ibcon#wrote, iclass 17, count 0 2006.161.08:27:51.90#ibcon#about to read 3, iclass 17, count 0 2006.161.08:27:51.92#ibcon#read 3, iclass 17, count 0 2006.161.08:27:51.92#ibcon#about to read 4, iclass 17, count 0 2006.161.08:27:51.92#ibcon#read 4, iclass 17, count 0 2006.161.08:27:51.92#ibcon#about to read 5, iclass 17, count 0 2006.161.08:27:51.92#ibcon#read 5, iclass 17, count 0 2006.161.08:27:51.92#ibcon#about to read 6, iclass 17, count 0 2006.161.08:27:51.92#ibcon#read 6, iclass 17, count 0 2006.161.08:27:51.92#ibcon#end of sib2, iclass 17, count 0 2006.161.08:27:51.92#ibcon#*mode == 0, iclass 17, count 0 2006.161.08:27:51.92#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.161.08:27:51.92#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:27:51.92#ibcon#*before write, iclass 17, count 0 2006.161.08:27:51.92#ibcon#enter sib2, iclass 17, count 0 2006.161.08:27:51.92#ibcon#flushed, iclass 17, count 0 2006.161.08:27:51.92#ibcon#about to write, iclass 17, count 0 2006.161.08:27:51.92#ibcon#wrote, iclass 17, count 0 2006.161.08:27:51.92#ibcon#about to read 3, iclass 17, count 0 2006.161.08:27:51.96#ibcon#read 3, iclass 17, count 0 2006.161.08:27:51.96#ibcon#about to read 4, iclass 17, count 0 2006.161.08:27:51.96#ibcon#read 4, iclass 17, count 0 2006.161.08:27:51.96#ibcon#about to read 5, iclass 17, count 0 2006.161.08:27:51.96#ibcon#read 5, iclass 17, count 0 2006.161.08:27:51.96#ibcon#about to read 6, iclass 17, count 0 2006.161.08:27:51.96#ibcon#read 6, iclass 17, count 0 2006.161.08:27:51.96#ibcon#end of sib2, iclass 17, count 0 2006.161.08:27:51.96#ibcon#*after write, iclass 17, count 0 2006.161.08:27:51.96#ibcon#*before return 0, iclass 17, count 0 2006.161.08:27:51.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:27:51.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.161.08:27:51.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.161.08:27:51.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.161.08:27:51.96$vc4f8/va=8,7 2006.161.08:27:51.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.161.08:27:51.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.161.08:27:51.96#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:51.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:27:52.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:27:52.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:27:52.02#ibcon#enter wrdev, iclass 19, count 2 2006.161.08:27:52.02#ibcon#first serial, iclass 19, count 2 2006.161.08:27:52.02#ibcon#enter sib2, iclass 19, count 2 2006.161.08:27:52.02#ibcon#flushed, iclass 19, count 2 2006.161.08:27:52.02#ibcon#about to write, iclass 19, count 2 2006.161.08:27:52.02#ibcon#wrote, iclass 19, count 2 2006.161.08:27:52.02#ibcon#about to read 3, iclass 19, count 2 2006.161.08:27:52.04#ibcon#read 3, iclass 19, count 2 2006.161.08:27:52.04#ibcon#about to read 4, iclass 19, count 2 2006.161.08:27:52.04#ibcon#read 4, iclass 19, count 2 2006.161.08:27:52.04#ibcon#about to read 5, iclass 19, count 2 2006.161.08:27:52.04#ibcon#read 5, iclass 19, count 2 2006.161.08:27:52.04#ibcon#about to read 6, iclass 19, count 2 2006.161.08:27:52.04#ibcon#read 6, iclass 19, count 2 2006.161.08:27:52.04#ibcon#end of sib2, iclass 19, count 2 2006.161.08:27:52.04#ibcon#*mode == 0, iclass 19, count 2 2006.161.08:27:52.04#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.161.08:27:52.04#ibcon#[25=AT08-07\r\n] 2006.161.08:27:52.04#ibcon#*before write, iclass 19, count 2 2006.161.08:27:52.04#ibcon#enter sib2, iclass 19, count 2 2006.161.08:27:52.04#ibcon#flushed, iclass 19, count 2 2006.161.08:27:52.04#ibcon#about to write, iclass 19, count 2 2006.161.08:27:52.04#ibcon#wrote, iclass 19, count 2 2006.161.08:27:52.04#ibcon#about to read 3, iclass 19, count 2 2006.161.08:27:52.07#ibcon#read 3, iclass 19, count 2 2006.161.08:27:52.07#ibcon#about to read 4, iclass 19, count 2 2006.161.08:27:52.07#ibcon#read 4, iclass 19, count 2 2006.161.08:27:52.07#ibcon#about to read 5, iclass 19, count 2 2006.161.08:27:52.07#ibcon#read 5, iclass 19, count 2 2006.161.08:27:52.07#ibcon#about to read 6, iclass 19, count 2 2006.161.08:27:52.07#ibcon#read 6, iclass 19, count 2 2006.161.08:27:52.07#ibcon#end of sib2, iclass 19, count 2 2006.161.08:27:52.07#ibcon#*after write, iclass 19, count 2 2006.161.08:27:52.07#ibcon#*before return 0, iclass 19, count 2 2006.161.08:27:52.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:27:52.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.161.08:27:52.07#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.161.08:27:52.07#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:52.07#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:27:52.19#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:27:52.19#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:27:52.19#ibcon#enter wrdev, iclass 19, count 0 2006.161.08:27:52.19#ibcon#first serial, iclass 19, count 0 2006.161.08:27:52.19#ibcon#enter sib2, iclass 19, count 0 2006.161.08:27:52.19#ibcon#flushed, iclass 19, count 0 2006.161.08:27:52.19#ibcon#about to write, iclass 19, count 0 2006.161.08:27:52.19#ibcon#wrote, iclass 19, count 0 2006.161.08:27:52.19#ibcon#about to read 3, iclass 19, count 0 2006.161.08:27:52.21#ibcon#read 3, iclass 19, count 0 2006.161.08:27:52.21#ibcon#about to read 4, iclass 19, count 0 2006.161.08:27:52.21#ibcon#read 4, iclass 19, count 0 2006.161.08:27:52.21#ibcon#about to read 5, iclass 19, count 0 2006.161.08:27:52.21#ibcon#read 5, iclass 19, count 0 2006.161.08:27:52.21#ibcon#about to read 6, iclass 19, count 0 2006.161.08:27:52.21#ibcon#read 6, iclass 19, count 0 2006.161.08:27:52.21#ibcon#end of sib2, iclass 19, count 0 2006.161.08:27:52.21#ibcon#*mode == 0, iclass 19, count 0 2006.161.08:27:52.21#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.161.08:27:52.21#ibcon#[25=USB\r\n] 2006.161.08:27:52.21#ibcon#*before write, iclass 19, count 0 2006.161.08:27:52.21#ibcon#enter sib2, iclass 19, count 0 2006.161.08:27:52.21#ibcon#flushed, iclass 19, count 0 2006.161.08:27:52.21#ibcon#about to write, iclass 19, count 0 2006.161.08:27:52.21#ibcon#wrote, iclass 19, count 0 2006.161.08:27:52.21#ibcon#about to read 3, iclass 19, count 0 2006.161.08:27:52.24#ibcon#read 3, iclass 19, count 0 2006.161.08:27:52.24#ibcon#about to read 4, iclass 19, count 0 2006.161.08:27:52.24#ibcon#read 4, iclass 19, count 0 2006.161.08:27:52.24#ibcon#about to read 5, iclass 19, count 0 2006.161.08:27:52.24#ibcon#read 5, iclass 19, count 0 2006.161.08:27:52.24#ibcon#about to read 6, iclass 19, count 0 2006.161.08:27:52.24#ibcon#read 6, iclass 19, count 0 2006.161.08:27:52.24#ibcon#end of sib2, iclass 19, count 0 2006.161.08:27:52.24#ibcon#*after write, iclass 19, count 0 2006.161.08:27:52.24#ibcon#*before return 0, iclass 19, count 0 2006.161.08:27:52.24#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:27:52.24#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.161.08:27:52.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.161.08:27:52.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.161.08:27:52.24$vc4f8/vblo=1,632.99 2006.161.08:27:52.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.161.08:27:52.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.161.08:27:52.24#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:52.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:27:52.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:27:52.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:27:52.24#ibcon#enter wrdev, iclass 21, count 0 2006.161.08:27:52.24#ibcon#first serial, iclass 21, count 0 2006.161.08:27:52.24#ibcon#enter sib2, iclass 21, count 0 2006.161.08:27:52.24#ibcon#flushed, iclass 21, count 0 2006.161.08:27:52.24#ibcon#about to write, iclass 21, count 0 2006.161.08:27:52.24#ibcon#wrote, iclass 21, count 0 2006.161.08:27:52.24#ibcon#about to read 3, iclass 21, count 0 2006.161.08:27:52.26#ibcon#read 3, iclass 21, count 0 2006.161.08:27:52.26#ibcon#about to read 4, iclass 21, count 0 2006.161.08:27:52.26#ibcon#read 4, iclass 21, count 0 2006.161.08:27:52.26#ibcon#about to read 5, iclass 21, count 0 2006.161.08:27:52.26#ibcon#read 5, iclass 21, count 0 2006.161.08:27:52.26#ibcon#about to read 6, iclass 21, count 0 2006.161.08:27:52.26#ibcon#read 6, iclass 21, count 0 2006.161.08:27:52.26#ibcon#end of sib2, iclass 21, count 0 2006.161.08:27:52.26#ibcon#*mode == 0, iclass 21, count 0 2006.161.08:27:52.26#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.161.08:27:52.26#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:27:52.26#ibcon#*before write, iclass 21, count 0 2006.161.08:27:52.26#ibcon#enter sib2, iclass 21, count 0 2006.161.08:27:52.26#ibcon#flushed, iclass 21, count 0 2006.161.08:27:52.26#ibcon#about to write, iclass 21, count 0 2006.161.08:27:52.26#ibcon#wrote, iclass 21, count 0 2006.161.08:27:52.26#ibcon#about to read 3, iclass 21, count 0 2006.161.08:27:52.30#ibcon#read 3, iclass 21, count 0 2006.161.08:27:52.30#ibcon#about to read 4, iclass 21, count 0 2006.161.08:27:52.30#ibcon#read 4, iclass 21, count 0 2006.161.08:27:52.30#ibcon#about to read 5, iclass 21, count 0 2006.161.08:27:52.30#ibcon#read 5, iclass 21, count 0 2006.161.08:27:52.30#ibcon#about to read 6, iclass 21, count 0 2006.161.08:27:52.30#ibcon#read 6, iclass 21, count 0 2006.161.08:27:52.30#ibcon#end of sib2, iclass 21, count 0 2006.161.08:27:52.30#ibcon#*after write, iclass 21, count 0 2006.161.08:27:52.30#ibcon#*before return 0, iclass 21, count 0 2006.161.08:27:52.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:27:52.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.161.08:27:52.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.161.08:27:52.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.161.08:27:52.30$vc4f8/vb=1,4 2006.161.08:27:52.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.161.08:27:52.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.161.08:27:52.30#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:52.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:27:52.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:27:52.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:27:52.30#ibcon#enter wrdev, iclass 23, count 2 2006.161.08:27:52.30#ibcon#first serial, iclass 23, count 2 2006.161.08:27:52.30#ibcon#enter sib2, iclass 23, count 2 2006.161.08:27:52.30#ibcon#flushed, iclass 23, count 2 2006.161.08:27:52.30#ibcon#about to write, iclass 23, count 2 2006.161.08:27:52.30#ibcon#wrote, iclass 23, count 2 2006.161.08:27:52.30#ibcon#about to read 3, iclass 23, count 2 2006.161.08:27:52.32#ibcon#read 3, iclass 23, count 2 2006.161.08:27:52.32#ibcon#about to read 4, iclass 23, count 2 2006.161.08:27:52.32#ibcon#read 4, iclass 23, count 2 2006.161.08:27:52.32#ibcon#about to read 5, iclass 23, count 2 2006.161.08:27:52.32#ibcon#read 5, iclass 23, count 2 2006.161.08:27:52.32#ibcon#about to read 6, iclass 23, count 2 2006.161.08:27:52.32#ibcon#read 6, iclass 23, count 2 2006.161.08:27:52.32#ibcon#end of sib2, iclass 23, count 2 2006.161.08:27:52.32#ibcon#*mode == 0, iclass 23, count 2 2006.161.08:27:52.32#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.161.08:27:52.32#ibcon#[27=AT01-04\r\n] 2006.161.08:27:52.32#ibcon#*before write, iclass 23, count 2 2006.161.08:27:52.32#ibcon#enter sib2, iclass 23, count 2 2006.161.08:27:52.32#ibcon#flushed, iclass 23, count 2 2006.161.08:27:52.32#ibcon#about to write, iclass 23, count 2 2006.161.08:27:52.32#ibcon#wrote, iclass 23, count 2 2006.161.08:27:52.32#ibcon#about to read 3, iclass 23, count 2 2006.161.08:27:52.35#ibcon#read 3, iclass 23, count 2 2006.161.08:27:52.35#ibcon#about to read 4, iclass 23, count 2 2006.161.08:27:52.35#ibcon#read 4, iclass 23, count 2 2006.161.08:27:52.35#ibcon#about to read 5, iclass 23, count 2 2006.161.08:27:52.35#ibcon#read 5, iclass 23, count 2 2006.161.08:27:52.35#ibcon#about to read 6, iclass 23, count 2 2006.161.08:27:52.35#ibcon#read 6, iclass 23, count 2 2006.161.08:27:52.35#ibcon#end of sib2, iclass 23, count 2 2006.161.08:27:52.35#ibcon#*after write, iclass 23, count 2 2006.161.08:27:52.35#ibcon#*before return 0, iclass 23, count 2 2006.161.08:27:52.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:27:52.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.161.08:27:52.35#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.161.08:27:52.35#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:52.35#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:27:52.47#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:27:52.47#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:27:52.47#ibcon#enter wrdev, iclass 23, count 0 2006.161.08:27:52.47#ibcon#first serial, iclass 23, count 0 2006.161.08:27:52.47#ibcon#enter sib2, iclass 23, count 0 2006.161.08:27:52.47#ibcon#flushed, iclass 23, count 0 2006.161.08:27:52.47#ibcon#about to write, iclass 23, count 0 2006.161.08:27:52.47#ibcon#wrote, iclass 23, count 0 2006.161.08:27:52.47#ibcon#about to read 3, iclass 23, count 0 2006.161.08:27:52.49#ibcon#read 3, iclass 23, count 0 2006.161.08:27:52.49#ibcon#about to read 4, iclass 23, count 0 2006.161.08:27:52.49#ibcon#read 4, iclass 23, count 0 2006.161.08:27:52.49#ibcon#about to read 5, iclass 23, count 0 2006.161.08:27:52.49#ibcon#read 5, iclass 23, count 0 2006.161.08:27:52.49#ibcon#about to read 6, iclass 23, count 0 2006.161.08:27:52.49#ibcon#read 6, iclass 23, count 0 2006.161.08:27:52.49#ibcon#end of sib2, iclass 23, count 0 2006.161.08:27:52.49#ibcon#*mode == 0, iclass 23, count 0 2006.161.08:27:52.49#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.161.08:27:52.49#ibcon#[27=USB\r\n] 2006.161.08:27:52.49#ibcon#*before write, iclass 23, count 0 2006.161.08:27:52.49#ibcon#enter sib2, iclass 23, count 0 2006.161.08:27:52.49#ibcon#flushed, iclass 23, count 0 2006.161.08:27:52.49#ibcon#about to write, iclass 23, count 0 2006.161.08:27:52.49#ibcon#wrote, iclass 23, count 0 2006.161.08:27:52.49#ibcon#about to read 3, iclass 23, count 0 2006.161.08:27:52.52#ibcon#read 3, iclass 23, count 0 2006.161.08:27:52.52#ibcon#about to read 4, iclass 23, count 0 2006.161.08:27:52.52#ibcon#read 4, iclass 23, count 0 2006.161.08:27:52.52#ibcon#about to read 5, iclass 23, count 0 2006.161.08:27:52.52#ibcon#read 5, iclass 23, count 0 2006.161.08:27:52.52#ibcon#about to read 6, iclass 23, count 0 2006.161.08:27:52.52#ibcon#read 6, iclass 23, count 0 2006.161.08:27:52.52#ibcon#end of sib2, iclass 23, count 0 2006.161.08:27:52.52#ibcon#*after write, iclass 23, count 0 2006.161.08:27:52.52#ibcon#*before return 0, iclass 23, count 0 2006.161.08:27:52.52#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:27:52.52#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.161.08:27:52.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.161.08:27:52.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.161.08:27:52.52$vc4f8/vblo=2,640.99 2006.161.08:27:52.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.161.08:27:52.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.161.08:27:52.52#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:52.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:52.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:52.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:52.52#ibcon#enter wrdev, iclass 25, count 0 2006.161.08:27:52.52#ibcon#first serial, iclass 25, count 0 2006.161.08:27:52.52#ibcon#enter sib2, iclass 25, count 0 2006.161.08:27:52.52#ibcon#flushed, iclass 25, count 0 2006.161.08:27:52.52#ibcon#about to write, iclass 25, count 0 2006.161.08:27:52.52#ibcon#wrote, iclass 25, count 0 2006.161.08:27:52.52#ibcon#about to read 3, iclass 25, count 0 2006.161.08:27:52.54#ibcon#read 3, iclass 25, count 0 2006.161.08:27:52.54#ibcon#about to read 4, iclass 25, count 0 2006.161.08:27:52.54#ibcon#read 4, iclass 25, count 0 2006.161.08:27:52.54#ibcon#about to read 5, iclass 25, count 0 2006.161.08:27:52.54#ibcon#read 5, iclass 25, count 0 2006.161.08:27:52.54#ibcon#about to read 6, iclass 25, count 0 2006.161.08:27:52.54#ibcon#read 6, iclass 25, count 0 2006.161.08:27:52.54#ibcon#end of sib2, iclass 25, count 0 2006.161.08:27:52.54#ibcon#*mode == 0, iclass 25, count 0 2006.161.08:27:52.54#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.161.08:27:52.54#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:27:52.54#ibcon#*before write, iclass 25, count 0 2006.161.08:27:52.54#ibcon#enter sib2, iclass 25, count 0 2006.161.08:27:52.54#ibcon#flushed, iclass 25, count 0 2006.161.08:27:52.54#ibcon#about to write, iclass 25, count 0 2006.161.08:27:52.54#ibcon#wrote, iclass 25, count 0 2006.161.08:27:52.54#ibcon#about to read 3, iclass 25, count 0 2006.161.08:27:52.58#ibcon#read 3, iclass 25, count 0 2006.161.08:27:52.58#ibcon#about to read 4, iclass 25, count 0 2006.161.08:27:52.58#ibcon#read 4, iclass 25, count 0 2006.161.08:27:52.58#ibcon#about to read 5, iclass 25, count 0 2006.161.08:27:52.58#ibcon#read 5, iclass 25, count 0 2006.161.08:27:52.58#ibcon#about to read 6, iclass 25, count 0 2006.161.08:27:52.58#ibcon#read 6, iclass 25, count 0 2006.161.08:27:52.58#ibcon#end of sib2, iclass 25, count 0 2006.161.08:27:52.58#ibcon#*after write, iclass 25, count 0 2006.161.08:27:52.58#ibcon#*before return 0, iclass 25, count 0 2006.161.08:27:52.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:52.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.161.08:27:52.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.161.08:27:52.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.161.08:27:52.58$vc4f8/vb=2,4 2006.161.08:27:52.58#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.161.08:27:52.58#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.161.08:27:52.58#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:52.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:52.64#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:52.64#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:52.64#ibcon#enter wrdev, iclass 27, count 2 2006.161.08:27:52.64#ibcon#first serial, iclass 27, count 2 2006.161.08:27:52.64#ibcon#enter sib2, iclass 27, count 2 2006.161.08:27:52.64#ibcon#flushed, iclass 27, count 2 2006.161.08:27:52.64#ibcon#about to write, iclass 27, count 2 2006.161.08:27:52.64#ibcon#wrote, iclass 27, count 2 2006.161.08:27:52.64#ibcon#about to read 3, iclass 27, count 2 2006.161.08:27:52.66#ibcon#read 3, iclass 27, count 2 2006.161.08:27:52.66#ibcon#about to read 4, iclass 27, count 2 2006.161.08:27:52.66#ibcon#read 4, iclass 27, count 2 2006.161.08:27:52.66#ibcon#about to read 5, iclass 27, count 2 2006.161.08:27:52.66#ibcon#read 5, iclass 27, count 2 2006.161.08:27:52.66#ibcon#about to read 6, iclass 27, count 2 2006.161.08:27:52.66#ibcon#read 6, iclass 27, count 2 2006.161.08:27:52.66#ibcon#end of sib2, iclass 27, count 2 2006.161.08:27:52.66#ibcon#*mode == 0, iclass 27, count 2 2006.161.08:27:52.66#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.161.08:27:52.66#ibcon#[27=AT02-04\r\n] 2006.161.08:27:52.66#ibcon#*before write, iclass 27, count 2 2006.161.08:27:52.66#ibcon#enter sib2, iclass 27, count 2 2006.161.08:27:52.66#ibcon#flushed, iclass 27, count 2 2006.161.08:27:52.66#ibcon#about to write, iclass 27, count 2 2006.161.08:27:52.66#ibcon#wrote, iclass 27, count 2 2006.161.08:27:52.66#ibcon#about to read 3, iclass 27, count 2 2006.161.08:27:52.69#ibcon#read 3, iclass 27, count 2 2006.161.08:27:52.69#ibcon#about to read 4, iclass 27, count 2 2006.161.08:27:52.69#ibcon#read 4, iclass 27, count 2 2006.161.08:27:52.69#ibcon#about to read 5, iclass 27, count 2 2006.161.08:27:52.69#ibcon#read 5, iclass 27, count 2 2006.161.08:27:52.69#ibcon#about to read 6, iclass 27, count 2 2006.161.08:27:52.69#ibcon#read 6, iclass 27, count 2 2006.161.08:27:52.69#ibcon#end of sib2, iclass 27, count 2 2006.161.08:27:52.69#ibcon#*after write, iclass 27, count 2 2006.161.08:27:52.69#ibcon#*before return 0, iclass 27, count 2 2006.161.08:27:52.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:52.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.161.08:27:52.69#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.161.08:27:52.69#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:52.69#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:52.81#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:52.81#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:52.81#ibcon#enter wrdev, iclass 27, count 0 2006.161.08:27:52.81#ibcon#first serial, iclass 27, count 0 2006.161.08:27:52.81#ibcon#enter sib2, iclass 27, count 0 2006.161.08:27:52.81#ibcon#flushed, iclass 27, count 0 2006.161.08:27:52.81#ibcon#about to write, iclass 27, count 0 2006.161.08:27:52.81#ibcon#wrote, iclass 27, count 0 2006.161.08:27:52.81#ibcon#about to read 3, iclass 27, count 0 2006.161.08:27:52.83#ibcon#read 3, iclass 27, count 0 2006.161.08:27:52.83#ibcon#about to read 4, iclass 27, count 0 2006.161.08:27:52.83#ibcon#read 4, iclass 27, count 0 2006.161.08:27:52.83#ibcon#about to read 5, iclass 27, count 0 2006.161.08:27:52.83#ibcon#read 5, iclass 27, count 0 2006.161.08:27:52.83#ibcon#about to read 6, iclass 27, count 0 2006.161.08:27:52.83#ibcon#read 6, iclass 27, count 0 2006.161.08:27:52.83#ibcon#end of sib2, iclass 27, count 0 2006.161.08:27:52.83#ibcon#*mode == 0, iclass 27, count 0 2006.161.08:27:52.83#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.161.08:27:52.83#ibcon#[27=USB\r\n] 2006.161.08:27:52.83#ibcon#*before write, iclass 27, count 0 2006.161.08:27:52.83#ibcon#enter sib2, iclass 27, count 0 2006.161.08:27:52.83#ibcon#flushed, iclass 27, count 0 2006.161.08:27:52.83#ibcon#about to write, iclass 27, count 0 2006.161.08:27:52.83#ibcon#wrote, iclass 27, count 0 2006.161.08:27:52.83#ibcon#about to read 3, iclass 27, count 0 2006.161.08:27:52.86#ibcon#read 3, iclass 27, count 0 2006.161.08:27:52.86#ibcon#about to read 4, iclass 27, count 0 2006.161.08:27:52.86#ibcon#read 4, iclass 27, count 0 2006.161.08:27:52.86#ibcon#about to read 5, iclass 27, count 0 2006.161.08:27:52.86#ibcon#read 5, iclass 27, count 0 2006.161.08:27:52.86#ibcon#about to read 6, iclass 27, count 0 2006.161.08:27:52.86#ibcon#read 6, iclass 27, count 0 2006.161.08:27:52.86#ibcon#end of sib2, iclass 27, count 0 2006.161.08:27:52.86#ibcon#*after write, iclass 27, count 0 2006.161.08:27:52.86#ibcon#*before return 0, iclass 27, count 0 2006.161.08:27:52.86#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:52.86#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.161.08:27:52.86#ibcon#about to clear, iclass 27 cls_cnt 0 2006.161.08:27:52.86#ibcon#cleared, iclass 27 cls_cnt 0 2006.161.08:27:52.86$vc4f8/vblo=3,656.99 2006.161.08:27:52.86#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.161.08:27:52.86#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.161.08:27:52.86#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:52.86#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:52.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:52.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:52.86#ibcon#enter wrdev, iclass 29, count 0 2006.161.08:27:52.86#ibcon#first serial, iclass 29, count 0 2006.161.08:27:52.86#ibcon#enter sib2, iclass 29, count 0 2006.161.08:27:52.86#ibcon#flushed, iclass 29, count 0 2006.161.08:27:52.86#ibcon#about to write, iclass 29, count 0 2006.161.08:27:52.86#ibcon#wrote, iclass 29, count 0 2006.161.08:27:52.86#ibcon#about to read 3, iclass 29, count 0 2006.161.08:27:52.88#ibcon#read 3, iclass 29, count 0 2006.161.08:27:52.88#ibcon#about to read 4, iclass 29, count 0 2006.161.08:27:52.88#ibcon#read 4, iclass 29, count 0 2006.161.08:27:52.88#ibcon#about to read 5, iclass 29, count 0 2006.161.08:27:52.88#ibcon#read 5, iclass 29, count 0 2006.161.08:27:52.88#ibcon#about to read 6, iclass 29, count 0 2006.161.08:27:52.88#ibcon#read 6, iclass 29, count 0 2006.161.08:27:52.88#ibcon#end of sib2, iclass 29, count 0 2006.161.08:27:52.88#ibcon#*mode == 0, iclass 29, count 0 2006.161.08:27:52.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.161.08:27:52.89#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:27:52.89#ibcon#*before write, iclass 29, count 0 2006.161.08:27:52.89#ibcon#enter sib2, iclass 29, count 0 2006.161.08:27:52.89#ibcon#flushed, iclass 29, count 0 2006.161.08:27:52.89#ibcon#about to write, iclass 29, count 0 2006.161.08:27:52.89#ibcon#wrote, iclass 29, count 0 2006.161.08:27:52.89#ibcon#about to read 3, iclass 29, count 0 2006.161.08:27:52.93#ibcon#read 3, iclass 29, count 0 2006.161.08:27:52.93#ibcon#about to read 4, iclass 29, count 0 2006.161.08:27:52.93#ibcon#read 4, iclass 29, count 0 2006.161.08:27:52.93#ibcon#about to read 5, iclass 29, count 0 2006.161.08:27:52.93#ibcon#read 5, iclass 29, count 0 2006.161.08:27:52.93#ibcon#about to read 6, iclass 29, count 0 2006.161.08:27:52.93#ibcon#read 6, iclass 29, count 0 2006.161.08:27:52.93#ibcon#end of sib2, iclass 29, count 0 2006.161.08:27:52.93#ibcon#*after write, iclass 29, count 0 2006.161.08:27:52.93#ibcon#*before return 0, iclass 29, count 0 2006.161.08:27:52.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:52.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.161.08:27:52.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.161.08:27:52.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.161.08:27:52.93$vc4f8/vb=3,4 2006.161.08:27:52.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.161.08:27:52.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.161.08:27:52.93#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:52.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:52.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:52.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:52.98#ibcon#enter wrdev, iclass 31, count 2 2006.161.08:27:52.98#ibcon#first serial, iclass 31, count 2 2006.161.08:27:52.98#ibcon#enter sib2, iclass 31, count 2 2006.161.08:27:52.98#ibcon#flushed, iclass 31, count 2 2006.161.08:27:52.98#ibcon#about to write, iclass 31, count 2 2006.161.08:27:52.98#ibcon#wrote, iclass 31, count 2 2006.161.08:27:52.98#ibcon#about to read 3, iclass 31, count 2 2006.161.08:27:53.00#ibcon#read 3, iclass 31, count 2 2006.161.08:27:53.00#ibcon#about to read 4, iclass 31, count 2 2006.161.08:27:53.00#ibcon#read 4, iclass 31, count 2 2006.161.08:27:53.00#ibcon#about to read 5, iclass 31, count 2 2006.161.08:27:53.00#ibcon#read 5, iclass 31, count 2 2006.161.08:27:53.00#ibcon#about to read 6, iclass 31, count 2 2006.161.08:27:53.00#ibcon#read 6, iclass 31, count 2 2006.161.08:27:53.00#ibcon#end of sib2, iclass 31, count 2 2006.161.08:27:53.00#ibcon#*mode == 0, iclass 31, count 2 2006.161.08:27:53.00#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.161.08:27:53.00#ibcon#[27=AT03-04\r\n] 2006.161.08:27:53.00#ibcon#*before write, iclass 31, count 2 2006.161.08:27:53.00#ibcon#enter sib2, iclass 31, count 2 2006.161.08:27:53.00#ibcon#flushed, iclass 31, count 2 2006.161.08:27:53.00#ibcon#about to write, iclass 31, count 2 2006.161.08:27:53.00#ibcon#wrote, iclass 31, count 2 2006.161.08:27:53.00#ibcon#about to read 3, iclass 31, count 2 2006.161.08:27:53.03#ibcon#read 3, iclass 31, count 2 2006.161.08:27:53.03#ibcon#about to read 4, iclass 31, count 2 2006.161.08:27:53.03#ibcon#read 4, iclass 31, count 2 2006.161.08:27:53.03#ibcon#about to read 5, iclass 31, count 2 2006.161.08:27:53.03#ibcon#read 5, iclass 31, count 2 2006.161.08:27:53.03#ibcon#about to read 6, iclass 31, count 2 2006.161.08:27:53.03#ibcon#read 6, iclass 31, count 2 2006.161.08:27:53.03#ibcon#end of sib2, iclass 31, count 2 2006.161.08:27:53.03#ibcon#*after write, iclass 31, count 2 2006.161.08:27:53.03#ibcon#*before return 0, iclass 31, count 2 2006.161.08:27:53.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:53.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.161.08:27:53.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.161.08:27:53.03#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:53.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:53.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:53.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:53.15#ibcon#enter wrdev, iclass 31, count 0 2006.161.08:27:53.15#ibcon#first serial, iclass 31, count 0 2006.161.08:27:53.15#ibcon#enter sib2, iclass 31, count 0 2006.161.08:27:53.15#ibcon#flushed, iclass 31, count 0 2006.161.08:27:53.15#ibcon#about to write, iclass 31, count 0 2006.161.08:27:53.15#ibcon#wrote, iclass 31, count 0 2006.161.08:27:53.15#ibcon#about to read 3, iclass 31, count 0 2006.161.08:27:53.17#ibcon#read 3, iclass 31, count 0 2006.161.08:27:53.17#ibcon#about to read 4, iclass 31, count 0 2006.161.08:27:53.17#ibcon#read 4, iclass 31, count 0 2006.161.08:27:53.17#ibcon#about to read 5, iclass 31, count 0 2006.161.08:27:53.17#ibcon#read 5, iclass 31, count 0 2006.161.08:27:53.17#ibcon#about to read 6, iclass 31, count 0 2006.161.08:27:53.17#ibcon#read 6, iclass 31, count 0 2006.161.08:27:53.17#ibcon#end of sib2, iclass 31, count 0 2006.161.08:27:53.17#ibcon#*mode == 0, iclass 31, count 0 2006.161.08:27:53.17#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.161.08:27:53.17#ibcon#[27=USB\r\n] 2006.161.08:27:53.17#ibcon#*before write, iclass 31, count 0 2006.161.08:27:53.17#ibcon#enter sib2, iclass 31, count 0 2006.161.08:27:53.17#ibcon#flushed, iclass 31, count 0 2006.161.08:27:53.17#ibcon#about to write, iclass 31, count 0 2006.161.08:27:53.17#ibcon#wrote, iclass 31, count 0 2006.161.08:27:53.17#ibcon#about to read 3, iclass 31, count 0 2006.161.08:27:53.20#ibcon#read 3, iclass 31, count 0 2006.161.08:27:53.20#ibcon#about to read 4, iclass 31, count 0 2006.161.08:27:53.20#ibcon#read 4, iclass 31, count 0 2006.161.08:27:53.20#ibcon#about to read 5, iclass 31, count 0 2006.161.08:27:53.20#ibcon#read 5, iclass 31, count 0 2006.161.08:27:53.20#ibcon#about to read 6, iclass 31, count 0 2006.161.08:27:53.20#ibcon#read 6, iclass 31, count 0 2006.161.08:27:53.20#ibcon#end of sib2, iclass 31, count 0 2006.161.08:27:53.20#ibcon#*after write, iclass 31, count 0 2006.161.08:27:53.20#ibcon#*before return 0, iclass 31, count 0 2006.161.08:27:53.20#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:53.20#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.161.08:27:53.20#ibcon#about to clear, iclass 31 cls_cnt 0 2006.161.08:27:53.20#ibcon#cleared, iclass 31 cls_cnt 0 2006.161.08:27:53.20$vc4f8/vblo=4,712.99 2006.161.08:27:53.20#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.161.08:27:53.20#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.161.08:27:53.20#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:53.20#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:53.20#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:53.20#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:53.20#ibcon#enter wrdev, iclass 33, count 0 2006.161.08:27:53.20#ibcon#first serial, iclass 33, count 0 2006.161.08:27:53.20#ibcon#enter sib2, iclass 33, count 0 2006.161.08:27:53.20#ibcon#flushed, iclass 33, count 0 2006.161.08:27:53.20#ibcon#about to write, iclass 33, count 0 2006.161.08:27:53.20#ibcon#wrote, iclass 33, count 0 2006.161.08:27:53.20#ibcon#about to read 3, iclass 33, count 0 2006.161.08:27:53.22#ibcon#read 3, iclass 33, count 0 2006.161.08:27:53.22#ibcon#about to read 4, iclass 33, count 0 2006.161.08:27:53.22#ibcon#read 4, iclass 33, count 0 2006.161.08:27:53.22#ibcon#about to read 5, iclass 33, count 0 2006.161.08:27:53.22#ibcon#read 5, iclass 33, count 0 2006.161.08:27:53.22#ibcon#about to read 6, iclass 33, count 0 2006.161.08:27:53.22#ibcon#read 6, iclass 33, count 0 2006.161.08:27:53.22#ibcon#end of sib2, iclass 33, count 0 2006.161.08:27:53.22#ibcon#*mode == 0, iclass 33, count 0 2006.161.08:27:53.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.161.08:27:53.22#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:27:53.22#ibcon#*before write, iclass 33, count 0 2006.161.08:27:53.22#ibcon#enter sib2, iclass 33, count 0 2006.161.08:27:53.22#ibcon#flushed, iclass 33, count 0 2006.161.08:27:53.22#ibcon#about to write, iclass 33, count 0 2006.161.08:27:53.22#ibcon#wrote, iclass 33, count 0 2006.161.08:27:53.22#ibcon#about to read 3, iclass 33, count 0 2006.161.08:27:53.26#ibcon#read 3, iclass 33, count 0 2006.161.08:27:53.26#ibcon#about to read 4, iclass 33, count 0 2006.161.08:27:53.26#ibcon#read 4, iclass 33, count 0 2006.161.08:27:53.26#ibcon#about to read 5, iclass 33, count 0 2006.161.08:27:53.26#ibcon#read 5, iclass 33, count 0 2006.161.08:27:53.26#ibcon#about to read 6, iclass 33, count 0 2006.161.08:27:53.26#ibcon#read 6, iclass 33, count 0 2006.161.08:27:53.26#ibcon#end of sib2, iclass 33, count 0 2006.161.08:27:53.26#ibcon#*after write, iclass 33, count 0 2006.161.08:27:53.26#ibcon#*before return 0, iclass 33, count 0 2006.161.08:27:53.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:53.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.161.08:27:53.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.161.08:27:53.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.161.08:27:53.26$vc4f8/vb=4,4 2006.161.08:27:53.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.161.08:27:53.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.161.08:27:53.26#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:53.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:53.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:53.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:53.32#ibcon#enter wrdev, iclass 35, count 2 2006.161.08:27:53.32#ibcon#first serial, iclass 35, count 2 2006.161.08:27:53.32#ibcon#enter sib2, iclass 35, count 2 2006.161.08:27:53.32#ibcon#flushed, iclass 35, count 2 2006.161.08:27:53.32#ibcon#about to write, iclass 35, count 2 2006.161.08:27:53.32#ibcon#wrote, iclass 35, count 2 2006.161.08:27:53.32#ibcon#about to read 3, iclass 35, count 2 2006.161.08:27:53.34#ibcon#read 3, iclass 35, count 2 2006.161.08:27:53.34#ibcon#about to read 4, iclass 35, count 2 2006.161.08:27:53.34#ibcon#read 4, iclass 35, count 2 2006.161.08:27:53.34#ibcon#about to read 5, iclass 35, count 2 2006.161.08:27:53.34#ibcon#read 5, iclass 35, count 2 2006.161.08:27:53.34#ibcon#about to read 6, iclass 35, count 2 2006.161.08:27:53.34#ibcon#read 6, iclass 35, count 2 2006.161.08:27:53.34#ibcon#end of sib2, iclass 35, count 2 2006.161.08:27:53.34#ibcon#*mode == 0, iclass 35, count 2 2006.161.08:27:53.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.161.08:27:53.34#ibcon#[27=AT04-04\r\n] 2006.161.08:27:53.34#ibcon#*before write, iclass 35, count 2 2006.161.08:27:53.34#ibcon#enter sib2, iclass 35, count 2 2006.161.08:27:53.34#ibcon#flushed, iclass 35, count 2 2006.161.08:27:53.34#ibcon#about to write, iclass 35, count 2 2006.161.08:27:53.34#ibcon#wrote, iclass 35, count 2 2006.161.08:27:53.34#ibcon#about to read 3, iclass 35, count 2 2006.161.08:27:53.37#ibcon#read 3, iclass 35, count 2 2006.161.08:27:53.37#ibcon#about to read 4, iclass 35, count 2 2006.161.08:27:53.37#ibcon#read 4, iclass 35, count 2 2006.161.08:27:53.37#ibcon#about to read 5, iclass 35, count 2 2006.161.08:27:53.37#ibcon#read 5, iclass 35, count 2 2006.161.08:27:53.37#ibcon#about to read 6, iclass 35, count 2 2006.161.08:27:53.37#ibcon#read 6, iclass 35, count 2 2006.161.08:27:53.37#ibcon#end of sib2, iclass 35, count 2 2006.161.08:27:53.37#ibcon#*after write, iclass 35, count 2 2006.161.08:27:53.37#ibcon#*before return 0, iclass 35, count 2 2006.161.08:27:53.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:53.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.161.08:27:53.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.161.08:27:53.37#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:53.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:53.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:53.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:53.49#ibcon#enter wrdev, iclass 35, count 0 2006.161.08:27:53.49#ibcon#first serial, iclass 35, count 0 2006.161.08:27:53.49#ibcon#enter sib2, iclass 35, count 0 2006.161.08:27:53.49#ibcon#flushed, iclass 35, count 0 2006.161.08:27:53.49#ibcon#about to write, iclass 35, count 0 2006.161.08:27:53.49#ibcon#wrote, iclass 35, count 0 2006.161.08:27:53.49#ibcon#about to read 3, iclass 35, count 0 2006.161.08:27:53.51#ibcon#read 3, iclass 35, count 0 2006.161.08:27:53.51#ibcon#about to read 4, iclass 35, count 0 2006.161.08:27:53.51#ibcon#read 4, iclass 35, count 0 2006.161.08:27:53.51#ibcon#about to read 5, iclass 35, count 0 2006.161.08:27:53.51#ibcon#read 5, iclass 35, count 0 2006.161.08:27:53.51#ibcon#about to read 6, iclass 35, count 0 2006.161.08:27:53.51#ibcon#read 6, iclass 35, count 0 2006.161.08:27:53.51#ibcon#end of sib2, iclass 35, count 0 2006.161.08:27:53.51#ibcon#*mode == 0, iclass 35, count 0 2006.161.08:27:53.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.161.08:27:53.51#ibcon#[27=USB\r\n] 2006.161.08:27:53.51#ibcon#*before write, iclass 35, count 0 2006.161.08:27:53.51#ibcon#enter sib2, iclass 35, count 0 2006.161.08:27:53.51#ibcon#flushed, iclass 35, count 0 2006.161.08:27:53.51#ibcon#about to write, iclass 35, count 0 2006.161.08:27:53.51#ibcon#wrote, iclass 35, count 0 2006.161.08:27:53.51#ibcon#about to read 3, iclass 35, count 0 2006.161.08:27:53.54#ibcon#read 3, iclass 35, count 0 2006.161.08:27:53.54#ibcon#about to read 4, iclass 35, count 0 2006.161.08:27:53.54#ibcon#read 4, iclass 35, count 0 2006.161.08:27:53.54#ibcon#about to read 5, iclass 35, count 0 2006.161.08:27:53.54#ibcon#read 5, iclass 35, count 0 2006.161.08:27:53.54#ibcon#about to read 6, iclass 35, count 0 2006.161.08:27:53.54#ibcon#read 6, iclass 35, count 0 2006.161.08:27:53.54#ibcon#end of sib2, iclass 35, count 0 2006.161.08:27:53.54#ibcon#*after write, iclass 35, count 0 2006.161.08:27:53.54#ibcon#*before return 0, iclass 35, count 0 2006.161.08:27:53.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:53.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.161.08:27:53.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.161.08:27:53.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.161.08:27:53.54$vc4f8/vblo=5,744.99 2006.161.08:27:53.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.161.08:27:53.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.161.08:27:53.54#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:53.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:53.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:53.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:53.54#ibcon#enter wrdev, iclass 37, count 0 2006.161.08:27:53.54#ibcon#first serial, iclass 37, count 0 2006.161.08:27:53.54#ibcon#enter sib2, iclass 37, count 0 2006.161.08:27:53.54#ibcon#flushed, iclass 37, count 0 2006.161.08:27:53.54#ibcon#about to write, iclass 37, count 0 2006.161.08:27:53.54#ibcon#wrote, iclass 37, count 0 2006.161.08:27:53.54#ibcon#about to read 3, iclass 37, count 0 2006.161.08:27:53.56#ibcon#read 3, iclass 37, count 0 2006.161.08:27:53.56#ibcon#about to read 4, iclass 37, count 0 2006.161.08:27:53.56#ibcon#read 4, iclass 37, count 0 2006.161.08:27:53.56#ibcon#about to read 5, iclass 37, count 0 2006.161.08:27:53.56#ibcon#read 5, iclass 37, count 0 2006.161.08:27:53.56#ibcon#about to read 6, iclass 37, count 0 2006.161.08:27:53.56#ibcon#read 6, iclass 37, count 0 2006.161.08:27:53.56#ibcon#end of sib2, iclass 37, count 0 2006.161.08:27:53.56#ibcon#*mode == 0, iclass 37, count 0 2006.161.08:27:53.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.161.08:27:53.56#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:27:53.56#ibcon#*before write, iclass 37, count 0 2006.161.08:27:53.56#ibcon#enter sib2, iclass 37, count 0 2006.161.08:27:53.56#ibcon#flushed, iclass 37, count 0 2006.161.08:27:53.56#ibcon#about to write, iclass 37, count 0 2006.161.08:27:53.56#ibcon#wrote, iclass 37, count 0 2006.161.08:27:53.56#ibcon#about to read 3, iclass 37, count 0 2006.161.08:27:53.60#ibcon#read 3, iclass 37, count 0 2006.161.08:27:53.60#ibcon#about to read 4, iclass 37, count 0 2006.161.08:27:53.60#ibcon#read 4, iclass 37, count 0 2006.161.08:27:53.60#ibcon#about to read 5, iclass 37, count 0 2006.161.08:27:53.60#ibcon#read 5, iclass 37, count 0 2006.161.08:27:53.60#ibcon#about to read 6, iclass 37, count 0 2006.161.08:27:53.60#ibcon#read 6, iclass 37, count 0 2006.161.08:27:53.60#ibcon#end of sib2, iclass 37, count 0 2006.161.08:27:53.60#ibcon#*after write, iclass 37, count 0 2006.161.08:27:53.60#ibcon#*before return 0, iclass 37, count 0 2006.161.08:27:53.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:53.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.161.08:27:53.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.161.08:27:53.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.161.08:27:53.60$vc4f8/vb=5,4 2006.161.08:27:53.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.161.08:27:53.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.161.08:27:53.60#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:53.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:53.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:53.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:53.66#ibcon#enter wrdev, iclass 39, count 2 2006.161.08:27:53.66#ibcon#first serial, iclass 39, count 2 2006.161.08:27:53.66#ibcon#enter sib2, iclass 39, count 2 2006.161.08:27:53.66#ibcon#flushed, iclass 39, count 2 2006.161.08:27:53.66#ibcon#about to write, iclass 39, count 2 2006.161.08:27:53.66#ibcon#wrote, iclass 39, count 2 2006.161.08:27:53.66#ibcon#about to read 3, iclass 39, count 2 2006.161.08:27:53.68#ibcon#read 3, iclass 39, count 2 2006.161.08:27:53.68#ibcon#about to read 4, iclass 39, count 2 2006.161.08:27:53.68#ibcon#read 4, iclass 39, count 2 2006.161.08:27:53.69#ibcon#about to read 5, iclass 39, count 2 2006.161.08:27:53.69#ibcon#read 5, iclass 39, count 2 2006.161.08:27:53.69#ibcon#about to read 6, iclass 39, count 2 2006.161.08:27:53.69#ibcon#read 6, iclass 39, count 2 2006.161.08:27:53.69#ibcon#end of sib2, iclass 39, count 2 2006.161.08:27:53.69#ibcon#*mode == 0, iclass 39, count 2 2006.161.08:27:53.69#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.161.08:27:53.69#ibcon#[27=AT05-04\r\n] 2006.161.08:27:53.69#ibcon#*before write, iclass 39, count 2 2006.161.08:27:53.69#ibcon#enter sib2, iclass 39, count 2 2006.161.08:27:53.69#ibcon#flushed, iclass 39, count 2 2006.161.08:27:53.69#ibcon#about to write, iclass 39, count 2 2006.161.08:27:53.69#ibcon#wrote, iclass 39, count 2 2006.161.08:27:53.69#ibcon#about to read 3, iclass 39, count 2 2006.161.08:27:53.72#ibcon#read 3, iclass 39, count 2 2006.161.08:27:53.72#ibcon#about to read 4, iclass 39, count 2 2006.161.08:27:53.72#ibcon#read 4, iclass 39, count 2 2006.161.08:27:53.72#ibcon#about to read 5, iclass 39, count 2 2006.161.08:27:53.72#ibcon#read 5, iclass 39, count 2 2006.161.08:27:53.72#ibcon#about to read 6, iclass 39, count 2 2006.161.08:27:53.72#ibcon#read 6, iclass 39, count 2 2006.161.08:27:53.72#ibcon#end of sib2, iclass 39, count 2 2006.161.08:27:53.72#ibcon#*after write, iclass 39, count 2 2006.161.08:27:53.72#ibcon#*before return 0, iclass 39, count 2 2006.161.08:27:53.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:53.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.161.08:27:53.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.161.08:27:53.72#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:53.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:53.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:53.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:53.84#ibcon#enter wrdev, iclass 39, count 0 2006.161.08:27:53.84#ibcon#first serial, iclass 39, count 0 2006.161.08:27:53.84#ibcon#enter sib2, iclass 39, count 0 2006.161.08:27:53.84#ibcon#flushed, iclass 39, count 0 2006.161.08:27:53.84#ibcon#about to write, iclass 39, count 0 2006.161.08:27:53.84#ibcon#wrote, iclass 39, count 0 2006.161.08:27:53.84#ibcon#about to read 3, iclass 39, count 0 2006.161.08:27:53.86#ibcon#read 3, iclass 39, count 0 2006.161.08:27:53.86#ibcon#about to read 4, iclass 39, count 0 2006.161.08:27:53.86#ibcon#read 4, iclass 39, count 0 2006.161.08:27:53.86#ibcon#about to read 5, iclass 39, count 0 2006.161.08:27:53.86#ibcon#read 5, iclass 39, count 0 2006.161.08:27:53.86#ibcon#about to read 6, iclass 39, count 0 2006.161.08:27:53.86#ibcon#read 6, iclass 39, count 0 2006.161.08:27:53.86#ibcon#end of sib2, iclass 39, count 0 2006.161.08:27:53.86#ibcon#*mode == 0, iclass 39, count 0 2006.161.08:27:53.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.161.08:27:53.86#ibcon#[27=USB\r\n] 2006.161.08:27:53.86#ibcon#*before write, iclass 39, count 0 2006.161.08:27:53.86#ibcon#enter sib2, iclass 39, count 0 2006.161.08:27:53.86#ibcon#flushed, iclass 39, count 0 2006.161.08:27:53.86#ibcon#about to write, iclass 39, count 0 2006.161.08:27:53.86#ibcon#wrote, iclass 39, count 0 2006.161.08:27:53.86#ibcon#about to read 3, iclass 39, count 0 2006.161.08:27:53.89#ibcon#read 3, iclass 39, count 0 2006.161.08:27:53.89#ibcon#about to read 4, iclass 39, count 0 2006.161.08:27:53.89#ibcon#read 4, iclass 39, count 0 2006.161.08:27:53.89#ibcon#about to read 5, iclass 39, count 0 2006.161.08:27:53.89#ibcon#read 5, iclass 39, count 0 2006.161.08:27:53.89#ibcon#about to read 6, iclass 39, count 0 2006.161.08:27:53.89#ibcon#read 6, iclass 39, count 0 2006.161.08:27:53.89#ibcon#end of sib2, iclass 39, count 0 2006.161.08:27:53.89#ibcon#*after write, iclass 39, count 0 2006.161.08:27:53.89#ibcon#*before return 0, iclass 39, count 0 2006.161.08:27:53.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:53.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.161.08:27:53.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.161.08:27:53.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.161.08:27:53.89$vc4f8/vblo=6,752.99 2006.161.08:27:53.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.161.08:27:53.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.161.08:27:53.89#ibcon#ireg 17 cls_cnt 0 2006.161.08:27:53.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:53.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:53.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:53.89#ibcon#enter wrdev, iclass 3, count 0 2006.161.08:27:53.89#ibcon#first serial, iclass 3, count 0 2006.161.08:27:53.89#ibcon#enter sib2, iclass 3, count 0 2006.161.08:27:53.89#ibcon#flushed, iclass 3, count 0 2006.161.08:27:53.89#ibcon#about to write, iclass 3, count 0 2006.161.08:27:53.89#ibcon#wrote, iclass 3, count 0 2006.161.08:27:53.89#ibcon#about to read 3, iclass 3, count 0 2006.161.08:27:53.91#ibcon#read 3, iclass 3, count 0 2006.161.08:27:53.91#ibcon#about to read 4, iclass 3, count 0 2006.161.08:27:53.91#ibcon#read 4, iclass 3, count 0 2006.161.08:27:53.91#ibcon#about to read 5, iclass 3, count 0 2006.161.08:27:53.91#ibcon#read 5, iclass 3, count 0 2006.161.08:27:53.91#ibcon#about to read 6, iclass 3, count 0 2006.161.08:27:53.91#ibcon#read 6, iclass 3, count 0 2006.161.08:27:53.91#ibcon#end of sib2, iclass 3, count 0 2006.161.08:27:53.91#ibcon#*mode == 0, iclass 3, count 0 2006.161.08:27:53.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.161.08:27:53.91#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:27:53.91#ibcon#*before write, iclass 3, count 0 2006.161.08:27:53.91#ibcon#enter sib2, iclass 3, count 0 2006.161.08:27:53.91#ibcon#flushed, iclass 3, count 0 2006.161.08:27:53.91#ibcon#about to write, iclass 3, count 0 2006.161.08:27:53.91#ibcon#wrote, iclass 3, count 0 2006.161.08:27:53.91#ibcon#about to read 3, iclass 3, count 0 2006.161.08:27:53.95#ibcon#read 3, iclass 3, count 0 2006.161.08:27:53.95#ibcon#about to read 4, iclass 3, count 0 2006.161.08:27:53.95#ibcon#read 4, iclass 3, count 0 2006.161.08:27:53.95#ibcon#about to read 5, iclass 3, count 0 2006.161.08:27:53.95#ibcon#read 5, iclass 3, count 0 2006.161.08:27:53.95#ibcon#about to read 6, iclass 3, count 0 2006.161.08:27:53.95#ibcon#read 6, iclass 3, count 0 2006.161.08:27:53.95#ibcon#end of sib2, iclass 3, count 0 2006.161.08:27:53.95#ibcon#*after write, iclass 3, count 0 2006.161.08:27:53.95#ibcon#*before return 0, iclass 3, count 0 2006.161.08:27:53.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:53.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.161.08:27:53.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.161.08:27:53.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.161.08:27:53.95$vc4f8/vb=6,4 2006.161.08:27:53.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.161.08:27:53.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.161.08:27:53.95#ibcon#ireg 11 cls_cnt 2 2006.161.08:27:53.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:54.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:54.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:54.01#ibcon#enter wrdev, iclass 5, count 2 2006.161.08:27:54.01#ibcon#first serial, iclass 5, count 2 2006.161.08:27:54.01#ibcon#enter sib2, iclass 5, count 2 2006.161.08:27:54.01#ibcon#flushed, iclass 5, count 2 2006.161.08:27:54.01#ibcon#about to write, iclass 5, count 2 2006.161.08:27:54.01#ibcon#wrote, iclass 5, count 2 2006.161.08:27:54.01#ibcon#about to read 3, iclass 5, count 2 2006.161.08:27:54.03#ibcon#read 3, iclass 5, count 2 2006.161.08:27:54.03#ibcon#about to read 4, iclass 5, count 2 2006.161.08:27:54.03#ibcon#read 4, iclass 5, count 2 2006.161.08:27:54.03#ibcon#about to read 5, iclass 5, count 2 2006.161.08:27:54.03#ibcon#read 5, iclass 5, count 2 2006.161.08:27:54.03#ibcon#about to read 6, iclass 5, count 2 2006.161.08:27:54.03#ibcon#read 6, iclass 5, count 2 2006.161.08:27:54.03#ibcon#end of sib2, iclass 5, count 2 2006.161.08:27:54.03#ibcon#*mode == 0, iclass 5, count 2 2006.161.08:27:54.03#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.161.08:27:54.03#ibcon#[27=AT06-04\r\n] 2006.161.08:27:54.03#ibcon#*before write, iclass 5, count 2 2006.161.08:27:54.03#ibcon#enter sib2, iclass 5, count 2 2006.161.08:27:54.03#ibcon#flushed, iclass 5, count 2 2006.161.08:27:54.03#ibcon#about to write, iclass 5, count 2 2006.161.08:27:54.03#ibcon#wrote, iclass 5, count 2 2006.161.08:27:54.03#ibcon#about to read 3, iclass 5, count 2 2006.161.08:27:54.06#ibcon#read 3, iclass 5, count 2 2006.161.08:27:54.06#ibcon#about to read 4, iclass 5, count 2 2006.161.08:27:54.06#ibcon#read 4, iclass 5, count 2 2006.161.08:27:54.06#ibcon#about to read 5, iclass 5, count 2 2006.161.08:27:54.06#ibcon#read 5, iclass 5, count 2 2006.161.08:27:54.06#ibcon#about to read 6, iclass 5, count 2 2006.161.08:27:54.06#ibcon#read 6, iclass 5, count 2 2006.161.08:27:54.06#ibcon#end of sib2, iclass 5, count 2 2006.161.08:27:54.06#ibcon#*after write, iclass 5, count 2 2006.161.08:27:54.06#ibcon#*before return 0, iclass 5, count 2 2006.161.08:27:54.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:54.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.161.08:27:54.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.161.08:27:54.06#ibcon#ireg 7 cls_cnt 0 2006.161.08:27:54.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:54.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:54.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:54.18#ibcon#enter wrdev, iclass 5, count 0 2006.161.08:27:54.18#ibcon#first serial, iclass 5, count 0 2006.161.08:27:54.18#ibcon#enter sib2, iclass 5, count 0 2006.161.08:27:54.18#ibcon#flushed, iclass 5, count 0 2006.161.08:27:54.18#ibcon#about to write, iclass 5, count 0 2006.161.08:27:54.18#ibcon#wrote, iclass 5, count 0 2006.161.08:27:54.18#ibcon#about to read 3, iclass 5, count 0 2006.161.08:27:54.20#ibcon#read 3, iclass 5, count 0 2006.161.08:27:54.20#ibcon#about to read 4, iclass 5, count 0 2006.161.08:27:54.20#ibcon#read 4, iclass 5, count 0 2006.161.08:27:54.20#ibcon#about to read 5, iclass 5, count 0 2006.161.08:27:54.20#ibcon#read 5, iclass 5, count 0 2006.161.08:27:54.20#ibcon#about to read 6, iclass 5, count 0 2006.161.08:27:54.20#ibcon#read 6, iclass 5, count 0 2006.161.08:27:54.20#ibcon#end of sib2, iclass 5, count 0 2006.161.08:27:54.20#ibcon#*mode == 0, iclass 5, count 0 2006.161.08:27:54.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.161.08:27:54.20#ibcon#[27=USB\r\n] 2006.161.08:27:54.20#ibcon#*before write, iclass 5, count 0 2006.161.08:27:54.20#ibcon#enter sib2, iclass 5, count 0 2006.161.08:27:54.20#ibcon#flushed, iclass 5, count 0 2006.161.08:27:54.20#ibcon#about to write, iclass 5, count 0 2006.161.08:27:54.20#ibcon#wrote, iclass 5, count 0 2006.161.08:27:54.20#ibcon#about to read 3, iclass 5, count 0 2006.161.08:27:54.23#ibcon#read 3, iclass 5, count 0 2006.161.08:27:54.23#ibcon#about to read 4, iclass 5, count 0 2006.161.08:27:54.23#ibcon#read 4, iclass 5, count 0 2006.161.08:27:54.23#ibcon#about to read 5, iclass 5, count 0 2006.161.08:27:54.23#ibcon#read 5, iclass 5, count 0 2006.161.08:27:54.23#ibcon#about to read 6, iclass 5, count 0 2006.161.08:27:54.23#ibcon#read 6, iclass 5, count 0 2006.161.08:27:54.23#ibcon#end of sib2, iclass 5, count 0 2006.161.08:27:54.23#ibcon#*after write, iclass 5, count 0 2006.161.08:27:54.23#ibcon#*before return 0, iclass 5, count 0 2006.161.08:27:54.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:54.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.161.08:27:54.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.161.08:27:54.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.161.08:27:54.23$vc4f8/vabw=wide 2006.161.08:27:54.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.161.08:27:54.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.161.08:27:54.23#ibcon#ireg 8 cls_cnt 0 2006.161.08:27:54.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:54.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:54.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:54.23#ibcon#enter wrdev, iclass 7, count 0 2006.161.08:27:54.23#ibcon#first serial, iclass 7, count 0 2006.161.08:27:54.23#ibcon#enter sib2, iclass 7, count 0 2006.161.08:27:54.23#ibcon#flushed, iclass 7, count 0 2006.161.08:27:54.23#ibcon#about to write, iclass 7, count 0 2006.161.08:27:54.23#ibcon#wrote, iclass 7, count 0 2006.161.08:27:54.23#ibcon#about to read 3, iclass 7, count 0 2006.161.08:27:54.25#ibcon#read 3, iclass 7, count 0 2006.161.08:27:54.25#ibcon#about to read 4, iclass 7, count 0 2006.161.08:27:54.25#ibcon#read 4, iclass 7, count 0 2006.161.08:27:54.25#ibcon#about to read 5, iclass 7, count 0 2006.161.08:27:54.25#ibcon#read 5, iclass 7, count 0 2006.161.08:27:54.25#ibcon#about to read 6, iclass 7, count 0 2006.161.08:27:54.25#ibcon#read 6, iclass 7, count 0 2006.161.08:27:54.25#ibcon#end of sib2, iclass 7, count 0 2006.161.08:27:54.25#ibcon#*mode == 0, iclass 7, count 0 2006.161.08:27:54.25#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.161.08:27:54.25#ibcon#[25=BW32\r\n] 2006.161.08:27:54.25#ibcon#*before write, iclass 7, count 0 2006.161.08:27:54.25#ibcon#enter sib2, iclass 7, count 0 2006.161.08:27:54.25#ibcon#flushed, iclass 7, count 0 2006.161.08:27:54.25#ibcon#about to write, iclass 7, count 0 2006.161.08:27:54.25#ibcon#wrote, iclass 7, count 0 2006.161.08:27:54.25#ibcon#about to read 3, iclass 7, count 0 2006.161.08:27:54.28#ibcon#read 3, iclass 7, count 0 2006.161.08:27:54.28#ibcon#about to read 4, iclass 7, count 0 2006.161.08:27:54.28#ibcon#read 4, iclass 7, count 0 2006.161.08:27:54.28#ibcon#about to read 5, iclass 7, count 0 2006.161.08:27:54.28#ibcon#read 5, iclass 7, count 0 2006.161.08:27:54.28#ibcon#about to read 6, iclass 7, count 0 2006.161.08:27:54.28#ibcon#read 6, iclass 7, count 0 2006.161.08:27:54.28#ibcon#end of sib2, iclass 7, count 0 2006.161.08:27:54.28#ibcon#*after write, iclass 7, count 0 2006.161.08:27:54.28#ibcon#*before return 0, iclass 7, count 0 2006.161.08:27:54.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:54.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.161.08:27:54.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.161.08:27:54.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.161.08:27:54.28$vc4f8/vbbw=wide 2006.161.08:27:54.28#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.161.08:27:54.28#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.161.08:27:54.28#ibcon#ireg 8 cls_cnt 0 2006.161.08:27:54.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:27:54.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:27:54.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:27:54.35#ibcon#enter wrdev, iclass 11, count 0 2006.161.08:27:54.35#ibcon#first serial, iclass 11, count 0 2006.161.08:27:54.35#ibcon#enter sib2, iclass 11, count 0 2006.161.08:27:54.35#ibcon#flushed, iclass 11, count 0 2006.161.08:27:54.35#ibcon#about to write, iclass 11, count 0 2006.161.08:27:54.35#ibcon#wrote, iclass 11, count 0 2006.161.08:27:54.35#ibcon#about to read 3, iclass 11, count 0 2006.161.08:27:54.37#ibcon#read 3, iclass 11, count 0 2006.161.08:27:54.37#ibcon#about to read 4, iclass 11, count 0 2006.161.08:27:54.37#ibcon#read 4, iclass 11, count 0 2006.161.08:27:54.37#ibcon#about to read 5, iclass 11, count 0 2006.161.08:27:54.37#ibcon#read 5, iclass 11, count 0 2006.161.08:27:54.37#ibcon#about to read 6, iclass 11, count 0 2006.161.08:27:54.37#ibcon#read 6, iclass 11, count 0 2006.161.08:27:54.37#ibcon#end of sib2, iclass 11, count 0 2006.161.08:27:54.37#ibcon#*mode == 0, iclass 11, count 0 2006.161.08:27:54.37#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.161.08:27:54.37#ibcon#[27=BW32\r\n] 2006.161.08:27:54.37#ibcon#*before write, iclass 11, count 0 2006.161.08:27:54.37#ibcon#enter sib2, iclass 11, count 0 2006.161.08:27:54.37#ibcon#flushed, iclass 11, count 0 2006.161.08:27:54.37#ibcon#about to write, iclass 11, count 0 2006.161.08:27:54.37#ibcon#wrote, iclass 11, count 0 2006.161.08:27:54.37#ibcon#about to read 3, iclass 11, count 0 2006.161.08:27:54.40#ibcon#read 3, iclass 11, count 0 2006.161.08:27:54.40#ibcon#about to read 4, iclass 11, count 0 2006.161.08:27:54.40#ibcon#read 4, iclass 11, count 0 2006.161.08:27:54.40#ibcon#about to read 5, iclass 11, count 0 2006.161.08:27:54.40#ibcon#read 5, iclass 11, count 0 2006.161.08:27:54.40#ibcon#about to read 6, iclass 11, count 0 2006.161.08:27:54.40#ibcon#read 6, iclass 11, count 0 2006.161.08:27:54.40#ibcon#end of sib2, iclass 11, count 0 2006.161.08:27:54.40#ibcon#*after write, iclass 11, count 0 2006.161.08:27:54.40#ibcon#*before return 0, iclass 11, count 0 2006.161.08:27:54.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:27:54.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.161.08:27:54.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.161.08:27:54.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.161.08:27:54.40$4f8m12a/ifd4f 2006.161.08:27:54.40$ifd4f/lo= 2006.161.08:27:54.40$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:27:54.40$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:27:54.40$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:27:54.40$ifd4f/patch= 2006.161.08:27:54.40$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:27:54.40$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:27:54.40$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:27:54.40$4f8m12a/"form=m,16.000,1:2 2006.161.08:27:54.40$4f8m12a/"tpicd 2006.161.08:27:54.40$4f8m12a/echo=off 2006.161.08:27:54.40$4f8m12a/xlog=off 2006.161.08:27:54.40:!2006.161.08:28:30 2006.161.08:28:06.14#trakl#Source acquired 2006.161.08:28:08.14#flagr#flagr/antenna,acquired 2006.161.08:28:30.00:preob 2006.161.08:28:30.14/onsource/TRACKING 2006.161.08:28:30.14:!2006.161.08:28:40 2006.161.08:28:40.00:data_valid=on 2006.161.08:28:40.00:midob 2006.161.08:28:41.14/onsource/TRACKING 2006.161.08:28:41.14/wx/23.97,1002.6,87 2006.161.08:28:41.28/cable/+6.5014E-03 2006.161.08:28:42.37/va/01,08,usb,yes,29,31 2006.161.08:28:42.37/va/02,07,usb,yes,30,31 2006.161.08:28:42.37/va/03,06,usb,yes,31,31 2006.161.08:28:42.37/va/04,07,usb,yes,30,33 2006.161.08:28:42.37/va/05,07,usb,yes,31,32 2006.161.08:28:42.37/va/06,06,usb,yes,30,29 2006.161.08:28:42.37/va/07,06,usb,yes,30,30 2006.161.08:28:42.37/va/08,07,usb,yes,28,28 2006.161.08:28:42.60/valo/01,532.99,yes,locked 2006.161.08:28:42.60/valo/02,572.99,yes,locked 2006.161.08:28:42.60/valo/03,672.99,yes,locked 2006.161.08:28:42.60/valo/04,832.99,yes,locked 2006.161.08:28:42.60/valo/05,652.99,yes,locked 2006.161.08:28:42.60/valo/06,772.99,yes,locked 2006.161.08:28:42.60/valo/07,832.99,yes,locked 2006.161.08:28:42.60/valo/08,852.99,yes,locked 2006.161.08:28:43.69/vb/01,04,usb,yes,29,28 2006.161.08:28:43.69/vb/02,04,usb,yes,31,33 2006.161.08:28:43.69/vb/03,04,usb,yes,28,31 2006.161.08:28:43.69/vb/04,04,usb,yes,29,29 2006.161.08:28:43.69/vb/05,04,usb,yes,27,31 2006.161.08:28:43.69/vb/06,04,usb,yes,28,31 2006.161.08:28:43.69/vb/07,04,usb,yes,30,30 2006.161.08:28:43.69/vb/08,04,usb,yes,28,31 2006.161.08:28:43.93/vblo/01,632.99,yes,locked 2006.161.08:28:43.93/vblo/02,640.99,yes,locked 2006.161.08:28:43.93/vblo/03,656.99,yes,locked 2006.161.08:28:43.93/vblo/04,712.99,yes,locked 2006.161.08:28:43.93/vblo/05,744.99,yes,locked 2006.161.08:28:43.93/vblo/06,752.99,yes,locked 2006.161.08:28:43.93/vblo/07,734.99,yes,locked 2006.161.08:28:43.93/vblo/08,744.99,yes,locked 2006.161.08:28:44.08/vabw/8 2006.161.08:28:44.23/vbbw/8 2006.161.08:28:44.32/xfe/off,on,14.7 2006.161.08:28:44.70/ifatt/23,28,28,28 2006.161.08:28:45.08/fmout-gps/S +4.52E-07 2006.161.08:28:45.16:!2006.161.08:29:40 2006.161.08:29:40.00:data_valid=off 2006.161.08:29:40.00:postob 2006.161.08:29:40.13/cable/+6.5021E-03 2006.161.08:29:40.13/wx/23.96,1002.6,87 2006.161.08:29:41.08/fmout-gps/S +4.51E-07 2006.161.08:29:41.08:scan_name=161-0830,k06161,60 2006.161.08:29:41.08:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.161.08:29:41.13#flagr#flagr/antenna,new-source 2006.161.08:29:42.13:checkk5 2006.161.08:29:42.57/chk_autoobs//k5ts1/ autoobs is running! 2006.161.08:29:42.96/chk_autoobs//k5ts2/ autoobs is running! 2006.161.08:29:43.39/chk_autoobs//k5ts3/ autoobs is running! 2006.161.08:29:43.81/chk_autoobs//k5ts4/ autoobs is running! 2006.161.08:29:44.21/chk_obsdata//k5ts1/T1610828??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:29:44.82/chk_obsdata//k5ts2/T1610828??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:29:45.41/chk_obsdata//k5ts3/T1610828??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:29:49.82/chk_obsdata//k5ts4/T1610828??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:29:50.57/k5log//k5ts1_log_newline 2006.161.08:29:51.46/k5log//k5ts2_log_newline 2006.161.08:29:52.49/k5log//k5ts3_log_newline 2006.161.08:29:53.28/k5log//k5ts4_log_newline 2006.161.08:29:53.30/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:29:53.30:4f8m12a=3 2006.161.08:29:53.30$4f8m12a/echo=on 2006.161.08:29:53.30$4f8m12a/pcalon 2006.161.08:29:53.30$pcalon/"no phase cal control is implemented here 2006.161.08:29:53.30$4f8m12a/"tpicd=stop 2006.161.08:29:53.30$4f8m12a/vc4f8 2006.161.08:29:53.30$vc4f8/valo=1,532.99 2006.161.08:29:53.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:29:53.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:29:53.30#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:53.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:53.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:53.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:53.30#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:29:53.30#ibcon#first serial, iclass 26, count 0 2006.161.08:29:53.30#ibcon#enter sib2, iclass 26, count 0 2006.161.08:29:53.30#ibcon#flushed, iclass 26, count 0 2006.161.08:29:53.30#ibcon#about to write, iclass 26, count 0 2006.161.08:29:53.30#ibcon#wrote, iclass 26, count 0 2006.161.08:29:53.30#ibcon#about to read 3, iclass 26, count 0 2006.161.08:29:53.32#ibcon#read 3, iclass 26, count 0 2006.161.08:29:53.32#ibcon#about to read 4, iclass 26, count 0 2006.161.08:29:53.32#ibcon#read 4, iclass 26, count 0 2006.161.08:29:53.32#ibcon#about to read 5, iclass 26, count 0 2006.161.08:29:53.32#ibcon#read 5, iclass 26, count 0 2006.161.08:29:53.32#ibcon#about to read 6, iclass 26, count 0 2006.161.08:29:53.32#ibcon#read 6, iclass 26, count 0 2006.161.08:29:53.32#ibcon#end of sib2, iclass 26, count 0 2006.161.08:29:53.32#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:29:53.32#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:29:53.32#ibcon#[26=FRQ=01,532.99\r\n] 2006.161.08:29:53.32#ibcon#*before write, iclass 26, count 0 2006.161.08:29:53.32#ibcon#enter sib2, iclass 26, count 0 2006.161.08:29:53.32#ibcon#flushed, iclass 26, count 0 2006.161.08:29:53.32#ibcon#about to write, iclass 26, count 0 2006.161.08:29:53.32#ibcon#wrote, iclass 26, count 0 2006.161.08:29:53.32#ibcon#about to read 3, iclass 26, count 0 2006.161.08:29:53.37#ibcon#read 3, iclass 26, count 0 2006.161.08:29:53.37#ibcon#about to read 4, iclass 26, count 0 2006.161.08:29:53.37#ibcon#read 4, iclass 26, count 0 2006.161.08:29:53.37#ibcon#about to read 5, iclass 26, count 0 2006.161.08:29:53.37#ibcon#read 5, iclass 26, count 0 2006.161.08:29:53.37#ibcon#about to read 6, iclass 26, count 0 2006.161.08:29:53.37#ibcon#read 6, iclass 26, count 0 2006.161.08:29:53.37#ibcon#end of sib2, iclass 26, count 0 2006.161.08:29:53.37#ibcon#*after write, iclass 26, count 0 2006.161.08:29:53.37#ibcon#*before return 0, iclass 26, count 0 2006.161.08:29:53.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:53.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:53.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:29:53.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:29:53.37$vc4f8/va=1,8 2006.161.08:29:53.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:29:53.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:29:53.37#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:53.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:53.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:53.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:53.37#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:29:53.37#ibcon#first serial, iclass 28, count 2 2006.161.08:29:53.37#ibcon#enter sib2, iclass 28, count 2 2006.161.08:29:53.37#ibcon#flushed, iclass 28, count 2 2006.161.08:29:53.37#ibcon#about to write, iclass 28, count 2 2006.161.08:29:53.37#ibcon#wrote, iclass 28, count 2 2006.161.08:29:53.37#ibcon#about to read 3, iclass 28, count 2 2006.161.08:29:53.39#ibcon#read 3, iclass 28, count 2 2006.161.08:29:53.39#ibcon#about to read 4, iclass 28, count 2 2006.161.08:29:53.39#ibcon#read 4, iclass 28, count 2 2006.161.08:29:53.39#ibcon#about to read 5, iclass 28, count 2 2006.161.08:29:53.39#ibcon#read 5, iclass 28, count 2 2006.161.08:29:53.39#ibcon#about to read 6, iclass 28, count 2 2006.161.08:29:53.39#ibcon#read 6, iclass 28, count 2 2006.161.08:29:53.39#ibcon#end of sib2, iclass 28, count 2 2006.161.08:29:53.39#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:29:53.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:29:53.39#ibcon#[25=AT01-08\r\n] 2006.161.08:29:53.39#ibcon#*before write, iclass 28, count 2 2006.161.08:29:53.39#ibcon#enter sib2, iclass 28, count 2 2006.161.08:29:53.39#ibcon#flushed, iclass 28, count 2 2006.161.08:29:53.39#ibcon#about to write, iclass 28, count 2 2006.161.08:29:53.39#ibcon#wrote, iclass 28, count 2 2006.161.08:29:53.39#ibcon#about to read 3, iclass 28, count 2 2006.161.08:29:53.42#ibcon#read 3, iclass 28, count 2 2006.161.08:29:53.42#ibcon#about to read 4, iclass 28, count 2 2006.161.08:29:53.42#ibcon#read 4, iclass 28, count 2 2006.161.08:29:53.42#ibcon#about to read 5, iclass 28, count 2 2006.161.08:29:53.42#ibcon#read 5, iclass 28, count 2 2006.161.08:29:53.42#ibcon#about to read 6, iclass 28, count 2 2006.161.08:29:53.42#ibcon#read 6, iclass 28, count 2 2006.161.08:29:53.42#ibcon#end of sib2, iclass 28, count 2 2006.161.08:29:53.42#ibcon#*after write, iclass 28, count 2 2006.161.08:29:53.42#ibcon#*before return 0, iclass 28, count 2 2006.161.08:29:53.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:53.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:53.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:29:53.42#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:53.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:53.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:53.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:53.54#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:29:53.54#ibcon#first serial, iclass 28, count 0 2006.161.08:29:53.54#ibcon#enter sib2, iclass 28, count 0 2006.161.08:29:53.54#ibcon#flushed, iclass 28, count 0 2006.161.08:29:53.54#ibcon#about to write, iclass 28, count 0 2006.161.08:29:53.54#ibcon#wrote, iclass 28, count 0 2006.161.08:29:53.54#ibcon#about to read 3, iclass 28, count 0 2006.161.08:29:53.56#ibcon#read 3, iclass 28, count 0 2006.161.08:29:53.56#ibcon#about to read 4, iclass 28, count 0 2006.161.08:29:53.56#ibcon#read 4, iclass 28, count 0 2006.161.08:29:53.56#ibcon#about to read 5, iclass 28, count 0 2006.161.08:29:53.56#ibcon#read 5, iclass 28, count 0 2006.161.08:29:53.56#ibcon#about to read 6, iclass 28, count 0 2006.161.08:29:53.56#ibcon#read 6, iclass 28, count 0 2006.161.08:29:53.56#ibcon#end of sib2, iclass 28, count 0 2006.161.08:29:53.56#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:29:53.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:29:53.56#ibcon#[25=USB\r\n] 2006.161.08:29:53.56#ibcon#*before write, iclass 28, count 0 2006.161.08:29:53.56#ibcon#enter sib2, iclass 28, count 0 2006.161.08:29:53.56#ibcon#flushed, iclass 28, count 0 2006.161.08:29:53.56#ibcon#about to write, iclass 28, count 0 2006.161.08:29:53.56#ibcon#wrote, iclass 28, count 0 2006.161.08:29:53.56#ibcon#about to read 3, iclass 28, count 0 2006.161.08:29:53.59#ibcon#read 3, iclass 28, count 0 2006.161.08:29:53.59#ibcon#about to read 4, iclass 28, count 0 2006.161.08:29:53.59#ibcon#read 4, iclass 28, count 0 2006.161.08:29:53.59#ibcon#about to read 5, iclass 28, count 0 2006.161.08:29:53.59#ibcon#read 5, iclass 28, count 0 2006.161.08:29:53.59#ibcon#about to read 6, iclass 28, count 0 2006.161.08:29:53.59#ibcon#read 6, iclass 28, count 0 2006.161.08:29:53.59#ibcon#end of sib2, iclass 28, count 0 2006.161.08:29:53.59#ibcon#*after write, iclass 28, count 0 2006.161.08:29:53.59#ibcon#*before return 0, iclass 28, count 0 2006.161.08:29:53.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:53.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:53.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:29:53.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:29:53.59$vc4f8/valo=2,572.99 2006.161.08:29:53.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:29:53.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:29:53.59#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:53.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:53.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:53.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:53.59#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:29:53.59#ibcon#first serial, iclass 30, count 0 2006.161.08:29:53.59#ibcon#enter sib2, iclass 30, count 0 2006.161.08:29:53.59#ibcon#flushed, iclass 30, count 0 2006.161.08:29:53.59#ibcon#about to write, iclass 30, count 0 2006.161.08:29:53.59#ibcon#wrote, iclass 30, count 0 2006.161.08:29:53.59#ibcon#about to read 3, iclass 30, count 0 2006.161.08:29:53.61#ibcon#read 3, iclass 30, count 0 2006.161.08:29:53.61#ibcon#about to read 4, iclass 30, count 0 2006.161.08:29:53.61#ibcon#read 4, iclass 30, count 0 2006.161.08:29:53.61#ibcon#about to read 5, iclass 30, count 0 2006.161.08:29:53.61#ibcon#read 5, iclass 30, count 0 2006.161.08:29:53.61#ibcon#about to read 6, iclass 30, count 0 2006.161.08:29:53.61#ibcon#read 6, iclass 30, count 0 2006.161.08:29:53.61#ibcon#end of sib2, iclass 30, count 0 2006.161.08:29:53.61#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:29:53.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:29:53.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.161.08:29:53.61#ibcon#*before write, iclass 30, count 0 2006.161.08:29:53.61#ibcon#enter sib2, iclass 30, count 0 2006.161.08:29:53.61#ibcon#flushed, iclass 30, count 0 2006.161.08:29:53.61#ibcon#about to write, iclass 30, count 0 2006.161.08:29:53.61#ibcon#wrote, iclass 30, count 0 2006.161.08:29:53.61#ibcon#about to read 3, iclass 30, count 0 2006.161.08:29:53.65#ibcon#read 3, iclass 30, count 0 2006.161.08:29:53.65#ibcon#about to read 4, iclass 30, count 0 2006.161.08:29:53.65#ibcon#read 4, iclass 30, count 0 2006.161.08:29:53.65#ibcon#about to read 5, iclass 30, count 0 2006.161.08:29:53.65#ibcon#read 5, iclass 30, count 0 2006.161.08:29:53.65#ibcon#about to read 6, iclass 30, count 0 2006.161.08:29:53.65#ibcon#read 6, iclass 30, count 0 2006.161.08:29:53.65#ibcon#end of sib2, iclass 30, count 0 2006.161.08:29:53.65#ibcon#*after write, iclass 30, count 0 2006.161.08:29:53.65#ibcon#*before return 0, iclass 30, count 0 2006.161.08:29:53.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:53.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:53.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:29:53.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:29:53.65$vc4f8/va=2,7 2006.161.08:29:53.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:29:53.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:29:53.65#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:53.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:53.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:53.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:53.71#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:29:53.71#ibcon#first serial, iclass 32, count 2 2006.161.08:29:53.71#ibcon#enter sib2, iclass 32, count 2 2006.161.08:29:53.71#ibcon#flushed, iclass 32, count 2 2006.161.08:29:53.71#ibcon#about to write, iclass 32, count 2 2006.161.08:29:53.71#ibcon#wrote, iclass 32, count 2 2006.161.08:29:53.71#ibcon#about to read 3, iclass 32, count 2 2006.161.08:29:53.73#ibcon#read 3, iclass 32, count 2 2006.161.08:29:53.73#ibcon#about to read 4, iclass 32, count 2 2006.161.08:29:53.73#ibcon#read 4, iclass 32, count 2 2006.161.08:29:53.73#ibcon#about to read 5, iclass 32, count 2 2006.161.08:29:53.73#ibcon#read 5, iclass 32, count 2 2006.161.08:29:53.73#ibcon#about to read 6, iclass 32, count 2 2006.161.08:29:53.73#ibcon#read 6, iclass 32, count 2 2006.161.08:29:53.73#ibcon#end of sib2, iclass 32, count 2 2006.161.08:29:53.73#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:29:53.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:29:53.73#ibcon#[25=AT02-07\r\n] 2006.161.08:29:53.73#ibcon#*before write, iclass 32, count 2 2006.161.08:29:53.73#ibcon#enter sib2, iclass 32, count 2 2006.161.08:29:53.73#ibcon#flushed, iclass 32, count 2 2006.161.08:29:53.73#ibcon#about to write, iclass 32, count 2 2006.161.08:29:53.73#ibcon#wrote, iclass 32, count 2 2006.161.08:29:53.73#ibcon#about to read 3, iclass 32, count 2 2006.161.08:29:53.77#ibcon#read 3, iclass 32, count 2 2006.161.08:29:53.77#ibcon#about to read 4, iclass 32, count 2 2006.161.08:29:53.77#ibcon#read 4, iclass 32, count 2 2006.161.08:29:53.77#ibcon#about to read 5, iclass 32, count 2 2006.161.08:29:53.77#ibcon#read 5, iclass 32, count 2 2006.161.08:29:53.77#ibcon#about to read 6, iclass 32, count 2 2006.161.08:29:53.77#ibcon#read 6, iclass 32, count 2 2006.161.08:29:53.77#ibcon#end of sib2, iclass 32, count 2 2006.161.08:29:53.77#ibcon#*after write, iclass 32, count 2 2006.161.08:29:53.77#ibcon#*before return 0, iclass 32, count 2 2006.161.08:29:53.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:53.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:53.77#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:29:53.77#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:53.77#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:53.89#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:53.89#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:53.89#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:29:53.89#ibcon#first serial, iclass 32, count 0 2006.161.08:29:53.89#ibcon#enter sib2, iclass 32, count 0 2006.161.08:29:53.89#ibcon#flushed, iclass 32, count 0 2006.161.08:29:53.89#ibcon#about to write, iclass 32, count 0 2006.161.08:29:53.89#ibcon#wrote, iclass 32, count 0 2006.161.08:29:53.89#ibcon#about to read 3, iclass 32, count 0 2006.161.08:29:53.91#ibcon#read 3, iclass 32, count 0 2006.161.08:29:53.91#ibcon#about to read 4, iclass 32, count 0 2006.161.08:29:53.91#ibcon#read 4, iclass 32, count 0 2006.161.08:29:53.91#ibcon#about to read 5, iclass 32, count 0 2006.161.08:29:53.91#ibcon#read 5, iclass 32, count 0 2006.161.08:29:53.91#ibcon#about to read 6, iclass 32, count 0 2006.161.08:29:53.91#ibcon#read 6, iclass 32, count 0 2006.161.08:29:53.91#ibcon#end of sib2, iclass 32, count 0 2006.161.08:29:53.91#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:29:53.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:29:53.91#ibcon#[25=USB\r\n] 2006.161.08:29:53.91#ibcon#*before write, iclass 32, count 0 2006.161.08:29:53.91#ibcon#enter sib2, iclass 32, count 0 2006.161.08:29:53.91#ibcon#flushed, iclass 32, count 0 2006.161.08:29:53.91#ibcon#about to write, iclass 32, count 0 2006.161.08:29:53.91#ibcon#wrote, iclass 32, count 0 2006.161.08:29:53.91#ibcon#about to read 3, iclass 32, count 0 2006.161.08:29:53.94#ibcon#read 3, iclass 32, count 0 2006.161.08:29:53.94#ibcon#about to read 4, iclass 32, count 0 2006.161.08:29:53.94#ibcon#read 4, iclass 32, count 0 2006.161.08:29:53.94#ibcon#about to read 5, iclass 32, count 0 2006.161.08:29:53.94#ibcon#read 5, iclass 32, count 0 2006.161.08:29:53.94#ibcon#about to read 6, iclass 32, count 0 2006.161.08:29:53.94#ibcon#read 6, iclass 32, count 0 2006.161.08:29:53.94#ibcon#end of sib2, iclass 32, count 0 2006.161.08:29:53.94#ibcon#*after write, iclass 32, count 0 2006.161.08:29:53.94#ibcon#*before return 0, iclass 32, count 0 2006.161.08:29:53.94#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:53.94#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:53.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:29:53.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:29:53.94$vc4f8/valo=3,672.99 2006.161.08:29:53.94#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:29:53.94#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:29:53.94#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:53.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:53.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:53.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:53.94#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:29:53.94#ibcon#first serial, iclass 34, count 0 2006.161.08:29:53.94#ibcon#enter sib2, iclass 34, count 0 2006.161.08:29:53.94#ibcon#flushed, iclass 34, count 0 2006.161.08:29:53.94#ibcon#about to write, iclass 34, count 0 2006.161.08:29:53.94#ibcon#wrote, iclass 34, count 0 2006.161.08:29:53.94#ibcon#about to read 3, iclass 34, count 0 2006.161.08:29:53.96#ibcon#read 3, iclass 34, count 0 2006.161.08:29:53.96#ibcon#about to read 4, iclass 34, count 0 2006.161.08:29:53.96#ibcon#read 4, iclass 34, count 0 2006.161.08:29:53.96#ibcon#about to read 5, iclass 34, count 0 2006.161.08:29:53.96#ibcon#read 5, iclass 34, count 0 2006.161.08:29:53.96#ibcon#about to read 6, iclass 34, count 0 2006.161.08:29:53.96#ibcon#read 6, iclass 34, count 0 2006.161.08:29:53.96#ibcon#end of sib2, iclass 34, count 0 2006.161.08:29:53.96#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:29:53.96#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:29:53.96#ibcon#[26=FRQ=03,672.99\r\n] 2006.161.08:29:53.96#ibcon#*before write, iclass 34, count 0 2006.161.08:29:53.96#ibcon#enter sib2, iclass 34, count 0 2006.161.08:29:53.96#ibcon#flushed, iclass 34, count 0 2006.161.08:29:53.96#ibcon#about to write, iclass 34, count 0 2006.161.08:29:53.96#ibcon#wrote, iclass 34, count 0 2006.161.08:29:53.96#ibcon#about to read 3, iclass 34, count 0 2006.161.08:29:54.01#ibcon#read 3, iclass 34, count 0 2006.161.08:29:54.01#ibcon#about to read 4, iclass 34, count 0 2006.161.08:29:54.01#ibcon#read 4, iclass 34, count 0 2006.161.08:29:54.01#ibcon#about to read 5, iclass 34, count 0 2006.161.08:29:54.01#ibcon#read 5, iclass 34, count 0 2006.161.08:29:54.01#ibcon#about to read 6, iclass 34, count 0 2006.161.08:29:54.01#ibcon#read 6, iclass 34, count 0 2006.161.08:29:54.01#ibcon#end of sib2, iclass 34, count 0 2006.161.08:29:54.01#ibcon#*after write, iclass 34, count 0 2006.161.08:29:54.01#ibcon#*before return 0, iclass 34, count 0 2006.161.08:29:54.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:54.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:54.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:29:54.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:29:54.01$vc4f8/va=3,6 2006.161.08:29:54.01#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:29:54.01#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:29:54.01#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:54.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:54.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:54.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:54.06#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:29:54.06#ibcon#first serial, iclass 36, count 2 2006.161.08:29:54.06#ibcon#enter sib2, iclass 36, count 2 2006.161.08:29:54.06#ibcon#flushed, iclass 36, count 2 2006.161.08:29:54.06#ibcon#about to write, iclass 36, count 2 2006.161.08:29:54.06#ibcon#wrote, iclass 36, count 2 2006.161.08:29:54.06#ibcon#about to read 3, iclass 36, count 2 2006.161.08:29:54.08#ibcon#read 3, iclass 36, count 2 2006.161.08:29:54.08#ibcon#about to read 4, iclass 36, count 2 2006.161.08:29:54.08#ibcon#read 4, iclass 36, count 2 2006.161.08:29:54.08#ibcon#about to read 5, iclass 36, count 2 2006.161.08:29:54.08#ibcon#read 5, iclass 36, count 2 2006.161.08:29:54.08#ibcon#about to read 6, iclass 36, count 2 2006.161.08:29:54.08#ibcon#read 6, iclass 36, count 2 2006.161.08:29:54.08#ibcon#end of sib2, iclass 36, count 2 2006.161.08:29:54.08#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:29:54.08#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:29:54.08#ibcon#[25=AT03-06\r\n] 2006.161.08:29:54.08#ibcon#*before write, iclass 36, count 2 2006.161.08:29:54.08#ibcon#enter sib2, iclass 36, count 2 2006.161.08:29:54.08#ibcon#flushed, iclass 36, count 2 2006.161.08:29:54.08#ibcon#about to write, iclass 36, count 2 2006.161.08:29:54.08#ibcon#wrote, iclass 36, count 2 2006.161.08:29:54.08#ibcon#about to read 3, iclass 36, count 2 2006.161.08:29:54.12#ibcon#read 3, iclass 36, count 2 2006.161.08:29:54.12#ibcon#about to read 4, iclass 36, count 2 2006.161.08:29:54.12#ibcon#read 4, iclass 36, count 2 2006.161.08:29:54.12#ibcon#about to read 5, iclass 36, count 2 2006.161.08:29:54.12#ibcon#read 5, iclass 36, count 2 2006.161.08:29:54.12#ibcon#about to read 6, iclass 36, count 2 2006.161.08:29:54.12#ibcon#read 6, iclass 36, count 2 2006.161.08:29:54.12#ibcon#end of sib2, iclass 36, count 2 2006.161.08:29:54.12#ibcon#*after write, iclass 36, count 2 2006.161.08:29:54.12#ibcon#*before return 0, iclass 36, count 2 2006.161.08:29:54.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:54.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:54.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:29:54.12#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:54.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:54.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:54.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:54.24#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:29:54.24#ibcon#first serial, iclass 36, count 0 2006.161.08:29:54.24#ibcon#enter sib2, iclass 36, count 0 2006.161.08:29:54.24#ibcon#flushed, iclass 36, count 0 2006.161.08:29:54.24#ibcon#about to write, iclass 36, count 0 2006.161.08:29:54.24#ibcon#wrote, iclass 36, count 0 2006.161.08:29:54.24#ibcon#about to read 3, iclass 36, count 0 2006.161.08:29:54.26#ibcon#read 3, iclass 36, count 0 2006.161.08:29:54.26#ibcon#about to read 4, iclass 36, count 0 2006.161.08:29:54.26#ibcon#read 4, iclass 36, count 0 2006.161.08:29:54.26#ibcon#about to read 5, iclass 36, count 0 2006.161.08:29:54.26#ibcon#read 5, iclass 36, count 0 2006.161.08:29:54.26#ibcon#about to read 6, iclass 36, count 0 2006.161.08:29:54.26#ibcon#read 6, iclass 36, count 0 2006.161.08:29:54.26#ibcon#end of sib2, iclass 36, count 0 2006.161.08:29:54.26#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:29:54.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:29:54.26#ibcon#[25=USB\r\n] 2006.161.08:29:54.26#ibcon#*before write, iclass 36, count 0 2006.161.08:29:54.26#ibcon#enter sib2, iclass 36, count 0 2006.161.08:29:54.26#ibcon#flushed, iclass 36, count 0 2006.161.08:29:54.26#ibcon#about to write, iclass 36, count 0 2006.161.08:29:54.26#ibcon#wrote, iclass 36, count 0 2006.161.08:29:54.26#ibcon#about to read 3, iclass 36, count 0 2006.161.08:29:54.29#ibcon#read 3, iclass 36, count 0 2006.161.08:29:54.29#ibcon#about to read 4, iclass 36, count 0 2006.161.08:29:54.29#ibcon#read 4, iclass 36, count 0 2006.161.08:29:54.29#ibcon#about to read 5, iclass 36, count 0 2006.161.08:29:54.29#ibcon#read 5, iclass 36, count 0 2006.161.08:29:54.29#ibcon#about to read 6, iclass 36, count 0 2006.161.08:29:54.29#ibcon#read 6, iclass 36, count 0 2006.161.08:29:54.29#ibcon#end of sib2, iclass 36, count 0 2006.161.08:29:54.29#ibcon#*after write, iclass 36, count 0 2006.161.08:29:54.29#ibcon#*before return 0, iclass 36, count 0 2006.161.08:29:54.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:54.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:54.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:29:54.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:29:54.29$vc4f8/valo=4,832.99 2006.161.08:29:54.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:29:54.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:29:54.29#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:54.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:54.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:54.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:54.29#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:29:54.29#ibcon#first serial, iclass 38, count 0 2006.161.08:29:54.29#ibcon#enter sib2, iclass 38, count 0 2006.161.08:29:54.29#ibcon#flushed, iclass 38, count 0 2006.161.08:29:54.29#ibcon#about to write, iclass 38, count 0 2006.161.08:29:54.29#ibcon#wrote, iclass 38, count 0 2006.161.08:29:54.29#ibcon#about to read 3, iclass 38, count 0 2006.161.08:29:54.31#ibcon#read 3, iclass 38, count 0 2006.161.08:29:54.31#ibcon#about to read 4, iclass 38, count 0 2006.161.08:29:54.31#ibcon#read 4, iclass 38, count 0 2006.161.08:29:54.31#ibcon#about to read 5, iclass 38, count 0 2006.161.08:29:54.31#ibcon#read 5, iclass 38, count 0 2006.161.08:29:54.31#ibcon#about to read 6, iclass 38, count 0 2006.161.08:29:54.31#ibcon#read 6, iclass 38, count 0 2006.161.08:29:54.31#ibcon#end of sib2, iclass 38, count 0 2006.161.08:29:54.31#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:29:54.31#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:29:54.31#ibcon#[26=FRQ=04,832.99\r\n] 2006.161.08:29:54.31#ibcon#*before write, iclass 38, count 0 2006.161.08:29:54.31#ibcon#enter sib2, iclass 38, count 0 2006.161.08:29:54.31#ibcon#flushed, iclass 38, count 0 2006.161.08:29:54.31#ibcon#about to write, iclass 38, count 0 2006.161.08:29:54.31#ibcon#wrote, iclass 38, count 0 2006.161.08:29:54.31#ibcon#about to read 3, iclass 38, count 0 2006.161.08:29:54.35#ibcon#read 3, iclass 38, count 0 2006.161.08:29:54.35#ibcon#about to read 4, iclass 38, count 0 2006.161.08:29:54.35#ibcon#read 4, iclass 38, count 0 2006.161.08:29:54.35#ibcon#about to read 5, iclass 38, count 0 2006.161.08:29:54.35#ibcon#read 5, iclass 38, count 0 2006.161.08:29:54.35#ibcon#about to read 6, iclass 38, count 0 2006.161.08:29:54.35#ibcon#read 6, iclass 38, count 0 2006.161.08:29:54.35#ibcon#end of sib2, iclass 38, count 0 2006.161.08:29:54.35#ibcon#*after write, iclass 38, count 0 2006.161.08:29:54.35#ibcon#*before return 0, iclass 38, count 0 2006.161.08:29:54.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:54.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:54.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:29:54.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:29:54.35$vc4f8/va=4,7 2006.161.08:29:54.35#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:29:54.35#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:29:54.35#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:54.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:54.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:54.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:54.41#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:29:54.41#ibcon#first serial, iclass 40, count 2 2006.161.08:29:54.41#ibcon#enter sib2, iclass 40, count 2 2006.161.08:29:54.41#ibcon#flushed, iclass 40, count 2 2006.161.08:29:54.41#ibcon#about to write, iclass 40, count 2 2006.161.08:29:54.41#ibcon#wrote, iclass 40, count 2 2006.161.08:29:54.41#ibcon#about to read 3, iclass 40, count 2 2006.161.08:29:54.43#ibcon#read 3, iclass 40, count 2 2006.161.08:29:54.43#ibcon#about to read 4, iclass 40, count 2 2006.161.08:29:54.43#ibcon#read 4, iclass 40, count 2 2006.161.08:29:54.43#ibcon#about to read 5, iclass 40, count 2 2006.161.08:29:54.43#ibcon#read 5, iclass 40, count 2 2006.161.08:29:54.43#ibcon#about to read 6, iclass 40, count 2 2006.161.08:29:54.43#ibcon#read 6, iclass 40, count 2 2006.161.08:29:54.43#ibcon#end of sib2, iclass 40, count 2 2006.161.08:29:54.43#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:29:54.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:29:54.43#ibcon#[25=AT04-07\r\n] 2006.161.08:29:54.43#ibcon#*before write, iclass 40, count 2 2006.161.08:29:54.43#ibcon#enter sib2, iclass 40, count 2 2006.161.08:29:54.43#ibcon#flushed, iclass 40, count 2 2006.161.08:29:54.43#ibcon#about to write, iclass 40, count 2 2006.161.08:29:54.43#ibcon#wrote, iclass 40, count 2 2006.161.08:29:54.43#ibcon#about to read 3, iclass 40, count 2 2006.161.08:29:54.46#ibcon#read 3, iclass 40, count 2 2006.161.08:29:54.46#ibcon#about to read 4, iclass 40, count 2 2006.161.08:29:54.46#ibcon#read 4, iclass 40, count 2 2006.161.08:29:54.46#ibcon#about to read 5, iclass 40, count 2 2006.161.08:29:54.46#ibcon#read 5, iclass 40, count 2 2006.161.08:29:54.46#ibcon#about to read 6, iclass 40, count 2 2006.161.08:29:54.46#ibcon#read 6, iclass 40, count 2 2006.161.08:29:54.46#ibcon#end of sib2, iclass 40, count 2 2006.161.08:29:54.46#ibcon#*after write, iclass 40, count 2 2006.161.08:29:54.46#ibcon#*before return 0, iclass 40, count 2 2006.161.08:29:54.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:54.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:54.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:29:54.46#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:54.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:54.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:54.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:54.58#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:29:54.58#ibcon#first serial, iclass 40, count 0 2006.161.08:29:54.58#ibcon#enter sib2, iclass 40, count 0 2006.161.08:29:54.58#ibcon#flushed, iclass 40, count 0 2006.161.08:29:54.58#ibcon#about to write, iclass 40, count 0 2006.161.08:29:54.58#ibcon#wrote, iclass 40, count 0 2006.161.08:29:54.58#ibcon#about to read 3, iclass 40, count 0 2006.161.08:29:54.60#ibcon#read 3, iclass 40, count 0 2006.161.08:29:54.60#ibcon#about to read 4, iclass 40, count 0 2006.161.08:29:54.60#ibcon#read 4, iclass 40, count 0 2006.161.08:29:54.60#ibcon#about to read 5, iclass 40, count 0 2006.161.08:29:54.60#ibcon#read 5, iclass 40, count 0 2006.161.08:29:54.60#ibcon#about to read 6, iclass 40, count 0 2006.161.08:29:54.60#ibcon#read 6, iclass 40, count 0 2006.161.08:29:54.60#ibcon#end of sib2, iclass 40, count 0 2006.161.08:29:54.60#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:29:54.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:29:54.60#ibcon#[25=USB\r\n] 2006.161.08:29:54.60#ibcon#*before write, iclass 40, count 0 2006.161.08:29:54.60#ibcon#enter sib2, iclass 40, count 0 2006.161.08:29:54.60#ibcon#flushed, iclass 40, count 0 2006.161.08:29:54.60#ibcon#about to write, iclass 40, count 0 2006.161.08:29:54.60#ibcon#wrote, iclass 40, count 0 2006.161.08:29:54.60#ibcon#about to read 3, iclass 40, count 0 2006.161.08:29:54.63#ibcon#read 3, iclass 40, count 0 2006.161.08:29:54.63#ibcon#about to read 4, iclass 40, count 0 2006.161.08:29:54.63#ibcon#read 4, iclass 40, count 0 2006.161.08:29:54.63#ibcon#about to read 5, iclass 40, count 0 2006.161.08:29:54.63#ibcon#read 5, iclass 40, count 0 2006.161.08:29:54.63#ibcon#about to read 6, iclass 40, count 0 2006.161.08:29:54.63#ibcon#read 6, iclass 40, count 0 2006.161.08:29:54.63#ibcon#end of sib2, iclass 40, count 0 2006.161.08:29:54.63#ibcon#*after write, iclass 40, count 0 2006.161.08:29:54.63#ibcon#*before return 0, iclass 40, count 0 2006.161.08:29:54.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:54.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:54.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:29:54.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:29:54.63$vc4f8/valo=5,652.99 2006.161.08:29:54.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:29:54.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:29:54.63#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:54.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:54.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:54.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:54.63#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:29:54.63#ibcon#first serial, iclass 4, count 0 2006.161.08:29:54.63#ibcon#enter sib2, iclass 4, count 0 2006.161.08:29:54.63#ibcon#flushed, iclass 4, count 0 2006.161.08:29:54.63#ibcon#about to write, iclass 4, count 0 2006.161.08:29:54.63#ibcon#wrote, iclass 4, count 0 2006.161.08:29:54.63#ibcon#about to read 3, iclass 4, count 0 2006.161.08:29:54.65#ibcon#read 3, iclass 4, count 0 2006.161.08:29:54.65#ibcon#about to read 4, iclass 4, count 0 2006.161.08:29:54.65#ibcon#read 4, iclass 4, count 0 2006.161.08:29:54.65#ibcon#about to read 5, iclass 4, count 0 2006.161.08:29:54.65#ibcon#read 5, iclass 4, count 0 2006.161.08:29:54.65#ibcon#about to read 6, iclass 4, count 0 2006.161.08:29:54.65#ibcon#read 6, iclass 4, count 0 2006.161.08:29:54.65#ibcon#end of sib2, iclass 4, count 0 2006.161.08:29:54.65#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:29:54.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:29:54.65#ibcon#[26=FRQ=05,652.99\r\n] 2006.161.08:29:54.65#ibcon#*before write, iclass 4, count 0 2006.161.08:29:54.65#ibcon#enter sib2, iclass 4, count 0 2006.161.08:29:54.65#ibcon#flushed, iclass 4, count 0 2006.161.08:29:54.65#ibcon#about to write, iclass 4, count 0 2006.161.08:29:54.65#ibcon#wrote, iclass 4, count 0 2006.161.08:29:54.65#ibcon#about to read 3, iclass 4, count 0 2006.161.08:29:54.69#ibcon#read 3, iclass 4, count 0 2006.161.08:29:54.69#ibcon#about to read 4, iclass 4, count 0 2006.161.08:29:54.69#ibcon#read 4, iclass 4, count 0 2006.161.08:29:54.69#ibcon#about to read 5, iclass 4, count 0 2006.161.08:29:54.69#ibcon#read 5, iclass 4, count 0 2006.161.08:29:54.69#ibcon#about to read 6, iclass 4, count 0 2006.161.08:29:54.69#ibcon#read 6, iclass 4, count 0 2006.161.08:29:54.69#ibcon#end of sib2, iclass 4, count 0 2006.161.08:29:54.69#ibcon#*after write, iclass 4, count 0 2006.161.08:29:54.69#ibcon#*before return 0, iclass 4, count 0 2006.161.08:29:54.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:54.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:54.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:29:54.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:29:54.69$vc4f8/va=5,7 2006.161.08:29:54.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:29:54.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:29:54.69#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:54.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:54.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:54.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:54.75#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:29:54.75#ibcon#first serial, iclass 6, count 2 2006.161.08:29:54.75#ibcon#enter sib2, iclass 6, count 2 2006.161.08:29:54.75#ibcon#flushed, iclass 6, count 2 2006.161.08:29:54.75#ibcon#about to write, iclass 6, count 2 2006.161.08:29:54.75#ibcon#wrote, iclass 6, count 2 2006.161.08:29:54.75#ibcon#about to read 3, iclass 6, count 2 2006.161.08:29:54.77#ibcon#read 3, iclass 6, count 2 2006.161.08:29:54.77#ibcon#about to read 4, iclass 6, count 2 2006.161.08:29:54.77#ibcon#read 4, iclass 6, count 2 2006.161.08:29:54.77#ibcon#about to read 5, iclass 6, count 2 2006.161.08:29:54.77#ibcon#read 5, iclass 6, count 2 2006.161.08:29:54.77#ibcon#about to read 6, iclass 6, count 2 2006.161.08:29:54.77#ibcon#read 6, iclass 6, count 2 2006.161.08:29:54.77#ibcon#end of sib2, iclass 6, count 2 2006.161.08:29:54.77#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:29:54.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:29:54.77#ibcon#[25=AT05-07\r\n] 2006.161.08:29:54.77#ibcon#*before write, iclass 6, count 2 2006.161.08:29:54.77#ibcon#enter sib2, iclass 6, count 2 2006.161.08:29:54.77#ibcon#flushed, iclass 6, count 2 2006.161.08:29:54.77#ibcon#about to write, iclass 6, count 2 2006.161.08:29:54.77#ibcon#wrote, iclass 6, count 2 2006.161.08:29:54.77#ibcon#about to read 3, iclass 6, count 2 2006.161.08:29:54.80#ibcon#read 3, iclass 6, count 2 2006.161.08:29:54.80#ibcon#about to read 4, iclass 6, count 2 2006.161.08:29:54.80#ibcon#read 4, iclass 6, count 2 2006.161.08:29:54.80#ibcon#about to read 5, iclass 6, count 2 2006.161.08:29:54.80#ibcon#read 5, iclass 6, count 2 2006.161.08:29:54.80#ibcon#about to read 6, iclass 6, count 2 2006.161.08:29:54.80#ibcon#read 6, iclass 6, count 2 2006.161.08:29:54.80#ibcon#end of sib2, iclass 6, count 2 2006.161.08:29:54.80#ibcon#*after write, iclass 6, count 2 2006.161.08:29:54.80#ibcon#*before return 0, iclass 6, count 2 2006.161.08:29:54.80#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:54.80#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:54.80#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:29:54.80#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:54.80#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:54.92#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:54.92#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:54.92#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:29:54.92#ibcon#first serial, iclass 6, count 0 2006.161.08:29:54.92#ibcon#enter sib2, iclass 6, count 0 2006.161.08:29:54.92#ibcon#flushed, iclass 6, count 0 2006.161.08:29:54.92#ibcon#about to write, iclass 6, count 0 2006.161.08:29:54.92#ibcon#wrote, iclass 6, count 0 2006.161.08:29:54.92#ibcon#about to read 3, iclass 6, count 0 2006.161.08:29:54.94#ibcon#read 3, iclass 6, count 0 2006.161.08:29:54.94#ibcon#about to read 4, iclass 6, count 0 2006.161.08:29:54.94#ibcon#read 4, iclass 6, count 0 2006.161.08:29:54.94#ibcon#about to read 5, iclass 6, count 0 2006.161.08:29:54.94#ibcon#read 5, iclass 6, count 0 2006.161.08:29:54.94#ibcon#about to read 6, iclass 6, count 0 2006.161.08:29:54.94#ibcon#read 6, iclass 6, count 0 2006.161.08:29:54.94#ibcon#end of sib2, iclass 6, count 0 2006.161.08:29:54.94#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:29:54.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:29:54.94#ibcon#[25=USB\r\n] 2006.161.08:29:54.94#ibcon#*before write, iclass 6, count 0 2006.161.08:29:54.94#ibcon#enter sib2, iclass 6, count 0 2006.161.08:29:54.94#ibcon#flushed, iclass 6, count 0 2006.161.08:29:54.94#ibcon#about to write, iclass 6, count 0 2006.161.08:29:54.94#ibcon#wrote, iclass 6, count 0 2006.161.08:29:54.94#ibcon#about to read 3, iclass 6, count 0 2006.161.08:29:54.97#ibcon#read 3, iclass 6, count 0 2006.161.08:29:54.97#ibcon#about to read 4, iclass 6, count 0 2006.161.08:29:54.97#ibcon#read 4, iclass 6, count 0 2006.161.08:29:54.97#ibcon#about to read 5, iclass 6, count 0 2006.161.08:29:54.97#ibcon#read 5, iclass 6, count 0 2006.161.08:29:54.97#ibcon#about to read 6, iclass 6, count 0 2006.161.08:29:54.97#ibcon#read 6, iclass 6, count 0 2006.161.08:29:54.97#ibcon#end of sib2, iclass 6, count 0 2006.161.08:29:54.97#ibcon#*after write, iclass 6, count 0 2006.161.08:29:54.97#ibcon#*before return 0, iclass 6, count 0 2006.161.08:29:54.97#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:54.97#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:54.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:29:54.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:29:54.97$vc4f8/valo=6,772.99 2006.161.08:29:54.97#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:29:54.97#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:29:54.97#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:54.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:54.97#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:54.97#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:54.97#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:29:54.97#ibcon#first serial, iclass 10, count 0 2006.161.08:29:54.97#ibcon#enter sib2, iclass 10, count 0 2006.161.08:29:54.97#ibcon#flushed, iclass 10, count 0 2006.161.08:29:54.97#ibcon#about to write, iclass 10, count 0 2006.161.08:29:54.97#ibcon#wrote, iclass 10, count 0 2006.161.08:29:54.97#ibcon#about to read 3, iclass 10, count 0 2006.161.08:29:54.99#ibcon#read 3, iclass 10, count 0 2006.161.08:29:54.99#ibcon#about to read 4, iclass 10, count 0 2006.161.08:29:54.99#ibcon#read 4, iclass 10, count 0 2006.161.08:29:54.99#ibcon#about to read 5, iclass 10, count 0 2006.161.08:29:54.99#ibcon#read 5, iclass 10, count 0 2006.161.08:29:54.99#ibcon#about to read 6, iclass 10, count 0 2006.161.08:29:54.99#ibcon#read 6, iclass 10, count 0 2006.161.08:29:54.99#ibcon#end of sib2, iclass 10, count 0 2006.161.08:29:54.99#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:29:54.99#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:29:54.99#ibcon#[26=FRQ=06,772.99\r\n] 2006.161.08:29:54.99#ibcon#*before write, iclass 10, count 0 2006.161.08:29:54.99#ibcon#enter sib2, iclass 10, count 0 2006.161.08:29:54.99#ibcon#flushed, iclass 10, count 0 2006.161.08:29:54.99#ibcon#about to write, iclass 10, count 0 2006.161.08:29:54.99#ibcon#wrote, iclass 10, count 0 2006.161.08:29:54.99#ibcon#about to read 3, iclass 10, count 0 2006.161.08:29:55.04#ibcon#read 3, iclass 10, count 0 2006.161.08:29:55.04#ibcon#about to read 4, iclass 10, count 0 2006.161.08:29:55.04#ibcon#read 4, iclass 10, count 0 2006.161.08:29:55.04#ibcon#about to read 5, iclass 10, count 0 2006.161.08:29:55.04#ibcon#read 5, iclass 10, count 0 2006.161.08:29:55.04#ibcon#about to read 6, iclass 10, count 0 2006.161.08:29:55.04#ibcon#read 6, iclass 10, count 0 2006.161.08:29:55.04#ibcon#end of sib2, iclass 10, count 0 2006.161.08:29:55.04#ibcon#*after write, iclass 10, count 0 2006.161.08:29:55.04#ibcon#*before return 0, iclass 10, count 0 2006.161.08:29:55.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:55.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:55.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:29:55.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:29:55.04$vc4f8/va=6,6 2006.161.08:29:55.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.161.08:29:55.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.161.08:29:55.04#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:55.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:29:55.09#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:29:55.09#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:29:55.09#ibcon#enter wrdev, iclass 12, count 2 2006.161.08:29:55.09#ibcon#first serial, iclass 12, count 2 2006.161.08:29:55.09#ibcon#enter sib2, iclass 12, count 2 2006.161.08:29:55.09#ibcon#flushed, iclass 12, count 2 2006.161.08:29:55.09#ibcon#about to write, iclass 12, count 2 2006.161.08:29:55.09#ibcon#wrote, iclass 12, count 2 2006.161.08:29:55.09#ibcon#about to read 3, iclass 12, count 2 2006.161.08:29:55.11#ibcon#read 3, iclass 12, count 2 2006.161.08:29:55.11#ibcon#about to read 4, iclass 12, count 2 2006.161.08:29:55.11#ibcon#read 4, iclass 12, count 2 2006.161.08:29:55.11#ibcon#about to read 5, iclass 12, count 2 2006.161.08:29:55.11#ibcon#read 5, iclass 12, count 2 2006.161.08:29:55.11#ibcon#about to read 6, iclass 12, count 2 2006.161.08:29:55.11#ibcon#read 6, iclass 12, count 2 2006.161.08:29:55.11#ibcon#end of sib2, iclass 12, count 2 2006.161.08:29:55.11#ibcon#*mode == 0, iclass 12, count 2 2006.161.08:29:55.11#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.161.08:29:55.11#ibcon#[25=AT06-06\r\n] 2006.161.08:29:55.11#ibcon#*before write, iclass 12, count 2 2006.161.08:29:55.11#ibcon#enter sib2, iclass 12, count 2 2006.161.08:29:55.11#ibcon#flushed, iclass 12, count 2 2006.161.08:29:55.11#ibcon#about to write, iclass 12, count 2 2006.161.08:29:55.11#ibcon#wrote, iclass 12, count 2 2006.161.08:29:55.11#ibcon#about to read 3, iclass 12, count 2 2006.161.08:29:55.14#ibcon#read 3, iclass 12, count 2 2006.161.08:29:55.14#ibcon#about to read 4, iclass 12, count 2 2006.161.08:29:55.14#ibcon#read 4, iclass 12, count 2 2006.161.08:29:55.14#ibcon#about to read 5, iclass 12, count 2 2006.161.08:29:55.14#ibcon#read 5, iclass 12, count 2 2006.161.08:29:55.14#ibcon#about to read 6, iclass 12, count 2 2006.161.08:29:55.14#ibcon#read 6, iclass 12, count 2 2006.161.08:29:55.14#ibcon#end of sib2, iclass 12, count 2 2006.161.08:29:55.14#ibcon#*after write, iclass 12, count 2 2006.161.08:29:55.14#ibcon#*before return 0, iclass 12, count 2 2006.161.08:29:55.14#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:29:55.14#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.161.08:29:55.14#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.161.08:29:55.14#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:55.14#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:29:55.26#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:29:55.26#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:29:55.26#ibcon#enter wrdev, iclass 12, count 0 2006.161.08:29:55.26#ibcon#first serial, iclass 12, count 0 2006.161.08:29:55.26#ibcon#enter sib2, iclass 12, count 0 2006.161.08:29:55.26#ibcon#flushed, iclass 12, count 0 2006.161.08:29:55.26#ibcon#about to write, iclass 12, count 0 2006.161.08:29:55.26#ibcon#wrote, iclass 12, count 0 2006.161.08:29:55.26#ibcon#about to read 3, iclass 12, count 0 2006.161.08:29:55.28#ibcon#read 3, iclass 12, count 0 2006.161.08:29:55.28#ibcon#about to read 4, iclass 12, count 0 2006.161.08:29:55.28#ibcon#read 4, iclass 12, count 0 2006.161.08:29:55.28#ibcon#about to read 5, iclass 12, count 0 2006.161.08:29:55.28#ibcon#read 5, iclass 12, count 0 2006.161.08:29:55.28#ibcon#about to read 6, iclass 12, count 0 2006.161.08:29:55.28#ibcon#read 6, iclass 12, count 0 2006.161.08:29:55.28#ibcon#end of sib2, iclass 12, count 0 2006.161.08:29:55.28#ibcon#*mode == 0, iclass 12, count 0 2006.161.08:29:55.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.161.08:29:55.28#ibcon#[25=USB\r\n] 2006.161.08:29:55.28#ibcon#*before write, iclass 12, count 0 2006.161.08:29:55.28#ibcon#enter sib2, iclass 12, count 0 2006.161.08:29:55.28#ibcon#flushed, iclass 12, count 0 2006.161.08:29:55.28#ibcon#about to write, iclass 12, count 0 2006.161.08:29:55.28#ibcon#wrote, iclass 12, count 0 2006.161.08:29:55.28#ibcon#about to read 3, iclass 12, count 0 2006.161.08:29:55.31#ibcon#read 3, iclass 12, count 0 2006.161.08:29:55.31#ibcon#about to read 4, iclass 12, count 0 2006.161.08:29:55.31#ibcon#read 4, iclass 12, count 0 2006.161.08:29:55.31#ibcon#about to read 5, iclass 12, count 0 2006.161.08:29:55.31#ibcon#read 5, iclass 12, count 0 2006.161.08:29:55.31#ibcon#about to read 6, iclass 12, count 0 2006.161.08:29:55.31#ibcon#read 6, iclass 12, count 0 2006.161.08:29:55.31#ibcon#end of sib2, iclass 12, count 0 2006.161.08:29:55.31#ibcon#*after write, iclass 12, count 0 2006.161.08:29:55.31#ibcon#*before return 0, iclass 12, count 0 2006.161.08:29:55.31#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:29:55.31#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.161.08:29:55.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.161.08:29:55.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.161.08:29:55.31$vc4f8/valo=7,832.99 2006.161.08:29:55.31#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.161.08:29:55.31#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.161.08:29:55.31#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:55.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:29:55.31#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:29:55.31#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:29:55.31#ibcon#enter wrdev, iclass 14, count 0 2006.161.08:29:55.31#ibcon#first serial, iclass 14, count 0 2006.161.08:29:55.31#ibcon#enter sib2, iclass 14, count 0 2006.161.08:29:55.31#ibcon#flushed, iclass 14, count 0 2006.161.08:29:55.31#ibcon#about to write, iclass 14, count 0 2006.161.08:29:55.31#ibcon#wrote, iclass 14, count 0 2006.161.08:29:55.31#ibcon#about to read 3, iclass 14, count 0 2006.161.08:29:55.33#ibcon#read 3, iclass 14, count 0 2006.161.08:29:55.33#ibcon#about to read 4, iclass 14, count 0 2006.161.08:29:55.33#ibcon#read 4, iclass 14, count 0 2006.161.08:29:55.33#ibcon#about to read 5, iclass 14, count 0 2006.161.08:29:55.33#ibcon#read 5, iclass 14, count 0 2006.161.08:29:55.33#ibcon#about to read 6, iclass 14, count 0 2006.161.08:29:55.33#ibcon#read 6, iclass 14, count 0 2006.161.08:29:55.33#ibcon#end of sib2, iclass 14, count 0 2006.161.08:29:55.33#ibcon#*mode == 0, iclass 14, count 0 2006.161.08:29:55.33#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.161.08:29:55.33#ibcon#[26=FRQ=07,832.99\r\n] 2006.161.08:29:55.33#ibcon#*before write, iclass 14, count 0 2006.161.08:29:55.33#ibcon#enter sib2, iclass 14, count 0 2006.161.08:29:55.33#ibcon#flushed, iclass 14, count 0 2006.161.08:29:55.33#ibcon#about to write, iclass 14, count 0 2006.161.08:29:55.33#ibcon#wrote, iclass 14, count 0 2006.161.08:29:55.33#ibcon#about to read 3, iclass 14, count 0 2006.161.08:29:55.37#ibcon#read 3, iclass 14, count 0 2006.161.08:29:55.37#ibcon#about to read 4, iclass 14, count 0 2006.161.08:29:55.37#ibcon#read 4, iclass 14, count 0 2006.161.08:29:55.37#ibcon#about to read 5, iclass 14, count 0 2006.161.08:29:55.37#ibcon#read 5, iclass 14, count 0 2006.161.08:29:55.37#ibcon#about to read 6, iclass 14, count 0 2006.161.08:29:55.37#ibcon#read 6, iclass 14, count 0 2006.161.08:29:55.37#ibcon#end of sib2, iclass 14, count 0 2006.161.08:29:55.37#ibcon#*after write, iclass 14, count 0 2006.161.08:29:55.37#ibcon#*before return 0, iclass 14, count 0 2006.161.08:29:55.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:29:55.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.161.08:29:55.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.161.08:29:55.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.161.08:29:55.37$vc4f8/va=7,6 2006.161.08:29:55.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.161.08:29:55.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.161.08:29:55.37#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:55.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:29:55.43#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:29:55.43#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:29:55.43#ibcon#enter wrdev, iclass 16, count 2 2006.161.08:29:55.43#ibcon#first serial, iclass 16, count 2 2006.161.08:29:55.43#ibcon#enter sib2, iclass 16, count 2 2006.161.08:29:55.43#ibcon#flushed, iclass 16, count 2 2006.161.08:29:55.43#ibcon#about to write, iclass 16, count 2 2006.161.08:29:55.43#ibcon#wrote, iclass 16, count 2 2006.161.08:29:55.43#ibcon#about to read 3, iclass 16, count 2 2006.161.08:29:55.45#ibcon#read 3, iclass 16, count 2 2006.161.08:29:55.45#ibcon#about to read 4, iclass 16, count 2 2006.161.08:29:55.45#ibcon#read 4, iclass 16, count 2 2006.161.08:29:55.45#ibcon#about to read 5, iclass 16, count 2 2006.161.08:29:55.45#ibcon#read 5, iclass 16, count 2 2006.161.08:29:55.45#ibcon#about to read 6, iclass 16, count 2 2006.161.08:29:55.45#ibcon#read 6, iclass 16, count 2 2006.161.08:29:55.45#ibcon#end of sib2, iclass 16, count 2 2006.161.08:29:55.45#ibcon#*mode == 0, iclass 16, count 2 2006.161.08:29:55.45#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.161.08:29:55.45#ibcon#[25=AT07-06\r\n] 2006.161.08:29:55.45#ibcon#*before write, iclass 16, count 2 2006.161.08:29:55.45#ibcon#enter sib2, iclass 16, count 2 2006.161.08:29:55.45#ibcon#flushed, iclass 16, count 2 2006.161.08:29:55.45#ibcon#about to write, iclass 16, count 2 2006.161.08:29:55.45#ibcon#wrote, iclass 16, count 2 2006.161.08:29:55.45#ibcon#about to read 3, iclass 16, count 2 2006.161.08:29:55.48#ibcon#read 3, iclass 16, count 2 2006.161.08:29:55.48#ibcon#about to read 4, iclass 16, count 2 2006.161.08:29:55.48#ibcon#read 4, iclass 16, count 2 2006.161.08:29:55.48#ibcon#about to read 5, iclass 16, count 2 2006.161.08:29:55.48#ibcon#read 5, iclass 16, count 2 2006.161.08:29:55.48#ibcon#about to read 6, iclass 16, count 2 2006.161.08:29:55.48#ibcon#read 6, iclass 16, count 2 2006.161.08:29:55.48#ibcon#end of sib2, iclass 16, count 2 2006.161.08:29:55.48#ibcon#*after write, iclass 16, count 2 2006.161.08:29:55.48#ibcon#*before return 0, iclass 16, count 2 2006.161.08:29:55.48#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:29:55.48#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.161.08:29:55.48#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.161.08:29:55.48#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:55.48#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:29:55.60#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:29:55.60#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:29:55.60#ibcon#enter wrdev, iclass 16, count 0 2006.161.08:29:55.60#ibcon#first serial, iclass 16, count 0 2006.161.08:29:55.60#ibcon#enter sib2, iclass 16, count 0 2006.161.08:29:55.60#ibcon#flushed, iclass 16, count 0 2006.161.08:29:55.60#ibcon#about to write, iclass 16, count 0 2006.161.08:29:55.60#ibcon#wrote, iclass 16, count 0 2006.161.08:29:55.60#ibcon#about to read 3, iclass 16, count 0 2006.161.08:29:55.62#ibcon#read 3, iclass 16, count 0 2006.161.08:29:55.62#ibcon#about to read 4, iclass 16, count 0 2006.161.08:29:55.62#ibcon#read 4, iclass 16, count 0 2006.161.08:29:55.62#ibcon#about to read 5, iclass 16, count 0 2006.161.08:29:55.62#ibcon#read 5, iclass 16, count 0 2006.161.08:29:55.62#ibcon#about to read 6, iclass 16, count 0 2006.161.08:29:55.62#ibcon#read 6, iclass 16, count 0 2006.161.08:29:55.62#ibcon#end of sib2, iclass 16, count 0 2006.161.08:29:55.62#ibcon#*mode == 0, iclass 16, count 0 2006.161.08:29:55.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.161.08:29:55.62#ibcon#[25=USB\r\n] 2006.161.08:29:55.62#ibcon#*before write, iclass 16, count 0 2006.161.08:29:55.62#ibcon#enter sib2, iclass 16, count 0 2006.161.08:29:55.62#ibcon#flushed, iclass 16, count 0 2006.161.08:29:55.62#ibcon#about to write, iclass 16, count 0 2006.161.08:29:55.62#ibcon#wrote, iclass 16, count 0 2006.161.08:29:55.62#ibcon#about to read 3, iclass 16, count 0 2006.161.08:29:55.65#ibcon#read 3, iclass 16, count 0 2006.161.08:29:55.65#ibcon#about to read 4, iclass 16, count 0 2006.161.08:29:55.65#ibcon#read 4, iclass 16, count 0 2006.161.08:29:55.65#ibcon#about to read 5, iclass 16, count 0 2006.161.08:29:55.65#ibcon#read 5, iclass 16, count 0 2006.161.08:29:55.65#ibcon#about to read 6, iclass 16, count 0 2006.161.08:29:55.65#ibcon#read 6, iclass 16, count 0 2006.161.08:29:55.65#ibcon#end of sib2, iclass 16, count 0 2006.161.08:29:55.65#ibcon#*after write, iclass 16, count 0 2006.161.08:29:55.65#ibcon#*before return 0, iclass 16, count 0 2006.161.08:29:55.65#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:29:55.65#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.161.08:29:55.65#ibcon#about to clear, iclass 16 cls_cnt 0 2006.161.08:29:55.65#ibcon#cleared, iclass 16 cls_cnt 0 2006.161.08:29:55.65$vc4f8/valo=8,852.99 2006.161.08:29:55.65#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.161.08:29:55.65#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.161.08:29:55.65#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:55.65#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:29:55.65#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:29:55.65#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:29:55.65#ibcon#enter wrdev, iclass 18, count 0 2006.161.08:29:55.65#ibcon#first serial, iclass 18, count 0 2006.161.08:29:55.65#ibcon#enter sib2, iclass 18, count 0 2006.161.08:29:55.65#ibcon#flushed, iclass 18, count 0 2006.161.08:29:55.65#ibcon#about to write, iclass 18, count 0 2006.161.08:29:55.65#ibcon#wrote, iclass 18, count 0 2006.161.08:29:55.65#ibcon#about to read 3, iclass 18, count 0 2006.161.08:29:55.67#ibcon#read 3, iclass 18, count 0 2006.161.08:29:55.67#ibcon#about to read 4, iclass 18, count 0 2006.161.08:29:55.67#ibcon#read 4, iclass 18, count 0 2006.161.08:29:55.67#ibcon#about to read 5, iclass 18, count 0 2006.161.08:29:55.67#ibcon#read 5, iclass 18, count 0 2006.161.08:29:55.67#ibcon#about to read 6, iclass 18, count 0 2006.161.08:29:55.67#ibcon#read 6, iclass 18, count 0 2006.161.08:29:55.67#ibcon#end of sib2, iclass 18, count 0 2006.161.08:29:55.67#ibcon#*mode == 0, iclass 18, count 0 2006.161.08:29:55.67#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.161.08:29:55.67#ibcon#[26=FRQ=08,852.99\r\n] 2006.161.08:29:55.67#ibcon#*before write, iclass 18, count 0 2006.161.08:29:55.67#ibcon#enter sib2, iclass 18, count 0 2006.161.08:29:55.67#ibcon#flushed, iclass 18, count 0 2006.161.08:29:55.67#ibcon#about to write, iclass 18, count 0 2006.161.08:29:55.67#ibcon#wrote, iclass 18, count 0 2006.161.08:29:55.67#ibcon#about to read 3, iclass 18, count 0 2006.161.08:29:55.71#ibcon#read 3, iclass 18, count 0 2006.161.08:29:55.71#ibcon#about to read 4, iclass 18, count 0 2006.161.08:29:55.71#ibcon#read 4, iclass 18, count 0 2006.161.08:29:55.71#ibcon#about to read 5, iclass 18, count 0 2006.161.08:29:55.71#ibcon#read 5, iclass 18, count 0 2006.161.08:29:55.71#ibcon#about to read 6, iclass 18, count 0 2006.161.08:29:55.71#ibcon#read 6, iclass 18, count 0 2006.161.08:29:55.71#ibcon#end of sib2, iclass 18, count 0 2006.161.08:29:55.71#ibcon#*after write, iclass 18, count 0 2006.161.08:29:55.71#ibcon#*before return 0, iclass 18, count 0 2006.161.08:29:55.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:29:55.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.161.08:29:55.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.161.08:29:55.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.161.08:29:55.71$vc4f8/va=8,7 2006.161.08:29:55.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.161.08:29:55.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.161.08:29:55.71#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:55.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:29:55.77#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:29:55.77#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:29:55.77#ibcon#enter wrdev, iclass 20, count 2 2006.161.08:29:55.77#ibcon#first serial, iclass 20, count 2 2006.161.08:29:55.77#ibcon#enter sib2, iclass 20, count 2 2006.161.08:29:55.77#ibcon#flushed, iclass 20, count 2 2006.161.08:29:55.77#ibcon#about to write, iclass 20, count 2 2006.161.08:29:55.77#ibcon#wrote, iclass 20, count 2 2006.161.08:29:55.77#ibcon#about to read 3, iclass 20, count 2 2006.161.08:29:55.79#ibcon#read 3, iclass 20, count 2 2006.161.08:29:55.79#ibcon#about to read 4, iclass 20, count 2 2006.161.08:29:55.79#ibcon#read 4, iclass 20, count 2 2006.161.08:29:55.79#ibcon#about to read 5, iclass 20, count 2 2006.161.08:29:55.79#ibcon#read 5, iclass 20, count 2 2006.161.08:29:55.79#ibcon#about to read 6, iclass 20, count 2 2006.161.08:29:55.79#ibcon#read 6, iclass 20, count 2 2006.161.08:29:55.79#ibcon#end of sib2, iclass 20, count 2 2006.161.08:29:55.79#ibcon#*mode == 0, iclass 20, count 2 2006.161.08:29:55.79#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.161.08:29:55.79#ibcon#[25=AT08-07\r\n] 2006.161.08:29:55.79#ibcon#*before write, iclass 20, count 2 2006.161.08:29:55.79#ibcon#enter sib2, iclass 20, count 2 2006.161.08:29:55.79#ibcon#flushed, iclass 20, count 2 2006.161.08:29:55.79#ibcon#about to write, iclass 20, count 2 2006.161.08:29:55.79#ibcon#wrote, iclass 20, count 2 2006.161.08:29:55.79#ibcon#about to read 3, iclass 20, count 2 2006.161.08:29:55.83#ibcon#read 3, iclass 20, count 2 2006.161.08:29:55.83#ibcon#about to read 4, iclass 20, count 2 2006.161.08:29:55.83#ibcon#read 4, iclass 20, count 2 2006.161.08:29:55.83#ibcon#about to read 5, iclass 20, count 2 2006.161.08:29:55.83#ibcon#read 5, iclass 20, count 2 2006.161.08:29:55.83#ibcon#about to read 6, iclass 20, count 2 2006.161.08:29:55.83#ibcon#read 6, iclass 20, count 2 2006.161.08:29:55.83#ibcon#end of sib2, iclass 20, count 2 2006.161.08:29:55.83#ibcon#*after write, iclass 20, count 2 2006.161.08:29:55.83#ibcon#*before return 0, iclass 20, count 2 2006.161.08:29:55.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:29:55.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.161.08:29:55.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.161.08:29:55.83#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:55.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:29:55.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:29:55.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:29:55.95#ibcon#enter wrdev, iclass 20, count 0 2006.161.08:29:55.95#ibcon#first serial, iclass 20, count 0 2006.161.08:29:55.95#ibcon#enter sib2, iclass 20, count 0 2006.161.08:29:55.95#ibcon#flushed, iclass 20, count 0 2006.161.08:29:55.95#ibcon#about to write, iclass 20, count 0 2006.161.08:29:55.95#ibcon#wrote, iclass 20, count 0 2006.161.08:29:55.95#ibcon#about to read 3, iclass 20, count 0 2006.161.08:29:55.97#ibcon#read 3, iclass 20, count 0 2006.161.08:29:55.97#ibcon#about to read 4, iclass 20, count 0 2006.161.08:29:55.97#ibcon#read 4, iclass 20, count 0 2006.161.08:29:55.97#ibcon#about to read 5, iclass 20, count 0 2006.161.08:29:55.97#ibcon#read 5, iclass 20, count 0 2006.161.08:29:55.97#ibcon#about to read 6, iclass 20, count 0 2006.161.08:29:55.97#ibcon#read 6, iclass 20, count 0 2006.161.08:29:55.97#ibcon#end of sib2, iclass 20, count 0 2006.161.08:29:55.97#ibcon#*mode == 0, iclass 20, count 0 2006.161.08:29:55.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.161.08:29:55.97#ibcon#[25=USB\r\n] 2006.161.08:29:55.97#ibcon#*before write, iclass 20, count 0 2006.161.08:29:55.97#ibcon#enter sib2, iclass 20, count 0 2006.161.08:29:55.97#ibcon#flushed, iclass 20, count 0 2006.161.08:29:55.97#ibcon#about to write, iclass 20, count 0 2006.161.08:29:55.97#ibcon#wrote, iclass 20, count 0 2006.161.08:29:55.97#ibcon#about to read 3, iclass 20, count 0 2006.161.08:29:56.00#ibcon#read 3, iclass 20, count 0 2006.161.08:29:56.00#ibcon#about to read 4, iclass 20, count 0 2006.161.08:29:56.00#ibcon#read 4, iclass 20, count 0 2006.161.08:29:56.00#ibcon#about to read 5, iclass 20, count 0 2006.161.08:29:56.00#ibcon#read 5, iclass 20, count 0 2006.161.08:29:56.00#ibcon#about to read 6, iclass 20, count 0 2006.161.08:29:56.00#ibcon#read 6, iclass 20, count 0 2006.161.08:29:56.00#ibcon#end of sib2, iclass 20, count 0 2006.161.08:29:56.00#ibcon#*after write, iclass 20, count 0 2006.161.08:29:56.00#ibcon#*before return 0, iclass 20, count 0 2006.161.08:29:56.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:29:56.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.161.08:29:56.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.161.08:29:56.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.161.08:29:56.00$vc4f8/vblo=1,632.99 2006.161.08:29:56.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.161.08:29:56.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.161.08:29:56.00#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:56.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:29:56.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:29:56.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:29:56.00#ibcon#enter wrdev, iclass 22, count 0 2006.161.08:29:56.00#ibcon#first serial, iclass 22, count 0 2006.161.08:29:56.00#ibcon#enter sib2, iclass 22, count 0 2006.161.08:29:56.00#ibcon#flushed, iclass 22, count 0 2006.161.08:29:56.00#ibcon#about to write, iclass 22, count 0 2006.161.08:29:56.00#ibcon#wrote, iclass 22, count 0 2006.161.08:29:56.00#ibcon#about to read 3, iclass 22, count 0 2006.161.08:29:56.02#ibcon#read 3, iclass 22, count 0 2006.161.08:29:56.02#ibcon#about to read 4, iclass 22, count 0 2006.161.08:29:56.02#ibcon#read 4, iclass 22, count 0 2006.161.08:29:56.02#ibcon#about to read 5, iclass 22, count 0 2006.161.08:29:56.02#ibcon#read 5, iclass 22, count 0 2006.161.08:29:56.02#ibcon#about to read 6, iclass 22, count 0 2006.161.08:29:56.02#ibcon#read 6, iclass 22, count 0 2006.161.08:29:56.02#ibcon#end of sib2, iclass 22, count 0 2006.161.08:29:56.02#ibcon#*mode == 0, iclass 22, count 0 2006.161.08:29:56.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.161.08:29:56.02#ibcon#[28=FRQ=01,632.99\r\n] 2006.161.08:29:56.02#ibcon#*before write, iclass 22, count 0 2006.161.08:29:56.02#ibcon#enter sib2, iclass 22, count 0 2006.161.08:29:56.02#ibcon#flushed, iclass 22, count 0 2006.161.08:29:56.02#ibcon#about to write, iclass 22, count 0 2006.161.08:29:56.02#ibcon#wrote, iclass 22, count 0 2006.161.08:29:56.02#ibcon#about to read 3, iclass 22, count 0 2006.161.08:29:56.06#ibcon#read 3, iclass 22, count 0 2006.161.08:29:56.06#ibcon#about to read 4, iclass 22, count 0 2006.161.08:29:56.06#ibcon#read 4, iclass 22, count 0 2006.161.08:29:56.06#ibcon#about to read 5, iclass 22, count 0 2006.161.08:29:56.06#ibcon#read 5, iclass 22, count 0 2006.161.08:29:56.06#ibcon#about to read 6, iclass 22, count 0 2006.161.08:29:56.06#ibcon#read 6, iclass 22, count 0 2006.161.08:29:56.06#ibcon#end of sib2, iclass 22, count 0 2006.161.08:29:56.06#ibcon#*after write, iclass 22, count 0 2006.161.08:29:56.06#ibcon#*before return 0, iclass 22, count 0 2006.161.08:29:56.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:29:56.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.161.08:29:56.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.161.08:29:56.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.161.08:29:56.06$vc4f8/vb=1,4 2006.161.08:29:56.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.161.08:29:56.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.161.08:29:56.06#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:56.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:29:56.06#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:29:56.06#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:29:56.06#ibcon#enter wrdev, iclass 24, count 2 2006.161.08:29:56.06#ibcon#first serial, iclass 24, count 2 2006.161.08:29:56.06#ibcon#enter sib2, iclass 24, count 2 2006.161.08:29:56.06#ibcon#flushed, iclass 24, count 2 2006.161.08:29:56.06#ibcon#about to write, iclass 24, count 2 2006.161.08:29:56.06#ibcon#wrote, iclass 24, count 2 2006.161.08:29:56.06#ibcon#about to read 3, iclass 24, count 2 2006.161.08:29:56.08#ibcon#read 3, iclass 24, count 2 2006.161.08:29:56.08#ibcon#about to read 4, iclass 24, count 2 2006.161.08:29:56.08#ibcon#read 4, iclass 24, count 2 2006.161.08:29:56.08#ibcon#about to read 5, iclass 24, count 2 2006.161.08:29:56.08#ibcon#read 5, iclass 24, count 2 2006.161.08:29:56.08#ibcon#about to read 6, iclass 24, count 2 2006.161.08:29:56.08#ibcon#read 6, iclass 24, count 2 2006.161.08:29:56.08#ibcon#end of sib2, iclass 24, count 2 2006.161.08:29:56.08#ibcon#*mode == 0, iclass 24, count 2 2006.161.08:29:56.08#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.161.08:29:56.08#ibcon#[27=AT01-04\r\n] 2006.161.08:29:56.08#ibcon#*before write, iclass 24, count 2 2006.161.08:29:56.08#ibcon#enter sib2, iclass 24, count 2 2006.161.08:29:56.08#ibcon#flushed, iclass 24, count 2 2006.161.08:29:56.08#ibcon#about to write, iclass 24, count 2 2006.161.08:29:56.08#ibcon#wrote, iclass 24, count 2 2006.161.08:29:56.08#ibcon#about to read 3, iclass 24, count 2 2006.161.08:29:56.11#ibcon#read 3, iclass 24, count 2 2006.161.08:29:56.11#ibcon#about to read 4, iclass 24, count 2 2006.161.08:29:56.11#ibcon#read 4, iclass 24, count 2 2006.161.08:29:56.11#ibcon#about to read 5, iclass 24, count 2 2006.161.08:29:56.11#ibcon#read 5, iclass 24, count 2 2006.161.08:29:56.11#ibcon#about to read 6, iclass 24, count 2 2006.161.08:29:56.11#ibcon#read 6, iclass 24, count 2 2006.161.08:29:56.11#ibcon#end of sib2, iclass 24, count 2 2006.161.08:29:56.11#ibcon#*after write, iclass 24, count 2 2006.161.08:29:56.11#ibcon#*before return 0, iclass 24, count 2 2006.161.08:29:56.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:29:56.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.161.08:29:56.11#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.161.08:29:56.11#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:56.11#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:29:56.23#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:29:56.23#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:29:56.23#ibcon#enter wrdev, iclass 24, count 0 2006.161.08:29:56.23#ibcon#first serial, iclass 24, count 0 2006.161.08:29:56.23#ibcon#enter sib2, iclass 24, count 0 2006.161.08:29:56.23#ibcon#flushed, iclass 24, count 0 2006.161.08:29:56.23#ibcon#about to write, iclass 24, count 0 2006.161.08:29:56.23#ibcon#wrote, iclass 24, count 0 2006.161.08:29:56.23#ibcon#about to read 3, iclass 24, count 0 2006.161.08:29:56.25#ibcon#read 3, iclass 24, count 0 2006.161.08:29:56.25#ibcon#about to read 4, iclass 24, count 0 2006.161.08:29:56.25#ibcon#read 4, iclass 24, count 0 2006.161.08:29:56.25#ibcon#about to read 5, iclass 24, count 0 2006.161.08:29:56.25#ibcon#read 5, iclass 24, count 0 2006.161.08:29:56.25#ibcon#about to read 6, iclass 24, count 0 2006.161.08:29:56.25#ibcon#read 6, iclass 24, count 0 2006.161.08:29:56.25#ibcon#end of sib2, iclass 24, count 0 2006.161.08:29:56.25#ibcon#*mode == 0, iclass 24, count 0 2006.161.08:29:56.25#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.161.08:29:56.25#ibcon#[27=USB\r\n] 2006.161.08:29:56.25#ibcon#*before write, iclass 24, count 0 2006.161.08:29:56.25#ibcon#enter sib2, iclass 24, count 0 2006.161.08:29:56.25#ibcon#flushed, iclass 24, count 0 2006.161.08:29:56.25#ibcon#about to write, iclass 24, count 0 2006.161.08:29:56.25#ibcon#wrote, iclass 24, count 0 2006.161.08:29:56.25#ibcon#about to read 3, iclass 24, count 0 2006.161.08:29:56.28#ibcon#read 3, iclass 24, count 0 2006.161.08:29:56.28#ibcon#about to read 4, iclass 24, count 0 2006.161.08:29:56.28#ibcon#read 4, iclass 24, count 0 2006.161.08:29:56.28#ibcon#about to read 5, iclass 24, count 0 2006.161.08:29:56.28#ibcon#read 5, iclass 24, count 0 2006.161.08:29:56.28#ibcon#about to read 6, iclass 24, count 0 2006.161.08:29:56.28#ibcon#read 6, iclass 24, count 0 2006.161.08:29:56.28#ibcon#end of sib2, iclass 24, count 0 2006.161.08:29:56.28#ibcon#*after write, iclass 24, count 0 2006.161.08:29:56.28#ibcon#*before return 0, iclass 24, count 0 2006.161.08:29:56.28#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:29:56.28#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.161.08:29:56.28#ibcon#about to clear, iclass 24 cls_cnt 0 2006.161.08:29:56.28#ibcon#cleared, iclass 24 cls_cnt 0 2006.161.08:29:56.28$vc4f8/vblo=2,640.99 2006.161.08:29:56.28#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.161.08:29:56.28#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.161.08:29:56.28#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:56.28#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:56.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:56.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:56.28#ibcon#enter wrdev, iclass 26, count 0 2006.161.08:29:56.28#ibcon#first serial, iclass 26, count 0 2006.161.08:29:56.28#ibcon#enter sib2, iclass 26, count 0 2006.161.08:29:56.28#ibcon#flushed, iclass 26, count 0 2006.161.08:29:56.28#ibcon#about to write, iclass 26, count 0 2006.161.08:29:56.28#ibcon#wrote, iclass 26, count 0 2006.161.08:29:56.28#ibcon#about to read 3, iclass 26, count 0 2006.161.08:29:56.30#ibcon#read 3, iclass 26, count 0 2006.161.08:29:56.30#ibcon#about to read 4, iclass 26, count 0 2006.161.08:29:56.30#ibcon#read 4, iclass 26, count 0 2006.161.08:29:56.30#ibcon#about to read 5, iclass 26, count 0 2006.161.08:29:56.30#ibcon#read 5, iclass 26, count 0 2006.161.08:29:56.30#ibcon#about to read 6, iclass 26, count 0 2006.161.08:29:56.30#ibcon#read 6, iclass 26, count 0 2006.161.08:29:56.30#ibcon#end of sib2, iclass 26, count 0 2006.161.08:29:56.30#ibcon#*mode == 0, iclass 26, count 0 2006.161.08:29:56.30#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.161.08:29:56.30#ibcon#[28=FRQ=02,640.99\r\n] 2006.161.08:29:56.30#ibcon#*before write, iclass 26, count 0 2006.161.08:29:56.30#ibcon#enter sib2, iclass 26, count 0 2006.161.08:29:56.30#ibcon#flushed, iclass 26, count 0 2006.161.08:29:56.30#ibcon#about to write, iclass 26, count 0 2006.161.08:29:56.30#ibcon#wrote, iclass 26, count 0 2006.161.08:29:56.30#ibcon#about to read 3, iclass 26, count 0 2006.161.08:29:56.34#ibcon#read 3, iclass 26, count 0 2006.161.08:29:56.34#ibcon#about to read 4, iclass 26, count 0 2006.161.08:29:56.34#ibcon#read 4, iclass 26, count 0 2006.161.08:29:56.34#ibcon#about to read 5, iclass 26, count 0 2006.161.08:29:56.34#ibcon#read 5, iclass 26, count 0 2006.161.08:29:56.34#ibcon#about to read 6, iclass 26, count 0 2006.161.08:29:56.34#ibcon#read 6, iclass 26, count 0 2006.161.08:29:56.34#ibcon#end of sib2, iclass 26, count 0 2006.161.08:29:56.34#ibcon#*after write, iclass 26, count 0 2006.161.08:29:56.34#ibcon#*before return 0, iclass 26, count 0 2006.161.08:29:56.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:56.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.161.08:29:56.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.161.08:29:56.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.161.08:29:56.34$vc4f8/vb=2,4 2006.161.08:29:56.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.161.08:29:56.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.161.08:29:56.34#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:56.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:56.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:56.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:56.40#ibcon#enter wrdev, iclass 28, count 2 2006.161.08:29:56.40#ibcon#first serial, iclass 28, count 2 2006.161.08:29:56.40#ibcon#enter sib2, iclass 28, count 2 2006.161.08:29:56.40#ibcon#flushed, iclass 28, count 2 2006.161.08:29:56.40#ibcon#about to write, iclass 28, count 2 2006.161.08:29:56.40#ibcon#wrote, iclass 28, count 2 2006.161.08:29:56.40#ibcon#about to read 3, iclass 28, count 2 2006.161.08:29:56.42#ibcon#read 3, iclass 28, count 2 2006.161.08:29:56.42#ibcon#about to read 4, iclass 28, count 2 2006.161.08:29:56.42#ibcon#read 4, iclass 28, count 2 2006.161.08:29:56.42#ibcon#about to read 5, iclass 28, count 2 2006.161.08:29:56.42#ibcon#read 5, iclass 28, count 2 2006.161.08:29:56.42#ibcon#about to read 6, iclass 28, count 2 2006.161.08:29:56.42#ibcon#read 6, iclass 28, count 2 2006.161.08:29:56.42#ibcon#end of sib2, iclass 28, count 2 2006.161.08:29:56.42#ibcon#*mode == 0, iclass 28, count 2 2006.161.08:29:56.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.161.08:29:56.42#ibcon#[27=AT02-04\r\n] 2006.161.08:29:56.42#ibcon#*before write, iclass 28, count 2 2006.161.08:29:56.42#ibcon#enter sib2, iclass 28, count 2 2006.161.08:29:56.42#ibcon#flushed, iclass 28, count 2 2006.161.08:29:56.42#ibcon#about to write, iclass 28, count 2 2006.161.08:29:56.42#ibcon#wrote, iclass 28, count 2 2006.161.08:29:56.42#ibcon#about to read 3, iclass 28, count 2 2006.161.08:29:56.46#ibcon#read 3, iclass 28, count 2 2006.161.08:29:56.46#ibcon#about to read 4, iclass 28, count 2 2006.161.08:29:56.46#ibcon#read 4, iclass 28, count 2 2006.161.08:29:56.46#ibcon#about to read 5, iclass 28, count 2 2006.161.08:29:56.46#ibcon#read 5, iclass 28, count 2 2006.161.08:29:56.46#ibcon#about to read 6, iclass 28, count 2 2006.161.08:29:56.46#ibcon#read 6, iclass 28, count 2 2006.161.08:29:56.46#ibcon#end of sib2, iclass 28, count 2 2006.161.08:29:56.46#ibcon#*after write, iclass 28, count 2 2006.161.08:29:56.46#ibcon#*before return 0, iclass 28, count 2 2006.161.08:29:56.46#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:56.46#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.161.08:29:56.46#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.161.08:29:56.46#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:56.46#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:56.58#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:56.58#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:56.58#ibcon#enter wrdev, iclass 28, count 0 2006.161.08:29:56.58#ibcon#first serial, iclass 28, count 0 2006.161.08:29:56.58#ibcon#enter sib2, iclass 28, count 0 2006.161.08:29:56.58#ibcon#flushed, iclass 28, count 0 2006.161.08:29:56.58#ibcon#about to write, iclass 28, count 0 2006.161.08:29:56.58#ibcon#wrote, iclass 28, count 0 2006.161.08:29:56.58#ibcon#about to read 3, iclass 28, count 0 2006.161.08:29:56.60#ibcon#read 3, iclass 28, count 0 2006.161.08:29:56.60#ibcon#about to read 4, iclass 28, count 0 2006.161.08:29:56.60#ibcon#read 4, iclass 28, count 0 2006.161.08:29:56.60#ibcon#about to read 5, iclass 28, count 0 2006.161.08:29:56.60#ibcon#read 5, iclass 28, count 0 2006.161.08:29:56.60#ibcon#about to read 6, iclass 28, count 0 2006.161.08:29:56.60#ibcon#read 6, iclass 28, count 0 2006.161.08:29:56.60#ibcon#end of sib2, iclass 28, count 0 2006.161.08:29:56.60#ibcon#*mode == 0, iclass 28, count 0 2006.161.08:29:56.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.161.08:29:56.60#ibcon#[27=USB\r\n] 2006.161.08:29:56.60#ibcon#*before write, iclass 28, count 0 2006.161.08:29:56.60#ibcon#enter sib2, iclass 28, count 0 2006.161.08:29:56.60#ibcon#flushed, iclass 28, count 0 2006.161.08:29:56.60#ibcon#about to write, iclass 28, count 0 2006.161.08:29:56.60#ibcon#wrote, iclass 28, count 0 2006.161.08:29:56.60#ibcon#about to read 3, iclass 28, count 0 2006.161.08:29:56.63#ibcon#read 3, iclass 28, count 0 2006.161.08:29:56.63#ibcon#about to read 4, iclass 28, count 0 2006.161.08:29:56.63#ibcon#read 4, iclass 28, count 0 2006.161.08:29:56.63#ibcon#about to read 5, iclass 28, count 0 2006.161.08:29:56.63#ibcon#read 5, iclass 28, count 0 2006.161.08:29:56.63#ibcon#about to read 6, iclass 28, count 0 2006.161.08:29:56.63#ibcon#read 6, iclass 28, count 0 2006.161.08:29:56.63#ibcon#end of sib2, iclass 28, count 0 2006.161.08:29:56.63#ibcon#*after write, iclass 28, count 0 2006.161.08:29:56.63#ibcon#*before return 0, iclass 28, count 0 2006.161.08:29:56.63#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:56.63#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.161.08:29:56.63#ibcon#about to clear, iclass 28 cls_cnt 0 2006.161.08:29:56.63#ibcon#cleared, iclass 28 cls_cnt 0 2006.161.08:29:56.63$vc4f8/vblo=3,656.99 2006.161.08:29:56.63#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.161.08:29:56.63#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.161.08:29:56.63#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:56.63#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:56.63#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:56.63#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:56.63#ibcon#enter wrdev, iclass 30, count 0 2006.161.08:29:56.63#ibcon#first serial, iclass 30, count 0 2006.161.08:29:56.63#ibcon#enter sib2, iclass 30, count 0 2006.161.08:29:56.63#ibcon#flushed, iclass 30, count 0 2006.161.08:29:56.63#ibcon#about to write, iclass 30, count 0 2006.161.08:29:56.63#ibcon#wrote, iclass 30, count 0 2006.161.08:29:56.63#ibcon#about to read 3, iclass 30, count 0 2006.161.08:29:56.65#ibcon#read 3, iclass 30, count 0 2006.161.08:29:56.65#ibcon#about to read 4, iclass 30, count 0 2006.161.08:29:56.65#ibcon#read 4, iclass 30, count 0 2006.161.08:29:56.65#ibcon#about to read 5, iclass 30, count 0 2006.161.08:29:56.65#ibcon#read 5, iclass 30, count 0 2006.161.08:29:56.65#ibcon#about to read 6, iclass 30, count 0 2006.161.08:29:56.65#ibcon#read 6, iclass 30, count 0 2006.161.08:29:56.65#ibcon#end of sib2, iclass 30, count 0 2006.161.08:29:56.65#ibcon#*mode == 0, iclass 30, count 0 2006.161.08:29:56.65#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.161.08:29:56.65#ibcon#[28=FRQ=03,656.99\r\n] 2006.161.08:29:56.65#ibcon#*before write, iclass 30, count 0 2006.161.08:29:56.65#ibcon#enter sib2, iclass 30, count 0 2006.161.08:29:56.65#ibcon#flushed, iclass 30, count 0 2006.161.08:29:56.65#ibcon#about to write, iclass 30, count 0 2006.161.08:29:56.65#ibcon#wrote, iclass 30, count 0 2006.161.08:29:56.65#ibcon#about to read 3, iclass 30, count 0 2006.161.08:29:56.69#ibcon#read 3, iclass 30, count 0 2006.161.08:29:56.69#ibcon#about to read 4, iclass 30, count 0 2006.161.08:29:56.69#ibcon#read 4, iclass 30, count 0 2006.161.08:29:56.69#ibcon#about to read 5, iclass 30, count 0 2006.161.08:29:56.69#ibcon#read 5, iclass 30, count 0 2006.161.08:29:56.69#ibcon#about to read 6, iclass 30, count 0 2006.161.08:29:56.69#ibcon#read 6, iclass 30, count 0 2006.161.08:29:56.69#ibcon#end of sib2, iclass 30, count 0 2006.161.08:29:56.69#ibcon#*after write, iclass 30, count 0 2006.161.08:29:56.69#ibcon#*before return 0, iclass 30, count 0 2006.161.08:29:56.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:56.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.161.08:29:56.69#ibcon#about to clear, iclass 30 cls_cnt 0 2006.161.08:29:56.69#ibcon#cleared, iclass 30 cls_cnt 0 2006.161.08:29:56.69$vc4f8/vb=3,4 2006.161.08:29:56.69#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.161.08:29:56.69#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.161.08:29:56.69#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:56.69#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:56.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:56.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:56.75#ibcon#enter wrdev, iclass 32, count 2 2006.161.08:29:56.75#ibcon#first serial, iclass 32, count 2 2006.161.08:29:56.75#ibcon#enter sib2, iclass 32, count 2 2006.161.08:29:56.75#ibcon#flushed, iclass 32, count 2 2006.161.08:29:56.75#ibcon#about to write, iclass 32, count 2 2006.161.08:29:56.75#ibcon#wrote, iclass 32, count 2 2006.161.08:29:56.75#ibcon#about to read 3, iclass 32, count 2 2006.161.08:29:56.77#ibcon#read 3, iclass 32, count 2 2006.161.08:29:56.77#ibcon#about to read 4, iclass 32, count 2 2006.161.08:29:56.77#ibcon#read 4, iclass 32, count 2 2006.161.08:29:56.77#ibcon#about to read 5, iclass 32, count 2 2006.161.08:29:56.77#ibcon#read 5, iclass 32, count 2 2006.161.08:29:56.77#ibcon#about to read 6, iclass 32, count 2 2006.161.08:29:56.77#ibcon#read 6, iclass 32, count 2 2006.161.08:29:56.77#ibcon#end of sib2, iclass 32, count 2 2006.161.08:29:56.77#ibcon#*mode == 0, iclass 32, count 2 2006.161.08:29:56.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.161.08:29:56.77#ibcon#[27=AT03-04\r\n] 2006.161.08:29:56.77#ibcon#*before write, iclass 32, count 2 2006.161.08:29:56.77#ibcon#enter sib2, iclass 32, count 2 2006.161.08:29:56.77#ibcon#flushed, iclass 32, count 2 2006.161.08:29:56.77#ibcon#about to write, iclass 32, count 2 2006.161.08:29:56.77#ibcon#wrote, iclass 32, count 2 2006.161.08:29:56.77#ibcon#about to read 3, iclass 32, count 2 2006.161.08:29:56.80#ibcon#read 3, iclass 32, count 2 2006.161.08:29:56.80#ibcon#about to read 4, iclass 32, count 2 2006.161.08:29:56.80#ibcon#read 4, iclass 32, count 2 2006.161.08:29:56.80#ibcon#about to read 5, iclass 32, count 2 2006.161.08:29:56.80#ibcon#read 5, iclass 32, count 2 2006.161.08:29:56.80#ibcon#about to read 6, iclass 32, count 2 2006.161.08:29:56.80#ibcon#read 6, iclass 32, count 2 2006.161.08:29:56.80#ibcon#end of sib2, iclass 32, count 2 2006.161.08:29:56.80#ibcon#*after write, iclass 32, count 2 2006.161.08:29:56.80#ibcon#*before return 0, iclass 32, count 2 2006.161.08:29:56.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:56.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.161.08:29:56.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.161.08:29:56.80#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:56.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:56.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:56.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:56.92#ibcon#enter wrdev, iclass 32, count 0 2006.161.08:29:56.92#ibcon#first serial, iclass 32, count 0 2006.161.08:29:56.92#ibcon#enter sib2, iclass 32, count 0 2006.161.08:29:56.92#ibcon#flushed, iclass 32, count 0 2006.161.08:29:56.92#ibcon#about to write, iclass 32, count 0 2006.161.08:29:56.92#ibcon#wrote, iclass 32, count 0 2006.161.08:29:56.92#ibcon#about to read 3, iclass 32, count 0 2006.161.08:29:56.94#ibcon#read 3, iclass 32, count 0 2006.161.08:29:56.94#ibcon#about to read 4, iclass 32, count 0 2006.161.08:29:56.94#ibcon#read 4, iclass 32, count 0 2006.161.08:29:56.94#ibcon#about to read 5, iclass 32, count 0 2006.161.08:29:56.94#ibcon#read 5, iclass 32, count 0 2006.161.08:29:56.94#ibcon#about to read 6, iclass 32, count 0 2006.161.08:29:56.94#ibcon#read 6, iclass 32, count 0 2006.161.08:29:56.94#ibcon#end of sib2, iclass 32, count 0 2006.161.08:29:56.94#ibcon#*mode == 0, iclass 32, count 0 2006.161.08:29:56.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.161.08:29:56.94#ibcon#[27=USB\r\n] 2006.161.08:29:56.94#ibcon#*before write, iclass 32, count 0 2006.161.08:29:56.94#ibcon#enter sib2, iclass 32, count 0 2006.161.08:29:56.94#ibcon#flushed, iclass 32, count 0 2006.161.08:29:56.94#ibcon#about to write, iclass 32, count 0 2006.161.08:29:56.94#ibcon#wrote, iclass 32, count 0 2006.161.08:29:56.94#ibcon#about to read 3, iclass 32, count 0 2006.161.08:29:56.97#ibcon#read 3, iclass 32, count 0 2006.161.08:29:56.97#ibcon#about to read 4, iclass 32, count 0 2006.161.08:29:56.97#ibcon#read 4, iclass 32, count 0 2006.161.08:29:56.97#ibcon#about to read 5, iclass 32, count 0 2006.161.08:29:56.97#ibcon#read 5, iclass 32, count 0 2006.161.08:29:56.97#ibcon#about to read 6, iclass 32, count 0 2006.161.08:29:56.97#ibcon#read 6, iclass 32, count 0 2006.161.08:29:56.97#ibcon#end of sib2, iclass 32, count 0 2006.161.08:29:56.97#ibcon#*after write, iclass 32, count 0 2006.161.08:29:56.97#ibcon#*before return 0, iclass 32, count 0 2006.161.08:29:56.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:56.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.161.08:29:56.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.161.08:29:56.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.161.08:29:56.97$vc4f8/vblo=4,712.99 2006.161.08:29:56.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.161.08:29:56.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.161.08:29:56.97#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:56.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:56.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:56.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:56.97#ibcon#enter wrdev, iclass 34, count 0 2006.161.08:29:56.97#ibcon#first serial, iclass 34, count 0 2006.161.08:29:56.97#ibcon#enter sib2, iclass 34, count 0 2006.161.08:29:56.97#ibcon#flushed, iclass 34, count 0 2006.161.08:29:56.97#ibcon#about to write, iclass 34, count 0 2006.161.08:29:56.97#ibcon#wrote, iclass 34, count 0 2006.161.08:29:56.97#ibcon#about to read 3, iclass 34, count 0 2006.161.08:29:56.99#ibcon#read 3, iclass 34, count 0 2006.161.08:29:56.99#ibcon#about to read 4, iclass 34, count 0 2006.161.08:29:56.99#ibcon#read 4, iclass 34, count 0 2006.161.08:29:56.99#ibcon#about to read 5, iclass 34, count 0 2006.161.08:29:56.99#ibcon#read 5, iclass 34, count 0 2006.161.08:29:56.99#ibcon#about to read 6, iclass 34, count 0 2006.161.08:29:56.99#ibcon#read 6, iclass 34, count 0 2006.161.08:29:56.99#ibcon#end of sib2, iclass 34, count 0 2006.161.08:29:56.99#ibcon#*mode == 0, iclass 34, count 0 2006.161.08:29:56.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.161.08:29:56.99#ibcon#[28=FRQ=04,712.99\r\n] 2006.161.08:29:56.99#ibcon#*before write, iclass 34, count 0 2006.161.08:29:56.99#ibcon#enter sib2, iclass 34, count 0 2006.161.08:29:56.99#ibcon#flushed, iclass 34, count 0 2006.161.08:29:56.99#ibcon#about to write, iclass 34, count 0 2006.161.08:29:56.99#ibcon#wrote, iclass 34, count 0 2006.161.08:29:56.99#ibcon#about to read 3, iclass 34, count 0 2006.161.08:29:57.03#ibcon#read 3, iclass 34, count 0 2006.161.08:29:57.03#ibcon#about to read 4, iclass 34, count 0 2006.161.08:29:57.03#ibcon#read 4, iclass 34, count 0 2006.161.08:29:57.03#ibcon#about to read 5, iclass 34, count 0 2006.161.08:29:57.03#ibcon#read 5, iclass 34, count 0 2006.161.08:29:57.03#ibcon#about to read 6, iclass 34, count 0 2006.161.08:29:57.03#ibcon#read 6, iclass 34, count 0 2006.161.08:29:57.03#ibcon#end of sib2, iclass 34, count 0 2006.161.08:29:57.03#ibcon#*after write, iclass 34, count 0 2006.161.08:29:57.03#ibcon#*before return 0, iclass 34, count 0 2006.161.08:29:57.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:57.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.161.08:29:57.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.161.08:29:57.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.161.08:29:57.03$vc4f8/vb=4,4 2006.161.08:29:57.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.161.08:29:57.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.161.08:29:57.03#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:57.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:57.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:57.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:57.09#ibcon#enter wrdev, iclass 36, count 2 2006.161.08:29:57.09#ibcon#first serial, iclass 36, count 2 2006.161.08:29:57.09#ibcon#enter sib2, iclass 36, count 2 2006.161.08:29:57.09#ibcon#flushed, iclass 36, count 2 2006.161.08:29:57.09#ibcon#about to write, iclass 36, count 2 2006.161.08:29:57.09#ibcon#wrote, iclass 36, count 2 2006.161.08:29:57.09#ibcon#about to read 3, iclass 36, count 2 2006.161.08:29:57.11#ibcon#read 3, iclass 36, count 2 2006.161.08:29:57.11#ibcon#about to read 4, iclass 36, count 2 2006.161.08:29:57.11#ibcon#read 4, iclass 36, count 2 2006.161.08:29:57.11#ibcon#about to read 5, iclass 36, count 2 2006.161.08:29:57.11#ibcon#read 5, iclass 36, count 2 2006.161.08:29:57.11#ibcon#about to read 6, iclass 36, count 2 2006.161.08:29:57.11#ibcon#read 6, iclass 36, count 2 2006.161.08:29:57.11#ibcon#end of sib2, iclass 36, count 2 2006.161.08:29:57.11#ibcon#*mode == 0, iclass 36, count 2 2006.161.08:29:57.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.161.08:29:57.11#ibcon#[27=AT04-04\r\n] 2006.161.08:29:57.11#ibcon#*before write, iclass 36, count 2 2006.161.08:29:57.11#ibcon#enter sib2, iclass 36, count 2 2006.161.08:29:57.11#ibcon#flushed, iclass 36, count 2 2006.161.08:29:57.11#ibcon#about to write, iclass 36, count 2 2006.161.08:29:57.11#ibcon#wrote, iclass 36, count 2 2006.161.08:29:57.11#ibcon#about to read 3, iclass 36, count 2 2006.161.08:29:57.15#ibcon#read 3, iclass 36, count 2 2006.161.08:29:57.15#ibcon#about to read 4, iclass 36, count 2 2006.161.08:29:57.15#ibcon#read 4, iclass 36, count 2 2006.161.08:29:57.15#ibcon#about to read 5, iclass 36, count 2 2006.161.08:29:57.15#ibcon#read 5, iclass 36, count 2 2006.161.08:29:57.15#ibcon#about to read 6, iclass 36, count 2 2006.161.08:29:57.15#ibcon#read 6, iclass 36, count 2 2006.161.08:29:57.15#ibcon#end of sib2, iclass 36, count 2 2006.161.08:29:57.15#ibcon#*after write, iclass 36, count 2 2006.161.08:29:57.15#ibcon#*before return 0, iclass 36, count 2 2006.161.08:29:57.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:57.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.161.08:29:57.15#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.161.08:29:57.15#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:57.15#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:57.27#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:57.27#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:57.27#ibcon#enter wrdev, iclass 36, count 0 2006.161.08:29:57.27#ibcon#first serial, iclass 36, count 0 2006.161.08:29:57.27#ibcon#enter sib2, iclass 36, count 0 2006.161.08:29:57.27#ibcon#flushed, iclass 36, count 0 2006.161.08:29:57.27#ibcon#about to write, iclass 36, count 0 2006.161.08:29:57.27#ibcon#wrote, iclass 36, count 0 2006.161.08:29:57.27#ibcon#about to read 3, iclass 36, count 0 2006.161.08:29:57.29#ibcon#read 3, iclass 36, count 0 2006.161.08:29:57.29#ibcon#about to read 4, iclass 36, count 0 2006.161.08:29:57.29#ibcon#read 4, iclass 36, count 0 2006.161.08:29:57.29#ibcon#about to read 5, iclass 36, count 0 2006.161.08:29:57.29#ibcon#read 5, iclass 36, count 0 2006.161.08:29:57.29#ibcon#about to read 6, iclass 36, count 0 2006.161.08:29:57.29#ibcon#read 6, iclass 36, count 0 2006.161.08:29:57.29#ibcon#end of sib2, iclass 36, count 0 2006.161.08:29:57.29#ibcon#*mode == 0, iclass 36, count 0 2006.161.08:29:57.29#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.161.08:29:57.29#ibcon#[27=USB\r\n] 2006.161.08:29:57.29#ibcon#*before write, iclass 36, count 0 2006.161.08:29:57.29#ibcon#enter sib2, iclass 36, count 0 2006.161.08:29:57.29#ibcon#flushed, iclass 36, count 0 2006.161.08:29:57.29#ibcon#about to write, iclass 36, count 0 2006.161.08:29:57.29#ibcon#wrote, iclass 36, count 0 2006.161.08:29:57.29#ibcon#about to read 3, iclass 36, count 0 2006.161.08:29:57.32#ibcon#read 3, iclass 36, count 0 2006.161.08:29:57.32#ibcon#about to read 4, iclass 36, count 0 2006.161.08:29:57.32#ibcon#read 4, iclass 36, count 0 2006.161.08:29:57.32#ibcon#about to read 5, iclass 36, count 0 2006.161.08:29:57.32#ibcon#read 5, iclass 36, count 0 2006.161.08:29:57.32#ibcon#about to read 6, iclass 36, count 0 2006.161.08:29:57.32#ibcon#read 6, iclass 36, count 0 2006.161.08:29:57.32#ibcon#end of sib2, iclass 36, count 0 2006.161.08:29:57.32#ibcon#*after write, iclass 36, count 0 2006.161.08:29:57.32#ibcon#*before return 0, iclass 36, count 0 2006.161.08:29:57.32#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:57.32#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.161.08:29:57.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.161.08:29:57.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.161.08:29:57.32$vc4f8/vblo=5,744.99 2006.161.08:29:57.32#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.161.08:29:57.32#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.161.08:29:57.32#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:57.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:57.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:57.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:57.32#ibcon#enter wrdev, iclass 38, count 0 2006.161.08:29:57.32#ibcon#first serial, iclass 38, count 0 2006.161.08:29:57.32#ibcon#enter sib2, iclass 38, count 0 2006.161.08:29:57.32#ibcon#flushed, iclass 38, count 0 2006.161.08:29:57.32#ibcon#about to write, iclass 38, count 0 2006.161.08:29:57.32#ibcon#wrote, iclass 38, count 0 2006.161.08:29:57.32#ibcon#about to read 3, iclass 38, count 0 2006.161.08:29:57.34#ibcon#read 3, iclass 38, count 0 2006.161.08:29:57.34#ibcon#about to read 4, iclass 38, count 0 2006.161.08:29:57.34#ibcon#read 4, iclass 38, count 0 2006.161.08:29:57.34#ibcon#about to read 5, iclass 38, count 0 2006.161.08:29:57.34#ibcon#read 5, iclass 38, count 0 2006.161.08:29:57.34#ibcon#about to read 6, iclass 38, count 0 2006.161.08:29:57.34#ibcon#read 6, iclass 38, count 0 2006.161.08:29:57.34#ibcon#end of sib2, iclass 38, count 0 2006.161.08:29:57.34#ibcon#*mode == 0, iclass 38, count 0 2006.161.08:29:57.34#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.161.08:29:57.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.161.08:29:57.34#ibcon#*before write, iclass 38, count 0 2006.161.08:29:57.34#ibcon#enter sib2, iclass 38, count 0 2006.161.08:29:57.34#ibcon#flushed, iclass 38, count 0 2006.161.08:29:57.34#ibcon#about to write, iclass 38, count 0 2006.161.08:29:57.34#ibcon#wrote, iclass 38, count 0 2006.161.08:29:57.34#ibcon#about to read 3, iclass 38, count 0 2006.161.08:29:57.38#ibcon#read 3, iclass 38, count 0 2006.161.08:29:57.38#ibcon#about to read 4, iclass 38, count 0 2006.161.08:29:57.38#ibcon#read 4, iclass 38, count 0 2006.161.08:29:57.38#ibcon#about to read 5, iclass 38, count 0 2006.161.08:29:57.38#ibcon#read 5, iclass 38, count 0 2006.161.08:29:57.38#ibcon#about to read 6, iclass 38, count 0 2006.161.08:29:57.38#ibcon#read 6, iclass 38, count 0 2006.161.08:29:57.38#ibcon#end of sib2, iclass 38, count 0 2006.161.08:29:57.38#ibcon#*after write, iclass 38, count 0 2006.161.08:29:57.38#ibcon#*before return 0, iclass 38, count 0 2006.161.08:29:57.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:57.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.161.08:29:57.38#ibcon#about to clear, iclass 38 cls_cnt 0 2006.161.08:29:57.38#ibcon#cleared, iclass 38 cls_cnt 0 2006.161.08:29:57.38$vc4f8/vb=5,4 2006.161.08:29:57.38#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.161.08:29:57.38#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.161.08:29:57.38#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:57.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:57.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:57.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:57.44#ibcon#enter wrdev, iclass 40, count 2 2006.161.08:29:57.44#ibcon#first serial, iclass 40, count 2 2006.161.08:29:57.44#ibcon#enter sib2, iclass 40, count 2 2006.161.08:29:57.44#ibcon#flushed, iclass 40, count 2 2006.161.08:29:57.44#ibcon#about to write, iclass 40, count 2 2006.161.08:29:57.44#ibcon#wrote, iclass 40, count 2 2006.161.08:29:57.44#ibcon#about to read 3, iclass 40, count 2 2006.161.08:29:57.46#ibcon#read 3, iclass 40, count 2 2006.161.08:29:57.46#ibcon#about to read 4, iclass 40, count 2 2006.161.08:29:57.46#ibcon#read 4, iclass 40, count 2 2006.161.08:29:57.46#ibcon#about to read 5, iclass 40, count 2 2006.161.08:29:57.46#ibcon#read 5, iclass 40, count 2 2006.161.08:29:57.46#ibcon#about to read 6, iclass 40, count 2 2006.161.08:29:57.46#ibcon#read 6, iclass 40, count 2 2006.161.08:29:57.46#ibcon#end of sib2, iclass 40, count 2 2006.161.08:29:57.46#ibcon#*mode == 0, iclass 40, count 2 2006.161.08:29:57.46#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.161.08:29:57.46#ibcon#[27=AT05-04\r\n] 2006.161.08:29:57.46#ibcon#*before write, iclass 40, count 2 2006.161.08:29:57.46#ibcon#enter sib2, iclass 40, count 2 2006.161.08:29:57.46#ibcon#flushed, iclass 40, count 2 2006.161.08:29:57.46#ibcon#about to write, iclass 40, count 2 2006.161.08:29:57.46#ibcon#wrote, iclass 40, count 2 2006.161.08:29:57.46#ibcon#about to read 3, iclass 40, count 2 2006.161.08:29:57.49#ibcon#read 3, iclass 40, count 2 2006.161.08:29:57.49#ibcon#about to read 4, iclass 40, count 2 2006.161.08:29:57.49#ibcon#read 4, iclass 40, count 2 2006.161.08:29:57.49#ibcon#about to read 5, iclass 40, count 2 2006.161.08:29:57.49#ibcon#read 5, iclass 40, count 2 2006.161.08:29:57.49#ibcon#about to read 6, iclass 40, count 2 2006.161.08:29:57.49#ibcon#read 6, iclass 40, count 2 2006.161.08:29:57.49#ibcon#end of sib2, iclass 40, count 2 2006.161.08:29:57.49#ibcon#*after write, iclass 40, count 2 2006.161.08:29:57.49#ibcon#*before return 0, iclass 40, count 2 2006.161.08:29:57.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:57.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.161.08:29:57.49#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.161.08:29:57.49#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:57.49#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:57.61#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:57.61#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:57.61#ibcon#enter wrdev, iclass 40, count 0 2006.161.08:29:57.61#ibcon#first serial, iclass 40, count 0 2006.161.08:29:57.61#ibcon#enter sib2, iclass 40, count 0 2006.161.08:29:57.61#ibcon#flushed, iclass 40, count 0 2006.161.08:29:57.61#ibcon#about to write, iclass 40, count 0 2006.161.08:29:57.61#ibcon#wrote, iclass 40, count 0 2006.161.08:29:57.61#ibcon#about to read 3, iclass 40, count 0 2006.161.08:29:57.63#ibcon#read 3, iclass 40, count 0 2006.161.08:29:57.63#ibcon#about to read 4, iclass 40, count 0 2006.161.08:29:57.63#ibcon#read 4, iclass 40, count 0 2006.161.08:29:57.63#ibcon#about to read 5, iclass 40, count 0 2006.161.08:29:57.63#ibcon#read 5, iclass 40, count 0 2006.161.08:29:57.63#ibcon#about to read 6, iclass 40, count 0 2006.161.08:29:57.63#ibcon#read 6, iclass 40, count 0 2006.161.08:29:57.63#ibcon#end of sib2, iclass 40, count 0 2006.161.08:29:57.63#ibcon#*mode == 0, iclass 40, count 0 2006.161.08:29:57.63#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.161.08:29:57.63#ibcon#[27=USB\r\n] 2006.161.08:29:57.63#ibcon#*before write, iclass 40, count 0 2006.161.08:29:57.63#ibcon#enter sib2, iclass 40, count 0 2006.161.08:29:57.63#ibcon#flushed, iclass 40, count 0 2006.161.08:29:57.63#ibcon#about to write, iclass 40, count 0 2006.161.08:29:57.63#ibcon#wrote, iclass 40, count 0 2006.161.08:29:57.63#ibcon#about to read 3, iclass 40, count 0 2006.161.08:29:57.66#ibcon#read 3, iclass 40, count 0 2006.161.08:29:57.66#ibcon#about to read 4, iclass 40, count 0 2006.161.08:29:57.66#ibcon#read 4, iclass 40, count 0 2006.161.08:29:57.66#ibcon#about to read 5, iclass 40, count 0 2006.161.08:29:57.66#ibcon#read 5, iclass 40, count 0 2006.161.08:29:57.66#ibcon#about to read 6, iclass 40, count 0 2006.161.08:29:57.66#ibcon#read 6, iclass 40, count 0 2006.161.08:29:57.66#ibcon#end of sib2, iclass 40, count 0 2006.161.08:29:57.66#ibcon#*after write, iclass 40, count 0 2006.161.08:29:57.66#ibcon#*before return 0, iclass 40, count 0 2006.161.08:29:57.66#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:57.66#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.161.08:29:57.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.161.08:29:57.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.161.08:29:57.66$vc4f8/vblo=6,752.99 2006.161.08:29:57.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.161.08:29:57.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.161.08:29:57.66#ibcon#ireg 17 cls_cnt 0 2006.161.08:29:57.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:57.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:57.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:57.66#ibcon#enter wrdev, iclass 4, count 0 2006.161.08:29:57.66#ibcon#first serial, iclass 4, count 0 2006.161.08:29:57.66#ibcon#enter sib2, iclass 4, count 0 2006.161.08:29:57.66#ibcon#flushed, iclass 4, count 0 2006.161.08:29:57.66#ibcon#about to write, iclass 4, count 0 2006.161.08:29:57.66#ibcon#wrote, iclass 4, count 0 2006.161.08:29:57.66#ibcon#about to read 3, iclass 4, count 0 2006.161.08:29:57.68#ibcon#read 3, iclass 4, count 0 2006.161.08:29:57.68#ibcon#about to read 4, iclass 4, count 0 2006.161.08:29:57.68#ibcon#read 4, iclass 4, count 0 2006.161.08:29:57.68#ibcon#about to read 5, iclass 4, count 0 2006.161.08:29:57.68#ibcon#read 5, iclass 4, count 0 2006.161.08:29:57.68#ibcon#about to read 6, iclass 4, count 0 2006.161.08:29:57.68#ibcon#read 6, iclass 4, count 0 2006.161.08:29:57.68#ibcon#end of sib2, iclass 4, count 0 2006.161.08:29:57.68#ibcon#*mode == 0, iclass 4, count 0 2006.161.08:29:57.68#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.161.08:29:57.68#ibcon#[28=FRQ=06,752.99\r\n] 2006.161.08:29:57.68#ibcon#*before write, iclass 4, count 0 2006.161.08:29:57.68#ibcon#enter sib2, iclass 4, count 0 2006.161.08:29:57.68#ibcon#flushed, iclass 4, count 0 2006.161.08:29:57.68#ibcon#about to write, iclass 4, count 0 2006.161.08:29:57.68#ibcon#wrote, iclass 4, count 0 2006.161.08:29:57.68#ibcon#about to read 3, iclass 4, count 0 2006.161.08:29:57.72#ibcon#read 3, iclass 4, count 0 2006.161.08:29:57.72#ibcon#about to read 4, iclass 4, count 0 2006.161.08:29:57.72#ibcon#read 4, iclass 4, count 0 2006.161.08:29:57.72#ibcon#about to read 5, iclass 4, count 0 2006.161.08:29:57.72#ibcon#read 5, iclass 4, count 0 2006.161.08:29:57.72#ibcon#about to read 6, iclass 4, count 0 2006.161.08:29:57.72#ibcon#read 6, iclass 4, count 0 2006.161.08:29:57.72#ibcon#end of sib2, iclass 4, count 0 2006.161.08:29:57.72#ibcon#*after write, iclass 4, count 0 2006.161.08:29:57.72#ibcon#*before return 0, iclass 4, count 0 2006.161.08:29:57.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:57.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.161.08:29:57.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.161.08:29:57.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.161.08:29:57.72$vc4f8/vb=6,4 2006.161.08:29:57.72#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.161.08:29:57.72#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.161.08:29:57.72#ibcon#ireg 11 cls_cnt 2 2006.161.08:29:57.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:57.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:57.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:57.78#ibcon#enter wrdev, iclass 6, count 2 2006.161.08:29:57.78#ibcon#first serial, iclass 6, count 2 2006.161.08:29:57.78#ibcon#enter sib2, iclass 6, count 2 2006.161.08:29:57.78#ibcon#flushed, iclass 6, count 2 2006.161.08:29:57.78#ibcon#about to write, iclass 6, count 2 2006.161.08:29:57.78#ibcon#wrote, iclass 6, count 2 2006.161.08:29:57.78#ibcon#about to read 3, iclass 6, count 2 2006.161.08:29:57.80#ibcon#read 3, iclass 6, count 2 2006.161.08:29:57.80#ibcon#about to read 4, iclass 6, count 2 2006.161.08:29:57.80#ibcon#read 4, iclass 6, count 2 2006.161.08:29:57.80#ibcon#about to read 5, iclass 6, count 2 2006.161.08:29:57.80#ibcon#read 5, iclass 6, count 2 2006.161.08:29:57.80#ibcon#about to read 6, iclass 6, count 2 2006.161.08:29:57.80#ibcon#read 6, iclass 6, count 2 2006.161.08:29:57.80#ibcon#end of sib2, iclass 6, count 2 2006.161.08:29:57.80#ibcon#*mode == 0, iclass 6, count 2 2006.161.08:29:57.80#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.161.08:29:57.80#ibcon#[27=AT06-04\r\n] 2006.161.08:29:57.80#ibcon#*before write, iclass 6, count 2 2006.161.08:29:57.80#ibcon#enter sib2, iclass 6, count 2 2006.161.08:29:57.80#ibcon#flushed, iclass 6, count 2 2006.161.08:29:57.80#ibcon#about to write, iclass 6, count 2 2006.161.08:29:57.80#ibcon#wrote, iclass 6, count 2 2006.161.08:29:57.80#ibcon#about to read 3, iclass 6, count 2 2006.161.08:29:57.83#ibcon#read 3, iclass 6, count 2 2006.161.08:29:57.83#ibcon#about to read 4, iclass 6, count 2 2006.161.08:29:57.83#ibcon#read 4, iclass 6, count 2 2006.161.08:29:57.83#ibcon#about to read 5, iclass 6, count 2 2006.161.08:29:57.83#ibcon#read 5, iclass 6, count 2 2006.161.08:29:57.83#ibcon#about to read 6, iclass 6, count 2 2006.161.08:29:57.83#ibcon#read 6, iclass 6, count 2 2006.161.08:29:57.83#ibcon#end of sib2, iclass 6, count 2 2006.161.08:29:57.83#ibcon#*after write, iclass 6, count 2 2006.161.08:29:57.83#ibcon#*before return 0, iclass 6, count 2 2006.161.08:29:57.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:57.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.161.08:29:57.83#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.161.08:29:57.83#ibcon#ireg 7 cls_cnt 0 2006.161.08:29:57.83#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:57.95#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:57.95#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:57.95#ibcon#enter wrdev, iclass 6, count 0 2006.161.08:29:57.95#ibcon#first serial, iclass 6, count 0 2006.161.08:29:57.95#ibcon#enter sib2, iclass 6, count 0 2006.161.08:29:57.95#ibcon#flushed, iclass 6, count 0 2006.161.08:29:57.95#ibcon#about to write, iclass 6, count 0 2006.161.08:29:57.95#ibcon#wrote, iclass 6, count 0 2006.161.08:29:57.95#ibcon#about to read 3, iclass 6, count 0 2006.161.08:29:57.97#ibcon#read 3, iclass 6, count 0 2006.161.08:29:57.97#ibcon#about to read 4, iclass 6, count 0 2006.161.08:29:57.97#ibcon#read 4, iclass 6, count 0 2006.161.08:29:57.97#ibcon#about to read 5, iclass 6, count 0 2006.161.08:29:57.97#ibcon#read 5, iclass 6, count 0 2006.161.08:29:57.97#ibcon#about to read 6, iclass 6, count 0 2006.161.08:29:57.97#ibcon#read 6, iclass 6, count 0 2006.161.08:29:57.97#ibcon#end of sib2, iclass 6, count 0 2006.161.08:29:57.97#ibcon#*mode == 0, iclass 6, count 0 2006.161.08:29:57.97#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.161.08:29:57.97#ibcon#[27=USB\r\n] 2006.161.08:29:57.97#ibcon#*before write, iclass 6, count 0 2006.161.08:29:57.97#ibcon#enter sib2, iclass 6, count 0 2006.161.08:29:57.97#ibcon#flushed, iclass 6, count 0 2006.161.08:29:57.97#ibcon#about to write, iclass 6, count 0 2006.161.08:29:57.97#ibcon#wrote, iclass 6, count 0 2006.161.08:29:57.97#ibcon#about to read 3, iclass 6, count 0 2006.161.08:29:58.00#ibcon#read 3, iclass 6, count 0 2006.161.08:29:58.00#ibcon#about to read 4, iclass 6, count 0 2006.161.08:29:58.00#ibcon#read 4, iclass 6, count 0 2006.161.08:29:58.00#ibcon#about to read 5, iclass 6, count 0 2006.161.08:29:58.00#ibcon#read 5, iclass 6, count 0 2006.161.08:29:58.00#ibcon#about to read 6, iclass 6, count 0 2006.161.08:29:58.00#ibcon#read 6, iclass 6, count 0 2006.161.08:29:58.00#ibcon#end of sib2, iclass 6, count 0 2006.161.08:29:58.00#ibcon#*after write, iclass 6, count 0 2006.161.08:29:58.00#ibcon#*before return 0, iclass 6, count 0 2006.161.08:29:58.00#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:58.00#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.161.08:29:58.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.161.08:29:58.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.161.08:29:58.00$vc4f8/vabw=wide 2006.161.08:29:58.00#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.161.08:29:58.00#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.161.08:29:58.00#ibcon#ireg 8 cls_cnt 0 2006.161.08:29:58.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:58.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:58.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:58.00#ibcon#enter wrdev, iclass 10, count 0 2006.161.08:29:58.00#ibcon#first serial, iclass 10, count 0 2006.161.08:29:58.00#ibcon#enter sib2, iclass 10, count 0 2006.161.08:29:58.00#ibcon#flushed, iclass 10, count 0 2006.161.08:29:58.00#ibcon#about to write, iclass 10, count 0 2006.161.08:29:58.00#ibcon#wrote, iclass 10, count 0 2006.161.08:29:58.00#ibcon#about to read 3, iclass 10, count 0 2006.161.08:29:58.02#ibcon#read 3, iclass 10, count 0 2006.161.08:29:58.02#ibcon#about to read 4, iclass 10, count 0 2006.161.08:29:58.02#ibcon#read 4, iclass 10, count 0 2006.161.08:29:58.02#ibcon#about to read 5, iclass 10, count 0 2006.161.08:29:58.02#ibcon#read 5, iclass 10, count 0 2006.161.08:29:58.02#ibcon#about to read 6, iclass 10, count 0 2006.161.08:29:58.02#ibcon#read 6, iclass 10, count 0 2006.161.08:29:58.02#ibcon#end of sib2, iclass 10, count 0 2006.161.08:29:58.02#ibcon#*mode == 0, iclass 10, count 0 2006.161.08:29:58.02#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.161.08:29:58.02#ibcon#[25=BW32\r\n] 2006.161.08:29:58.02#ibcon#*before write, iclass 10, count 0 2006.161.08:29:58.02#ibcon#enter sib2, iclass 10, count 0 2006.161.08:29:58.02#ibcon#flushed, iclass 10, count 0 2006.161.08:29:58.02#ibcon#about to write, iclass 10, count 0 2006.161.08:29:58.02#ibcon#wrote, iclass 10, count 0 2006.161.08:29:58.02#ibcon#about to read 3, iclass 10, count 0 2006.161.08:29:58.05#abcon#<5=/06 2.6 4.9 23.95 871002.6\r\n> 2006.161.08:29:58.05#ibcon#read 3, iclass 10, count 0 2006.161.08:29:58.05#ibcon#about to read 4, iclass 10, count 0 2006.161.08:29:58.05#ibcon#read 4, iclass 10, count 0 2006.161.08:29:58.05#ibcon#about to read 5, iclass 10, count 0 2006.161.08:29:58.05#ibcon#read 5, iclass 10, count 0 2006.161.08:29:58.05#ibcon#about to read 6, iclass 10, count 0 2006.161.08:29:58.05#ibcon#read 6, iclass 10, count 0 2006.161.08:29:58.05#ibcon#end of sib2, iclass 10, count 0 2006.161.08:29:58.05#ibcon#*after write, iclass 10, count 0 2006.161.08:29:58.05#ibcon#*before return 0, iclass 10, count 0 2006.161.08:29:58.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:58.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.161.08:29:58.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.161.08:29:58.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.161.08:29:58.05$vc4f8/vbbw=wide 2006.161.08:29:58.05#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.161.08:29:58.05#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.161.08:29:58.05#ibcon#ireg 8 cls_cnt 0 2006.161.08:29:58.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:29:58.07#abcon#{5=INTERFACE CLEAR} 2006.161.08:29:58.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:29:58.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:29:58.12#ibcon#enter wrdev, iclass 15, count 0 2006.161.08:29:58.12#ibcon#first serial, iclass 15, count 0 2006.161.08:29:58.12#ibcon#enter sib2, iclass 15, count 0 2006.161.08:29:58.12#ibcon#flushed, iclass 15, count 0 2006.161.08:29:58.12#ibcon#about to write, iclass 15, count 0 2006.161.08:29:58.12#ibcon#wrote, iclass 15, count 0 2006.161.08:29:58.12#ibcon#about to read 3, iclass 15, count 0 2006.161.08:29:58.13#abcon#[5=S1D000X0/0*\r\n] 2006.161.08:29:58.14#ibcon#read 3, iclass 15, count 0 2006.161.08:29:58.14#ibcon#about to read 4, iclass 15, count 0 2006.161.08:29:58.14#ibcon#read 4, iclass 15, count 0 2006.161.08:29:58.14#ibcon#about to read 5, iclass 15, count 0 2006.161.08:29:58.14#ibcon#read 5, iclass 15, count 0 2006.161.08:29:58.14#ibcon#about to read 6, iclass 15, count 0 2006.161.08:29:58.14#ibcon#read 6, iclass 15, count 0 2006.161.08:29:58.14#ibcon#end of sib2, iclass 15, count 0 2006.161.08:29:58.14#ibcon#*mode == 0, iclass 15, count 0 2006.161.08:29:58.14#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.161.08:29:58.14#ibcon#[27=BW32\r\n] 2006.161.08:29:58.14#ibcon#*before write, iclass 15, count 0 2006.161.08:29:58.14#ibcon#enter sib2, iclass 15, count 0 2006.161.08:29:58.14#ibcon#flushed, iclass 15, count 0 2006.161.08:29:58.14#ibcon#about to write, iclass 15, count 0 2006.161.08:29:58.14#ibcon#wrote, iclass 15, count 0 2006.161.08:29:58.14#ibcon#about to read 3, iclass 15, count 0 2006.161.08:29:58.17#ibcon#read 3, iclass 15, count 0 2006.161.08:29:58.17#ibcon#about to read 4, iclass 15, count 0 2006.161.08:29:58.17#ibcon#read 4, iclass 15, count 0 2006.161.08:29:58.17#ibcon#about to read 5, iclass 15, count 0 2006.161.08:29:58.17#ibcon#read 5, iclass 15, count 0 2006.161.08:29:58.17#ibcon#about to read 6, iclass 15, count 0 2006.161.08:29:58.17#ibcon#read 6, iclass 15, count 0 2006.161.08:29:58.17#ibcon#end of sib2, iclass 15, count 0 2006.161.08:29:58.17#ibcon#*after write, iclass 15, count 0 2006.161.08:29:58.17#ibcon#*before return 0, iclass 15, count 0 2006.161.08:29:58.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:29:58.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.161.08:29:58.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.161.08:29:58.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.161.08:29:58.17$4f8m12a/ifd4f 2006.161.08:29:58.17$ifd4f/lo= 2006.161.08:29:58.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.161.08:29:58.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.161.08:29:58.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.161.08:29:58.17$ifd4f/patch= 2006.161.08:29:58.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.161.08:29:58.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.161.08:29:58.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.161.08:29:58.17$4f8m12a/"form=m,16.000,1:2 2006.161.08:29:58.17$4f8m12a/"tpicd 2006.161.08:29:58.17$4f8m12a/echo=off 2006.161.08:29:58.17$4f8m12a/xlog=off 2006.161.08:29:58.17:!2006.161.08:30:20 2006.161.08:30:01.13#trakl#Source acquired 2006.161.08:30:02.13#flagr#flagr/antenna,acquired 2006.161.08:30:20.00:preob 2006.161.08:30:21.13/onsource/TRACKING 2006.161.08:30:21.13:!2006.161.08:30:30 2006.161.08:30:30.00:data_valid=on 2006.161.08:30:30.00:midob 2006.161.08:30:30.13/onsource/TRACKING 2006.161.08:30:30.13/wx/23.95,1002.5,87 2006.161.08:30:30.24/cable/+6.5011E-03 2006.161.08:30:31.33/va/01,08,usb,yes,28,30 2006.161.08:30:31.33/va/02,07,usb,yes,29,30 2006.161.08:30:31.33/va/03,06,usb,yes,30,30 2006.161.08:30:31.33/va/04,07,usb,yes,29,31 2006.161.08:30:31.33/va/05,07,usb,yes,29,31 2006.161.08:30:31.33/va/06,06,usb,yes,28,28 2006.161.08:30:31.33/va/07,06,usb,yes,29,28 2006.161.08:30:31.33/va/08,07,usb,yes,27,27 2006.161.08:30:31.56/valo/01,532.99,yes,locked 2006.161.08:30:31.56/valo/02,572.99,yes,locked 2006.161.08:30:31.56/valo/03,672.99,yes,locked 2006.161.08:30:31.56/valo/04,832.99,yes,locked 2006.161.08:30:31.56/valo/05,652.99,yes,locked 2006.161.08:30:31.56/valo/06,772.99,yes,locked 2006.161.08:30:31.56/valo/07,832.99,yes,locked 2006.161.08:30:31.56/valo/08,852.99,yes,locked 2006.161.08:30:32.65/vb/01,04,usb,yes,29,27 2006.161.08:30:32.65/vb/02,04,usb,yes,30,32 2006.161.08:30:32.65/vb/03,04,usb,yes,27,31 2006.161.08:30:32.65/vb/04,04,usb,yes,28,28 2006.161.08:30:32.65/vb/05,04,usb,yes,26,30 2006.161.08:30:32.65/vb/06,04,usb,yes,27,30 2006.161.08:30:32.65/vb/07,04,usb,yes,29,29 2006.161.08:30:32.65/vb/08,04,usb,yes,27,30 2006.161.08:30:32.88/vblo/01,632.99,yes,locked 2006.161.08:30:32.88/vblo/02,640.99,yes,locked 2006.161.08:30:32.88/vblo/03,656.99,yes,locked 2006.161.08:30:32.88/vblo/04,712.99,yes,locked 2006.161.08:30:32.88/vblo/05,744.99,yes,locked 2006.161.08:30:32.88/vblo/06,752.99,yes,locked 2006.161.08:30:32.88/vblo/07,734.99,yes,locked 2006.161.08:30:32.88/vblo/08,744.99,yes,locked 2006.161.08:30:33.03/vabw/8 2006.161.08:30:33.18/vbbw/8 2006.161.08:30:33.27/xfe/off,on,14.7 2006.161.08:30:33.64/ifatt/23,28,28,28 2006.161.08:30:34.08/fmout-gps/S +4.52E-07 2006.161.08:30:34.12:!2006.161.08:31:30 2006.161.08:31:30.00:data_valid=off 2006.161.08:31:30.00:postob 2006.161.08:31:30.18/cable/+6.4989E-03 2006.161.08:31:30.18/wx/23.93,1002.5,87 2006.161.08:31:31.08/fmout-gps/S +4.52E-07 2006.161.08:31:31.08:checkk5last 2006.161.08:31:31.08&checkk5last/chk_obsdata=1 2006.161.08:31:31.09&checkk5last/chk_obsdata=2 2006.161.08:31:31.09&checkk5last/chk_obsdata=3 2006.161.08:31:31.09&checkk5last/chk_obsdata=4 2006.161.08:31:31.10&checkk5last/k5log=1 2006.161.08:31:31.10&checkk5last/k5log=2 2006.161.08:31:31.10&checkk5last/k5log=3 2006.161.08:31:31.10&checkk5last/k5log=4 2006.161.08:31:31.10&checkk5last/obsinfo 2006.161.08:31:31.61/chk_obsdata//k5ts1/T1610830??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:31:32.28/chk_obsdata//k5ts2/T1610830??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:31:32.69/chk_obsdata//k5ts3/T1610830??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:31:33.16/chk_obsdata//k5ts4/T1610830??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.161.08:31:34.17/k5log//k5ts1_log_newline 2006.161.08:31:35.05/k5log//k5ts2_log_newline 2006.161.08:31:35.85/k5log//k5ts3_log_newline 2006.161.08:31:36.72/k5log//k5ts4_log_newline 2006.161.08:31:36.75/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.161.08:31:36.75:"sched_end 2006.161.08:31:36.75:source=idle 2006.161.08:31:37.14:stow 2006.161.08:31:37.14&stow/source=idle 2006.161.08:31:37.14&stow/"this is stow command. 2006.161.08:31:37.14&stow/antenna=m3 2006.161.08:31:37.14#flagr#flagr/antenna,new-source 2006.161.08:31:40.01:!+10m 2006.161.08:41:40.02:standby 2006.161.08:41:40.02&standby/"this is standby command. 2006.161.08:41:40.02&standby/antenna=m0 2006.161.08:41:41.01:sy=cp /usr2/log/k06161ts.log /usr2/log_backup/ 2006.161.08:41:41.10:log=k06162ts