2006.147.08:41:30.10:Log Opened: Mark IV Field System Version 9.7.7 2006.147.08:41:30.10:location,TSUKUB32,-140.09,36.10,61.0 2006.147.08:41:30.10:horizon1,0.,5.,360. 2006.147.08:41:30.11:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.147.08:41:30.11:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.147.08:41:30.12:drivev11,330,270,no 2006.147.08:41:30.12:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.147.08:41:30.12:drivev13,15.000,268,10.000,10.000,10.000 2006.147.08:41:30.13:drivev21,330,270,no 2006.147.08:41:30.13:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.147.08:41:30.19:drivev23,15.000,268,10.000,10.000,10.000 2006.147.08:41:30.19:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.147.08:41:30.20:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.147.08:41:30.20:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.147.08:41:30.20:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.147.08:41:30.21:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.147.08:41:30.21:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.147.08:41:30.22:time,-0.364,101.533,rate 2006.147.08:41:30.22:flagr,200 2006.147.08:41:30.22:proc=k06148ts 2006.147.08:41:30.28:" k06148 2006 tsukub32 t ts 2006.147.08:41:30.28:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.147.08:41:30.29:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.147.08:41:30.29:" 108 tsukub32 14 17400 2006.147.08:41:30.30:" drudg version 050216 compiled under fs 9.7.07 2006.147.08:41:30.30:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.147.08:41:30.30:!2006.148.07:19:50 2006.147.16:30:33.32?ERROR st -97 Trouble decoding pressure data 2006.147.16:30:33.32#wxget#04 3.4 5.9 17.561001006.3 2006.148.07:19:50.00:unstow 2006.148.07:19:50.00&unstow/antenna=e 2006.148.07:19:50.00&unstow/!+10s 2006.148.07:19:50.00&unstow/antenna=m2 2006.148.07:20:02.01:scan_name=148-0730,k06148,60 2006.148.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.148.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.148.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.148.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.148.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.148.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.148.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.148.07:20:03.14:ready_k5 2006.148.07:20:03.14&ready_k5/obsinfo=st 2006.148.07:20:03.14&ready_k5/autoobs=1 2006.148.07:20:03.14&ready_k5/autoobs=2 2006.148.07:20:03.14&ready_k5/autoobs=3 2006.148.07:20:03.14&ready_k5/autoobs=4 2006.148.07:20:03.14&ready_k5/obsinfo 2006.148.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.148.07:20:03.14#flagr#flagr/antenna,new-source 2006.148.07:20:06.36/autoobs//k5ts1/ autoobs started! 2006.148.07:20:09.50/autoobs//k5ts2/ autoobs started! 2006.148.07:20:12.59/autoobs//k5ts3/ autoobs started! 2006.148.07:20:15.70/autoobs//k5ts4/ autoobs started! 2006.148.07:20:15.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:20:15.73:4f8m12a=1 2006.148.07:20:15.73&4f8m12a/xlog=on 2006.148.07:20:15.73&4f8m12a/echo=on 2006.148.07:20:15.73&4f8m12a/pcalon 2006.148.07:20:15.73&4f8m12a/"tpicd=stop 2006.148.07:20:15.73&4f8m12a/vc4f8 2006.148.07:20:15.73&4f8m12a/ifd4f 2006.148.07:20:15.73&4f8m12a/"form=m,16.000,1:2 2006.148.07:20:15.73&4f8m12a/"tpicd 2006.148.07:20:15.73&4f8m12a/echo=off 2006.148.07:20:15.73&4f8m12a/xlog=off 2006.148.07:20:15.73$4f8m12a/echo=on 2006.148.07:20:15.73$4f8m12a/pcalon 2006.148.07:20:15.73&pcalon/"no phase cal control is implemented here 2006.148.07:20:15.73$pcalon/"no phase cal control is implemented here 2006.148.07:20:15.73$4f8m12a/"tpicd=stop 2006.148.07:20:15.73$4f8m12a/vc4f8 2006.148.07:20:15.73&vc4f8/valo=1,532.99 2006.148.07:20:15.73&vc4f8/va=1,8 2006.148.07:20:15.73&vc4f8/valo=2,572.99 2006.148.07:20:15.73&vc4f8/va=2,7 2006.148.07:20:15.73&vc4f8/valo=3,672.99 2006.148.07:20:15.73&vc4f8/va=3,8 2006.148.07:20:15.73&vc4f8/valo=4,832.99 2006.148.07:20:15.73&vc4f8/va=4,7 2006.148.07:20:15.73&vc4f8/valo=5,652.99 2006.148.07:20:15.73&vc4f8/va=5,6 2006.148.07:20:15.73&vc4f8/valo=6,772.99 2006.148.07:20:15.73&vc4f8/va=6,5 2006.148.07:20:15.73&vc4f8/valo=7,832.99 2006.148.07:20:15.73&vc4f8/va=7,5 2006.148.07:20:15.73&vc4f8/valo=8,852.99 2006.148.07:20:15.73&vc4f8/va=8,5 2006.148.07:20:15.73&vc4f8/vblo=1,632.99 2006.148.07:20:15.73&vc4f8/vb=1,4 2006.148.07:20:15.73&vc4f8/vblo=2,640.99 2006.148.07:20:15.73&vc4f8/vb=2,4 2006.148.07:20:15.73&vc4f8/vblo=3,656.99 2006.148.07:20:15.73&vc4f8/vb=3,4 2006.148.07:20:15.73&vc4f8/vblo=4,712.99 2006.148.07:20:15.73&vc4f8/vb=4,4 2006.148.07:20:15.73&vc4f8/vblo=5,744.99 2006.148.07:20:15.73&vc4f8/vb=5,3 2006.148.07:20:15.73&vc4f8/vblo=6,752.99 2006.148.07:20:15.73&vc4f8/vb=6,4 2006.148.07:20:15.73&vc4f8/vabw=wide 2006.148.07:20:15.73&vc4f8/vbbw=wide 2006.148.07:20:15.73$vc4f8/valo=1,532.99 2006.148.07:20:15.73#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:20:15.73#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:20:15.73#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:15.73#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:15.73#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:15.73#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:15.78#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:20:15.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:15.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:15.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:20:15.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:20:15.82$vc4f8/va=1,8 2006.148.07:20:15.82#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:20:15.82#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:20:15.82#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:15.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:15.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:15.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:15.84#ibcon#[25=AT01-08\r\n] 2006.148.07:20:15.87#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:15.87#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:15.87#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:20:15.87#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:15.87#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:15.99#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:15.99#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:16.01#ibcon#[25=USB\r\n] 2006.148.07:20:16.04#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:16.04#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:16.04#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:20:16.04#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:20:16.04$vc4f8/valo=2,572.99 2006.148.07:20:16.04#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:20:16.04#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:20:16.04#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:16.04#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:16.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:16.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:16.08#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:20:16.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:16.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:16.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:20:16.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:20:16.12$vc4f8/va=2,7 2006.148.07:20:16.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.07:20:16.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.07:20:16.12#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:16.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:16.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:16.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:16.19#ibcon#[25=AT02-07\r\n] 2006.148.07:20:16.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:16.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:16.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.07:20:16.22#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:16.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:16.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:16.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:16.37#ibcon#[25=USB\r\n] 2006.148.07:20:16.40#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:16.40#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:16.40#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:20:16.40#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:20:16.40$vc4f8/valo=3,672.99 2006.148.07:20:16.40#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:20:16.40#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:20:16.40#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:16.40#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:16.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:16.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:16.44#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:20:16.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:16.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:16.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:20:16.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:20:16.48$vc4f8/va=3,8 2006.148.07:20:16.48#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:20:16.48#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:20:16.48#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:16.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:16.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:16.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:16.54#ibcon#[25=AT03-08\r\n] 2006.148.07:20:16.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:16.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:16.57#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:20:16.57#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:16.57#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:16.69#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:16.69#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:16.71#ibcon#[25=USB\r\n] 2006.148.07:20:16.74#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:16.74#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:16.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:20:16.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:20:16.74$vc4f8/valo=4,832.99 2006.148.07:20:16.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:20:16.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:20:16.74#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:16.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:16.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:16.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:16.76#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:20:16.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:16.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:16.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:20:16.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:20:16.80$vc4f8/va=4,7 2006.148.07:20:16.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:20:16.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:20:16.80#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:16.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:16.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:16.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:16.88#ibcon#[25=AT04-07\r\n] 2006.148.07:20:16.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:16.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:16.91#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:20:16.91#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:16.91#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:17.03#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:17.03#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:17.05#ibcon#[25=USB\r\n] 2006.148.07:20:17.08#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:17.08#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:17.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:20:17.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:20:17.08$vc4f8/valo=5,652.99 2006.148.07:20:17.08#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:20:17.08#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:20:17.08#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:17.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:17.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:17.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:17.10#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:20:17.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:17.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:17.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:20:17.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:20:17.14$vc4f8/va=5,6 2006.148.07:20:17.14#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:20:17.14#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:20:17.14#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:17.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:17.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:17.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:17.22#ibcon#[25=AT05-06\r\n] 2006.148.07:20:17.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:17.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:17.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:20:17.25#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:17.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:17.37#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:17.37#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:17.39#ibcon#[25=USB\r\n] 2006.148.07:20:17.42#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:17.42#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:17.42#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:20:17.42#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:20:17.42$vc4f8/valo=6,772.99 2006.148.07:20:17.42#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:20:17.42#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:20:17.42#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:17.42#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:17.42#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:17.42#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:17.44#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:20:17.48#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:17.48#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:17.48#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:20:17.48#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:20:17.48$vc4f8/va=6,5 2006.148.07:20:17.48#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.07:20:17.48#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.07:20:17.48#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:17.48#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:17.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:17.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:17.56#ibcon#[25=AT06-05\r\n] 2006.148.07:20:17.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:17.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:17.59#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.07:20:17.59#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:17.59#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:20:17.71#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:20:17.71#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:20:17.73#ibcon#[25=USB\r\n] 2006.148.07:20:17.76#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:20:17.76#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:20:17.76#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:20:17.76#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:20:17.76$vc4f8/valo=7,832.99 2006.148.07:20:17.76#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:20:17.76#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:20:17.76#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:17.76#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:20:17.76#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:20:17.76#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:20:17.78#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:20:17.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:20:17.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:20:17.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:20:17.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:20:17.82$vc4f8/va=7,5 2006.148.07:20:17.82#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:20:17.82#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:20:17.82#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:17.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:20:17.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:20:17.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:20:17.90#ibcon#[25=AT07-05\r\n] 2006.148.07:20:17.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:20:17.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:20:17.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:20:17.93#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:17.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:20:18.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:20:18.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:20:18.07#ibcon#[25=USB\r\n] 2006.148.07:20:18.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:20:18.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:20:18.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:20:18.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:20:18.10$vc4f8/valo=8,852.99 2006.148.07:20:18.10#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:20:18.10#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:20:18.10#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:18.10#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:20:18.10#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:20:18.10#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:20:18.12#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:20:18.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:20:18.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:20:18.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:20:18.16#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:20:18.16$vc4f8/va=8,5 2006.148.07:20:18.16#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:20:18.16#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:20:18.16#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:18.16#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:20:18.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:20:18.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:20:18.24#ibcon#[25=AT08-05\r\n] 2006.148.07:20:18.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:20:18.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:20:18.27#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:20:18.27#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:18.27#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:20:18.39#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:20:18.39#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:20:18.41#ibcon#[25=USB\r\n] 2006.148.07:20:18.44#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:20:18.44#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:20:18.44#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:20:18.44#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:20:18.44$vc4f8/vblo=1,632.99 2006.148.07:20:18.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:20:18.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:20:18.44#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:18.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:20:18.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:20:18.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:20:18.46#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:20:18.50#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:20:18.50#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:20:18.50#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:20:18.50#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:20:18.50$vc4f8/vb=1,4 2006.148.07:20:18.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:20:18.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:20:18.50#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:18.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:20:18.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:20:18.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:20:18.52#ibcon#[27=AT01-04\r\n] 2006.148.07:20:18.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:20:18.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:20:18.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:20:18.55#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:18.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:20:18.67#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:20:18.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:20:18.69#ibcon#[27=USB\r\n] 2006.148.07:20:18.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:20:18.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:20:18.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:20:18.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:20:18.72$vc4f8/vblo=2,640.99 2006.148.07:20:18.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:20:18.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:20:18.72#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:18.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:18.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:18.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:18.74#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:20:18.78#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:18.78#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:20:18.78#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:20:18.78#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:20:18.78$vc4f8/vb=2,4 2006.148.07:20:18.78#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:20:18.78#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:20:18.78#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:18.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:18.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:18.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:18.86#ibcon#[27=AT02-04\r\n] 2006.148.07:20:18.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:18.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:20:18.89#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:20:18.89#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:18.89#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:19.01#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:19.01#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:19.03#ibcon#[27=USB\r\n] 2006.148.07:20:19.06#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:19.06#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:20:19.06#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:20:19.06#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:20:19.06$vc4f8/vblo=3,656.99 2006.148.07:20:19.06#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:20:19.06#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:20:19.06#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:19.06#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:19.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:19.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:19.08#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:20:19.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:19.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:20:19.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:20:19.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:20:19.12$vc4f8/vb=3,4 2006.148.07:20:19.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.07:20:19.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.07:20:19.12#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:19.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:19.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:19.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:19.20#ibcon#[27=AT03-04\r\n] 2006.148.07:20:19.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:19.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:20:19.23#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.07:20:19.23#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:19.23#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:19.35#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:19.35#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:19.38#ibcon#[27=USB\r\n] 2006.148.07:20:19.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:19.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:20:19.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:20:19.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:20:19.41$vc4f8/vblo=4,712.99 2006.148.07:20:19.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:20:19.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:20:19.41#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:19.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:19.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:19.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:19.43#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:20:19.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:19.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:20:19.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:20:19.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:20:19.47$vc4f8/vb=4,4 2006.148.07:20:19.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:20:19.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:20:19.47#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:19.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:19.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:19.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:19.55#ibcon#[27=AT04-04\r\n] 2006.148.07:20:19.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:19.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:20:19.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:20:19.58#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:19.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:19.70#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:19.70#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:19.72#ibcon#[27=USB\r\n] 2006.148.07:20:19.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:19.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:20:19.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:20:19.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:20:19.75$vc4f8/vblo=5,744.99 2006.148.07:20:19.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:20:19.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:20:19.75#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:19.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:19.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:19.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:19.77#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:20:19.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:19.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:20:19.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:20:19.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:20:19.81$vc4f8/vb=5,3 2006.148.07:20:19.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:20:19.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:20:19.81#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:19.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:19.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:19.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:19.89#ibcon#[27=AT05-03\r\n] 2006.148.07:20:19.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:19.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:20:19.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:20:19.92#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:19.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:20.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:20.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:20.09#ibcon#[27=USB\r\n] 2006.148.07:20:20.12#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:20.12#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:20:20.12#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:20:20.12#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:20:20.12$vc4f8/vblo=6,752.99 2006.148.07:20:20.12#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:20:20.12#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:20:20.12#ibcon#ireg 17 cls_cnt 0 2006.148.07:20:20.12#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:20.12#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:20.12#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:20.14#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:20:20.18#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:20.18#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:20:20.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:20:20.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:20:20.18$vc4f8/vb=6,4 2006.148.07:20:20.18#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:20:20.18#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:20:20.18#ibcon#ireg 11 cls_cnt 2 2006.148.07:20:20.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:20.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:20.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:20.26#ibcon#[27=AT06-04\r\n] 2006.148.07:20:20.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:20.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:20:20.29#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:20:20.29#ibcon#ireg 7 cls_cnt 0 2006.148.07:20:20.29#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:20.41#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:20.41#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:20.43#ibcon#[27=USB\r\n] 2006.148.07:20:20.46#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:20.46#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:20:20.46#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:20:20.46#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:20:20.46$vc4f8/vabw=wide 2006.148.07:20:20.46#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:20:20.46#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:20:20.46#ibcon#ireg 8 cls_cnt 0 2006.148.07:20:20.46#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:20.46#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:20.46#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:20.48#ibcon#[25=BW32\r\n] 2006.148.07:20:20.51#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:20.51#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:20:20.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:20:20.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:20:20.51$vc4f8/vbbw=wide 2006.148.07:20:20.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:20:20.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:20:20.51#ibcon#ireg 8 cls_cnt 0 2006.148.07:20:20.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:20:20.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:20:20.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:20:20.60#ibcon#[27=BW32\r\n] 2006.148.07:20:20.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:20:20.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:20:20.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:20:20.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:20:20.63$4f8m12a/ifd4f 2006.148.07:20:20.63&ifd4f/lo= 2006.148.07:20:20.63&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:20:20.63&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:20:20.63&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:20:20.63&ifd4f/patch= 2006.148.07:20:20.63&ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:20:20.63&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:20:20.63&ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:20:20.63$ifd4f/lo= 2006.148.07:20:20.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:20:20.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:20:20.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:20:20.63$ifd4f/patch= 2006.148.07:20:20.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:20:20.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:20:20.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:20:20.63$4f8m12a/"form=m,16.000,1:2 2006.148.07:20:20.63$4f8m12a/"tpicd 2006.148.07:20:20.63$4f8m12a/echo=off 2006.148.07:20:20.63$4f8m12a/xlog=off 2006.148.07:20:20.63:!2006.148.07:29:50 2006.148.07:20:40.14#trakl#Source acquired 2006.148.07:20:41.14#flagr#flagr/antenna,acquired 2006.148.07:29:50.00:preob 2006.148.07:29:50.00&preob/onsource 2006.148.07:29:51.14/onsource/TRACKING 2006.148.07:29:51.14:!2006.148.07:30:00 2006.148.07:30:00.00:data_valid=on 2006.148.07:30:00.00:midob 2006.148.07:30:00.00&midob/onsource 2006.148.07:30:00.00&midob/wx 2006.148.07:30:00.00&midob/cable 2006.148.07:30:00.00&midob/va 2006.148.07:30:00.00&midob/valo 2006.148.07:30:00.00&midob/vb 2006.148.07:30:00.00&midob/vblo 2006.148.07:30:00.00&midob/vabw 2006.148.07:30:00.00&midob/vbbw 2006.148.07:30:00.00&midob/"form 2006.148.07:30:00.00&midob/xfe 2006.148.07:30:00.00&midob/ifatt 2006.148.07:30:00.00&midob/clockoff 2006.148.07:30:00.00&midob/sy=logmail 2006.148.07:30:00.00&midob/"sy=run setcl adapt & 2006.148.07:30:00.14/onsource/TRACKING 2006.148.07:30:00.14/wx/21.60,994.3,96 2006.148.07:30:00.32/cable/+6.5347E-03 2006.148.07:30:01.41/va/01,08,usb,yes,31,32 2006.148.07:30:01.41/va/02,07,usb,yes,31,32 2006.148.07:30:01.41/va/03,08,usb,yes,23,23 2006.148.07:30:01.41/va/04,07,usb,yes,31,34 2006.148.07:30:01.41/va/05,06,usb,yes,35,37 2006.148.07:30:01.41/va/06,05,usb,yes,35,35 2006.148.07:30:01.41/va/07,05,usb,yes,35,35 2006.148.07:30:01.41/va/08,05,usb,yes,38,37 2006.148.07:30:01.64/valo/01,532.99,yes,locked 2006.148.07:30:01.64/valo/02,572.99,yes,locked 2006.148.07:30:01.64/valo/03,672.99,yes,locked 2006.148.07:30:01.64/valo/04,832.99,yes,locked 2006.148.07:30:01.64/valo/05,652.99,yes,locked 2006.148.07:30:01.64/valo/06,772.99,yes,locked 2006.148.07:30:01.64/valo/07,832.99,yes,locked 2006.148.07:30:01.64/valo/08,852.99,yes,locked 2006.148.07:30:02.73/vb/01,04,usb,yes,30,29 2006.148.07:30:02.73/vb/02,04,usb,yes,32,33 2006.148.07:30:02.73/vb/03,04,usb,yes,28,32 2006.148.07:30:02.73/vb/04,04,usb,yes,29,30 2006.148.07:30:02.73/vb/05,03,usb,yes,35,39 2006.148.07:30:02.73/vb/06,04,usb,yes,29,31 2006.148.07:30:02.73/vb/07,04,usb,yes,31,31 2006.148.07:30:02.73/vb/08,03,usb,yes,35,39 2006.148.07:30:02.96/vblo/01,632.99,yes,locked 2006.148.07:30:02.96/vblo/02,640.99,yes,locked 2006.148.07:30:02.96/vblo/03,656.99,yes,locked 2006.148.07:30:02.96/vblo/04,712.99,yes,locked 2006.148.07:30:02.96/vblo/05,744.99,yes,locked 2006.148.07:30:02.96/vblo/06,752.99,yes,locked 2006.148.07:30:02.96/vblo/07,734.99,yes,locked 2006.148.07:30:02.96/vblo/08,744.99,yes,locked 2006.148.07:30:03.11/vabw/8 2006.148.07:30:03.26/vbbw/8 2006.148.07:30:03.35/xfe/off,on,15.2 2006.148.07:30:03.72/ifatt/23,28,28,28 2006.148.07:30:03.72&clockoff/"gps-fmout=1p 2006.148.07:30:03.72&clockoff/fmout-gps=1p 2006.148.07:30:04.07/fmout-gps/S +4.95E-07 2006.148.07:30:04.16:!2006.148.07:31:00 2006.148.07:31:00.01:data_valid=off 2006.148.07:31:00.01:postob 2006.148.07:31:00.02&postob/cable 2006.148.07:31:00.02&postob/wx 2006.148.07:31:00.03&postob/clockoff 2006.148.07:31:00.17/cable/+6.5346E-03 2006.148.07:31:00.17/wx/21.63,994.3,96 2006.148.07:31:00.23/fmout-gps/S +4.96E-07 2006.148.07:31:00.23:scan_name=148-0733,k06148,60 2006.148.07:31:00.24:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.148.07:31:01.14#flagr#flagr/antenna,new-source 2006.148.07:31:01.14:checkk5 2006.148.07:31:01.15&checkk5/chk_autoobs=1 2006.148.07:31:01.15&checkk5/chk_autoobs=2 2006.148.07:31:01.16&checkk5/chk_autoobs=3 2006.148.07:31:01.16&checkk5/chk_autoobs=4 2006.148.07:31:01.16&checkk5/chk_obsdata=1 2006.148.07:31:01.17&checkk5/chk_obsdata=2 2006.148.07:31:01.17&checkk5/chk_obsdata=3 2006.148.07:31:01.18&checkk5/chk_obsdata=4 2006.148.07:31:01.18&checkk5/k5log=1 2006.148.07:31:01.18&checkk5/k5log=2 2006.148.07:31:01.18&checkk5/k5log=3 2006.148.07:31:01.18&checkk5/k5log=4 2006.148.07:31:01.18&checkk5/obsinfo 2006.148.07:31:01.60/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:31:01.98/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:31:02.37/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:31:02.75/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:31:03.13/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0730*_20??1480730??.k5 file! 2006.148.07:31:03.51/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0730*_20??1480730??.k5 file! 2006.148.07:31:03.88/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0730*_20??1480730??.k5 file! 2006.148.07:31:04.26/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0730*_20??1480730??.k5 file! 2006.148.07:31:04.97/k5log//k5ts1_log_newline 2006.148.07:31:05.66/k5log//k5ts2_log_newline 2006.148.07:31:06.36/k5log//k5ts3_log_newline 2006.148.07:31:07.05/k5log//k5ts4_log_newline 2006.148.07:31:07.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:31:07.28:4f8m12a=1 2006.148.07:31:07.28$4f8m12a/echo=on 2006.148.07:31:07.28$4f8m12a/pcalon 2006.148.07:31:07.28$pcalon/"no phase cal control is implemented here 2006.148.07:31:07.28$4f8m12a/"tpicd=stop 2006.148.07:31:07.28$4f8m12a/vc4f8 2006.148.07:31:07.28$vc4f8/valo=1,532.99 2006.148.07:31:07.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:31:07.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:31:07.29#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:07.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:07.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:07.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:07.31#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:31:07.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:07.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:07.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:31:07.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:31:07.36$vc4f8/va=1,8 2006.148.07:31:07.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:31:07.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:31:07.36#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:07.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:07.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:07.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:07.38#ibcon#[25=AT01-08\r\n] 2006.148.07:31:07.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:07.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:07.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:31:07.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:07.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:07.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:07.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:07.55#ibcon#[25=USB\r\n] 2006.148.07:31:07.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:07.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:07.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:31:07.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:31:07.60$vc4f8/valo=2,572.99 2006.148.07:31:07.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:31:07.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:31:07.60#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:07.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:07.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:07.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:07.62#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:31:07.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:07.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:07.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:31:07.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:31:07.66$vc4f8/va=2,7 2006.148.07:31:07.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:31:07.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:31:07.66#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:07.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:07.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:07.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:07.74#ibcon#[25=AT02-07\r\n] 2006.148.07:31:07.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:07.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:07.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:31:07.79#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:07.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:07.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:07.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:07.93#ibcon#[25=USB\r\n] 2006.148.07:31:07.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:07.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:07.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:31:07.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:31:07.98$vc4f8/valo=3,672.99 2006.148.07:31:07.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:31:07.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:31:07.98#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:07.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:07.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:07.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:08.00#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:31:08.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:08.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:08.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:31:08.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:31:08.04$vc4f8/va=3,8 2006.148.07:31:08.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:31:08.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:31:08.04#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:08.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:08.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:08.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:08.12#ibcon#[25=AT03-08\r\n] 2006.148.07:31:08.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:08.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:08.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:31:08.15#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:08.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:08.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:08.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:08.29#ibcon#[25=USB\r\n] 2006.148.07:31:08.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:08.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:08.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:31:08.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:31:08.32$vc4f8/valo=4,832.99 2006.148.07:31:08.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:31:08.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:31:08.32#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:08.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:08.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:08.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:08.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:31:08.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:08.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:08.38#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:31:08.38#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:31:08.38$vc4f8/va=4,7 2006.148.07:31:08.38#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:31:08.38#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:31:08.38#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:08.38#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:08.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:08.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:08.46#ibcon#[25=AT04-07\r\n] 2006.148.07:31:08.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:08.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:08.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:31:08.49#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:08.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:08.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:08.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:08.63#ibcon#[25=USB\r\n] 2006.148.07:31:08.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:08.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:08.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:31:08.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:31:08.66$vc4f8/valo=5,652.99 2006.148.07:31:08.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:31:08.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:31:08.66#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:08.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:08.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:08.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:08.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:31:08.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:08.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:08.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:31:08.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:31:08.72$vc4f8/va=5,6 2006.148.07:31:08.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.07:31:08.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.07:31:08.72#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:08.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:08.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:08.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:08.80#ibcon#[25=AT05-06\r\n] 2006.148.07:31:08.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:08.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:08.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.07:31:08.83#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:08.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:08.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:08.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:08.97#ibcon#[25=USB\r\n] 2006.148.07:31:09.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:09.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:09.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:31:09.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:31:09.00$vc4f8/valo=6,772.99 2006.148.07:31:09.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:31:09.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:31:09.00#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:09.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:09.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:09.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:09.02#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:31:09.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:09.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:09.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:31:09.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:31:09.06$vc4f8/va=6,5 2006.148.07:31:09.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:31:09.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:31:09.06#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:09.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:09.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:09.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:09.14#ibcon#[25=AT06-05\r\n] 2006.148.07:31:09.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:09.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:09.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:31:09.17#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:09.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:31:09.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:31:09.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:31:09.31#ibcon#[25=USB\r\n] 2006.148.07:31:09.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:31:09.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:31:09.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:31:09.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:31:09.34$vc4f8/valo=7,832.99 2006.148.07:31:09.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:31:09.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:31:09.34#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:09.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:31:09.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:31:09.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:31:09.36#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:31:09.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:31:09.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:31:09.42#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:31:09.42#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:31:09.42$vc4f8/va=7,5 2006.148.07:31:09.42#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:31:09.42#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:31:09.42#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:09.42#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:31:09.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:31:09.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:31:09.48#ibcon#[25=AT07-05\r\n] 2006.148.07:31:09.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:31:09.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:31:09.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:31:09.51#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:09.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:31:09.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:31:09.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:31:09.65#ibcon#[25=USB\r\n] 2006.148.07:31:09.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:31:09.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:31:09.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:31:09.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:31:09.68$vc4f8/valo=8,852.99 2006.148.07:31:09.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:31:09.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:31:09.68#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:09.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:31:09.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:31:09.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:31:09.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:31:09.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:31:09.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:31:09.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:31:09.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:31:09.74$vc4f8/va=8,5 2006.148.07:31:09.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:31:09.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:31:09.74#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:09.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:31:09.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:31:09.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:31:09.82#ibcon#[25=AT08-05\r\n] 2006.148.07:31:09.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:31:09.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:31:09.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:31:09.85#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:09.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:31:09.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:31:09.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:31:09.99#ibcon#[25=USB\r\n] 2006.148.07:31:10.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:31:10.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:31:10.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:31:10.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:31:10.02$vc4f8/vblo=1,632.99 2006.148.07:31:10.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:31:10.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:31:10.02#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:10.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:31:10.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:31:10.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:31:10.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:31:10.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:31:10.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:31:10.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:31:10.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:31:10.08$vc4f8/vb=1,4 2006.148.07:31:10.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.07:31:10.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.07:31:10.08#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:10.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:31:10.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:31:10.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:31:10.10#ibcon#[27=AT01-04\r\n] 2006.148.07:31:10.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:31:10.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:31:10.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.07:31:10.13#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:10.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:31:10.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:31:10.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:31:10.27#ibcon#[27=USB\r\n] 2006.148.07:31:10.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:31:10.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:31:10.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:31:10.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:31:10.30$vc4f8/vblo=2,640.99 2006.148.07:31:10.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:31:10.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:31:10.30#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:10.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:10.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:10.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:10.32#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:31:10.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:10.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:31:10.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:31:10.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:31:10.36$vc4f8/vb=2,4 2006.148.07:31:10.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:31:10.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:31:10.36#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:10.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:10.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:10.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:10.44#ibcon#[27=AT02-04\r\n] 2006.148.07:31:10.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:10.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:31:10.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:31:10.47#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:10.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:10.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:10.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:10.61#ibcon#[27=USB\r\n] 2006.148.07:31:10.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:10.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:31:10.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:31:10.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:31:10.64$vc4f8/vblo=3,656.99 2006.148.07:31:10.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:31:10.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:31:10.64#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:10.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:10.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:10.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:10.66#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:31:10.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:10.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:31:10.70#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:31:10.70#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:31:10.70$vc4f8/vb=3,4 2006.148.07:31:10.70#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:31:10.70#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:31:10.70#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:10.70#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:10.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:10.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:10.78#ibcon#[27=AT03-04\r\n] 2006.148.07:31:10.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:10.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:31:10.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:31:10.81#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:10.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:10.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:10.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:10.95#ibcon#[27=USB\r\n] 2006.148.07:31:10.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:10.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:31:10.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:31:10.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:31:10.98$vc4f8/vblo=4,712.99 2006.148.07:31:10.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:31:10.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:31:10.98#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:10.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:10.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:10.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:11.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:31:11.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:11.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:31:11.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:31:11.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:31:11.04$vc4f8/vb=4,4 2006.148.07:31:11.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:31:11.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:31:11.04#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:11.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:11.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:11.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:11.12#ibcon#[27=AT04-04\r\n] 2006.148.07:31:11.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:11.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:31:11.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:31:11.15#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:11.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:11.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:11.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:11.29#ibcon#[27=USB\r\n] 2006.148.07:31:11.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:11.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:31:11.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:31:11.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:31:11.32$vc4f8/vblo=5,744.99 2006.148.07:31:11.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:31:11.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:31:11.32#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:11.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:11.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:11.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:11.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:31:11.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:11.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:31:11.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:31:11.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:31:11.40$vc4f8/vb=5,3 2006.148.07:31:11.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:31:11.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:31:11.40#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:11.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:11.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:11.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:11.46#ibcon#[27=AT05-03\r\n] 2006.148.07:31:11.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:11.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:31:11.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:31:11.49#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:11.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:11.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:11.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:11.63#ibcon#[27=USB\r\n] 2006.148.07:31:11.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:11.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:31:11.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:31:11.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:31:11.66$vc4f8/vblo=6,752.99 2006.148.07:31:11.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:31:11.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:31:11.66#ibcon#ireg 17 cls_cnt 0 2006.148.07:31:11.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:11.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:11.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:11.68#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:31:11.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:11.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:31:11.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:31:11.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:31:11.72$vc4f8/vb=6,4 2006.148.07:31:11.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.07:31:11.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.07:31:11.72#ibcon#ireg 11 cls_cnt 2 2006.148.07:31:11.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:11.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:11.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:11.80#ibcon#[27=AT06-04\r\n] 2006.148.07:31:11.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:11.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:31:11.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.07:31:11.83#ibcon#ireg 7 cls_cnt 0 2006.148.07:31:11.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:11.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:11.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:11.97#ibcon#[27=USB\r\n] 2006.148.07:31:12.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:12.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:31:12.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:31:12.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:31:12.00$vc4f8/vabw=wide 2006.148.07:31:12.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:31:12.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:31:12.00#ibcon#ireg 8 cls_cnt 0 2006.148.07:31:12.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:12.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:12.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:12.02#ibcon#[25=BW32\r\n] 2006.148.07:31:12.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:12.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:31:12.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:31:12.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:31:12.05$vc4f8/vbbw=wide 2006.148.07:31:12.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:31:12.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:31:12.05#ibcon#ireg 8 cls_cnt 0 2006.148.07:31:12.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:31:12.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:31:12.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:31:12.14#ibcon#[27=BW32\r\n] 2006.148.07:31:12.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:31:12.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:31:12.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:31:12.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:31:12.17$4f8m12a/ifd4f 2006.148.07:31:12.17$ifd4f/lo= 2006.148.07:31:12.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:31:12.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:31:12.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:31:12.17$ifd4f/patch= 2006.148.07:31:12.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:31:12.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:31:12.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:31:12.17$4f8m12a/"form=m,16.000,1:2 2006.148.07:31:12.17$4f8m12a/"tpicd 2006.148.07:31:12.17$4f8m12a/echo=off 2006.148.07:31:12.17$4f8m12a/xlog=off 2006.148.07:31:12.17:!2006.148.07:33:20 2006.148.07:31:47.14#trakl#Source acquired 2006.148.07:31:48.14#flagr#flagr/antenna,acquired 2006.148.07:33:20.00:preob 2006.148.07:33:20.13/onsource/TRACKING 2006.148.07:33:20.13:!2006.148.07:33:30 2006.148.07:33:30.00:data_valid=on 2006.148.07:33:30.00:midob 2006.148.07:33:30.13/onsource/TRACKING 2006.148.07:33:30.13/wx/21.65,994.3,95 2006.148.07:33:30.25/cable/+6.5360E-03 2006.148.07:33:31.34/va/01,08,usb,yes,29,31 2006.148.07:33:31.34/va/02,07,usb,yes,29,31 2006.148.07:33:31.34/va/03,08,usb,yes,22,22 2006.148.07:33:31.34/va/04,07,usb,yes,30,32 2006.148.07:33:31.34/va/05,06,usb,yes,33,35 2006.148.07:33:31.34/va/06,05,usb,yes,33,33 2006.148.07:33:31.34/va/07,05,usb,yes,33,33 2006.148.07:33:31.34/va/08,05,usb,yes,36,35 2006.148.07:33:31.57/valo/01,532.99,yes,locked 2006.148.07:33:31.57/valo/02,572.99,yes,locked 2006.148.07:33:31.57/valo/03,672.99,yes,locked 2006.148.07:33:31.57/valo/04,832.99,yes,locked 2006.148.07:33:31.57/valo/05,652.99,yes,locked 2006.148.07:33:31.57/valo/06,772.99,yes,locked 2006.148.07:33:31.57/valo/07,832.99,yes,locked 2006.148.07:33:31.57/valo/08,852.99,yes,locked 2006.148.07:33:32.66/vb/01,04,usb,yes,29,28 2006.148.07:33:32.66/vb/02,04,usb,yes,31,32 2006.148.07:33:32.66/vb/03,04,usb,yes,27,31 2006.148.07:33:32.66/vb/04,04,usb,yes,28,29 2006.148.07:33:32.66/vb/05,03,usb,yes,34,38 2006.148.07:33:32.66/vb/06,04,usb,yes,28,31 2006.148.07:33:32.66/vb/07,04,usb,yes,30,30 2006.148.07:33:32.66/vb/08,03,usb,yes,34,38 2006.148.07:33:32.89/vblo/01,632.99,yes,locked 2006.148.07:33:32.89/vblo/02,640.99,yes,locked 2006.148.07:33:32.89/vblo/03,656.99,yes,locked 2006.148.07:33:32.89/vblo/04,712.99,yes,locked 2006.148.07:33:32.89/vblo/05,744.99,yes,locked 2006.148.07:33:32.89/vblo/06,752.99,yes,locked 2006.148.07:33:32.89/vblo/07,734.99,yes,locked 2006.148.07:33:32.89/vblo/08,744.99,yes,locked 2006.148.07:33:33.04/vabw/8 2006.148.07:33:33.19/vbbw/8 2006.148.07:33:33.34/xfe/off,on,15.0 2006.148.07:33:33.73/ifatt/23,28,28,28 2006.148.07:33:34.08/fmout-gps/S +4.96E-07 2006.148.07:33:34.12:!2006.148.07:34:30 2006.148.07:34:30.01:data_valid=off 2006.148.07:34:30.01:postob 2006.148.07:34:30.21/cable/+6.5336E-03 2006.148.07:34:30.21/wx/21.65,994.3,96 2006.148.07:34:30.27/fmout-gps/S +4.96E-07 2006.148.07:34:30.27:scan_name=148-0735,k06148,60 2006.148.07:34:30.28:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.148.07:34:31.13#flagr#flagr/antenna,new-source 2006.148.07:34:31.13:checkk5 2006.148.07:34:31.51/chk_autoobs//k5ts1?ERROR: autoobs is not running! 2006.148.07:34:31.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:34:32.29/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:34:32.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:34:33.10/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0733*_20??1480733??.k5 file! 2006.148.07:34:33.48/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0733*_20??1480733??.k5 file! 2006.148.07:34:33.87/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0733*_20??1480733??.k5 file! 2006.148.07:34:34.25/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0733*_20??1480733??.k5 file! 2006.148.07:34:34.95/k5log//k5ts1_log_newline 2006.148.07:34:35.64/k5log//k5ts2_log_newline 2006.148.07:34:36.34/k5log//k5ts3_log_newline 2006.148.07:34:37.03/k5log//k5ts4_log_newline 2006.148.07:34:37.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:34:37.20:4f8m12a=1 2006.148.07:34:37.20$4f8m12a/echo=on 2006.148.07:34:37.20$4f8m12a/pcalon 2006.148.07:34:37.20$pcalon/"no phase cal control is implemented here 2006.148.07:34:37.20$4f8m12a/"tpicd=stop 2006.148.07:34:37.20$4f8m12a/vc4f8 2006.148.07:34:37.20$vc4f8/valo=1,532.99 2006.148.07:34:37.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:34:37.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:34:37.21#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:37.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:37.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:37.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:37.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:34:37.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:37.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:37.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:34:37.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:34:37.28$vc4f8/va=1,8 2006.148.07:34:37.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:34:37.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:34:37.28#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:37.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:37.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:37.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:37.30#ibcon#[25=AT01-08\r\n] 2006.148.07:34:37.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:37.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:37.33#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:34:37.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:37.33#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:37.45#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:37.45#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:37.47#ibcon#[25=USB\r\n] 2006.148.07:34:37.50#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:37.50#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:37.50#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:34:37.50#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:34:37.50$vc4f8/valo=2,572.99 2006.148.07:34:37.50#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.07:34:37.50#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.07:34:37.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:37.50#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:37.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:37.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:37.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:34:37.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:37.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:37.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:34:37.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:34:37.58$vc4f8/va=2,7 2006.148.07:34:37.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.07:34:37.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.07:34:37.58#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:37.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:37.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:37.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:37.64#ibcon#[25=AT02-07\r\n] 2006.148.07:34:37.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:37.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:37.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.07:34:37.67#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:37.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:37.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:37.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:37.81#ibcon#[25=USB\r\n] 2006.148.07:34:37.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:37.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:37.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:34:37.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:34:37.86$vc4f8/valo=3,672.99 2006.148.07:34:37.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.07:34:37.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.07:34:37.86#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:37.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:34:37.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:34:37.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:34:37.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:34:37.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:34:37.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:34:37.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:34:37.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:34:37.92$vc4f8/va=3,8 2006.148.07:34:37.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.07:34:37.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.07:34:37.92#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:37.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:34:37.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:34:37.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:34:38.00#ibcon#[25=AT03-08\r\n] 2006.148.07:34:38.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:34:38.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:34:38.05#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.07:34:38.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:38.05#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:34:38.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:34:38.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:34:38.18#ibcon#[25=USB\r\n] 2006.148.07:34:38.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:34:38.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:34:38.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:34:38.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:34:38.21$vc4f8/valo=4,832.99 2006.148.07:34:38.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:34:38.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:34:38.21#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:38.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:38.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:38.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:38.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:34:38.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:38.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:38.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:34:38.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:34:38.27$vc4f8/va=4,7 2006.148.07:34:38.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:34:38.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:34:38.27#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:38.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:38.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:38.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:38.35#ibcon#[25=AT04-07\r\n] 2006.148.07:34:38.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:38.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:38.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:34:38.38#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:38.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:38.50#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:38.50#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:38.52#ibcon#[25=USB\r\n] 2006.148.07:34:38.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:38.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:38.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:34:38.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:34:38.55$vc4f8/valo=5,652.99 2006.148.07:34:38.55#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:34:38.55#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:34:38.55#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:38.55#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:38.55#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:38.55#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:38.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:34:38.61#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:38.61#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:38.61#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:34:38.61#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:34:38.61$vc4f8/va=5,6 2006.148.07:34:38.61#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:34:38.61#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:34:38.61#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:38.61#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:38.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:38.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:38.69#ibcon#[25=AT05-06\r\n] 2006.148.07:34:38.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:38.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:38.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:34:38.72#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:38.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:38.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:38.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:38.86#ibcon#[25=USB\r\n] 2006.148.07:34:38.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:38.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:38.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:34:38.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:34:38.89$vc4f8/valo=6,772.99 2006.148.07:34:38.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:34:38.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:34:38.89#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:38.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:38.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:38.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:38.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:34:38.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:38.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:38.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:34:38.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:34:38.95$vc4f8/va=6,5 2006.148.07:34:38.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:34:38.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:34:38.95#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:38.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:39.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:39.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:39.03#ibcon#[25=AT06-05\r\n] 2006.148.07:34:39.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:39.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:39.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:34:39.06#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:39.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:39.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:39.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:39.20#ibcon#[25=USB\r\n] 2006.148.07:34:39.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:39.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:39.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:34:39.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:34:39.23$vc4f8/valo=7,832.99 2006.148.07:34:39.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.07:34:39.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.07:34:39.23#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:39.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:39.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:39.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:39.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:34:39.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:39.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:39.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:34:39.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:34:39.29$vc4f8/va=7,5 2006.148.07:34:39.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.07:34:39.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.07:34:39.29#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:39.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:39.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:39.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:39.37#ibcon#[25=AT07-05\r\n] 2006.148.07:34:39.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:39.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:39.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.07:34:39.40#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:39.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:34:39.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:34:39.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:34:39.54#ibcon#[25=USB\r\n] 2006.148.07:34:39.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:34:39.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:34:39.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:34:39.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:34:39.57$vc4f8/valo=8,852.99 2006.148.07:34:39.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.07:34:39.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.07:34:39.57#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:39.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:34:39.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:34:39.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:34:39.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:34:39.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:34:39.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:34:39.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:34:39.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:34:39.63$vc4f8/va=8,5 2006.148.07:34:39.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.07:34:39.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.07:34:39.63#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:39.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:34:39.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:34:39.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:34:39.72#ibcon#[25=AT08-05\r\n] 2006.148.07:34:39.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:34:39.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:34:39.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.07:34:39.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:39.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:34:39.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:34:39.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:34:39.89#ibcon#[25=USB\r\n] 2006.148.07:34:39.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:34:39.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:34:39.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:34:39.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:34:39.92$vc4f8/vblo=1,632.99 2006.148.07:34:39.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.07:34:39.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.07:34:39.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:39.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:34:39.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:34:39.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:34:39.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:34:39.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:34:39.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:34:39.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:34:39.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:34:39.98$vc4f8/vb=1,4 2006.148.07:34:39.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.07:34:39.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.07:34:39.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:39.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:34:39.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:34:39.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:34:40.00#ibcon#[27=AT01-04\r\n] 2006.148.07:34:40.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:34:40.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:34:40.03#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.07:34:40.03#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:40.03#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:34:40.15#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:34:40.15#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:34:40.17#ibcon#[27=USB\r\n] 2006.148.07:34:40.20#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:34:40.20#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:34:40.20#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:34:40.20#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:34:40.20$vc4f8/vblo=2,640.99 2006.148.07:34:40.20#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:34:40.20#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:34:40.20#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:40.20#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:40.20#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:40.20#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:40.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:34:40.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:40.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:34:40.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:34:40.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:34:40.26$vc4f8/vb=2,4 2006.148.07:34:40.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:34:40.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:34:40.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:40.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:40.32#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:40.32#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:40.34#ibcon#[27=AT02-04\r\n] 2006.148.07:34:40.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:40.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:34:40.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:34:40.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:40.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:40.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:40.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:40.51#ibcon#[27=USB\r\n] 2006.148.07:34:40.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:40.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:34:40.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:34:40.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:34:40.56$vc4f8/vblo=3,656.99 2006.148.07:34:40.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.07:34:40.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.07:34:40.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:40.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:40.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:40.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:40.58#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:34:40.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:40.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:34:40.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:34:40.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:34:40.62$vc4f8/vb=3,4 2006.148.07:34:40.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.07:34:40.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.07:34:40.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:40.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:40.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:40.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:40.70#ibcon#[27=AT03-04\r\n] 2006.148.07:34:40.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:40.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:34:40.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.07:34:40.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:40.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:40.74#abcon#<5=/08 1.5 4.0 21.66 96 994.3\r\n> 2006.148.07:34:40.76#abcon#{5=INTERFACE CLEAR} 2006.148.07:34:40.82#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:34:40.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:40.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:40.87#ibcon#[27=USB\r\n] 2006.148.07:34:40.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:40.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:34:40.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:34:40.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:34:40.90$vc4f8/vblo=4,712.99 2006.148.07:34:40.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:34:40.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:34:40.90#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:40.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:40.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:40.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:40.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:34:40.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:40.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:34:40.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:34:40.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:34:40.96$vc4f8/vb=4,4 2006.148.07:34:40.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:34:40.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:34:40.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:40.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:41.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:41.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:41.04#ibcon#[27=AT04-04\r\n] 2006.148.07:34:41.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:41.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:34:41.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:34:41.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:41.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:41.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:41.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:41.21#ibcon#[27=USB\r\n] 2006.148.07:34:41.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:41.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:34:41.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:34:41.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:34:41.26$vc4f8/vblo=5,744.99 2006.148.07:34:41.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:34:41.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:34:41.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:41.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:41.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:41.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:41.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:34:41.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:41.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:34:41.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:34:41.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:34:41.32$vc4f8/vb=5,3 2006.148.07:34:41.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:34:41.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:34:41.32#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:41.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:41.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:41.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:41.40#ibcon#[27=AT05-03\r\n] 2006.148.07:34:41.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:41.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:34:41.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:34:41.43#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:41.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:41.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:41.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:41.57#ibcon#[27=USB\r\n] 2006.148.07:34:41.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:41.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:34:41.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:34:41.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:34:41.60$vc4f8/vblo=6,752.99 2006.148.07:34:41.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:34:41.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:34:41.60#ibcon#ireg 17 cls_cnt 0 2006.148.07:34:41.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:41.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:41.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:41.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:34:41.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:41.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:34:41.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:34:41.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:34:41.66$vc4f8/vb=6,4 2006.148.07:34:41.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:34:41.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:34:41.66#ibcon#ireg 11 cls_cnt 2 2006.148.07:34:41.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:41.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:41.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:41.74#ibcon#[27=AT06-04\r\n] 2006.148.07:34:41.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:41.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:34:41.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:34:41.77#ibcon#ireg 7 cls_cnt 0 2006.148.07:34:41.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:41.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:41.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:41.91#ibcon#[27=USB\r\n] 2006.148.07:34:41.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:41.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:34:41.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:34:41.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:34:41.94$vc4f8/vabw=wide 2006.148.07:34:41.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.07:34:41.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.07:34:41.94#ibcon#ireg 8 cls_cnt 0 2006.148.07:34:41.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:41.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:41.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:41.96#ibcon#[25=BW32\r\n] 2006.148.07:34:41.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:41.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:34:41.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:34:41.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:34:41.99$vc4f8/vbbw=wide 2006.148.07:34:41.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:34:41.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:34:41.99#ibcon#ireg 8 cls_cnt 0 2006.148.07:34:41.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:34:42.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:34:42.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:34:42.08#ibcon#[27=BW32\r\n] 2006.148.07:34:42.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:34:42.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:34:42.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:34:42.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:34:42.11$4f8m12a/ifd4f 2006.148.07:34:42.11$ifd4f/lo= 2006.148.07:34:42.11$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:34:42.11$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:34:42.11$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:34:42.11$ifd4f/patch= 2006.148.07:34:42.11$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:34:42.11$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:34:42.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:34:42.11$4f8m12a/"form=m,16.000,1:2 2006.148.07:34:42.11$4f8m12a/"tpicd 2006.148.07:34:42.11$4f8m12a/echo=off 2006.148.07:34:42.11$4f8m12a/xlog=off 2006.148.07:34:42.11:!2006.148.07:35:10 2006.148.07:34:53.14#trakl#Source acquired 2006.148.07:34:54.14#flagr#flagr/antenna,acquired 2006.148.07:35:10.00:preob 2006.148.07:35:10.14/onsource/TRACKING 2006.148.07:35:10.14:!2006.148.07:35:20 2006.148.07:35:20.00:data_valid=on 2006.148.07:35:20.00:midob 2006.148.07:35:21.14/onsource/TRACKING 2006.148.07:35:21.14/wx/21.67,994.3,96 2006.148.07:35:21.24/cable/+6.5358E-03 2006.148.07:35:22.33/va/01,08,usb,yes,29,30 2006.148.07:35:22.33/va/02,07,usb,yes,29,30 2006.148.07:35:22.33/va/03,08,usb,yes,21,22 2006.148.07:35:22.33/va/04,07,usb,yes,29,32 2006.148.07:35:22.33/va/05,06,usb,yes,32,34 2006.148.07:35:22.33/va/06,05,usb,yes,33,33 2006.148.07:35:22.33/va/07,05,usb,yes,33,32 2006.148.07:35:22.33/va/08,05,usb,yes,35,35 2006.148.07:35:22.56/valo/01,532.99,yes,locked 2006.148.07:35:22.56/valo/02,572.99,yes,locked 2006.148.07:35:22.56/valo/03,672.99,yes,locked 2006.148.07:35:22.56/valo/04,832.99,yes,locked 2006.148.07:35:22.56/valo/05,652.99,yes,locked 2006.148.07:35:22.56/valo/06,772.99,yes,locked 2006.148.07:35:22.56/valo/07,832.99,yes,locked 2006.148.07:35:22.56/valo/08,852.99,yes,locked 2006.148.07:35:23.65/vb/01,04,usb,yes,29,27 2006.148.07:35:23.65/vb/02,04,usb,yes,30,32 2006.148.07:35:23.65/vb/03,04,usb,yes,27,30 2006.148.07:35:23.65/vb/04,04,usb,yes,28,30 2006.148.07:35:23.65/vb/05,03,usb,yes,33,37 2006.148.07:35:23.65/vb/06,04,usb,yes,27,30 2006.148.07:35:23.65/vb/07,04,usb,yes,29,29 2006.148.07:35:23.65/vb/08,03,usb,yes,33,37 2006.148.07:35:23.88/vblo/01,632.99,yes,locked 2006.148.07:35:23.88/vblo/02,640.99,yes,locked 2006.148.07:35:23.88/vblo/03,656.99,yes,locked 2006.148.07:35:23.88/vblo/04,712.99,yes,locked 2006.148.07:35:23.88/vblo/05,744.99,yes,locked 2006.148.07:35:23.88/vblo/06,752.99,yes,locked 2006.148.07:35:23.88/vblo/07,734.99,yes,locked 2006.148.07:35:23.88/vblo/08,744.99,yes,locked 2006.148.07:35:24.03/vabw/8 2006.148.07:35:24.18/vbbw/8 2006.148.07:35:24.27/xfe/off,on,14.2 2006.148.07:35:24.64/ifatt/23,28,28,28 2006.148.07:35:25.07/fmout-gps/S +4.95E-07 2006.148.07:35:25.11:!2006.148.07:36:20 2006.148.07:36:20.01:data_valid=off 2006.148.07:36:20.01:postob 2006.148.07:36:20.16/cable/+6.5327E-03 2006.148.07:36:20.16/wx/21.68,994.3,95 2006.148.07:36:21.08/fmout-gps/S +4.96E-07 2006.148.07:36:21.08:scan_name=148-0737,k06148,60 2006.148.07:36:21.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.148.07:36:21.14#flagr#flagr/antenna,new-source 2006.148.07:36:22.14:checkk5 2006.148.07:36:26.16/chk_autoobs//k5ts1?ERROR: timeout happened! 2006.148.07:36:26.54/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:36:26.93/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:36:27.31/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:36:34.34/chk_obsdata//k5ts1?ERROR: timeout happened! 2006.148.07:36:34.72/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0735*_20??1480735??.k5 file! 2006.148.07:36:35.09/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0735*_20??1480735??.k5 file! 2006.148.07:36:35.48/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0735*_20??1480735??.k5 file! 2006.148.07:36:42.58/k5log//k5ts1?ERROR: timeout happened! 2006.148.07:36:43.28/k5log//k5ts2_log_newline 2006.148.07:36:43.97/k5log//k5ts3_log_newline 2006.148.07:36:44.66/k5log//k5ts4_log_newline 2006.148.07:36:44.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:36:44.84:4f8m12a=1 2006.148.07:36:44.84$4f8m12a/echo=on 2006.148.07:36:44.84$4f8m12a/pcalon 2006.148.07:36:44.84$pcalon/"no phase cal control is implemented here 2006.148.07:36:44.84$4f8m12a/"tpicd=stop 2006.148.07:36:44.84$4f8m12a/vc4f8 2006.148.07:36:44.84$vc4f8/valo=1,532.99 2006.148.07:36:44.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:36:44.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:36:44.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:44.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:44.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:44.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:44.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:36:44.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:44.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:44.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:36:44.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:36:44.92$vc4f8/va=1,8 2006.148.07:36:44.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:36:44.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:36:44.92#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:44.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:44.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:44.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:44.94#ibcon#[25=AT01-08\r\n] 2006.148.07:36:44.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:44.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:44.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:36:44.97#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:44.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:45.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:45.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:45.11#ibcon#[25=USB\r\n] 2006.148.07:36:45.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:45.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:45.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:36:45.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:36:45.14$vc4f8/valo=2,572.99 2006.148.07:36:45.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:36:45.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:36:45.14#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:45.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:45.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:45.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:45.14#trakl#Source acquired 2006.148.07:36:45.14#flagr#flagr/antenna,acquired 2006.148.07:36:45.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:36:45.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:45.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:45.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:36:45.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:36:45.22$vc4f8/va=2,7 2006.148.07:36:45.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:36:45.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:36:45.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:45.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:45.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:45.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:45.28#ibcon#[25=AT02-07\r\n] 2006.148.07:36:45.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:45.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:45.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:36:45.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:45.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:45.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:45.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:45.45#ibcon#[25=USB\r\n] 2006.148.07:36:45.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:45.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:45.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:36:45.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:36:45.48$vc4f8/valo=3,672.99 2006.148.07:36:45.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:36:45.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:36:45.48#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:45.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:45.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:45.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:45.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:36:45.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:45.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:45.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:36:45.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:36:45.56$vc4f8/va=3,8 2006.148.07:36:45.56#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:36:45.56#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:36:45.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:45.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:45.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:45.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:45.62#ibcon#[25=AT03-08\r\n] 2006.148.07:36:45.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:45.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:45.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:36:45.65#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:45.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:45.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:45.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:45.79#ibcon#[25=USB\r\n] 2006.148.07:36:45.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:45.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:45.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:36:45.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:36:45.82$vc4f8/valo=4,832.99 2006.148.07:36:45.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:36:45.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:36:45.82#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:45.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:45.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:45.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:45.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:36:45.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:45.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:45.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:36:45.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:36:45.88$vc4f8/va=4,7 2006.148.07:36:45.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:36:45.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:36:45.88#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:45.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:45.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:45.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:45.96#ibcon#[25=AT04-07\r\n] 2006.148.07:36:45.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:45.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:45.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:36:45.99#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:45.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:46.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:46.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:46.13#ibcon#[25=USB\r\n] 2006.148.07:36:46.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:46.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:46.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:36:46.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:36:46.16$vc4f8/valo=5,652.99 2006.148.07:36:46.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:36:46.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:36:46.16#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:46.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:46.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:46.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:46.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:36:46.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:46.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:46.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:36:46.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:36:46.22$vc4f8/va=5,6 2006.148.07:36:46.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:36:46.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:36:46.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:46.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:46.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:46.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:46.30#ibcon#[25=AT05-06\r\n] 2006.148.07:36:46.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:46.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:46.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:36:46.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:46.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:46.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:46.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:46.47#ibcon#[25=USB\r\n] 2006.148.07:36:46.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:46.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:46.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:36:46.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:36:46.50$vc4f8/valo=6,772.99 2006.148.07:36:46.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:36:46.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:36:46.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:46.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:46.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:46.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:46.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:36:46.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:46.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:46.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:36:46.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:36:46.58$vc4f8/va=6,5 2006.148.07:36:46.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:36:46.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:36:46.58#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:46.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:46.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:46.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:46.64#ibcon#[25=AT06-05\r\n] 2006.148.07:36:46.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:46.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:46.67#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:36:46.67#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:46.67#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:36:46.79#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:36:46.79#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:36:46.81#ibcon#[25=USB\r\n] 2006.148.07:36:46.84#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:36:46.84#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:36:46.84#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:36:46.84#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:36:46.84$vc4f8/valo=7,832.99 2006.148.07:36:46.84#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:36:46.84#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:36:46.84#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:46.84#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:36:46.84#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:36:46.84#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:36:46.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:36:46.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:36:46.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:36:46.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:36:46.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:36:46.90$vc4f8/va=7,5 2006.148.07:36:46.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:36:46.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:36:46.90#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:46.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:36:46.96#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:36:46.96#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:36:46.98#ibcon#[25=AT07-05\r\n] 2006.148.07:36:47.01#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:36:47.01#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:36:47.01#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:36:47.01#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:47.01#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:36:47.13#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:36:47.13#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:36:47.15#ibcon#[25=USB\r\n] 2006.148.07:36:47.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:36:47.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:36:47.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:36:47.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:36:47.18$vc4f8/valo=8,852.99 2006.148.07:36:47.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:36:47.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:36:47.18#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:47.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:36:47.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:36:47.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:36:47.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:36:47.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:36:47.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:36:47.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:36:47.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:36:47.24$vc4f8/va=8,5 2006.148.07:36:47.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:36:47.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:36:47.24#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:47.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:36:47.30#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:36:47.30#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:36:47.32#ibcon#[25=AT08-05\r\n] 2006.148.07:36:47.35#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:36:47.35#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:36:47.35#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:36:47.35#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:47.35#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:36:47.47#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:36:47.47#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:36:47.49#ibcon#[25=USB\r\n] 2006.148.07:36:47.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:36:47.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:36:47.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:36:47.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:36:47.52$vc4f8/vblo=1,632.99 2006.148.07:36:47.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:36:47.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:36:47.52#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:47.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:36:47.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:36:47.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:36:47.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:36:47.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:36:47.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:36:47.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:36:47.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:36:47.58$vc4f8/vb=1,4 2006.148.07:36:47.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:36:47.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:36:47.58#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:47.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:36:47.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:36:47.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:36:47.60#ibcon#[27=AT01-04\r\n] 2006.148.07:36:47.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:36:47.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:36:47.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:36:47.63#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:47.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:36:47.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:36:47.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:36:47.77#ibcon#[27=USB\r\n] 2006.148.07:36:47.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:36:47.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:36:47.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:36:47.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:36:47.80$vc4f8/vblo=2,640.99 2006.148.07:36:47.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:36:47.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:36:47.80#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:47.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:47.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:47.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:47.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:36:47.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:47.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:36:47.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:36:47.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:36:47.86$vc4f8/vb=2,4 2006.148.07:36:47.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:36:47.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:36:47.86#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:47.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:47.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:47.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:47.94#ibcon#[27=AT02-04\r\n] 2006.148.07:36:47.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:47.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:36:47.97#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:36:47.97#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:47.97#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:48.09#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:48.09#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:48.11#ibcon#[27=USB\r\n] 2006.148.07:36:48.14#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:48.14#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:36:48.14#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:36:48.14#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:36:48.14$vc4f8/vblo=3,656.99 2006.148.07:36:48.14#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:36:48.14#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:36:48.14#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:48.14#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:48.14#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:48.14#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:48.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:36:48.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:48.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:36:48.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:36:48.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:36:48.20$vc4f8/vb=3,4 2006.148.07:36:48.20#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:36:48.20#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:36:48.20#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:48.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:48.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:48.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:48.28#ibcon#[27=AT03-04\r\n] 2006.148.07:36:48.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:48.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:36:48.31#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:36:48.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:48.31#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:48.43#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:48.43#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:48.45#ibcon#[27=USB\r\n] 2006.148.07:36:48.48#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:48.48#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:36:48.48#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:36:48.48#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:36:48.48$vc4f8/vblo=4,712.99 2006.148.07:36:48.48#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:36:48.48#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:36:48.48#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:48.48#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:48.48#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:48.48#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:48.50#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:36:48.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:48.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:36:48.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:36:48.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:36:48.54$vc4f8/vb=4,4 2006.148.07:36:48.54#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:36:48.54#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:36:48.54#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:48.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:48.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:48.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:48.62#ibcon#[27=AT04-04\r\n] 2006.148.07:36:48.65#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:48.65#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:36:48.65#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:36:48.65#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:48.65#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:48.77#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:48.77#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:48.79#ibcon#[27=USB\r\n] 2006.148.07:36:48.82#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:48.82#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:36:48.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:36:48.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:36:48.82$vc4f8/vblo=5,744.99 2006.148.07:36:48.82#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:36:48.82#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:36:48.82#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:48.82#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:48.82#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:48.82#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:48.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:36:48.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:48.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:36:48.88#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:36:48.88#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:36:48.88$vc4f8/vb=5,3 2006.148.07:36:48.88#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:36:48.88#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:36:48.88#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:48.88#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:48.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:48.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:48.96#ibcon#[27=AT05-03\r\n] 2006.148.07:36:48.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:48.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:36:48.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:36:48.99#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:48.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:49.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:49.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:49.13#ibcon#[27=USB\r\n] 2006.148.07:36:49.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:49.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:36:49.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:36:49.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:36:49.16$vc4f8/vblo=6,752.99 2006.148.07:36:49.16#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:36:49.16#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:36:49.16#ibcon#ireg 17 cls_cnt 0 2006.148.07:36:49.16#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:49.16#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:49.16#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:49.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:36:49.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:49.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:36:49.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:36:49.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:36:49.22$vc4f8/vb=6,4 2006.148.07:36:49.22#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:36:49.22#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:36:49.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:36:49.22#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:49.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:49.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:49.30#ibcon#[27=AT06-04\r\n] 2006.148.07:36:49.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:49.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:36:49.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:36:49.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:36:49.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:49.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:49.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:49.47#ibcon#[27=USB\r\n] 2006.148.07:36:49.50#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:49.50#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:36:49.50#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:36:49.50#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:36:49.50$vc4f8/vabw=wide 2006.148.07:36:49.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:36:49.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:36:49.50#ibcon#ireg 8 cls_cnt 0 2006.148.07:36:49.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:49.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:49.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:49.52#ibcon#[25=BW32\r\n] 2006.148.07:36:49.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:49.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:36:49.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:36:49.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:36:49.55$vc4f8/vbbw=wide 2006.148.07:36:49.55#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:36:49.55#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:36:49.55#ibcon#ireg 8 cls_cnt 0 2006.148.07:36:49.55#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:36:49.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:36:49.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:36:49.64#ibcon#[27=BW32\r\n] 2006.148.07:36:49.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:36:49.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:36:49.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:36:49.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:36:49.67$4f8m12a/ifd4f 2006.148.07:36:49.67$ifd4f/lo= 2006.148.07:36:49.67$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:36:49.67$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:36:49.67$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:36:49.67$ifd4f/patch= 2006.148.07:36:49.67$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:36:49.67$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:36:49.67$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:36:49.67$4f8m12a/"form=m,16.000,1:2 2006.148.07:36:49.67$4f8m12a/"tpicd 2006.148.07:36:49.67$4f8m12a/echo=off 2006.148.07:36:49.67$4f8m12a/xlog=off 2006.148.07:36:49.67:!2006.148.07:37:00 2006.148.07:37:00.00:preob 2006.148.07:37:01.14/onsource/TRACKING 2006.148.07:37:01.14:!2006.148.07:37:10 2006.148.07:37:10.00:data_valid=on 2006.148.07:37:10.00:midob 2006.148.07:37:10.14/onsource/TRACKING 2006.148.07:37:10.14/wx/21.70,994.3,95 2006.148.07:37:10.29/cable/+6.5361E-03 2006.148.07:37:11.38/va/01,08,usb,yes,29,30 2006.148.07:37:11.38/va/02,07,usb,yes,29,30 2006.148.07:37:11.38/va/03,08,usb,yes,21,22 2006.148.07:37:11.38/va/04,07,usb,yes,29,32 2006.148.07:37:11.38/va/05,06,usb,yes,32,34 2006.148.07:37:11.38/va/06,05,usb,yes,33,32 2006.148.07:37:11.38/va/07,05,usb,yes,33,32 2006.148.07:37:11.38/va/08,05,usb,yes,35,35 2006.148.07:37:11.61/valo/01,532.99,yes,locked 2006.148.07:37:11.61/valo/02,572.99,yes,locked 2006.148.07:37:11.61/valo/03,672.99,yes,locked 2006.148.07:37:11.61/valo/04,832.99,yes,locked 2006.148.07:37:11.61/valo/05,652.99,yes,locked 2006.148.07:37:11.61/valo/06,772.99,yes,locked 2006.148.07:37:11.61/valo/07,832.99,yes,locked 2006.148.07:37:11.61/valo/08,852.99,yes,locked 2006.148.07:37:12.70/vb/01,04,usb,yes,29,28 2006.148.07:37:12.70/vb/02,04,usb,yes,31,32 2006.148.07:37:12.70/vb/03,04,usb,yes,27,31 2006.148.07:37:12.70/vb/04,04,usb,yes,28,29 2006.148.07:37:12.70/vb/05,03,usb,yes,33,38 2006.148.07:37:12.70/vb/06,04,usb,yes,28,30 2006.148.07:37:12.70/vb/07,04,usb,yes,29,29 2006.148.07:37:12.70/vb/08,03,usb,yes,34,37 2006.148.07:37:12.94/vblo/01,632.99,yes,locked 2006.148.07:37:12.94/vblo/02,640.99,yes,locked 2006.148.07:37:12.94/vblo/03,656.99,yes,locked 2006.148.07:37:12.94/vblo/04,712.99,yes,locked 2006.148.07:37:12.94/vblo/05,744.99,yes,locked 2006.148.07:37:12.94/vblo/06,752.99,yes,locked 2006.148.07:37:12.94/vblo/07,734.99,yes,locked 2006.148.07:37:12.94/vblo/08,744.99,yes,locked 2006.148.07:37:13.09/vabw/8 2006.148.07:37:13.24/vbbw/8 2006.148.07:37:13.33/xfe/off,on,15.2 2006.148.07:37:13.75/ifatt/23,28,28,28 2006.148.07:37:14.08/fmout-gps/S +4.95E-07 2006.148.07:37:14.12:!2006.148.07:38:10 2006.148.07:38:10.00:data_valid=off 2006.148.07:38:10.00:postob 2006.148.07:38:10.12/cable/+6.5346E-03 2006.148.07:38:10.12/wx/21.72,994.3,95 2006.148.07:38:11.08/fmout-gps/S +4.95E-07 2006.148.07:38:11.08:scan_name=148-0739,k06148,60 2006.148.07:38:11.09:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.148.07:38:11.14#flagr#flagr/antenna,new-source 2006.148.07:38:12.14:checkk5 2006.148.07:38:12.52/chk_autoobs//k5ts1?ERROR: autoobs is not running! 2006.148.07:38:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:38:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:38:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:38:14.04/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0737*_20??1480737??.k5 file! 2006.148.07:38:14.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0737*_20??1480737??.k5 file! 2006.148.07:38:14.81/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0737*_20??1480737??.k5 file! 2006.148.07:38:15.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0737*_20??1480737??.k5 file! 2006.148.07:38:15.93/k5log//k5ts1_log_newline 2006.148.07:38:16.62/k5log//k5ts2_log_newline 2006.148.07:38:17.32/k5log//k5ts3_log_newline 2006.148.07:38:18.01/k5log//k5ts4_log_newline 2006.148.07:38:18.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:38:18.18:4f8m12a=1 2006.148.07:38:18.18$4f8m12a/echo=on 2006.148.07:38:18.18$4f8m12a/pcalon 2006.148.07:38:18.19$pcalon/"no phase cal control is implemented here 2006.148.07:38:18.19$4f8m12a/"tpicd=stop 2006.148.07:38:18.19$4f8m12a/vc4f8 2006.148.07:38:18.19$vc4f8/valo=1,532.99 2006.148.07:38:18.19#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.07:38:18.19#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.07:38:18.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:18.19#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:18.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:18.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:18.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:38:18.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:18.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:18.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:38:18.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:38:18.26$vc4f8/va=1,8 2006.148.07:38:18.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.07:38:18.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.07:38:18.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:18.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:18.26#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:18.26#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:18.28#ibcon#[25=AT01-08\r\n] 2006.148.07:38:18.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:18.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:18.31#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.07:38:18.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:18.31#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:18.43#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:18.43#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:18.45#ibcon#[25=USB\r\n] 2006.148.07:38:18.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:18.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:18.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:38:18.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:38:18.50$vc4f8/valo=2,572.99 2006.148.07:38:18.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.07:38:18.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.07:38:18.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:18.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:18.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:18.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:18.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:38:18.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:18.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:18.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:38:18.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:38:18.56$vc4f8/va=2,7 2006.148.07:38:18.56#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.07:38:18.56#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.07:38:18.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:18.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:18.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:18.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:18.64#ibcon#[25=AT02-07\r\n] 2006.148.07:38:18.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:18.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:18.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.07:38:18.69#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:18.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:18.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:18.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:18.83#ibcon#[25=USB\r\n] 2006.148.07:38:18.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:18.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:18.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:38:18.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:38:18.88$vc4f8/valo=3,672.99 2006.148.07:38:18.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:38:18.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:38:18.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:18.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:18.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:18.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:18.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:38:18.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:18.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:18.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:38:18.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:38:18.94$vc4f8/va=3,8 2006.148.07:38:18.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:38:18.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:38:18.94#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:18.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:19.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:19.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:19.02#ibcon#[25=AT03-08\r\n] 2006.148.07:38:19.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:19.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:19.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:38:19.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:19.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:19.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:19.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:19.19#ibcon#[25=USB\r\n] 2006.148.07:38:19.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:19.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:19.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:38:19.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:38:19.22$vc4f8/valo=4,832.99 2006.148.07:38:19.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.07:38:19.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.07:38:19.22#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:19.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:19.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:19.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:19.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:38:19.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:19.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:19.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:38:19.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:38:19.28$vc4f8/va=4,7 2006.148.07:38:19.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.07:38:19.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.07:38:19.28#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:19.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:19.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:19.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:19.36#ibcon#[25=AT04-07\r\n] 2006.148.07:38:19.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:19.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:19.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.07:38:19.39#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:19.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:19.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:19.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:19.53#ibcon#[25=USB\r\n] 2006.148.07:38:19.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:19.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:19.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:38:19.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:38:19.56$vc4f8/valo=5,652.99 2006.148.07:38:19.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.07:38:19.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.07:38:19.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:19.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:19.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:19.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:19.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:38:19.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:19.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:19.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:38:19.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:38:19.64$vc4f8/va=5,6 2006.148.07:38:19.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.07:38:19.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.07:38:19.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:19.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:19.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:19.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:19.70#ibcon#[25=AT05-06\r\n] 2006.148.07:38:19.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:19.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:19.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.07:38:19.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:19.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:19.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:19.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:19.87#ibcon#[25=USB\r\n] 2006.148.07:38:19.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:19.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:19.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:38:19.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:38:19.90$vc4f8/valo=6,772.99 2006.148.07:38:19.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:38:19.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:38:19.90#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:19.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:19.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:19.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:19.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:38:19.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:19.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:19.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:38:19.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:38:19.96$vc4f8/va=6,5 2006.148.07:38:19.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.07:38:19.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.07:38:19.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:19.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:20.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:20.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:20.04#ibcon#[25=AT06-05\r\n] 2006.148.07:38:20.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:20.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:20.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.07:38:20.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:20.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:38:20.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:38:20.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:38:20.21#ibcon#[25=USB\r\n] 2006.148.07:38:20.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:38:20.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:38:20.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:38:20.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:38:20.24$vc4f8/valo=7,832.99 2006.148.07:38:20.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.07:38:20.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.07:38:20.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:20.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:38:20.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:38:20.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:38:20.29#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:38:20.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:38:20.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:38:20.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:38:20.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:38:20.33$vc4f8/va=7,5 2006.148.07:38:20.33#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.07:38:20.33#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.07:38:20.33#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:20.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:38:20.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:38:20.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:38:20.38#ibcon#[25=AT07-05\r\n] 2006.148.07:38:20.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:38:20.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:38:20.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.07:38:20.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:20.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:38:20.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:38:20.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:38:20.55#ibcon#[25=USB\r\n] 2006.148.07:38:20.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:38:20.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:38:20.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:38:20.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:38:20.58$vc4f8/valo=8,852.99 2006.148.07:38:20.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.07:38:20.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.07:38:20.58#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:20.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:38:20.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:38:20.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:38:20.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:38:20.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:38:20.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:38:20.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:38:20.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:38:20.64$vc4f8/va=8,5 2006.148.07:38:20.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.07:38:20.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.07:38:20.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:20.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:38:20.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:38:20.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:38:20.72#ibcon#[25=AT08-05\r\n] 2006.148.07:38:20.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:38:20.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:38:20.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.07:38:20.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:20.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:38:20.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:38:20.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:38:20.89#ibcon#[25=USB\r\n] 2006.148.07:38:20.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:38:20.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:38:20.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:38:20.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:38:20.92$vc4f8/vblo=1,632.99 2006.148.07:38:20.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:38:20.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:38:20.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:20.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:38:20.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:38:20.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:38:20.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:38:20.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:38:20.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:38:20.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:38:20.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:38:20.98$vc4f8/vb=1,4 2006.148.07:38:20.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.07:38:20.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.07:38:20.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:20.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:38:20.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:38:20.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:38:21.01#ibcon#[27=AT01-04\r\n] 2006.148.07:38:21.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:38:21.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:38:21.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.07:38:21.04#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:21.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:38:21.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:38:21.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:38:21.18#ibcon#[27=USB\r\n] 2006.148.07:38:21.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:38:21.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:38:21.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:38:21.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:38:21.21$vc4f8/vblo=2,640.99 2006.148.07:38:21.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.07:38:21.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.07:38:21.21#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:21.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:21.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:21.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:21.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:38:21.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:21.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:38:21.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:38:21.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:38:21.27$vc4f8/vb=2,4 2006.148.07:38:21.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.07:38:21.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.07:38:21.27#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:21.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:21.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:21.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:21.35#ibcon#[27=AT02-04\r\n] 2006.148.07:38:21.38#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:21.38#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:38:21.38#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.07:38:21.38#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:21.38#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:21.50#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:21.50#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:21.52#ibcon#[27=USB\r\n] 2006.148.07:38:21.55#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:21.55#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:38:21.55#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:38:21.55#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:38:21.55$vc4f8/vblo=3,656.99 2006.148.07:38:21.55#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.07:38:21.55#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.07:38:21.55#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:21.55#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:21.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:21.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:21.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:38:21.61#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:21.61#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:38:21.61#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:38:21.61#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:38:21.61$vc4f8/vb=3,4 2006.148.07:38:21.61#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.07:38:21.61#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.07:38:21.61#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:21.61#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:21.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:21.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:21.69#ibcon#[27=AT03-04\r\n] 2006.148.07:38:21.72#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:21.72#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:38:21.72#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.07:38:21.72#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:21.72#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:21.84#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:21.84#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:21.86#ibcon#[27=USB\r\n] 2006.148.07:38:21.89#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:21.89#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:38:21.89#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:38:21.89#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:38:21.89$vc4f8/vblo=4,712.99 2006.148.07:38:21.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:38:21.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:38:21.89#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:21.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:21.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:21.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:21.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:38:21.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:21.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:38:21.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:38:21.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:38:21.95$vc4f8/vb=4,4 2006.148.07:38:21.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:38:21.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:38:21.95#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:21.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:22.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:22.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:22.03#ibcon#[27=AT04-04\r\n] 2006.148.07:38:22.06#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:22.06#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:38:22.06#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:38:22.06#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:22.06#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:22.18#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:22.18#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:22.20#ibcon#[27=USB\r\n] 2006.148.07:38:22.23#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:22.23#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:38:22.23#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:38:22.23#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:38:22.23$vc4f8/vblo=5,744.99 2006.148.07:38:22.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.07:38:22.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.07:38:22.23#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:22.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:22.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:22.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:22.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:38:22.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:22.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:38:22.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:38:22.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:38:22.29$vc4f8/vb=5,3 2006.148.07:38:22.29#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.07:38:22.29#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.07:38:22.29#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:22.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:22.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:22.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:22.37#ibcon#[27=AT05-03\r\n] 2006.148.07:38:22.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:22.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:38:22.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.07:38:22.40#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:22.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:22.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:22.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:22.54#ibcon#[27=USB\r\n] 2006.148.07:38:22.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:22.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:38:22.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:38:22.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:38:22.57$vc4f8/vblo=6,752.99 2006.148.07:38:22.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.07:38:22.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.07:38:22.57#ibcon#ireg 17 cls_cnt 0 2006.148.07:38:22.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:22.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:22.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:22.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:38:22.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:22.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:38:22.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:38:22.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:38:22.63$vc4f8/vb=6,4 2006.148.07:38:22.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.07:38:22.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.07:38:22.63#ibcon#ireg 11 cls_cnt 2 2006.148.07:38:22.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:22.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:22.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:22.71#ibcon#[27=AT06-04\r\n] 2006.148.07:38:22.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:22.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:38:22.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.07:38:22.74#ibcon#ireg 7 cls_cnt 0 2006.148.07:38:22.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:22.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:22.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:22.88#ibcon#[27=USB\r\n] 2006.148.07:38:22.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:22.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:38:22.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:38:22.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:38:22.91$vc4f8/vabw=wide 2006.148.07:38:22.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:38:22.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:38:22.91#ibcon#ireg 8 cls_cnt 0 2006.148.07:38:22.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:22.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:22.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:22.93#ibcon#[25=BW32\r\n] 2006.148.07:38:22.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:22.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:38:22.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:38:22.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:38:22.96$vc4f8/vbbw=wide 2006.148.07:38:22.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:38:22.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:38:22.96#ibcon#ireg 8 cls_cnt 0 2006.148.07:38:22.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:38:23.03#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:38:23.03#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:38:23.05#ibcon#[27=BW32\r\n] 2006.148.07:38:23.08#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:38:23.08#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:38:23.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:38:23.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:38:23.08$4f8m12a/ifd4f 2006.148.07:38:23.08$ifd4f/lo= 2006.148.07:38:23.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:38:23.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:38:23.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:38:23.08$ifd4f/patch= 2006.148.07:38:23.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:38:23.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:38:23.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:38:23.08$4f8m12a/"form=m,16.000,1:2 2006.148.07:38:23.08$4f8m12a/"tpicd 2006.148.07:38:23.08$4f8m12a/echo=off 2006.148.07:38:23.08$4f8m12a/xlog=off 2006.148.07:38:23.08:!2006.148.07:38:50 2006.148.07:38:36.14#trakl#Source acquired 2006.148.07:38:38.14#flagr#flagr/antenna,acquired 2006.148.07:38:50.00:preob 2006.148.07:38:51.14/onsource/TRACKING 2006.148.07:38:51.14:!2006.148.07:39:00 2006.148.07:38:52.27;autoobs=1 2006.148.07:38:55.47/autoobs//k5ts1/ autoobs started! 2006.148.07:39:00.00:data_valid=on 2006.148.07:39:00.00:midob 2006.148.07:39:00.14/onsource/TRACKING 2006.148.07:39:00.14/wx/21.74,994.3,95 2006.148.07:39:00.21/cable/+6.5353E-03 2006.148.07:39:01.31/va/01,08,usb,yes,34,35 2006.148.07:39:01.31/va/02,07,usb,yes,34,35 2006.148.07:39:01.31/va/03,08,usb,yes,25,26 2006.148.07:39:01.31/va/04,07,usb,yes,34,37 2006.148.07:39:01.31/va/05,06,usb,yes,38,41 2006.148.07:39:01.31/va/06,05,usb,yes,39,38 2006.148.07:39:01.31/va/07,05,usb,yes,39,38 2006.148.07:39:01.31/va/08,05,usb,yes,42,41 2006.148.07:39:01.54/valo/01,532.99,yes,locked 2006.148.07:39:01.54/valo/02,572.99,yes,locked 2006.148.07:39:01.54/valo/03,672.99,yes,locked 2006.148.07:39:01.54/valo/04,832.99,yes,locked 2006.148.07:39:01.54/valo/05,652.99,yes,locked 2006.148.07:39:01.54/valo/06,772.99,yes,locked 2006.148.07:39:01.54/valo/07,832.99,yes,locked 2006.148.07:39:01.54/valo/08,852.99,yes,locked 2006.148.07:39:02.63/vb/01,04,usb,yes,32,30 2006.148.07:39:02.63/vb/02,04,usb,yes,34,35 2006.148.07:39:02.63/vb/03,04,usb,yes,30,34 2006.148.07:39:02.63/vb/04,04,usb,yes,31,32 2006.148.07:39:02.63/vb/05,03,usb,yes,37,41 2006.148.07:39:02.63/vb/06,04,usb,yes,31,34 2006.148.07:39:02.63/vb/07,04,usb,yes,33,32 2006.148.07:39:02.63/vb/08,03,usb,yes,37,41 2006.148.07:39:02.86/vblo/01,632.99,yes,locked 2006.148.07:39:02.86/vblo/02,640.99,yes,locked 2006.148.07:39:02.86/vblo/03,656.99,yes,locked 2006.148.07:39:02.86/vblo/04,712.99,yes,locked 2006.148.07:39:02.86/vblo/05,744.99,yes,locked 2006.148.07:39:02.86/vblo/06,752.99,yes,locked 2006.148.07:39:02.86/vblo/07,734.99,yes,locked 2006.148.07:39:02.86/vblo/08,744.99,yes,locked 2006.148.07:39:03.01/vabw/8 2006.148.07:39:03.16/vbbw/8 2006.148.07:39:03.31/xfe/off,on,16.0 2006.148.07:39:03.68/ifatt/23,28,28,28 2006.148.07:39:04.08/fmout-gps/S +4.95E-07 2006.148.07:39:04.16:!2006.148.07:40:00 2006.148.07:40:00.00:data_valid=off 2006.148.07:40:00.00:postob 2006.148.07:40:00.09/cable/+6.5339E-03 2006.148.07:40:00.09/wx/21.76,994.3,95 2006.148.07:40:01.08/fmout-gps/S +4.93E-07 2006.148.07:40:01.08:scan_name=148-0741,k06148,60 2006.148.07:40:01.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.148.07:40:01.14#flagr#flagr/antenna,new-source 2006.148.07:40:02.14:checkk5 2006.148.07:40:02.54/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:40:02.93/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:40:03.31/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:40:03.69/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:40:04.07/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0739*_20??1480739??.k5 file! 2006.148.07:40:04.45/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0739*_20??1480739??.k5 file! 2006.148.07:40:04.83/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0739*_20??1480739??.k5 file! 2006.148.07:40:05.21/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0739*_20??1480739??.k5 file! 2006.148.07:40:05.92/k5log//k5ts1_log_newline 2006.148.07:40:06.62/k5log//k5ts2_log_newline 2006.148.07:40:07.31/k5log//k5ts3_log_newline 2006.148.07:40:08.01/k5log//k5ts4_log_newline 2006.148.07:40:08.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:40:08.18:4f8m12a=1 2006.148.07:40:08.18$4f8m12a/echo=on 2006.148.07:40:08.18$4f8m12a/pcalon 2006.148.07:40:08.18$pcalon/"no phase cal control is implemented here 2006.148.07:40:08.18$4f8m12a/"tpicd=stop 2006.148.07:40:08.18$4f8m12a/vc4f8 2006.148.07:40:08.18$vc4f8/valo=1,532.99 2006.148.07:40:08.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:40:08.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:40:08.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:08.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:08.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:08.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:08.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:40:08.26#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:08.26#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:08.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:40:08.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:40:08.26$vc4f8/va=1,8 2006.148.07:40:08.26#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:40:08.26#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:40:08.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:08.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:08.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:08.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:08.28#ibcon#[25=AT01-08\r\n] 2006.148.07:40:08.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:08.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:08.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:40:08.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:08.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:08.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:08.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:08.45#ibcon#[25=USB\r\n] 2006.148.07:40:08.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:08.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:08.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:40:08.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:40:08.48$vc4f8/valo=2,572.99 2006.148.07:40:08.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:40:08.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:40:08.48#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:08.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:08.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:08.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:08.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:40:08.56#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:08.56#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:08.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:40:08.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:40:08.56$vc4f8/va=2,7 2006.148.07:40:08.56#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:40:08.56#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:40:08.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:08.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:08.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:08.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:08.62#ibcon#[25=AT02-07\r\n] 2006.148.07:40:08.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:08.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:08.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:40:08.65#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:08.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:08.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:08.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:08.79#ibcon#[25=USB\r\n] 2006.148.07:40:08.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:08.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:08.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:40:08.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:40:08.82$vc4f8/valo=3,672.99 2006.148.07:40:08.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:40:08.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:40:08.82#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:08.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:08.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:08.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:08.86#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:40:08.90#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:08.90#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:08.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:40:08.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:40:08.90$vc4f8/va=3,8 2006.148.07:40:08.90#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:40:08.90#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:40:08.90#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:08.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:08.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:08.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:08.96#ibcon#[25=AT03-08\r\n] 2006.148.07:40:08.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:08.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:08.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:40:08.99#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:08.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:09.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:09.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:09.13#ibcon#[25=USB\r\n] 2006.148.07:40:09.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:09.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:09.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:40:09.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:40:09.16$vc4f8/valo=4,832.99 2006.148.07:40:09.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:40:09.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:40:09.16#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:09.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:09.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:09.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:09.18#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:40:09.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:09.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:09.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:40:09.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:40:09.22$vc4f8/va=4,7 2006.148.07:40:09.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:40:09.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:40:09.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:09.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:09.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:09.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:09.30#ibcon#[25=AT04-07\r\n] 2006.148.07:40:09.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:09.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:09.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:40:09.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:09.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:09.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:09.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:09.47#ibcon#[25=USB\r\n] 2006.148.07:40:09.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:09.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:09.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:40:09.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:40:09.50$vc4f8/valo=5,652.99 2006.148.07:40:09.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:40:09.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:40:09.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:09.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:09.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:09.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:09.52#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:40:09.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:09.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:09.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:40:09.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:40:09.56$vc4f8/va=5,6 2006.148.07:40:09.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:40:09.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:40:09.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:09.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:09.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:09.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:09.64#ibcon#[25=AT05-06\r\n] 2006.148.07:40:09.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:09.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:09.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:40:09.67#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:09.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:09.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:09.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:09.81#ibcon#[25=USB\r\n] 2006.148.07:40:09.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:09.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:09.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:40:09.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:40:09.84$vc4f8/valo=6,772.99 2006.148.07:40:09.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:40:09.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:40:09.84#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:09.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:09.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:09.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:09.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:40:09.90#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:09.90#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:09.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:40:09.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:40:09.90$vc4f8/va=6,5 2006.148.07:40:09.90#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:40:09.90#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:40:09.90#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:09.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:09.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:09.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:09.98#ibcon#[25=AT06-05\r\n] 2006.148.07:40:10.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:10.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:10.01#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:40:10.01#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:10.01#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:40:10.13#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:40:10.13#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:40:10.15#ibcon#[25=USB\r\n] 2006.148.07:40:10.18#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:40:10.18#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:40:10.18#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:40:10.18#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:40:10.18$vc4f8/valo=7,832.99 2006.148.07:40:10.18#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:40:10.18#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:40:10.18#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:10.18#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:40:10.18#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:40:10.18#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:40:10.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:40:10.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:40:10.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:40:10.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:40:10.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:40:10.24$vc4f8/va=7,5 2006.148.07:40:10.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:40:10.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:40:10.24#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:10.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:40:10.30#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:40:10.30#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:40:10.32#ibcon#[25=AT07-05\r\n] 2006.148.07:40:10.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:40:10.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:40:10.35#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:40:10.35#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:10.35#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:40:10.47#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:40:10.47#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:40:10.49#ibcon#[25=USB\r\n] 2006.148.07:40:10.52#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:40:10.52#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:40:10.52#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:40:10.52#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:40:10.52$vc4f8/valo=8,852.99 2006.148.07:40:10.52#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:40:10.52#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:40:10.52#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:10.52#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:40:10.52#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:40:10.52#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:40:10.54#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:40:10.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:40:10.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:40:10.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:40:10.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:40:10.58$vc4f8/va=8,5 2006.148.07:40:10.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:40:10.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:40:10.58#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:10.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:40:10.64#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:40:10.64#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:40:10.66#ibcon#[25=AT08-05\r\n] 2006.148.07:40:10.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:40:10.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:40:10.69#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:40:10.69#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:10.69#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:40:10.81#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:40:10.81#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:40:10.83#ibcon#[25=USB\r\n] 2006.148.07:40:10.86#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:40:10.86#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:40:10.86#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:40:10.86#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:40:10.86$vc4f8/vblo=1,632.99 2006.148.07:40:10.86#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:40:10.86#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:40:10.86#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:10.86#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:40:10.86#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:40:10.86#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:40:10.88#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:40:10.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:40:10.92#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:40:10.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:40:10.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:40:10.92$vc4f8/vb=1,4 2006.148.07:40:10.92#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:40:10.92#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:40:10.92#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:10.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:40:10.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:40:10.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:40:10.94#ibcon#[27=AT01-04\r\n] 2006.148.07:40:10.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:40:10.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:40:10.97#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:40:10.97#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:10.97#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:40:11.09#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:40:11.09#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:40:11.11#ibcon#[27=USB\r\n] 2006.148.07:40:11.14#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:40:11.14#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:40:11.14#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:40:11.14#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:40:11.14$vc4f8/vblo=2,640.99 2006.148.07:40:11.14#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:40:11.14#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:40:11.14#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:11.14#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:11.14#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:11.14#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:11.16#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:40:11.20#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:11.20#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:40:11.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:40:11.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:40:11.20$vc4f8/vb=2,4 2006.148.07:40:11.20#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:40:11.20#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:40:11.20#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:11.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:11.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:11.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:11.28#ibcon#[27=AT02-04\r\n] 2006.148.07:40:11.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:11.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:40:11.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:40:11.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:11.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:11.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:11.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:11.45#ibcon#[27=USB\r\n] 2006.148.07:40:11.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:11.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:40:11.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:40:11.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:40:11.48$vc4f8/vblo=3,656.99 2006.148.07:40:11.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:40:11.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:40:11.48#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:11.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:11.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:11.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:11.50#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:40:11.54#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:11.54#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:40:11.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:40:11.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:40:11.54$vc4f8/vb=3,4 2006.148.07:40:11.54#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:40:11.54#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:40:11.54#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:11.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:11.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:11.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:11.62#ibcon#[27=AT03-04\r\n] 2006.148.07:40:11.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:11.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:40:11.65#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:40:11.65#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:11.65#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:11.77#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:11.77#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:11.79#ibcon#[27=USB\r\n] 2006.148.07:40:11.82#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:11.82#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:40:11.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:40:11.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:40:11.82$vc4f8/vblo=4,712.99 2006.148.07:40:11.82#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:40:11.82#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:40:11.82#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:11.82#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:11.82#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:11.82#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:11.84#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:40:11.88#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:11.88#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:40:11.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:40:11.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:40:11.88$vc4f8/vb=4,4 2006.148.07:40:11.88#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:40:11.88#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:40:11.88#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:11.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:11.94#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:11.94#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:11.96#ibcon#[27=AT04-04\r\n] 2006.148.07:40:11.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:11.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:40:11.99#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:40:11.99#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:11.99#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:12.11#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:12.11#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:12.13#ibcon#[27=USB\r\n] 2006.148.07:40:12.16#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:12.16#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:40:12.16#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:40:12.16#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:40:12.16$vc4f8/vblo=5,744.99 2006.148.07:40:12.16#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:40:12.16#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:40:12.16#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:12.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:12.16#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:12.16#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:12.18#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:40:12.22#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:12.22#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:40:12.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:40:12.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:40:12.22$vc4f8/vb=5,3 2006.148.07:40:12.22#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:40:12.22#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:40:12.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:12.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:12.28#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:12.28#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:12.30#ibcon#[27=AT05-03\r\n] 2006.148.07:40:12.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:12.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:40:12.33#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:40:12.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:12.33#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:12.45#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:12.45#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:12.47#ibcon#[27=USB\r\n] 2006.148.07:40:12.50#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:12.50#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:40:12.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:40:12.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:40:12.50$vc4f8/vblo=6,752.99 2006.148.07:40:12.50#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:40:12.50#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:40:12.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:40:12.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:12.50#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:12.50#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:12.52#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:40:12.56#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:12.56#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:40:12.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:40:12.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:40:12.56$vc4f8/vb=6,4 2006.148.07:40:12.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:40:12.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:40:12.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:40:12.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:12.62#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:12.62#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:12.64#ibcon#[27=AT06-04\r\n] 2006.148.07:40:12.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:12.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:40:12.67#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:40:12.67#ibcon#ireg 7 cls_cnt 0 2006.148.07:40:12.67#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:12.79#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:12.79#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:12.81#ibcon#[27=USB\r\n] 2006.148.07:40:12.84#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:12.84#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:40:12.84#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:40:12.84#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:40:12.84$vc4f8/vabw=wide 2006.148.07:40:12.84#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:40:12.84#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:40:12.84#ibcon#ireg 8 cls_cnt 0 2006.148.07:40:12.84#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:12.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:12.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:12.86#ibcon#[25=BW32\r\n] 2006.148.07:40:12.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:12.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:40:12.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:40:12.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:40:12.89$vc4f8/vbbw=wide 2006.148.07:40:12.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:40:12.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:40:12.89#ibcon#ireg 8 cls_cnt 0 2006.148.07:40:12.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:40:12.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:40:12.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:40:12.98#ibcon#[27=BW32\r\n] 2006.148.07:40:13.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:40:13.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:40:13.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:40:13.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:40:13.01$4f8m12a/ifd4f 2006.148.07:40:13.01$ifd4f/lo= 2006.148.07:40:13.01$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:40:13.01$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:40:13.01$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:40:13.01$ifd4f/patch= 2006.148.07:40:13.01$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:40:13.01$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:40:13.01$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:40:13.01$4f8m12a/"form=m,16.000,1:2 2006.148.07:40:13.01$4f8m12a/"tpicd 2006.148.07:40:13.01$4f8m12a/echo=off 2006.148.07:40:13.01$4f8m12a/xlog=off 2006.148.07:40:13.01:!2006.148.07:40:50 2006.148.07:40:29.14#trakl#Source acquired 2006.148.07:40:31.14#flagr#flagr/antenna,acquired 2006.148.07:40:50.00:preob 2006.148.07:40:50.13/onsource/TRACKING 2006.148.07:40:50.13:!2006.148.07:41:00 2006.148.07:41:00.00:data_valid=on 2006.148.07:41:00.00:midob 2006.148.07:41:01.13/onsource/TRACKING 2006.148.07:41:01.13/wx/21.77,994.3,95 2006.148.07:41:01.21/cable/+6.5358E-03 2006.148.07:41:02.31/va/01,08,usb,yes,29,31 2006.148.07:41:02.31/va/02,07,usb,yes,29,30 2006.148.07:41:02.31/va/03,08,usb,yes,22,22 2006.148.07:41:02.31/va/04,07,usb,yes,30,32 2006.148.07:41:02.31/va/05,06,usb,yes,33,35 2006.148.07:41:02.31/va/06,05,usb,yes,33,33 2006.148.07:41:02.31/va/07,05,usb,yes,33,33 2006.148.07:41:02.31/va/08,05,usb,yes,36,35 2006.148.07:41:02.54/valo/01,532.99,yes,locked 2006.148.07:41:02.54/valo/02,572.99,yes,locked 2006.148.07:41:02.54/valo/03,672.99,yes,locked 2006.148.07:41:02.54/valo/04,832.99,yes,locked 2006.148.07:41:02.54/valo/05,652.99,yes,locked 2006.148.07:41:02.54/valo/06,772.99,yes,locked 2006.148.07:41:02.54/valo/07,832.99,yes,locked 2006.148.07:41:02.54/valo/08,852.99,yes,locked 2006.148.07:41:03.63/vb/01,04,usb,yes,29,28 2006.148.07:41:03.63/vb/02,04,usb,yes,31,32 2006.148.07:41:03.63/vb/03,04,usb,yes,27,31 2006.148.07:41:03.63/vb/04,04,usb,yes,28,33 2006.148.07:41:03.63/vb/05,03,usb,yes,33,37 2006.148.07:41:03.63/vb/06,04,usb,yes,28,30 2006.148.07:41:03.63/vb/07,04,usb,yes,29,29 2006.148.07:41:03.63/vb/08,03,usb,yes,34,37 2006.148.07:41:03.86/vblo/01,632.99,yes,locked 2006.148.07:41:03.86/vblo/02,640.99,yes,locked 2006.148.07:41:03.86/vblo/03,656.99,yes,locked 2006.148.07:41:03.86/vblo/04,712.99,yes,locked 2006.148.07:41:03.86/vblo/05,744.99,yes,locked 2006.148.07:41:03.86/vblo/06,752.99,yes,locked 2006.148.07:41:03.86/vblo/07,734.99,yes,locked 2006.148.07:41:03.86/vblo/08,744.99,yes,locked 2006.148.07:41:04.01/vabw/8 2006.148.07:41:04.16/vbbw/8 2006.148.07:41:04.25/xfe/off,on,14.7 2006.148.07:41:04.62/ifatt/23,28,28,28 2006.148.07:41:05.08/fmout-gps/S +4.93E-07 2006.148.07:41:05.12:!2006.148.07:42:00 2006.148.07:42:00.01:data_valid=off 2006.148.07:42:00.01:postob 2006.148.07:42:00.16/cable/+6.5340E-03 2006.148.07:42:00.16/wx/21.78,994.3,94 2006.148.07:42:01.08/fmout-gps/S +4.93E-07 2006.148.07:42:01.08:scan_name=148-0742,k06148,60 2006.148.07:42:01.08:source=0955+476,095819.67,472507.8,2000.0,cw 2006.148.07:42:01.13#flagr#flagr/antenna,new-source 2006.148.07:42:02.13:checkk5 2006.148.07:42:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:42:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:42:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:42:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:42:04.04/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0741*_20??1480741??.k5 file! 2006.148.07:42:04.42/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0741*_20??1480741??.k5 file! 2006.148.07:42:04.80/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0741*_20??1480741??.k5 file! 2006.148.07:42:05.22/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0741*_20??1480741??.k5 file! 2006.148.07:42:05.92/k5log//k5ts1_log_newline 2006.148.07:42:06.61/k5log//k5ts2_log_newline 2006.148.07:42:07.31/k5log//k5ts3_log_newline 2006.148.07:42:08.00/k5log//k5ts4_log_newline 2006.148.07:42:08.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:42:08.18:4f8m12a=1 2006.148.07:42:08.19$4f8m12a/echo=on 2006.148.07:42:08.19$4f8m12a/pcalon 2006.148.07:42:08.19$pcalon/"no phase cal control is implemented here 2006.148.07:42:08.19$4f8m12a/"tpicd=stop 2006.148.07:42:08.19$4f8m12a/vc4f8 2006.148.07:42:08.19$vc4f8/valo=1,532.99 2006.148.07:42:08.19#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:42:08.19#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:42:08.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:08.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:08.19#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:08.19#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:08.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:42:08.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:08.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:08.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:42:08.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:42:08.26$vc4f8/va=1,8 2006.148.07:42:08.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.07:42:08.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.07:42:08.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:08.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:08.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:08.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:08.28#ibcon#[25=AT01-08\r\n] 2006.148.07:42:08.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:08.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:08.31#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.07:42:08.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:08.31#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:08.43#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:08.43#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:08.45#ibcon#[25=USB\r\n] 2006.148.07:42:08.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:08.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:08.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:42:08.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:42:08.50$vc4f8/valo=2,572.99 2006.148.07:42:08.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.07:42:08.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.07:42:08.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:08.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:08.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:08.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:08.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:42:08.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:08.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:08.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:42:08.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:42:08.56$vc4f8/va=2,7 2006.148.07:42:08.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.07:42:08.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.07:42:08.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:08.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:08.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:08.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:08.64#ibcon#[25=AT02-07\r\n] 2006.148.07:42:08.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:08.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:08.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.07:42:08.69#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:08.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:08.74#abcon#<5=/08 1.6 4.4 21.78 94 994.3\r\n> 2006.148.07:42:08.78#abcon#{5=INTERFACE CLEAR} 2006.148.07:42:08.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:08.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:08.83#ibcon#[25=USB\r\n] 2006.148.07:42:08.84#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:42:08.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:08.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:08.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:42:08.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:42:08.88$vc4f8/valo=3,672.99 2006.148.07:42:08.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:42:08.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:42:08.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:08.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:08.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:08.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:08.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:42:08.95#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:08.95#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:08.95#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:42:08.95#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:42:08.95$vc4f8/va=3,8 2006.148.07:42:08.95#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:42:08.95#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:42:08.95#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:08.95#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:09.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:09.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:09.02#ibcon#[25=AT03-08\r\n] 2006.148.07:42:09.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:09.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:09.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:42:09.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:09.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:09.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:09.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:09.19#ibcon#[25=USB\r\n] 2006.148.07:42:09.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:09.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:09.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:42:09.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:42:09.22$vc4f8/valo=4,832.99 2006.148.07:42:09.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.07:42:09.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.07:42:09.22#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:09.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:09.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:09.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:09.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:42:09.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:09.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:09.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:42:09.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:42:09.28$vc4f8/va=4,7 2006.148.07:42:09.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.07:42:09.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.07:42:09.28#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:09.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:09.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:09.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:09.36#ibcon#[25=AT04-07\r\n] 2006.148.07:42:09.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:09.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:09.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.07:42:09.39#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:09.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:09.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:09.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:09.53#ibcon#[25=USB\r\n] 2006.148.07:42:09.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:09.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:09.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:42:09.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:42:09.56$vc4f8/valo=5,652.99 2006.148.07:42:09.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.07:42:09.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.07:42:09.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:09.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:09.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:09.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:09.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:42:09.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:09.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:09.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:42:09.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:42:09.64$vc4f8/va=5,6 2006.148.07:42:09.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.07:42:09.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.07:42:09.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:09.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:09.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:09.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:09.70#ibcon#[25=AT05-06\r\n] 2006.148.07:42:09.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:09.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:09.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.07:42:09.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:09.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:09.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:09.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:09.87#ibcon#[25=USB\r\n] 2006.148.07:42:09.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:09.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:09.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:42:09.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:42:09.90$vc4f8/valo=6,772.99 2006.148.07:42:09.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:42:09.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:42:09.90#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:09.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:09.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:09.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:09.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:42:09.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:09.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:09.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:42:09.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:42:09.96$vc4f8/va=6,5 2006.148.07:42:09.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.07:42:09.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.07:42:09.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:09.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:10.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:10.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:10.04#ibcon#[25=AT06-05\r\n] 2006.148.07:42:10.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:10.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:10.07#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.07:42:10.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:10.07#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:42:10.19#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:42:10.19#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:42:10.21#ibcon#[25=USB\r\n] 2006.148.07:42:10.24#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:42:10.24#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:42:10.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:42:10.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:42:10.24$vc4f8/valo=7,832.99 2006.148.07:42:10.24#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.07:42:10.24#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.07:42:10.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:10.24#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:42:10.24#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:42:10.24#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:42:10.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:42:10.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:42:10.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:42:10.30#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:42:10.30#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:42:10.30$vc4f8/va=7,5 2006.148.07:42:10.30#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.07:42:10.30#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.07:42:10.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:10.30#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:42:10.36#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:42:10.36#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:42:10.38#ibcon#[25=AT07-05\r\n] 2006.148.07:42:10.41#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:42:10.41#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:42:10.41#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.07:42:10.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:10.41#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:42:10.53#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:42:10.53#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:42:10.55#ibcon#[25=USB\r\n] 2006.148.07:42:10.58#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:42:10.58#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:42:10.58#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:42:10.58#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:42:10.58$vc4f8/valo=8,852.99 2006.148.07:42:10.58#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.07:42:10.58#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.07:42:10.58#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:10.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:42:10.58#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:42:10.58#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:42:10.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:42:10.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:42:10.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:42:10.64#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:42:10.64#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:42:10.64$vc4f8/va=8,5 2006.148.07:42:10.64#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.07:42:10.64#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.07:42:10.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:10.64#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:42:10.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:42:10.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:42:10.72#ibcon#[25=AT08-05\r\n] 2006.148.07:42:10.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:42:10.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:42:10.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.07:42:10.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:10.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:42:10.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:42:10.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:42:10.89#ibcon#[25=USB\r\n] 2006.148.07:42:10.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:42:10.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:42:10.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:42:10.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:42:10.92$vc4f8/vblo=1,632.99 2006.148.07:42:10.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:42:10.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:42:10.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:10.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:10.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:10.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:10.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:42:10.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:10.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:42:10.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:42:10.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:42:10.98$vc4f8/vb=1,4 2006.148.07:42:10.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.07:42:10.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.07:42:10.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:10.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:10.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:10.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:11.00#ibcon#[27=AT01-04\r\n] 2006.148.07:42:11.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:11.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:42:11.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.07:42:11.03#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:11.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:11.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:11.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:11.17#ibcon#[27=USB\r\n] 2006.148.07:42:11.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:11.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:42:11.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:42:11.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:42:11.20$vc4f8/vblo=2,640.99 2006.148.07:42:11.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.07:42:11.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.07:42:11.20#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:11.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:11.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:11.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:11.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:42:11.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:11.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:42:11.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:42:11.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:42:11.26$vc4f8/vb=2,4 2006.148.07:42:11.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.07:42:11.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.07:42:11.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:11.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:11.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:11.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:11.34#ibcon#[27=AT02-04\r\n] 2006.148.07:42:11.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:11.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:42:11.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.07:42:11.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:11.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:11.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:11.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:11.51#ibcon#[27=USB\r\n] 2006.148.07:42:11.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:11.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:42:11.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:42:11.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:42:11.54$vc4f8/vblo=3,656.99 2006.148.07:42:11.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.07:42:11.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.07:42:11.54#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:11.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:42:11.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:42:11.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:42:11.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:42:11.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:42:11.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:42:11.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:42:11.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:42:11.60$vc4f8/vb=3,4 2006.148.07:42:11.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.07:42:11.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.07:42:11.60#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:11.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:42:11.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:42:11.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:42:11.68#ibcon#[27=AT03-04\r\n] 2006.148.07:42:11.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:42:11.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:42:11.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.07:42:11.71#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:11.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:42:11.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:42:11.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:42:11.85#ibcon#[27=USB\r\n] 2006.148.07:42:11.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:42:11.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:42:11.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:42:11.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:42:11.88$vc4f8/vblo=4,712.99 2006.148.07:42:11.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:42:11.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:42:11.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:11.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:11.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:11.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:11.90#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:42:11.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:11.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:42:11.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:42:11.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:42:11.94$vc4f8/vb=4,4 2006.148.07:42:11.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:42:11.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:42:11.94#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:11.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:12.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:12.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:12.02#ibcon#[27=AT04-04\r\n] 2006.148.07:42:12.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:12.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:42:12.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:42:12.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:12.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:12.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:12.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:12.19#ibcon#[27=USB\r\n] 2006.148.07:42:12.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:12.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:42:12.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:42:12.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:42:12.22$vc4f8/vblo=5,744.99 2006.148.07:42:12.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.07:42:12.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.07:42:12.22#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:12.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:12.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:12.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:12.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:42:12.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:12.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:42:12.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:42:12.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:42:12.32$vc4f8/vb=5,3 2006.148.07:42:12.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.07:42:12.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.07:42:12.32#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:12.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:12.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:12.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:12.36#ibcon#[27=AT05-03\r\n] 2006.148.07:42:12.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:12.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:42:12.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.07:42:12.39#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:12.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:12.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:12.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:12.53#ibcon#[27=USB\r\n] 2006.148.07:42:12.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:12.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:42:12.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:42:12.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:42:12.56$vc4f8/vblo=6,752.99 2006.148.07:42:12.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.07:42:12.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.07:42:12.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:42:12.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:12.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:12.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:12.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:42:12.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:12.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:42:12.62#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:42:12.62#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:42:12.62$vc4f8/vb=6,4 2006.148.07:42:12.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.07:42:12.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.07:42:12.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:42:12.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:12.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:12.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:12.70#ibcon#[27=AT06-04\r\n] 2006.148.07:42:12.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:12.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:42:12.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.07:42:12.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:42:12.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:12.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:12.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:12.87#ibcon#[27=USB\r\n] 2006.148.07:42:12.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:12.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:42:12.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:42:12.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:42:12.90$vc4f8/vabw=wide 2006.148.07:42:12.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:42:12.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:42:12.90#ibcon#ireg 8 cls_cnt 0 2006.148.07:42:12.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:12.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:12.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:12.92#ibcon#[25=BW32\r\n] 2006.148.07:42:12.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:12.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:42:12.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:42:12.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:42:12.95$vc4f8/vbbw=wide 2006.148.07:42:12.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:42:12.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:42:12.95#ibcon#ireg 8 cls_cnt 0 2006.148.07:42:12.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:42:13.02#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:42:13.02#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:42:13.04#ibcon#[27=BW32\r\n] 2006.148.07:42:13.07#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:42:13.07#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:42:13.07#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:42:13.07#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:42:13.07$4f8m12a/ifd4f 2006.148.07:42:13.07$ifd4f/lo= 2006.148.07:42:13.07$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:42:13.07$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:42:13.07$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:42:13.07$ifd4f/patch= 2006.148.07:42:13.07$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:42:13.07$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:42:13.07$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:42:13.07$4f8m12a/"form=m,16.000,1:2 2006.148.07:42:13.07$4f8m12a/"tpicd 2006.148.07:42:13.07$4f8m12a/echo=off 2006.148.07:42:13.07$4f8m12a/xlog=off 2006.148.07:42:13.07:!2006.148.07:42:40 2006.148.07:42:24.13#trakl#Source acquired 2006.148.07:42:25.13#flagr#flagr/antenna,acquired 2006.148.07:42:40.00:preob 2006.148.07:42:41.13/onsource/TRACKING 2006.148.07:42:41.13:!2006.148.07:42:50 2006.148.07:42:50.00:data_valid=on 2006.148.07:42:50.00:midob 2006.148.07:42:50.13/onsource/TRACKING 2006.148.07:42:50.13/wx/21.79,994.3,94 2006.148.07:42:50.22/cable/+6.5342E-03 2006.148.07:42:51.31/va/01,08,usb,yes,28,30 2006.148.07:42:51.31/va/02,07,usb,yes,28,30 2006.148.07:42:51.31/va/03,08,usb,yes,21,21 2006.148.07:42:51.31/va/04,07,usb,yes,29,31 2006.148.07:42:51.31/va/05,06,usb,yes,32,34 2006.148.07:42:51.31/va/06,05,usb,yes,32,32 2006.148.07:42:51.31/va/07,05,usb,yes,33,32 2006.148.07:42:51.31/va/08,05,usb,yes,35,34 2006.148.07:42:51.54/valo/01,532.99,yes,locked 2006.148.07:42:51.54/valo/02,572.99,yes,locked 2006.148.07:42:51.54/valo/03,672.99,yes,locked 2006.148.07:42:51.54/valo/04,832.99,yes,locked 2006.148.07:42:51.54/valo/05,652.99,yes,locked 2006.148.07:42:51.54/valo/06,772.99,yes,locked 2006.148.07:42:51.54/valo/07,832.99,yes,locked 2006.148.07:42:51.54/valo/08,852.99,yes,locked 2006.148.07:42:52.63/vb/01,04,usb,yes,29,27 2006.148.07:42:52.63/vb/02,04,usb,yes,30,32 2006.148.07:42:52.63/vb/03,04,usb,yes,27,30 2006.148.07:42:52.63/vb/04,04,usb,yes,29,38 2006.148.07:42:52.63/vb/05,03,usb,yes,33,37 2006.148.07:42:52.63/vb/06,04,usb,yes,27,30 2006.148.07:42:52.63/vb/07,04,usb,yes,29,29 2006.148.07:42:52.63/vb/08,03,usb,yes,34,37 2006.148.07:42:52.86/vblo/01,632.99,yes,locked 2006.148.07:42:52.86/vblo/02,640.99,yes,locked 2006.148.07:42:52.86/vblo/03,656.99,yes,locked 2006.148.07:42:52.86/vblo/04,712.99,yes,locked 2006.148.07:42:52.86/vblo/05,744.99,yes,locked 2006.148.07:42:52.86/vblo/06,752.99,yes,locked 2006.148.07:42:52.86/vblo/07,734.99,yes,locked 2006.148.07:42:52.86/vblo/08,744.99,yes,locked 2006.148.07:42:53.01/vabw/8 2006.148.07:42:53.16/vbbw/8 2006.148.07:42:53.25/xfe/off,on,14.5 2006.148.07:42:53.63/ifatt/23,28,28,28 2006.148.07:42:54.08/fmout-gps/S +4.93E-07 2006.148.07:42:54.12:!2006.148.07:43:50 2006.148.07:43:50.00:data_valid=off 2006.148.07:43:50.00:postob 2006.148.07:43:50.13/cable/+6.5343E-03 2006.148.07:43:50.13/wx/21.81,994.3,95 2006.148.07:43:51.08/fmout-gps/S +4.94E-07 2006.148.07:43:51.08:scan_name=148-0745,k06148,70 2006.148.07:43:51.08:source=0536+145,053942.37,143345.6,2000.0,ccw 2006.148.07:43:51.14#flagr#flagr/antenna,new-source 2006.148.07:43:52.14:checkk5 2006.148.07:43:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:43:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:43:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:43:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:43:54.10/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0742*_20??1480742??.k5 file! 2006.148.07:43:54.48/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0742*_20??1480742??.k5 file! 2006.148.07:43:54.86/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0742*_20??1480742??.k5 file! 2006.148.07:43:55.24/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0742*_20??1480742??.k5 file! 2006.148.07:43:55.93/k5log//k5ts1_log_newline 2006.148.07:43:56.63/k5log//k5ts2_log_newline 2006.148.07:43:57.32/k5log//k5ts3_log_newline 2006.148.07:43:58.01/k5log//k5ts4_log_newline 2006.148.07:43:58.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:43:58.19:4f8m12a=1 2006.148.07:43:58.19$4f8m12a/echo=on 2006.148.07:43:58.19$4f8m12a/pcalon 2006.148.07:43:58.19$pcalon/"no phase cal control is implemented here 2006.148.07:43:58.19$4f8m12a/"tpicd=stop 2006.148.07:43:58.19$4f8m12a/vc4f8 2006.148.07:43:58.19$vc4f8/valo=1,532.99 2006.148.07:43:58.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:43:58.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:43:58.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:58.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:43:58.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:43:58.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:43:58.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:43:58.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:43:58.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:43:58.27#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:43:58.27#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:43:58.27$vc4f8/va=1,8 2006.148.07:43:58.27#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:43:58.27#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:43:58.27#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:58.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:43:58.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:43:58.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:43:58.29#ibcon#[25=AT01-08\r\n] 2006.148.07:43:58.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:43:58.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:43:58.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:43:58.32#ibcon#ireg 7 cls_cnt 0 2006.148.07:43:58.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:43:58.43#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:43:58.43#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:43:58.45#ibcon#[25=USB\r\n] 2006.148.07:43:58.48#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:43:58.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:43:58.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:43:58.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:43:58.49$vc4f8/valo=2,572.99 2006.148.07:43:58.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:43:58.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:43:58.49#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:58.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:43:58.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:43:58.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:43:58.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:43:58.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:43:58.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:43:58.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:43:58.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:43:58.57$vc4f8/va=2,7 2006.148.07:43:58.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:43:58.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:43:58.57#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:58.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:43:58.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:43:58.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:43:58.63#ibcon#[25=AT02-07\r\n] 2006.148.07:43:58.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:43:58.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:43:58.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:43:58.66#ibcon#ireg 7 cls_cnt 0 2006.148.07:43:58.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:43:58.77#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:43:58.77#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:43:58.79#ibcon#[25=USB\r\n] 2006.148.07:43:58.82#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:43:58.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:43:58.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:43:58.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:43:58.83$vc4f8/valo=3,672.99 2006.148.07:43:58.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:43:58.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:43:58.83#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:58.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:43:58.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:43:58.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:43:58.87#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:43:58.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:43:58.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:43:58.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:43:58.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:43:58.91$vc4f8/va=3,8 2006.148.07:43:58.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:43:58.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:43:58.91#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:58.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:43:58.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:43:58.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:43:58.96#ibcon#[25=AT03-08\r\n] 2006.148.07:43:58.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:43:59.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:43:59.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:43:59.00#ibcon#ireg 7 cls_cnt 0 2006.148.07:43:59.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:43:59.11#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:43:59.11#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:43:59.13#ibcon#[25=USB\r\n] 2006.148.07:43:59.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:43:59.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:43:59.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:43:59.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:43:59.17$vc4f8/valo=4,832.99 2006.148.07:43:59.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:43:59.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:43:59.17#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:59.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:43:59.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:43:59.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:43:59.18#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:43:59.23#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:43:59.23#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:43:59.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:43:59.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:43:59.23$vc4f8/va=4,7 2006.148.07:43:59.23#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.07:43:59.23#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.07:43:59.23#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:59.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:43:59.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:43:59.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:43:59.30#ibcon#[25=AT04-07\r\n] 2006.148.07:43:59.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:43:59.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:43:59.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.07:43:59.34#ibcon#ireg 7 cls_cnt 0 2006.148.07:43:59.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:43:59.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:43:59.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:43:59.47#ibcon#[25=USB\r\n] 2006.148.07:43:59.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:43:59.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:43:59.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:43:59.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:43:59.51$vc4f8/valo=5,652.99 2006.148.07:43:59.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:43:59.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:43:59.51#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:59.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:43:59.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:43:59.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:43:59.52#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:43:59.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:43:59.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:43:59.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:43:59.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:43:59.57$vc4f8/va=5,6 2006.148.07:43:59.57#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:43:59.57#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:43:59.57#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:59.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:43:59.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:43:59.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:43:59.64#ibcon#[25=AT05-06\r\n] 2006.148.07:43:59.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:43:59.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:43:59.68#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:43:59.68#ibcon#ireg 7 cls_cnt 0 2006.148.07:43:59.68#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:43:59.79#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:43:59.79#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:43:59.81#ibcon#[25=USB\r\n] 2006.148.07:43:59.84#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:43:59.85#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:43:59.85#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:43:59.85#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:43:59.85$vc4f8/valo=6,772.99 2006.148.07:43:59.85#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:43:59.85#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:43:59.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:43:59.85#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:43:59.85#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:43:59.85#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:43:59.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:43:59.90#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:43:59.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:43:59.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:43:59.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:43:59.91$vc4f8/va=6,5 2006.148.07:43:59.91#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:43:59.91#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:43:59.91#ibcon#ireg 11 cls_cnt 2 2006.148.07:43:59.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:43:59.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:43:59.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:43:59.98#ibcon#[25=AT06-05\r\n] 2006.148.07:44:00.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:00.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:00.02#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:44:00.02#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:00.02#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:00.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:00.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:00.14#ibcon#[25=USB\r\n] 2006.148.07:44:00.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:00.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:00.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:44:00.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:44:00.18$vc4f8/valo=7,832.99 2006.148.07:44:00.18#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:44:00.18#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:44:00.18#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:00.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:00.18#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:00.18#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:00.19#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:44:00.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:00.24#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:00.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:44:00.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:44:00.24$vc4f8/va=7,5 2006.148.07:44:00.24#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:44:00.24#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:44:00.24#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:00.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:00.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:00.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:00.30#ibcon#[25=AT07-05\r\n] 2006.148.07:44:00.33#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:00.33#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:00.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:44:00.34#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:00.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:44:00.44#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:44:00.44#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:44:00.46#ibcon#[25=USB\r\n] 2006.148.07:44:00.49#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:44:00.50#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:44:00.50#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:44:00.50#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:44:00.50$vc4f8/valo=8,852.99 2006.148.07:44:00.50#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:44:00.50#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:44:00.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:00.50#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:44:00.50#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:44:00.50#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:44:00.51#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:44:00.55#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:44:00.56#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:44:00.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:44:00.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:44:00.56$vc4f8/va=8,5 2006.148.07:44:00.56#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:44:00.56#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:44:00.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:00.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:44:00.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:44:00.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:44:00.62#ibcon#[25=AT08-05\r\n] 2006.148.07:44:00.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:44:00.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:44:00.66#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:44:00.66#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:00.66#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:44:00.73#abcon#<5=/08 1.7 4.4 21.81 95 994.3\r\n> 2006.148.07:44:00.76#abcon#{5=INTERFACE CLEAR} 2006.148.07:44:00.76#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:44:00.76#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:44:00.78#ibcon#[25=USB\r\n] 2006.148.07:44:00.81#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:44:00.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:44:00.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:44:00.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:44:00.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:44:00.82$vc4f8/vblo=1,632.99 2006.148.07:44:00.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:44:00.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:44:00.82#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:00.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:44:00.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:44:00.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:44:00.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:44:00.87#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:44:00.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:44:00.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:44:00.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:44:00.88$vc4f8/vb=1,4 2006.148.07:44:00.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:44:00.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:44:00.88#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:00.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:44:00.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:44:00.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:44:00.89#ibcon#[27=AT01-04\r\n] 2006.148.07:44:00.92#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:44:00.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:44:00.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:44:00.93#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:00.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:44:01.04#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:44:01.04#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:44:01.06#ibcon#[27=USB\r\n] 2006.148.07:44:01.09#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:44:01.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:44:01.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:44:01.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:44:01.10$vc4f8/vblo=2,640.99 2006.148.07:44:01.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:44:01.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:44:01.10#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:01.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:44:01.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:44:01.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:44:01.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:44:01.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:44:01.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:44:01.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:44:01.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:44:01.16$vc4f8/vb=2,4 2006.148.07:44:01.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:44:01.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:44:01.16#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:01.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:44:01.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:44:01.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:44:01.24#ibcon#[27=AT02-04\r\n] 2006.148.07:44:01.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:44:01.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:44:01.28#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:44:01.28#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:01.28#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:44:01.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:44:01.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:44:01.41#ibcon#[27=USB\r\n] 2006.148.07:44:01.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:44:01.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:44:01.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:44:01.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:44:01.45$vc4f8/vblo=3,656.99 2006.148.07:44:01.45#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:44:01.45#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:44:01.45#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:01.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:44:01.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:44:01.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:44:01.46#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:44:01.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:44:01.51#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:44:01.51#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:44:01.51#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:44:01.51$vc4f8/vb=3,4 2006.148.07:44:01.51#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:44:01.51#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:44:01.51#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:01.51#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:44:01.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:44:01.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:44:01.57#ibcon#[27=AT03-04\r\n] 2006.148.07:44:01.60#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:44:01.60#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:44:01.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:44:01.61#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:01.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:44:01.71#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:44:01.71#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:44:01.73#ibcon#[27=USB\r\n] 2006.148.07:44:01.76#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:44:01.76#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:44:01.76#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:44:01.77#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:44:01.77$vc4f8/vblo=4,712.99 2006.148.07:44:01.77#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:44:01.77#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:44:01.77#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:01.77#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:44:01.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:44:01.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:44:01.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:44:01.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:44:01.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:44:01.83#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:44:01.83#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:44:01.83$vc4f8/vb=4,4 2006.148.07:44:01.83#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.07:44:01.83#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.07:44:01.83#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:01.83#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:44:01.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:44:01.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:44:01.89#ibcon#[27=AT04-04\r\n] 2006.148.07:44:01.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:44:01.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:44:01.93#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.07:44:01.93#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:01.93#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:44:02.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:44:02.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:44:02.06#ibcon#[27=USB\r\n] 2006.148.07:44:02.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:44:02.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:44:02.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:44:02.10#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:44:02.10$vc4f8/vblo=5,744.99 2006.148.07:44:02.10#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:44:02.10#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:44:02.10#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:02.10#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:44:02.10#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:44:02.10#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:44:02.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:44:02.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:44:02.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:44:02.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:44:02.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:44:02.16$vc4f8/vb=5,3 2006.148.07:44:02.16#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:44:02.16#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:44:02.16#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:02.16#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:44:02.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:44:02.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:44:02.22#ibcon#[27=AT05-03\r\n] 2006.148.07:44:02.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:44:02.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:44:02.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:44:02.26#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:02.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:44:02.36#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:44:02.36#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:44:02.38#ibcon#[27=USB\r\n] 2006.148.07:44:02.41#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:44:02.41#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:44:02.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:44:02.42#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:44:02.42$vc4f8/vblo=6,752.99 2006.148.07:44:02.42#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:44:02.42#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:44:02.42#ibcon#ireg 17 cls_cnt 0 2006.148.07:44:02.42#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:44:02.42#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:44:02.42#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:44:02.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:44:02.47#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:44:02.47#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:44:02.47#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:44:02.48#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:44:02.48$vc4f8/vb=6,4 2006.148.07:44:02.48#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:44:02.48#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:44:02.48#ibcon#ireg 11 cls_cnt 2 2006.148.07:44:02.48#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:02.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:02.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:02.54#ibcon#[27=AT06-04\r\n] 2006.148.07:44:02.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:02.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:44:02.58#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:44:02.58#ibcon#ireg 7 cls_cnt 0 2006.148.07:44:02.58#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:02.68#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:02.68#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:02.70#ibcon#[27=USB\r\n] 2006.148.07:44:02.73#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:02.74#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:44:02.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:44:02.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:44:02.74$vc4f8/vabw=wide 2006.148.07:44:02.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:44:02.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:44:02.74#ibcon#ireg 8 cls_cnt 0 2006.148.07:44:02.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:02.74#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:02.74#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:02.75#ibcon#[25=BW32\r\n] 2006.148.07:44:02.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:02.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:44:02.79#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:44:02.79#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:44:02.79$vc4f8/vbbw=wide 2006.148.07:44:02.79#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:44:02.79#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:44:02.79#ibcon#ireg 8 cls_cnt 0 2006.148.07:44:02.79#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:44:02.84#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:44:02.84#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:44:02.86#ibcon#[27=BW32\r\n] 2006.148.07:44:02.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:44:02.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:44:02.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:44:02.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:44:02.90$4f8m12a/ifd4f 2006.148.07:44:02.90$ifd4f/lo= 2006.148.07:44:02.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:44:02.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:44:02.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:44:02.90$ifd4f/patch= 2006.148.07:44:02.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:44:02.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:44:02.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:44:02.90$4f8m12a/"form=m,16.000,1:2 2006.148.07:44:02.90$4f8m12a/"tpicd 2006.148.07:44:02.90$4f8m12a/echo=off 2006.148.07:44:02.90$4f8m12a/xlog=off 2006.148.07:44:02.90:!2006.148.07:45:00 2006.148.07:44:41.14#trakl#Source acquired 2006.148.07:44:42.15#flagr#flagr/antenna,acquired 2006.148.07:45:00.02:preob 2006.148.07:45:01.15/onsource/TRACKING 2006.148.07:45:01.15:!2006.148.07:45:10 2006.148.07:45:10.02:data_valid=on 2006.148.07:45:10.02:midob 2006.148.07:45:11.15/onsource/TRACKING 2006.148.07:45:11.15/wx/21.84,994.3,95 2006.148.07:45:11.23/cable/+6.5371E-03 2006.148.07:45:12.32/va/01,08,usb,yes,29,31 2006.148.07:45:12.32/va/02,07,usb,yes,29,31 2006.148.07:45:12.32/va/03,08,usb,yes,22,22 2006.148.07:45:12.32/va/04,07,usb,yes,30,32 2006.148.07:45:12.32/va/05,06,usb,yes,33,35 2006.148.07:45:12.32/va/06,05,usb,yes,33,33 2006.148.07:45:12.32/va/07,05,usb,yes,33,33 2006.148.07:45:12.32/va/08,05,usb,yes,35,35 2006.148.07:45:12.55/valo/01,532.99,yes,locked 2006.148.07:45:12.55/valo/02,572.99,yes,locked 2006.148.07:45:12.55/valo/03,672.99,yes,locked 2006.148.07:45:12.55/valo/04,832.99,yes,locked 2006.148.07:45:12.55/valo/05,652.99,yes,locked 2006.148.07:45:12.55/valo/06,772.99,yes,locked 2006.148.07:45:12.55/valo/07,832.99,yes,locked 2006.148.07:45:12.55/valo/08,852.99,yes,locked 2006.148.07:45:13.64/vb/01,04,usb,yes,29,28 2006.148.07:45:13.64/vb/02,04,usb,yes,31,32 2006.148.07:45:13.64/vb/03,04,usb,yes,27,31 2006.148.07:45:13.64/vb/04,04,usb,yes,28,30 2006.148.07:45:13.64/vb/05,03,usb,yes,33,38 2006.148.07:45:13.64/vb/06,04,usb,yes,28,30 2006.148.07:45:13.64/vb/07,04,usb,yes,30,29 2006.148.07:45:13.64/vb/08,03,usb,yes,34,38 2006.148.07:45:13.88/vblo/01,632.99,yes,locked 2006.148.07:45:13.88/vblo/02,640.99,yes,locked 2006.148.07:45:13.88/vblo/03,656.99,yes,locked 2006.148.07:45:13.88/vblo/04,712.99,yes,locked 2006.148.07:45:13.88/vblo/05,744.99,yes,locked 2006.148.07:45:13.88/vblo/06,752.99,yes,locked 2006.148.07:45:13.88/vblo/07,734.99,yes,locked 2006.148.07:45:13.88/vblo/08,744.99,yes,locked 2006.148.07:45:14.03/vabw/8 2006.148.07:45:14.18/vbbw/8 2006.148.07:45:14.27/xfe/off,on,15.2 2006.148.07:45:14.65/ifatt/23,28,28,28 2006.148.07:45:15.07/fmout-gps/S +4.94E-07 2006.148.07:45:15.12:!2006.148.07:46:20 2006.148.07:46:20.02:data_valid=off 2006.148.07:46:20.02:postob 2006.148.07:46:20.10/cable/+6.5341E-03 2006.148.07:46:20.10/wx/21.87,994.2,95 2006.148.07:46:21.07/fmout-gps/S +4.94E-07 2006.148.07:46:21.08:scan_name=148-0747,k06148,60 2006.148.07:46:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.148.07:46:21.14#flagr#flagr/antenna,new-source 2006.148.07:46:22.15:checkk5 2006.148.07:46:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:46:22.93/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:46:23.33/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:46:23.71/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:46:24.09/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0745*_20??1480745??.k5 file! 2006.148.07:46:24.47/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0745*_20??1480745??.k5 file! 2006.148.07:46:24.86/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0745*_20??1480745??.k5 file! 2006.148.07:46:25.25/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0745*_20??1480745??.k5 file! 2006.148.07:46:25.95/k5log//k5ts1_log_newline 2006.148.07:46:26.67/k5log//k5ts2_log_newline 2006.148.07:46:27.37/k5log//k5ts3_log_newline 2006.148.07:46:28.07/k5log//k5ts4_log_newline 2006.148.07:46:28.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:46:28.25:4f8m12a=1 2006.148.07:46:28.25$4f8m12a/echo=on 2006.148.07:46:28.25$4f8m12a/pcalon 2006.148.07:46:28.25$pcalon/"no phase cal control is implemented here 2006.148.07:46:28.25$4f8m12a/"tpicd=stop 2006.148.07:46:28.25$4f8m12a/vc4f8 2006.148.07:46:28.25$vc4f8/valo=1,532.99 2006.148.07:46:28.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:46:28.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:46:28.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:28.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:28.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:28.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:28.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:46:28.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:28.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:28.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:46:28.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:46:28.33$vc4f8/va=1,8 2006.148.07:46:28.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:46:28.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:46:28.33#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:28.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:28.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:28.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:28.34#ibcon#[25=AT01-08\r\n] 2006.148.07:46:28.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:28.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:28.37#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:46:28.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:28.37#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:28.49#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:28.49#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:28.51#ibcon#[25=USB\r\n] 2006.148.07:46:28.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:28.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:28.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:46:28.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:46:28.57$vc4f8/valo=2,572.99 2006.148.07:46:28.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.07:46:28.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.07:46:28.57#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:28.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:28.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:28.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:28.58#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:46:28.62#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:28.62#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:28.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:46:28.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:46:28.62$vc4f8/va=2,7 2006.148.07:46:28.62#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.07:46:28.62#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.07:46:28.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:28.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:28.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:28.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:28.71#ibcon#[25=AT02-07\r\n] 2006.148.07:46:28.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:28.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:28.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.07:46:28.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:28.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:28.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:28.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:28.88#ibcon#[25=USB\r\n] 2006.148.07:46:28.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:28.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:28.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:46:28.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:46:28.94$vc4f8/valo=3,672.99 2006.148.07:46:28.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.07:46:28.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.07:46:28.94#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:28.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:28.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:28.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:28.95#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:46:28.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:28.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:28.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:46:28.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:46:28.99$vc4f8/va=3,8 2006.148.07:46:28.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.07:46:28.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.07:46:28.99#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:28.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:29.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:29.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:29.08#ibcon#[25=AT03-08\r\n] 2006.148.07:46:29.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:29.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:29.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.07:46:29.11#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:29.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:29.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:29.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:29.25#ibcon#[25=USB\r\n] 2006.148.07:46:29.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:29.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:29.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:46:29.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:46:29.28$vc4f8/valo=4,832.99 2006.148.07:46:29.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:46:29.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:46:29.28#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:29.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:29.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:29.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:29.30#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:46:29.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:29.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:29.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:46:29.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:46:29.34$vc4f8/va=4,7 2006.148.07:46:29.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:46:29.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:46:29.34#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:29.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:29.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:29.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:29.42#ibcon#[25=AT04-07\r\n] 2006.148.07:46:29.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:29.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:29.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:46:29.45#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:29.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:29.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:29.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:29.59#ibcon#[25=USB\r\n] 2006.148.07:46:29.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:29.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:29.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:46:29.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:46:29.62$vc4f8/valo=5,652.99 2006.148.07:46:29.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:46:29.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:46:29.62#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:29.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:29.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:29.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:29.64#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:46:29.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:29.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:29.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:46:29.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:46:29.68$vc4f8/va=5,6 2006.148.07:46:29.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:46:29.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:46:29.68#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:29.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:29.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:29.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:29.76#ibcon#[25=AT05-06\r\n] 2006.148.07:46:29.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:29.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:29.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:46:29.79#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:29.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:29.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:29.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:29.93#ibcon#[25=USB\r\n] 2006.148.07:46:29.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:29.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:29.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:46:29.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:46:29.96$vc4f8/valo=6,772.99 2006.148.07:46:29.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:46:29.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:46:29.96#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:29.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:29.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:29.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:29.98#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:46:30.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:30.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:30.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:46:30.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:46:30.02$vc4f8/va=6,5 2006.148.07:46:30.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:46:30.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:46:30.02#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:30.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:30.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:30.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:30.10#ibcon#[25=AT06-05\r\n] 2006.148.07:46:30.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:30.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:30.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:46:30.13#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:30.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:46:30.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:46:30.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:46:30.27#ibcon#[25=USB\r\n] 2006.148.07:46:30.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:46:30.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:46:30.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:46:30.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:46:30.30$vc4f8/valo=7,832.99 2006.148.07:46:30.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.07:46:30.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.07:46:30.30#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:30.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:46:30.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:46:30.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:46:30.32#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:46:30.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:46:30.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:46:30.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:46:30.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:46:30.36$vc4f8/va=7,5 2006.148.07:46:30.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.07:46:30.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.07:46:30.36#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:30.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:46:30.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:46:30.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:46:30.44#ibcon#[25=AT07-05\r\n] 2006.148.07:46:30.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:46:30.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:46:30.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.07:46:30.47#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:30.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:46:30.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:46:30.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:46:30.61#ibcon#[25=USB\r\n] 2006.148.07:46:30.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:46:30.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:46:30.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:46:30.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:46:30.64$vc4f8/valo=8,852.99 2006.148.07:46:30.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.07:46:30.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.07:46:30.64#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:30.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:46:30.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:46:30.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:46:30.66#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:46:30.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:46:30.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:46:30.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:46:30.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:46:30.70$vc4f8/va=8,5 2006.148.07:46:30.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.07:46:30.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.07:46:30.70#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:30.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:46:30.76#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:46:30.76#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:46:30.78#ibcon#[25=AT08-05\r\n] 2006.148.07:46:30.81#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:46:30.81#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:46:30.81#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.07:46:30.81#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:30.81#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:46:30.93#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:46:30.93#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:46:30.95#ibcon#[25=USB\r\n] 2006.148.07:46:30.98#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:46:30.98#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:46:30.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:46:30.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:46:30.98$vc4f8/vblo=1,632.99 2006.148.07:46:30.98#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.07:46:30.98#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.07:46:30.98#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:30.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:46:30.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:46:30.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:46:31.00#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:46:31.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:46:31.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:46:31.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:46:31.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:46:31.04$vc4f8/vb=1,4 2006.148.07:46:31.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.07:46:31.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.07:46:31.04#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:31.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:46:31.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:46:31.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:46:31.06#ibcon#[27=AT01-04\r\n] 2006.148.07:46:31.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:46:31.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:46:31.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.07:46:31.09#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:31.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:46:31.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:46:31.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:46:31.23#ibcon#[27=USB\r\n] 2006.148.07:46:31.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:46:31.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:46:31.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:46:31.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:46:31.26$vc4f8/vblo=2,640.99 2006.148.07:46:31.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:46:31.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:46:31.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:31.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:31.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:31.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:31.28#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:46:31.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:31.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:46:31.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:46:31.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:46:31.32$vc4f8/vb=2,4 2006.148.07:46:31.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:46:31.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:46:31.32#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:31.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:31.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:31.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:31.40#ibcon#[27=AT02-04\r\n] 2006.148.07:46:31.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:31.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:46:31.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:46:31.43#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:31.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:31.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:31.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:31.57#ibcon#[27=USB\r\n] 2006.148.07:46:31.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:31.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:46:31.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:46:31.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:46:31.63$vc4f8/vblo=3,656.99 2006.148.07:46:31.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.07:46:31.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.07:46:31.63#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:31.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:31.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:31.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:31.64#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:46:31.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:31.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:46:31.68#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:46:31.68#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:46:31.68$vc4f8/vb=3,4 2006.148.07:46:31.68#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.07:46:31.68#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.07:46:31.68#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:31.68#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:31.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:31.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:31.77#ibcon#[27=AT03-04\r\n] 2006.148.07:46:31.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:31.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:46:31.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.07:46:31.80#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:31.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:31.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:31.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:31.94#ibcon#[27=USB\r\n] 2006.148.07:46:31.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:31.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:46:31.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:46:31.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:46:31.97$vc4f8/vblo=4,712.99 2006.148.07:46:31.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.07:46:31.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.07:46:31.97#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:31.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:31.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:31.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:31.99#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:46:32.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:32.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:46:32.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:46:32.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:46:32.03$vc4f8/vb=4,4 2006.148.07:46:32.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.07:46:32.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.07:46:32.03#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:32.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:32.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:32.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:32.11#ibcon#[27=AT04-04\r\n] 2006.148.07:46:32.15#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:32.15#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:46:32.15#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.07:46:32.15#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:32.15#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:32.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:32.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:32.28#ibcon#[27=USB\r\n] 2006.148.07:46:32.34#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:32.34#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:46:32.34#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:46:32.34#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:46:32.34$vc4f8/vblo=5,744.99 2006.148.07:46:32.34#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:46:32.34#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:46:32.34#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:32.34#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:32.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:32.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:32.35#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:46:32.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:32.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:46:32.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:46:32.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:46:32.39$vc4f8/vb=5,3 2006.148.07:46:32.39#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:46:32.39#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:46:32.39#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:32.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:32.46#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:32.46#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:32.48#ibcon#[27=AT05-03\r\n] 2006.148.07:46:32.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:32.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:46:32.51#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:46:32.51#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:32.51#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:32.63#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:32.63#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:32.65#ibcon#[27=USB\r\n] 2006.148.07:46:32.68#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:32.68#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:46:32.68#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:46:32.68#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:46:32.68$vc4f8/vblo=6,752.99 2006.148.07:46:32.68#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:46:32.68#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:46:32.68#ibcon#ireg 17 cls_cnt 0 2006.148.07:46:32.68#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:32.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:32.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:32.70#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:46:32.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:32.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:46:32.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:46:32.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:46:32.74$vc4f8/vb=6,4 2006.148.07:46:32.74#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:46:32.74#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:46:32.74#ibcon#ireg 11 cls_cnt 2 2006.148.07:46:32.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:32.80#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:32.80#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:32.82#ibcon#[27=AT06-04\r\n] 2006.148.07:46:32.85#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:32.85#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:46:32.85#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:46:32.85#ibcon#ireg 7 cls_cnt 0 2006.148.07:46:32.85#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:32.97#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:32.97#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:32.99#ibcon#[27=USB\r\n] 2006.148.07:46:33.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:33.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:46:33.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:46:33.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:46:33.02$vc4f8/vabw=wide 2006.148.07:46:33.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:46:33.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:46:33.02#ibcon#ireg 8 cls_cnt 0 2006.148.07:46:33.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:33.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:33.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:33.04#ibcon#[25=BW32\r\n] 2006.148.07:46:33.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:33.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:46:33.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:46:33.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:46:33.07$vc4f8/vbbw=wide 2006.148.07:46:33.07#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.07:46:33.07#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.07:46:33.07#ibcon#ireg 8 cls_cnt 0 2006.148.07:46:33.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:46:33.15#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:46:33.15#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:46:33.16#ibcon#[27=BW32\r\n] 2006.148.07:46:33.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:46:33.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:46:33.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:46:33.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:46:33.19$4f8m12a/ifd4f 2006.148.07:46:33.19$ifd4f/lo= 2006.148.07:46:33.20$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:46:33.20$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:46:33.20$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:46:33.20$ifd4f/patch= 2006.148.07:46:33.20$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:46:33.20$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:46:33.20$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:46:33.20$4f8m12a/"form=m,16.000,1:2 2006.148.07:46:33.20$4f8m12a/"tpicd 2006.148.07:46:33.20$4f8m12a/echo=off 2006.148.07:46:33.20$4f8m12a/xlog=off 2006.148.07:46:33.20:!2006.148.07:47:30 2006.148.07:47:13.14#trakl#Source acquired 2006.148.07:47:15.14#flagr#flagr/antenna,acquired 2006.148.07:47:30.01:preob 2006.148.07:47:31.14/onsource/TRACKING 2006.148.07:47:31.14:!2006.148.07:47:40 2006.148.07:47:40.00:data_valid=on 2006.148.07:47:40.00:midob 2006.148.07:47:40.14/onsource/TRACKING 2006.148.07:47:40.15/wx/21.92,994.2,95 2006.148.07:47:40.24/cable/+6.5337E-03 2006.148.07:47:41.33/va/01,08,usb,yes,33,35 2006.148.07:47:41.33/va/02,07,usb,yes,33,35 2006.148.07:47:41.33/va/03,08,usb,yes,25,25 2006.148.07:47:41.33/va/04,07,usb,yes,34,37 2006.148.07:47:41.33/va/05,06,usb,yes,38,40 2006.148.07:47:41.33/va/06,05,usb,yes,38,38 2006.148.07:47:41.33/va/07,05,usb,yes,38,38 2006.148.07:47:41.33/va/08,05,usb,yes,41,40 2006.148.07:47:41.56/valo/01,532.99,yes,locked 2006.148.07:47:41.56/valo/02,572.99,yes,locked 2006.148.07:47:41.56/valo/03,672.99,yes,locked 2006.148.07:47:41.56/valo/04,832.99,yes,locked 2006.148.07:47:41.56/valo/05,652.99,yes,locked 2006.148.07:47:41.56/valo/06,772.99,yes,locked 2006.148.07:47:41.56/valo/07,832.99,yes,locked 2006.148.07:47:41.56/valo/08,852.99,yes,locked 2006.148.07:47:42.65/vb/01,04,usb,yes,31,30 2006.148.07:47:42.65/vb/02,04,usb,yes,33,34 2006.148.07:47:42.65/vb/03,04,usb,yes,29,33 2006.148.07:47:42.65/vb/04,04,usb,yes,30,33 2006.148.07:47:42.65/vb/05,03,usb,yes,36,40 2006.148.07:47:42.65/vb/06,04,usb,yes,30,33 2006.148.07:47:42.65/vb/07,04,usb,yes,32,32 2006.148.07:47:42.65/vb/08,03,usb,yes,36,40 2006.148.07:47:42.88/vblo/01,632.99,yes,locked 2006.148.07:47:42.88/vblo/02,640.99,yes,locked 2006.148.07:47:42.88/vblo/03,656.99,yes,locked 2006.148.07:47:42.88/vblo/04,712.99,yes,locked 2006.148.07:47:42.88/vblo/05,744.99,yes,locked 2006.148.07:47:42.88/vblo/06,752.99,yes,locked 2006.148.07:47:42.88/vblo/07,734.99,yes,locked 2006.148.07:47:42.88/vblo/08,744.99,yes,locked 2006.148.07:47:43.03/vabw/8 2006.148.07:47:43.18/vbbw/8 2006.148.07:47:43.34/xfe/off,on,15.2 2006.148.07:47:43.73/ifatt/23,28,28,28 2006.148.07:47:44.07/fmout-gps/S +4.93E-07 2006.148.07:47:44.16:!2006.148.07:48:40 2006.148.07:48:40.01:data_valid=off 2006.148.07:48:40.02:postob 2006.148.07:48:40.20/cable/+6.5375E-03 2006.148.07:48:40.21/wx/21.93,994.2,94 2006.148.07:48:41.07/fmout-gps/S +4.94E-07 2006.148.07:48:41.08:scan_name=148-0749,k06148,60 2006.148.07:48:41.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.148.07:48:41.14#flagr#flagr/antenna,new-source 2006.148.07:48:42.14:checkk5 2006.148.07:48:42.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:48:42.93/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:48:43.32/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:48:43.70/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:48:44.08/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0747*_20??1480747??.k5 file! 2006.148.07:48:44.47/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0747*_20??1480747??.k5 file! 2006.148.07:48:44.85/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0747*_20??1480747??.k5 file! 2006.148.07:48:45.24/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0747*_20??1480747??.k5 file! 2006.148.07:48:45.94/k5log//k5ts1_log_newline 2006.148.07:48:46.64/k5log//k5ts2_log_newline 2006.148.07:48:47.34/k5log//k5ts3_log_newline 2006.148.07:48:48.07/k5log//k5ts4_log_newline 2006.148.07:48:48.25/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:48:48.25:4f8m12a=1 2006.148.07:48:48.25$4f8m12a/echo=on 2006.148.07:48:48.25$4f8m12a/pcalon 2006.148.07:48:48.25$pcalon/"no phase cal control is implemented here 2006.148.07:48:48.25$4f8m12a/"tpicd=stop 2006.148.07:48:48.25$4f8m12a/vc4f8 2006.148.07:48:48.25$vc4f8/valo=1,532.99 2006.148.07:48:48.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:48:48.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:48:48.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:48.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:48.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:48.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:48.27#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:48:48.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:48.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:48.33#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:48:48.33#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:48:48.33$vc4f8/va=1,8 2006.148.07:48:48.33#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:48:48.33#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:48:48.33#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:48.33#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:48.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:48.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:48.34#ibcon#[25=AT01-08\r\n] 2006.148.07:48:48.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:48.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:48.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:48:48.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:48.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:48.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:48.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:48.51#ibcon#[25=USB\r\n] 2006.148.07:48:48.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:48.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:48.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:48:48.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:48:48.54$vc4f8/valo=2,572.99 2006.148.07:48:48.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:48:48.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:48:48.54#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:48.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:48.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:48.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:48.58#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:48:48.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:48.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:48.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:48:48.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:48:48.62$vc4f8/va=2,7 2006.148.07:48:48.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:48:48.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:48:48.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:48.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:48.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:48.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:48.69#ibcon#[25=AT02-07\r\n] 2006.148.07:48:48.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:48.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:48.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:48:48.71#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:48.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:48.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:48.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:48.85#ibcon#[25=USB\r\n] 2006.148.07:48:48.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:48.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:48.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:48:48.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:48:48.88$vc4f8/valo=3,672.99 2006.148.07:48:48.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:48:48.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:48:48.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:48.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:48.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:48.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:48.92#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:48:48.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:48.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:48.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:48:48.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:48:48.96$vc4f8/va=3,8 2006.148.07:48:48.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:48:48.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:48:48.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:48.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:49.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:49.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:49.02#ibcon#[25=AT03-08\r\n] 2006.148.07:48:49.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:49.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:49.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:48:49.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:49.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:49.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:49.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:49.19#ibcon#[25=USB\r\n] 2006.148.07:48:49.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:49.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:49.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:48:49.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:48:49.22$vc4f8/valo=4,832.99 2006.148.07:48:49.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:48:49.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:48:49.22#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:49.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:49.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:49.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:49.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:48:49.28#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:49.28#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:49.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:48:49.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:48:49.28$vc4f8/va=4,7 2006.148.07:48:49.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:48:49.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:48:49.28#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:49.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:49.34#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:49.34#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:49.36#ibcon#[25=AT04-07\r\n] 2006.148.07:48:49.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:49.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:49.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:48:49.39#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:49.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:49.51#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:49.51#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:49.53#ibcon#[25=USB\r\n] 2006.148.07:48:49.56#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:49.56#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:49.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:48:49.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:48:49.56$vc4f8/valo=5,652.99 2006.148.07:48:49.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:48:49.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:48:49.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:49.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:49.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:49.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:49.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:48:49.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:49.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:49.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:48:49.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:48:49.62$vc4f8/va=5,6 2006.148.07:48:49.62#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:48:49.62#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:48:49.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:49.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:49.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:49.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:49.70#ibcon#[25=AT05-06\r\n] 2006.148.07:48:49.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:49.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:49.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:48:49.74#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:49.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:49.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:49.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:49.87#ibcon#[25=USB\r\n] 2006.148.07:48:49.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:49.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:49.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:48:49.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:48:49.90$vc4f8/valo=6,772.99 2006.148.07:48:49.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:48:49.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:48:49.90#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:49.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:49.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:49.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:49.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:48:49.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:49.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:49.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:48:49.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:48:49.96$vc4f8/va=6,5 2006.148.07:48:49.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:48:49.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:48:49.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:49.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:50.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:50.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:50.04#ibcon#[25=AT06-05\r\n] 2006.148.07:48:50.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:50.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:50.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:48:50.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:50.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:48:50.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:48:50.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:48:50.21#ibcon#[25=USB\r\n] 2006.148.07:48:50.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:48:50.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:48:50.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:48:50.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:48:50.24$vc4f8/valo=7,832.99 2006.148.07:48:50.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:48:50.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:48:50.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:50.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:48:50.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:48:50.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:48:50.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:48:50.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:48:50.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:48:50.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:48:50.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:48:50.30$vc4f8/va=7,5 2006.148.07:48:50.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:48:50.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:48:50.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:50.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:48:50.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:48:50.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:48:50.38#ibcon#[25=AT07-05\r\n] 2006.148.07:48:50.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:48:50.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:48:50.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:48:50.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:50.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:48:50.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:48:50.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:48:50.55#ibcon#[25=USB\r\n] 2006.148.07:48:50.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:48:50.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:48:50.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:48:50.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:48:50.58$vc4f8/valo=8,852.99 2006.148.07:48:50.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:48:50.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:48:50.58#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:50.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:48:50.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:48:50.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:48:50.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:48:50.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:48:50.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:48:50.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:48:50.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:48:50.64$vc4f8/va=8,5 2006.148.07:48:50.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:48:50.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:48:50.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:50.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:48:50.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:48:50.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:48:50.72#ibcon#[25=AT08-05\r\n] 2006.148.07:48:50.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:48:50.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:48:50.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:48:50.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:50.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:48:50.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:48:50.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:48:50.89#ibcon#[25=USB\r\n] 2006.148.07:48:50.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:48:50.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:48:50.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:48:50.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:48:50.92$vc4f8/vblo=1,632.99 2006.148.07:48:50.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:48:50.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:48:50.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:50.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:48:50.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:48:50.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:48:50.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:48:50.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:48:50.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:48:50.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:48:50.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:48:50.98$vc4f8/vb=1,4 2006.148.07:48:50.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:48:50.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:48:50.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:50.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:48:50.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:48:50.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:48:51.00#ibcon#[27=AT01-04\r\n] 2006.148.07:48:51.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:48:51.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:48:51.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:48:51.03#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:51.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:48:51.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:48:51.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:48:51.17#ibcon#[27=USB\r\n] 2006.148.07:48:51.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:48:51.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:48:51.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:48:51.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:48:51.20$vc4f8/vblo=2,640.99 2006.148.07:48:51.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:48:51.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:48:51.20#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:51.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:51.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:51.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:51.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:48:51.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:51.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:48:51.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:48:51.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:48:51.26$vc4f8/vb=2,4 2006.148.07:48:51.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:48:51.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:48:51.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:51.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:51.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:51.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:51.35#ibcon#[27=AT02-04\r\n] 2006.148.07:48:51.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:51.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:48:51.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:48:51.38#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:51.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:51.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:51.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:51.52#ibcon#[27=USB\r\n] 2006.148.07:48:51.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:51.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:48:51.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:48:51.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:48:51.55$vc4f8/vblo=3,656.99 2006.148.07:48:51.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:48:51.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:48:51.55#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:51.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:51.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:51.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:51.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:48:51.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:51.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:48:51.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:48:51.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:48:51.61$vc4f8/vb=3,4 2006.148.07:48:51.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:48:51.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:48:51.61#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:51.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:51.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:51.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:51.69#ibcon#[27=AT03-04\r\n] 2006.148.07:48:51.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:51.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:48:51.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:48:51.72#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:51.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:51.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:51.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:51.86#ibcon#[27=USB\r\n] 2006.148.07:48:51.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:51.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:48:51.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:48:51.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:48:51.89$vc4f8/vblo=4,712.99 2006.148.07:48:51.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:48:51.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:48:51.89#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:51.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:51.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:51.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:51.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:48:51.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:51.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:48:51.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:48:51.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:48:51.95$vc4f8/vb=4,4 2006.148.07:48:51.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:48:51.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:48:51.95#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:51.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:52.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:52.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:52.03#ibcon#[27=AT04-04\r\n] 2006.148.07:48:52.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:52.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:48:52.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:48:52.06#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:52.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:52.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:52.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:52.22#ibcon#[27=USB\r\n] 2006.148.07:48:52.25#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:52.25#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:48:52.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:48:52.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:48:52.25$vc4f8/vblo=5,744.99 2006.148.07:48:52.25#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:48:52.25#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:48:52.25#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:52.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:52.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:52.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:52.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:48:52.31#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:52.31#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:48:52.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:48:52.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:48:52.31$vc4f8/vb=5,3 2006.148.07:48:52.31#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:48:52.31#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:48:52.31#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:52.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:52.37#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:52.37#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:52.39#ibcon#[27=AT05-03\r\n] 2006.148.07:48:52.42#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:52.42#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:48:52.42#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:48:52.42#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:52.42#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:52.54#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:52.54#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:52.56#ibcon#[27=USB\r\n] 2006.148.07:48:52.59#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:52.59#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:48:52.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:48:52.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:48:52.59$vc4f8/vblo=6,752.99 2006.148.07:48:52.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:48:52.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:48:52.59#ibcon#ireg 17 cls_cnt 0 2006.148.07:48:52.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:52.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:52.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:52.61#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:48:52.65#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:52.65#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:48:52.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:48:52.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:48:52.65$vc4f8/vb=6,4 2006.148.07:48:52.65#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:48:52.65#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:48:52.65#ibcon#ireg 11 cls_cnt 2 2006.148.07:48:52.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:52.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:52.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:52.73#ibcon#[27=AT06-04\r\n] 2006.148.07:48:52.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:52.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:48:52.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:48:52.76#ibcon#ireg 7 cls_cnt 0 2006.148.07:48:52.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:52.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:52.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:52.90#ibcon#[27=USB\r\n] 2006.148.07:48:52.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:52.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:48:52.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:48:52.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:48:52.93$vc4f8/vabw=wide 2006.148.07:48:52.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:48:52.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:48:52.93#ibcon#ireg 8 cls_cnt 0 2006.148.07:48:52.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:52.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:52.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:52.95#ibcon#[25=BW32\r\n] 2006.148.07:48:52.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:52.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:48:52.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:48:52.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:48:52.98$vc4f8/vbbw=wide 2006.148.07:48:52.98#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:48:52.98#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:48:52.98#ibcon#ireg 8 cls_cnt 0 2006.148.07:48:52.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:48:53.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:48:53.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:48:53.07#ibcon#[27=BW32\r\n] 2006.148.07:48:53.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:48:53.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:48:53.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:48:53.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:48:53.10$4f8m12a/ifd4f 2006.148.07:48:53.10$ifd4f/lo= 2006.148.07:48:53.10$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:48:53.10$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:48:53.10$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:48:53.10$ifd4f/patch= 2006.148.07:48:53.11$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:48:53.11$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:48:53.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:48:53.11$4f8m12a/"form=m,16.000,1:2 2006.148.07:48:53.11$4f8m12a/"tpicd 2006.148.07:48:53.11$4f8m12a/echo=off 2006.148.07:48:53.11$4f8m12a/xlog=off 2006.148.07:48:53.11:!2006.148.07:49:20 2006.148.07:49:06.14#trakl#Source acquired 2006.148.07:49:08.14#flagr#flagr/antenna,acquired 2006.148.07:49:20.01:preob 2006.148.07:49:21.13/onsource/TRACKING 2006.148.07:49:21.13:!2006.148.07:49:30 2006.148.07:49:30.00:data_valid=on 2006.148.07:49:30.00:midob 2006.148.07:49:30.13/onsource/TRACKING 2006.148.07:49:30.13/wx/21.93,994.2,94 2006.148.07:49:30.28/cable/+6.5355E-03 2006.148.07:49:31.37/va/01,08,usb,yes,29,30 2006.148.07:49:31.37/va/02,07,usb,yes,29,30 2006.148.07:49:31.37/va/03,08,usb,yes,21,22 2006.148.07:49:31.37/va/04,07,usb,yes,29,31 2006.148.07:49:31.37/va/05,06,usb,yes,32,34 2006.148.07:49:31.37/va/06,05,usb,yes,33,32 2006.148.07:49:31.37/va/07,05,usb,yes,33,32 2006.148.07:49:31.37/va/08,05,usb,yes,35,34 2006.148.07:49:31.60/valo/01,532.99,yes,locked 2006.148.07:49:31.60/valo/02,572.99,yes,locked 2006.148.07:49:31.60/valo/03,672.99,yes,locked 2006.148.07:49:31.60/valo/04,832.99,yes,locked 2006.148.07:49:31.60/valo/05,652.99,yes,locked 2006.148.07:49:31.60/valo/06,772.99,yes,locked 2006.148.07:49:31.60/valo/07,832.99,yes,locked 2006.148.07:49:31.60/valo/08,852.99,yes,locked 2006.148.07:49:32.69/vb/01,04,usb,yes,28,27 2006.148.07:49:32.69/vb/02,04,usb,yes,30,31 2006.148.07:49:32.69/vb/03,04,usb,yes,26,30 2006.148.07:49:32.69/vb/04,04,usb,yes,27,34 2006.148.07:49:32.69/vb/05,03,usb,yes,32,37 2006.148.07:49:32.69/vb/06,04,usb,yes,27,29 2006.148.07:49:32.69/vb/07,04,usb,yes,29,28 2006.148.07:49:32.69/vb/08,03,usb,yes,33,37 2006.148.07:49:32.93/vblo/01,632.99,yes,locked 2006.148.07:49:32.93/vblo/02,640.99,yes,locked 2006.148.07:49:32.93/vblo/03,656.99,yes,locked 2006.148.07:49:32.93/vblo/04,712.99,yes,locked 2006.148.07:49:32.93/vblo/05,744.99,yes,locked 2006.148.07:49:32.93/vblo/06,752.99,yes,locked 2006.148.07:49:32.93/vblo/07,734.99,yes,locked 2006.148.07:49:32.93/vblo/08,744.99,yes,locked 2006.148.07:49:33.08/vabw/8 2006.148.07:49:33.23/vbbw/8 2006.148.07:49:33.32/xfe/off,on,14.2 2006.148.07:49:33.70/ifatt/23,28,28,28 2006.148.07:49:34.07/fmout-gps/S +4.94E-07 2006.148.07:49:34.12:!2006.148.07:50:30 2006.148.07:50:30.01:data_valid=off 2006.148.07:50:30.02:postob 2006.148.07:50:30.20/cable/+6.5318E-03 2006.148.07:50:30.21/wx/21.93,994.2,93 2006.148.07:50:30.27/fmout-gps/S +4.94E-07 2006.148.07:50:30.28:scan_name=148-0751,k06148,60 2006.148.07:50:30.28:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.148.07:50:31.13#flagr#flagr/antenna,new-source 2006.148.07:50:31.14:checkk5 2006.148.07:50:31.51/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:50:31.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:50:32.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:50:32.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:50:33.04/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0749*_20??1480749??.k5 file! 2006.148.07:50:33.42/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0749*_20??1480749??.k5 file! 2006.148.07:50:33.81/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0749*_20??1480749??.k5 file! 2006.148.07:50:34.20/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0749*_20??1480749??.k5 file! 2006.148.07:50:34.90/k5log//k5ts1_log_newline 2006.148.07:50:35.60/k5log//k5ts2_log_newline 2006.148.07:50:36.29/k5log//k5ts3_log_newline 2006.148.07:50:36.98/k5log//k5ts4_log_newline 2006.148.07:50:37.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:50:37.18:4f8m12a=1 2006.148.07:50:37.19$4f8m12a/echo=on 2006.148.07:50:37.19$4f8m12a/pcalon 2006.148.07:50:37.19$pcalon/"no phase cal control is implemented here 2006.148.07:50:37.19$4f8m12a/"tpicd=stop 2006.148.07:50:37.19$4f8m12a/vc4f8 2006.148.07:50:37.19$vc4f8/valo=1,532.99 2006.148.07:50:37.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:50:37.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:50:37.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:37.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:37.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:37.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:37.20#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:50:37.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:37.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:37.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:50:37.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:50:37.27$vc4f8/va=1,8 2006.148.07:50:37.27#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:50:37.27#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:50:37.27#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:37.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:37.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:37.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:37.28#ibcon#[25=AT01-08\r\n] 2006.148.07:50:37.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:37.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:37.31#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:50:37.31#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:37.31#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:37.43#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:37.43#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:37.45#ibcon#[25=USB\r\n] 2006.148.07:50:37.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:37.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:37.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:50:37.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:50:37.51$vc4f8/valo=2,572.99 2006.148.07:50:37.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:50:37.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:50:37.51#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:37.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:50:37.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:50:37.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:50:37.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:50:37.55#abcon#<5=/08 1.7 5.1 21.93 93 994.2\r\n> 2006.148.07:50:37.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:50:37.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:50:37.56#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:50:37.56#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:50:37.56$vc4f8/va=2,7 2006.148.07:50:37.56#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:50:37.56#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:50:37.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:37.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:50:37.59#abcon#{5=INTERFACE CLEAR} 2006.148.07:50:37.63#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:50:37.63#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:50:37.65#ibcon#[25=AT02-07\r\n] 2006.148.07:50:37.65#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:50:37.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:50:37.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:50:37.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:50:37.69#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:37.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:50:37.80#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:50:37.80#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:50:37.82#ibcon#[25=USB\r\n] 2006.148.07:50:37.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:50:37.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:50:37.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:50:37.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:50:37.88$vc4f8/valo=3,672.99 2006.148.07:50:37.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:50:37.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:50:37.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:37.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:37.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:37.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:37.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:50:37.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:37.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:37.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:50:37.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:50:37.93$vc4f8/va=3,8 2006.148.07:50:37.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.07:50:37.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.07:50:37.93#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:37.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:38.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:38.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:38.02#ibcon#[25=AT03-08\r\n] 2006.148.07:50:38.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:38.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:38.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.07:50:38.05#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:38.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:38.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:38.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:38.19#ibcon#[25=USB\r\n] 2006.148.07:50:38.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:38.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:38.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:50:38.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:50:38.22$vc4f8/valo=4,832.99 2006.148.07:50:38.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.07:50:38.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.07:50:38.22#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:38.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:38.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:38.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:38.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:50:38.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:38.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:38.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:50:38.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:50:38.28$vc4f8/va=4,7 2006.148.07:50:38.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.07:50:38.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.07:50:38.28#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:38.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:38.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:38.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:38.36#ibcon#[25=AT04-07\r\n] 2006.148.07:50:38.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:38.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:38.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.07:50:38.39#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:38.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:38.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:38.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:38.53#ibcon#[25=USB\r\n] 2006.148.07:50:38.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:38.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:38.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:50:38.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:50:38.56$vc4f8/valo=5,652.99 2006.148.07:50:38.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.07:50:38.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.07:50:38.56#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:38.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:38.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:38.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:38.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:50:38.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:38.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:38.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:50:38.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:50:38.62$vc4f8/va=5,6 2006.148.07:50:38.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.07:50:38.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.07:50:38.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:38.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:38.69#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:38.69#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:38.70#ibcon#[25=AT05-06\r\n] 2006.148.07:50:38.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:38.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:38.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.07:50:38.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:38.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:38.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:38.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:38.87#ibcon#[25=USB\r\n] 2006.148.07:50:38.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:38.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:38.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:50:38.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:50:38.90$vc4f8/valo=6,772.99 2006.148.07:50:38.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:50:38.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:50:38.90#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:38.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:38.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:38.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:38.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:50:38.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:38.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:38.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:50:38.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:50:38.96$vc4f8/va=6,5 2006.148.07:50:38.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.07:50:38.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.07:50:38.96#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:38.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:39.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:39.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:39.04#ibcon#[25=AT06-05\r\n] 2006.148.07:50:39.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:39.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:39.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.07:50:39.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:39.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:50:39.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:50:39.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:50:39.21#ibcon#[25=USB\r\n] 2006.148.07:50:39.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:50:39.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.07:50:39.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:50:39.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:50:39.24$vc4f8/valo=7,832.99 2006.148.07:50:39.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.07:50:39.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.07:50:39.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:39.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:50:39.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:50:39.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:50:39.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:50:39.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:50:39.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.07:50:39.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:50:39.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:50:39.30$vc4f8/va=7,5 2006.148.07:50:39.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.07:50:39.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.07:50:39.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:39.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:50:39.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:50:39.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:50:39.38#ibcon#[25=AT07-05\r\n] 2006.148.07:50:39.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:50:39.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.07:50:39.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.07:50:39.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:39.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:50:39.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:50:39.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:50:39.56#ibcon#[25=USB\r\n] 2006.148.07:50:39.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:50:39.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.07:50:39.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:50:39.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:50:39.58$vc4f8/valo=8,852.99 2006.148.07:50:39.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.07:50:39.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.07:50:39.58#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:39.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:50:39.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:50:39.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:50:39.63#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:50:39.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:50:39.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.07:50:39.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:50:39.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:50:39.66$vc4f8/va=8,5 2006.148.07:50:39.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.07:50:39.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.07:50:39.66#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:39.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:50:39.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:50:39.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:50:39.72#ibcon#[25=AT08-05\r\n] 2006.148.07:50:39.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:50:39.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.07:50:39.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.07:50:39.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:39.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:50:39.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:50:39.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:50:39.89#ibcon#[25=USB\r\n] 2006.148.07:50:39.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:50:39.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.07:50:39.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:50:39.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:50:39.92$vc4f8/vblo=1,632.99 2006.148.07:50:39.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.07:50:39.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.07:50:39.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:39.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:39.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:39.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:39.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:50:39.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:39.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.07:50:39.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:50:39.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:50:39.98$vc4f8/vb=1,4 2006.148.07:50:39.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.07:50:39.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.07:50:39.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:39.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:39.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:39.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:40.00#ibcon#[27=AT01-04\r\n] 2006.148.07:50:40.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:40.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.07:50:40.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.07:50:40.03#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:40.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:40.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:40.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:40.17#ibcon#[27=USB\r\n] 2006.148.07:50:40.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:40.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.07:50:40.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:50:40.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:50:40.20$vc4f8/vblo=2,640.99 2006.148.07:50:40.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.07:50:40.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.07:50:40.20#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:40.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:50:40.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:50:40.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:50:40.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:50:40.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:50:40.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.07:50:40.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:50:40.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:50:40.26$vc4f8/vb=2,4 2006.148.07:50:40.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.07:50:40.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.07:50:40.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:40.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:50:40.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:50:40.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:50:40.35#ibcon#[27=AT02-04\r\n] 2006.148.07:50:40.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:50:40.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.07:50:40.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.07:50:40.38#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:40.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:50:40.50#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:50:40.50#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:50:40.52#ibcon#[27=USB\r\n] 2006.148.07:50:40.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:50:40.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.07:50:40.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:50:40.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:50:40.55$vc4f8/vblo=3,656.99 2006.148.07:50:40.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.07:50:40.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.07:50:40.55#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:40.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:50:40.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:50:40.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:50:40.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:50:40.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:50:40.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.07:50:40.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:50:40.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:50:40.61$vc4f8/vb=3,4 2006.148.07:50:40.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.07:50:40.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.07:50:40.61#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:40.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:50:40.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:50:40.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:50:40.69#ibcon#[27=AT03-04\r\n] 2006.148.07:50:40.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:50:40.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.07:50:40.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.07:50:40.72#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:40.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:50:40.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:50:40.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:50:40.86#ibcon#[27=USB\r\n] 2006.148.07:50:40.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:50:40.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.07:50:40.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:50:40.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:50:40.89$vc4f8/vblo=4,712.99 2006.148.07:50:40.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.07:50:40.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.07:50:40.89#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:40.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:40.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:40.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:40.91#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:50:40.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:40.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.07:50:40.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:50:40.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:50:40.95$vc4f8/vb=4,4 2006.148.07:50:40.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.07:50:40.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.07:50:40.95#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:40.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:41.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:41.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:41.03#ibcon#[27=AT04-04\r\n] 2006.148.07:50:41.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:41.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.07:50:41.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.07:50:41.06#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:41.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:41.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:41.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:41.22#ibcon#[27=USB\r\n] 2006.148.07:50:41.25#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:41.25#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.07:50:41.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:50:41.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:50:41.25$vc4f8/vblo=5,744.99 2006.148.07:50:41.25#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.07:50:41.25#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.07:50:41.25#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:41.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:41.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:41.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:41.27#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:50:41.31#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:41.31#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.07:50:41.31#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:50:41.31#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:50:41.31$vc4f8/vb=5,3 2006.148.07:50:41.31#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.07:50:41.31#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.07:50:41.31#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:41.31#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:41.37#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:41.37#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:41.39#ibcon#[27=AT05-03\r\n] 2006.148.07:50:41.42#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:41.42#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.07:50:41.42#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.07:50:41.42#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:41.42#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:41.54#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:41.54#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:41.56#ibcon#[27=USB\r\n] 2006.148.07:50:41.59#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:41.59#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.07:50:41.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:50:41.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:50:41.59$vc4f8/vblo=6,752.99 2006.148.07:50:41.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.07:50:41.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.07:50:41.59#ibcon#ireg 17 cls_cnt 0 2006.148.07:50:41.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:41.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:41.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:41.61#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:50:41.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:41.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.07:50:41.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:50:41.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:50:41.65$vc4f8/vb=6,4 2006.148.07:50:41.65#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.07:50:41.65#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.07:50:41.65#ibcon#ireg 11 cls_cnt 2 2006.148.07:50:41.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:41.71#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:41.71#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:41.73#ibcon#[27=AT06-04\r\n] 2006.148.07:50:41.76#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:41.76#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.07:50:41.76#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.07:50:41.76#ibcon#ireg 7 cls_cnt 0 2006.148.07:50:41.76#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:41.88#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:41.88#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:41.90#ibcon#[27=USB\r\n] 2006.148.07:50:41.93#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:41.93#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.07:50:41.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:50:41.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:50:41.93$vc4f8/vabw=wide 2006.148.07:50:41.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:50:41.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:50:41.93#ibcon#ireg 8 cls_cnt 0 2006.148.07:50:41.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:41.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:41.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:41.95#ibcon#[25=BW32\r\n] 2006.148.07:50:41.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:41.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:50:41.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:50:41.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:50:41.98$vc4f8/vbbw=wide 2006.148.07:50:41.98#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.07:50:41.98#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.07:50:41.98#ibcon#ireg 8 cls_cnt 0 2006.148.07:50:41.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:50:42.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:50:42.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:50:42.07#ibcon#[27=BW32\r\n] 2006.148.07:50:42.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:50:42.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:50:42.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:50:42.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:50:42.10$4f8m12a/ifd4f 2006.148.07:50:42.10$ifd4f/lo= 2006.148.07:50:42.10$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:50:42.10$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:50:42.10$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:50:42.10$ifd4f/patch= 2006.148.07:50:42.10$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:50:42.10$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:50:42.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:50:42.11$4f8m12a/"form=m,16.000,1:2 2006.148.07:50:42.11$4f8m12a/"tpicd 2006.148.07:50:42.11$4f8m12a/echo=off 2006.148.07:50:42.11$4f8m12a/xlog=off 2006.148.07:50:42.11:!2006.148.07:51:20 2006.148.07:51:00.13#trakl#Source acquired 2006.148.07:51:00.13#flagr#flagr/antenna,acquired 2006.148.07:51:20.01:preob 2006.148.07:51:21.13/onsource/TRACKING 2006.148.07:51:21.13:!2006.148.07:51:30 2006.148.07:51:30.00:data_valid=on 2006.148.07:51:30.00:midob 2006.148.07:51:30.14/onsource/TRACKING 2006.148.07:51:30.14/wx/21.92,994.2,94 2006.148.07:51:30.20/cable/+6.5336E-03 2006.148.07:51:31.29/va/01,08,usb,yes,30,31 2006.148.07:51:31.29/va/02,07,usb,yes,30,31 2006.148.07:51:31.29/va/03,08,usb,yes,22,23 2006.148.07:51:31.29/va/04,07,usb,yes,30,33 2006.148.07:51:31.29/va/05,06,usb,yes,33,35 2006.148.07:51:31.29/va/06,05,usb,yes,33,33 2006.148.07:51:31.29/va/07,05,usb,yes,33,33 2006.148.07:51:31.29/va/08,05,usb,yes,36,35 2006.148.07:51:31.52/valo/01,532.99,yes,locked 2006.148.07:51:31.52/valo/02,572.99,yes,locked 2006.148.07:51:31.52/valo/03,672.99,yes,locked 2006.148.07:51:31.52/valo/04,832.99,yes,locked 2006.148.07:51:31.52/valo/05,652.99,yes,locked 2006.148.07:51:31.52/valo/06,772.99,yes,locked 2006.148.07:51:31.52/valo/07,832.99,yes,locked 2006.148.07:51:31.52/valo/08,852.99,yes,locked 2006.148.07:51:32.61/vb/01,04,usb,yes,29,28 2006.148.07:51:32.61/vb/02,04,usb,yes,31,32 2006.148.07:51:32.61/vb/03,04,usb,yes,27,31 2006.148.07:51:32.61/vb/04,04,usb,yes,28,30 2006.148.07:51:32.61/vb/05,03,usb,yes,33,38 2006.148.07:51:32.61/vb/06,04,usb,yes,28,30 2006.148.07:51:32.61/vb/07,04,usb,yes,30,29 2006.148.07:51:32.61/vb/08,03,usb,yes,34,38 2006.148.07:51:32.85/vblo/01,632.99,yes,locked 2006.148.07:51:32.85/vblo/02,640.99,yes,locked 2006.148.07:51:32.85/vblo/03,656.99,yes,locked 2006.148.07:51:32.85/vblo/04,712.99,yes,locked 2006.148.07:51:32.85/vblo/05,744.99,yes,locked 2006.148.07:51:32.85/vblo/06,752.99,yes,locked 2006.148.07:51:32.85/vblo/07,734.99,yes,locked 2006.148.07:51:32.85/vblo/08,744.99,yes,locked 2006.148.07:51:33.00/vabw/8 2006.148.07:51:33.15/vbbw/8 2006.148.07:51:33.24/xfe/off,on,15.2 2006.148.07:51:33.62/ifatt/23,28,28,28 2006.148.07:51:34.07/fmout-gps/S +4.94E-07 2006.148.07:51:34.16:!2006.148.07:52:30 2006.148.07:52:30.01:data_valid=off 2006.148.07:52:30.02:postob 2006.148.07:52:30.10/cable/+6.5338E-03 2006.148.07:52:30.11/wx/21.92,994.1,94 2006.148.07:52:31.07/fmout-gps/S +4.93E-07 2006.148.07:52:31.08:scan_name=148-0753,k06148,60 2006.148.07:52:31.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.148.07:52:32.14#flagr#flagr/antenna,new-source 2006.148.07:52:32.15:checkk5 2006.148.07:52:32.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:52:32.92/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:52:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:52:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:52:34.10/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0751*_20??1480751??.k5 file! 2006.148.07:52:34.49/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0751*_20??1480751??.k5 file! 2006.148.07:52:34.87/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0751*_20??1480751??.k5 file! 2006.148.07:52:35.26/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0751*_20??1480751??.k5 file! 2006.148.07:52:35.96/k5log//k5ts1_log_newline 2006.148.07:52:36.65/k5log//k5ts2_log_newline 2006.148.07:52:37.34/k5log//k5ts3_log_newline 2006.148.07:52:38.03/k5log//k5ts4_log_newline 2006.148.07:52:38.22/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:52:38.22:4f8m12a=1 2006.148.07:52:38.22$4f8m12a/echo=on 2006.148.07:52:38.22$4f8m12a/pcalon 2006.148.07:52:38.22$pcalon/"no phase cal control is implemented here 2006.148.07:52:38.22$4f8m12a/"tpicd=stop 2006.148.07:52:38.22$4f8m12a/vc4f8 2006.148.07:52:38.22$vc4f8/valo=1,532.99 2006.148.07:52:38.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:52:38.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:52:38.23#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:38.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:38.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:38.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:38.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:52:38.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:38.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:38.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:52:38.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:52:38.30$vc4f8/va=1,8 2006.148.07:52:38.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:52:38.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:52:38.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:38.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:38.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:38.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:38.31#ibcon#[25=AT01-08\r\n] 2006.148.07:52:38.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:38.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:38.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:52:38.34#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:38.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:38.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:38.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:38.48#ibcon#[25=USB\r\n] 2006.148.07:52:38.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:38.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:38.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:52:38.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:52:38.51$vc4f8/valo=2,572.99 2006.148.07:52:38.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:52:38.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:52:38.51#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:38.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:38.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:38.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:38.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:52:38.59#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:38.59#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:38.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:52:38.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:52:38.59$vc4f8/va=2,7 2006.148.07:52:38.59#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:52:38.59#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:52:38.59#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:38.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:38.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:38.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:38.65#ibcon#[25=AT02-07\r\n] 2006.148.07:52:38.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:38.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:38.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:52:38.68#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:38.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:38.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:38.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:38.82#ibcon#[25=USB\r\n] 2006.148.07:52:38.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:38.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:38.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:52:38.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:52:38.85$vc4f8/valo=3,672.99 2006.148.07:52:38.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:52:38.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:52:38.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:38.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:38.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:38.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:38.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:52:38.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:38.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:38.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:52:38.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:52:38.93$vc4f8/va=3,8 2006.148.07:52:38.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:52:38.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:52:38.93#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:38.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:38.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:38.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:38.99#ibcon#[25=AT03-08\r\n] 2006.148.07:52:39.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:39.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:39.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:52:39.02#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:39.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:39.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:39.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:39.16#ibcon#[25=USB\r\n] 2006.148.07:52:39.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:39.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:39.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:52:39.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:52:39.19$vc4f8/valo=4,832.99 2006.148.07:52:39.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:52:39.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:52:39.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:39.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:39.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:39.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:39.21#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:52:39.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:39.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:39.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:52:39.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:52:39.25$vc4f8/va=4,7 2006.148.07:52:39.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:52:39.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:52:39.25#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:39.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:39.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:39.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:39.33#ibcon#[25=AT04-07\r\n] 2006.148.07:52:39.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:39.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:39.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:52:39.36#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:39.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:39.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:39.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:39.50#ibcon#[25=USB\r\n] 2006.148.07:52:39.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:39.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:39.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:52:39.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:52:39.53$vc4f8/valo=5,652.99 2006.148.07:52:39.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:52:39.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:52:39.53#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:39.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:39.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:39.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:39.55#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:52:39.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:39.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:39.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:52:39.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:52:39.59$vc4f8/va=5,6 2006.148.07:52:39.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:52:39.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:52:39.59#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:39.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:52:39.62#abcon#<5=/08 1.8 5.1 21.92 94 994.1\r\n> 2006.148.07:52:39.64#abcon#{5=INTERFACE CLEAR} 2006.148.07:52:39.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:52:39.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:52:39.67#ibcon#[25=AT05-06\r\n] 2006.148.07:52:39.70#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:52:39.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:52:39.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:52:39.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:52:39.70#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:39.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:52:39.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:52:39.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:52:39.84#ibcon#[25=USB\r\n] 2006.148.07:52:39.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:52:39.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:52:39.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:52:39.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:52:39.87$vc4f8/valo=6,772.99 2006.148.07:52:39.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:52:39.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:52:39.87#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:39.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:39.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:39.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:39.89#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:52:39.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:39.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:39.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:52:39.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:52:39.94$vc4f8/va=6,5 2006.148.07:52:39.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.07:52:39.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.07:52:39.94#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:39.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:39.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:39.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:40.00#ibcon#[25=AT06-05\r\n] 2006.148.07:52:40.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:40.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:40.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.07:52:40.03#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:40.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:52:40.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:52:40.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:52:40.17#ibcon#[25=USB\r\n] 2006.148.07:52:40.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:52:40.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.07:52:40.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:52:40.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:52:40.20$vc4f8/valo=7,832.99 2006.148.07:52:40.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.07:52:40.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.07:52:40.20#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:40.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:52:40.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:52:40.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:52:40.22#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:52:40.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:52:40.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.07:52:40.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:52:40.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:52:40.26$vc4f8/va=7,5 2006.148.07:52:40.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.07:52:40.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.07:52:40.26#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:40.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:52:40.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:52:40.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:52:40.34#ibcon#[25=AT07-05\r\n] 2006.148.07:52:40.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:52:40.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.07:52:40.37#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.07:52:40.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:40.37#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:52:40.49#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:52:40.49#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:52:40.51#ibcon#[25=USB\r\n] 2006.148.07:52:40.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:52:40.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.07:52:40.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:52:40.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:52:40.54$vc4f8/valo=8,852.99 2006.148.07:52:40.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.07:52:40.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.07:52:40.54#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:40.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:52:40.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:52:40.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:52:40.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:52:40.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:52:40.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.07:52:40.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:52:40.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:52:40.60$vc4f8/va=8,5 2006.148.07:52:40.60#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.07:52:40.60#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.07:52:40.60#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:40.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:52:40.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:52:40.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:52:40.68#ibcon#[25=AT08-05\r\n] 2006.148.07:52:40.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:52:40.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.07:52:40.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.07:52:40.71#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:40.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:52:40.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:52:40.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:52:40.85#ibcon#[25=USB\r\n] 2006.148.07:52:40.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:52:40.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.07:52:40.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:52:40.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:52:40.88$vc4f8/vblo=1,632.99 2006.148.07:52:40.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.07:52:40.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.07:52:40.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:40.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:40.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:40.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:40.90#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:52:40.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:40.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.07:52:40.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:52:40.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:52:40.94$vc4f8/vb=1,4 2006.148.07:52:40.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.07:52:40.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.07:52:40.94#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:40.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:40.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:40.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:40.96#ibcon#[27=AT01-04\r\n] 2006.148.07:52:40.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:40.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.07:52:40.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.07:52:40.99#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:40.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:41.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:41.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:41.13#ibcon#[27=USB\r\n] 2006.148.07:52:41.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:41.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.07:52:41.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:52:41.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:52:41.16$vc4f8/vblo=2,640.99 2006.148.07:52:41.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:52:41.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:52:41.16#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:41.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:41.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:41.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:41.18#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:52:41.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:41.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:52:41.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:52:41.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:52:41.22$vc4f8/vb=2,4 2006.148.07:52:41.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:52:41.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:52:41.22#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:41.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:41.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:41.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:41.30#ibcon#[27=AT02-04\r\n] 2006.148.07:52:41.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:41.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:52:41.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:52:41.33#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:41.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:41.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:41.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:41.47#ibcon#[27=USB\r\n] 2006.148.07:52:41.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:41.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:52:41.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:52:41.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:52:41.50$vc4f8/vblo=3,656.99 2006.148.07:52:41.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.07:52:41.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.07:52:41.50#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:41.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:41.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:41.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:41.52#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:52:41.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:41.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.07:52:41.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:52:41.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:52:41.56$vc4f8/vb=3,4 2006.148.07:52:41.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.07:52:41.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.07:52:41.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:41.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:41.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:41.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:41.65#ibcon#[27=AT03-04\r\n] 2006.148.07:52:41.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:41.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.07:52:41.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.07:52:41.68#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:41.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:41.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:41.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:41.82#ibcon#[27=USB\r\n] 2006.148.07:52:41.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:41.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.07:52:41.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:52:41.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:52:41.85$vc4f8/vblo=4,712.99 2006.148.07:52:41.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.07:52:41.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.07:52:41.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:41.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:41.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:41.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:41.87#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:52:41.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:41.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.07:52:41.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:52:41.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:52:41.91$vc4f8/vb=4,4 2006.148.07:52:41.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.07:52:41.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.07:52:41.91#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:41.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:41.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:41.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:41.99#ibcon#[27=AT04-04\r\n] 2006.148.07:52:42.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:42.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.07:52:42.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.07:52:42.02#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:42.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:42.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:42.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:42.16#ibcon#[27=USB\r\n] 2006.148.07:52:42.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:42.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.07:52:42.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:52:42.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:52:42.19$vc4f8/vblo=5,744.99 2006.148.07:52:42.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.07:52:42.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.07:52:42.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:42.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:42.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:42.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:42.21#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:52:42.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:42.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.07:52:42.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:52:42.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:52:42.25$vc4f8/vb=5,3 2006.148.07:52:42.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.07:52:42.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.07:52:42.25#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:42.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:52:42.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:52:42.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:52:42.33#ibcon#[27=AT05-03\r\n] 2006.148.07:52:42.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:52:42.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.07:52:42.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.07:52:42.36#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:42.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:52:42.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:52:42.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:52:42.50#ibcon#[27=USB\r\n] 2006.148.07:52:42.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:52:42.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.07:52:42.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:52:42.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:52:42.53$vc4f8/vblo=6,752.99 2006.148.07:52:42.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.07:52:42.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.07:52:42.53#ibcon#ireg 17 cls_cnt 0 2006.148.07:52:42.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:52:42.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:52:42.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:52:42.55#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:52:42.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:52:42.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.07:52:42.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:52:42.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:52:42.59$vc4f8/vb=6,4 2006.148.07:52:42.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.07:52:42.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.07:52:42.59#ibcon#ireg 11 cls_cnt 2 2006.148.07:52:42.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:52:42.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:52:42.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:52:42.67#ibcon#[27=AT06-04\r\n] 2006.148.07:52:42.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:52:42.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.07:52:42.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.07:52:42.70#ibcon#ireg 7 cls_cnt 0 2006.148.07:52:42.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:52:42.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:52:42.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:52:42.84#ibcon#[27=USB\r\n] 2006.148.07:52:42.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:52:42.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.07:52:42.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:52:42.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:52:42.87$vc4f8/vabw=wide 2006.148.07:52:42.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.07:52:42.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.07:52:42.87#ibcon#ireg 8 cls_cnt 0 2006.148.07:52:42.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:42.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:42.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:42.89#ibcon#[25=BW32\r\n] 2006.148.07:52:42.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:42.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.07:52:42.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:52:42.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:52:42.92$vc4f8/vbbw=wide 2006.148.07:52:42.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:52:42.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:52:42.92#ibcon#ireg 8 cls_cnt 0 2006.148.07:52:42.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:52:42.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:52:42.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:52:43.01#ibcon#[27=BW32\r\n] 2006.148.07:52:43.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:52:43.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:52:43.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:52:43.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:52:43.04$4f8m12a/ifd4f 2006.148.07:52:43.04$ifd4f/lo= 2006.148.07:52:43.04$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:52:43.04$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:52:43.04$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:52:43.04$ifd4f/patch= 2006.148.07:52:43.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:52:43.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:52:43.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:52:43.04$4f8m12a/"form=m,16.000,1:2 2006.148.07:52:43.04$4f8m12a/"tpicd 2006.148.07:52:43.04$4f8m12a/echo=off 2006.148.07:52:43.05$4f8m12a/xlog=off 2006.148.07:52:43.05:!2006.148.07:53:10 2006.148.07:52:53.14#trakl#Source acquired 2006.148.07:52:54.14#flagr#flagr/antenna,acquired 2006.148.07:53:10.01:preob 2006.148.07:53:11.14/onsource/TRACKING 2006.148.07:53:11.14:!2006.148.07:53:20 2006.148.07:53:20.00:data_valid=on 2006.148.07:53:20.00:midob 2006.148.07:53:20.14/onsource/TRACKING 2006.148.07:53:20.14/wx/21.93,994.2,94 2006.148.07:53:20.22/cable/+6.5358E-03 2006.148.07:53:21.31/va/01,08,usb,yes,29,31 2006.148.07:53:21.31/va/02,07,usb,yes,29,30 2006.148.07:53:21.31/va/03,08,usb,yes,22,22 2006.148.07:53:21.31/va/04,07,usb,yes,30,32 2006.148.07:53:21.31/va/05,06,usb,yes,32,34 2006.148.07:53:21.31/va/06,05,usb,yes,33,32 2006.148.07:53:21.31/va/07,05,usb,yes,33,32 2006.148.07:53:21.31/va/08,05,usb,yes,35,35 2006.148.07:53:21.54/valo/01,532.99,yes,locked 2006.148.07:53:21.54/valo/02,572.99,yes,locked 2006.148.07:53:21.54/valo/03,672.99,yes,locked 2006.148.07:53:21.54/valo/04,832.99,yes,locked 2006.148.07:53:21.54/valo/05,652.99,yes,locked 2006.148.07:53:21.54/valo/06,772.99,yes,locked 2006.148.07:53:21.54/valo/07,832.99,yes,locked 2006.148.07:53:21.54/valo/08,852.99,yes,locked 2006.148.07:53:22.63/vb/01,04,usb,yes,29,27 2006.148.07:53:22.63/vb/02,04,usb,yes,30,32 2006.148.07:53:22.63/vb/03,04,usb,yes,27,31 2006.148.07:53:22.63/vb/04,04,usb,yes,28,30 2006.148.07:53:22.63/vb/05,03,usb,yes,33,37 2006.148.07:53:22.63/vb/06,04,usb,yes,27,30 2006.148.07:53:22.63/vb/07,04,usb,yes,29,29 2006.148.07:53:22.63/vb/08,03,usb,yes,34,37 2006.148.07:53:22.86/vblo/01,632.99,yes,locked 2006.148.07:53:22.86/vblo/02,640.99,yes,locked 2006.148.07:53:22.86/vblo/03,656.99,yes,locked 2006.148.07:53:22.86/vblo/04,712.99,yes,locked 2006.148.07:53:22.86/vblo/05,744.99,yes,locked 2006.148.07:53:22.86/vblo/06,752.99,yes,locked 2006.148.07:53:22.86/vblo/07,734.99,yes,locked 2006.148.07:53:22.86/vblo/08,744.99,yes,locked 2006.148.07:53:23.01/vabw/8 2006.148.07:53:23.16/vbbw/8 2006.148.07:53:23.36/xfe/off,on,16.0 2006.148.07:53:23.75/ifatt/23,28,28,28 2006.148.07:53:24.07/fmout-gps/S +4.92E-07 2006.148.07:53:24.11:!2006.148.07:54:20 2006.148.07:54:20.01:data_valid=off 2006.148.07:54:20.02:postob 2006.148.07:54:20.16/cable/+6.5326E-03 2006.148.07:54:20.17/wx/21.95,994.1,93 2006.148.07:54:21.07/fmout-gps/S +4.91E-07 2006.148.07:54:21.08:scan_name=148-0756,k06148,60 2006.148.07:54:21.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.148.07:54:22.14#flagr#flagr/antenna,new-source 2006.148.07:54:22.15:checkk5 2006.148.07:54:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:54:22.93/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:54:26.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:54:26.68/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:54:27.10/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0753*_20??1480753??.k5 file! 2006.148.07:54:27.49/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0753*_20??1480753??.k5 file! 2006.148.07:54:27.87/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0753*_20??1480753??.k5 file! 2006.148.07:54:28.26/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0753*_20??1480753??.k5 file! 2006.148.07:54:28.95/k5log//k5ts1_log_newline 2006.148.07:54:29.66/k5log//k5ts2_log_newline 2006.148.07:54:30.35/k5log//k5ts3_log_newline 2006.148.07:54:31.04/k5log//k5ts4_log_newline 2006.148.07:54:31.23/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:54:31.23:4f8m12a=2 2006.148.07:54:31.23$4f8m12a/echo=on 2006.148.07:54:31.23$4f8m12a/pcalon 2006.148.07:54:31.23$pcalon/"no phase cal control is implemented here 2006.148.07:54:31.23$4f8m12a/"tpicd=stop 2006.148.07:54:31.23$4f8m12a/vc4f8 2006.148.07:54:31.23$vc4f8/valo=1,532.99 2006.148.07:54:31.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:54:31.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:54:31.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:31.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:31.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:31.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:31.25#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:54:31.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:31.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:31.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:54:31.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:54:31.30$vc4f8/va=1,8 2006.148.07:54:31.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:54:31.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:54:31.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:31.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:31.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:31.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:31.32#ibcon#[25=AT01-08\r\n] 2006.148.07:54:31.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:31.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:31.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:54:31.35#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:31.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:31.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:31.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:31.49#ibcon#[25=USB\r\n] 2006.148.07:54:31.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:31.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:31.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:54:31.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:54:31.55$vc4f8/valo=2,572.99 2006.148.07:54:31.55#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:54:31.55#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:54:31.55#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:31.55#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:54:31.55#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:54:31.55#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:54:31.56#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:54:31.59#abcon#<5=/08 1.7 5.1 21.95 93 994.1\r\n> 2006.148.07:54:31.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:54:31.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:54:31.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:54:31.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:54:31.60$vc4f8/va=2,7 2006.148.07:54:31.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.07:54:31.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.07:54:31.60#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:31.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:54:31.63#abcon#{5=INTERFACE CLEAR} 2006.148.07:54:31.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:54:31.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:54:31.69#ibcon#[25=AT02-07\r\n] 2006.148.07:54:31.69#abcon#[5=S1D000X0/0*\r\n] 2006.148.07:54:31.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:54:31.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.07:54:31.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.07:54:31.73#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:31.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:54:31.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:54:31.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:54:31.86#ibcon#[25=USB\r\n] 2006.148.07:54:31.92#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:54:31.92#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.07:54:31.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:54:31.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:54:31.92$vc4f8/valo=3,672.99 2006.148.07:54:31.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:54:31.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:54:31.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:31.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:31.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:31.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:31.93#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:54:31.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:31.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:31.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:54:31.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:54:31.97$vc4f8/va=3,8 2006.148.07:54:31.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:54:31.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:54:31.97#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:31.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:32.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:32.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:32.06#ibcon#[25=AT03-08\r\n] 2006.148.07:54:32.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:32.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:32.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:54:32.09#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:32.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:32.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:32.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:32.23#ibcon#[25=USB\r\n] 2006.148.07:54:32.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:32.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:32.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:54:32.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:54:32.26$vc4f8/valo=4,832.99 2006.148.07:54:32.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:54:32.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:54:32.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:32.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:32.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:32.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:32.28#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:54:32.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:32.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:32.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:54:32.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:54:32.32$vc4f8/va=4,7 2006.148.07:54:32.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:54:32.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:54:32.32#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:32.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:32.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:32.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:32.40#ibcon#[25=AT04-07\r\n] 2006.148.07:54:32.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:32.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:32.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:54:32.43#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:32.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:32.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:32.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:32.57#ibcon#[25=USB\r\n] 2006.148.07:54:32.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:32.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:32.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:54:32.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:54:32.60$vc4f8/valo=5,652.99 2006.148.07:54:32.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:54:32.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:54:32.60#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:32.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:32.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:32.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:32.62#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:54:32.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:32.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:32.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:54:32.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:54:32.68$vc4f8/va=5,6 2006.148.07:54:32.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:54:32.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:54:32.68#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:32.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:32.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:32.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:32.74#ibcon#[25=AT05-06\r\n] 2006.148.07:54:32.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:32.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:32.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:54:32.77#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:32.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:32.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:32.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:32.91#ibcon#[25=USB\r\n] 2006.148.07:54:32.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:32.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:32.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:54:32.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:54:32.94$vc4f8/valo=6,772.99 2006.148.07:54:32.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.07:54:32.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.07:54:32.94#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:32.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:32.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:32.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:32.96#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:54:33.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:33.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:33.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:54:33.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:54:33.00$vc4f8/va=6,5 2006.148.07:54:33.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.07:54:33.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.07:54:33.00#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:33.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:33.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:33.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:33.08#ibcon#[25=AT06-05\r\n] 2006.148.07:54:33.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:33.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:33.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.07:54:33.11#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:33.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:54:33.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:54:33.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:54:33.25#ibcon#[25=USB\r\n] 2006.148.07:54:33.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:54:33.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.07:54:33.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:54:33.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:54:33.28$vc4f8/valo=7,832.99 2006.148.07:54:33.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.07:54:33.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.07:54:33.28#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:33.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:54:33.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:54:33.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:54:33.30#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:54:33.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:54:33.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.07:54:33.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.07:54:33.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.07:54:33.34$vc4f8/va=7,5 2006.148.07:54:33.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.07:54:33.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.07:54:33.34#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:33.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:54:33.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:54:33.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:54:33.42#ibcon#[25=AT07-05\r\n] 2006.148.07:54:33.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:54:33.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.07:54:33.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.07:54:33.45#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:33.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:54:33.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:54:33.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:54:33.59#ibcon#[25=USB\r\n] 2006.148.07:54:33.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:54:33.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.07:54:33.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.07:54:33.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.07:54:33.62$vc4f8/valo=8,852.99 2006.148.07:54:33.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.07:54:33.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.07:54:33.62#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:33.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:54:33.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:54:33.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:54:33.64#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:54:33.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:54:33.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.07:54:33.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.07:54:33.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.07:54:33.68$vc4f8/va=8,5 2006.148.07:54:33.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.07:54:33.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.07:54:33.68#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:33.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:54:33.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:54:33.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:54:33.76#ibcon#[25=AT08-05\r\n] 2006.148.07:54:33.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:54:33.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.07:54:33.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.07:54:33.79#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:33.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:54:33.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:54:33.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:54:33.93#ibcon#[25=USB\r\n] 2006.148.07:54:33.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:54:33.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.07:54:33.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.07:54:33.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.07:54:33.96$vc4f8/vblo=1,632.99 2006.148.07:54:33.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.07:54:33.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.07:54:33.96#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:33.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:33.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:33.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:33.98#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:54:34.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:34.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.07:54:34.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.07:54:34.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.07:54:34.02$vc4f8/vb=1,4 2006.148.07:54:34.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.07:54:34.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.07:54:34.02#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:34.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:34.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:34.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:34.04#ibcon#[27=AT01-04\r\n] 2006.148.07:54:34.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:34.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.07:54:34.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.07:54:34.07#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:34.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:34.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:34.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:34.21#ibcon#[27=USB\r\n] 2006.148.07:54:34.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:34.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.07:54:34.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.07:54:34.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.07:54:34.24$vc4f8/vblo=2,640.99 2006.148.07:54:34.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.07:54:34.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.07:54:34.24#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:34.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:54:34.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:54:34.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:54:34.26#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:54:34.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:54:34.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.07:54:34.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.07:54:34.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.07:54:34.30$vc4f8/vb=2,4 2006.148.07:54:34.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.07:54:34.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.07:54:34.30#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:34.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:54:34.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:54:34.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:54:34.38#ibcon#[27=AT02-04\r\n] 2006.148.07:54:34.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:54:34.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.07:54:34.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.07:54:34.41#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:34.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:54:34.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:54:34.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:54:34.55#ibcon#[27=USB\r\n] 2006.148.07:54:34.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:54:34.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.07:54:34.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.07:54:34.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.07:54:34.58$vc4f8/vblo=3,656.99 2006.148.07:54:34.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.07:54:34.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.07:54:34.58#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:34.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:54:34.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:54:34.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:54:34.60#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:54:34.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:54:34.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.07:54:34.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.07:54:34.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.07:54:34.64$vc4f8/vb=3,4 2006.148.07:54:34.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.07:54:34.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.07:54:34.64#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:34.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:54:34.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:54:34.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:54:34.72#ibcon#[27=AT03-04\r\n] 2006.148.07:54:34.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:54:34.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.07:54:34.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.07:54:34.75#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:34.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:54:34.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:54:34.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:54:34.89#ibcon#[27=USB\r\n] 2006.148.07:54:34.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:54:34.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.07:54:34.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.07:54:34.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.07:54:34.92$vc4f8/vblo=4,712.99 2006.148.07:54:34.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.07:54:34.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.07:54:34.92#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:34.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:34.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:34.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:34.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:54:34.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:34.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.07:54:34.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.07:54:34.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.07:54:34.98$vc4f8/vb=4,4 2006.148.07:54:34.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.07:54:34.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.07:54:34.98#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:34.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:35.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:35.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:35.06#ibcon#[27=AT04-04\r\n] 2006.148.07:54:35.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:35.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.07:54:35.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.07:54:35.09#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:35.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:35.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:35.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:35.23#ibcon#[27=USB\r\n] 2006.148.07:54:35.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:35.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.07:54:35.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.07:54:35.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.07:54:35.26$vc4f8/vblo=5,744.99 2006.148.07:54:35.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.07:54:35.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.07:54:35.26#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:35.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:35.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:35.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:35.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:54:35.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:35.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.07:54:35.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.07:54:35.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.07:54:35.32$vc4f8/vb=5,3 2006.148.07:54:35.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.07:54:35.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.07:54:35.32#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:35.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:35.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:35.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:35.40#ibcon#[27=AT05-03\r\n] 2006.148.07:54:35.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:35.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.07:54:35.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.07:54:35.43#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:35.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:35.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:35.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:35.57#ibcon#[27=USB\r\n] 2006.148.07:54:35.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:35.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.07:54:35.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.07:54:35.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.07:54:35.60$vc4f8/vblo=6,752.99 2006.148.07:54:35.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.07:54:35.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.07:54:35.60#ibcon#ireg 17 cls_cnt 0 2006.148.07:54:35.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:35.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:35.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:35.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:54:35.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:35.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.07:54:35.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.07:54:35.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.07:54:35.66$vc4f8/vb=6,4 2006.148.07:54:35.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.07:54:35.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.07:54:35.66#ibcon#ireg 11 cls_cnt 2 2006.148.07:54:35.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:35.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:35.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:35.74#ibcon#[27=AT06-04\r\n] 2006.148.07:54:35.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:35.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.07:54:35.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.07:54:35.77#ibcon#ireg 7 cls_cnt 0 2006.148.07:54:35.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:35.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:35.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:35.91#ibcon#[27=USB\r\n] 2006.148.07:54:35.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:35.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.07:54:35.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.07:54:35.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.07:54:35.94$vc4f8/vabw=wide 2006.148.07:54:35.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.07:54:35.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.07:54:35.94#ibcon#ireg 8 cls_cnt 0 2006.148.07:54:35.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:35.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:35.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:35.96#ibcon#[25=BW32\r\n] 2006.148.07:54:35.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:35.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.07:54:35.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.07:54:35.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.07:54:35.99$vc4f8/vbbw=wide 2006.148.07:54:35.99#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.07:54:35.99#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.07:54:35.99#ibcon#ireg 8 cls_cnt 0 2006.148.07:54:35.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:54:36.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:54:36.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:54:36.08#ibcon#[27=BW32\r\n] 2006.148.07:54:36.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:54:36.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.07:54:36.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.07:54:36.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.07:54:36.12$4f8m12a/ifd4f 2006.148.07:54:36.12$ifd4f/lo= 2006.148.07:54:36.12$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:54:36.12$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:54:36.12$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:54:36.12$ifd4f/patch= 2006.148.07:54:36.12$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:54:36.12$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:54:36.12$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:54:36.12$4f8m12a/"form=m,16.000,1:2 2006.148.07:54:36.13$4f8m12a/"tpicd 2006.148.07:54:36.13$4f8m12a/echo=off 2006.148.07:54:36.13$4f8m12a/xlog=off 2006.148.07:54:36.13:!2006.148.07:56:00 2006.148.07:54:43.14#trakl#Source acquired 2006.148.07:54:44.14#flagr#flagr/antenna,acquired 2006.148.07:56:00.01:preob 2006.148.07:56:01.14/onsource/TRACKING 2006.148.07:56:01.14:!2006.148.07:56:10 2006.148.07:56:10.00:data_valid=on 2006.148.07:56:10.00:midob 2006.148.07:56:10.14/onsource/TRACKING 2006.148.07:56:10.14/wx/21.96,994.2,93 2006.148.07:56:10.24/cable/+6.5359E-03 2006.148.07:56:11.33/va/01,08,usb,yes,30,31 2006.148.07:56:11.33/va/02,07,usb,yes,30,31 2006.148.07:56:11.33/va/03,08,usb,yes,22,22 2006.148.07:56:11.33/va/04,07,usb,yes,30,33 2006.148.07:56:11.33/va/05,06,usb,yes,33,35 2006.148.07:56:11.33/va/06,05,usb,yes,33,33 2006.148.07:56:11.33/va/07,05,usb,yes,33,33 2006.148.07:56:11.33/va/08,05,usb,yes,36,35 2006.148.07:56:11.56/valo/01,532.99,yes,locked 2006.148.07:56:11.56/valo/02,572.99,yes,locked 2006.148.07:56:11.56/valo/03,672.99,yes,locked 2006.148.07:56:11.56/valo/04,832.99,yes,locked 2006.148.07:56:11.56/valo/05,652.99,yes,locked 2006.148.07:56:11.56/valo/06,772.99,yes,locked 2006.148.07:56:11.56/valo/07,832.99,yes,locked 2006.148.07:56:11.56/valo/08,852.99,yes,locked 2006.148.07:56:12.65/vb/01,04,usb,yes,29,28 2006.148.07:56:12.65/vb/02,04,usb,yes,31,33 2006.148.07:56:12.65/vb/03,04,usb,yes,28,31 2006.148.07:56:12.65/vb/04,04,usb,yes,28,29 2006.148.07:56:12.65/vb/05,03,usb,yes,34,38 2006.148.07:56:12.65/vb/06,04,usb,yes,28,31 2006.148.07:56:12.65/vb/07,04,usb,yes,30,30 2006.148.07:56:12.65/vb/08,03,usb,yes,34,38 2006.148.07:56:12.88/vblo/01,632.99,yes,locked 2006.148.07:56:12.88/vblo/02,640.99,yes,locked 2006.148.07:56:12.88/vblo/03,656.99,yes,locked 2006.148.07:56:12.88/vblo/04,712.99,yes,locked 2006.148.07:56:12.88/vblo/05,744.99,yes,locked 2006.148.07:56:12.88/vblo/06,752.99,yes,locked 2006.148.07:56:12.88/vblo/07,734.99,yes,locked 2006.148.07:56:12.88/vblo/08,744.99,yes,locked 2006.148.07:56:13.03/vabw/8 2006.148.07:56:13.18/vbbw/8 2006.148.07:56:13.35/xfe/off,on,14.5 2006.148.07:56:13.81/ifatt/23,28,28,28 2006.148.07:56:14.07/fmout-gps/S +4.90E-07 2006.148.07:56:14.16:!2006.148.07:57:10 2006.148.07:57:10.01:data_valid=off 2006.148.07:57:10.02:postob 2006.148.07:57:10.21/cable/+6.5356E-03 2006.148.07:57:10.22/wx/21.96,994.2,93 2006.148.07:57:10.27/fmout-gps/S +4.90E-07 2006.148.07:57:10.28:scan_name=148-0759,k06148,60 2006.148.07:57:10.28:source=3c371,180650.68,694928.1,2000.0,cw 2006.148.07:57:12.14#flagr#flagr/antenna,new-source 2006.148.07:57:12.15:checkk5 2006.148.07:57:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.07:57:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.07:57:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.148.07:57:13.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.07:57:14.05/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0756*_20??1480756??.k5 file! 2006.148.07:57:14.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0756*_20??1480756??.k5 file! 2006.148.07:57:14.81/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0756*_20??1480756??.k5 file! 2006.148.07:57:15.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0756*_20??1480756??.k5 file! 2006.148.07:57:15.92/k5log//k5ts1_log_newline 2006.148.07:57:16.62/k5log//k5ts2_log_newline 2006.148.07:57:17.31/k5log//k5ts3_log_newline 2006.148.07:57:18.00/k5log//k5ts4_log_newline 2006.148.07:57:18.18/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.07:57:18.18:4f8m12a=2 2006.148.07:57:18.18$4f8m12a/echo=on 2006.148.07:57:18.18$4f8m12a/pcalon 2006.148.07:57:18.18$pcalon/"no phase cal control is implemented here 2006.148.07:57:18.18$4f8m12a/"tpicd=stop 2006.148.07:57:18.18$4f8m12a/vc4f8 2006.148.07:57:18.18$vc4f8/valo=1,532.99 2006.148.07:57:18.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:57:18.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:57:18.18#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:18.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:18.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:18.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:18.20#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.07:57:18.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:18.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:18.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:57:18.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:57:18.25$vc4f8/va=1,8 2006.148.07:57:18.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:57:18.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:57:18.25#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:18.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:18.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:18.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:18.27#ibcon#[25=AT01-08\r\n] 2006.148.07:57:18.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:18.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:18.30#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:57:18.30#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:18.30#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:18.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:18.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:18.45#ibcon#[25=USB\r\n] 2006.148.07:57:18.48#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:18.48#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:18.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:57:18.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:57:18.48$vc4f8/valo=2,572.99 2006.148.07:57:18.48#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:57:18.48#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:57:18.48#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:18.48#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:18.48#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:18.48#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:18.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.07:57:18.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:18.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:18.56#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:57:18.56#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:57:18.56$vc4f8/va=2,7 2006.148.07:57:18.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:57:18.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:57:18.56#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:18.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:18.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:18.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:18.63#ibcon#[25=AT02-07\r\n] 2006.148.07:57:18.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:18.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:18.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:57:18.65#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:18.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:18.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:18.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:18.79#ibcon#[25=USB\r\n] 2006.148.07:57:18.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:18.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:18.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:57:18.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:57:18.85$vc4f8/valo=3,672.99 2006.148.07:57:18.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:57:18.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:57:18.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:18.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:18.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:18.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:18.86#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.07:57:18.90#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:18.90#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:18.90#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:57:18.90#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:57:18.90$vc4f8/va=3,8 2006.148.07:57:18.90#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:57:18.90#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:57:18.90#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:18.90#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:18.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:18.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:18.99#ibcon#[25=AT03-08\r\n] 2006.148.07:57:19.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:19.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:19.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:57:19.02#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:19.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:19.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:19.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:19.16#ibcon#[25=USB\r\n] 2006.148.07:57:19.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:19.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:19.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:57:19.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:57:19.19$vc4f8/valo=4,832.99 2006.148.07:57:19.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:57:19.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:57:19.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:19.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:19.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:19.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:19.21#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.07:57:19.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:19.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:19.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:57:19.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:57:19.25$vc4f8/va=4,7 2006.148.07:57:19.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:57:19.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:57:19.25#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:19.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:19.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:19.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:19.33#ibcon#[25=AT04-07\r\n] 2006.148.07:57:19.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:19.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:19.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:57:19.36#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:19.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:19.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:19.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:19.50#ibcon#[25=USB\r\n] 2006.148.07:57:19.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:19.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:19.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:57:19.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:57:19.53$vc4f8/valo=5,652.99 2006.148.07:57:19.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:57:19.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:57:19.53#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:19.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:19.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:19.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:19.55#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.07:57:19.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:19.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:19.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:57:19.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:57:19.59$vc4f8/va=5,6 2006.148.07:57:19.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:57:19.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:57:19.59#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:19.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:19.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:19.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:19.67#ibcon#[25=AT05-06\r\n] 2006.148.07:57:19.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:19.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:19.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:57:19.70#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:19.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:19.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:19.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:19.84#ibcon#[25=USB\r\n] 2006.148.07:57:19.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:19.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:19.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:57:19.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:57:19.87$vc4f8/valo=6,772.99 2006.148.07:57:19.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:57:19.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:57:19.87#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:19.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:19.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:19.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:19.89#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.07:57:19.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:19.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:19.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:57:19.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:57:19.93$vc4f8/va=6,5 2006.148.07:57:19.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.07:57:19.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.07:57:19.93#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:19.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:19.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:19.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:20.01#ibcon#[25=AT06-05\r\n] 2006.148.07:57:20.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:20.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:20.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.07:57:20.04#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:20.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:57:20.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:57:20.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:57:20.18#ibcon#[25=USB\r\n] 2006.148.07:57:20.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:57:20.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.07:57:20.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:57:20.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:57:20.21$vc4f8/valo=7,832.99 2006.148.07:57:20.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.07:57:20.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.07:57:20.21#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:20.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:57:20.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:57:20.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:57:20.23#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.07:57:20.29#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:57:20.29#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.07:57:20.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.07:57:20.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.07:57:20.29$vc4f8/va=7,5 2006.148.07:57:20.29#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.07:57:20.29#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.07:57:20.29#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:20.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:57:20.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:57:20.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:57:20.34#ibcon#[25=AT07-05\r\n] 2006.148.07:57:20.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:57:20.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.07:57:20.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.07:57:20.37#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:20.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:57:20.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:57:20.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:57:20.51#ibcon#[25=USB\r\n] 2006.148.07:57:20.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:57:20.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.07:57:20.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.07:57:20.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.07:57:20.54$vc4f8/valo=8,852.99 2006.148.07:57:20.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.07:57:20.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.07:57:20.54#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:20.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:57:20.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:57:20.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:57:20.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.07:57:20.60#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:57:20.60#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.07:57:20.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.07:57:20.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.07:57:20.60$vc4f8/va=8,5 2006.148.07:57:20.60#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.07:57:20.60#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.07:57:20.60#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:20.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:57:20.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:57:20.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:57:20.68#ibcon#[25=AT08-05\r\n] 2006.148.07:57:20.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:57:20.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.07:57:20.71#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.07:57:20.71#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:20.71#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:57:20.83#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:57:20.83#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:57:20.85#ibcon#[25=USB\r\n] 2006.148.07:57:20.88#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:57:20.88#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.07:57:20.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.07:57:20.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.07:57:20.88$vc4f8/vblo=1,632.99 2006.148.07:57:20.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.07:57:20.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.07:57:20.88#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:20.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:57:20.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:57:20.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:57:20.90#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.07:57:20.94#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:57:20.94#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.07:57:20.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.07:57:20.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.07:57:20.94$vc4f8/vb=1,4 2006.148.07:57:20.94#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.07:57:20.94#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.07:57:20.94#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:20.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:57:20.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:57:20.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:57:20.97#ibcon#[27=AT01-04\r\n] 2006.148.07:57:21.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:57:21.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.07:57:21.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.07:57:21.00#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:21.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:57:21.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:57:21.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:57:21.14#ibcon#[27=USB\r\n] 2006.148.07:57:21.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:57:21.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.07:57:21.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.07:57:21.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.07:57:21.17$vc4f8/vblo=2,640.99 2006.148.07:57:21.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.07:57:21.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.07:57:21.17#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:21.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:21.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:21.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:21.19#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.07:57:21.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:21.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.07:57:21.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.07:57:21.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.07:57:21.23$vc4f8/vb=2,4 2006.148.07:57:21.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.07:57:21.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.07:57:21.23#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:21.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:21.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:21.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:21.31#ibcon#[27=AT02-04\r\n] 2006.148.07:57:21.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:21.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.07:57:21.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.07:57:21.34#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:21.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:21.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:21.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:21.48#ibcon#[27=USB\r\n] 2006.148.07:57:21.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:21.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.07:57:21.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.07:57:21.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.07:57:21.51$vc4f8/vblo=3,656.99 2006.148.07:57:21.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.07:57:21.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.07:57:21.51#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:21.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:21.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:21.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:21.53#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.07:57:21.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:21.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.07:57:21.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.07:57:21.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.07:57:21.57$vc4f8/vb=3,4 2006.148.07:57:21.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.07:57:21.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.07:57:21.57#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:21.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:21.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:21.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:21.65#ibcon#[27=AT03-04\r\n] 2006.148.07:57:21.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:21.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.07:57:21.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.07:57:21.68#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:21.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:21.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:21.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:21.82#ibcon#[27=USB\r\n] 2006.148.07:57:21.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:21.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.07:57:21.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.07:57:21.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.07:57:21.85$vc4f8/vblo=4,712.99 2006.148.07:57:21.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.07:57:21.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.07:57:21.85#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:21.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:21.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:21.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:21.87#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.07:57:21.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:21.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.07:57:21.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.07:57:21.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.07:57:21.91$vc4f8/vb=4,4 2006.148.07:57:21.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.07:57:21.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.07:57:21.91#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:21.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:21.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:21.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:21.99#ibcon#[27=AT04-04\r\n] 2006.148.07:57:22.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:22.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.07:57:22.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.07:57:22.02#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:22.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:22.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:22.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:22.16#ibcon#[27=USB\r\n] 2006.148.07:57:22.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:22.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.07:57:22.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.07:57:22.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.07:57:22.19$vc4f8/vblo=5,744.99 2006.148.07:57:22.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.07:57:22.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.07:57:22.19#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:22.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:22.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:22.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:22.21#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.07:57:22.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:22.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.07:57:22.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.07:57:22.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.07:57:22.25$vc4f8/vb=5,3 2006.148.07:57:22.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.07:57:22.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.07:57:22.25#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:22.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:22.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:22.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:22.33#ibcon#[27=AT05-03\r\n] 2006.148.07:57:22.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:22.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.07:57:22.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.07:57:22.36#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:22.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:22.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:22.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:22.50#ibcon#[27=USB\r\n] 2006.148.07:57:22.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:22.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.07:57:22.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.07:57:22.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.07:57:22.53$vc4f8/vblo=6,752.99 2006.148.07:57:22.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.07:57:22.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.07:57:22.53#ibcon#ireg 17 cls_cnt 0 2006.148.07:57:22.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:22.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:22.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:22.58#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.07:57:22.62#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:22.62#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.07:57:22.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.07:57:22.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.07:57:22.62$vc4f8/vb=6,4 2006.148.07:57:22.62#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.07:57:22.62#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.07:57:22.62#ibcon#ireg 11 cls_cnt 2 2006.148.07:57:22.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:22.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:22.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:22.67#ibcon#[27=AT06-04\r\n] 2006.148.07:57:22.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:22.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.07:57:22.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.07:57:22.70#ibcon#ireg 7 cls_cnt 0 2006.148.07:57:22.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:22.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:22.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:22.84#ibcon#[27=USB\r\n] 2006.148.07:57:22.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:22.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.07:57:22.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.07:57:22.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.07:57:22.87$vc4f8/vabw=wide 2006.148.07:57:22.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.07:57:22.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.07:57:22.87#ibcon#ireg 8 cls_cnt 0 2006.148.07:57:22.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:22.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:22.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:22.89#ibcon#[25=BW32\r\n] 2006.148.07:57:22.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:22.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.07:57:22.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.07:57:22.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.07:57:22.92$vc4f8/vbbw=wide 2006.148.07:57:22.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.07:57:22.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.07:57:22.92#ibcon#ireg 8 cls_cnt 0 2006.148.07:57:22.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:57:22.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:57:22.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:57:23.01#ibcon#[27=BW32\r\n] 2006.148.07:57:23.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:57:23.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.07:57:23.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.07:57:23.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.07:57:23.04$4f8m12a/ifd4f 2006.148.07:57:23.04$ifd4f/lo= 2006.148.07:57:23.04$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.07:57:23.04$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.07:57:23.04$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.07:57:23.04$ifd4f/patch= 2006.148.07:57:23.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.07:57:23.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.07:57:23.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.07:57:23.04$4f8m12a/"form=m,16.000,1:2 2006.148.07:57:23.04$4f8m12a/"tpicd 2006.148.07:57:23.04$4f8m12a/echo=off 2006.148.07:57:23.04$4f8m12a/xlog=off 2006.148.07:57:23.04:!2006.148.07:59:30 2006.148.07:57:58.13#trakl#Source acquired 2006.148.07:57:58.13#flagr#flagr/antenna,acquired 2006.148.07:59:30.00:preob 2006.148.07:59:30.13/onsource/TRACKING 2006.148.07:59:30.13:!2006.148.07:59:40 2006.148.07:59:40.00:data_valid=on 2006.148.07:59:40.00:midob 2006.148.07:59:40.13/onsource/TRACKING 2006.148.07:59:40.13/wx/22.00,994.2,93 2006.148.07:59:40.28/cable/+6.5349E-03 2006.148.07:59:41.37/va/01,08,usb,yes,30,32 2006.148.07:59:41.37/va/02,07,usb,yes,30,32 2006.148.07:59:41.37/va/03,08,usb,yes,23,23 2006.148.07:59:41.37/va/04,07,usb,yes,31,33 2006.148.07:59:41.37/va/05,06,usb,yes,34,36 2006.148.07:59:41.37/va/06,05,usb,yes,34,34 2006.148.07:59:41.37/va/07,05,usb,yes,34,34 2006.148.07:59:41.37/va/08,05,usb,yes,37,36 2006.148.07:59:41.60/valo/01,532.99,yes,locked 2006.148.07:59:41.60/valo/02,572.99,yes,locked 2006.148.07:59:41.60/valo/03,672.99,yes,locked 2006.148.07:59:41.60/valo/04,832.99,yes,locked 2006.148.07:59:41.60/valo/05,652.99,yes,locked 2006.148.07:59:41.60/valo/06,772.99,yes,locked 2006.148.07:59:41.60/valo/07,832.99,yes,locked 2006.148.07:59:41.60/valo/08,852.99,yes,locked 2006.148.07:59:42.69/vb/01,04,usb,yes,30,29 2006.148.07:59:42.69/vb/02,04,usb,yes,32,33 2006.148.07:59:42.69/vb/03,04,usb,yes,28,32 2006.148.07:59:42.69/vb/04,04,usb,yes,29,31 2006.148.07:59:42.69/vb/05,03,usb,yes,34,39 2006.148.07:59:42.69/vb/06,04,usb,yes,29,31 2006.148.07:59:42.69/vb/07,04,usb,yes,31,31 2006.148.07:59:42.69/vb/08,03,usb,yes,35,39 2006.148.07:59:42.93/vblo/01,632.99,yes,locked 2006.148.07:59:42.93/vblo/02,640.99,yes,locked 2006.148.07:59:42.93/vblo/03,656.99,yes,locked 2006.148.07:59:42.93/vblo/04,712.99,yes,locked 2006.148.07:59:42.93/vblo/05,744.99,yes,locked 2006.148.07:59:42.93/vblo/06,752.99,yes,locked 2006.148.07:59:42.93/vblo/07,734.99,yes,locked 2006.148.07:59:42.93/vblo/08,744.99,yes,locked 2006.148.07:59:43.08/vabw/8 2006.148.07:59:43.23/vbbw/8 2006.148.07:59:43.32/xfe/off,on,15.0 2006.148.07:59:43.70/ifatt/23,28,28,28 2006.148.07:59:44.07/fmout-gps/S +4.90E-07 2006.148.07:59:44.15:!2006.148.08:00:40 2006.148.08:00:40.01:data_valid=off 2006.148.08:00:40.02:postob 2006.148.08:00:40.21/cable/+6.5334E-03 2006.148.08:00:40.22/wx/22.01,994.2,93 2006.148.08:00:41.07/fmout-gps/S +4.89E-07 2006.148.08:00:41.08:scan_name=148-0802,k06148,90 2006.148.08:00:41.08:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.148.08:00:41.14#flagr#flagr/antenna,new-source 2006.148.08:00:42.14:checkk5 2006.148.08:00:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:00:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:00:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:00:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:00:44.09/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0759*_20??1480759??.k5 file! 2006.148.08:00:44.48/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0759*_20??1480759??.k5 file! 2006.148.08:00:44.86/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0759*_20??1480759??.k5 file! 2006.148.08:00:45.24/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0759*_20??1480759??.k5 file! 2006.148.08:00:45.93/k5log//k5ts1_log_newline 2006.148.08:00:46.62/k5log//k5ts2_log_newline 2006.148.08:00:47.32/k5log//k5ts3_log_newline 2006.148.08:00:48.00/k5log//k5ts4_log_newline 2006.148.08:00:48.20/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:00:48.20:4f8m12a=2 2006.148.08:00:48.20$4f8m12a/echo=on 2006.148.08:00:48.20$4f8m12a/pcalon 2006.148.08:00:48.20$pcalon/"no phase cal control is implemented here 2006.148.08:00:48.20$4f8m12a/"tpicd=stop 2006.148.08:00:48.20$4f8m12a/vc4f8 2006.148.08:00:48.20$vc4f8/valo=1,532.99 2006.148.08:00:48.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:00:48.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:00:48.21#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:48.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:48.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:48.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:48.23#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:00:48.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:48.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:48.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:00:48.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:00:48.29$vc4f8/va=1,8 2006.148.08:00:48.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:00:48.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:00:48.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:48.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:48.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:48.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:48.30#ibcon#[25=AT01-08\r\n] 2006.148.08:00:48.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:48.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:48.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:00:48.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:48.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:48.43#abcon#<5=/08 1.7 5.0 22.02 93 994.2\r\n> 2006.148.08:00:48.47#abcon#{5=INTERFACE CLEAR} 2006.148.08:00:48.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:48.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:48.49#ibcon#[25=USB\r\n] 2006.148.08:00:48.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:48.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:48.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:00:48.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:00:48.52$vc4f8/valo=2,572.99 2006.148.08:00:48.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:00:48.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:00:48.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:48.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:48.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:48.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:48.56#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:00:48.56#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:00:48.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:48.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:48.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:00:48.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:00:48.60$vc4f8/va=2,7 2006.148.08:00:48.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.08:00:48.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.08:00:48.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:48.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:48.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:48.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:48.66#ibcon#[25=AT02-07\r\n] 2006.148.08:00:48.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:48.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:48.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.08:00:48.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:48.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:48.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:48.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:48.83#ibcon#[25=USB\r\n] 2006.148.08:00:48.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:48.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:48.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:00:48.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:00:48.89$vc4f8/valo=3,672.99 2006.148.08:00:48.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.08:00:48.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.08:00:48.89#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:48.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:48.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:48.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:48.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:00:48.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:48.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:48.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:00:48.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:00:48.94$vc4f8/va=3,8 2006.148.08:00:48.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.08:00:48.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.08:00:48.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:48.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:49.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:49.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:49.03#ibcon#[25=AT03-08\r\n] 2006.148.08:00:49.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:49.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:49.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.08:00:49.06#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:49.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:49.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:49.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:49.20#ibcon#[25=USB\r\n] 2006.148.08:00:49.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:49.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:49.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:00:49.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:00:49.23$vc4f8/valo=4,832.99 2006.148.08:00:49.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:00:49.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:00:49.23#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:49.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:49.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:49.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:49.25#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:00:49.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:49.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:49.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:00:49.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:00:49.29$vc4f8/va=4,7 2006.148.08:00:49.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:00:49.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:00:49.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:49.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:49.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:49.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:49.37#ibcon#[25=AT04-07\r\n] 2006.148.08:00:49.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:49.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:49.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:00:49.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:49.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:49.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:49.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:49.54#ibcon#[25=USB\r\n] 2006.148.08:00:49.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:49.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:49.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:00:49.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:00:49.57$vc4f8/valo=5,652.99 2006.148.08:00:49.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:00:49.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:00:49.57#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:49.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:49.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:49.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:49.59#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:00:49.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:49.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:49.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:00:49.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:00:49.63$vc4f8/va=5,6 2006.148.08:00:49.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.08:00:49.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.08:00:49.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:49.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:49.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:49.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:49.72#ibcon#[25=AT05-06\r\n] 2006.148.08:00:49.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:49.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:49.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.08:00:49.74#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:49.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:49.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:49.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:49.88#ibcon#[25=USB\r\n] 2006.148.08:00:49.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:49.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:49.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:00:49.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:00:49.91$vc4f8/valo=6,772.99 2006.148.08:00:49.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.08:00:49.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.08:00:49.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:49.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:49.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:49.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:49.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:00:49.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:49.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:49.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:00:49.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:00:49.97$vc4f8/va=6,5 2006.148.08:00:49.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.08:00:49.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.08:00:49.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:49.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:50.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:50.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:50.05#ibcon#[25=AT06-05\r\n] 2006.148.08:00:50.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:50.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:50.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.08:00:50.08#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:50.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:00:50.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:00:50.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:00:50.22#ibcon#[25=USB\r\n] 2006.148.08:00:50.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:00:50.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:00:50.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:00:50.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:00:50.25$vc4f8/valo=7,832.99 2006.148.08:00:50.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.08:00:50.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.08:00:50.25#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:50.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:00:50.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:00:50.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:00:50.27#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:00:50.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:00:50.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:00:50.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:00:50.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:00:50.31$vc4f8/va=7,5 2006.148.08:00:50.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.08:00:50.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.08:00:50.31#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:50.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:00:50.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:00:50.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:00:50.39#ibcon#[25=AT07-05\r\n] 2006.148.08:00:50.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:00:50.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:00:50.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.08:00:50.42#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:50.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:00:50.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:00:50.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:00:50.56#ibcon#[25=USB\r\n] 2006.148.08:00:50.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:00:50.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:00:50.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:00:50.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:00:50.59$vc4f8/valo=8,852.99 2006.148.08:00:50.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.08:00:50.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.08:00:50.59#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:50.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:00:50.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:00:50.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:00:50.61#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:00:50.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:00:50.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:00:50.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:00:50.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:00:50.65$vc4f8/va=8,5 2006.148.08:00:50.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.08:00:50.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.08:00:50.65#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:50.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:00:50.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:00:50.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:00:50.73#ibcon#[25=AT08-05\r\n] 2006.148.08:00:50.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:00:50.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:00:50.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.08:00:50.76#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:50.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:00:50.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:00:50.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:00:50.90#ibcon#[25=USB\r\n] 2006.148.08:00:50.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:00:50.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:00:50.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:00:50.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:00:50.93$vc4f8/vblo=1,632.99 2006.148.08:00:50.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:00:50.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:00:50.93#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:50.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:50.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:50.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:50.95#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:00:50.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:50.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:00:50.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:00:50.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:00:50.99$vc4f8/vb=1,4 2006.148.08:00:50.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:00:50.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:00:50.99#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:50.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:50.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:50.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:51.01#ibcon#[27=AT01-04\r\n] 2006.148.08:00:51.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:51.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:00:51.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:00:51.04#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:51.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:51.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:51.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:51.18#ibcon#[27=USB\r\n] 2006.148.08:00:51.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:51.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:00:51.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:00:51.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:00:51.21$vc4f8/vblo=2,640.99 2006.148.08:00:51.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:00:51.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:00:51.21#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:51.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:00:51.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:00:51.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:00:51.23#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:00:51.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:00:51.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:00:51.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:00:51.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:00:51.27$vc4f8/vb=2,4 2006.148.08:00:51.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.08:00:51.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.08:00:51.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:51.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:00:51.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:00:51.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:00:51.35#ibcon#[27=AT02-04\r\n] 2006.148.08:00:51.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:00:51.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:00:51.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.08:00:51.38#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:51.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:00:51.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:00:51.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:00:51.52#ibcon#[27=USB\r\n] 2006.148.08:00:51.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:00:51.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:00:51.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:00:51.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:00:51.55$vc4f8/vblo=3,656.99 2006.148.08:00:51.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:00:51.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:00:51.55#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:51.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:51.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:51.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:51.57#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:00:51.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:51.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:00:51.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:00:51.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:00:51.61$vc4f8/vb=3,4 2006.148.08:00:51.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.08:00:51.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.08:00:51.61#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:51.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:51.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:51.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:51.69#ibcon#[27=AT03-04\r\n] 2006.148.08:00:51.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:51.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:00:51.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.08:00:51.72#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:51.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:51.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:51.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:51.86#ibcon#[27=USB\r\n] 2006.148.08:00:51.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:51.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:00:51.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:00:51.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:00:51.89$vc4f8/vblo=4,712.99 2006.148.08:00:51.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.08:00:51.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.08:00:51.89#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:51.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:51.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:51.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:51.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:00:51.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:51.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:00:51.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:00:51.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:00:51.98$vc4f8/vb=4,4 2006.148.08:00:51.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.08:00:51.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.08:00:51.98#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:51.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:52.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:52.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:52.03#ibcon#[27=AT04-04\r\n] 2006.148.08:00:52.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:52.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:00:52.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.08:00:52.06#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:52.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:52.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:52.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:52.20#ibcon#[27=USB\r\n] 2006.148.08:00:52.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:52.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:00:52.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:00:52.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:00:52.23$vc4f8/vblo=5,744.99 2006.148.08:00:52.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:00:52.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:00:52.23#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:52.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:52.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:52.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:52.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:00:52.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:52.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:00:52.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:00:52.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:00:52.29$vc4f8/vb=5,3 2006.148.08:00:52.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:00:52.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:00:52.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:52.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:52.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:52.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:52.37#ibcon#[27=AT05-03\r\n] 2006.148.08:00:52.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:52.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:00:52.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:00:52.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:52.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:52.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:52.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:52.54#ibcon#[27=USB\r\n] 2006.148.08:00:52.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:52.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:00:52.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:00:52.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:00:52.57$vc4f8/vblo=6,752.99 2006.148.08:00:52.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:00:52.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:00:52.57#ibcon#ireg 17 cls_cnt 0 2006.148.08:00:52.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:52.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:52.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:52.59#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:00:52.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:52.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:00:52.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:00:52.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:00:52.63$vc4f8/vb=6,4 2006.148.08:00:52.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.08:00:52.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.08:00:52.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:00:52.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:52.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:52.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:52.71#ibcon#[27=AT06-04\r\n] 2006.148.08:00:52.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:52.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:00:52.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.08:00:52.74#ibcon#ireg 7 cls_cnt 0 2006.148.08:00:52.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:52.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:52.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:52.88#ibcon#[27=USB\r\n] 2006.148.08:00:52.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:52.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:00:52.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:00:52.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:00:52.91$vc4f8/vabw=wide 2006.148.08:00:52.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.08:00:52.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.08:00:52.91#ibcon#ireg 8 cls_cnt 0 2006.148.08:00:52.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:52.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:52.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:52.93#ibcon#[25=BW32\r\n] 2006.148.08:00:52.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:52.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:00:52.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:00:52.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:00:52.96$vc4f8/vbbw=wide 2006.148.08:00:52.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:00:52.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:00:52.96#ibcon#ireg 8 cls_cnt 0 2006.148.08:00:52.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:00:53.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:00:53.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:00:53.05#ibcon#[27=BW32\r\n] 2006.148.08:00:53.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:00:53.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:00:53.08#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:00:53.08#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:00:53.08$4f8m12a/ifd4f 2006.148.08:00:53.08$ifd4f/lo= 2006.148.08:00:53.08$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:00:53.08$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:00:53.08$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:00:53.08$ifd4f/patch= 2006.148.08:00:53.08$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:00:53.08$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:00:53.08$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:00:53.08$4f8m12a/"form=m,16.000,1:2 2006.148.08:00:53.08$4f8m12a/"tpicd 2006.148.08:00:53.08$4f8m12a/echo=off 2006.148.08:00:53.08$4f8m12a/xlog=off 2006.148.08:00:53.08:!2006.148.08:01:50 2006.148.08:01:30.14#trakl#Source acquired 2006.148.08:01:32.14#flagr#flagr/antenna,acquired 2006.148.08:01:50.00:preob 2006.148.08:01:51.14/onsource/TRACKING 2006.148.08:01:51.14:!2006.148.08:02:00 2006.148.08:02:00.00:data_valid=on 2006.148.08:02:00.00:midob 2006.148.08:02:00.14/onsource/TRACKING 2006.148.08:02:00.14/wx/22.01,994.2,93 2006.148.08:02:00.33/cable/+6.5331E-03 2006.148.08:02:01.42/va/01,08,usb,yes,32,34 2006.148.08:02:01.42/va/02,07,usb,yes,32,34 2006.148.08:02:01.42/va/03,08,usb,yes,24,24 2006.148.08:02:01.42/va/04,07,usb,yes,33,35 2006.148.08:02:01.42/va/05,06,usb,yes,36,38 2006.148.08:02:01.42/va/06,05,usb,yes,36,36 2006.148.08:02:01.42/va/07,05,usb,yes,36,36 2006.148.08:02:01.42/va/08,05,usb,yes,39,38 2006.148.08:02:01.65/valo/01,532.99,yes,locked 2006.148.08:02:01.65/valo/02,572.99,yes,locked 2006.148.08:02:01.65/valo/03,672.99,yes,locked 2006.148.08:02:01.65/valo/04,832.99,yes,locked 2006.148.08:02:01.65/valo/05,652.99,yes,locked 2006.148.08:02:01.65/valo/06,772.99,yes,locked 2006.148.08:02:01.65/valo/07,832.99,yes,locked 2006.148.08:02:01.65/valo/08,852.99,yes,locked 2006.148.08:02:02.74/vb/01,04,usb,yes,30,29 2006.148.08:02:02.74/vb/02,04,usb,yes,32,33 2006.148.08:02:02.74/vb/03,04,usb,yes,28,32 2006.148.08:02:02.74/vb/04,04,usb,yes,29,31 2006.148.08:02:02.74/vb/05,03,usb,yes,35,39 2006.148.08:02:02.74/vb/06,04,usb,yes,29,31 2006.148.08:02:02.74/vb/07,04,usb,yes,31,30 2006.148.08:02:02.74/vb/08,03,usb,yes,35,39 2006.148.08:02:02.97/vblo/01,632.99,yes,locked 2006.148.08:02:02.97/vblo/02,640.99,yes,locked 2006.148.08:02:02.97/vblo/03,656.99,yes,locked 2006.148.08:02:02.97/vblo/04,712.99,yes,locked 2006.148.08:02:02.97/vblo/05,744.99,yes,locked 2006.148.08:02:02.97/vblo/06,752.99,yes,locked 2006.148.08:02:02.97/vblo/07,734.99,yes,locked 2006.148.08:02:02.97/vblo/08,744.99,yes,locked 2006.148.08:02:03.12/vabw/8 2006.148.08:02:03.27/vbbw/8 2006.148.08:02:03.37/xfe/off,on,15.2 2006.148.08:02:03.76/ifatt/23,28,28,28 2006.148.08:02:04.07/fmout-gps/S +4.90E-07 2006.148.08:02:04.11:!2006.148.08:03:30 2006.148.08:03:30.01:data_valid=off 2006.148.08:03:30.02:postob 2006.148.08:03:30.12/cable/+6.5355E-03 2006.148.08:03:30.12/wx/22.00,994.3,93 2006.148.08:03:30.21/fmout-gps/S +4.90E-07 2006.148.08:03:30.22:scan_name=148-0805,k06148,60 2006.148.08:03:30.22:source=1418+546,141946.60,542314.8,2000.0,cw 2006.148.08:03:31.14#flagr#flagr/antenna,new-source 2006.148.08:03:31.15:checkk5 2006.148.08:03:31.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:03:31.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:03:32.29/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:03:32.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:03:33.10/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0802*_20??1480802??.k5 file! 2006.148.08:03:33.48/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0802*_20??1480802??.k5 file! 2006.148.08:03:33.86/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0802*_20??1480802??.k5 file! 2006.148.08:03:34.24/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0802*_20??1480802??.k5 file! 2006.148.08:03:34.94/k5log//k5ts1_log_newline 2006.148.08:03:35.64/k5log//k5ts2_log_newline 2006.148.08:03:36.34/k5log//k5ts3_log_newline 2006.148.08:03:37.03/k5log//k5ts4_log_newline 2006.148.08:03:37.19/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:03:37.19:4f8m12a=2 2006.148.08:03:37.19$4f8m12a/echo=on 2006.148.08:03:37.19$4f8m12a/pcalon 2006.148.08:03:37.19$pcalon/"no phase cal control is implemented here 2006.148.08:03:37.19$4f8m12a/"tpicd=stop 2006.148.08:03:37.19$4f8m12a/vc4f8 2006.148.08:03:37.19$vc4f8/valo=1,532.99 2006.148.08:03:37.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:03:37.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:03:37.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:37.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:37.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:37.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:37.22#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:03:37.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:37.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:37.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:03:37.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:03:37.27$vc4f8/va=1,8 2006.148.08:03:37.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:03:37.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:03:37.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:37.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:37.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:37.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:37.29#ibcon#[25=AT01-08\r\n] 2006.148.08:03:37.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:37.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:37.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:03:37.32#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:37.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:37.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:37.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:37.46#ibcon#[25=USB\r\n] 2006.148.08:03:37.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:37.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:37.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:03:37.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:03:37.49$vc4f8/valo=2,572.99 2006.148.08:03:37.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:03:37.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:03:37.49#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:37.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:37.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:37.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:37.53#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:03:37.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:37.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:37.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:03:37.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:03:37.57$vc4f8/va=2,7 2006.148.08:03:37.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:03:37.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:03:37.57#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:37.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:37.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:37.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:37.63#ibcon#[25=AT02-07\r\n] 2006.148.08:03:37.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:37.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:37.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:03:37.66#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:37.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:37.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:37.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:37.80#ibcon#[25=USB\r\n] 2006.148.08:03:37.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:37.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:37.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:03:37.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:03:37.83$vc4f8/valo=3,672.99 2006.148.08:03:37.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:03:37.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:03:37.83#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:37.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:37.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:37.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:37.87#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:03:37.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:37.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:37.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:03:37.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:03:37.91$vc4f8/va=3,8 2006.148.08:03:37.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:03:37.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:03:37.91#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:37.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:37.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:37.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:37.97#ibcon#[25=AT03-08\r\n] 2006.148.08:03:38.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:38.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:38.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:03:38.00#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:38.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:38.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:38.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:38.14#ibcon#[25=USB\r\n] 2006.148.08:03:38.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:38.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:38.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:03:38.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:03:38.17$vc4f8/valo=4,832.99 2006.148.08:03:38.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:03:38.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:03:38.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:38.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:38.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:38.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:38.19#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:03:38.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:38.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:38.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:03:38.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:03:38.23$vc4f8/va=4,7 2006.148.08:03:38.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:03:38.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:03:38.23#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:38.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:38.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:38.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:38.31#ibcon#[25=AT04-07\r\n] 2006.148.08:03:38.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:38.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:38.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:03:38.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:38.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:38.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:38.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:38.48#ibcon#[25=USB\r\n] 2006.148.08:03:38.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:38.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:38.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:03:38.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:03:38.51$vc4f8/valo=5,652.99 2006.148.08:03:38.51#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:03:38.51#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:03:38.51#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:38.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:03:38.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:03:38.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:03:38.53#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:03:38.57#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:03:38.57#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:03:38.57#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:03:38.57#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:03:38.57$vc4f8/va=5,6 2006.148.08:03:38.57#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:03:38.57#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:03:38.57#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:38.57#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:03:38.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:03:38.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:03:38.65#ibcon#[25=AT05-06\r\n] 2006.148.08:03:38.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:03:38.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:03:38.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:03:38.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:38.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:03:38.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:03:38.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:03:38.82#ibcon#[25=USB\r\n] 2006.148.08:03:38.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:03:38.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:03:38.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:03:38.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:03:38.85$vc4f8/valo=6,772.99 2006.148.08:03:38.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:03:38.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:03:38.85#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:38.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:38.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:38.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:38.87#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:03:38.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:38.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:38.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:03:38.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:03:38.91$vc4f8/va=6,5 2006.148.08:03:38.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:03:38.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:03:38.91#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:38.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:38.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:38.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:38.99#ibcon#[25=AT06-05\r\n] 2006.148.08:03:39.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:39.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:39.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:03:39.02#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:39.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:39.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:39.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:39.16#ibcon#[25=USB\r\n] 2006.148.08:03:39.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:39.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:39.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:03:39.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:03:39.19$vc4f8/valo=7,832.99 2006.148.08:03:39.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:03:39.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:03:39.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:39.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:39.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:39.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:39.21#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:03:39.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:39.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:39.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:03:39.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:03:39.25$vc4f8/va=7,5 2006.148.08:03:39.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.08:03:39.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.08:03:39.25#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:39.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:39.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:39.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:39.33#ibcon#[25=AT07-05\r\n] 2006.148.08:03:39.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:39.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:39.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.08:03:39.36#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:39.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:03:39.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:03:39.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:03:39.50#ibcon#[25=USB\r\n] 2006.148.08:03:39.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:03:39.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:03:39.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:03:39.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:03:39.53$vc4f8/valo=8,852.99 2006.148.08:03:39.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.08:03:39.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.08:03:39.53#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:39.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:03:39.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:03:39.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:03:39.55#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:03:39.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:03:39.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:03:39.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:03:39.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:03:39.59$vc4f8/va=8,5 2006.148.08:03:39.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.08:03:39.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.08:03:39.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:39.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:03:39.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:03:39.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:03:39.67#ibcon#[25=AT08-05\r\n] 2006.148.08:03:39.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:03:39.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:03:39.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.08:03:39.70#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:39.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:03:39.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:03:39.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:03:39.84#ibcon#[25=USB\r\n] 2006.148.08:03:39.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:03:39.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:03:39.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:03:39.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:03:39.87$vc4f8/vblo=1,632.99 2006.148.08:03:39.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.08:03:39.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.08:03:39.87#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:39.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:03:39.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:03:39.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:03:39.89#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:03:39.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:03:39.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:03:39.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:03:39.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:03:39.93$vc4f8/vb=1,4 2006.148.08:03:39.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.08:03:39.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.08:03:39.93#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:39.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:03:39.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:03:39.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:03:39.95#ibcon#[27=AT01-04\r\n] 2006.148.08:03:39.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:03:39.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:03:39.98#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.08:03:39.98#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:39.98#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:03:40.10#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:03:40.10#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:03:40.12#ibcon#[27=USB\r\n] 2006.148.08:03:40.15#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:03:40.15#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:03:40.15#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:03:40.15#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:03:40.15$vc4f8/vblo=2,640.99 2006.148.08:03:40.15#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:03:40.15#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:03:40.15#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:40.15#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:40.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:40.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:40.17#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:03:40.21#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:40.21#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:03:40.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:03:40.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:03:40.21$vc4f8/vb=2,4 2006.148.08:03:40.21#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:03:40.21#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:03:40.21#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:40.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:40.27#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:40.27#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:40.29#ibcon#[27=AT02-04\r\n] 2006.148.08:03:40.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:40.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:03:40.32#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:03:40.32#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:40.32#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:40.44#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:40.44#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:40.46#ibcon#[27=USB\r\n] 2006.148.08:03:40.49#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:40.49#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:03:40.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:03:40.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:03:40.49$vc4f8/vblo=3,656.99 2006.148.08:03:40.49#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:03:40.49#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:03:40.49#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:40.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:40.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:40.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:40.51#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:03:40.55#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:40.55#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:03:40.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:03:40.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:03:40.55$vc4f8/vb=3,4 2006.148.08:03:40.55#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:03:40.55#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:03:40.55#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:40.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:40.61#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:40.61#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:40.63#ibcon#[27=AT03-04\r\n] 2006.148.08:03:40.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:40.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:03:40.66#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:03:40.66#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:40.66#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:40.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:40.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:40.80#ibcon#[27=USB\r\n] 2006.148.08:03:40.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:40.83#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:03:40.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:03:40.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:03:40.83$vc4f8/vblo=4,712.99 2006.148.08:03:40.83#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:03:40.83#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:03:40.83#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:40.83#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:40.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:40.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:40.85#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:03:40.89#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:40.89#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:03:40.89#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:03:40.89#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:03:40.89$vc4f8/vb=4,4 2006.148.08:03:40.89#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:03:40.89#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:03:40.89#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:40.89#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:40.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:40.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:40.97#ibcon#[27=AT04-04\r\n] 2006.148.08:03:41.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:41.00#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:03:41.00#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:03:41.00#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:41.00#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:41.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:41.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:41.14#ibcon#[27=USB\r\n] 2006.148.08:03:41.17#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:41.17#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:03:41.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:03:41.17#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:03:41.17$vc4f8/vblo=5,744.99 2006.148.08:03:41.17#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:03:41.17#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:03:41.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:41.17#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:41.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:41.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:41.19#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:03:41.23#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:41.23#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:03:41.23#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:03:41.23#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:03:41.23$vc4f8/vb=5,3 2006.148.08:03:41.23#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:03:41.23#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:03:41.23#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:41.23#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:41.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:41.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:41.31#ibcon#[27=AT05-03\r\n] 2006.148.08:03:41.34#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:41.34#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:03:41.34#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:03:41.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:41.34#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:41.42#abcon#<5=/07 1.8 4.2 22.00 94 994.3\r\n> 2006.148.08:03:41.44#abcon#{5=INTERFACE CLEAR} 2006.148.08:03:41.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:41.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:41.48#ibcon#[27=USB\r\n] 2006.148.08:03:41.50#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:03:41.51#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:41.51#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:03:41.51#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:03:41.51#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:03:41.51$vc4f8/vblo=6,752.99 2006.148.08:03:41.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:03:41.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:03:41.51#ibcon#ireg 17 cls_cnt 0 2006.148.08:03:41.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:41.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:41.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:41.53#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:03:41.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:41.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:03:41.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:03:41.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:03:41.57$vc4f8/vb=6,4 2006.148.08:03:41.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:03:41.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:03:41.57#ibcon#ireg 11 cls_cnt 2 2006.148.08:03:41.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:41.63#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:41.63#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:41.65#ibcon#[27=AT06-04\r\n] 2006.148.08:03:41.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:41.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:03:41.68#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:03:41.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:03:41.68#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:41.80#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:41.80#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:41.82#ibcon#[27=USB\r\n] 2006.148.08:03:41.85#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:41.85#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:03:41.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:03:41.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:03:41.85$vc4f8/vabw=wide 2006.148.08:03:41.85#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:03:41.85#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:03:41.85#ibcon#ireg 8 cls_cnt 0 2006.148.08:03:41.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:41.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:41.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:41.87#ibcon#[25=BW32\r\n] 2006.148.08:03:41.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:41.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:03:41.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:03:41.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:03:41.90$vc4f8/vbbw=wide 2006.148.08:03:41.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.08:03:41.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.08:03:41.90#ibcon#ireg 8 cls_cnt 0 2006.148.08:03:41.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:03:41.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:03:41.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:03:41.99#ibcon#[27=BW32\r\n] 2006.148.08:03:42.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:03:42.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:03:42.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:03:42.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:03:42.02$4f8m12a/ifd4f 2006.148.08:03:42.02$ifd4f/lo= 2006.148.08:03:42.02$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:03:42.02$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:03:42.02$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:03:42.02$ifd4f/patch= 2006.148.08:03:42.02$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:03:42.02$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:03:42.02$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:03:42.02$4f8m12a/"form=m,16.000,1:2 2006.148.08:03:42.02$4f8m12a/"tpicd 2006.148.08:03:42.02$4f8m12a/echo=off 2006.148.08:03:42.02$4f8m12a/xlog=off 2006.148.08:03:42.02:!2006.148.08:04:50 2006.148.08:04:26.14#trakl#Source acquired 2006.148.08:04:27.14#flagr#flagr/antenna,acquired 2006.148.08:04:50.00:preob 2006.148.08:04:50.14/onsource/TRACKING 2006.148.08:04:50.14:!2006.148.08:05:00 2006.148.08:05:00.00:data_valid=on 2006.148.08:05:00.00:midob 2006.148.08:05:00.14/onsource/TRACKING 2006.148.08:05:00.14/wx/22.00,994.3,94 2006.148.08:05:00.32/cable/+6.5326E-03 2006.148.08:05:01.41/va/01,08,usb,yes,29,30 2006.148.08:05:01.41/va/02,07,usb,yes,29,30 2006.148.08:05:01.41/va/03,08,usb,yes,21,22 2006.148.08:05:01.41/va/04,07,usb,yes,30,32 2006.148.08:05:01.41/va/05,06,usb,yes,32,34 2006.148.08:05:01.41/va/06,05,usb,yes,33,32 2006.148.08:05:01.41/va/07,05,usb,yes,33,32 2006.148.08:05:01.41/va/08,05,usb,yes,35,35 2006.148.08:05:01.64/valo/01,532.99,yes,locked 2006.148.08:05:01.64/valo/02,572.99,yes,locked 2006.148.08:05:01.64/valo/03,672.99,yes,locked 2006.148.08:05:01.64/valo/04,832.99,yes,locked 2006.148.08:05:01.64/valo/05,652.99,yes,locked 2006.148.08:05:01.64/valo/06,772.99,yes,locked 2006.148.08:05:01.64/valo/07,832.99,yes,locked 2006.148.08:05:01.64/valo/08,852.99,yes,locked 2006.148.08:05:02.73/vb/01,04,usb,yes,29,27 2006.148.08:05:02.73/vb/02,04,usb,yes,31,32 2006.148.08:05:02.73/vb/03,04,usb,yes,27,30 2006.148.08:05:02.73/vb/04,04,usb,yes,27,29 2006.148.08:05:02.73/vb/05,03,usb,yes,33,37 2006.148.08:05:02.73/vb/06,04,usb,yes,27,30 2006.148.08:05:02.73/vb/07,04,usb,yes,29,29 2006.148.08:05:02.73/vb/08,03,usb,yes,33,37 2006.148.08:05:02.96/vblo/01,632.99,yes,locked 2006.148.08:05:02.96/vblo/02,640.99,yes,locked 2006.148.08:05:02.96/vblo/03,656.99,yes,locked 2006.148.08:05:02.96/vblo/04,712.99,yes,locked 2006.148.08:05:02.96/vblo/05,744.99,yes,locked 2006.148.08:05:02.96/vblo/06,752.99,yes,locked 2006.148.08:05:02.96/vblo/07,734.99,yes,locked 2006.148.08:05:02.96/vblo/08,744.99,yes,locked 2006.148.08:05:03.11/vabw/8 2006.148.08:05:03.26/vbbw/8 2006.148.08:05:03.39/xfe/off,on,14.7 2006.148.08:05:03.78/ifatt/23,28,28,28 2006.148.08:05:04.07/fmout-gps/S +4.90E-07 2006.148.08:05:04.11:!2006.148.08:06:00 2006.148.08:06:00.01:data_valid=off 2006.148.08:06:00.01:postob 2006.148.08:06:00.09/cable/+6.5336E-03 2006.148.08:06:00.10/wx/22.00,994.3,94 2006.148.08:06:00.18/fmout-gps/S +4.89E-07 2006.148.08:06:00.19:scan_name=148-0807,k06148,60 2006.148.08:06:00.19:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.148.08:06:01.13#flagr#flagr/antenna,new-source 2006.148.08:06:01.14:checkk5 2006.148.08:06:01.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:06:01.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:06:02.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:06:02.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:06:03.09/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0805*_20??1480805??.k5 file! 2006.148.08:06:03.47/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0805*_20??1480805??.k5 file! 2006.148.08:06:03.85/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0805*_20??1480805??.k5 file! 2006.148.08:06:04.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0805*_20??1480805??.k5 file! 2006.148.08:06:04.92/k5log//k5ts1_log_newline 2006.148.08:06:05.62/k5log//k5ts2_log_newline 2006.148.08:06:06.32/k5log//k5ts3_log_newline 2006.148.08:06:07.02/k5log//k5ts4_log_newline 2006.148.08:06:07.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:06:07.17:4f8m12a=2 2006.148.08:06:07.17$4f8m12a/echo=on 2006.148.08:06:07.17$4f8m12a/pcalon 2006.148.08:06:07.17$pcalon/"no phase cal control is implemented here 2006.148.08:06:07.17$4f8m12a/"tpicd=stop 2006.148.08:06:07.17$4f8m12a/vc4f8 2006.148.08:06:07.17$vc4f8/valo=1,532.99 2006.148.08:06:07.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:06:07.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:06:07.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:07.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:07.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:07.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:07.20#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:06:07.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:07.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:07.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:06:07.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:06:07.25$vc4f8/va=1,8 2006.148.08:06:07.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:06:07.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:06:07.25#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:07.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:07.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:07.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:07.27#ibcon#[25=AT01-08\r\n] 2006.148.08:06:07.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:07.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:07.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:06:07.30#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:07.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:07.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:07.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:07.44#ibcon#[25=USB\r\n] 2006.148.08:06:07.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:07.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:07.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:06:07.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:06:07.50$vc4f8/valo=2,572.99 2006.148.08:06:07.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:06:07.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:06:07.50#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:07.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:07.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:07.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:07.51#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:06:07.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:07.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:07.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:06:07.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:06:07.55$vc4f8/va=2,7 2006.148.08:06:07.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.08:06:07.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.08:06:07.55#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:07.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:07.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:07.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:07.63#ibcon#[25=AT02-07\r\n] 2006.148.08:06:07.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:07.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:07.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.08:06:07.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:07.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:07.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:07.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:07.82#ibcon#[25=USB\r\n] 2006.148.08:06:07.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:07.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:07.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:06:07.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:06:07.88$vc4f8/valo=3,672.99 2006.148.08:06:07.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:06:07.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:06:07.88#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:07.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:07.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:07.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:07.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:06:07.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:07.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:07.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:06:07.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:06:07.93$vc4f8/va=3,8 2006.148.08:06:07.93#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.08:06:07.93#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.08:06:07.93#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:07.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:07.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:07.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:08.01#ibcon#[25=AT03-08\r\n] 2006.148.08:06:08.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:08.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:08.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.08:06:08.04#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:08.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:08.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:08.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:08.18#ibcon#[25=USB\r\n] 2006.148.08:06:08.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:08.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:08.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:06:08.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:06:08.21$vc4f8/valo=4,832.99 2006.148.08:06:08.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.08:06:08.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.08:06:08.21#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:08.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:08.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:08.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:08.23#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:06:08.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:08.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:08.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:06:08.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:06:08.27$vc4f8/va=4,7 2006.148.08:06:08.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.08:06:08.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.08:06:08.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:08.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:08.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:08.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:08.35#ibcon#[25=AT04-07\r\n] 2006.148.08:06:08.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:08.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:08.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.08:06:08.38#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:08.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:08.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:08.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:08.52#ibcon#[25=USB\r\n] 2006.148.08:06:08.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:08.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:08.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:06:08.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:06:08.55$vc4f8/valo=5,652.99 2006.148.08:06:08.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.08:06:08.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.08:06:08.55#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:08.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:08.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:08.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:08.57#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:06:08.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:08.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:08.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:06:08.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:06:08.61$vc4f8/va=5,6 2006.148.08:06:08.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.08:06:08.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.08:06:08.61#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:08.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:08.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:08.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:08.69#ibcon#[25=AT05-06\r\n] 2006.148.08:06:08.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:08.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:08.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.08:06:08.72#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:08.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:08.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:08.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:08.86#ibcon#[25=USB\r\n] 2006.148.08:06:08.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:08.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:08.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:06:08.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:06:08.89$vc4f8/valo=6,772.99 2006.148.08:06:08.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.08:06:08.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.08:06:08.89#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:08.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:08.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:08.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:08.91#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:06:08.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:08.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:08.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:06:08.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:06:08.95$vc4f8/va=6,5 2006.148.08:06:08.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.08:06:08.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.08:06:08.95#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:08.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:09.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:09.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:09.03#ibcon#[25=AT06-05\r\n] 2006.148.08:06:09.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:09.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:09.06#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.08:06:09.06#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:09.06#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:06:09.18#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:06:09.18#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:06:09.20#ibcon#[25=USB\r\n] 2006.148.08:06:09.23#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:06:09.23#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:06:09.23#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:06:09.23#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:06:09.23$vc4f8/valo=7,832.99 2006.148.08:06:09.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:06:09.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:06:09.23#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:09.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:06:09.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:06:09.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:06:09.25#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:06:09.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:06:09.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:06:09.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:06:09.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:06:09.29$vc4f8/va=7,5 2006.148.08:06:09.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:06:09.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:06:09.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:09.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:06:09.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:06:09.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:06:09.37#ibcon#[25=AT07-05\r\n] 2006.148.08:06:09.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:06:09.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:06:09.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:06:09.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:09.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:06:09.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:06:09.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:06:09.54#ibcon#[25=USB\r\n] 2006.148.08:06:09.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:06:09.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:06:09.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:06:09.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:06:09.57$vc4f8/valo=8,852.99 2006.148.08:06:09.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:06:09.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:06:09.57#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:09.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:06:09.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:06:09.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:06:09.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:06:09.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:06:09.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:06:09.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:06:09.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:06:09.63$vc4f8/va=8,5 2006.148.08:06:09.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.08:06:09.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.08:06:09.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:09.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:06:09.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:06:09.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:06:09.71#ibcon#[25=AT08-05\r\n] 2006.148.08:06:09.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:06:09.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:06:09.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.08:06:09.74#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:09.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:06:09.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:06:09.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:06:09.88#ibcon#[25=USB\r\n] 2006.148.08:06:09.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:06:09.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:06:09.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:06:09.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:06:09.91$vc4f8/vblo=1,632.99 2006.148.08:06:09.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.08:06:09.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.08:06:09.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:09.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:06:09.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:06:09.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:06:09.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:06:09.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:06:09.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:06:09.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:06:09.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:06:09.97$vc4f8/vb=1,4 2006.148.08:06:09.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.08:06:09.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.08:06:09.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:09.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:06:09.97#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:06:09.97#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:06:09.99#ibcon#[27=AT01-04\r\n] 2006.148.08:06:10.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:06:10.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:06:10.02#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.08:06:10.02#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:10.02#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:06:10.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:06:10.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:06:10.16#ibcon#[27=USB\r\n] 2006.148.08:06:10.19#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:06:10.19#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:06:10.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:06:10.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:06:10.19$vc4f8/vblo=2,640.99 2006.148.08:06:10.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:06:10.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:06:10.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:10.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:10.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:10.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:10.21#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:06:10.27#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:10.27#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:06:10.27#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:06:10.27#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:06:10.27$vc4f8/vb=2,4 2006.148.08:06:10.27#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:06:10.27#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:06:10.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:10.27#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:10.31#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:10.31#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:10.33#ibcon#[27=AT02-04\r\n] 2006.148.08:06:10.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:10.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:06:10.36#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:06:10.36#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:10.36#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:10.48#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:10.48#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:10.50#ibcon#[27=USB\r\n] 2006.148.08:06:10.53#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:10.53#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:06:10.53#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:06:10.53#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:06:10.53$vc4f8/vblo=3,656.99 2006.148.08:06:10.53#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:06:10.53#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:06:10.53#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:10.53#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:10.53#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:10.53#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:10.55#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:06:10.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:10.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:06:10.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:06:10.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:06:10.59$vc4f8/vb=3,4 2006.148.08:06:10.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.08:06:10.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.08:06:10.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:10.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:10.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:10.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:10.67#ibcon#[27=AT03-04\r\n] 2006.148.08:06:10.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:10.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:06:10.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.08:06:10.70#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:10.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:10.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:10.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:10.84#ibcon#[27=USB\r\n] 2006.148.08:06:10.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:10.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:06:10.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:06:10.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:06:10.87$vc4f8/vblo=4,712.99 2006.148.08:06:10.87#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:06:10.87#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:06:10.87#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:10.87#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:10.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:10.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:10.89#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:06:10.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:10.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:06:10.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:06:10.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:06:10.95$vc4f8/vb=4,4 2006.148.08:06:10.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.08:06:10.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.08:06:10.95#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:10.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:10.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:10.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:11.01#ibcon#[27=AT04-04\r\n] 2006.148.08:06:11.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:11.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:06:11.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.08:06:11.04#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:11.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:11.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:11.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:11.18#ibcon#[27=USB\r\n] 2006.148.08:06:11.21#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:11.21#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:06:11.21#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:06:11.21#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:06:11.21$vc4f8/vblo=5,744.99 2006.148.08:06:11.21#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.08:06:11.21#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.08:06:11.21#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:11.21#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:11.21#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:11.21#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:11.23#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:06:11.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:11.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:06:11.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:06:11.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:06:11.27$vc4f8/vb=5,3 2006.148.08:06:11.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.08:06:11.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.08:06:11.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:11.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:11.33#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:11.33#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:11.35#ibcon#[27=AT05-03\r\n] 2006.148.08:06:11.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:11.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:06:11.38#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.08:06:11.38#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:11.38#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:11.50#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:11.50#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:11.52#ibcon#[27=USB\r\n] 2006.148.08:06:11.55#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:11.55#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:06:11.55#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:06:11.55#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:06:11.55$vc4f8/vblo=6,752.99 2006.148.08:06:11.55#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.08:06:11.55#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.08:06:11.55#ibcon#ireg 17 cls_cnt 0 2006.148.08:06:11.55#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:11.55#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:11.55#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:11.57#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:06:11.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:11.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:06:11.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:06:11.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:06:11.63$vc4f8/vb=6,4 2006.148.08:06:11.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.08:06:11.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.08:06:11.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:06:11.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:11.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:11.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:11.69#ibcon#[27=AT06-04\r\n] 2006.148.08:06:11.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:11.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:06:11.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.08:06:11.72#ibcon#ireg 7 cls_cnt 0 2006.148.08:06:11.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:11.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:11.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:11.86#ibcon#[27=USB\r\n] 2006.148.08:06:11.89#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:11.89#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:06:11.89#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:06:11.89#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:06:11.89$vc4f8/vabw=wide 2006.148.08:06:11.89#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.08:06:11.89#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.08:06:11.89#ibcon#ireg 8 cls_cnt 0 2006.148.08:06:11.89#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:11.89#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:11.89#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:11.91#ibcon#[25=BW32\r\n] 2006.148.08:06:11.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:11.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:06:11.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:06:11.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:06:11.94$vc4f8/vbbw=wide 2006.148.08:06:11.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:06:11.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:06:11.94#ibcon#ireg 8 cls_cnt 0 2006.148.08:06:11.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:06:12.01#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:06:12.01#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:06:12.03#ibcon#[27=BW32\r\n] 2006.148.08:06:12.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:06:12.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:06:12.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:06:12.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:06:12.06$4f8m12a/ifd4f 2006.148.08:06:12.06$ifd4f/lo= 2006.148.08:06:12.06$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:06:12.06$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:06:12.06$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:06:12.06$ifd4f/patch= 2006.148.08:06:12.06$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:06:12.06$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:06:12.06$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:06:12.06$4f8m12a/"form=m,16.000,1:2 2006.148.08:06:12.06$4f8m12a/"tpicd 2006.148.08:06:12.06$4f8m12a/echo=off 2006.148.08:06:12.06$4f8m12a/xlog=off 2006.148.08:06:12.06:!2006.148.08:07:00 2006.148.08:06:33.13#trakl#Source acquired 2006.148.08:06:33.13#flagr#flagr/antenna,acquired 2006.148.08:07:00.00:preob 2006.148.08:07:01.13/onsource/TRACKING 2006.148.08:07:01.13:!2006.148.08:07:10 2006.148.08:07:10.00:data_valid=on 2006.148.08:07:10.00:midob 2006.148.08:07:10.13/onsource/TRACKING 2006.148.08:07:10.13/wx/22.00,994.4,94 2006.148.08:07:10.28/cable/+6.5391E-03 2006.148.08:07:11.37/va/01,08,usb,yes,33,35 2006.148.08:07:11.37/va/02,07,usb,yes,33,35 2006.148.08:07:11.37/va/03,08,usb,yes,25,25 2006.148.08:07:11.37/va/04,07,usb,yes,34,36 2006.148.08:07:11.37/va/05,06,usb,yes,37,39 2006.148.08:07:11.37/va/06,05,usb,yes,37,37 2006.148.08:07:11.37/va/07,05,usb,yes,37,37 2006.148.08:07:11.37/va/08,05,usb,yes,40,39 2006.148.08:07:11.60/valo/01,532.99,yes,locked 2006.148.08:07:11.60/valo/02,572.99,yes,locked 2006.148.08:07:11.60/valo/03,672.99,yes,locked 2006.148.08:07:11.60/valo/04,832.99,yes,locked 2006.148.08:07:11.60/valo/05,652.99,yes,locked 2006.148.08:07:11.60/valo/06,772.99,yes,locked 2006.148.08:07:11.60/valo/07,832.99,yes,locked 2006.148.08:07:11.60/valo/08,852.99,yes,locked 2006.148.08:07:12.69/vb/01,04,usb,yes,31,30 2006.148.08:07:12.69/vb/02,04,usb,yes,33,35 2006.148.08:07:12.69/vb/03,04,usb,yes,29,33 2006.148.08:07:12.69/vb/04,04,usb,yes,30,31 2006.148.08:07:12.69/vb/05,03,usb,yes,36,41 2006.148.08:07:12.69/vb/06,04,usb,yes,30,33 2006.148.08:07:12.69/vb/07,04,usb,yes,32,32 2006.148.08:07:12.69/vb/08,03,usb,yes,37,41 2006.148.08:07:12.93/vblo/01,632.99,yes,locked 2006.148.08:07:12.93/vblo/02,640.99,yes,locked 2006.148.08:07:12.93/vblo/03,656.99,yes,locked 2006.148.08:07:12.93/vblo/04,712.99,yes,locked 2006.148.08:07:12.93/vblo/05,744.99,yes,locked 2006.148.08:07:12.93/vblo/06,752.99,yes,locked 2006.148.08:07:12.93/vblo/07,734.99,yes,locked 2006.148.08:07:12.93/vblo/08,744.99,yes,locked 2006.148.08:07:13.08/vabw/8 2006.148.08:07:13.23/vbbw/8 2006.148.08:07:13.32/xfe/off,on,15.2 2006.148.08:07:13.71/ifatt/23,28,28,28 2006.148.08:07:14.07/fmout-gps/S +4.89E-07 2006.148.08:07:14.15:!2006.148.08:08:10 2006.148.08:08:10.01:data_valid=off 2006.148.08:08:10.01:postob 2006.148.08:08:10.14/cable/+6.5329E-03 2006.148.08:08:10.14/wx/22.00,994.4,94 2006.148.08:08:10.23/fmout-gps/S +4.88E-07 2006.148.08:08:10.24:scan_name=148-0809,k06148,60 2006.148.08:08:10.24:source=1803+784,180045.68,782804.0,2000.0,cw 2006.148.08:08:11.13#flagr#flagr/antenna,new-source 2006.148.08:08:11.14:checkk5 2006.148.08:08:11.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:08:11.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:08:12.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:08:12.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:08:13.04/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0807*_20??1480807??.k5 file! 2006.148.08:08:13.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0807*_20??1480807??.k5 file! 2006.148.08:08:13.80/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0807*_20??1480807??.k5 file! 2006.148.08:08:14.22/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0807*_20??1480807??.k5 file! 2006.148.08:08:14.91/k5log//k5ts1_log_newline 2006.148.08:08:15.60/k5log//k5ts2_log_newline 2006.148.08:08:16.30/k5log//k5ts3_log_newline 2006.148.08:08:17.00/k5log//k5ts4_log_newline 2006.148.08:08:17.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:08:17.16:4f8m12a=2 2006.148.08:08:17.16$4f8m12a/echo=on 2006.148.08:08:17.16$4f8m12a/pcalon 2006.148.08:08:17.16$pcalon/"no phase cal control is implemented here 2006.148.08:08:17.16$4f8m12a/"tpicd=stop 2006.148.08:08:17.16$4f8m12a/vc4f8 2006.148.08:08:17.16$vc4f8/valo=1,532.99 2006.148.08:08:17.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:08:17.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:08:17.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:17.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:17.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:17.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:17.22#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:08:17.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:17.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:17.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:08:17.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:08:17.26$vc4f8/va=1,8 2006.148.08:08:17.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.08:08:17.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.08:08:17.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:17.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:17.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:17.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:17.30#ibcon#[25=AT01-08\r\n] 2006.148.08:08:17.33#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:17.33#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:17.33#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.08:08:17.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:17.33#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:17.45#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:17.45#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:17.47#ibcon#[25=USB\r\n] 2006.148.08:08:17.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:17.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:17.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:08:17.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:08:17.52$vc4f8/valo=2,572.99 2006.148.08:08:17.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:08:17.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:08:17.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:17.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:17.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:17.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:17.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:08:17.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:17.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:17.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:08:17.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:08:17.58$vc4f8/va=2,7 2006.148.08:08:17.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.08:08:17.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.08:08:17.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:17.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:17.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:17.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:17.66#ibcon#[25=AT02-07\r\n] 2006.148.08:08:17.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:17.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:17.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.08:08:17.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:17.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:17.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:17.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:17.85#ibcon#[25=USB\r\n] 2006.148.08:08:17.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:17.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:17.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:08:17.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:08:17.90$vc4f8/valo=3,672.99 2006.148.08:08:17.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.08:08:17.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.08:08:17.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:17.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:17.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:17.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:17.92#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:08:17.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:17.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:17.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:08:17.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:08:17.96$vc4f8/va=3,8 2006.148.08:08:17.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.08:08:17.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.08:08:17.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:17.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:18.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:18.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:18.04#ibcon#[25=AT03-08\r\n] 2006.148.08:08:18.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:18.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:18.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.08:08:18.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:18.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:18.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:18.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:18.21#ibcon#[25=USB\r\n] 2006.148.08:08:18.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:18.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:18.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:08:18.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:08:18.24$vc4f8/valo=4,832.99 2006.148.08:08:18.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:08:18.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:08:18.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:18.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:18.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:18.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:18.26#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:08:18.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:18.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:18.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:08:18.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:08:18.30$vc4f8/va=4,7 2006.148.08:08:18.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.08:08:18.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.08:08:18.30#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:18.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:18.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:18.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:18.38#ibcon#[25=AT04-07\r\n] 2006.148.08:08:18.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:18.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:18.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.08:08:18.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:18.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:18.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:18.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:18.55#ibcon#[25=USB\r\n] 2006.148.08:08:18.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:18.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:18.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:08:18.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:08:18.58$vc4f8/valo=5,652.99 2006.148.08:08:18.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:08:18.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:08:18.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:18.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:18.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:18.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:18.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:08:18.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:18.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:18.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:08:18.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:08:18.64$vc4f8/va=5,6 2006.148.08:08:18.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.08:08:18.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.08:08:18.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:18.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:18.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:18.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:18.72#ibcon#[25=AT05-06\r\n] 2006.148.08:08:18.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:18.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:18.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.08:08:18.75#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:18.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:18.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:18.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:18.89#ibcon#[25=USB\r\n] 2006.148.08:08:18.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:18.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:18.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:08:18.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:08:18.92$vc4f8/valo=6,772.99 2006.148.08:08:18.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.08:08:18.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.08:08:18.92#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:18.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:18.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:18.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:18.94#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:08:18.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:18.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:18.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:08:18.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:08:18.98$vc4f8/va=6,5 2006.148.08:08:18.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.08:08:18.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.08:08:18.98#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:18.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:19.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:19.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:19.06#ibcon#[25=AT06-05\r\n] 2006.148.08:08:19.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:19.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:19.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.08:08:19.09#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:19.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:08:19.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:08:19.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:08:19.23#ibcon#[25=USB\r\n] 2006.148.08:08:19.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:08:19.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:08:19.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:08:19.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:08:19.26$vc4f8/valo=7,832.99 2006.148.08:08:19.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.08:08:19.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.08:08:19.26#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:19.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:08:19.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:08:19.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:08:19.28#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:08:19.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:08:19.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:08:19.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:08:19.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:08:19.32$vc4f8/va=7,5 2006.148.08:08:19.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.08:08:19.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.08:08:19.32#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:19.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:08:19.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:08:19.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:08:19.40#ibcon#[25=AT07-05\r\n] 2006.148.08:08:19.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:08:19.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:08:19.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.08:08:19.43#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:19.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:08:19.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:08:19.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:08:19.57#ibcon#[25=USB\r\n] 2006.148.08:08:19.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:08:19.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:08:19.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:08:19.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:08:19.60$vc4f8/valo=8,852.99 2006.148.08:08:19.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.08:08:19.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.08:08:19.60#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:19.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:08:19.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:08:19.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:08:19.62#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:08:19.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:08:19.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:08:19.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:08:19.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:08:19.66$vc4f8/va=8,5 2006.148.08:08:19.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.08:08:19.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.08:08:19.66#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:19.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:08:19.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:08:19.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:08:19.74#ibcon#[25=AT08-05\r\n] 2006.148.08:08:19.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:08:19.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:08:19.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.08:08:19.77#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:19.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:08:19.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:08:19.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:08:19.91#ibcon#[25=USB\r\n] 2006.148.08:08:19.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:08:19.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:08:19.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:08:19.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:08:19.94$vc4f8/vblo=1,632.99 2006.148.08:08:19.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.08:08:19.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.08:08:19.94#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:19.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:08:19.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:08:19.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:08:19.96#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:08:20.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:08:20.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:08:20.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:08:20.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:08:20.00$vc4f8/vb=1,4 2006.148.08:08:20.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.08:08:20.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.08:08:20.00#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:20.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:08:20.00#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:08:20.00#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:08:20.02#ibcon#[27=AT01-04\r\n] 2006.148.08:08:20.05#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:08:20.05#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:08:20.05#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.08:08:20.05#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:20.05#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:08:20.17#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:08:20.17#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:08:20.19#ibcon#[27=USB\r\n] 2006.148.08:08:20.24#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:08:20.24#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:08:20.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:08:20.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:08:20.24$vc4f8/vblo=2,640.99 2006.148.08:08:20.24#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:08:20.24#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:08:20.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:20.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:20.24#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:20.24#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:20.26#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:08:20.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:20.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:08:20.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:08:20.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:08:20.30$vc4f8/vb=2,4 2006.148.08:08:20.30#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.08:08:20.30#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.08:08:20.30#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:20.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:20.36#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:20.36#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:20.38#ibcon#[27=AT02-04\r\n] 2006.148.08:08:20.41#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:20.41#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:08:20.41#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.08:08:20.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:20.41#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:20.53#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:20.53#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:20.55#ibcon#[27=USB\r\n] 2006.148.08:08:20.58#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:20.58#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:08:20.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:08:20.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:08:20.58$vc4f8/vblo=3,656.99 2006.148.08:08:20.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:08:20.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:08:20.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:20.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:20.58#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:20.58#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:20.60#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:08:20.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:20.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:08:20.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:08:20.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:08:20.64$vc4f8/vb=3,4 2006.148.08:08:20.64#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.08:08:20.64#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.08:08:20.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:20.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:20.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:20.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:20.72#ibcon#[27=AT03-04\r\n] 2006.148.08:08:20.75#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:20.75#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:08:20.75#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.08:08:20.75#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:20.75#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:20.87#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:20.87#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:20.89#ibcon#[27=USB\r\n] 2006.148.08:08:20.92#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:20.92#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:08:20.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:08:20.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:08:20.92$vc4f8/vblo=4,712.99 2006.148.08:08:20.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.08:08:20.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.08:08:20.92#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:20.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:20.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:20.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:20.94#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:08:20.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:20.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:08:20.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:08:20.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:08:20.98$vc4f8/vb=4,4 2006.148.08:08:20.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.08:08:20.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.08:08:20.98#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:20.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:21.04#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:21.04#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:21.06#ibcon#[27=AT04-04\r\n] 2006.148.08:08:21.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:21.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:08:21.09#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.08:08:21.09#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:21.09#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:21.21#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:21.21#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:21.23#ibcon#[27=USB\r\n] 2006.148.08:08:21.26#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:21.26#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:08:21.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:08:21.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:08:21.26$vc4f8/vblo=5,744.99 2006.148.08:08:21.26#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:08:21.26#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:08:21.26#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:21.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:21.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:21.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:21.28#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:08:21.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:21.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:08:21.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:08:21.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:08:21.32$vc4f8/vb=5,3 2006.148.08:08:21.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.08:08:21.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.08:08:21.32#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:21.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:21.38#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:21.38#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:21.40#ibcon#[27=AT05-03\r\n] 2006.148.08:08:21.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:21.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:08:21.43#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.08:08:21.43#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:21.43#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:21.55#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:21.55#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:21.57#ibcon#[27=USB\r\n] 2006.148.08:08:21.60#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:21.60#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:08:21.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:08:21.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:08:21.60$vc4f8/vblo=6,752.99 2006.148.08:08:21.60#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:08:21.60#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:08:21.60#ibcon#ireg 17 cls_cnt 0 2006.148.08:08:21.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:21.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:21.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:21.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:08:21.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:21.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:08:21.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:08:21.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:08:21.68$vc4f8/vb=6,4 2006.148.08:08:21.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.08:08:21.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.08:08:21.68#ibcon#ireg 11 cls_cnt 2 2006.148.08:08:21.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:21.72#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:21.72#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:21.74#ibcon#[27=AT06-04\r\n] 2006.148.08:08:21.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:21.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:08:21.77#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.08:08:21.77#ibcon#ireg 7 cls_cnt 0 2006.148.08:08:21.77#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:21.89#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:21.89#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:21.91#ibcon#[27=USB\r\n] 2006.148.08:08:21.94#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:21.94#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:08:21.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:08:21.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:08:21.94$vc4f8/vabw=wide 2006.148.08:08:21.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.08:08:21.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.08:08:21.94#ibcon#ireg 8 cls_cnt 0 2006.148.08:08:21.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:21.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:21.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:21.96#ibcon#[25=BW32\r\n] 2006.148.08:08:21.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:21.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:08:21.99#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:08:21.99#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:08:21.99$vc4f8/vbbw=wide 2006.148.08:08:21.99#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:08:21.99#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:08:21.99#ibcon#ireg 8 cls_cnt 0 2006.148.08:08:21.99#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:08:22.06#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:08:22.06#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:08:22.08#ibcon#[27=BW32\r\n] 2006.148.08:08:22.11#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:08:22.11#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:08:22.11#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:08:22.11#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:08:22.11$4f8m12a/ifd4f 2006.148.08:08:22.11$ifd4f/lo= 2006.148.08:08:22.11$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:08:22.11$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:08:22.11$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:08:22.11$ifd4f/patch= 2006.148.08:08:22.11$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:08:22.11$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:08:22.11$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:08:22.11$4f8m12a/"form=m,16.000,1:2 2006.148.08:08:22.11$4f8m12a/"tpicd 2006.148.08:08:22.11$4f8m12a/echo=off 2006.148.08:08:22.11$4f8m12a/xlog=off 2006.148.08:08:22.11:!2006.148.08:08:50 2006.148.08:08:33.14#trakl#Source acquired 2006.148.08:08:34.14#flagr#flagr/antenna,acquired 2006.148.08:08:50.00:preob 2006.148.08:08:50.14/onsource/TRACKING 2006.148.08:08:50.14:!2006.148.08:09:00 2006.148.08:09:00.00:data_valid=on 2006.148.08:09:00.00:midob 2006.148.08:09:01.14/onsource/TRACKING 2006.148.08:09:01.14/wx/22.01,994.4,94 2006.148.08:09:01.32/cable/+6.5328E-03 2006.148.08:09:02.41/va/01,08,usb,yes,30,31 2006.148.08:09:02.41/va/02,07,usb,yes,30,31 2006.148.08:09:02.41/va/03,08,usb,yes,22,23 2006.148.08:09:02.41/va/04,07,usb,yes,30,33 2006.148.08:09:02.41/va/05,06,usb,yes,33,35 2006.148.08:09:02.41/va/06,05,usb,yes,33,33 2006.148.08:09:02.41/va/07,05,usb,yes,33,33 2006.148.08:09:02.41/va/08,05,usb,yes,36,35 2006.148.08:09:02.64/valo/01,532.99,yes,locked 2006.148.08:09:02.64/valo/02,572.99,yes,locked 2006.148.08:09:02.64/valo/03,672.99,yes,locked 2006.148.08:09:02.64/valo/04,832.99,yes,locked 2006.148.08:09:02.64/valo/05,652.99,yes,locked 2006.148.08:09:02.64/valo/06,772.99,yes,locked 2006.148.08:09:02.64/valo/07,832.99,yes,locked 2006.148.08:09:02.64/valo/08,852.99,yes,locked 2006.148.08:09:03.73/vb/01,04,usb,yes,29,28 2006.148.08:09:03.73/vb/02,04,usb,yes,31,32 2006.148.08:09:03.73/vb/03,04,usb,yes,27,31 2006.148.08:09:03.73/vb/04,04,usb,yes,28,31 2006.148.08:09:03.73/vb/05,03,usb,yes,34,38 2006.148.08:09:03.73/vb/06,04,usb,yes,28,31 2006.148.08:09:03.73/vb/07,04,usb,yes,30,30 2006.148.08:09:03.73/vb/08,03,usb,yes,34,38 2006.148.08:09:03.97/vblo/01,632.99,yes,locked 2006.148.08:09:03.97/vblo/02,640.99,yes,locked 2006.148.08:09:03.97/vblo/03,656.99,yes,locked 2006.148.08:09:03.97/vblo/04,712.99,yes,locked 2006.148.08:09:03.97/vblo/05,744.99,yes,locked 2006.148.08:09:03.97/vblo/06,752.99,yes,locked 2006.148.08:09:03.97/vblo/07,734.99,yes,locked 2006.148.08:09:03.97/vblo/08,744.99,yes,locked 2006.148.08:09:04.12/vabw/8 2006.148.08:09:04.27/vbbw/8 2006.148.08:09:04.36/xfe/off,on,15.2 2006.148.08:09:04.75/ifatt/23,28,28,28 2006.148.08:09:05.08/fmout-gps/S +4.89E-07 2006.148.08:09:05.12:!2006.148.08:10:00 2006.148.08:10:00.00:data_valid=off 2006.148.08:10:00.00:postob 2006.148.08:10:00.08/cable/+6.5328E-03 2006.148.08:10:00.08/wx/22.01,994.4,94 2006.148.08:10:01.08/fmout-gps/S +4.88E-07 2006.148.08:10:01.08:scan_name=148-0810,k06148,60 2006.148.08:10:01.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.148.08:10:01.14#flagr#flagr/antenna,new-source 2006.148.08:10:02.14:checkk5 2006.148.08:10:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:10:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:10:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:10:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:10:04.05/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0809*_20??1480809??.k5 file! 2006.148.08:10:04.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0809*_20??1480809??.k5 file! 2006.148.08:10:04.80/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0809*_20??1480809??.k5 file! 2006.148.08:10:05.22/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0809*_20??1480809??.k5 file! 2006.148.08:10:05.92/k5log//k5ts1_log_newline 2006.148.08:10:06.61/k5log//k5ts2_log_newline 2006.148.08:10:07.31/k5log//k5ts3_log_newline 2006.148.08:10:08.01/k5log//k5ts4_log_newline 2006.148.08:10:08.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:10:08.17:4f8m12a=2 2006.148.08:10:08.17$4f8m12a/echo=on 2006.148.08:10:08.17$4f8m12a/pcalon 2006.148.08:10:08.17$pcalon/"no phase cal control is implemented here 2006.148.08:10:08.17$4f8m12a/"tpicd=stop 2006.148.08:10:08.17$4f8m12a/vc4f8 2006.148.08:10:08.17$vc4f8/valo=1,532.99 2006.148.08:10:08.17#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:10:08.17#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:10:08.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:08.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:08.17#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:08.17#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:08.22#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:10:08.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:08.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:08.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:10:08.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:10:08.26$vc4f8/va=1,8 2006.148.08:10:08.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:10:08.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:10:08.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:08.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:08.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:08.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:08.30#ibcon#[25=AT01-08\r\n] 2006.148.08:10:08.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:08.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:08.33#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:10:08.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:08.33#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:08.45#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:08.45#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:08.47#ibcon#[25=USB\r\n] 2006.148.08:10:08.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:08.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:08.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:10:08.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:10:08.52$vc4f8/valo=2,572.99 2006.148.08:10:08.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:10:08.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:10:08.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:08.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:08.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:08.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:08.54#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:10:08.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:08.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:08.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:10:08.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:10:08.58$vc4f8/va=2,7 2006.148.08:10:08.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.08:10:08.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.08:10:08.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:08.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:08.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:08.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:08.66#ibcon#[25=AT02-07\r\n] 2006.148.08:10:08.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:08.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:08.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.08:10:08.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:08.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:08.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:08.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:08.85#ibcon#[25=USB\r\n] 2006.148.08:10:08.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:08.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:08.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:10:08.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:10:08.88$vc4f8/valo=3,672.99 2006.148.08:10:08.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:10:08.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:10:08.88#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:08.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:08.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:08.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:08.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:10:08.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:08.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:08.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:10:08.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:10:08.94$vc4f8/va=3,8 2006.148.08:10:08.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.08:10:08.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.08:10:08.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:08.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:09.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:09.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:09.02#ibcon#[25=AT03-08\r\n] 2006.148.08:10:09.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:09.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:09.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.08:10:09.05#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:09.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:09.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:09.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:09.19#ibcon#[25=USB\r\n] 2006.148.08:10:09.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:09.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:09.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:10:09.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:10:09.22$vc4f8/valo=4,832.99 2006.148.08:10:09.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.08:10:09.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.08:10:09.22#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:09.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:09.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:09.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:09.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:10:09.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:09.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:09.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:10:09.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:10:09.28$vc4f8/va=4,7 2006.148.08:10:09.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.08:10:09.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.08:10:09.28#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:09.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:09.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:09.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:09.36#ibcon#[25=AT04-07\r\n] 2006.148.08:10:09.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:09.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:09.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.08:10:09.39#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:09.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:09.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:09.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:09.53#ibcon#[25=USB\r\n] 2006.148.08:10:09.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:09.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:09.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:10:09.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:10:09.56$vc4f8/valo=5,652.99 2006.148.08:10:09.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:10:09.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:10:09.56#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:09.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:09.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:09.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:09.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:10:09.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:09.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:09.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:10:09.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:10:09.64$vc4f8/va=5,6 2006.148.08:10:09.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:10:09.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:10:09.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:09.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:09.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:09.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:09.70#ibcon#[25=AT05-06\r\n] 2006.148.08:10:09.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:09.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:09.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:10:09.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:09.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:09.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:09.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:09.87#ibcon#[25=USB\r\n] 2006.148.08:10:09.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:09.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:09.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:10:09.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:10:09.90$vc4f8/valo=6,772.99 2006.148.08:10:09.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:10:09.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:10:09.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:09.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:09.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:09.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:09.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:10:09.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:09.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:09.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:10:09.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:10:09.96$vc4f8/va=6,5 2006.148.08:10:09.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.08:10:09.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.08:10:09.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:09.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:10.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:10.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:10.04#ibcon#[25=AT06-05\r\n] 2006.148.08:10:10.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:10.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:10.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.08:10:10.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:10.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:10:10.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:10:10.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:10:10.21#ibcon#[25=USB\r\n] 2006.148.08:10:10.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:10:10.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:10:10.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:10:10.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:10:10.24$vc4f8/valo=7,832.99 2006.148.08:10:10.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.08:10:10.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.08:10:10.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:10.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:10:10.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:10:10.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:10:10.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:10:10.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:10:10.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:10:10.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:10:10.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:10:10.32$vc4f8/va=7,5 2006.148.08:10:10.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.08:10:10.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.08:10:10.32#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:10.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:10:10.35#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:10:10.35#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:10:10.37#ibcon#[25=AT07-05\r\n] 2006.148.08:10:10.40#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:10:10.40#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:10:10.40#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.08:10:10.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:10.40#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:10:10.52#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:10:10.52#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:10:10.54#ibcon#[25=USB\r\n] 2006.148.08:10:10.57#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:10:10.57#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:10:10.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:10:10.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:10:10.57$vc4f8/valo=8,852.99 2006.148.08:10:10.57#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.08:10:10.57#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.08:10:10.57#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:10.57#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:10:10.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:10:10.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:10:10.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:10:10.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:10:10.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:10:10.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:10:10.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:10:10.63$vc4f8/va=8,5 2006.148.08:10:10.63#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.08:10:10.63#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.08:10:10.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:10.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:10:10.69#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:10:10.69#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:10:10.71#ibcon#[25=AT08-05\r\n] 2006.148.08:10:10.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:10:10.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:10:10.74#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.08:10:10.74#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:10.74#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:10:10.86#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:10:10.86#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:10:10.88#ibcon#[25=USB\r\n] 2006.148.08:10:10.91#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:10:10.91#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:10:10.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:10:10.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:10:10.91$vc4f8/vblo=1,632.99 2006.148.08:10:10.91#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.08:10:10.91#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.08:10:10.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:10.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:10:10.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:10:10.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:10:10.93#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:10:10.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:10:10.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:10:10.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:10:10.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:10:10.97$vc4f8/vb=1,4 2006.148.08:10:10.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.08:10:10.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.08:10:10.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:10.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:10:10.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:10:10.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:10:11.00#ibcon#[27=AT01-04\r\n] 2006.148.08:10:11.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:10:11.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:10:11.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.08:10:11.03#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:11.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:10:11.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:10:11.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:10:11.17#ibcon#[27=USB\r\n] 2006.148.08:10:11.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:10:11.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:10:11.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:10:11.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:10:11.20$vc4f8/vblo=2,640.99 2006.148.08:10:11.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:10:11.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:10:11.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:11.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:11.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:11.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:11.22#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:10:11.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:11.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:10:11.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:10:11.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:10:11.26$vc4f8/vb=2,4 2006.148.08:10:11.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:10:11.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:10:11.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:11.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:11.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:11.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:11.34#ibcon#[27=AT02-04\r\n] 2006.148.08:10:11.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:11.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:10:11.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:10:11.37#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:11.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:11.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:11.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:11.51#ibcon#[27=USB\r\n] 2006.148.08:10:11.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:11.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:10:11.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:10:11.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:10:11.54$vc4f8/vblo=3,656.99 2006.148.08:10:11.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:10:11.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:10:11.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:11.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:11.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:11.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:11.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:10:11.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:11.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:10:11.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:10:11.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:10:11.60$vc4f8/vb=3,4 2006.148.08:10:11.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.08:10:11.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.08:10:11.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:11.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:11.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:11.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:11.70#ibcon#[27=AT03-04\r\n] 2006.148.08:10:11.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:11.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:10:11.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.08:10:11.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:11.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:11.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:11.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:11.87#ibcon#[27=USB\r\n] 2006.148.08:10:11.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:11.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:10:11.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:10:11.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:10:11.90$vc4f8/vblo=4,712.99 2006.148.08:10:11.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:10:11.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:10:11.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:11.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:11.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:11.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:11.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:10:11.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:11.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:10:11.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:10:11.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:10:11.96$vc4f8/vb=4,4 2006.148.08:10:11.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.08:10:11.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.08:10:11.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:11.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:12.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:12.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:12.04#ibcon#[27=AT04-04\r\n] 2006.148.08:10:12.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:12.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:10:12.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.08:10:12.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:12.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:12.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:12.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:12.21#ibcon#[27=USB\r\n] 2006.148.08:10:12.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:12.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:10:12.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:10:12.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:10:12.24$vc4f8/vblo=5,744.99 2006.148.08:10:12.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.148.08:10:12.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.148.08:10:12.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:12.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:12.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:12.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:12.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:10:12.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:12.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.148.08:10:12.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:10:12.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:10:12.30$vc4f8/vb=5,3 2006.148.08:10:12.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.148.08:10:12.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.148.08:10:12.30#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:12.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:12.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:12.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:12.38#ibcon#[27=AT05-03\r\n] 2006.148.08:10:12.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:12.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.148.08:10:12.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.148.08:10:12.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:12.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:12.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:12.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:12.55#ibcon#[27=USB\r\n] 2006.148.08:10:12.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:12.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.148.08:10:12.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:10:12.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:10:12.58$vc4f8/vblo=6,752.99 2006.148.08:10:12.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:10:12.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:10:12.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:10:12.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:12.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:12.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:12.60#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:10:12.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:12.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:10:12.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:10:12.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:10:12.64$vc4f8/vb=6,4 2006.148.08:10:12.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:10:12.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:10:12.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:10:12.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:12.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:12.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:12.72#ibcon#[27=AT06-04\r\n] 2006.148.08:10:12.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:12.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:10:12.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:10:12.75#ibcon#ireg 7 cls_cnt 0 2006.148.08:10:12.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:12.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:12.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:12.89#ibcon#[27=USB\r\n] 2006.148.08:10:12.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:12.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:10:12.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:10:12.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:10:12.92$vc4f8/vabw=wide 2006.148.08:10:12.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:10:12.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:10:12.92#ibcon#ireg 8 cls_cnt 0 2006.148.08:10:12.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:12.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:12.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:12.94#ibcon#[25=BW32\r\n] 2006.148.08:10:12.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:12.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:10:12.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:10:12.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:10:12.97$vc4f8/vbbw=wide 2006.148.08:10:12.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:10:12.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:10:12.97#ibcon#ireg 8 cls_cnt 0 2006.148.08:10:12.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:10:13.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:10:13.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:10:13.06#ibcon#[27=BW32\r\n] 2006.148.08:10:13.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:10:13.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:10:13.09#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:10:13.09#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:10:13.09$4f8m12a/ifd4f 2006.148.08:10:13.09$ifd4f/lo= 2006.148.08:10:13.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:10:13.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:10:13.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:10:13.09$ifd4f/patch= 2006.148.08:10:13.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:10:13.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:10:13.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:10:13.09$4f8m12a/"form=m,16.000,1:2 2006.148.08:10:13.09$4f8m12a/"tpicd 2006.148.08:10:13.09$4f8m12a/echo=off 2006.148.08:10:13.09$4f8m12a/xlog=off 2006.148.08:10:13.09:!2006.148.08:10:40 2006.148.08:10:24.14#trakl#Source acquired 2006.148.08:10:25.14#flagr#flagr/antenna,acquired 2006.148.08:10:40.00:preob 2006.148.08:10:41.14/onsource/TRACKING 2006.148.08:10:41.14:!2006.148.08:10:50 2006.148.08:10:50.00:data_valid=on 2006.148.08:10:50.00:midob 2006.148.08:10:50.14/onsource/TRACKING 2006.148.08:10:50.14/wx/22.01,994.4,94 2006.148.08:10:50.28/cable/+6.5321E-03 2006.148.08:10:51.37/va/01,08,usb,yes,29,30 2006.148.08:10:51.37/va/02,07,usb,yes,29,30 2006.148.08:10:51.37/va/03,08,usb,yes,21,22 2006.148.08:10:51.37/va/04,07,usb,yes,30,32 2006.148.08:10:51.37/va/05,06,usb,yes,32,34 2006.148.08:10:51.37/va/06,05,usb,yes,32,32 2006.148.08:10:51.37/va/07,05,usb,yes,32,32 2006.148.08:10:51.37/va/08,05,usb,yes,35,34 2006.148.08:10:51.60/valo/01,532.99,yes,locked 2006.148.08:10:51.60/valo/02,572.99,yes,locked 2006.148.08:10:51.60/valo/03,672.99,yes,locked 2006.148.08:10:51.60/valo/04,832.99,yes,locked 2006.148.08:10:51.60/valo/05,652.99,yes,locked 2006.148.08:10:51.60/valo/06,772.99,yes,locked 2006.148.08:10:51.60/valo/07,832.99,yes,locked 2006.148.08:10:51.60/valo/08,852.99,yes,locked 2006.148.08:10:52.69/vb/01,04,usb,yes,29,28 2006.148.08:10:52.69/vb/02,04,usb,yes,31,32 2006.148.08:10:52.69/vb/03,04,usb,yes,27,31 2006.148.08:10:52.69/vb/04,04,usb,yes,28,40 2006.148.08:10:52.69/vb/05,03,usb,yes,33,38 2006.148.08:10:52.69/vb/06,04,usb,yes,28,30 2006.148.08:10:52.69/vb/07,04,usb,yes,29,29 2006.148.08:10:52.69/vb/08,03,usb,yes,34,37 2006.148.08:10:52.92/vblo/01,632.99,yes,locked 2006.148.08:10:52.92/vblo/02,640.99,yes,locked 2006.148.08:10:52.92/vblo/03,656.99,yes,locked 2006.148.08:10:52.92/vblo/04,712.99,yes,locked 2006.148.08:10:52.92/vblo/05,744.99,yes,locked 2006.148.08:10:52.92/vblo/06,752.99,yes,locked 2006.148.08:10:52.92/vblo/07,734.99,yes,locked 2006.148.08:10:52.92/vblo/08,744.99,yes,locked 2006.148.08:10:53.07/vabw/8 2006.148.08:10:53.22/vbbw/8 2006.148.08:10:53.31/xfe/off,on,14.5 2006.148.08:10:53.68/ifatt/23,28,28,28 2006.148.08:10:54.08/fmout-gps/S +4.88E-07 2006.148.08:10:54.16:!2006.148.08:11:50 2006.148.08:11:50.01:data_valid=off 2006.148.08:11:50.01:postob 2006.148.08:11:50.13/cable/+6.5351E-03 2006.148.08:11:50.13/wx/22.03,994.4,94 2006.148.08:11:51.07/fmout-gps/S +4.87E-07 2006.148.08:11:51.07:scan_name=148-0812,k06148,60 2006.148.08:11:51.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.148.08:11:51.14#flagr#flagr/antenna,new-source 2006.148.08:11:52.14:checkk5 2006.148.08:11:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:11:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:11:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:11:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:11:54.05/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0810*_20??1480810??.k5 file! 2006.148.08:11:54.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0810*_20??1480810??.k5 file! 2006.148.08:11:54.81/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0810*_20??1480810??.k5 file! 2006.148.08:11:55.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0810*_20??1480810??.k5 file! 2006.148.08:11:55.92/k5log//k5ts1_log_newline 2006.148.08:11:56.61/k5log//k5ts2_log_newline 2006.148.08:11:57.31/k5log//k5ts3_log_newline 2006.148.08:11:58.01/k5log//k5ts4_log_newline 2006.148.08:11:58.16/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:11:58.16:4f8m12a=2 2006.148.08:11:58.17$4f8m12a/echo=on 2006.148.08:11:58.17$4f8m12a/pcalon 2006.148.08:11:58.17$pcalon/"no phase cal control is implemented here 2006.148.08:11:58.17$4f8m12a/"tpicd=stop 2006.148.08:11:58.17$4f8m12a/vc4f8 2006.148.08:11:58.17$vc4f8/valo=1,532.99 2006.148.08:11:58.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:11:58.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:11:58.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:58.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:11:58.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:11:58.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:11:58.18#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:11:58.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:11:58.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:11:58.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:11:58.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:11:58.23$vc4f8/va=1,8 2006.148.08:11:58.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:11:58.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:11:58.23#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:58.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:11:58.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:11:58.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:11:58.25#ibcon#[25=AT01-08\r\n] 2006.148.08:11:58.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:11:58.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:11:58.29#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:11:58.29#ibcon#ireg 7 cls_cnt 0 2006.148.08:11:58.29#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:11:58.41#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:11:58.41#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:11:58.43#ibcon#[25=USB\r\n] 2006.148.08:11:58.46#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:11:58.46#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:11:58.46#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:11:58.46#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:11:58.46$vc4f8/valo=2,572.99 2006.148.08:11:58.46#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:11:58.46#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:11:58.46#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:58.46#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:11:58.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:11:58.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:11:58.50#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:11:58.54#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:11:58.54#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:11:58.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:11:58.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:11:58.54$vc4f8/va=2,7 2006.148.08:11:58.54#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:11:58.54#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:11:58.54#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:58.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:11:58.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:11:58.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:11:58.60#ibcon#[25=AT02-07\r\n] 2006.148.08:11:58.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:11:58.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:11:58.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:11:58.63#ibcon#ireg 7 cls_cnt 0 2006.148.08:11:58.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:11:58.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:11:58.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:11:58.77#ibcon#[25=USB\r\n] 2006.148.08:11:58.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:11:58.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:11:58.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:11:58.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:11:58.82$vc4f8/valo=3,672.99 2006.148.08:11:58.82#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:11:58.82#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:11:58.82#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:58.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:11:58.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:11:58.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:11:58.84#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:11:58.88#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:11:58.88#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:11:58.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:11:58.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:11:58.88$vc4f8/va=3,8 2006.148.08:11:58.88#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:11:58.88#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:11:58.88#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:58.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:11:58.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:11:58.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:11:58.96#ibcon#[25=AT03-08\r\n] 2006.148.08:11:58.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:11:58.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:11:58.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:11:58.99#ibcon#ireg 7 cls_cnt 0 2006.148.08:11:58.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:11:59.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:11:59.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:11:59.13#ibcon#[25=USB\r\n] 2006.148.08:11:59.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:11:59.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:11:59.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:11:59.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:11:59.16$vc4f8/valo=4,832.99 2006.148.08:11:59.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:11:59.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:11:59.16#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:59.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:11:59.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:11:59.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:11:59.18#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:11:59.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:11:59.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:11:59.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:11:59.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:11:59.22$vc4f8/va=4,7 2006.148.08:11:59.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:11:59.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:11:59.22#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:59.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:11:59.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:11:59.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:11:59.30#ibcon#[25=AT04-07\r\n] 2006.148.08:11:59.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:11:59.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:11:59.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:11:59.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:11:59.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:11:59.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:11:59.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:11:59.47#ibcon#[25=USB\r\n] 2006.148.08:11:59.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:11:59.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:11:59.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:11:59.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:11:59.50$vc4f8/valo=5,652.99 2006.148.08:11:59.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:11:59.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:11:59.50#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:59.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:11:59.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:11:59.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:11:59.52#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:11:59.56#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:11:59.56#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:11:59.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:11:59.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:11:59.56$vc4f8/va=5,6 2006.148.08:11:59.56#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.08:11:59.56#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.08:11:59.56#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:59.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:11:59.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:11:59.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:11:59.64#ibcon#[25=AT05-06\r\n] 2006.148.08:11:59.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:11:59.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:11:59.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.08:11:59.67#ibcon#ireg 7 cls_cnt 0 2006.148.08:11:59.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:11:59.78#abcon#<5=/07 1.8 4.6 22.03 94 994.4\r\n> 2006.148.08:11:59.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:11:59.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:11:59.80#abcon#{5=INTERFACE CLEAR} 2006.148.08:11:59.81#ibcon#[25=USB\r\n] 2006.148.08:11:59.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:11:59.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:11:59.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:11:59.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:11:59.84$vc4f8/valo=6,772.99 2006.148.08:11:59.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:11:59.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:11:59.84#ibcon#ireg 17 cls_cnt 0 2006.148.08:11:59.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:11:59.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:11:59.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:11:59.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:11:59.86#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:11:59.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:11:59.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:11:59.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:11:59.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:11:59.90$vc4f8/va=6,5 2006.148.08:11:59.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.08:11:59.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.08:11:59.90#ibcon#ireg 11 cls_cnt 2 2006.148.08:11:59.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:11:59.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:11:59.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:11:59.98#ibcon#[25=AT06-05\r\n] 2006.148.08:12:00.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:12:00.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:12:00.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.08:12:00.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:00.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:12:00.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:12:00.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:12:00.15#ibcon#[25=USB\r\n] 2006.148.08:12:00.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:12:00.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:12:00.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:12:00.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:12:00.18$vc4f8/valo=7,832.99 2006.148.08:12:00.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:12:00.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:12:00.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:00.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:12:00.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:12:00.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:12:00.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:12:00.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:12:00.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:12:00.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:12:00.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:12:00.24$vc4f8/va=7,5 2006.148.08:12:00.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:12:00.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:12:00.24#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:00.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:12:00.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:12:00.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:12:00.32#ibcon#[25=AT07-05\r\n] 2006.148.08:12:00.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:12:00.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:12:00.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:12:00.35#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:00.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:12:00.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:12:00.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:12:00.49#ibcon#[25=USB\r\n] 2006.148.08:12:00.54#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:12:00.54#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:12:00.54#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:12:00.54#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:12:00.54$vc4f8/valo=8,852.99 2006.148.08:12:00.54#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:12:00.54#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:12:00.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:00.54#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:12:00.54#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:12:00.54#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:12:00.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:12:00.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:12:00.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:12:00.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:12:00.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:12:00.60$vc4f8/va=8,5 2006.148.08:12:00.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:12:00.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:12:00.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:00.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:12:00.66#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:12:00.66#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:12:00.68#ibcon#[25=AT08-05\r\n] 2006.148.08:12:00.71#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:12:00.71#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:12:00.71#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:12:00.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:00.71#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:12:00.83#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:12:00.83#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:12:00.85#ibcon#[25=USB\r\n] 2006.148.08:12:00.88#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:12:00.88#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:12:00.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:12:00.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:12:00.88$vc4f8/vblo=1,632.99 2006.148.08:12:00.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:12:00.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:12:00.88#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:00.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:12:00.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:12:00.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:12:00.90#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:12:00.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:12:00.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:12:00.94#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:12:00.94#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:12:00.94$vc4f8/vb=1,4 2006.148.08:12:00.94#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:12:00.94#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:12:00.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:00.94#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:12:00.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:12:00.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:12:00.96#ibcon#[27=AT01-04\r\n] 2006.148.08:12:00.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:12:00.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:12:00.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:12:00.99#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:00.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:12:01.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:12:01.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:12:01.13#ibcon#[27=USB\r\n] 2006.148.08:12:01.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:12:01.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:12:01.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:12:01.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:12:01.16$vc4f8/vblo=2,640.99 2006.148.08:12:01.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:12:01.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:12:01.16#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:01.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:12:01.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:12:01.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:12:01.18#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:12:01.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:12:01.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:12:01.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:12:01.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:12:01.22$vc4f8/vb=2,4 2006.148.08:12:01.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:12:01.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:12:01.22#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:01.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:12:01.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:12:01.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:12:01.32#ibcon#[27=AT02-04\r\n] 2006.148.08:12:01.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:12:01.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:12:01.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:12:01.35#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:01.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:12:01.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:12:01.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:12:01.49#ibcon#[27=USB\r\n] 2006.148.08:12:01.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:12:01.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:12:01.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:12:01.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:12:01.52$vc4f8/vblo=3,656.99 2006.148.08:12:01.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:12:01.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:12:01.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:01.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:12:01.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:12:01.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:12:01.54#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:12:01.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:12:01.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:12:01.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:12:01.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:12:01.58$vc4f8/vb=3,4 2006.148.08:12:01.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:12:01.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:12:01.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:01.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:12:01.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:12:01.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:12:01.66#ibcon#[27=AT03-04\r\n] 2006.148.08:12:01.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:12:01.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:12:01.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:12:01.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:01.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:12:01.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:12:01.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:12:01.83#ibcon#[27=USB\r\n] 2006.148.08:12:01.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:12:01.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:12:01.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:12:01.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:12:01.86$vc4f8/vblo=4,712.99 2006.148.08:12:01.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:12:01.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:12:01.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:01.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:12:01.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:12:01.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:12:01.88#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:12:01.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:12:01.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:12:01.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:12:01.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:12:01.92$vc4f8/vb=4,4 2006.148.08:12:01.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:12:01.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:12:01.92#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:01.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:12:01.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:12:01.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:12:02.00#ibcon#[27=AT04-04\r\n] 2006.148.08:12:02.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:12:02.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:12:02.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:12:02.03#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:02.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:12:02.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:12:02.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:12:02.17#ibcon#[27=USB\r\n] 2006.148.08:12:02.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:12:02.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:12:02.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:12:02.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:12:02.20$vc4f8/vblo=5,744.99 2006.148.08:12:02.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:12:02.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:12:02.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:02.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:12:02.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:12:02.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:12:02.25#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:12:02.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:12:02.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:12:02.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:12:02.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:12:02.29$vc4f8/vb=5,3 2006.148.08:12:02.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.08:12:02.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.08:12:02.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:02.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:12:02.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:12:02.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:12:02.34#ibcon#[27=AT05-03\r\n] 2006.148.08:12:02.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:12:02.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:12:02.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.08:12:02.37#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:02.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:12:02.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:12:02.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:12:02.51#ibcon#[27=USB\r\n] 2006.148.08:12:02.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:12:02.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:12:02.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:12:02.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:12:02.54$vc4f8/vblo=6,752.99 2006.148.08:12:02.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.08:12:02.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.08:12:02.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:12:02.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:12:02.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:12:02.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:12:02.56#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:12:02.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:12:02.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:12:02.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:12:02.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:12:02.60$vc4f8/vb=6,4 2006.148.08:12:02.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.08:12:02.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.08:12:02.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:12:02.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:12:02.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:12:02.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:12:02.68#ibcon#[27=AT06-04\r\n] 2006.148.08:12:02.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:12:02.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:12:02.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.08:12:02.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:12:02.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:12:02.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:12:02.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:12:02.85#ibcon#[27=USB\r\n] 2006.148.08:12:02.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:12:02.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:12:02.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:12:02.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:12:02.88$vc4f8/vabw=wide 2006.148.08:12:02.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.08:12:02.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.08:12:02.88#ibcon#ireg 8 cls_cnt 0 2006.148.08:12:02.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:12:02.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:12:02.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:12:02.90#ibcon#[25=BW32\r\n] 2006.148.08:12:02.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:12:02.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:12:02.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:12:02.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:12:02.93$vc4f8/vbbw=wide 2006.148.08:12:02.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:12:02.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:12:02.93#ibcon#ireg 8 cls_cnt 0 2006.148.08:12:02.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:12:03.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:12:03.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:12:03.02#ibcon#[27=BW32\r\n] 2006.148.08:12:03.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:12:03.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:12:03.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:12:03.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:12:03.05$4f8m12a/ifd4f 2006.148.08:12:03.05$ifd4f/lo= 2006.148.08:12:03.05$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:12:03.05$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:12:03.05$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:12:03.05$ifd4f/patch= 2006.148.08:12:03.05$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:12:03.05$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:12:03.05$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:12:03.05$4f8m12a/"form=m,16.000,1:2 2006.148.08:12:03.05$4f8m12a/"tpicd 2006.148.08:12:03.05$4f8m12a/echo=off 2006.148.08:12:03.05$4f8m12a/xlog=off 2006.148.08:12:03.05:!2006.148.08:12:30 2006.148.08:12:14.14#trakl#Source acquired 2006.148.08:12:15.14#flagr#flagr/antenna,acquired 2006.148.08:12:30.00:preob 2006.148.08:12:31.14/onsource/TRACKING 2006.148.08:12:31.14:!2006.148.08:12:40 2006.148.08:12:40.00:data_valid=on 2006.148.08:12:40.00:midob 2006.148.08:12:40.14/onsource/TRACKING 2006.148.08:12:40.14/wx/22.04,994.4,93 2006.148.08:12:40.25/cable/+6.5359E-03 2006.148.08:12:41.34/va/01,08,usb,yes,29,31 2006.148.08:12:41.34/va/02,07,usb,yes,29,31 2006.148.08:12:41.34/va/03,08,usb,yes,22,22 2006.148.08:12:41.34/va/04,07,usb,yes,30,32 2006.148.08:12:41.34/va/05,06,usb,yes,32,34 2006.148.08:12:41.34/va/06,05,usb,yes,33,32 2006.148.08:12:41.34/va/07,05,usb,yes,33,32 2006.148.08:12:41.34/va/08,05,usb,yes,35,34 2006.148.08:12:41.57/valo/01,532.99,yes,locked 2006.148.08:12:41.57/valo/02,572.99,yes,locked 2006.148.08:12:41.57/valo/03,672.99,yes,locked 2006.148.08:12:41.57/valo/04,832.99,yes,locked 2006.148.08:12:41.57/valo/05,652.99,yes,locked 2006.148.08:12:41.57/valo/06,772.99,yes,locked 2006.148.08:12:41.57/valo/07,832.99,yes,locked 2006.148.08:12:41.57/valo/08,852.99,yes,locked 2006.148.08:12:42.66/vb/01,04,usb,yes,29,28 2006.148.08:12:42.66/vb/02,04,usb,yes,31,32 2006.148.08:12:42.66/vb/03,04,usb,yes,27,31 2006.148.08:12:42.66/vb/04,04,usb,yes,28,29 2006.148.08:12:42.66/vb/05,03,usb,yes,33,38 2006.148.08:12:42.66/vb/06,04,usb,yes,28,30 2006.148.08:12:42.66/vb/07,04,usb,yes,30,29 2006.148.08:12:42.66/vb/08,03,usb,yes,34,38 2006.148.08:12:42.90/vblo/01,632.99,yes,locked 2006.148.08:12:42.90/vblo/02,640.99,yes,locked 2006.148.08:12:42.90/vblo/03,656.99,yes,locked 2006.148.08:12:42.90/vblo/04,712.99,yes,locked 2006.148.08:12:42.90/vblo/05,744.99,yes,locked 2006.148.08:12:42.90/vblo/06,752.99,yes,locked 2006.148.08:12:42.90/vblo/07,734.99,yes,locked 2006.148.08:12:42.90/vblo/08,744.99,yes,locked 2006.148.08:12:43.05/vabw/8 2006.148.08:12:43.20/vbbw/8 2006.148.08:12:43.29/xfe/off,on,14.7 2006.148.08:12:43.71/ifatt/23,28,28,28 2006.148.08:12:44.07/fmout-gps/S +4.87E-07 2006.148.08:12:44.11:!2006.148.08:13:40 2006.148.08:13:40.01:data_valid=off 2006.148.08:13:40.01:postob 2006.148.08:13:40.13/cable/+6.5370E-03 2006.148.08:13:40.13/wx/22.05,994.4,94 2006.148.08:13:41.07/fmout-gps/S +4.87E-07 2006.148.08:13:41.07:scan_name=148-0814,k06148,60 2006.148.08:13:41.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.148.08:13:41.14#flagr#flagr/antenna,new-source 2006.148.08:13:42.14:checkk5 2006.148.08:13:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:13:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:13:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:13:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:13:44.03/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0812*_20??1480812??.k5 file! 2006.148.08:13:44.41/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0812*_20??1480812??.k5 file! 2006.148.08:13:44.79/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0812*_20??1480812??.k5 file! 2006.148.08:13:45.16/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0812*_20??1480812??.k5 file! 2006.148.08:13:45.86/k5log//k5ts1_log_newline 2006.148.08:13:46.57/k5log//k5ts2_log_newline 2006.148.08:13:47.26/k5log//k5ts3_log_newline 2006.148.08:13:47.96/k5log//k5ts4_log_newline 2006.148.08:13:48.12/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:13:48.12:4f8m12a=2 2006.148.08:13:48.12$4f8m12a/echo=on 2006.148.08:13:48.12$4f8m12a/pcalon 2006.148.08:13:48.12$pcalon/"no phase cal control is implemented here 2006.148.08:13:48.12$4f8m12a/"tpicd=stop 2006.148.08:13:48.12$4f8m12a/vc4f8 2006.148.08:13:48.12$vc4f8/valo=1,532.99 2006.148.08:13:48.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:13:48.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:13:48.12#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:48.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:48.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:48.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:48.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:13:48.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:48.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:48.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:13:48.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:13:48.20$vc4f8/va=1,8 2006.148.08:13:48.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:13:48.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:13:48.20#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:48.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:48.20#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:48.20#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:48.22#ibcon#[25=AT01-08\r\n] 2006.148.08:13:48.25#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:48.25#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:48.25#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:13:48.25#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:48.25#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:48.37#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:48.37#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:48.39#ibcon#[25=USB\r\n] 2006.148.08:13:48.44#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:48.44#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:48.44#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:13:48.44#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:13:48.44$vc4f8/valo=2,572.99 2006.148.08:13:48.44#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:13:48.44#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:13:48.44#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:48.44#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:48.44#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:48.44#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:48.46#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:13:48.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:48.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:48.50#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:13:48.50#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:13:48.50$vc4f8/va=2,7 2006.148.08:13:48.50#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:13:48.50#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:13:48.50#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:48.50#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:48.56#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:48.56#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:48.58#ibcon#[25=AT02-07\r\n] 2006.148.08:13:48.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:48.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:48.63#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:13:48.63#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:48.63#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:48.75#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:48.75#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:48.77#ibcon#[25=USB\r\n] 2006.148.08:13:48.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:48.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:48.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:13:48.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:13:48.82$vc4f8/valo=3,672.99 2006.148.08:13:48.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:13:48.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:13:48.82#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:48.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:48.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:48.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:48.84#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:13:48.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:48.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:48.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:13:48.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:13:48.88$vc4f8/va=3,8 2006.148.08:13:48.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:13:48.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:13:48.88#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:48.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:48.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:48.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:48.96#ibcon#[25=AT03-08\r\n] 2006.148.08:13:48.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:48.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:48.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:13:48.99#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:48.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:49.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:49.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:49.13#ibcon#[25=USB\r\n] 2006.148.08:13:49.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:49.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:49.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:13:49.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:13:49.16$vc4f8/valo=4,832.99 2006.148.08:13:49.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:13:49.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:13:49.16#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:49.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:49.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:49.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:49.18#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:13:49.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:49.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:49.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:13:49.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:13:49.22$vc4f8/va=4,7 2006.148.08:13:49.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:13:49.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:13:49.22#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:49.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:49.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:49.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:49.30#ibcon#[25=AT04-07\r\n] 2006.148.08:13:49.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:49.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:49.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:13:49.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:49.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:49.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:49.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:49.47#ibcon#[25=USB\r\n] 2006.148.08:13:49.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:49.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:49.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:13:49.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:13:49.50$vc4f8/valo=5,652.99 2006.148.08:13:49.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:13:49.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:13:49.50#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:49.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:49.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:49.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:49.52#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:13:49.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:49.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:49.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:13:49.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:13:49.56$vc4f8/va=5,6 2006.148.08:13:49.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:13:49.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:13:49.56#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:49.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:49.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:49.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:49.64#ibcon#[25=AT05-06\r\n] 2006.148.08:13:49.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:49.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:49.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:13:49.67#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:49.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:49.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:49.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:49.81#ibcon#[25=USB\r\n] 2006.148.08:13:49.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:49.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:49.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:13:49.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:13:49.84$vc4f8/valo=6,772.99 2006.148.08:13:49.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:13:49.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:13:49.84#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:49.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:49.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:49.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:49.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:13:49.90#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:49.90#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:49.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:13:49.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:13:49.90$vc4f8/va=6,5 2006.148.08:13:49.90#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:13:49.90#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:13:49.90#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:49.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:49.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:49.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:49.98#ibcon#[25=AT06-05\r\n] 2006.148.08:13:50.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:50.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:50.01#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:13:50.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:50.01#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:13:50.13#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:13:50.13#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:13:50.15#ibcon#[25=USB\r\n] 2006.148.08:13:50.18#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:13:50.18#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:13:50.18#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:13:50.18#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:13:50.18$vc4f8/valo=7,832.99 2006.148.08:13:50.18#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:13:50.18#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:13:50.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:50.18#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:13:50.18#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:13:50.18#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:13:50.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:13:50.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:13:50.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:13:50.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:13:50.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:13:50.24$vc4f8/va=7,5 2006.148.08:13:50.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.08:13:50.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.08:13:50.24#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:50.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:13:50.30#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:13:50.30#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:13:50.32#ibcon#[25=AT07-05\r\n] 2006.148.08:13:50.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:13:50.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:13:50.35#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.08:13:50.35#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:50.35#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:13:50.47#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:13:50.47#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:13:50.49#ibcon#[25=USB\r\n] 2006.148.08:13:50.52#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:13:50.52#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:13:50.52#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:13:50.52#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:13:50.52$vc4f8/valo=8,852.99 2006.148.08:13:50.52#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.08:13:50.52#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.08:13:50.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:50.52#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:13:50.52#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:13:50.52#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:13:50.56#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:13:50.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:13:50.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:13:50.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:13:50.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:13:50.61$vc4f8/va=8,5 2006.148.08:13:50.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.08:13:50.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.08:13:50.61#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:50.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:13:50.64#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:13:50.64#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:13:50.66#ibcon#[25=AT08-05\r\n] 2006.148.08:13:50.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:13:50.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:13:50.69#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.08:13:50.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:50.69#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:13:50.81#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:13:50.81#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:13:50.83#ibcon#[25=USB\r\n] 2006.148.08:13:50.86#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:13:50.86#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:13:50.86#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:13:50.86#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:13:50.86$vc4f8/vblo=1,632.99 2006.148.08:13:50.86#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.08:13:50.86#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.08:13:50.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:50.86#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:13:50.86#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:13:50.86#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:13:50.88#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:13:50.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:13:50.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:13:50.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:13:50.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:13:50.92$vc4f8/vb=1,4 2006.148.08:13:50.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.08:13:50.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.08:13:50.92#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:50.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:13:50.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:13:50.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:13:50.94#ibcon#[27=AT01-04\r\n] 2006.148.08:13:50.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:13:50.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:13:50.97#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.08:13:50.97#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:50.97#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:13:51.09#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:13:51.09#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:13:51.11#ibcon#[27=USB\r\n] 2006.148.08:13:51.14#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:13:51.14#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:13:51.14#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:13:51.14#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:13:51.14$vc4f8/vblo=2,640.99 2006.148.08:13:51.14#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:13:51.14#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:13:51.14#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:51.14#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:51.14#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:51.14#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:51.16#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:13:51.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:51.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:13:51.20#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:13:51.20#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:13:51.20$vc4f8/vb=2,4 2006.148.08:13:51.20#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:13:51.20#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:13:51.20#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:51.20#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:51.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:51.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:51.28#ibcon#[27=AT02-04\r\n] 2006.148.08:13:51.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:51.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:13:51.31#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:13:51.31#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:51.31#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:51.43#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:51.43#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:51.45#ibcon#[27=USB\r\n] 2006.148.08:13:51.48#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:51.48#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:13:51.48#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:13:51.48#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:13:51.48$vc4f8/vblo=3,656.99 2006.148.08:13:51.48#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:13:51.48#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:13:51.48#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:51.48#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:51.48#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:51.48#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:51.50#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:13:51.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:51.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:13:51.54#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:13:51.54#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:13:51.54$vc4f8/vb=3,4 2006.148.08:13:51.54#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:13:51.54#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:13:51.54#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:51.54#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:51.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:51.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:51.62#ibcon#[27=AT03-04\r\n] 2006.148.08:13:51.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:51.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:13:51.65#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:13:51.65#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:51.65#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:51.77#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:51.77#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:51.79#ibcon#[27=USB\r\n] 2006.148.08:13:51.82#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:51.82#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:13:51.82#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:13:51.82#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:13:51.82$vc4f8/vblo=4,712.99 2006.148.08:13:51.82#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:13:51.82#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:13:51.82#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:51.82#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:51.82#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:51.82#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:51.84#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:13:51.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:51.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:13:51.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:13:51.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:13:51.88$vc4f8/vb=4,4 2006.148.08:13:51.88#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:13:51.88#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:13:51.88#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:51.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:51.94#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:51.94#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:51.96#ibcon#[27=AT04-04\r\n] 2006.148.08:13:51.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:51.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:13:51.99#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:13:51.99#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:51.99#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:52.11#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:52.11#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:52.13#ibcon#[27=USB\r\n] 2006.148.08:13:52.16#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:52.16#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:13:52.16#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:13:52.16#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:13:52.16$vc4f8/vblo=5,744.99 2006.148.08:13:52.16#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:13:52.16#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:13:52.16#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:52.16#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:52.16#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:52.16#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:52.18#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:13:52.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:52.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:13:52.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:13:52.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:13:52.22$vc4f8/vb=5,3 2006.148.08:13:52.22#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:13:52.22#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:13:52.22#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:52.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:52.28#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:52.28#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:52.30#ibcon#[27=AT05-03\r\n] 2006.148.08:13:52.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:52.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:13:52.33#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:13:52.33#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:52.33#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:52.45#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:52.45#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:52.47#ibcon#[27=USB\r\n] 2006.148.08:13:52.50#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:52.50#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:13:52.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:13:52.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:13:52.50$vc4f8/vblo=6,752.99 2006.148.08:13:52.50#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:13:52.50#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:13:52.50#ibcon#ireg 17 cls_cnt 0 2006.148.08:13:52.50#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:52.50#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:52.50#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:52.52#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:13:52.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:52.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:13:52.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:13:52.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:13:52.56$vc4f8/vb=6,4 2006.148.08:13:52.56#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:13:52.56#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:13:52.56#ibcon#ireg 11 cls_cnt 2 2006.148.08:13:52.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:52.62#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:52.62#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:52.64#ibcon#[27=AT06-04\r\n] 2006.148.08:13:52.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:52.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:13:52.67#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:13:52.67#ibcon#ireg 7 cls_cnt 0 2006.148.08:13:52.67#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:52.79#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:52.79#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:52.81#ibcon#[27=USB\r\n] 2006.148.08:13:52.84#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:52.84#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:13:52.84#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:13:52.84#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:13:52.84$vc4f8/vabw=wide 2006.148.08:13:52.84#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:13:52.84#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:13:52.84#ibcon#ireg 8 cls_cnt 0 2006.148.08:13:52.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:52.84#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:52.84#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:52.86#ibcon#[25=BW32\r\n] 2006.148.08:13:52.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:52.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:13:52.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:13:52.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:13:52.89$vc4f8/vbbw=wide 2006.148.08:13:52.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:13:52.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:13:52.89#ibcon#ireg 8 cls_cnt 0 2006.148.08:13:52.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:13:52.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:13:52.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:13:52.98#ibcon#[27=BW32\r\n] 2006.148.08:13:53.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:13:53.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:13:53.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:13:53.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:13:53.01$4f8m12a/ifd4f 2006.148.08:13:53.01$ifd4f/lo= 2006.148.08:13:53.01$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:13:53.01$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:13:53.01$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:13:53.01$ifd4f/patch= 2006.148.08:13:53.01$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:13:53.01$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:13:53.01$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:13:53.01$4f8m12a/"form=m,16.000,1:2 2006.148.08:13:53.01$4f8m12a/"tpicd 2006.148.08:13:53.01$4f8m12a/echo=off 2006.148.08:13:53.01$4f8m12a/xlog=off 2006.148.08:13:53.01:!2006.148.08:14:20 2006.148.08:14:03.14#trakl#Source acquired 2006.148.08:14:05.14#flagr#flagr/antenna,acquired 2006.148.08:14:20.00:preob 2006.148.08:14:21.14/onsource/TRACKING 2006.148.08:14:21.14:!2006.148.08:14:30 2006.148.08:14:30.00:data_valid=on 2006.148.08:14:30.00:midob 2006.148.08:14:30.13/onsource/TRACKING 2006.148.08:14:30.13/wx/22.05,994.5,94 2006.148.08:14:30.29/cable/+6.5349E-03 2006.148.08:14:31.38/va/01,08,usb,yes,30,32 2006.148.08:14:31.38/va/02,07,usb,yes,30,31 2006.148.08:14:31.38/va/03,08,usb,yes,22,23 2006.148.08:14:31.38/va/04,07,usb,yes,31,33 2006.148.08:14:31.38/va/05,06,usb,yes,33,35 2006.148.08:14:31.38/va/06,05,usb,yes,33,33 2006.148.08:14:31.38/va/07,05,usb,yes,33,33 2006.148.08:14:31.38/va/08,05,usb,yes,36,35 2006.148.08:14:31.61/valo/01,532.99,yes,locked 2006.148.08:14:31.61/valo/02,572.99,yes,locked 2006.148.08:14:31.61/valo/03,672.99,yes,locked 2006.148.08:14:31.61/valo/04,832.99,yes,locked 2006.148.08:14:31.61/valo/05,652.99,yes,locked 2006.148.08:14:31.61/valo/06,772.99,yes,locked 2006.148.08:14:31.61/valo/07,832.99,yes,locked 2006.148.08:14:31.61/valo/08,852.99,yes,locked 2006.148.08:14:32.70/vb/01,04,usb,yes,30,28 2006.148.08:14:32.70/vb/02,04,usb,yes,31,33 2006.148.08:14:32.70/vb/03,04,usb,yes,28,31 2006.148.08:14:32.70/vb/04,04,usb,yes,29,29 2006.148.08:14:32.70/vb/05,03,usb,yes,34,38 2006.148.08:14:32.70/vb/06,04,usb,yes,28,31 2006.148.08:14:32.70/vb/07,04,usb,yes,30,30 2006.148.08:14:32.70/vb/08,03,usb,yes,35,38 2006.148.08:14:32.94/vblo/01,632.99,yes,locked 2006.148.08:14:32.94/vblo/02,640.99,yes,locked 2006.148.08:14:32.94/vblo/03,656.99,yes,locked 2006.148.08:14:32.94/vblo/04,712.99,yes,locked 2006.148.08:14:32.94/vblo/05,744.99,yes,locked 2006.148.08:14:32.94/vblo/06,752.99,yes,locked 2006.148.08:14:32.94/vblo/07,734.99,yes,locked 2006.148.08:14:32.94/vblo/08,744.99,yes,locked 2006.148.08:14:33.09/vabw/8 2006.148.08:14:33.24/vbbw/8 2006.148.08:14:33.33/xfe/off,on,15.2 2006.148.08:14:33.71/ifatt/23,28,28,28 2006.148.08:14:34.07/fmout-gps/S +4.87E-07 2006.148.08:14:34.15:!2006.148.08:15:30 2006.148.08:15:30.01:data_valid=off 2006.148.08:15:30.01:postob 2006.148.08:15:30.21/cable/+6.5340E-03 2006.148.08:15:30.21/wx/22.04,994.5,94 2006.148.08:15:30.27/fmout-gps/S +4.87E-07 2006.148.08:15:30.27:scan_name=148-0816,k06148,70 2006.148.08:15:30.28:source=0536+145,053942.37,143345.6,2000.0,ccw 2006.148.08:15:31.13#flagr#flagr/antenna,new-source 2006.148.08:15:31.13:checkk5 2006.148.08:15:31.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:15:31.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:15:32.28/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:15:32.66/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:15:33.04/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0814*_20??1480814??.k5 file! 2006.148.08:15:33.42/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0814*_20??1480814??.k5 file! 2006.148.08:15:33.80/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0814*_20??1480814??.k5 file! 2006.148.08:15:34.22/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0814*_20??1480814??.k5 file! 2006.148.08:15:34.92/k5log//k5ts1_log_newline 2006.148.08:15:35.62/k5log//k5ts2_log_newline 2006.148.08:15:36.31/k5log//k5ts3_log_newline 2006.148.08:15:37.01/k5log//k5ts4_log_newline 2006.148.08:15:37.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:15:37.17:4f8m12a=2 2006.148.08:15:37.17$4f8m12a/echo=on 2006.148.08:15:37.17$4f8m12a/pcalon 2006.148.08:15:37.17$pcalon/"no phase cal control is implemented here 2006.148.08:15:37.17$4f8m12a/"tpicd=stop 2006.148.08:15:37.17$4f8m12a/vc4f8 2006.148.08:15:37.17$vc4f8/valo=1,532.99 2006.148.08:15:37.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.08:15:37.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.08:15:37.17#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:37.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:37.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:37.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:37.22#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:15:37.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:37.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:37.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:15:37.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:15:37.27$vc4f8/va=1,8 2006.148.08:15:37.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.08:15:37.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.08:15:37.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:37.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:37.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:37.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:37.30#ibcon#[25=AT01-08\r\n] 2006.148.08:15:37.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:37.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:37.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.08:15:37.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:37.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:37.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:37.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:37.48#ibcon#[25=USB\r\n] 2006.148.08:15:37.51#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:37.51#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:37.51#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:15:37.51#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:15:37.51$vc4f8/valo=2,572.99 2006.148.08:15:37.51#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:15:37.51#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:15:37.51#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:37.51#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:37.51#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:37.51#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:37.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:15:37.59#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:37.59#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:37.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:15:37.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:15:37.59$vc4f8/va=2,7 2006.148.08:15:37.59#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:15:37.59#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:15:37.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:37.59#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:37.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:37.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:37.65#ibcon#[25=AT02-07\r\n] 2006.148.08:15:37.68#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:37.68#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:37.68#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:15:37.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:37.68#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:37.80#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:37.80#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:37.82#ibcon#[25=USB\r\n] 2006.148.08:15:37.85#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:37.85#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:37.85#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:15:37.85#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:15:37.85$vc4f8/valo=3,672.99 2006.148.08:15:37.85#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:15:37.85#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:15:37.85#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:37.85#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:37.85#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:37.85#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:37.89#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:15:37.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:37.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:37.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:15:37.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:15:37.93$vc4f8/va=3,8 2006.148.08:15:37.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.08:15:37.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.08:15:37.93#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:37.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:37.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:37.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:37.99#ibcon#[25=AT03-08\r\n] 2006.148.08:15:38.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:38.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:38.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.08:15:38.02#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:38.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:38.14#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:38.14#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:38.16#ibcon#[25=USB\r\n] 2006.148.08:15:38.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:38.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:38.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:15:38.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:15:38.19$vc4f8/valo=4,832.99 2006.148.08:15:38.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.08:15:38.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.08:15:38.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:38.19#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:38.19#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:38.19#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:38.21#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:15:38.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:38.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:38.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:15:38.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:15:38.25$vc4f8/va=4,7 2006.148.08:15:38.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.08:15:38.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.08:15:38.25#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:38.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:38.31#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:38.31#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:38.33#ibcon#[25=AT04-07\r\n] 2006.148.08:15:38.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:38.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:38.36#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.08:15:38.36#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:38.36#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:38.48#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:38.48#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:38.50#ibcon#[25=USB\r\n] 2006.148.08:15:38.53#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:38.53#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:38.53#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:15:38.53#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:15:38.53$vc4f8/valo=5,652.99 2006.148.08:15:38.53#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:15:38.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:15:38.53#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:38.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:38.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:38.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:38.55#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:15:38.59#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:38.59#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:38.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:15:38.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:15:38.59$vc4f8/va=5,6 2006.148.08:15:38.59#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:15:38.59#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:15:38.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:38.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:38.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:38.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:38.67#ibcon#[25=AT05-06\r\n] 2006.148.08:15:38.70#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:38.70#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:38.70#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:15:38.70#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:38.70#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:38.82#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:38.82#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:38.84#ibcon#[25=USB\r\n] 2006.148.08:15:38.87#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:38.87#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:38.87#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:15:38.87#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:15:38.87$vc4f8/valo=6,772.99 2006.148.08:15:38.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:15:38.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:15:38.87#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:38.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:38.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:38.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:38.89#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:15:38.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:38.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:38.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:15:38.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:15:38.93$vc4f8/va=6,5 2006.148.08:15:38.93#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.08:15:38.93#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.08:15:38.93#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:38.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:38.99#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:38.99#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:39.01#ibcon#[25=AT06-05\r\n] 2006.148.08:15:39.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:39.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:39.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.08:15:39.04#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:39.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:15:39.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:15:39.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:15:39.18#ibcon#[25=USB\r\n] 2006.148.08:15:39.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:15:39.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:15:39.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:15:39.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:15:39.21$vc4f8/valo=7,832.99 2006.148.08:15:39.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:15:39.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:15:39.21#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:39.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:15:39.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:15:39.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:15:39.23#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:15:39.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:15:39.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:15:39.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:15:39.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:15:39.27$vc4f8/va=7,5 2006.148.08:15:39.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.08:15:39.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.08:15:39.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:39.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:15:39.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:15:39.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:15:39.35#ibcon#[25=AT07-05\r\n] 2006.148.08:15:39.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:15:39.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:15:39.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.08:15:39.38#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:39.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:15:39.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:15:39.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:15:39.53#ibcon#[25=USB\r\n] 2006.148.08:15:39.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:15:39.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:15:39.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:15:39.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:15:39.56$vc4f8/valo=8,852.99 2006.148.08:15:39.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.08:15:39.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.08:15:39.56#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:39.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:15:39.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:15:39.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:15:39.58#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:15:39.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:15:39.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:15:39.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:15:39.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:15:39.62$vc4f8/va=8,5 2006.148.08:15:39.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.08:15:39.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.08:15:39.62#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:39.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:15:39.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:15:39.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:15:39.70#ibcon#[25=AT08-05\r\n] 2006.148.08:15:39.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:15:39.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:15:39.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.08:15:39.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:39.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:15:39.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:15:39.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:15:39.87#ibcon#[25=USB\r\n] 2006.148.08:15:39.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:15:39.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:15:39.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:15:39.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:15:39.90$vc4f8/vblo=1,632.99 2006.148.08:15:39.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.08:15:39.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.08:15:39.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:39.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:15:39.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:15:39.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:15:39.92#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:15:39.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:15:39.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:15:39.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:15:39.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:15:39.96$vc4f8/vb=1,4 2006.148.08:15:39.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.08:15:39.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.08:15:39.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:39.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:15:39.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:15:39.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:15:39.98#ibcon#[27=AT01-04\r\n] 2006.148.08:15:40.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:15:40.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:15:40.01#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.08:15:40.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:40.01#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:15:40.13#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:15:40.13#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:15:40.15#ibcon#[27=USB\r\n] 2006.148.08:15:40.18#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:15:40.18#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:15:40.18#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:15:40.18#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:15:40.18$vc4f8/vblo=2,640.99 2006.148.08:15:40.18#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.08:15:40.18#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.08:15:40.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:40.18#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:40.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:40.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:40.20#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:15:40.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:40.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:15:40.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:15:40.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:15:40.24$vc4f8/vb=2,4 2006.148.08:15:40.24#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.08:15:40.24#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.08:15:40.24#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:40.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:40.30#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:40.30#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:40.32#ibcon#[27=AT02-04\r\n] 2006.148.08:15:40.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:40.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:15:40.35#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.08:15:40.35#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:40.35#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:40.47#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:40.47#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:40.49#ibcon#[27=USB\r\n] 2006.148.08:15:40.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:40.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:15:40.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:15:40.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:15:40.52$vc4f8/vblo=3,656.99 2006.148.08:15:40.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:15:40.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:15:40.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:40.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:40.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:40.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:40.54#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:15:40.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:40.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:15:40.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:15:40.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:15:40.58$vc4f8/vb=3,4 2006.148.08:15:40.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:15:40.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:15:40.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:40.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:40.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:40.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:40.66#ibcon#[27=AT03-04\r\n] 2006.148.08:15:40.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:40.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:15:40.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:15:40.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:40.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:40.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:40.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:40.83#ibcon#[27=USB\r\n] 2006.148.08:15:40.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:40.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:15:40.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:15:40.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:15:40.86$vc4f8/vblo=4,712.99 2006.148.08:15:40.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:15:40.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:15:40.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:40.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:40.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:40.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:40.88#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:15:40.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:40.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:15:40.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:15:40.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:15:40.92$vc4f8/vb=4,4 2006.148.08:15:40.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.08:15:40.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.08:15:40.92#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:40.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:40.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:40.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:41.00#ibcon#[27=AT04-04\r\n] 2006.148.08:15:41.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:41.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:15:41.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.08:15:41.03#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:41.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:41.13#trakl#Source acquired 2006.148.08:15:41.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:41.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:41.17#ibcon#[27=USB\r\n] 2006.148.08:15:41.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:41.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:15:41.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:15:41.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:15:41.20$vc4f8/vblo=5,744.99 2006.148.08:15:41.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.08:15:41.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.08:15:41.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:41.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:41.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:41.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:41.22#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:15:41.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:41.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:15:41.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:15:41.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:15:41.26$vc4f8/vb=5,3 2006.148.08:15:41.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.08:15:41.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.08:15:41.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:41.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:41.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:41.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:41.34#ibcon#[27=AT05-03\r\n] 2006.148.08:15:41.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:41.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:15:41.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.08:15:41.37#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:41.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:41.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:41.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:41.51#ibcon#[27=USB\r\n] 2006.148.08:15:41.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:41.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:15:41.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:15:41.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:15:41.54$vc4f8/vblo=6,752.99 2006.148.08:15:41.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:15:41.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:15:41.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:15:41.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:41.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:41.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:41.56#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:15:41.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:41.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:15:41.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:15:41.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:15:41.60$vc4f8/vb=6,4 2006.148.08:15:41.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:15:41.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:15:41.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:15:41.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:41.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:41.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:41.68#ibcon#[27=AT06-04\r\n] 2006.148.08:15:41.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:41.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:15:41.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:15:41.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:15:41.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:41.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:41.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:41.85#ibcon#[27=USB\r\n] 2006.148.08:15:41.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:41.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:15:41.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:15:41.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:15:41.88$vc4f8/vabw=wide 2006.148.08:15:41.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:15:41.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:15:41.88#ibcon#ireg 8 cls_cnt 0 2006.148.08:15:41.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:41.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:41.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:41.90#ibcon#[25=BW32\r\n] 2006.148.08:15:41.93#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:41.93#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:15:41.93#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:15:41.93#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:15:41.93$vc4f8/vbbw=wide 2006.148.08:15:41.93#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:15:41.93#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:15:41.93#ibcon#ireg 8 cls_cnt 0 2006.148.08:15:41.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:15:42.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:15:42.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:15:42.02#ibcon#[27=BW32\r\n] 2006.148.08:15:42.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:15:42.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:15:42.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:15:42.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:15:42.05$4f8m12a/ifd4f 2006.148.08:15:42.05$ifd4f/lo= 2006.148.08:15:42.05$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:15:42.05$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:15:42.05$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:15:42.05$ifd4f/patch= 2006.148.08:15:42.05$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:15:42.05$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:15:42.05$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:15:42.05$4f8m12a/"form=m,16.000,1:2 2006.148.08:15:42.05$4f8m12a/"tpicd 2006.148.08:15:42.05$4f8m12a/echo=off 2006.148.08:15:42.05$4f8m12a/xlog=off 2006.148.08:15:42.05:!2006.148.08:16:10 2006.148.08:15:42.13#flagr#flagr/antenna,acquired 2006.148.08:16:10.00:preob 2006.148.08:16:10.13/onsource/TRACKING 2006.148.08:16:10.13:!2006.148.08:16:20 2006.148.08:16:20.00:data_valid=on 2006.148.08:16:20.00:midob 2006.148.08:16:21.13/onsource/TRACKING 2006.148.08:16:21.13/wx/22.03,994.5,94 2006.148.08:16:21.25/cable/+6.5323E-03 2006.148.08:16:22.34/va/01,08,usb,yes,30,31 2006.148.08:16:22.34/va/02,07,usb,yes,30,31 2006.148.08:16:22.34/va/03,08,usb,yes,22,22 2006.148.08:16:22.34/va/04,07,usb,yes,30,33 2006.148.08:16:22.34/va/05,06,usb,yes,33,35 2006.148.08:16:22.34/va/06,05,usb,yes,33,33 2006.148.08:16:22.34/va/07,05,usb,yes,33,33 2006.148.08:16:22.34/va/08,05,usb,yes,36,35 2006.148.08:16:22.57/valo/01,532.99,yes,locked 2006.148.08:16:22.57/valo/02,572.99,yes,locked 2006.148.08:16:22.57/valo/03,672.99,yes,locked 2006.148.08:16:22.57/valo/04,832.99,yes,locked 2006.148.08:16:22.57/valo/05,652.99,yes,locked 2006.148.08:16:22.57/valo/06,772.99,yes,locked 2006.148.08:16:22.57/valo/07,832.99,yes,locked 2006.148.08:16:22.57/valo/08,852.99,yes,locked 2006.148.08:16:23.66/vb/01,04,usb,yes,29,28 2006.148.08:16:23.66/vb/02,04,usb,yes,31,32 2006.148.08:16:23.66/vb/03,04,usb,yes,27,31 2006.148.08:16:23.66/vb/04,04,usb,yes,28,28 2006.148.08:16:23.66/vb/05,03,usb,yes,33,38 2006.148.08:16:23.66/vb/06,04,usb,yes,28,30 2006.148.08:16:23.66/vb/07,04,usb,yes,29,29 2006.148.08:16:23.66/vb/08,03,usb,yes,34,37 2006.148.08:16:23.90/vblo/01,632.99,yes,locked 2006.148.08:16:23.90/vblo/02,640.99,yes,locked 2006.148.08:16:23.90/vblo/03,656.99,yes,locked 2006.148.08:16:23.90/vblo/04,712.99,yes,locked 2006.148.08:16:23.90/vblo/05,744.99,yes,locked 2006.148.08:16:23.90/vblo/06,752.99,yes,locked 2006.148.08:16:23.90/vblo/07,734.99,yes,locked 2006.148.08:16:23.90/vblo/08,744.99,yes,locked 2006.148.08:16:24.05/vabw/8 2006.148.08:16:24.20/vbbw/8 2006.148.08:16:24.29/xfe/off,on,15.2 2006.148.08:16:24.68/ifatt/23,28,28,28 2006.148.08:16:25.08/fmout-gps/S +4.86E-07 2006.148.08:16:25.12:!2006.148.08:17:30 2006.148.08:17:30.01:data_valid=off 2006.148.08:17:30.01:postob 2006.148.08:17:30.24/cable/+6.5326E-03 2006.148.08:17:30.24/wx/22.02,994.5,94 2006.148.08:17:31.08/fmout-gps/S +4.86E-07 2006.148.08:17:31.08:scan_name=148-0818,k06148,60 2006.148.08:17:31.09:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.148.08:17:32.14#flagr#flagr/antenna,new-source 2006.148.08:17:32.14:checkk5 2006.148.08:17:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:17:32.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:17:33.31/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:17:33.68/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:17:34.07/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0816*_20??1480816??.k5 file! 2006.148.08:17:34.45/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0816*_20??1480816??.k5 file! 2006.148.08:17:34.84/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0816*_20??1480816??.k5 file! 2006.148.08:17:35.22/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0816*_20??1480816??.k5 file! 2006.148.08:17:35.91/k5log//k5ts1_log_newline 2006.148.08:17:36.61/k5log//k5ts2_log_newline 2006.148.08:17:37.33/k5log//k5ts3_log_newline 2006.148.08:17:38.03/k5log//k5ts4_log_newline 2006.148.08:17:38.28/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:17:38.28:4f8m12a=2 2006.148.08:17:38.28$4f8m12a/echo=on 2006.148.08:17:38.28$4f8m12a/pcalon 2006.148.08:17:38.28$pcalon/"no phase cal control is implemented here 2006.148.08:17:38.28$4f8m12a/"tpicd=stop 2006.148.08:17:38.28$4f8m12a/vc4f8 2006.148.08:17:38.28$vc4f8/valo=1,532.99 2006.148.08:17:38.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:17:38.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:17:38.28#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:38.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:38.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:38.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:38.30#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:17:38.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:38.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:38.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:17:38.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:17:38.35$vc4f8/va=1,8 2006.148.08:17:38.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.08:17:38.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.08:17:38.35#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:38.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:38.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:38.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:38.37#ibcon#[25=AT01-08\r\n] 2006.148.08:17:38.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:38.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:38.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.08:17:38.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:38.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:38.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:38.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:38.54#ibcon#[25=USB\r\n] 2006.148.08:17:38.59#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:38.59#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:38.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:17:38.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:17:38.59$vc4f8/valo=2,572.99 2006.148.08:17:38.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:17:38.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:17:38.59#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:38.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:17:38.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:17:38.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:17:38.61#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:17:38.64#abcon#<5=/08 2.1 5.5 22.01 94 994.5\r\n> 2006.148.08:17:38.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:17:38.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:17:38.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:17:38.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:17:38.65$vc4f8/va=2,7 2006.148.08:17:38.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:17:38.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:17:38.65#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:38.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:17:38.68#abcon#{5=INTERFACE CLEAR} 2006.148.08:17:38.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:17:38.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:17:38.73#ibcon#[25=AT02-07\r\n] 2006.148.08:17:38.74#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:17:38.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:17:38.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:17:38.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:17:38.77#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:38.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:17:38.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:17:38.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:17:38.91#ibcon#[25=USB\r\n] 2006.148.08:17:38.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:17:38.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:17:38.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:17:38.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:17:38.96$vc4f8/valo=3,672.99 2006.148.08:17:38.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.08:17:38.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.08:17:38.96#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:38.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:38.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:38.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:38.98#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:17:39.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:39.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:39.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:17:39.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:17:39.02$vc4f8/va=3,8 2006.148.08:17:39.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.08:17:39.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.08:17:39.02#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:39.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:39.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:39.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:39.10#ibcon#[25=AT03-08\r\n] 2006.148.08:17:39.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:39.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:39.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.08:17:39.13#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:39.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:39.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:39.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:39.27#ibcon#[25=USB\r\n] 2006.148.08:17:39.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:39.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:39.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:17:39.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:17:39.30$vc4f8/valo=4,832.99 2006.148.08:17:39.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.08:17:39.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.08:17:39.30#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:39.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:39.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:39.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:39.32#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:17:39.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:39.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:39.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:17:39.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:17:39.36$vc4f8/va=4,7 2006.148.08:17:39.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.08:17:39.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.08:17:39.36#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:39.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:39.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:39.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:39.44#ibcon#[25=AT04-07\r\n] 2006.148.08:17:39.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:39.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:39.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.08:17:39.47#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:39.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:39.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:39.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:39.61#ibcon#[25=USB\r\n] 2006.148.08:17:39.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:39.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:39.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:17:39.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:17:39.64$vc4f8/valo=5,652.99 2006.148.08:17:39.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.08:17:39.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.08:17:39.64#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:39.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:39.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:39.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:39.66#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:17:39.70#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:39.70#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:39.70#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:17:39.70#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:17:39.70$vc4f8/va=5,6 2006.148.08:17:39.70#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.08:17:39.70#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.08:17:39.70#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:39.70#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:39.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:39.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:39.78#ibcon#[25=AT05-06\r\n] 2006.148.08:17:39.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:39.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:39.81#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.08:17:39.81#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:39.81#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:39.93#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:39.93#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:39.95#ibcon#[25=USB\r\n] 2006.148.08:17:40.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:40.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:40.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:17:40.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:17:40.00$vc4f8/valo=6,772.99 2006.148.08:17:40.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:17:40.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:17:40.00#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:40.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:40.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:40.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:40.02#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:17:40.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:40.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:40.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:17:40.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:17:40.06$vc4f8/va=6,5 2006.148.08:17:40.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.08:17:40.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.08:17:40.06#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:40.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:40.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:40.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:40.14#ibcon#[25=AT06-05\r\n] 2006.148.08:17:40.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:40.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:40.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.08:17:40.17#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:40.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:17:40.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:17:40.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:17:40.31#ibcon#[25=USB\r\n] 2006.148.08:17:40.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:17:40.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:17:40.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:17:40.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:17:40.34$vc4f8/valo=7,832.99 2006.148.08:17:40.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:17:40.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:17:40.34#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:40.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:17:40.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:17:40.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:17:40.36#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:17:40.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:17:40.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:17:40.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:17:40.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:17:40.40$vc4f8/va=7,5 2006.148.08:17:40.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.08:17:40.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.08:17:40.40#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:40.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:17:40.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:17:40.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:17:40.48#ibcon#[25=AT07-05\r\n] 2006.148.08:17:40.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:17:40.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:17:40.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.08:17:40.51#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:40.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:17:40.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:17:40.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:17:40.65#ibcon#[25=USB\r\n] 2006.148.08:17:40.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:17:40.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:17:40.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:17:40.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:17:40.68$vc4f8/valo=8,852.99 2006.148.08:17:40.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.08:17:40.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.08:17:40.68#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:40.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:17:40.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:17:40.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:17:40.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:17:40.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:17:40.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:17:40.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:17:40.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:17:40.74$vc4f8/va=8,5 2006.148.08:17:40.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.08:17:40.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.08:17:40.74#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:40.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:17:40.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:17:40.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:17:40.82#ibcon#[25=AT08-05\r\n] 2006.148.08:17:40.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:17:40.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:17:40.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.08:17:40.85#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:40.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:17:40.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:17:40.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:17:40.99#ibcon#[25=USB\r\n] 2006.148.08:17:41.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:17:41.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:17:41.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:17:41.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:17:41.02$vc4f8/vblo=1,632.99 2006.148.08:17:41.02#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:17:41.02#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:17:41.02#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:41.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:41.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:41.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:41.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:17:41.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:41.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:17:41.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:17:41.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:17:41.08$vc4f8/vb=1,4 2006.148.08:17:41.08#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.08:17:41.08#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.08:17:41.08#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:41.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:41.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:41.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:41.10#ibcon#[27=AT01-04\r\n] 2006.148.08:17:41.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:41.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:17:41.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.08:17:41.13#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:41.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:41.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:41.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:41.27#ibcon#[27=USB\r\n] 2006.148.08:17:41.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:41.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:17:41.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:17:41.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:17:41.30$vc4f8/vblo=2,640.99 2006.148.08:17:41.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:17:41.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:17:41.30#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:41.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:17:41.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:17:41.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:17:41.32#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:17:41.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:17:41.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:17:41.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:17:41.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:17:41.36$vc4f8/vb=2,4 2006.148.08:17:41.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.08:17:41.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.08:17:41.36#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:41.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:17:41.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:17:41.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:17:41.44#ibcon#[27=AT02-04\r\n] 2006.148.08:17:41.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:17:41.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:17:41.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.08:17:41.47#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:41.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:17:41.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:17:41.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:17:41.61#ibcon#[27=USB\r\n] 2006.148.08:17:41.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:17:41.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:17:41.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:17:41.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:17:41.64$vc4f8/vblo=3,656.99 2006.148.08:17:41.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.08:17:41.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.08:17:41.64#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:41.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:17:41.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:17:41.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:17:41.66#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:17:41.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:17:41.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:17:41.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:17:41.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:17:41.70$vc4f8/vb=3,4 2006.148.08:17:41.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.08:17:41.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.08:17:41.70#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:41.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:17:41.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:17:41.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:17:41.78#ibcon#[27=AT03-04\r\n] 2006.148.08:17:41.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:17:41.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:17:41.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.08:17:41.81#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:41.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:17:41.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:17:41.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:17:41.95#ibcon#[27=USB\r\n] 2006.148.08:17:41.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:17:41.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:17:41.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:17:41.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:17:41.98$vc4f8/vblo=4,712.99 2006.148.08:17:41.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.08:17:41.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.08:17:41.98#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:41.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:41.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:41.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:42.00#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:17:42.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:42.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:17:42.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:17:42.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:17:42.04$vc4f8/vb=4,4 2006.148.08:17:42.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.08:17:42.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.08:17:42.04#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:42.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:42.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:42.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:42.12#ibcon#[27=AT04-04\r\n] 2006.148.08:17:42.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:42.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:17:42.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.08:17:42.15#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:42.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:42.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:42.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:42.29#ibcon#[27=USB\r\n] 2006.148.08:17:42.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:42.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:17:42.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:17:42.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:17:42.32$vc4f8/vblo=5,744.99 2006.148.08:17:42.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.08:17:42.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.08:17:42.32#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:42.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:42.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:42.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:42.34#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:17:42.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:42.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:17:42.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:17:42.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:17:42.38$vc4f8/vb=5,3 2006.148.08:17:42.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.08:17:42.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.08:17:42.38#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:42.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:42.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:42.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:42.46#ibcon#[27=AT05-03\r\n] 2006.148.08:17:42.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:42.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:17:42.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.08:17:42.49#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:42.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:42.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:42.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:42.63#ibcon#[27=USB\r\n] 2006.148.08:17:42.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:42.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:17:42.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:17:42.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:17:42.66$vc4f8/vblo=6,752.99 2006.148.08:17:42.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.08:17:42.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.08:17:42.66#ibcon#ireg 17 cls_cnt 0 2006.148.08:17:42.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:42.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:42.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:42.68#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:17:42.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:42.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:17:42.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:17:42.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:17:42.72$vc4f8/vb=6,4 2006.148.08:17:42.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.08:17:42.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.08:17:42.72#ibcon#ireg 11 cls_cnt 2 2006.148.08:17:42.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:42.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:42.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:42.80#ibcon#[27=AT06-04\r\n] 2006.148.08:17:42.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:42.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:17:42.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.08:17:42.83#ibcon#ireg 7 cls_cnt 0 2006.148.08:17:42.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:42.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:42.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:42.97#ibcon#[27=USB\r\n] 2006.148.08:17:43.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:43.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:17:43.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:17:43.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:17:43.00$vc4f8/vabw=wide 2006.148.08:17:43.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:17:43.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:17:43.00#ibcon#ireg 8 cls_cnt 0 2006.148.08:17:43.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:43.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:43.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:43.02#ibcon#[25=BW32\r\n] 2006.148.08:17:43.05#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:43.05#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:17:43.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:17:43.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:17:43.05$vc4f8/vbbw=wide 2006.148.08:17:43.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:17:43.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:17:43.05#ibcon#ireg 8 cls_cnt 0 2006.148.08:17:43.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:17:43.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:17:43.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:17:43.14#ibcon#[27=BW32\r\n] 2006.148.08:17:43.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:17:43.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:17:43.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:17:43.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:17:43.17$4f8m12a/ifd4f 2006.148.08:17:43.17$ifd4f/lo= 2006.148.08:17:43.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:17:43.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:17:43.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:17:43.17$ifd4f/patch= 2006.148.08:17:43.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:17:43.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:17:43.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:17:43.17$4f8m12a/"form=m,16.000,1:2 2006.148.08:17:43.17$4f8m12a/"tpicd 2006.148.08:17:43.17$4f8m12a/echo=off 2006.148.08:17:43.17$4f8m12a/xlog=off 2006.148.08:17:43.17:!2006.148.08:18:20 2006.148.08:17:57.14#trakl#Source acquired 2006.148.08:17:57.14#flagr#flagr/antenna,acquired 2006.148.08:18:20.00:preob 2006.148.08:18:20.14/onsource/TRACKING 2006.148.08:18:20.14:!2006.148.08:18:30 2006.148.08:18:30.00:data_valid=on 2006.148.08:18:30.00:midob 2006.148.08:18:30.14/onsource/TRACKING 2006.148.08:18:30.14/wx/22.00,994.5,94 2006.148.08:18:30.25/cable/+6.5337E-03 2006.148.08:18:31.34/va/01,08,usb,yes,28,30 2006.148.08:18:31.34/va/02,07,usb,yes,29,30 2006.148.08:18:31.34/va/03,08,usb,yes,21,22 2006.148.08:18:31.34/va/04,07,usb,yes,29,31 2006.148.08:18:31.34/va/05,06,usb,yes,32,34 2006.148.08:18:31.34/va/06,05,usb,yes,32,32 2006.148.08:18:31.34/va/07,05,usb,yes,32,32 2006.148.08:18:31.34/va/08,05,usb,yes,35,34 2006.148.08:18:31.57/valo/01,532.99,yes,locked 2006.148.08:18:31.57/valo/02,572.99,yes,locked 2006.148.08:18:31.57/valo/03,672.99,yes,locked 2006.148.08:18:31.57/valo/04,832.99,yes,locked 2006.148.08:18:31.57/valo/05,652.99,yes,locked 2006.148.08:18:31.57/valo/06,772.99,yes,locked 2006.148.08:18:31.57/valo/07,832.99,yes,locked 2006.148.08:18:31.57/valo/08,852.99,yes,locked 2006.148.08:18:32.66/vb/01,04,usb,yes,29,27 2006.148.08:18:32.66/vb/02,04,usb,yes,30,32 2006.148.08:18:32.66/vb/03,04,usb,yes,27,30 2006.148.08:18:32.66/vb/04,04,usb,yes,28,29 2006.148.08:18:32.66/vb/05,03,usb,yes,33,37 2006.148.08:18:32.66/vb/06,04,usb,yes,28,30 2006.148.08:18:32.66/vb/07,04,usb,yes,29,29 2006.148.08:18:32.66/vb/08,03,usb,yes,34,37 2006.148.08:18:32.90/vblo/01,632.99,yes,locked 2006.148.08:18:32.90/vblo/02,640.99,yes,locked 2006.148.08:18:32.90/vblo/03,656.99,yes,locked 2006.148.08:18:32.90/vblo/04,712.99,yes,locked 2006.148.08:18:32.90/vblo/05,744.99,yes,locked 2006.148.08:18:32.90/vblo/06,752.99,yes,locked 2006.148.08:18:32.90/vblo/07,734.99,yes,locked 2006.148.08:18:32.90/vblo/08,744.99,yes,locked 2006.148.08:18:33.05/vabw/8 2006.148.08:18:33.20/vbbw/8 2006.148.08:18:33.29/xfe/off,on,14.2 2006.148.08:18:33.66/ifatt/23,28,28,28 2006.148.08:18:34.08/fmout-gps/S +4.86E-07 2006.148.08:18:34.16:!2006.148.08:19:30 2006.148.08:19:30.00:data_valid=off 2006.148.08:19:30.00:postob 2006.148.08:19:30.13/cable/+6.5329E-03 2006.148.08:19:30.13/wx/21.98,994.5,94 2006.148.08:19:31.08/fmout-gps/S +4.87E-07 2006.148.08:19:31.08:scan_name=148-0820,k06148,60 2006.148.08:19:31.08:source=0955+476,095819.67,472507.8,2000.0,neutral 2006.148.08:19:31.14#flagr#flagr/antenna,new-source 2006.148.08:19:32.14:checkk5 2006.148.08:19:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:19:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:19:33.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:19:33.69/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:19:34.08/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0818*_20??1480818??.k5 file! 2006.148.08:19:34.46/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0818*_20??1480818??.k5 file! 2006.148.08:19:34.85/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0818*_20??1480818??.k5 file! 2006.148.08:19:35.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0818*_20??1480818??.k5 file! 2006.148.08:19:35.92/k5log//k5ts1_log_newline 2006.148.08:19:36.63/k5log//k5ts2_log_newline 2006.148.08:19:37.33/k5log//k5ts3_log_newline 2006.148.08:19:38.03/k5log//k5ts4_log_newline 2006.148.08:19:38.21/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:19:38.21:4f8m12a=2 2006.148.08:19:38.21$4f8m12a/echo=on 2006.148.08:19:38.22$4f8m12a/pcalon 2006.148.08:19:38.22$pcalon/"no phase cal control is implemented here 2006.148.08:19:38.22$4f8m12a/"tpicd=stop 2006.148.08:19:38.22$4f8m12a/vc4f8 2006.148.08:19:38.22$vc4f8/valo=1,532.99 2006.148.08:19:38.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.148.08:19:38.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.148.08:19:38.22#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:38.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:19:38.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:19:38.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:19:38.24#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:19:38.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:19:38.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.148.08:19:38.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:19:38.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:19:38.29$vc4f8/va=1,8 2006.148.08:19:38.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:19:38.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:19:38.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:38.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:38.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:38.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:38.31#ibcon#[25=AT01-08\r\n] 2006.148.08:19:38.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:38.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:38.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:19:38.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:38.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:38.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:38.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:38.48#ibcon#[25=USB\r\n] 2006.148.08:19:38.53#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:38.53#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:38.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:19:38.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:19:38.53$vc4f8/valo=2,572.99 2006.148.08:19:38.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:19:38.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:19:38.53#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:38.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:38.53#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:38.53#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:38.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:19:38.59#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:38.59#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:38.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:19:38.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:19:38.59$vc4f8/va=2,7 2006.148.08:19:38.59#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.08:19:38.59#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.08:19:38.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:38.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:38.65#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:38.65#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:38.67#ibcon#[25=AT02-07\r\n] 2006.148.08:19:38.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:38.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:38.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.08:19:38.72#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:38.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:38.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:38.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:38.86#ibcon#[25=USB\r\n] 2006.148.08:19:38.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:38.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:38.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:19:38.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:19:38.91$vc4f8/valo=3,672.99 2006.148.08:19:38.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.08:19:38.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.08:19:38.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:38.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:38.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:38.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:38.93#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:19:38.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:38.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:38.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:19:38.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:19:38.97$vc4f8/va=3,8 2006.148.08:19:38.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.08:19:38.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.08:19:38.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:38.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:39.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:39.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:39.05#ibcon#[25=AT03-08\r\n] 2006.148.08:19:39.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:39.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:39.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.08:19:39.08#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:39.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:39.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:39.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:39.22#ibcon#[25=USB\r\n] 2006.148.08:19:39.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:39.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:39.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:19:39.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:19:39.25$vc4f8/valo=4,832.99 2006.148.08:19:39.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.08:19:39.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.08:19:39.25#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:39.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:39.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:39.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:39.27#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:19:39.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:39.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:39.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:19:39.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:19:39.31$vc4f8/va=4,7 2006.148.08:19:39.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.08:19:39.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.08:19:39.31#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:39.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:39.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:39.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:39.39#ibcon#[25=AT04-07\r\n] 2006.148.08:19:39.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:39.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:39.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.08:19:39.42#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:39.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:39.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:39.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:39.56#ibcon#[25=USB\r\n] 2006.148.08:19:39.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:39.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:39.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:19:39.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:19:39.59$vc4f8/valo=5,652.99 2006.148.08:19:39.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.08:19:39.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.08:19:39.59#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:39.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:39.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:39.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:39.61#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:19:39.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:39.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:39.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:19:39.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:19:39.65$vc4f8/va=5,6 2006.148.08:19:39.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.08:19:39.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.08:19:39.65#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:39.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:39.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:39.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:39.73#ibcon#[25=AT05-06\r\n] 2006.148.08:19:39.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:39.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:39.76#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.08:19:39.76#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:39.76#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:39.88#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:39.88#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:39.90#ibcon#[25=USB\r\n] 2006.148.08:19:39.93#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:39.93#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:39.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:19:39.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:19:39.93$vc4f8/valo=6,772.99 2006.148.08:19:39.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:19:39.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:19:39.93#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:39.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:39.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:39.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:39.95#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:19:39.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:39.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:39.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:19:39.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:19:39.99$vc4f8/va=6,5 2006.148.08:19:39.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:19:39.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:19:39.99#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:39.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:40.05#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:40.05#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:40.07#ibcon#[25=AT06-05\r\n] 2006.148.08:19:40.10#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:40.10#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:40.10#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:19:40.10#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:40.10#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:40.22#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:40.22#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:40.24#ibcon#[25=USB\r\n] 2006.148.08:19:40.27#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:40.27#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:40.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:19:40.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:19:40.27$vc4f8/valo=7,832.99 2006.148.08:19:40.27#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:19:40.27#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:19:40.27#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:40.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:40.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:40.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:40.29#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:19:40.33#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:40.33#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:40.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:19:40.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:19:40.33$vc4f8/va=7,5 2006.148.08:19:40.33#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.148.08:19:40.33#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.148.08:19:40.33#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:40.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:40.39#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:40.39#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:40.41#ibcon#[25=AT07-05\r\n] 2006.148.08:19:40.44#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:40.44#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:40.44#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.148.08:19:40.44#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:40.44#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:19:40.56#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:19:40.56#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:19:40.58#ibcon#[25=USB\r\n] 2006.148.08:19:40.63#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:19:40.63#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.148.08:19:40.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:19:40.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:19:40.63$vc4f8/valo=8,852.99 2006.148.08:19:40.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:19:40.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:19:40.63#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:40.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:19:40.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:19:40.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:19:40.65#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:19:40.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:19:40.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:19:40.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:19:40.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:19:40.69$vc4f8/va=8,5 2006.148.08:19:40.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.148.08:19:40.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.148.08:19:40.69#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:40.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:19:40.75#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:19:40.75#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:19:40.77#ibcon#[25=AT08-05\r\n] 2006.148.08:19:40.80#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:19:40.80#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.148.08:19:40.80#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.148.08:19:40.80#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:40.80#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:19:40.91#abcon#<5=/08 2.1 5.5 21.98 94 994.5\r\n> 2006.148.08:19:40.92#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:19:40.92#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:19:40.93#abcon#{5=INTERFACE CLEAR} 2006.148.08:19:40.94#ibcon#[25=USB\r\n] 2006.148.08:19:40.97#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:19:40.97#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.148.08:19:40.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:19:40.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:19:40.97$vc4f8/vblo=1,632.99 2006.148.08:19:40.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:19:40.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:19:40.97#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:40.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:19:40.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:19:40.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:19:40.99#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:19:40.99#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:19:41.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:19:41.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:19:41.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:19:41.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:19:41.03$vc4f8/vb=1,4 2006.148.08:19:41.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.148.08:19:41.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.148.08:19:41.03#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:41.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:41.03#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:41.03#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:41.05#ibcon#[27=AT01-04\r\n] 2006.148.08:19:41.08#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:41.08#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.148.08:19:41.08#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.148.08:19:41.08#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:41.08#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:41.20#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:41.20#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:41.22#ibcon#[27=USB\r\n] 2006.148.08:19:41.25#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:41.25#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.148.08:19:41.25#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:19:41.25#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:19:41.25$vc4f8/vblo=2,640.99 2006.148.08:19:41.25#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.148.08:19:41.25#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.148.08:19:41.25#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:41.25#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:41.25#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:41.25#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:41.27#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:19:41.31#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:41.31#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.148.08:19:41.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:19:41.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:19:41.31$vc4f8/vb=2,4 2006.148.08:19:41.31#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.148.08:19:41.31#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.148.08:19:41.31#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:41.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:41.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:41.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:41.40#ibcon#[27=AT02-04\r\n] 2006.148.08:19:41.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:41.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.148.08:19:41.44#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.148.08:19:41.44#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:41.44#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:41.56#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:41.56#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:41.58#ibcon#[27=USB\r\n] 2006.148.08:19:41.61#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:41.61#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.148.08:19:41.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:19:41.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:19:41.61$vc4f8/vblo=3,656.99 2006.148.08:19:41.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.148.08:19:41.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.148.08:19:41.61#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:41.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:41.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:41.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:41.63#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:19:41.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:41.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.148.08:19:41.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:19:41.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:19:41.67$vc4f8/vb=3,4 2006.148.08:19:41.67#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.148.08:19:41.67#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.148.08:19:41.67#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:41.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:41.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:41.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:41.75#ibcon#[27=AT03-04\r\n] 2006.148.08:19:41.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:41.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.148.08:19:41.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.148.08:19:41.78#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:41.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:41.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:41.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:41.92#ibcon#[27=USB\r\n] 2006.148.08:19:41.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:41.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.148.08:19:41.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:19:41.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:19:41.95$vc4f8/vblo=4,712.99 2006.148.08:19:41.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.148.08:19:41.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.148.08:19:41.95#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:41.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:41.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:41.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:41.97#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:19:42.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:42.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.148.08:19:42.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:19:42.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:19:42.01$vc4f8/vb=4,4 2006.148.08:19:42.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.148.08:19:42.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.148.08:19:42.01#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:42.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:42.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:42.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:42.09#ibcon#[27=AT04-04\r\n] 2006.148.08:19:42.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:42.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.148.08:19:42.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.148.08:19:42.12#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:42.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:42.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:42.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:42.26#ibcon#[27=USB\r\n] 2006.148.08:19:42.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:42.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.148.08:19:42.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:19:42.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:19:42.29$vc4f8/vblo=5,744.99 2006.148.08:19:42.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.148.08:19:42.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.148.08:19:42.29#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:42.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:42.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:42.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:42.33#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:19:42.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:42.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.148.08:19:42.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:19:42.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:19:42.37$vc4f8/vb=5,3 2006.148.08:19:42.37#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.148.08:19:42.37#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.148.08:19:42.37#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:42.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:42.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:42.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:42.43#ibcon#[27=AT05-03\r\n] 2006.148.08:19:42.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:42.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.148.08:19:42.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.148.08:19:42.46#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:42.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:42.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:42.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:42.60#ibcon#[27=USB\r\n] 2006.148.08:19:42.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:42.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.148.08:19:42.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:19:42.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:19:42.63$vc4f8/vblo=6,752.99 2006.148.08:19:42.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:19:42.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:19:42.63#ibcon#ireg 17 cls_cnt 0 2006.148.08:19:42.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:42.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:42.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:42.65#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:19:42.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:42.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:19:42.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:19:42.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:19:42.69$vc4f8/vb=6,4 2006.148.08:19:42.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.148.08:19:42.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.148.08:19:42.69#ibcon#ireg 11 cls_cnt 2 2006.148.08:19:42.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:42.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:42.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:42.77#ibcon#[27=AT06-04\r\n] 2006.148.08:19:42.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:42.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.148.08:19:42.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.148.08:19:42.80#ibcon#ireg 7 cls_cnt 0 2006.148.08:19:42.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:42.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:42.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:42.94#ibcon#[27=USB\r\n] 2006.148.08:19:42.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:42.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.148.08:19:42.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:19:42.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:19:42.97$vc4f8/vabw=wide 2006.148.08:19:42.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.148.08:19:42.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.148.08:19:42.97#ibcon#ireg 8 cls_cnt 0 2006.148.08:19:42.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:42.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:42.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:42.99#ibcon#[25=BW32\r\n] 2006.148.08:19:43.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:43.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.148.08:19:43.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:19:43.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:19:43.02$vc4f8/vbbw=wide 2006.148.08:19:43.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:19:43.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:19:43.02#ibcon#ireg 8 cls_cnt 0 2006.148.08:19:43.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:19:43.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:19:43.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:19:43.11#ibcon#[27=BW32\r\n] 2006.148.08:19:43.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:19:43.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:19:43.14#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:19:43.14#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:19:43.14$4f8m12a/ifd4f 2006.148.08:19:43.14$ifd4f/lo= 2006.148.08:19:43.14$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:19:43.14$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:19:43.14$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:19:43.14$ifd4f/patch= 2006.148.08:19:43.14$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:19:43.14$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:19:43.14$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:19:43.14$4f8m12a/"form=m,16.000,1:2 2006.148.08:19:43.14$4f8m12a/"tpicd 2006.148.08:19:43.14$4f8m12a/echo=off 2006.148.08:19:43.14$4f8m12a/xlog=off 2006.148.08:19:43.14:!2006.148.08:20:10 2006.148.08:19:53.14#trakl#Source acquired 2006.148.08:19:55.14#flagr#flagr/antenna,acquired 2006.148.08:20:10.00:preob 2006.148.08:20:11.14/onsource/TRACKING 2006.148.08:20:11.14:!2006.148.08:20:20 2006.148.08:20:20.00:data_valid=on 2006.148.08:20:20.00:midob 2006.148.08:20:20.14/onsource/TRACKING 2006.148.08:20:20.14/wx/21.98,994.5,94 2006.148.08:20:20.21/cable/+6.5354E-03 2006.148.08:20:21.30/va/01,08,usb,yes,28,30 2006.148.08:20:21.30/va/02,07,usb,yes,28,30 2006.148.08:20:21.30/va/03,08,usb,yes,21,21 2006.148.08:20:21.30/va/04,07,usb,yes,29,31 2006.148.08:20:21.30/va/05,06,usb,yes,31,33 2006.148.08:20:21.30/va/06,05,usb,yes,32,31 2006.148.08:20:21.30/va/07,05,usb,yes,32,31 2006.148.08:20:21.30/va/08,05,usb,yes,34,33 2006.148.08:20:21.53/valo/01,532.99,yes,locked 2006.148.08:20:21.53/valo/02,572.99,yes,locked 2006.148.08:20:21.53/valo/03,672.99,yes,locked 2006.148.08:20:21.53/valo/04,832.99,yes,locked 2006.148.08:20:21.53/valo/05,652.99,yes,locked 2006.148.08:20:21.53/valo/06,772.99,yes,locked 2006.148.08:20:21.53/valo/07,832.99,yes,locked 2006.148.08:20:21.53/valo/08,852.99,yes,locked 2006.148.08:20:22.62/vb/01,04,usb,yes,28,27 2006.148.08:20:22.62/vb/02,04,usb,yes,30,31 2006.148.08:20:22.62/vb/03,04,usb,yes,26,30 2006.148.08:20:22.62/vb/04,04,usb,yes,28,37 2006.148.08:20:22.62/vb/05,03,usb,yes,32,36 2006.148.08:20:22.62/vb/06,04,usb,yes,27,29 2006.148.08:20:22.62/vb/07,04,usb,yes,29,28 2006.148.08:20:22.62/vb/08,03,usb,yes,33,36 2006.148.08:20:22.85/vblo/01,632.99,yes,locked 2006.148.08:20:22.85/vblo/02,640.99,yes,locked 2006.148.08:20:22.85/vblo/03,656.99,yes,locked 2006.148.08:20:22.85/vblo/04,712.99,yes,locked 2006.148.08:20:22.85/vblo/05,744.99,yes,locked 2006.148.08:20:22.85/vblo/06,752.99,yes,locked 2006.148.08:20:22.85/vblo/07,734.99,yes,locked 2006.148.08:20:22.85/vblo/08,744.99,yes,locked 2006.148.08:20:23.00/vabw/8 2006.148.08:20:23.15/vbbw/8 2006.148.08:20:23.24/xfe/off,on,15.2 2006.148.08:20:23.61/ifatt/23,28,28,28 2006.148.08:20:24.08/fmout-gps/S +4.87E-07 2006.148.08:20:24.12:!2006.148.08:21:20 2006.148.08:21:20.00:data_valid=off 2006.148.08:21:20.00:postob 2006.148.08:21:20.16/cable/+6.5310E-03 2006.148.08:21:20.16/wx/21.98,994.6,94 2006.148.08:21:21.08/fmout-gps/S +4.87E-07 2006.148.08:21:21.08:scan_name=148-0822,k06148,60 2006.148.08:21:21.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.148.08:21:21.14#flagr#flagr/antenna,new-source 2006.148.08:21:22.14:checkk5 2006.148.08:21:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:21:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:21:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:21:23.69/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:21:24.06/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0820*_20??1480820??.k5 file! 2006.148.08:21:24.45/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0820*_20??1480820??.k5 file! 2006.148.08:21:24.84/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0820*_20??1480820??.k5 file! 2006.148.08:21:25.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0820*_20??1480820??.k5 file! 2006.148.08:21:25.93/k5log//k5ts1_log_newline 2006.148.08:21:26.63/k5log//k5ts2_log_newline 2006.148.08:21:27.32/k5log//k5ts3_log_newline 2006.148.08:21:28.01/k5log//k5ts4_log_newline 2006.148.08:21:28.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:21:28.17:4f8m12a=3 2006.148.08:21:28.18$4f8m12a/echo=on 2006.148.08:21:28.18$4f8m12a/pcalon 2006.148.08:21:28.18$pcalon/"no phase cal control is implemented here 2006.148.08:21:28.18$4f8m12a/"tpicd=stop 2006.148.08:21:28.18$4f8m12a/vc4f8 2006.148.08:21:28.18$vc4f8/valo=1,532.99 2006.148.08:21:28.19#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.08:21:28.19#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.08:21:28.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:28.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:28.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:28.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:28.21#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:21:28.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:28.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:28.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:21:28.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:21:28.26$vc4f8/va=1,8 2006.148.08:21:28.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.08:21:28.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.08:21:28.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:28.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:28.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:28.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:28.28#ibcon#[25=AT01-08\r\n] 2006.148.08:21:28.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:28.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:28.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.08:21:28.31#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:28.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:28.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:28.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:28.45#ibcon#[25=USB\r\n] 2006.148.08:21:28.50#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:28.50#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:28.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:21:28.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:21:28.50$vc4f8/valo=2,572.99 2006.148.08:21:28.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.08:21:28.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.08:21:28.50#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:28.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:28.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:28.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:28.52#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:21:28.56#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:28.56#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:28.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:21:28.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:21:28.56$vc4f8/va=2,7 2006.148.08:21:28.56#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.08:21:28.56#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.08:21:28.56#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:28.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:28.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:28.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:28.64#ibcon#[25=AT02-07\r\n] 2006.148.08:21:28.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:28.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:28.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.08:21:28.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:28.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:28.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:28.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:28.83#ibcon#[25=USB\r\n] 2006.148.08:21:28.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:28.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:28.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:21:28.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:21:28.88$vc4f8/valo=3,672.99 2006.148.08:21:28.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:21:28.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:21:28.88#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:28.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:28.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:28.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:28.90#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:21:28.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:28.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:28.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:21:28.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:21:28.94$vc4f8/va=3,8 2006.148.08:21:28.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:21:28.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:21:28.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:28.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:29.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:29.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:29.02#ibcon#[25=AT03-08\r\n] 2006.148.08:21:29.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:29.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:29.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:21:29.05#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:29.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:29.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:29.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:29.19#ibcon#[25=USB\r\n] 2006.148.08:21:29.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:29.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:29.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:21:29.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:21:29.22$vc4f8/valo=4,832.99 2006.148.08:21:29.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:21:29.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:21:29.22#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:29.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:29.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:29.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:29.24#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:21:29.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:29.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:29.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:21:29.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:21:29.28$vc4f8/va=4,7 2006.148.08:21:29.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:21:29.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:21:29.28#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:29.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:29.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:29.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:29.36#ibcon#[25=AT04-07\r\n] 2006.148.08:21:29.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:29.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:29.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:21:29.39#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:29.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:29.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:29.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:29.53#ibcon#[25=USB\r\n] 2006.148.08:21:29.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:29.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:29.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:21:29.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:21:29.56$vc4f8/valo=5,652.99 2006.148.08:21:29.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:21:29.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:21:29.56#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:29.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:29.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:29.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:29.58#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:21:29.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:29.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:29.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:21:29.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:21:29.62$vc4f8/va=5,6 2006.148.08:21:29.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:21:29.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:21:29.62#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:29.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:29.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:29.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:29.70#ibcon#[25=AT05-06\r\n] 2006.148.08:21:29.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:29.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:29.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:21:29.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:29.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:29.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:29.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:29.87#ibcon#[25=USB\r\n] 2006.148.08:21:29.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:29.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:29.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:21:29.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:21:29.90$vc4f8/valo=6,772.99 2006.148.08:21:29.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.148.08:21:29.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.148.08:21:29.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:29.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:21:29.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:21:29.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:21:29.92#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:21:29.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:21:29.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.148.08:21:29.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:21:29.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:21:29.96$vc4f8/va=6,5 2006.148.08:21:29.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.148.08:21:29.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.148.08:21:29.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:29.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:21:30.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:21:30.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:21:30.04#ibcon#[25=AT06-05\r\n] 2006.148.08:21:30.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:21:30.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.148.08:21:30.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.148.08:21:30.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:30.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:21:30.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:21:30.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:21:30.21#ibcon#[25=USB\r\n] 2006.148.08:21:30.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:21:30.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.148.08:21:30.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:21:30.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:21:30.24$vc4f8/valo=7,832.99 2006.148.08:21:30.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.148.08:21:30.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.148.08:21:30.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:30.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:21:30.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:21:30.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:21:30.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:21:30.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:21:30.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.148.08:21:30.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:21:30.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:21:30.30$vc4f8/va=7,5 2006.148.08:21:30.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.148.08:21:30.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.148.08:21:30.30#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:30.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:30.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:30.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:30.38#ibcon#[25=AT07-05\r\n] 2006.148.08:21:30.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:30.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:30.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.148.08:21:30.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:30.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:21:30.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:21:30.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:21:30.55#ibcon#[25=USB\r\n] 2006.148.08:21:30.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:21:30.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.148.08:21:30.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:21:30.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:21:30.58$vc4f8/valo=8,852.99 2006.148.08:21:30.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.148.08:21:30.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.148.08:21:30.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:30.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:21:30.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:21:30.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:21:30.60#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:21:30.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:21:30.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.148.08:21:30.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:21:30.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:21:30.64$vc4f8/va=8,5 2006.148.08:21:30.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.148.08:21:30.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.148.08:21:30.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:30.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:21:30.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:21:30.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:21:30.72#ibcon#[25=AT08-05\r\n] 2006.148.08:21:30.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:21:30.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.148.08:21:30.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.148.08:21:30.75#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:30.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:21:30.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:21:30.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:21:30.89#ibcon#[25=USB\r\n] 2006.148.08:21:30.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:21:30.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.148.08:21:30.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:21:30.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:21:30.92$vc4f8/vblo=1,632.99 2006.148.08:21:30.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:21:30.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:21:30.92#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:30.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:21:30.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:21:30.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:21:30.94#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:21:30.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:21:30.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:21:30.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:21:30.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:21:30.98$vc4f8/vb=1,4 2006.148.08:21:30.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.148.08:21:30.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.148.08:21:30.98#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:30.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:21:30.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:21:30.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:21:31.00#ibcon#[27=AT01-04\r\n] 2006.148.08:21:31.03#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:21:31.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.148.08:21:31.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.148.08:21:31.03#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:31.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:21:31.15#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:21:31.15#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:21:31.17#ibcon#[27=USB\r\n] 2006.148.08:21:31.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:21:31.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.148.08:21:31.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:21:31.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:21:31.20$vc4f8/vblo=2,640.99 2006.148.08:21:31.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.148.08:21:31.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.148.08:21:31.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:31.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:31.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:31.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:31.24#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:21:31.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:31.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.148.08:21:31.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:21:31.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:21:31.29$vc4f8/vb=2,4 2006.148.08:21:31.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.148.08:21:31.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.148.08:21:31.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:31.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:31.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:31.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:31.34#ibcon#[27=AT02-04\r\n] 2006.148.08:21:31.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:31.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.148.08:21:31.37#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.148.08:21:31.37#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:31.37#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:31.49#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:31.49#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:31.51#ibcon#[27=USB\r\n] 2006.148.08:21:31.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:31.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.148.08:21:31.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:21:31.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:21:31.54$vc4f8/vblo=3,656.99 2006.148.08:21:31.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.148.08:21:31.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.148.08:21:31.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:31.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:31.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:31.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:31.56#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:21:31.60#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:31.60#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.148.08:21:31.60#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:21:31.60#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:21:31.60$vc4f8/vb=3,4 2006.148.08:21:31.60#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.148.08:21:31.60#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.148.08:21:31.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:31.60#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:31.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:31.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:31.68#ibcon#[27=AT03-04\r\n] 2006.148.08:21:31.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:31.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.148.08:21:31.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.148.08:21:31.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:31.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:31.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:31.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:31.85#ibcon#[27=USB\r\n] 2006.148.08:21:31.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:31.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.148.08:21:31.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:21:31.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:21:31.90$vc4f8/vblo=4,712.99 2006.148.08:21:31.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.148.08:21:31.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.148.08:21:31.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:31.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:31.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:31.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:31.92#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:21:31.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:31.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.148.08:21:31.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:21:31.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:21:31.96$vc4f8/vb=4,4 2006.148.08:21:31.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.148.08:21:31.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.148.08:21:31.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:31.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:32.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:32.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:32.04#ibcon#[27=AT04-04\r\n] 2006.148.08:21:32.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:32.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.148.08:21:32.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.148.08:21:32.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:32.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:32.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:32.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:32.21#ibcon#[27=USB\r\n] 2006.148.08:21:32.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:32.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.148.08:21:32.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:21:32.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:21:32.24$vc4f8/vblo=5,744.99 2006.148.08:21:32.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.148.08:21:32.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.148.08:21:32.24#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:32.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:32.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:32.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:32.26#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:21:32.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:32.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.148.08:21:32.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:21:32.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:21:32.30$vc4f8/vb=5,3 2006.148.08:21:32.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.148.08:21:32.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.148.08:21:32.30#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:32.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:32.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:32.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:32.38#ibcon#[27=AT05-03\r\n] 2006.148.08:21:32.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:32.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.148.08:21:32.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.148.08:21:32.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:32.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:32.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:32.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:32.55#ibcon#[27=USB\r\n] 2006.148.08:21:32.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:32.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.148.08:21:32.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:21:32.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:21:32.58$vc4f8/vblo=6,752.99 2006.148.08:21:32.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.148.08:21:32.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.148.08:21:32.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:21:32.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:32.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:32.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:32.62#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:21:32.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:32.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.148.08:21:32.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:21:32.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:21:32.67$vc4f8/vb=6,4 2006.148.08:21:32.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.148.08:21:32.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.148.08:21:32.67#ibcon#ireg 11 cls_cnt 2 2006.148.08:21:32.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:32.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:32.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:32.72#ibcon#[27=AT06-04\r\n] 2006.148.08:21:32.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:32.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.148.08:21:32.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.148.08:21:32.75#ibcon#ireg 7 cls_cnt 0 2006.148.08:21:32.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:32.87#abcon#<5=/08 2.2 5.7 21.98 94 994.5\r\n> 2006.148.08:21:32.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:32.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:32.89#ibcon#[27=USB\r\n] 2006.148.08:21:32.89#abcon#{5=INTERFACE CLEAR} 2006.148.08:21:32.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:32.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.148.08:21:32.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:21:32.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:21:32.92$vc4f8/vabw=wide 2006.148.08:21:32.92#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.148.08:21:32.92#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.148.08:21:32.92#ibcon#ireg 8 cls_cnt 0 2006.148.08:21:32.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:21:32.92#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:21:32.92#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:21:32.94#ibcon#[25=BW32\r\n] 2006.148.08:21:32.95#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:21:32.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:21:32.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.148.08:21:32.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:21:32.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:21:32.97$vc4f8/vbbw=wide 2006.148.08:21:32.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:21:32.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:21:32.97#ibcon#ireg 8 cls_cnt 0 2006.148.08:21:32.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:21:33.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:21:33.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:21:33.06#ibcon#[27=BW32\r\n] 2006.148.08:21:33.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:21:33.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:21:33.09#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:21:33.09#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:21:33.09$4f8m12a/ifd4f 2006.148.08:21:33.09$ifd4f/lo= 2006.148.08:21:33.09$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:21:33.09$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:21:33.09$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:21:33.09$ifd4f/patch= 2006.148.08:21:33.09$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:21:33.09$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:21:33.09$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:21:33.09$4f8m12a/"form=m,16.000,1:2 2006.148.08:21:33.09$4f8m12a/"tpicd 2006.148.08:21:33.09$4f8m12a/echo=off 2006.148.08:21:33.09$4f8m12a/xlog=off 2006.148.08:21:33.09:!2006.148.08:22:30 2006.148.08:21:52.14#trakl#Source acquired 2006.148.08:21:54.14#flagr#flagr/antenna,acquired 2006.148.08:22:30.02:preob 2006.148.08:22:31.14/onsource/TRACKING 2006.148.08:22:31.14:!2006.148.08:22:40 2006.148.08:22:40.02:data_valid=on 2006.148.08:22:40.02:midob 2006.148.08:22:41.15/onsource/TRACKING 2006.148.08:22:41.15/wx/21.97,994.5,93 2006.148.08:22:41.25/cable/+6.5329E-03 2006.148.08:22:42.33/va/01,08,usb,yes,30,32 2006.148.08:22:42.34/va/02,07,usb,yes,30,32 2006.148.08:22:42.34/va/03,08,usb,yes,22,23 2006.148.08:22:42.34/va/04,07,usb,yes,31,33 2006.148.08:22:42.34/va/05,06,usb,yes,34,35 2006.148.08:22:42.34/va/06,05,usb,yes,34,34 2006.148.08:22:42.34/va/07,05,usb,yes,34,33 2006.148.08:22:42.34/va/08,05,usb,yes,36,36 2006.148.08:22:42.57/valo/01,532.99,yes,locked 2006.148.08:22:42.57/valo/02,572.99,yes,locked 2006.148.08:22:42.57/valo/03,672.99,yes,locked 2006.148.08:22:42.57/valo/04,832.99,yes,locked 2006.148.08:22:42.57/valo/05,652.99,yes,locked 2006.148.08:22:42.57/valo/06,772.99,yes,locked 2006.148.08:22:42.57/valo/07,832.99,yes,locked 2006.148.08:22:42.57/valo/08,852.99,yes,locked 2006.148.08:22:43.65/vb/01,04,usb,yes,30,28 2006.148.08:22:43.65/vb/02,04,usb,yes,32,33 2006.148.08:22:43.66/vb/03,04,usb,yes,28,32 2006.148.08:22:43.66/vb/04,04,usb,yes,29,34 2006.148.08:22:43.66/vb/05,03,usb,yes,34,39 2006.148.08:22:43.66/vb/06,04,usb,yes,29,31 2006.148.08:22:43.66/vb/07,04,usb,yes,30,30 2006.148.08:22:43.66/vb/08,03,usb,yes,35,39 2006.148.08:22:43.89/vblo/01,632.99,yes,locked 2006.148.08:22:43.89/vblo/02,640.99,yes,locked 2006.148.08:22:43.89/vblo/03,656.99,yes,locked 2006.148.08:22:43.89/vblo/04,712.99,yes,locked 2006.148.08:22:43.89/vblo/05,744.99,yes,locked 2006.148.08:22:43.89/vblo/06,752.99,yes,locked 2006.148.08:22:43.89/vblo/07,734.99,yes,locked 2006.148.08:22:43.89/vblo/08,744.99,yes,locked 2006.148.08:22:44.03/vabw/8 2006.148.08:22:44.18/vbbw/8 2006.148.08:22:44.27/xfe/off,on,15.2 2006.148.08:22:44.67/ifatt/23,28,28,28 2006.148.08:22:45.07/fmout-gps/S +4.87E-07 2006.148.08:22:45.16:!2006.148.08:23:40 2006.148.08:23:40.02:data_valid=off 2006.148.08:23:40.02:postob 2006.148.08:23:40.12/cable/+6.5292E-03 2006.148.08:23:40.13/wx/21.96,994.5,93 2006.148.08:23:41.07/fmout-gps/S +4.87E-07 2006.148.08:23:41.08:scan_name=148-0826,k06148,60 2006.148.08:23:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.148.08:23:42.13#flagr#flagr/antenna,new-source 2006.148.08:23:42.13:checkk5 2006.148.08:23:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:23:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:23:43.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:23:43.69/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:23:44.09/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0822*_20??1480822??.k5 file! 2006.148.08:23:44.47/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0822*_20??1480822??.k5 file! 2006.148.08:23:44.85/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0822*_20??1480822??.k5 file! 2006.148.08:23:45.24/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0822*_20??1480822??.k5 file! 2006.148.08:23:45.94/k5log//k5ts1_log_newline 2006.148.08:23:46.64/k5log//k5ts2_log_newline 2006.148.08:23:47.33/k5log//k5ts3_log_newline 2006.148.08:23:48.06/k5log//k5ts4_log_newline 2006.148.08:23:48.26/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:23:48.26:4f8m12a=3 2006.148.08:23:48.26$4f8m12a/echo=on 2006.148.08:23:48.26$4f8m12a/pcalon 2006.148.08:23:48.26$pcalon/"no phase cal control is implemented here 2006.148.08:23:48.26$4f8m12a/"tpicd=stop 2006.148.08:23:48.26$4f8m12a/vc4f8 2006.148.08:23:48.26$vc4f8/valo=1,532.99 2006.148.08:23:48.27#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:23:48.27#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:23:48.27#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:48.27#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:48.27#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:48.27#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:48.28#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:23:48.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:48.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:48.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:23:48.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:23:48.34$vc4f8/va=1,8 2006.148.08:23:48.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:23:48.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:23:48.34#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:48.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:48.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:48.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:48.35#ibcon#[25=AT01-08\r\n] 2006.148.08:23:48.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:48.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:48.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:23:48.38#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:48.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:48.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:48.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:48.52#ibcon#[25=USB\r\n] 2006.148.08:23:48.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:48.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:48.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:23:48.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:23:48.55$vc4f8/valo=2,572.99 2006.148.08:23:48.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:23:48.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:23:48.56#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:48.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:48.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:48.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:48.60#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:23:48.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:48.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:48.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:23:48.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:23:48.63$vc4f8/va=2,7 2006.148.08:23:48.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.08:23:48.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.08:23:48.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:48.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:48.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:48.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:48.68#ibcon#[25=AT02-07\r\n] 2006.148.08:23:48.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:48.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:48.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.08:23:48.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:48.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:48.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:48.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:48.85#ibcon#[25=USB\r\n] 2006.148.08:23:48.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:48.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:48.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:23:48.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:23:48.91$vc4f8/valo=3,672.99 2006.148.08:23:48.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.08:23:48.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.08:23:48.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:48.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:48.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:48.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:48.92#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:23:48.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:48.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:48.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:23:48.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:23:48.96$vc4f8/va=3,8 2006.148.08:23:48.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.08:23:48.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.08:23:48.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:48.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:49.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:49.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:49.04#ibcon#[25=AT03-08\r\n] 2006.148.08:23:49.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:49.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:49.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.08:23:49.09#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:49.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:49.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:49.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:49.22#ibcon#[25=USB\r\n] 2006.148.08:23:49.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:49.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:49.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:23:49.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:23:49.25$vc4f8/valo=4,832.99 2006.148.08:23:49.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:23:49.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:23:49.26#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:49.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:49.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:49.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:49.27#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:23:49.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:49.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:49.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:23:49.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:23:49.31$vc4f8/va=4,7 2006.148.08:23:49.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:23:49.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:23:49.32#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:49.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:49.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:49.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:49.38#ibcon#[25=AT04-07\r\n] 2006.148.08:23:49.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:49.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:49.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:23:49.41#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:49.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:49.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:49.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:49.55#ibcon#[25=USB\r\n] 2006.148.08:23:49.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:49.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:49.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:23:49.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:23:49.58$vc4f8/valo=5,652.99 2006.148.08:23:49.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:23:49.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:23:49.59#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:49.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:49.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:49.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:49.60#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:23:49.64#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:49.64#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:49.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:23:49.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:23:49.64$vc4f8/va=5,6 2006.148.08:23:49.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.08:23:49.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.08:23:49.65#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:49.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:49.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:49.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:49.71#ibcon#[25=AT05-06\r\n] 2006.148.08:23:49.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:49.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:49.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.08:23:49.74#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:49.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:49.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:49.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:49.88#ibcon#[25=USB\r\n] 2006.148.08:23:49.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:49.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:49.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:23:49.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:23:49.91$vc4f8/valo=6,772.99 2006.148.08:23:49.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:23:49.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:23:49.92#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:49.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:49.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:49.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:49.93#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:23:49.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:49.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:49.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:23:49.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:23:49.97$vc4f8/va=6,5 2006.148.08:23:49.98#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.148.08:23:49.98#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.148.08:23:49.98#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:49.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:50.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:50.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:50.04#ibcon#[25=AT06-05\r\n] 2006.148.08:23:50.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:50.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:50.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.148.08:23:50.07#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:50.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:23:50.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:23:50.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:23:50.21#ibcon#[25=USB\r\n] 2006.148.08:23:50.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:23:50.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.148.08:23:50.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:23:50.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:23:50.24$vc4f8/valo=7,832.99 2006.148.08:23:50.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.148.08:23:50.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.148.08:23:50.25#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:50.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:23:50.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:23:50.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:23:50.26#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:23:50.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:23:50.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.148.08:23:50.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.148.08:23:50.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.148.08:23:50.30$vc4f8/va=7,5 2006.148.08:23:50.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.148.08:23:50.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.148.08:23:50.31#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:50.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:23:50.35#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:23:50.35#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:23:50.37#ibcon#[25=AT07-05\r\n] 2006.148.08:23:50.40#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:23:50.40#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.148.08:23:50.40#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.148.08:23:50.40#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:50.40#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:23:50.52#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:23:50.52#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:23:50.54#ibcon#[25=USB\r\n] 2006.148.08:23:50.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:23:50.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.148.08:23:50.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.148.08:23:50.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.148.08:23:50.57$vc4f8/valo=8,852.99 2006.148.08:23:50.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.148.08:23:50.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.148.08:23:50.58#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:50.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:23:50.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:23:50.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:23:50.59#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:23:50.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:23:50.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.148.08:23:50.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.148.08:23:50.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.148.08:23:50.63$vc4f8/va=8,5 2006.148.08:23:50.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.148.08:23:50.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.148.08:23:50.64#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:50.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:23:50.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:23:50.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:23:50.70#ibcon#[25=AT08-05\r\n] 2006.148.08:23:50.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:23:50.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.148.08:23:50.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.148.08:23:50.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:50.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:23:50.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:23:50.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:23:50.87#ibcon#[25=USB\r\n] 2006.148.08:23:50.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:23:50.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.148.08:23:50.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.148.08:23:50.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.148.08:23:50.90$vc4f8/vblo=1,632.99 2006.148.08:23:50.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.148.08:23:50.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.148.08:23:50.91#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:50.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:23:50.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:23:50.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:23:50.92#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:23:50.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:23:50.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.148.08:23:50.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.148.08:23:50.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.148.08:23:50.96$vc4f8/vb=1,4 2006.148.08:23:50.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.148.08:23:50.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.148.08:23:50.97#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:50.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:23:50.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:23:50.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:23:50.98#ibcon#[27=AT01-04\r\n] 2006.148.08:23:51.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:23:51.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.148.08:23:51.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.148.08:23:51.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:51.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:23:51.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:23:51.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:23:51.15#ibcon#[27=USB\r\n] 2006.148.08:23:51.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:23:51.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.148.08:23:51.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.148.08:23:51.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.148.08:23:51.18$vc4f8/vblo=2,640.99 2006.148.08:23:51.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.148.08:23:51.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.148.08:23:51.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:51.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:51.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:51.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:51.20#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:23:51.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:51.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.148.08:23:51.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.148.08:23:51.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.148.08:23:51.24$vc4f8/vb=2,4 2006.148.08:23:51.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.148.08:23:51.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.148.08:23:51.25#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:51.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:51.29#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:51.29#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:51.31#ibcon#[27=AT02-04\r\n] 2006.148.08:23:51.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:51.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.148.08:23:51.34#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.148.08:23:51.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:51.34#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:51.46#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:51.46#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:51.48#ibcon#[27=USB\r\n] 2006.148.08:23:51.51#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:51.51#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.148.08:23:51.51#ibcon#about to clear, iclass 5 cls_cnt 0 2006.148.08:23:51.51#ibcon#cleared, iclass 5 cls_cnt 0 2006.148.08:23:51.51$vc4f8/vblo=3,656.99 2006.148.08:23:51.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.148.08:23:51.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.148.08:23:51.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:51.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:51.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:51.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:51.54#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:23:51.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:51.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.148.08:23:51.57#ibcon#about to clear, iclass 7 cls_cnt 0 2006.148.08:23:51.57#ibcon#cleared, iclass 7 cls_cnt 0 2006.148.08:23:51.57$vc4f8/vb=3,4 2006.148.08:23:51.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.148.08:23:51.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.148.08:23:51.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:51.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:51.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:51.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:51.65#ibcon#[27=AT03-04\r\n] 2006.148.08:23:51.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:51.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.148.08:23:51.68#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.148.08:23:51.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:51.68#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:51.80#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:51.80#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:51.82#ibcon#[27=USB\r\n] 2006.148.08:23:51.85#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:51.85#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.148.08:23:51.85#ibcon#about to clear, iclass 11 cls_cnt 0 2006.148.08:23:51.85#ibcon#cleared, iclass 11 cls_cnt 0 2006.148.08:23:51.85$vc4f8/vblo=4,712.99 2006.148.08:23:51.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.148.08:23:51.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.148.08:23:51.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:51.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:51.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:51.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:51.87#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:23:51.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:51.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.148.08:23:51.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.148.08:23:51.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.148.08:23:51.91$vc4f8/vb=4,4 2006.148.08:23:51.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.148.08:23:51.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.148.08:23:51.92#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:51.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:51.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:51.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:51.98#ibcon#[27=AT04-04\r\n] 2006.148.08:23:52.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:52.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.148.08:23:52.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.148.08:23:52.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:52.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:52.14#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:52.14#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:52.15#ibcon#[27=USB\r\n] 2006.148.08:23:52.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:52.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.148.08:23:52.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.148.08:23:52.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.148.08:23:52.18$vc4f8/vblo=5,744.99 2006.148.08:23:52.19#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.148.08:23:52.19#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.148.08:23:52.19#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:52.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:52.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:52.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:52.20#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:23:52.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:52.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.148.08:23:52.24#ibcon#about to clear, iclass 17 cls_cnt 0 2006.148.08:23:52.24#ibcon#cleared, iclass 17 cls_cnt 0 2006.148.08:23:52.24$vc4f8/vb=5,3 2006.148.08:23:52.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.148.08:23:52.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.148.08:23:52.25#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:52.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:52.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:52.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:52.31#ibcon#[27=AT05-03\r\n] 2006.148.08:23:52.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:52.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.148.08:23:52.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.148.08:23:52.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:52.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:52.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:52.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:52.48#ibcon#[27=USB\r\n] 2006.148.08:23:52.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:52.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.148.08:23:52.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.148.08:23:52.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.148.08:23:52.54$vc4f8/vblo=6,752.99 2006.148.08:23:52.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.148.08:23:52.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.148.08:23:52.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:23:52.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:52.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:52.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:52.55#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:23:52.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:52.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.148.08:23:52.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.148.08:23:52.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.148.08:23:52.59$vc4f8/vb=6,4 2006.148.08:23:52.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.148.08:23:52.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.148.08:23:52.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:23:52.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:52.65#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:52.65#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:52.67#ibcon#[27=AT06-04\r\n] 2006.148.08:23:52.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:52.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.148.08:23:52.70#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.148.08:23:52.70#ibcon#ireg 7 cls_cnt 0 2006.148.08:23:52.70#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:52.82#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:52.82#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:52.84#ibcon#[27=USB\r\n] 2006.148.08:23:52.87#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:52.87#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.148.08:23:52.87#ibcon#about to clear, iclass 23 cls_cnt 0 2006.148.08:23:52.87#ibcon#cleared, iclass 23 cls_cnt 0 2006.148.08:23:52.87$vc4f8/vabw=wide 2006.148.08:23:52.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.148.08:23:52.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.148.08:23:52.88#ibcon#ireg 8 cls_cnt 0 2006.148.08:23:52.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:52.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:52.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:52.89#ibcon#[25=BW32\r\n] 2006.148.08:23:52.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:52.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.148.08:23:52.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.148.08:23:52.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.148.08:23:52.92$vc4f8/vbbw=wide 2006.148.08:23:52.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.148.08:23:52.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.148.08:23:52.93#ibcon#ireg 8 cls_cnt 0 2006.148.08:23:52.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:23:52.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:23:52.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:23:53.00#ibcon#[27=BW32\r\n] 2006.148.08:23:53.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:23:53.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.148.08:23:53.03#ibcon#about to clear, iclass 27 cls_cnt 0 2006.148.08:23:53.03#ibcon#cleared, iclass 27 cls_cnt 0 2006.148.08:23:53.04$4f8m12a/ifd4f 2006.148.08:23:53.04$ifd4f/lo= 2006.148.08:23:53.04$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:23:53.04$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:23:53.04$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:23:53.04$ifd4f/patch= 2006.148.08:23:53.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:23:53.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:23:53.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:23:53.04$4f8m12a/"form=m,16.000,1:2 2006.148.08:23:53.04$4f8m12a/"tpicd 2006.148.08:23:53.04$4f8m12a/echo=off 2006.148.08:23:53.04$4f8m12a/xlog=off 2006.148.08:23:53.04:!2006.148.08:26:00 2006.148.08:23:58.13#trakl#Source acquired 2006.148.08:23:58.14#flagr#flagr/antenna,acquired 2006.148.08:26:00.01:preob 2006.148.08:26:01.14/onsource/TRACKING 2006.148.08:26:01.14:!2006.148.08:26:10 2006.148.08:26:10.00:data_valid=on 2006.148.08:26:10.00:midob 2006.148.08:26:10.14/onsource/TRACKING 2006.148.08:26:10.15/wx/21.95,994.4,92 2006.148.08:26:10.25/cable/+6.5325E-03 2006.148.08:26:11.34/va/01,08,usb,yes,32,33 2006.148.08:26:11.34/va/02,07,usb,yes,32,33 2006.148.08:26:11.34/va/03,08,usb,yes,24,24 2006.148.08:26:11.34/va/04,07,usb,yes,32,35 2006.148.08:26:11.34/va/05,06,usb,yes,36,38 2006.148.08:26:11.34/va/06,05,usb,yes,36,36 2006.148.08:26:11.34/va/07,05,usb,yes,36,36 2006.148.08:26:11.34/va/08,05,usb,yes,39,38 2006.148.08:26:11.57/valo/01,532.99,yes,locked 2006.148.08:26:11.57/valo/02,572.99,yes,locked 2006.148.08:26:11.57/valo/03,672.99,yes,locked 2006.148.08:26:11.57/valo/04,832.99,yes,locked 2006.148.08:26:11.57/valo/05,652.99,yes,locked 2006.148.08:26:11.57/valo/06,772.99,yes,locked 2006.148.08:26:11.57/valo/07,832.99,yes,locked 2006.148.08:26:11.57/valo/08,852.99,yes,locked 2006.148.08:26:12.66/vb/01,04,usb,yes,30,29 2006.148.08:26:12.66/vb/02,04,usb,yes,35,34 2006.148.08:26:12.66/vb/03,04,usb,yes,28,35 2006.148.08:26:12.66/vb/04,04,usb,yes,29,32 2006.148.08:26:12.66/vb/05,03,usb,yes,35,39 2006.148.08:26:12.66/vb/06,04,usb,yes,29,32 2006.148.08:26:12.66/vb/07,04,usb,yes,31,31 2006.148.08:26:12.66/vb/08,03,usb,yes,35,39 2006.148.08:26:12.90/vblo/01,632.99,yes,locked 2006.148.08:26:12.90/vblo/02,640.99,yes,locked 2006.148.08:26:12.90/vblo/03,656.99,yes,locked 2006.148.08:26:12.90/vblo/04,712.99,yes,locked 2006.148.08:26:12.90/vblo/05,744.99,yes,locked 2006.148.08:26:12.90/vblo/06,752.99,yes,locked 2006.148.08:26:12.90/vblo/07,734.99,yes,locked 2006.148.08:26:12.90/vblo/08,744.99,yes,locked 2006.148.08:26:13.05/vabw/8 2006.148.08:26:13.20/vbbw/8 2006.148.08:26:13.29/xfe/off,on,14.7 2006.148.08:26:13.69/ifatt/23,28,28,28 2006.148.08:26:14.07/fmout-gps/S +4.88E-07 2006.148.08:26:14.16:!2006.148.08:27:10 2006.148.08:27:10.01:data_valid=off 2006.148.08:27:10.02:postob 2006.148.08:27:10.11/cable/+6.5316E-03 2006.148.08:27:10.11/wx/21.94,994.4,92 2006.148.08:27:10.20/fmout-gps/S +4.88E-07 2006.148.08:27:10.20:scan_name=148-0828,k06148,60 2006.148.08:27:10.21:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.148.08:27:12.14#flagr#flagr/antenna,new-source 2006.148.08:27:12.15:checkk5 2006.148.08:27:12.53/chk_autoobs//k5ts1/ autoobs is running! 2006.148.08:27:12.92/chk_autoobs//k5ts2/ autoobs is running! 2006.148.08:27:13.30/chk_autoobs//k5ts3/ autoobs is running! 2006.148.08:27:13.68/chk_autoobs//k5ts4/ autoobs is running! 2006.148.08:27:14.05/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0826*_20??1480826??.k5 file! 2006.148.08:27:14.43/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0826*_20??1480826??.k5 file! 2006.148.08:27:14.81/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0826*_20??1480826??.k5 file! 2006.148.08:27:15.23/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0826*_20??1480826??.k5 file! 2006.148.08:27:15.93/k5log//k5ts1_log_newline 2006.148.08:27:16.62/k5log//k5ts2_log_newline 2006.148.08:27:17.31/k5log//k5ts3_log_newline 2006.148.08:27:18.01/k5log//k5ts4_log_newline 2006.148.08:27:18.17/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:27:18.17:4f8m12a=3 2006.148.08:27:18.17$4f8m12a/echo=on 2006.148.08:27:18.17$4f8m12a/pcalon 2006.148.08:27:18.17$pcalon/"no phase cal control is implemented here 2006.148.08:27:18.17$4f8m12a/"tpicd=stop 2006.148.08:27:18.17$4f8m12a/vc4f8 2006.148.08:27:18.17$vc4f8/valo=1,532.99 2006.148.08:27:18.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:27:18.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:27:18.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:18.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:18.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:18.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:18.22#ibcon#[26=FRQ=01,532.99\r\n] 2006.148.08:27:18.27#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:18.27#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:18.27#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:27:18.27#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:27:18.27$vc4f8/va=1,8 2006.148.08:27:18.27#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.08:27:18.27#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.08:27:18.27#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:18.27#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:18.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:18.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:18.31#ibcon#[25=AT01-08\r\n] 2006.148.08:27:18.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:18.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:18.34#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.08:27:18.34#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:18.34#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:18.46#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:18.46#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:18.48#ibcon#[25=USB\r\n] 2006.148.08:27:18.51#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:18.51#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:18.51#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:27:18.51#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:27:18.51$vc4f8/valo=2,572.99 2006.148.08:27:18.51#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.08:27:18.51#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.08:27:18.51#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:18.51#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:18.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:18.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:18.55#ibcon#[26=FRQ=02,572.99\r\n] 2006.148.08:27:18.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:18.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:18.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:27:18.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:27:18.59$vc4f8/va=2,7 2006.148.08:27:18.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.08:27:18.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.08:27:18.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:18.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:18.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:18.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:18.65#ibcon#[25=AT02-07\r\n] 2006.148.08:27:18.67#abcon#<5=/08 2.2 7.2 21.93 93 994.4\r\n> 2006.148.08:27:18.68#abcon#{5=INTERFACE CLEAR} 2006.148.08:27:18.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:18.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:18.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.08:27:18.68#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:18.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:18.76#abcon#[5=S1D000X0/0*\r\n] 2006.148.08:27:18.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:18.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:18.82#ibcon#[25=USB\r\n] 2006.148.08:27:18.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:18.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:18.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:27:18.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:27:18.86$vc4f8/valo=3,672.99 2006.148.08:27:18.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.08:27:18.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.08:27:18.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:18.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:18.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:18.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:18.88#ibcon#[26=FRQ=03,672.99\r\n] 2006.148.08:27:18.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:18.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:18.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:27:18.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:27:18.94$vc4f8/va=3,8 2006.148.08:27:18.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.08:27:18.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.08:27:18.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:18.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:18.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:18.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:18.99#ibcon#[25=AT03-08\r\n] 2006.148.08:27:19.04#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:19.04#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:19.04#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.08:27:19.04#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:19.04#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:19.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:19.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:19.17#ibcon#[25=USB\r\n] 2006.148.08:27:19.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:19.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:19.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:27:19.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:27:19.20$vc4f8/valo=4,832.99 2006.148.08:27:19.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.08:27:19.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.08:27:19.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:19.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:19.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:19.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:19.22#ibcon#[26=FRQ=04,832.99\r\n] 2006.148.08:27:19.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:19.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:19.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:27:19.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:27:19.26$vc4f8/va=4,7 2006.148.08:27:19.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.08:27:19.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.08:27:19.26#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:19.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:19.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:19.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:19.34#ibcon#[25=AT04-07\r\n] 2006.148.08:27:19.37#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:19.37#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:19.37#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.08:27:19.37#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:19.37#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:19.49#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:19.49#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:19.51#ibcon#[25=USB\r\n] 2006.148.08:27:19.54#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:19.54#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:19.54#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:27:19.54#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:27:19.54$vc4f8/valo=5,652.99 2006.148.08:27:19.54#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:27:19.54#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:27:19.54#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:19.54#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:19.54#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:19.54#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:19.56#ibcon#[26=FRQ=05,652.99\r\n] 2006.148.08:27:19.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:19.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:19.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:27:19.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:27:19.60$vc4f8/va=5,6 2006.148.08:27:19.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.08:27:19.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.08:27:19.60#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:19.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:19.66#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:19.66#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:19.68#ibcon#[25=AT05-06\r\n] 2006.148.08:27:19.71#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:19.71#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:19.71#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.08:27:19.71#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:19.71#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:19.83#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:19.83#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:19.85#ibcon#[25=USB\r\n] 2006.148.08:27:19.88#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:19.88#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:19.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:27:19.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:27:19.88$vc4f8/valo=6,772.99 2006.148.08:27:19.88#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:27:19.88#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:27:19.88#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:19.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:19.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:19.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:19.90#ibcon#[26=FRQ=06,772.99\r\n] 2006.148.08:27:19.94#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:19.94#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:19.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:27:19.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:27:19.94$vc4f8/va=6,5 2006.148.08:27:19.94#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.148.08:27:19.94#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.148.08:27:19.94#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:19.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:20.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:20.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:20.02#ibcon#[25=AT06-05\r\n] 2006.148.08:27:20.05#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:20.05#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:20.05#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.148.08:27:20.05#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:20.05#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:27:20.17#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:27:20.17#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:27:20.19#ibcon#[25=USB\r\n] 2006.148.08:27:20.22#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:27:20.22#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.148.08:27:20.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:27:20.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:27:20.22$vc4f8/valo=7,832.99 2006.148.08:27:20.22#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.148.08:27:20.22#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.148.08:27:20.22#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:20.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:27:20.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:27:20.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:27:20.24#ibcon#[26=FRQ=07,832.99\r\n] 2006.148.08:27:20.28#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:27:20.28#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.148.08:27:20.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.148.08:27:20.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.148.08:27:20.28$vc4f8/va=7,5 2006.148.08:27:20.28#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.148.08:27:20.28#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.148.08:27:20.28#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:20.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:27:20.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:27:20.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:27:20.36#ibcon#[25=AT07-05\r\n] 2006.148.08:27:20.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:27:20.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.148.08:27:20.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.148.08:27:20.39#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:20.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:27:20.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:27:20.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:27:20.53#ibcon#[25=USB\r\n] 2006.148.08:27:20.56#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:27:20.56#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.148.08:27:20.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.148.08:27:20.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.148.08:27:20.56$vc4f8/valo=8,852.99 2006.148.08:27:20.56#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.148.08:27:20.56#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.148.08:27:20.56#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:20.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:27:20.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:27:20.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:27:20.58#ibcon#[26=FRQ=08,852.99\r\n] 2006.148.08:27:20.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:27:20.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.148.08:27:20.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.148.08:27:20.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.148.08:27:20.63$vc4f8/va=8,5 2006.148.08:27:20.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.148.08:27:20.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.148.08:27:20.63#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:20.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:27:20.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:27:20.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:27:20.70#ibcon#[25=AT08-05\r\n] 2006.148.08:27:20.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:27:20.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.148.08:27:20.73#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.148.08:27:20.73#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:20.73#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:27:20.85#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:27:20.85#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:27:20.87#ibcon#[25=USB\r\n] 2006.148.08:27:20.90#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:27:20.90#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.148.08:27:20.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.148.08:27:20.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.148.08:27:20.90$vc4f8/vblo=1,632.99 2006.148.08:27:20.90#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.148.08:27:20.90#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.148.08:27:20.90#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:20.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:20.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:20.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:20.92#ibcon#[28=FRQ=01,632.99\r\n] 2006.148.08:27:20.96#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:20.96#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.148.08:27:20.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.148.08:27:20.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.148.08:27:20.96$vc4f8/vb=1,4 2006.148.08:27:20.96#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.148.08:27:20.96#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.148.08:27:20.96#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:20.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:20.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:20.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:20.98#ibcon#[27=AT01-04\r\n] 2006.148.08:27:21.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:21.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.148.08:27:21.01#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.148.08:27:21.01#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:21.01#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:21.13#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:21.13#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:21.15#ibcon#[27=USB\r\n] 2006.148.08:27:21.18#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:21.18#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.148.08:27:21.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.148.08:27:21.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.148.08:27:21.18$vc4f8/vblo=2,640.99 2006.148.08:27:21.18#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.148.08:27:21.18#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.148.08:27:21.18#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:21.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:21.18#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:21.18#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:21.20#ibcon#[28=FRQ=02,640.99\r\n] 2006.148.08:27:21.24#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:21.24#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.148.08:27:21.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.148.08:27:21.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.148.08:27:21.24$vc4f8/vb=2,4 2006.148.08:27:21.24#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.148.08:27:21.24#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.148.08:27:21.24#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:21.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:21.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:21.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:21.32#ibcon#[27=AT02-04\r\n] 2006.148.08:27:21.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:21.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.148.08:27:21.35#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.148.08:27:21.35#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:21.35#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:21.47#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:21.47#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:21.49#ibcon#[27=USB\r\n] 2006.148.08:27:21.52#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:21.52#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.148.08:27:21.52#ibcon#about to clear, iclass 6 cls_cnt 0 2006.148.08:27:21.52#ibcon#cleared, iclass 6 cls_cnt 0 2006.148.08:27:21.52$vc4f8/vblo=3,656.99 2006.148.08:27:21.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.148.08:27:21.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.148.08:27:21.52#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:21.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:27:21.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:27:21.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:27:21.54#ibcon#[28=FRQ=03,656.99\r\n] 2006.148.08:27:21.58#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:27:21.58#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.148.08:27:21.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.148.08:27:21.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.148.08:27:21.58$vc4f8/vb=3,4 2006.148.08:27:21.58#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.148.08:27:21.58#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.148.08:27:21.58#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:21.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:27:21.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:27:21.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:27:21.66#ibcon#[27=AT03-04\r\n] 2006.148.08:27:21.69#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:27:21.69#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.148.08:27:21.69#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.148.08:27:21.69#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:21.69#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:27:21.81#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:27:21.81#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:27:21.83#ibcon#[27=USB\r\n] 2006.148.08:27:21.86#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:27:21.86#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.148.08:27:21.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.148.08:27:21.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.148.08:27:21.86$vc4f8/vblo=4,712.99 2006.148.08:27:21.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.148.08:27:21.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.148.08:27:21.86#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:21.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:21.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:21.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:21.88#ibcon#[28=FRQ=04,712.99\r\n] 2006.148.08:27:21.92#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:21.92#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.148.08:27:21.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.148.08:27:21.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.148.08:27:21.92$vc4f8/vb=4,4 2006.148.08:27:21.92#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.148.08:27:21.92#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.148.08:27:21.92#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:21.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:21.98#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:21.98#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:22.00#ibcon#[27=AT04-04\r\n] 2006.148.08:27:22.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:22.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.148.08:27:22.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.148.08:27:22.03#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:22.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:22.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:22.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:22.17#ibcon#[27=USB\r\n] 2006.148.08:27:22.20#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:22.20#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.148.08:27:22.20#ibcon#about to clear, iclass 16 cls_cnt 0 2006.148.08:27:22.20#ibcon#cleared, iclass 16 cls_cnt 0 2006.148.08:27:22.20$vc4f8/vblo=5,744.99 2006.148.08:27:22.20#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.148.08:27:22.20#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.148.08:27:22.20#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:22.20#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:22.20#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:22.20#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:22.22#ibcon#[28=FRQ=05,744.99\r\n] 2006.148.08:27:22.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:22.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.148.08:27:22.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.148.08:27:22.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.148.08:27:22.29$vc4f8/vb=5,3 2006.148.08:27:22.29#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.148.08:27:22.29#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.148.08:27:22.29#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:22.29#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:22.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:22.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:22.33#ibcon#[27=AT05-03\r\n] 2006.148.08:27:22.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:22.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.148.08:27:22.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.148.08:27:22.36#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:22.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:22.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:22.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:22.50#ibcon#[27=USB\r\n] 2006.148.08:27:22.53#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:22.53#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.148.08:27:22.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.148.08:27:22.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.148.08:27:22.53$vc4f8/vblo=6,752.99 2006.148.08:27:22.53#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.148.08:27:22.53#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.148.08:27:22.53#ibcon#ireg 17 cls_cnt 0 2006.148.08:27:22.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:22.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:22.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:22.55#ibcon#[28=FRQ=06,752.99\r\n] 2006.148.08:27:22.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:22.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.148.08:27:22.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.148.08:27:22.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.148.08:27:22.59$vc4f8/vb=6,4 2006.148.08:27:22.59#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.148.08:27:22.59#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.148.08:27:22.59#ibcon#ireg 11 cls_cnt 2 2006.148.08:27:22.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:22.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:22.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:22.67#ibcon#[27=AT06-04\r\n] 2006.148.08:27:22.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:22.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.148.08:27:22.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.148.08:27:22.70#ibcon#ireg 7 cls_cnt 0 2006.148.08:27:22.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:22.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:22.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:22.84#ibcon#[27=USB\r\n] 2006.148.08:27:22.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:22.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.148.08:27:22.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.148.08:27:22.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.148.08:27:22.87$vc4f8/vabw=wide 2006.148.08:27:22.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.148.08:27:22.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.148.08:27:22.87#ibcon#ireg 8 cls_cnt 0 2006.148.08:27:22.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:22.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:22.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:22.89#ibcon#[25=BW32\r\n] 2006.148.08:27:22.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:22.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.148.08:27:22.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.148.08:27:22.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.148.08:27:22.93$vc4f8/vbbw=wide 2006.148.08:27:22.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.148.08:27:22.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.148.08:27:22.93#ibcon#ireg 8 cls_cnt 0 2006.148.08:27:22.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:27:22.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:27:22.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:27:23.00#ibcon#[27=BW32\r\n] 2006.148.08:27:23.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:27:23.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.148.08:27:23.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.148.08:27:23.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.148.08:27:23.03$4f8m12a/ifd4f 2006.148.08:27:23.03$ifd4f/lo= 2006.148.08:27:23.03$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.148.08:27:23.03$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.148.08:27:23.03$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.148.08:27:23.03$ifd4f/patch= 2006.148.08:27:23.04$ifd4f/patch=lo1,a1,a2,a3,a4 2006.148.08:27:23.04$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.148.08:27:23.04$ifd4f/patch=lo3,a5,a6,a7,a8 2006.148.08:27:23.04$4f8m12a/"form=m,16.000,1:2 2006.148.08:27:23.04$4f8m12a/"tpicd 2006.148.08:27:23.04$4f8m12a/echo=off 2006.148.08:27:23.04$4f8m12a/xlog=off 2006.148.08:27:23.04:!2006.148.08:28:30 2006.148.08:28:03.14#trakl#Source acquired 2006.148.08:28:04.14#flagr#flagr/antenna,acquired 2006.148.08:28:30.01:preob 2006.148.08:28:31.14/onsource/TRACKING 2006.148.08:28:31.14:!2006.148.08:28:40 2006.148.08:28:40.00:data_valid=on 2006.148.08:28:40.00:midob 2006.148.08:28:40.14/onsource/TRACKING 2006.148.08:28:40.14/wx/21.93,994.4,93 2006.148.08:28:40.23/cable/+6.5323E-03 2006.148.08:28:41.32/va/01,08,usb,yes,28,30 2006.148.08:28:41.32/va/02,07,usb,yes,28,30 2006.148.08:28:41.32/va/03,08,usb,yes,21,21 2006.148.08:28:41.32/va/04,07,usb,yes,29,31 2006.148.08:28:41.32/va/05,06,usb,yes,31,33 2006.148.08:28:41.32/va/06,05,usb,yes,32,31 2006.148.08:28:41.32/va/07,05,usb,yes,32,31 2006.148.08:28:41.32/va/08,05,usb,yes,34,33 2006.148.08:28:41.55/valo/01,532.99,yes,locked 2006.148.08:28:41.55/valo/02,572.99,yes,locked 2006.148.08:28:41.55/valo/03,672.99,yes,locked 2006.148.08:28:41.55/valo/04,832.99,yes,locked 2006.148.08:28:41.55/valo/05,652.99,yes,locked 2006.148.08:28:41.55/valo/06,772.99,yes,locked 2006.148.08:28:41.55/valo/07,832.99,yes,locked 2006.148.08:28:41.55/valo/08,852.99,yes,locked 2006.148.08:28:42.64/vb/01,04,usb,yes,29,27 2006.148.08:28:42.64/vb/02,04,usb,yes,30,32 2006.148.08:28:42.64/vb/03,04,usb,yes,27,30 2006.148.08:28:42.64/vb/04,04,usb,yes,28,31 2006.148.08:28:42.64/vb/05,03,usb,yes,33,37 2006.148.08:28:42.64/vb/06,04,usb,yes,27,30 2006.148.08:28:42.64/vb/07,04,usb,yes,29,29 2006.148.08:28:42.64/vb/08,03,usb,yes,33,37 2006.148.08:28:42.88/vblo/01,632.99,yes,locked 2006.148.08:28:42.88/vblo/02,640.99,yes,locked 2006.148.08:28:42.88/vblo/03,656.99,yes,locked 2006.148.08:28:42.88/vblo/04,712.99,yes,locked 2006.148.08:28:42.88/vblo/05,744.99,yes,locked 2006.148.08:28:42.88/vblo/06,752.99,yes,locked 2006.148.08:28:42.88/vblo/07,734.99,yes,locked 2006.148.08:28:42.88/vblo/08,744.99,yes,locked 2006.148.08:28:43.03/vabw/8 2006.148.08:28:43.18/vbbw/8 2006.148.08:28:43.27/xfe/off,on,15.2 2006.148.08:28:43.65/ifatt/23,28,28,28 2006.148.08:28:44.07/fmout-gps/S +4.89E-07 2006.148.08:28:44.12:!2006.148.08:29:40 2006.148.08:29:40.01:data_valid=off 2006.148.08:29:40.02:postob 2006.148.08:29:40.20/cable/+6.5322E-03 2006.148.08:29:40.21/wx/21.94,994.4,93 2006.148.08:29:40.28/fmout-gps/S +4.89E-07 2006.148.08:29:40.29:checkk5last 2006.148.08:29:40.29&checkk5last/chk_obsdata=1 2006.148.08:29:40.30&checkk5last/chk_obsdata=2 2006.148.08:29:40.30&checkk5last/chk_obsdata=3 2006.148.08:29:40.30&checkk5last/chk_obsdata=4 2006.148.08:29:40.31&checkk5last/k5log=1 2006.148.08:29:40.31&checkk5last/k5log=2 2006.148.08:29:40.32&checkk5last/k5log=3 2006.148.08:29:40.32&checkk5last/k5log=4 2006.148.08:29:40.33&checkk5last/obsinfo 2006.148.08:29:40.72/chk_obsdata//k5ts1?ERROR: no k06148_ts1_148-0828*_20??1480828??.k5 file! 2006.148.08:29:41.10/chk_obsdata//k5ts2?ERROR: no k06148_ts2_148-0828*_20??1480828??.k5 file! 2006.148.08:29:41.49/chk_obsdata//k5ts3?ERROR: no k06148_ts3_148-0828*_20??1480828??.k5 file! 2006.148.08:29:41.86/chk_obsdata//k5ts4?ERROR: no k06148_ts4_148-0828*_20??1480828??.k5 file! 2006.148.08:29:42.55/k5log//k5ts1_log_newline 2006.148.08:29:43.26/k5log//k5ts2_log_newline 2006.148.08:29:43.95/k5log//k5ts3_log_newline 2006.148.08:29:44.65/k5log//k5ts4_log_newline 2006.148.08:29:44.81/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.148.08:29:44.81:sched_end 2006.148.08:29:44.81&sched_end/stopcheck 2006.148.08:29:44.81&stopcheck/sy=killall check_fsrun.pl 2006.148.08:29:44.81&stopcheck/" sy=killall chmem.sh 2006.148.08:29:44.91:source=idle 2006.148.08:29:45.14#flagr#flagr/antenna,new-source 2006.148.08:29:45.15:stow 2006.148.08:29:45.15&stow/source=idle 2006.148.08:29:45.16&stow/"this is stow command. 2006.148.08:29:45.16&stow/antenna=m3 2006.148.08:29:49.01:!+10m 2006.148.08:39:49.03:standby 2006.148.08:39:49.03&standby/"this is standby command. 2006.148.08:39:49.04&standby/antenna=m0 2006.148.08:39:50.01:sy=cp /usr2/log/k06148ts.log /usr2/log_backup/ 2006.148.08:39:50.05:*end of schedule