2006.146.08:18:04.91;Log Opened: Mark IV Field System Version 9.7.7 2006.146.08:18:04.91;location,TSUKUB32,-140.09,36.10,61.0 2006.146.08:18:04.91;horizon1,0.,5.,360. 2006.146.08:18:04.91;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.146.08:18:04.91;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.146.08:18:04.91;drivev11,330,270,no 2006.146.08:18:04.91;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.146.08:18:04.91;drivev13,15.000,268,10.000,10.000,10.000 2006.146.08:18:04.91;drivev21,330,270,no 2006.146.08:18:04.91;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.146.08:18:04.91;drivev23,15.000,268,10.000,10.000,10.000 2006.146.08:18:04.91;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.146.08:18:04.91;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.146.08:18:04.91;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.146.08:18:04.91;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.146.08:18:04.91;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.146.08:18:04.91;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.146.08:18:04.91;time,-0.364,101.533,rate 2006.146.08:18:04.91;flagr,200 2006.146.08:18:04.91:" K06147 2006 TSUKUB32 T Ts 2006.146.08:18:04.91:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.146.08:18:04.91:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.146.08:18:04.91:" 108 TSUKUB32 14 17400 2006.146.08:18:04.91:" drudg version 050216 compiled under FS 9.7.07 2006.146.08:18:04.91:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.146.08:18:04.91:exper_initi 2006.146.08:18:04.91&exper_initi/proc_library 2006.146.08:18:04.91&exper_initi/sched_initi 2006.146.08:18:04.91:!2006.147.07:19:50 2006.146.08:18:04.91&proc_library/" k06147 tsukub32 ts 2006.146.08:18:04.91&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.146.08:18:04.91&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.146.08:18:04.91&sched_initi/startcheck 2006.146.08:18:04.91&startcheck/sy=check_fsrun.pl & 2006.146.08:18:04.91&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.146.08:18:15.10;cable 2006.146.08:18:15.21/cable/+6.5370E-03 2006.146.08:18:55.90;cablelong 2006.146.08:18:56.01/cablelong/+7.0881E-03 2006.146.08:18:58.04;cablediff 2006.146.08:18:58.05/cablediff/551.1e-6,+ 2006.146.08:19:43.22;cable 2006.146.08:19:43.28/cable/+6.5388E-03 2006.146.08:20:08.51;wx 2006.146.08:20:08.51/wx/19.89,1017.8,72 2006.146.08:20:20.70;"Sky is cloudy. 2006.146.08:20:25.38;xfe 2006.146.08:20:25.46/xfe/off,on,15.2 2006.146.08:20:35.07;clockoff 2006.146.08:20:35.07&clockoff/"gps-fmout=1p 2006.146.08:20:35.07&clockoff/fmout-gps=1p 2006.146.08:20:36.07/fmout-gps/S +4.83E-07 2006.147.05:08:03.30?ERROR st -97 Trouble decoding pressure data 2006.147.05:08:03.30#wxget#06 5.1 8.8 20.42 801012.3 2006.147.07:19:50.00:unstow 2006.147.07:19:50.00&unstow/antenna=e 2006.147.07:19:50.00&unstow/!+10s 2006.147.07:19:50.00&unstow/antenna=m2 2006.147.07:20:02.01:scan_name=147-0730,k06147,60 2006.147.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.147.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.147.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.147.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.147.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.147.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.147.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.147.07:20:03.14:ready_k5 2006.147.07:20:03.14&ready_k5/obsinfo=st 2006.147.07:20:03.14&ready_k5/autoobs=1 2006.147.07:20:03.14&ready_k5/autoobs=2 2006.147.07:20:03.14&ready_k5/autoobs=3 2006.147.07:20:03.14&ready_k5/autoobs=4 2006.147.07:20:03.14&ready_k5/obsinfo 2006.147.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.147.07:20:03.14#flagr#flagr/antenna,new-source 2006.147.07:20:06.34/autoobs//k5ts1/ autoobs started! 2006.147.07:20:09.45/autoobs//k5ts2/ autoobs started! 2006.147.07:20:12.55/autoobs//k5ts3/ autoobs started! 2006.147.07:20:15.66/autoobs//k5ts4/ autoobs started! 2006.147.07:20:15.69/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:20:15.69:4f8m12a=1 2006.147.07:20:15.69&4f8m12a/xlog=on 2006.147.07:20:15.69&4f8m12a/echo=on 2006.147.07:20:15.69&4f8m12a/pcalon 2006.147.07:20:15.69&4f8m12a/"tpicd=stop 2006.147.07:20:15.69&4f8m12a/vc4f8 2006.147.07:20:15.69&4f8m12a/ifd4f 2006.147.07:20:15.69&4f8m12a/"form=m,16.000,1:2 2006.147.07:20:15.69&4f8m12a/"tpicd 2006.147.07:20:15.69&4f8m12a/echo=off 2006.147.07:20:15.69&4f8m12a/xlog=off 2006.147.07:20:15.69$4f8m12a/echo=on 2006.147.07:20:15.69$4f8m12a/pcalon 2006.147.07:20:15.69&pcalon/"no phase cal control is implemented here 2006.147.07:20:15.69$pcalon/"no phase cal control is implemented here 2006.147.07:20:15.69$4f8m12a/"tpicd=stop 2006.147.07:20:15.69$4f8m12a/vc4f8 2006.147.07:20:15.69&vc4f8/valo=1,532.99 2006.147.07:20:15.69&vc4f8/va=1,8 2006.147.07:20:15.69&vc4f8/valo=2,572.99 2006.147.07:20:15.69&vc4f8/va=2,7 2006.147.07:20:15.69&vc4f8/valo=3,672.99 2006.147.07:20:15.69&vc4f8/va=3,8 2006.147.07:20:15.69&vc4f8/valo=4,832.99 2006.147.07:20:15.69&vc4f8/va=4,7 2006.147.07:20:15.69&vc4f8/valo=5,652.99 2006.147.07:20:15.69&vc4f8/va=5,6 2006.147.07:20:15.69&vc4f8/valo=6,772.99 2006.147.07:20:15.69&vc4f8/va=6,5 2006.147.07:20:15.69&vc4f8/valo=7,832.99 2006.147.07:20:15.69&vc4f8/va=7,5 2006.147.07:20:15.69&vc4f8/valo=8,852.99 2006.147.07:20:15.69&vc4f8/va=8,5 2006.147.07:20:15.69&vc4f8/vblo=1,632.99 2006.147.07:20:15.69&vc4f8/vb=1,4 2006.147.07:20:15.69&vc4f8/vblo=2,640.99 2006.147.07:20:15.69&vc4f8/vb=2,4 2006.147.07:20:15.69&vc4f8/vblo=3,656.99 2006.147.07:20:15.69&vc4f8/vb=3,4 2006.147.07:20:15.69&vc4f8/vblo=4,712.99 2006.147.07:20:15.69&vc4f8/vb=4,4 2006.147.07:20:15.69&vc4f8/vblo=5,744.99 2006.147.07:20:15.69&vc4f8/vb=5,3 2006.147.07:20:15.69&vc4f8/vblo=6,752.99 2006.147.07:20:15.69&vc4f8/vb=6,4 2006.147.07:20:15.69&vc4f8/vabw=wide 2006.147.07:20:15.70&vc4f8/vbbw=wide 2006.147.07:20:15.70$vc4f8/valo=1,532.99 2006.147.07:20:15.70#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:20:15.70#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:20:15.70#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:15.70#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:15.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:15.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:15.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:20:15.80#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:15.80#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:15.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:20:15.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:20:15.80$vc4f8/va=1,8 2006.147.07:20:15.80#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:20:15.80#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:20:15.80#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:15.80#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:15.80#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:15.80#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:15.83#ibcon#[25=AT01-08\r\n] 2006.147.07:20:15.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:15.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:15.87#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:20:15.87#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:15.87#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:15.99#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:15.99#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:16.02#ibcon#[25=USB\r\n] 2006.147.07:20:16.05#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:16.05#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:16.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:20:16.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:20:16.05$vc4f8/valo=2,572.99 2006.147.07:20:16.05#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.07:20:16.05#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.07:20:16.05#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:16.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:20:16.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:20:16.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:20:16.07#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:20:16.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:20:16.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:20:16.11#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:20:16.12#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:20:16.12$vc4f8/va=2,7 2006.147.07:20:16.12#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.07:20:16.12#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.07:20:16.12#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:16.12#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:20:16.16#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:20:16.16#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:20:16.19#ibcon#[25=AT02-07\r\n] 2006.147.07:20:16.22#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:20:16.22#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:20:16.22#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.07:20:16.22#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:16.22#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:20:16.34#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:20:16.34#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:20:16.36#ibcon#[25=USB\r\n] 2006.147.07:20:16.39#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:20:16.39#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:20:16.39#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:20:16.39#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:20:16.39$vc4f8/valo=3,672.99 2006.147.07:20:16.39#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:20:16.39#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:20:16.39#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:16.39#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:16.39#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:16.39#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:16.42#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:20:16.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:16.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:16.47#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:20:16.47#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:20:16.47$vc4f8/va=3,8 2006.147.07:20:16.47#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:20:16.47#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:20:16.47#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:16.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:16.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:16.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:16.53#ibcon#[25=AT03-08\r\n] 2006.147.07:20:16.56#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:16.56#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:16.56#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:20:16.56#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:16.56#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:16.68#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:16.68#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:16.70#ibcon#[25=USB\r\n] 2006.147.07:20:16.73#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:16.73#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:16.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:20:16.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:20:16.73$vc4f8/valo=4,832.99 2006.147.07:20:16.73#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:20:16.73#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:20:16.73#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:16.73#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:16.73#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:16.73#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:16.75#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:20:16.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:16.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:16.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:20:16.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:20:16.79$vc4f8/va=4,7 2006.147.07:20:16.79#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:20:16.79#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:20:16.79#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:16.79#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:16.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:16.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:16.87#ibcon#[25=AT04-07\r\n] 2006.147.07:20:16.90#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:16.90#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:16.90#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:20:16.90#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:16.90#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:17.02#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:17.02#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:17.04#ibcon#[25=USB\r\n] 2006.147.07:20:17.07#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:17.07#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:17.07#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:20:17.07#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:20:17.07$vc4f8/valo=5,652.99 2006.147.07:20:17.07#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:20:17.07#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:20:17.07#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:17.07#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:17.07#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:17.07#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:17.09#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:20:17.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:17.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:17.13#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:20:17.13#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:20:17.13$vc4f8/va=5,6 2006.147.07:20:17.13#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:20:17.13#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:20:17.13#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:17.13#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:17.19#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:17.19#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:17.21#ibcon#[25=AT05-06\r\n] 2006.147.07:20:17.24#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:17.24#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:17.24#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:20:17.24#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:17.24#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:17.36#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:17.36#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:17.38#ibcon#[25=USB\r\n] 2006.147.07:20:17.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:17.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:17.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:20:17.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:20:17.43$vc4f8/valo=6,772.99 2006.147.07:20:17.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:20:17.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:20:17.43#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:17.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:17.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:17.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:17.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:20:17.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:17.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:17.49#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:20:17.49#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:20:17.49$vc4f8/va=6,5 2006.147.07:20:17.49#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:20:17.49#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:20:17.49#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:17.49#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:17.55#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:17.55#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:17.57#ibcon#[25=AT06-05\r\n] 2006.147.07:20:17.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:17.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:17.60#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:20:17.60#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:17.60#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:17.72#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:17.72#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:17.74#ibcon#[25=USB\r\n] 2006.147.07:20:17.77#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:17.77#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:17.77#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:20:17.77#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:20:17.77$vc4f8/valo=7,832.99 2006.147.07:20:17.77#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:20:17.77#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:20:17.77#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:17.77#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:17.77#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:17.77#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:17.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:20:17.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:17.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:17.83#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:20:17.83#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:20:17.83$vc4f8/va=7,5 2006.147.07:20:17.83#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:20:17.83#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:20:17.83#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:17.83#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:17.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:17.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:17.91#ibcon#[25=AT07-05\r\n] 2006.147.07:20:17.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:17.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:17.94#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:20:17.94#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:17.94#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:20:18.06#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:20:18.06#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:20:18.08#ibcon#[25=USB\r\n] 2006.147.07:20:18.11#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:20:18.11#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:20:18.11#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:20:18.11#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:20:18.11$vc4f8/valo=8,852.99 2006.147.07:20:18.11#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:20:18.11#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:20:18.11#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:18.11#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:20:18.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:20:18.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:20:18.13#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:20:18.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:20:18.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:20:18.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:20:18.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:20:18.17$vc4f8/va=8,5 2006.147.07:20:18.17#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:20:18.17#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:20:18.17#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:18.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:20:18.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:20:18.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:20:18.25#ibcon#[25=AT08-05\r\n] 2006.147.07:20:18.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:20:18.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:20:18.28#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:20:18.28#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:18.28#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:20:18.40#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:20:18.40#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:20:18.42#ibcon#[25=USB\r\n] 2006.147.07:20:18.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:20:18.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:20:18.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:20:18.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:20:18.45$vc4f8/vblo=1,632.99 2006.147.07:20:18.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:20:18.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:20:18.45#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:18.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:20:18.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:20:18.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:20:18.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:20:18.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:20:18.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:20:18.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:20:18.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:20:18.53$vc4f8/vb=1,4 2006.147.07:20:18.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:20:18.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:20:18.53#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:18.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:20:18.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:20:18.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:20:18.55#ibcon#[27=AT01-04\r\n] 2006.147.07:20:18.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:20:18.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:20:18.59#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:20:18.59#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:18.59#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:20:18.71#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:20:18.71#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:20:18.73#ibcon#[27=USB\r\n] 2006.147.07:20:18.76#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:20:18.76#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:20:18.76#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:20:18.76#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:20:18.76$vc4f8/vblo=2,640.99 2006.147.07:20:18.76#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:20:18.76#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:20:18.76#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:18.76#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:18.76#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:18.76#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:18.78#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:20:18.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:18.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:20:18.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:20:18.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:20:18.82$vc4f8/vb=2,4 2006.147.07:20:18.82#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:20:18.82#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:20:18.82#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:18.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:18.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:18.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:18.90#ibcon#[27=AT02-04\r\n] 2006.147.07:20:18.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:18.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:20:18.93#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:20:18.93#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:18.93#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:18.99#abcon#<5=/06 3.9 7.1 20.03 791011.3\r\n> 2006.147.07:20:19.01#abcon#{5=INTERFACE CLEAR} 2006.147.07:20:19.07#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:19.07#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:19.09#ibcon#[27=USB\r\n] 2006.147.07:20:19.09#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:20:19.12#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:19.12#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:20:19.12#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:20:19.12#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:20:19.12$vc4f8/vblo=3,656.99 2006.147.07:20:19.12#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:20:19.12#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:20:19.12#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:19.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:19.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:19.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:19.14#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:20:19.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:19.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:20:19.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:20:19.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:20:19.18$vc4f8/vb=3,4 2006.147.07:20:19.18#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:20:19.18#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:20:19.18#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:19.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:19.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:19.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:19.26#ibcon#[27=AT03-04\r\n] 2006.147.07:20:19.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:19.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:20:19.29#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:20:19.29#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:19.29#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:19.41#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:19.41#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:19.43#ibcon#[27=USB\r\n] 2006.147.07:20:19.46#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:19.46#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:20:19.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:20:19.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:20:19.46$vc4f8/vblo=4,712.99 2006.147.07:20:19.46#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:20:19.46#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:20:19.46#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:19.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:19.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:19.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:19.48#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:20:19.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:19.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:20:19.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:20:19.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:20:19.52$vc4f8/vb=4,4 2006.147.07:20:19.52#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:20:19.52#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:20:19.52#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:19.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:19.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:19.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:19.60#ibcon#[27=AT04-04\r\n] 2006.147.07:20:19.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:19.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:20:19.63#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:20:19.63#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:19.63#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:19.75#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:19.75#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:19.77#ibcon#[27=USB\r\n] 2006.147.07:20:19.80#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:19.80#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:20:19.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:20:19.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:20:19.80$vc4f8/vblo=5,744.99 2006.147.07:20:19.80#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:20:19.80#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:20:19.80#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:19.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:19.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:19.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:19.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:20:19.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:19.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:20:19.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:20:19.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:20:19.86$vc4f8/vb=5,3 2006.147.07:20:19.86#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:20:19.86#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:20:19.86#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:19.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:19.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:19.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:19.94#ibcon#[27=AT05-03\r\n] 2006.147.07:20:19.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:19.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:20:19.97#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:20:19.97#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:19.97#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:20.09#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:20.09#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:20.11#ibcon#[27=USB\r\n] 2006.147.07:20:20.14#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:20.14#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:20:20.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:20:20.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:20:20.14$vc4f8/vblo=6,752.99 2006.147.07:20:20.14#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:20:20.14#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:20:20.14#ibcon#ireg 17 cls_cnt 0 2006.147.07:20:20.14#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:20.14#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:20.14#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:20.16#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:20:20.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:20.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:20:20.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:20:20.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:20:20.20$vc4f8/vb=6,4 2006.147.07:20:20.20#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:20:20.20#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:20:20.20#ibcon#ireg 11 cls_cnt 2 2006.147.07:20:20.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:20.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:20.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:20.28#ibcon#[27=AT06-04\r\n] 2006.147.07:20:20.31#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:20.31#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:20:20.31#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:20:20.31#ibcon#ireg 7 cls_cnt 0 2006.147.07:20:20.31#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:20.43#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:20.43#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:20.45#ibcon#[27=USB\r\n] 2006.147.07:20:20.48#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:20.48#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:20:20.48#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:20:20.48#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:20:20.48$vc4f8/vabw=wide 2006.147.07:20:20.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:20:20.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:20:20.48#ibcon#ireg 8 cls_cnt 0 2006.147.07:20:20.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:20.48#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:20.48#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:20.50#ibcon#[25=BW32\r\n] 2006.147.07:20:20.53#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:20.53#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:20:20.53#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:20:20.53#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:20:20.53$vc4f8/vbbw=wide 2006.147.07:20:20.53#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.07:20:20.53#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.07:20:20.53#ibcon#ireg 8 cls_cnt 0 2006.147.07:20:20.53#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:20:20.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:20:20.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:20:20.62#ibcon#[27=BW32\r\n] 2006.147.07:20:20.65#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:20:20.65#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:20:20.65#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:20:20.65#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:20:20.65$4f8m12a/ifd4f 2006.147.07:20:20.65&ifd4f/lo= 2006.147.07:20:20.65&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:20:20.65&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:20:20.65&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:20:20.65&ifd4f/patch= 2006.147.07:20:20.65&ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:20:20.65&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:20:20.65&ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:20:20.65$ifd4f/lo= 2006.147.07:20:20.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:20:20.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:20:20.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:20:20.65$ifd4f/patch= 2006.147.07:20:20.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:20:20.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:20:20.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:20:20.65$4f8m12a/"form=m,16.000,1:2 2006.147.07:20:20.65$4f8m12a/"tpicd 2006.147.07:20:20.65$4f8m12a/echo=off 2006.147.07:20:20.65$4f8m12a/xlog=off 2006.147.07:20:20.65:!2006.147.07:29:50 2006.147.07:20:38.14#trakl#Source acquired 2006.147.07:20:38.14#flagr#flagr/antenna,acquired 2006.147.07:29:50.00:preob 2006.147.07:29:50.00&preob/onsource 2006.147.07:29:51.14/onsource/TRACKING 2006.147.07:29:51.14:!2006.147.07:30:00 2006.147.07:30:00.00:data_valid=on 2006.147.07:30:00.00:midob 2006.147.07:30:00.00&midob/onsource 2006.147.07:30:00.00&midob/wx 2006.147.07:30:00.00&midob/cable 2006.147.07:30:00.00&midob/va 2006.147.07:30:00.00&midob/valo 2006.147.07:30:00.00&midob/vb 2006.147.07:30:00.00&midob/vblo 2006.147.07:30:00.00&midob/vabw 2006.147.07:30:00.00&midob/vbbw 2006.147.07:30:00.00&midob/"form 2006.147.07:30:00.00&midob/xfe 2006.147.07:30:00.00&midob/ifatt 2006.147.07:30:00.00&midob/clockoff 2006.147.07:30:00.00&midob/sy=logmail 2006.147.07:30:00.00&midob/"sy=run setcl adapt & 2006.147.07:30:00.14/onsource/TRACKING 2006.147.07:30:00.14/wx/19.96,1011.4,79 2006.147.07:30:00.32/cable/+6.5363E-03 2006.147.07:30:01.41/va/01,08,usb,yes,32,34 2006.147.07:30:01.41/va/02,07,usb,yes,32,34 2006.147.07:30:01.41/va/03,08,usb,yes,24,24 2006.147.07:30:01.41/va/04,07,usb,yes,33,35 2006.147.07:30:01.41/va/05,06,usb,yes,37,39 2006.147.07:30:01.41/va/06,05,usb,yes,37,37 2006.147.07:30:01.41/va/07,05,usb,yes,37,37 2006.147.07:30:01.41/va/08,05,usb,yes,40,39 2006.147.07:30:01.64/valo/01,532.99,yes,locked 2006.147.07:30:01.64/valo/02,572.99,yes,locked 2006.147.07:30:01.64/valo/03,672.99,yes,locked 2006.147.07:30:01.64/valo/04,832.99,yes,locked 2006.147.07:30:01.64/valo/05,652.99,yes,locked 2006.147.07:30:01.64/valo/06,772.99,yes,locked 2006.147.07:30:01.64/valo/07,832.99,yes,locked 2006.147.07:30:01.64/valo/08,852.99,yes,locked 2006.147.07:30:02.73/vb/01,04,usb,yes,29,28 2006.147.07:30:02.73/vb/02,04,usb,yes,31,33 2006.147.07:30:02.73/vb/03,04,usb,yes,28,31 2006.147.07:30:02.73/vb/04,04,usb,yes,29,29 2006.147.07:30:02.73/vb/05,03,usb,yes,34,38 2006.147.07:30:02.73/vb/06,04,usb,yes,28,31 2006.147.07:30:02.73/vb/07,04,usb,yes,30,30 2006.147.07:30:02.73/vb/08,03,usb,yes,34,38 2006.147.07:30:02.96/vblo/01,632.99,yes,locked 2006.147.07:30:02.96/vblo/02,640.99,yes,locked 2006.147.07:30:02.96/vblo/03,656.99,yes,locked 2006.147.07:30:02.96/vblo/04,712.99,yes,locked 2006.147.07:30:02.96/vblo/05,744.99,yes,locked 2006.147.07:30:02.96/vblo/06,752.99,yes,locked 2006.147.07:30:02.96/vblo/07,734.99,yes,locked 2006.147.07:30:02.96/vblo/08,744.99,yes,locked 2006.147.07:30:03.11/vabw/8 2006.147.07:30:03.26/vbbw/8 2006.147.07:30:03.35/xfe/off,on,15.2 2006.147.07:30:03.72/ifatt/23,28,28,28 2006.147.07:30:04.08/fmout-gps/S +4.90E-07 2006.147.07:30:04.16:!2006.147.07:31:00 2006.147.07:31:00.01:data_valid=off 2006.147.07:31:00.01:postob 2006.147.07:31:00.01&postob/cable 2006.147.07:31:00.02&postob/wx 2006.147.07:31:00.02&postob/clockoff 2006.147.07:31:00.22/cable/+6.5389E-03 2006.147.07:31:00.22/wx/19.95,1011.4,78 2006.147.07:31:01.08/fmout-gps/S +4.91E-07 2006.147.07:31:01.08:scan_name=147-0733,k06147,60 2006.147.07:31:01.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.147.07:31:01.14#flagr#flagr/antenna,new-source 2006.147.07:31:02.14:checkk5 2006.147.07:31:02.14&checkk5/chk_autoobs=1 2006.147.07:31:02.14&checkk5/chk_autoobs=2 2006.147.07:31:02.15&checkk5/chk_autoobs=3 2006.147.07:31:02.15&checkk5/chk_autoobs=4 2006.147.07:31:02.15&checkk5/chk_obsdata=1 2006.147.07:31:02.16&checkk5/chk_obsdata=2 2006.147.07:31:02.16&checkk5/chk_obsdata=3 2006.147.07:31:02.17&checkk5/chk_obsdata=4 2006.147.07:31:02.17&checkk5/k5log=1 2006.147.07:31:02.17&checkk5/k5log=2 2006.147.07:31:02.22&checkk5/k5log=3 2006.147.07:31:02.23&checkk5/k5log=4 2006.147.07:31:02.23&checkk5/obsinfo 2006.147.07:31:02.62/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:31:03.01/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:31:03.41/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:31:03.79/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:31:04.16/chk_obsdata//k5ts1/k06147_ts1_147-0730*_20??1470730??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:31:04.54/chk_obsdata//k5ts2/k06147_ts2_147-0730*_20??1470730??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:31:04.90/chk_obsdata//k5ts3/k06147_ts3_147-0730*_20??1470730??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:31:05.27/chk_obsdata//k5ts4/k06147_ts4_147-0730*_20??1470730??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:31:05.98/k5log//k5ts1_log_newline 2006.147.07:31:06.67/k5log//k5ts2_log_newline 2006.147.07:31:07.36/k5log//k5ts3_log_newline 2006.147.07:31:08.05/k5log//k5ts4_log_newline 2006.147.07:31:08.07/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:31:08.07:4f8m12a=1 2006.147.07:31:08.07$4f8m12a/echo=on 2006.147.07:31:08.07$4f8m12a/pcalon 2006.147.07:31:08.07$pcalon/"no phase cal control is implemented here 2006.147.07:31:08.07$4f8m12a/"tpicd=stop 2006.147.07:31:08.07$4f8m12a/vc4f8 2006.147.07:31:08.07$vc4f8/valo=1,532.99 2006.147.07:31:08.08#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.07:31:08.08#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.07:31:08.08#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:08.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:08.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:08.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:08.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:31:08.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:08.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:08.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:31:08.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:31:08.17$vc4f8/va=1,8 2006.147.07:31:08.17#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.07:31:08.17#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.07:31:08.17#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:08.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:08.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:08.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:08.20#ibcon#[25=AT01-08\r\n] 2006.147.07:31:08.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:08.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:08.23#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.07:31:08.23#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:08.23#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:08.35#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:08.35#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:08.37#ibcon#[25=USB\r\n] 2006.147.07:31:08.40#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:08.40#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:08.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:31:08.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:31:08.40$vc4f8/valo=2,572.99 2006.147.07:31:08.40#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:31:08.40#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:31:08.40#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:08.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:08.40#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:08.40#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:08.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:31:08.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:08.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:08.47#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:31:08.47#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:31:08.47$vc4f8/va=2,7 2006.147.07:31:08.47#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:31:08.47#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:31:08.47#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:08.47#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:08.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:08.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:08.54#ibcon#[25=AT02-07\r\n] 2006.147.07:31:08.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:08.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:08.57#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:31:08.57#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:08.57#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:08.69#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:08.69#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:08.71#ibcon#[25=USB\r\n] 2006.147.07:31:08.76#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:08.76#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:08.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:31:08.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:31:08.76$vc4f8/valo=3,672.99 2006.147.07:31:08.76#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:31:08.76#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:31:08.76#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:08.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:08.76#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:08.76#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:08.78#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:31:08.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:08.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:08.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:31:08.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:31:08.82$vc4f8/va=3,8 2006.147.07:31:08.82#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.07:31:08.82#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.07:31:08.82#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:08.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:08.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:08.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:08.90#ibcon#[25=AT03-08\r\n] 2006.147.07:31:08.93#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:08.93#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:08.93#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.07:31:08.93#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:08.93#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:09.05#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:09.05#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:09.07#ibcon#[25=USB\r\n] 2006.147.07:31:09.10#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:09.10#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:09.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:31:09.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:31:09.10$vc4f8/valo=4,832.99 2006.147.07:31:09.10#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.07:31:09.10#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.07:31:09.10#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:09.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:09.10#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:09.10#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:09.12#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:31:09.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:09.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:09.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:31:09.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:31:09.16$vc4f8/va=4,7 2006.147.07:31:09.16#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.07:31:09.16#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.07:31:09.16#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:09.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:09.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:09.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:09.24#ibcon#[25=AT04-07\r\n] 2006.147.07:31:09.27#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:09.27#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:09.27#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.07:31:09.27#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:09.27#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:09.39#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:09.39#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:09.41#ibcon#[25=USB\r\n] 2006.147.07:31:09.44#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:09.44#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:09.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:31:09.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:31:09.44$vc4f8/valo=5,652.99 2006.147.07:31:09.44#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.07:31:09.44#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.07:31:09.44#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:09.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:09.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:09.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:09.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:31:09.50#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:09.50#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:09.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:31:09.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:31:09.50$vc4f8/va=5,6 2006.147.07:31:09.50#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.07:31:09.50#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.07:31:09.50#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:09.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:09.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:09.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:09.58#ibcon#[25=AT05-06\r\n] 2006.147.07:31:09.61#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:09.61#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:09.61#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.07:31:09.61#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:09.61#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:09.73#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:09.73#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:09.75#ibcon#[25=USB\r\n] 2006.147.07:31:09.78#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:09.78#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:09.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:31:09.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:31:09.78$vc4f8/valo=6,772.99 2006.147.07:31:09.78#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:31:09.78#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:31:09.78#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:09.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:09.78#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:09.78#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:09.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:31:09.84#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:09.84#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:09.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:31:09.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:31:09.84$vc4f8/va=6,5 2006.147.07:31:09.84#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.07:31:09.84#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.07:31:09.84#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:09.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:09.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:09.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:09.92#ibcon#[25=AT06-05\r\n] 2006.147.07:31:09.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:09.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:09.95#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.07:31:09.95#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:09.95#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:10.07#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:10.07#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:10.09#ibcon#[25=USB\r\n] 2006.147.07:31:10.12#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:10.12#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:10.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:31:10.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:31:10.12$vc4f8/valo=7,832.99 2006.147.07:31:10.12#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:31:10.12#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:31:10.12#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:10.12#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:31:10.12#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:31:10.12#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:31:10.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:31:10.14#abcon#<5=/06 3.5 6.5 19.94 781011.3\r\n> 2006.147.07:31:10.16#abcon#{5=INTERFACE CLEAR} 2006.147.07:31:10.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:31:10.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:31:10.18#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:31:10.18#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:31:10.18$vc4f8/va=7,5 2006.147.07:31:10.18#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:31:10.18#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:31:10.18#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:10.18#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:31:10.22#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:31:10.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:31:10.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:31:10.26#ibcon#[25=AT07-05\r\n] 2006.147.07:31:10.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:31:10.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:31:10.29#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:31:10.29#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:10.29#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:31:10.41#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:31:10.41#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:31:10.43#ibcon#[25=USB\r\n] 2006.147.07:31:10.46#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:31:10.46#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:31:10.46#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:31:10.46#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:31:10.46$vc4f8/valo=8,852.99 2006.147.07:31:10.46#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.07:31:10.46#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.07:31:10.46#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:10.46#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:31:10.46#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:31:10.46#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:31:10.48#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:31:10.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:31:10.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:31:10.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:31:10.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:31:10.52$vc4f8/va=8,5 2006.147.07:31:10.52#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.07:31:10.52#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.07:31:10.52#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:10.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:31:10.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:31:10.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:31:10.60#ibcon#[25=AT08-05\r\n] 2006.147.07:31:10.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:31:10.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:31:10.63#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.07:31:10.63#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:10.63#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:31:10.75#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:31:10.75#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:31:10.77#ibcon#[25=USB\r\n] 2006.147.07:31:10.80#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:31:10.80#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:31:10.80#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:31:10.80#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:31:10.80$vc4f8/vblo=1,632.99 2006.147.07:31:10.80#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.07:31:10.80#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.07:31:10.80#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:10.80#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:10.80#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:10.80#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:10.82#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:31:10.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:10.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:31:10.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:31:10.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:31:10.86$vc4f8/vb=1,4 2006.147.07:31:10.86#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.07:31:10.86#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.07:31:10.86#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:10.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:10.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:10.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:10.88#ibcon#[27=AT01-04\r\n] 2006.147.07:31:10.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:10.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:31:10.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.07:31:10.91#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:10.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:11.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:11.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:11.05#ibcon#[27=USB\r\n] 2006.147.07:31:11.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:11.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:31:11.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:31:11.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:31:11.08$vc4f8/vblo=2,640.99 2006.147.07:31:11.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:31:11.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:31:11.08#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:11.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:11.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:11.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:11.10#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:31:11.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:11.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:31:11.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:31:11.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:31:11.14$vc4f8/vb=2,4 2006.147.07:31:11.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:31:11.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:31:11.14#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:11.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:11.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:11.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:11.22#ibcon#[27=AT02-04\r\n] 2006.147.07:31:11.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:11.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:31:11.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:31:11.25#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:11.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:11.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:11.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:11.39#ibcon#[27=USB\r\n] 2006.147.07:31:11.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:11.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:31:11.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:31:11.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:31:11.42$vc4f8/vblo=3,656.99 2006.147.07:31:11.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:31:11.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:31:11.42#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:11.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:11.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:11.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:11.44#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:31:11.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:11.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:31:11.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:31:11.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:31:11.48$vc4f8/vb=3,4 2006.147.07:31:11.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.07:31:11.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.07:31:11.48#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:11.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:11.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:11.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:11.56#ibcon#[27=AT03-04\r\n] 2006.147.07:31:11.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:11.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:31:11.59#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.07:31:11.59#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:11.59#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:11.71#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:11.71#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:11.73#ibcon#[27=USB\r\n] 2006.147.07:31:11.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:11.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:31:11.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:31:11.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:31:11.76$vc4f8/vblo=4,712.99 2006.147.07:31:11.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.07:31:11.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.07:31:11.76#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:11.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:11.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:11.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:11.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:31:11.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:11.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:31:11.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:31:11.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:31:11.82$vc4f8/vb=4,4 2006.147.07:31:11.82#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.07:31:11.82#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.07:31:11.82#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:11.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:11.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:11.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:11.90#ibcon#[27=AT04-04\r\n] 2006.147.07:31:11.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:11.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:31:11.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.07:31:11.93#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:11.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:12.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:12.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:12.07#ibcon#[27=USB\r\n] 2006.147.07:31:12.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:12.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:31:12.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:31:12.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:31:12.10$vc4f8/vblo=5,744.99 2006.147.07:31:12.10#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.07:31:12.10#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.07:31:12.10#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:12.10#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:12.10#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:12.10#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:12.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:31:12.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:12.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:31:12.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:31:12.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:31:12.16$vc4f8/vb=5,3 2006.147.07:31:12.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.07:31:12.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.07:31:12.16#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:12.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:12.22#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:12.22#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:12.24#ibcon#[27=AT05-03\r\n] 2006.147.07:31:12.27#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:12.27#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:31:12.27#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.07:31:12.27#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:12.27#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:12.39#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:12.39#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:12.41#ibcon#[27=USB\r\n] 2006.147.07:31:12.44#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:12.44#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:31:12.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:31:12.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:31:12.44$vc4f8/vblo=6,752.99 2006.147.07:31:12.44#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:31:12.44#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:31:12.44#ibcon#ireg 17 cls_cnt 0 2006.147.07:31:12.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:12.44#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:12.44#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:12.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:31:12.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:12.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:31:12.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:31:12.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:31:12.50$vc4f8/vb=6,4 2006.147.07:31:12.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.07:31:12.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.07:31:12.50#ibcon#ireg 11 cls_cnt 2 2006.147.07:31:12.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:12.56#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:12.56#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:12.58#ibcon#[27=AT06-04\r\n] 2006.147.07:31:12.61#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:12.61#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:31:12.61#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.07:31:12.61#ibcon#ireg 7 cls_cnt 0 2006.147.07:31:12.61#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:12.73#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:12.73#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:12.75#ibcon#[27=USB\r\n] 2006.147.07:31:12.78#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:12.78#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:31:12.78#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:31:12.78#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:31:12.78$vc4f8/vabw=wide 2006.147.07:31:12.78#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:31:12.78#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:31:12.78#ibcon#ireg 8 cls_cnt 0 2006.147.07:31:12.78#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:31:12.78#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:31:12.78#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:31:12.80#ibcon#[25=BW32\r\n] 2006.147.07:31:12.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:31:12.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:31:12.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:31:12.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:31:12.83$vc4f8/vbbw=wide 2006.147.07:31:12.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:31:12.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:31:12.83#ibcon#ireg 8 cls_cnt 0 2006.147.07:31:12.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:31:12.90#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:31:12.90#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:31:12.92#ibcon#[27=BW32\r\n] 2006.147.07:31:12.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:31:12.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:31:12.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:31:12.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:31:12.95$4f8m12a/ifd4f 2006.147.07:31:12.95$ifd4f/lo= 2006.147.07:31:12.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:31:12.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:31:12.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:31:12.95$ifd4f/patch= 2006.147.07:31:12.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:31:12.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:31:12.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:31:12.95$4f8m12a/"form=m,16.000,1:2 2006.147.07:31:12.95$4f8m12a/"tpicd 2006.147.07:31:12.95$4f8m12a/echo=off 2006.147.07:31:12.95$4f8m12a/xlog=off 2006.147.07:31:12.95:!2006.147.07:33:20 2006.147.07:31:47.14#trakl#Source acquired 2006.147.07:31:49.14#flagr#flagr/antenna,acquired 2006.147.07:33:20.00:preob 2006.147.07:33:20.13/onsource/TRACKING 2006.147.07:33:20.13:!2006.147.07:33:30 2006.147.07:33:30.00:data_valid=on 2006.147.07:33:30.00:midob 2006.147.07:33:31.13/onsource/TRACKING 2006.147.07:33:31.13/wx/19.92,1011.3,80 2006.147.07:33:31.21/cable/+6.5398E-03 2006.147.07:33:32.30/va/01,08,usb,yes,30,32 2006.147.07:33:32.30/va/02,07,usb,yes,30,32 2006.147.07:33:32.30/va/03,08,usb,yes,23,23 2006.147.07:33:32.30/va/04,07,usb,yes,31,33 2006.147.07:33:32.30/va/05,06,usb,yes,34,36 2006.147.07:33:32.30/va/06,05,usb,yes,35,34 2006.147.07:33:32.30/va/07,05,usb,yes,35,34 2006.147.07:33:32.30/va/08,05,usb,yes,37,37 2006.147.07:33:32.53/valo/01,532.99,yes,locked 2006.147.07:33:32.53/valo/02,572.99,yes,locked 2006.147.07:33:32.53/valo/03,672.99,yes,locked 2006.147.07:33:32.53/valo/04,832.99,yes,locked 2006.147.07:33:32.53/valo/05,652.99,yes,locked 2006.147.07:33:32.53/valo/06,772.99,yes,locked 2006.147.07:33:32.53/valo/07,832.99,yes,locked 2006.147.07:33:32.53/valo/08,852.99,yes,locked 2006.147.07:33:33.62/vb/01,04,usb,yes,29,28 2006.147.07:33:33.62/vb/02,04,usb,yes,31,32 2006.147.07:33:33.62/vb/03,04,usb,yes,27,31 2006.147.07:33:33.62/vb/04,04,usb,yes,28,28 2006.147.07:33:33.62/vb/05,03,usb,yes,34,38 2006.147.07:33:33.62/vb/06,04,usb,yes,28,31 2006.147.07:33:33.62/vb/07,04,usb,yes,30,30 2006.147.07:33:33.62/vb/08,03,usb,yes,34,38 2006.147.07:33:33.85/vblo/01,632.99,yes,locked 2006.147.07:33:33.85/vblo/02,640.99,yes,locked 2006.147.07:33:33.85/vblo/03,656.99,yes,locked 2006.147.07:33:33.85/vblo/04,712.99,yes,locked 2006.147.07:33:33.85/vblo/05,744.99,yes,locked 2006.147.07:33:33.85/vblo/06,752.99,yes,locked 2006.147.07:33:33.85/vblo/07,734.99,yes,locked 2006.147.07:33:33.85/vblo/08,744.99,yes,locked 2006.147.07:33:34.00/vabw/8 2006.147.07:33:34.15/vbbw/8 2006.147.07:33:34.25/xfe/off,on,15.0 2006.147.07:33:34.63/ifatt/23,28,28,28 2006.147.07:33:35.08/fmout-gps/S +4.91E-07 2006.147.07:33:35.12:!2006.147.07:34:30 2006.147.07:34:30.02:data_valid=off 2006.147.07:34:30.02:postob 2006.147.07:34:30.20/cable/+6.5355E-03 2006.147.07:34:30.20/wx/19.91,1011.4,80 2006.147.07:34:31.08/fmout-gps/S +4.91E-07 2006.147.07:34:31.08:scan_name=147-0735,k06147,60 2006.147.07:34:31.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.147.07:34:31.15#flagr#flagr/antenna,new-source 2006.147.07:34:32.14:checkk5 2006.147.07:34:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:34:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:34:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:34:33.67/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:34:34.05/chk_obsdata//k5ts1/k06147_ts1_147-0733*_20??1470733??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:34:34.42/chk_obsdata//k5ts2/k06147_ts2_147-0733*_20??1470733??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:34:34.80/chk_obsdata//k5ts3/k06147_ts3_147-0733*_20??1470733??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:34:35.18/chk_obsdata//k5ts4/k06147_ts4_147-0733*_20??1470733??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:34:35.88/k5log//k5ts1_log_newline 2006.147.07:34:36.57/k5log//k5ts2_log_newline 2006.147.07:34:37.25/k5log//k5ts3_log_newline 2006.147.07:34:37.94/k5log//k5ts4_log_newline 2006.147.07:34:37.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:34:37.96:4f8m12a=1 2006.147.07:34:37.96$4f8m12a/echo=on 2006.147.07:34:37.96$4f8m12a/pcalon 2006.147.07:34:37.96$pcalon/"no phase cal control is implemented here 2006.147.07:34:37.96$4f8m12a/"tpicd=stop 2006.147.07:34:37.96$4f8m12a/vc4f8 2006.147.07:34:37.96$vc4f8/valo=1,532.99 2006.147.07:34:37.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.07:34:37.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.07:34:37.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:37.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:37.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:37.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:38.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:34:38.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:38.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:38.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:34:38.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:34:38.06$vc4f8/va=1,8 2006.147.07:34:38.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.07:34:38.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.07:34:38.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:38.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:38.06#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:38.06#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:38.09#ibcon#[25=AT01-08\r\n] 2006.147.07:34:38.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:38.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:38.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.07:34:38.12#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:38.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:38.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:38.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:38.26#ibcon#[25=USB\r\n] 2006.147.07:34:38.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:38.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:38.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:34:38.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:34:38.30$vc4f8/valo=2,572.99 2006.147.07:34:38.30#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:34:38.30#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:34:38.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:38.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:38.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:38.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:34:38.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:38.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:38.36#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:34:38.36#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:34:38.37$vc4f8/va=2,7 2006.147.07:34:38.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:34:38.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:34:38.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:38.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:38.40#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:38.40#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:38.43#ibcon#[25=AT02-07\r\n] 2006.147.07:34:38.45#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:38.45#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:38.45#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:34:38.45#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:38.45#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:38.57#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:38.57#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:38.59#ibcon#[25=USB\r\n] 2006.147.07:34:38.62#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:38.63#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:38.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:34:38.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:34:38.63$vc4f8/valo=3,672.99 2006.147.07:34:38.63#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:34:38.63#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:34:38.63#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:38.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:38.63#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:38.63#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:34:38.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:38.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:38.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:34:38.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:34:38.70$vc4f8/va=3,8 2006.147.07:34:38.70#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:34:38.70#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:34:38.70#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:38.70#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:38.75#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:38.75#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:38.76#ibcon#[25=AT03-08\r\n] 2006.147.07:34:38.79#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:38.79#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:38.79#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:34:38.79#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:38.79#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:38.91#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:38.91#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:38.93#ibcon#[25=USB\r\n] 2006.147.07:34:38.96#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:38.96#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:38.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:34:38.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:34:38.97$vc4f8/valo=4,832.99 2006.147.07:34:38.97#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:34:38.97#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:34:38.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:38.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:38.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:38.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:38.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:34:39.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:39.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:39.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:34:39.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:34:39.03$vc4f8/va=4,7 2006.147.07:34:39.03#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.07:34:39.03#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.07:34:39.03#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:39.03#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:39.07#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:39.07#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:39.09#ibcon#[25=AT04-07\r\n] 2006.147.07:34:39.12#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:39.12#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:39.12#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.07:34:39.12#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:39.12#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:39.24#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:39.24#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:39.26#ibcon#[25=USB\r\n] 2006.147.07:34:39.29#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:39.29#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:39.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:34:39.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:34:39.30$vc4f8/valo=5,652.99 2006.147.07:34:39.30#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:34:39.30#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:34:39.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:39.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:39.30#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:39.30#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:34:39.35#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:39.35#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:39.35#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:34:39.35#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:34:39.36$vc4f8/va=5,6 2006.147.07:34:39.36#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.07:34:39.36#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.07:34:39.36#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:39.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:39.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:39.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:39.42#ibcon#[25=AT05-06\r\n] 2006.147.07:34:39.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:39.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:39.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.07:34:39.45#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:39.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:39.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:39.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:39.59#ibcon#[25=USB\r\n] 2006.147.07:34:39.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:39.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:39.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:34:39.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:34:39.63$vc4f8/valo=6,772.99 2006.147.07:34:39.63#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:34:39.63#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:34:39.63#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:39.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:39.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:39.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:34:39.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:39.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:39.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:34:39.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:34:39.69$vc4f8/va=6,5 2006.147.07:34:39.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.07:34:39.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.07:34:39.69#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:39.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:39.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:39.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:39.75#ibcon#[25=AT06-05\r\n] 2006.147.07:34:39.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:39.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:39.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.07:34:39.78#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:39.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:34:39.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:34:39.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:34:39.92#ibcon#[25=USB\r\n] 2006.147.07:34:39.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:34:39.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:34:39.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:34:39.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:34:39.96$vc4f8/valo=7,832.99 2006.147.07:34:39.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:34:39.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:34:39.96#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:39.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:34:39.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:34:39.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:34:39.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:34:40.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:34:40.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:34:40.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:34:40.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:34:40.02$vc4f8/va=7,5 2006.147.07:34:40.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.07:34:40.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.07:34:40.02#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:40.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:34:40.06#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:34:40.06#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:34:40.08#ibcon#[25=AT07-05\r\n] 2006.147.07:34:40.11#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:34:40.11#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:34:40.11#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.07:34:40.11#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:40.11#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:34:40.23#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:34:40.23#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:34:40.25#ibcon#[25=USB\r\n] 2006.147.07:34:40.28#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:34:40.28#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:34:40.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:34:40.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:34:40.29$vc4f8/valo=8,852.99 2006.147.07:34:40.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.07:34:40.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.07:34:40.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:40.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:34:40.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:34:40.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:34:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:34:40.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:34:40.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:34:40.34#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:34:40.34#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:34:40.35$vc4f8/va=8,5 2006.147.07:34:40.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.07:34:40.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.07:34:40.35#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:40.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:34:40.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:34:40.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:34:40.41#ibcon#[25=AT08-05\r\n] 2006.147.07:34:40.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:34:40.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:34:40.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.07:34:40.44#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:40.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:34:40.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:34:40.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:34:40.58#ibcon#[25=USB\r\n] 2006.147.07:34:40.61#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:34:40.61#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:34:40.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:34:40.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:34:40.62$vc4f8/vblo=1,632.99 2006.147.07:34:40.62#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.07:34:40.62#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.07:34:40.62#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:40.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:34:40.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:34:40.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:34:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:34:40.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:34:40.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:34:40.67#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:34:40.67#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:34:40.68$vc4f8/vb=1,4 2006.147.07:34:40.68#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.07:34:40.68#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.07:34:40.68#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:40.68#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:34:40.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:34:40.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:34:40.69#ibcon#[27=AT01-04\r\n] 2006.147.07:34:40.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:34:40.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:34:40.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.07:34:40.72#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:40.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:34:40.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:34:40.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:34:40.86#ibcon#[27=USB\r\n] 2006.147.07:34:40.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:34:40.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:34:40.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:34:40.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:34:40.90$vc4f8/vblo=2,640.99 2006.147.07:34:40.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.07:34:40.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.07:34:40.90#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:40.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:40.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:40.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:34:40.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:40.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:34:40.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:34:40.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:34:40.96$vc4f8/vb=2,4 2006.147.07:34:40.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.07:34:40.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.07:34:40.96#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:40.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:41.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:41.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:41.02#ibcon#[27=AT02-04\r\n] 2006.147.07:34:41.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:41.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:34:41.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.07:34:41.05#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:41.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:41.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:41.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:41.19#ibcon#[27=USB\r\n] 2006.147.07:34:41.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:41.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:34:41.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:34:41.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:34:41.23$vc4f8/vblo=3,656.99 2006.147.07:34:41.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:34:41.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:34:41.23#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:41.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:41.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:41.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:34:41.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:41.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:34:41.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:34:41.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:34:41.29$vc4f8/vb=3,4 2006.147.07:34:41.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:34:41.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:34:41.29#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:41.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:41.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:41.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:41.35#ibcon#[27=AT03-04\r\n] 2006.147.07:34:41.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:41.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:34:41.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:34:41.38#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:41.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:41.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:41.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:41.52#ibcon#[27=USB\r\n] 2006.147.07:34:41.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:41.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:34:41.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:34:41.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:34:41.56$vc4f8/vblo=4,712.99 2006.147.07:34:41.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:34:41.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:34:41.56#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:41.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:41.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:41.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:34:41.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:41.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:34:41.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:34:41.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:34:41.62$vc4f8/vb=4,4 2006.147.07:34:41.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:34:41.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:34:41.62#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:41.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:41.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:41.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.147.07:34:41.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:41.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:34:41.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:41.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:41.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:41.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:41.85#ibcon#[27=USB\r\n] 2006.147.07:34:41.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:41.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:34:41.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:34:41.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:34:41.89$vc4f8/vblo=5,744.99 2006.147.07:34:41.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:34:41.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:34:41.89#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:41.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:41.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:41.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:34:41.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:41.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:34:41.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:34:41.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:34:41.95$vc4f8/vb=5,3 2006.147.07:34:41.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.07:34:41.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.07:34:41.95#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:41.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:41.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:41.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:42.01#ibcon#[27=AT05-03\r\n] 2006.147.07:34:42.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:42.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:34:42.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.07:34:42.04#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:42.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:42.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:42.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:42.18#ibcon#[27=USB\r\n] 2006.147.07:34:42.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:42.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:34:42.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:34:42.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:34:42.22$vc4f8/vblo=6,752.99 2006.147.07:34:42.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:34:42.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:34:42.22#ibcon#ireg 17 cls_cnt 0 2006.147.07:34:42.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:42.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:42.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:42.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:34:42.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:42.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:34:42.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:34:42.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:34:42.28$vc4f8/vb=6,4 2006.147.07:34:42.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.07:34:42.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.07:34:42.28#ibcon#ireg 11 cls_cnt 2 2006.147.07:34:42.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:42.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:42.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:42.34#ibcon#[27=AT06-04\r\n] 2006.147.07:34:42.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:42.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:34:42.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.07:34:42.37#ibcon#ireg 7 cls_cnt 0 2006.147.07:34:42.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:42.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:42.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:42.51#ibcon#[27=USB\r\n] 2006.147.07:34:42.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:42.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:34:42.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:34:42.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:34:42.55$vc4f8/vabw=wide 2006.147.07:34:42.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:34:42.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:34:42.55#ibcon#ireg 8 cls_cnt 0 2006.147.07:34:42.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:42.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:42.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:42.56#ibcon#[25=BW32\r\n] 2006.147.07:34:42.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:42.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:34:42.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:34:42.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:34:42.60$vc4f8/vbbw=wide 2006.147.07:34:42.60#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:34:42.60#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:34:42.60#ibcon#ireg 8 cls_cnt 0 2006.147.07:34:42.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:34:42.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:34:42.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:34:42.67#ibcon#[27=BW32\r\n] 2006.147.07:34:42.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:34:42.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:34:42.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:34:42.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:34:42.71$4f8m12a/ifd4f 2006.147.07:34:42.71$ifd4f/lo= 2006.147.07:34:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:34:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:34:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:34:42.71$ifd4f/patch= 2006.147.07:34:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:34:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:34:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:34:42.71$4f8m12a/"form=m,16.000,1:2 2006.147.07:34:42.71$4f8m12a/"tpicd 2006.147.07:34:42.71$4f8m12a/echo=off 2006.147.07:34:42.71$4f8m12a/xlog=off 2006.147.07:34:42.71:!2006.147.07:35:10 2006.147.07:34:53.14#trakl#Source acquired 2006.147.07:34:55.15#flagr#flagr/antenna,acquired 2006.147.07:35:10.01:preob 2006.147.07:35:11.15/onsource/TRACKING 2006.147.07:35:11.15:!2006.147.07:35:20 2006.147.07:35:20.02:data_valid=on 2006.147.07:35:20.02:midob 2006.147.07:35:21.15/onsource/TRACKING 2006.147.07:35:21.15/wx/19.90,1011.4,79 2006.147.07:35:21.24/cable/+6.5390E-03 2006.147.07:35:22.33/va/01,08,usb,yes,30,31 2006.147.07:35:22.33/va/02,07,usb,yes,30,31 2006.147.07:35:22.33/va/03,08,usb,yes,22,22 2006.147.07:35:22.33/va/04,07,usb,yes,30,33 2006.147.07:35:22.33/va/05,06,usb,yes,34,36 2006.147.07:35:22.33/va/06,05,usb,yes,34,34 2006.147.07:35:22.33/va/07,05,usb,yes,34,34 2006.147.07:35:22.33/va/08,05,usb,yes,37,36 2006.147.07:35:22.56/valo/01,532.99,yes,locked 2006.147.07:35:22.56/valo/02,572.99,yes,locked 2006.147.07:35:22.56/valo/03,672.99,yes,locked 2006.147.07:35:22.56/valo/04,832.99,yes,locked 2006.147.07:35:22.56/valo/05,652.99,yes,locked 2006.147.07:35:22.56/valo/06,772.99,yes,locked 2006.147.07:35:22.56/valo/07,832.99,yes,locked 2006.147.07:35:22.56/valo/08,852.99,yes,locked 2006.147.07:35:23.65/vb/01,04,usb,yes,28,27 2006.147.07:35:23.65/vb/02,04,usb,yes,30,31 2006.147.07:35:23.65/vb/03,04,usb,yes,26,30 2006.147.07:35:23.65/vb/04,04,usb,yes,27,27 2006.147.07:35:23.65/vb/05,03,usb,yes,32,36 2006.147.07:35:23.65/vb/06,04,usb,yes,27,29 2006.147.07:35:23.65/vb/07,04,usb,yes,29,28 2006.147.07:35:23.65/vb/08,03,usb,yes,33,36 2006.147.07:35:23.88/vblo/01,632.99,yes,locked 2006.147.07:35:23.88/vblo/02,640.99,yes,locked 2006.147.07:35:23.88/vblo/03,656.99,yes,locked 2006.147.07:35:23.88/vblo/04,712.99,yes,locked 2006.147.07:35:23.88/vblo/05,744.99,yes,locked 2006.147.07:35:23.88/vblo/06,752.99,yes,locked 2006.147.07:35:23.88/vblo/07,734.99,yes,locked 2006.147.07:35:23.88/vblo/08,744.99,yes,locked 2006.147.07:35:24.03/vabw/8 2006.147.07:35:24.18/vbbw/8 2006.147.07:35:24.27/xfe/off,on,14.2 2006.147.07:35:24.65/ifatt/23,28,28,28 2006.147.07:35:25.07/fmout-gps/S +4.92E-07 2006.147.07:35:25.12:!2006.147.07:36:20 2006.147.07:36:20.02:data_valid=off 2006.147.07:36:20.02:postob 2006.147.07:36:20.21/cable/+6.5399E-03 2006.147.07:36:20.22/wx/19.89,1011.3,81 2006.147.07:36:21.07/fmout-gps/S +4.92E-07 2006.147.07:36:21.08:scan_name=147-0737,k06147,60 2006.147.07:36:21.08:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.147.07:36:22.15#flagr#flagr/antenna,new-source 2006.147.07:36:22.15:checkk5 2006.147.07:36:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:36:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:36:23.29/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:36:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:36:24.06/chk_obsdata//k5ts1/k06147_ts1_147-0735*_20??1470735??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:36:24.44/chk_obsdata//k5ts2/k06147_ts2_147-0735*_20??1470735??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:36:24.82/chk_obsdata//k5ts3/k06147_ts3_147-0735*_20??1470735??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:36:25.19/chk_obsdata//k5ts4/k06147_ts4_147-0735*_20??1470735??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:36:25.89/k5log//k5ts1_log_newline 2006.147.07:36:26.58/k5log//k5ts2_log_newline 2006.147.07:36:27.27/k5log//k5ts3_log_newline 2006.147.07:36:27.96/k5log//k5ts4_log_newline 2006.147.07:36:27.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:36:27.98:4f8m12a=1 2006.147.07:36:27.98$4f8m12a/echo=on 2006.147.07:36:27.98$4f8m12a/pcalon 2006.147.07:36:27.98$pcalon/"no phase cal control is implemented here 2006.147.07:36:27.98$4f8m12a/"tpicd=stop 2006.147.07:36:27.98$4f8m12a/vc4f8 2006.147.07:36:27.98$vc4f8/valo=1,532.99 2006.147.07:36:27.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:36:27.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:36:27.99#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:27.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:27.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:27.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:28.03#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:36:28.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:28.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:28.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:36:28.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:36:28.08$vc4f8/va=1,8 2006.147.07:36:28.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:36:28.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:36:28.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:28.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:28.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:28.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:28.12#ibcon#[25=AT01-08\r\n] 2006.147.07:36:28.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:28.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:28.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:36:28.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:28.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:28.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:28.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:28.28#ibcon#[25=USB\r\n] 2006.147.07:36:28.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:28.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:28.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:36:28.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:36:28.33$vc4f8/valo=2,572.99 2006.147.07:36:28.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:36:28.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:36:28.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:28.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:28.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:28.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:28.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:36:28.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:28.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:28.41#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:36:28.41#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:36:28.41$vc4f8/va=2,7 2006.147.07:36:28.41#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:36:28.41#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:36:28.41#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:28.41#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:28.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:28.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:28.46#ibcon#[25=AT02-07\r\n] 2006.147.07:36:28.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:28.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:28.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:36:28.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:28.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:28.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:28.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:28.63#ibcon#[25=USB\r\n] 2006.147.07:36:28.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:28.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:28.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:36:28.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:36:28.66$vc4f8/valo=3,672.99 2006.147.07:36:28.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:36:28.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:36:28.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:28.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:28.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:28.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:28.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:36:28.73#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:28.73#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:28.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:36:28.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:36:28.73$vc4f8/va=3,8 2006.147.07:36:28.73#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:36:28.73#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:36:28.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:28.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:28.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:28.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:28.80#ibcon#[25=AT03-08\r\n] 2006.147.07:36:28.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:28.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:28.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:36:28.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:28.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:28.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:28.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:28.97#ibcon#[25=USB\r\n] 2006.147.07:36:29.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:29.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:29.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:36:29.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:36:29.00$vc4f8/valo=4,832.99 2006.147.07:36:29.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:36:29.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:36:29.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:29.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:29.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:29.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:36:29.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:29.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:29.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:36:29.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:36:29.06$vc4f8/va=4,7 2006.147.07:36:29.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:36:29.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:36:29.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:29.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:29.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:29.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:29.14#ibcon#[25=AT04-07\r\n] 2006.147.07:36:29.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:29.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:29.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:36:29.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:29.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:29.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:29.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:29.31#ibcon#[25=USB\r\n] 2006.147.07:36:29.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:29.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:29.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:36:29.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:36:29.34$vc4f8/valo=5,652.99 2006.147.07:36:29.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:36:29.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:36:29.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:29.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:29.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:29.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:36:29.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:29.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:29.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:36:29.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:36:29.40$vc4f8/va=5,6 2006.147.07:36:29.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:36:29.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:36:29.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:29.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:29.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:29.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:29.48#ibcon#[25=AT05-06\r\n] 2006.147.07:36:29.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:29.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:29.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:36:29.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:29.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:29.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:29.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:29.65#ibcon#[25=USB\r\n] 2006.147.07:36:29.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:29.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:29.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:36:29.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:36:29.68$vc4f8/valo=6,772.99 2006.147.07:36:29.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:36:29.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:36:29.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:29.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:29.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:29.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:36:29.74#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:29.74#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:29.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:36:29.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:36:29.74$vc4f8/va=6,5 2006.147.07:36:29.74#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.07:36:29.74#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.07:36:29.74#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:29.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:29.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:29.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:29.82#ibcon#[25=AT06-05\r\n] 2006.147.07:36:29.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:29.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:29.85#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.07:36:29.85#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:29.85#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:36:29.97#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:36:29.97#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:36:29.99#ibcon#[25=USB\r\n] 2006.147.07:36:30.02#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:36:30.02#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:36:30.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:36:30.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:36:30.02$vc4f8/valo=7,832.99 2006.147.07:36:30.02#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:36:30.02#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:36:30.02#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:30.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:36:30.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:36:30.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:36:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:36:30.08#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:36:30.08#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:36:30.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:36:30.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:36:30.08$vc4f8/va=7,5 2006.147.07:36:30.08#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.07:36:30.08#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.07:36:30.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:30.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:36:30.15#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:36:30.15#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:36:30.16#ibcon#[25=AT07-05\r\n] 2006.147.07:36:30.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:36:30.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:36:30.19#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.07:36:30.19#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:30.19#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:36:30.31#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:36:30.31#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:36:30.33#ibcon#[25=USB\r\n] 2006.147.07:36:30.36#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:36:30.36#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:36:30.36#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:36:30.36#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:36:30.36$vc4f8/valo=8,852.99 2006.147.07:36:30.36#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:36:30.36#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:36:30.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:30.36#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:36:30.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:36:30.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:36:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:36:30.42#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:36:30.42#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:36:30.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:36:30.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:36:30.42$vc4f8/va=8,5 2006.147.07:36:30.42#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.07:36:30.42#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.07:36:30.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:30.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:36:30.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:36:30.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:36:30.50#ibcon#[25=AT08-05\r\n] 2006.147.07:36:30.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:36:30.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:36:30.53#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.07:36:30.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:30.53#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:36:30.65#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:36:30.65#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:36:30.67#ibcon#[25=USB\r\n] 2006.147.07:36:30.70#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:36:30.70#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:36:30.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:36:30.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:36:30.70$vc4f8/vblo=1,632.99 2006.147.07:36:30.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:36:30.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:36:30.70#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:30.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:36:30.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:36:30.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:36:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:36:30.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:36:30.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:36:30.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:36:30.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:36:30.76$vc4f8/vb=1,4 2006.147.07:36:30.76#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.07:36:30.76#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.07:36:30.76#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:30.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:36:30.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:36:30.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:36:30.78#ibcon#[27=AT01-04\r\n] 2006.147.07:36:30.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:36:30.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:36:30.81#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.07:36:30.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:30.81#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:36:30.93#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:36:30.93#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:36:30.95#ibcon#[27=USB\r\n] 2006.147.07:36:30.98#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:36:30.98#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:36:30.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:36:30.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:36:30.98$vc4f8/vblo=2,640.99 2006.147.07:36:30.98#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:36:30.98#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:36:30.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:30.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:30.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:30.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:36:31.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:31.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:36:31.04#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:36:31.04#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:36:31.04$vc4f8/vb=2,4 2006.147.07:36:31.04#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:36:31.04#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:36:31.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:31.04#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:31.10#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:31.10#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:31.12#ibcon#[27=AT02-04\r\n] 2006.147.07:36:31.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:31.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:36:31.15#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:36:31.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:31.15#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:31.27#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:31.27#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:31.29#ibcon#[27=USB\r\n] 2006.147.07:36:31.32#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:31.32#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:36:31.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:36:31.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:36:31.32$vc4f8/vblo=3,656.99 2006.147.07:36:31.32#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:36:31.32#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:36:31.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:31.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:31.32#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:31.32#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:36:31.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:31.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:36:31.38#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:36:31.38#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:36:31.38$vc4f8/vb=3,4 2006.147.07:36:31.38#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:36:31.38#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:36:31.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:31.38#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:31.44#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:31.44#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:31.46#ibcon#[27=AT03-04\r\n] 2006.147.07:36:31.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:31.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:36:31.49#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:36:31.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:31.49#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:31.61#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:31.61#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:31.63#ibcon#[27=USB\r\n] 2006.147.07:36:31.66#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:31.66#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:36:31.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:36:31.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:36:31.66$vc4f8/vblo=4,712.99 2006.147.07:36:31.66#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:36:31.66#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:36:31.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:31.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:31.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:31.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:36:31.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:31.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:36:31.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:36:31.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:36:31.72$vc4f8/vb=4,4 2006.147.07:36:31.72#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:36:31.72#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:36:31.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:31.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:31.78#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:31.78#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:31.80#ibcon#[27=AT04-04\r\n] 2006.147.07:36:31.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:31.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:36:31.83#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:36:31.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:31.83#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:31.95#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:31.95#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:31.97#ibcon#[27=USB\r\n] 2006.147.07:36:32.00#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:32.00#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:36:32.00#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:36:32.00#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:36:32.00$vc4f8/vblo=5,744.99 2006.147.07:36:32.00#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:36:32.00#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:36:32.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:32.00#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:32.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:32.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:36:32.06#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:32.06#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:36:32.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:36:32.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:36:32.06$vc4f8/vb=5,3 2006.147.07:36:32.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:36:32.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:36:32.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:32.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:32.12#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:32.12#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:32.14#ibcon#[27=AT05-03\r\n] 2006.147.07:36:32.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:32.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:36:32.17#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:36:32.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:32.17#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:32.29#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:32.29#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:32.31#ibcon#[27=USB\r\n] 2006.147.07:36:32.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:32.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:36:32.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:36:32.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:36:32.34$vc4f8/vblo=6,752.99 2006.147.07:36:32.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:36:32.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:36:32.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:36:32.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:32.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:32.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:36:32.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:32.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:36:32.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:36:32.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:36:32.40$vc4f8/vb=6,4 2006.147.07:36:32.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:36:32.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:36:32.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:36:32.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:32.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:32.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:32.48#ibcon#[27=AT06-04\r\n] 2006.147.07:36:32.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:32.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:36:32.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:36:32.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:36:32.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:32.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:32.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:32.65#ibcon#[27=USB\r\n] 2006.147.07:36:32.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:32.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:36:32.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:36:32.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:36:32.68$vc4f8/vabw=wide 2006.147.07:36:32.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:36:32.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:36:32.68#ibcon#ireg 8 cls_cnt 0 2006.147.07:36:32.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:32.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:32.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:32.70#ibcon#[25=BW32\r\n] 2006.147.07:36:32.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:32.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:36:32.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:36:32.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:36:32.73$vc4f8/vbbw=wide 2006.147.07:36:32.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:36:32.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:36:32.73#ibcon#ireg 8 cls_cnt 0 2006.147.07:36:32.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:36:32.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:36:32.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:36:32.82#ibcon#[27=BW32\r\n] 2006.147.07:36:32.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:36:32.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:36:32.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:36:32.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:36:32.85$4f8m12a/ifd4f 2006.147.07:36:32.85$ifd4f/lo= 2006.147.07:36:32.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:36:32.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:36:32.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:36:32.86$ifd4f/patch= 2006.147.07:36:32.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:36:32.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:36:32.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:36:32.86$4f8m12a/"form=m,16.000,1:2 2006.147.07:36:32.86$4f8m12a/"tpicd 2006.147.07:36:32.86$4f8m12a/echo=off 2006.147.07:36:32.86$4f8m12a/xlog=off 2006.147.07:36:32.86:!2006.147.07:37:00 2006.147.07:36:43.14#trakl#Source acquired 2006.147.07:36:45.14#flagr#flagr/antenna,acquired 2006.147.07:37:00.01:preob 2006.147.07:37:01.14/onsource/TRACKING 2006.147.07:37:01.15:!2006.147.07:37:10 2006.147.07:37:10.01:data_valid=on 2006.147.07:37:10.02:midob 2006.147.07:37:11.14/onsource/TRACKING 2006.147.07:37:11.15/wx/19.88,1011.4,80 2006.147.07:37:11.33/cable/+6.5374E-03 2006.147.07:37:12.42/va/01,08,usb,yes,30,32 2006.147.07:37:12.42/va/02,07,usb,yes,30,32 2006.147.07:37:12.42/va/03,08,usb,yes,22,23 2006.147.07:37:12.42/va/04,07,usb,yes,31,33 2006.147.07:37:12.42/va/05,06,usb,yes,34,36 2006.147.07:37:12.42/va/06,05,usb,yes,35,34 2006.147.07:37:12.42/va/07,05,usb,yes,35,34 2006.147.07:37:12.42/va/08,05,usb,yes,37,37 2006.147.07:37:12.65/valo/01,532.99,yes,locked 2006.147.07:37:12.65/valo/02,572.99,yes,locked 2006.147.07:37:12.65/valo/03,672.99,yes,locked 2006.147.07:37:12.65/valo/04,832.99,yes,locked 2006.147.07:37:12.65/valo/05,652.99,yes,locked 2006.147.07:37:12.65/valo/06,772.99,yes,locked 2006.147.07:37:12.65/valo/07,832.99,yes,locked 2006.147.07:37:12.65/valo/08,852.99,yes,locked 2006.147.07:37:13.74/vb/01,04,usb,yes,29,28 2006.147.07:37:13.74/vb/02,04,usb,yes,31,32 2006.147.07:37:13.74/vb/03,04,usb,yes,27,31 2006.147.07:37:13.74/vb/04,04,usb,yes,28,28 2006.147.07:37:13.74/vb/05,03,usb,yes,33,37 2006.147.07:37:13.74/vb/06,04,usb,yes,28,30 2006.147.07:37:13.74/vb/07,04,usb,yes,29,29 2006.147.07:37:13.74/vb/08,03,usb,yes,34,37 2006.147.07:37:13.97/vblo/01,632.99,yes,locked 2006.147.07:37:13.97/vblo/02,640.99,yes,locked 2006.147.07:37:13.97/vblo/03,656.99,yes,locked 2006.147.07:37:13.97/vblo/04,712.99,yes,locked 2006.147.07:37:13.97/vblo/05,744.99,yes,locked 2006.147.07:37:13.97/vblo/06,752.99,yes,locked 2006.147.07:37:13.97/vblo/07,734.99,yes,locked 2006.147.07:37:13.97/vblo/08,744.99,yes,locked 2006.147.07:37:14.12/vabw/8 2006.147.07:37:14.27/vbbw/8 2006.147.07:37:14.36/xfe/off,on,14.7 2006.147.07:37:14.73/ifatt/23,28,28,28 2006.147.07:37:15.07/fmout-gps/S +4.91E-07 2006.147.07:37:15.12:!2006.147.07:38:10 2006.147.07:38:10.01:data_valid=off 2006.147.07:38:10.02:postob 2006.147.07:38:10.17/cable/+6.5387E-03 2006.147.07:38:10.18/wx/19.87,1011.4,81 2006.147.07:38:11.07/fmout-gps/S +4.91E-07 2006.147.07:38:11.08:scan_name=147-0739,k06147,60 2006.147.07:38:11.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.147.07:38:12.14#flagr#flagr/antenna,new-source 2006.147.07:38:12.15:checkk5 2006.147.07:38:12.55/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:38:12.93/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:38:13.32/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:38:13.70/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:38:14.06/chk_obsdata//k5ts1/k06147_ts1_147-0737*_20??1470737??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:38:14.44/chk_obsdata//k5ts2/k06147_ts2_147-0737*_20??1470737??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:38:14.82/chk_obsdata//k5ts3/k06147_ts3_147-0737*_20??1470737??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:38:15.20/chk_obsdata//k5ts4/k06147_ts4_147-0737*_20??1470737??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:38:15.88/k5log//k5ts1_log_newline 2006.147.07:38:16.57/k5log//k5ts2_log_newline 2006.147.07:38:17.26/k5log//k5ts3_log_newline 2006.147.07:38:17.95/k5log//k5ts4_log_newline 2006.147.07:38:17.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:38:17.97:4f8m12a=1 2006.147.07:38:17.97$4f8m12a/echo=on 2006.147.07:38:17.97$4f8m12a/pcalon 2006.147.07:38:17.97$pcalon/"no phase cal control is implemented here 2006.147.07:38:17.97$4f8m12a/"tpicd=stop 2006.147.07:38:17.97$4f8m12a/vc4f8 2006.147.07:38:17.97$vc4f8/valo=1,532.99 2006.147.07:38:17.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:38:17.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:38:17.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:17.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:17.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:17.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:18.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:38:18.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:18.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:18.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:38:18.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:38:18.06$vc4f8/va=1,8 2006.147.07:38:18.06#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:38:18.06#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:38:18.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:18.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:18.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:18.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:18.10#ibcon#[25=AT01-08\r\n] 2006.147.07:38:18.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:18.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:18.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:38:18.13#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:18.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:18.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:18.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:18.27#ibcon#[25=USB\r\n] 2006.147.07:38:18.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:18.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:18.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:38:18.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:38:18.30$vc4f8/valo=2,572.99 2006.147.07:38:18.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:38:18.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:38:18.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:18.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:18.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:18.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:18.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:38:18.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:18.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:18.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:38:18.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:38:18.37$vc4f8/va=2,7 2006.147.07:38:18.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:38:18.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:38:18.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:18.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:18.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:18.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:18.44#ibcon#[25=AT02-07\r\n] 2006.147.07:38:18.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:18.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:18.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:38:18.47#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:18.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:18.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:18.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:18.61#ibcon#[25=USB\r\n] 2006.147.07:38:18.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:18.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:18.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:38:18.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:38:18.64$vc4f8/valo=3,672.99 2006.147.07:38:18.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:38:18.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:38:18.64#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:18.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:18.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:18.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:18.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:38:18.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:18.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:18.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:38:18.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:38:18.71$vc4f8/va=3,8 2006.147.07:38:18.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:38:18.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:38:18.71#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:18.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:18.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:18.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:18.78#ibcon#[25=AT03-08\r\n] 2006.147.07:38:18.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:18.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:18.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:38:18.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:18.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:18.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:18.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:18.95#ibcon#[25=USB\r\n] 2006.147.07:38:18.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:18.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:18.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:38:18.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:38:18.98$vc4f8/valo=4,832.99 2006.147.07:38:18.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:38:18.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:38:18.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:18.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:18.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:18.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:19.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:38:19.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:19.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:19.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:38:19.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:38:19.04$vc4f8/va=4,7 2006.147.07:38:19.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:38:19.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:38:19.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:19.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:19.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:19.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:19.12#ibcon#[25=AT04-07\r\n] 2006.147.07:38:19.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:19.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:19.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:38:19.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:19.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:19.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:19.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:19.29#ibcon#[25=USB\r\n] 2006.147.07:38:19.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:19.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:19.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:38:19.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:38:19.32$vc4f8/valo=5,652.99 2006.147.07:38:19.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.07:38:19.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.07:38:19.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:19.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:19.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:19.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:19.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:38:19.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:19.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:19.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:38:19.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:38:19.38$vc4f8/va=5,6 2006.147.07:38:19.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.07:38:19.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.07:38:19.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:19.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:19.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:19.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:19.46#ibcon#[25=AT05-06\r\n] 2006.147.07:38:19.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:19.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:19.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.07:38:19.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:19.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:19.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:19.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:19.63#ibcon#[25=USB\r\n] 2006.147.07:38:19.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:19.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:19.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:38:19.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:38:19.66$vc4f8/valo=6,772.99 2006.147.07:38:19.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:38:19.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:38:19.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:19.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:19.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:19.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:19.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:38:19.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:19.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:19.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:38:19.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:38:19.72$vc4f8/va=6,5 2006.147.07:38:19.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:38:19.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:38:19.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:19.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:19.78#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:19.78#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:19.80#ibcon#[25=AT06-05\r\n] 2006.147.07:38:19.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:19.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:19.83#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:38:19.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:19.83#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:38:19.95#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:38:19.95#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:38:19.97#ibcon#[25=USB\r\n] 2006.147.07:38:20.00#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:38:20.00#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:38:20.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:38:20.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:38:20.00$vc4f8/valo=7,832.99 2006.147.07:38:20.00#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:38:20.00#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:38:20.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:20.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:38:20.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:38:20.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:38:20.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:38:20.06#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:38:20.06#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:38:20.06#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:38:20.06#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:38:20.06$vc4f8/va=7,5 2006.147.07:38:20.06#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:38:20.06#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:38:20.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:20.06#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:38:20.12#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:38:20.12#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:38:20.14#ibcon#[25=AT07-05\r\n] 2006.147.07:38:20.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:38:20.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:38:20.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:38:20.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:20.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:38:20.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:38:20.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:38:20.31#ibcon#[25=USB\r\n] 2006.147.07:38:20.34#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:38:20.34#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:38:20.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:38:20.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:38:20.34$vc4f8/valo=8,852.99 2006.147.07:38:20.34#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:38:20.34#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:38:20.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:20.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:38:20.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:38:20.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:38:20.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:38:20.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:38:20.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:38:20.40#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:38:20.40#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:38:20.40$vc4f8/va=8,5 2006.147.07:38:20.40#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:38:20.40#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:38:20.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:20.40#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:38:20.46#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:38:20.46#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:38:20.48#ibcon#[25=AT08-05\r\n] 2006.147.07:38:20.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:38:20.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:38:20.51#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:38:20.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:20.51#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:38:20.63#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:38:20.63#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:38:20.65#ibcon#[25=USB\r\n] 2006.147.07:38:20.68#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:38:20.68#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:38:20.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:38:20.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:38:20.68$vc4f8/vblo=1,632.99 2006.147.07:38:20.68#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:38:20.68#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:38:20.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:20.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:38:20.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:38:20.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:38:20.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:38:20.74#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:38:20.74#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:38:20.74#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:38:20.74#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:38:20.74$vc4f8/vb=1,4 2006.147.07:38:20.74#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:38:20.74#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:38:20.74#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:20.74#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:38:20.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:38:20.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:38:20.76#ibcon#[27=AT01-04\r\n] 2006.147.07:38:20.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:38:20.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:38:20.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:38:20.79#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:20.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:38:20.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:38:20.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:38:20.93#ibcon#[27=USB\r\n] 2006.147.07:38:20.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:38:20.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:38:20.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:38:20.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:38:20.96$vc4f8/vblo=2,640.99 2006.147.07:38:20.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:38:20.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:38:20.96#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:20.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:20.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:20.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:20.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:38:21.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:21.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:38:21.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:38:21.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:38:21.02$vc4f8/vb=2,4 2006.147.07:38:21.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:38:21.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:38:21.02#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:21.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:21.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:21.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:21.10#ibcon#[27=AT02-04\r\n] 2006.147.07:38:21.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:21.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:38:21.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:38:21.13#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:21.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:21.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:21.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:21.27#ibcon#[27=USB\r\n] 2006.147.07:38:21.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:21.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:38:21.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:38:21.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:38:21.30$vc4f8/vblo=3,656.99 2006.147.07:38:21.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:38:21.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:38:21.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:21.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:21.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:21.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:21.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:38:21.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:21.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:38:21.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:38:21.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:38:21.36$vc4f8/vb=3,4 2006.147.07:38:21.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:38:21.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:38:21.36#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:21.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:21.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:21.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:21.44#ibcon#[27=AT03-04\r\n] 2006.147.07:38:21.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:21.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:38:21.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:38:21.47#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:21.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:21.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:21.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:21.61#ibcon#[27=USB\r\n] 2006.147.07:38:21.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:21.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:38:21.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:38:21.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:38:21.64$vc4f8/vblo=4,712.99 2006.147.07:38:21.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:38:21.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:38:21.64#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:21.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:21.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:21.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:21.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:38:21.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:21.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:38:21.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:38:21.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:38:21.70$vc4f8/vb=4,4 2006.147.07:38:21.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:38:21.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:38:21.70#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:21.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:21.77#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:21.77#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:21.78#ibcon#[27=AT04-04\r\n] 2006.147.07:38:21.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:21.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:38:21.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:38:21.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:21.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:21.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:21.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:21.95#ibcon#[27=USB\r\n] 2006.147.07:38:21.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:21.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:38:21.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:38:21.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:38:21.98$vc4f8/vblo=5,744.99 2006.147.07:38:21.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:38:21.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:38:21.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:21.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:21.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:21.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:22.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:38:22.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:22.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:38:22.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:38:22.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:38:22.04$vc4f8/vb=5,3 2006.147.07:38:22.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:38:22.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:38:22.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:22.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:22.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:22.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:22.12#ibcon#[27=AT05-03\r\n] 2006.147.07:38:22.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:22.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:38:22.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:38:22.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:22.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:22.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:22.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:22.29#ibcon#[27=USB\r\n] 2006.147.07:38:22.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:22.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:38:22.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:38:22.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:38:22.32$vc4f8/vblo=6,752.99 2006.147.07:38:22.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.07:38:22.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.07:38:22.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:38:22.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:22.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:22.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:22.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:38:22.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:22.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:38:22.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:38:22.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:38:22.38$vc4f8/vb=6,4 2006.147.07:38:22.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.07:38:22.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.07:38:22.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:38:22.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:22.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:22.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:22.46#ibcon#[27=AT06-04\r\n] 2006.147.07:38:22.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:22.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:38:22.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.07:38:22.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:38:22.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:22.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:22.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:22.63#ibcon#[27=USB\r\n] 2006.147.07:38:22.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:22.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:38:22.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:38:22.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:38:22.66$vc4f8/vabw=wide 2006.147.07:38:22.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:38:22.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:38:22.66#ibcon#ireg 8 cls_cnt 0 2006.147.07:38:22.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:22.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:22.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:22.68#ibcon#[25=BW32\r\n] 2006.147.07:38:22.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:22.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:38:22.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:38:22.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:38:22.71$vc4f8/vbbw=wide 2006.147.07:38:22.71#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:38:22.71#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:38:22.71#ibcon#ireg 8 cls_cnt 0 2006.147.07:38:22.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:38:22.79#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:38:22.79#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:38:22.80#ibcon#[27=BW32\r\n] 2006.147.07:38:22.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:38:22.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:38:22.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:38:22.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:38:22.83$4f8m12a/ifd4f 2006.147.07:38:22.83$ifd4f/lo= 2006.147.07:38:22.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:38:22.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:38:22.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:38:22.84$ifd4f/patch= 2006.147.07:38:22.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:38:22.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:38:22.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:38:22.84$4f8m12a/"form=m,16.000,1:2 2006.147.07:38:22.84$4f8m12a/"tpicd 2006.147.07:38:22.84$4f8m12a/echo=off 2006.147.07:38:22.84$4f8m12a/xlog=off 2006.147.07:38:22.84:!2006.147.07:38:50 2006.147.07:38:36.14#trakl#Source acquired 2006.147.07:38:38.14#flagr#flagr/antenna,acquired 2006.147.07:38:50.01:preob 2006.147.07:38:51.14/onsource/TRACKING 2006.147.07:38:51.14:!2006.147.07:39:00 2006.147.07:39:00.00:data_valid=on 2006.147.07:39:00.00:midob 2006.147.07:39:00.14/onsource/TRACKING 2006.147.07:39:00.15/wx/19.86,1011.4,81 2006.147.07:39:00.25/cable/+6.5373E-03 2006.147.07:39:01.34/va/01,08,usb,yes,36,38 2006.147.07:39:01.34/va/02,07,usb,yes,36,38 2006.147.07:39:01.34/va/03,08,usb,yes,27,28 2006.147.07:39:01.34/va/04,07,usb,yes,37,40 2006.147.07:39:01.34/va/05,06,usb,yes,42,44 2006.147.07:39:01.34/va/06,05,usb,yes,42,42 2006.147.07:39:01.34/va/07,05,usb,yes,42,42 2006.147.07:39:01.34/va/08,05,usb,yes,45,44 2006.147.07:39:01.57/valo/01,532.99,yes,locked 2006.147.07:39:01.57/valo/02,572.99,yes,locked 2006.147.07:39:01.57/valo/03,672.99,yes,locked 2006.147.07:39:01.57/valo/04,832.99,yes,locked 2006.147.07:39:01.57/valo/05,652.99,yes,locked 2006.147.07:39:01.57/valo/06,772.99,yes,locked 2006.147.07:39:01.57/valo/07,832.99,yes,locked 2006.147.07:39:01.57/valo/08,852.99,yes,locked 2006.147.07:39:02.66/vb/01,04,usb,yes,32,30 2006.147.07:39:02.66/vb/02,04,usb,yes,34,35 2006.147.07:39:02.66/vb/03,04,usb,yes,30,34 2006.147.07:39:02.66/vb/04,04,usb,yes,31,31 2006.147.07:39:02.66/vb/05,03,usb,yes,37,41 2006.147.07:39:02.66/vb/06,04,usb,yes,31,34 2006.147.07:39:02.66/vb/07,04,usb,yes,33,32 2006.147.07:39:02.66/vb/08,03,usb,yes,37,41 2006.147.07:39:02.89/vblo/01,632.99,yes,locked 2006.147.07:39:02.89/vblo/02,640.99,yes,locked 2006.147.07:39:02.89/vblo/03,656.99,yes,locked 2006.147.07:39:02.89/vblo/04,712.99,yes,locked 2006.147.07:39:02.89/vblo/05,744.99,yes,locked 2006.147.07:39:02.89/vblo/06,752.99,yes,locked 2006.147.07:39:02.89/vblo/07,734.99,yes,locked 2006.147.07:39:02.89/vblo/08,744.99,yes,locked 2006.147.07:39:03.04/vabw/8 2006.147.07:39:03.19/vbbw/8 2006.147.07:39:03.28/xfe/off,on,15.2 2006.147.07:39:03.67/ifatt/23,28,28,28 2006.147.07:39:04.07/fmout-gps/S +4.91E-07 2006.147.07:39:04.12:!2006.147.07:40:00 2006.147.07:40:00.01:data_valid=off 2006.147.07:40:00.02:postob 2006.147.07:40:00.16/cable/+6.5364E-03 2006.147.07:40:00.17/wx/19.85,1011.4,80 2006.147.07:40:01.07/fmout-gps/S +4.92E-07 2006.147.07:40:01.08:scan_name=147-0741,k06147,60 2006.147.07:40:01.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.147.07:40:01.14#flagr#flagr/antenna,new-source 2006.147.07:40:02.14:checkk5 2006.147.07:40:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:40:02.92/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:40:03.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:40:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:40:04.05/chk_obsdata//k5ts1/k06147_ts1_147-0739*_20??1470739??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:40:04.42/chk_obsdata//k5ts2/k06147_ts2_147-0739*_20??1470739??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:40:04.81/chk_obsdata//k5ts3/k06147_ts3_147-0739*_20??1470739??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:40:05.19/chk_obsdata//k5ts4/k06147_ts4_147-0739*_20??1470739??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:40:05.88/k5log//k5ts1_log_newline 2006.147.07:40:06.57/k5log//k5ts2_log_newline 2006.147.07:40:07.26/k5log//k5ts3_log_newline 2006.147.07:40:07.95/k5log//k5ts4_log_newline 2006.147.07:40:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:40:07.97:4f8m12a=1 2006.147.07:40:07.97$4f8m12a/echo=on 2006.147.07:40:07.97$4f8m12a/pcalon 2006.147.07:40:07.97$pcalon/"no phase cal control is implemented here 2006.147.07:40:07.97$4f8m12a/"tpicd=stop 2006.147.07:40:07.97$4f8m12a/vc4f8 2006.147.07:40:07.97$vc4f8/valo=1,532.99 2006.147.07:40:07.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:40:07.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:40:07.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:07.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:07.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:07.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:40:08.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:08.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:08.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:40:08.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:40:08.06$vc4f8/va=1,8 2006.147.07:40:08.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.07:40:08.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.07:40:08.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:08.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:08.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:08.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:08.10#ibcon#[25=AT01-08\r\n] 2006.147.07:40:08.13#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:08.13#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:08.13#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.07:40:08.13#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:08.13#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:08.25#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:08.25#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:08.27#ibcon#[25=USB\r\n] 2006.147.07:40:08.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:08.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:08.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:40:08.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:40:08.32$vc4f8/valo=2,572.99 2006.147.07:40:08.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.07:40:08.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.07:40:08.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:08.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:08.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:08.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:08.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:40:08.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:08.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:08.40#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:40:08.40#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:40:08.40$vc4f8/va=2,7 2006.147.07:40:08.40#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.07:40:08.40#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.07:40:08.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:08.40#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:08.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:08.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:08.45#ibcon#[25=AT02-07\r\n] 2006.147.07:40:08.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:08.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:08.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.07:40:08.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:08.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:08.60#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:08.60#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:08.62#ibcon#[25=USB\r\n] 2006.147.07:40:08.68#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:08.68#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:08.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:40:08.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:40:08.68$vc4f8/valo=3,672.99 2006.147.07:40:08.68#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.07:40:08.68#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.07:40:08.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:08.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:08.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:08.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:08.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:40:08.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:08.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:08.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:40:08.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:40:08.73$vc4f8/va=3,8 2006.147.07:40:08.73#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.07:40:08.73#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.07:40:08.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:08.73#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:08.80#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:08.80#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:08.82#ibcon#[25=AT03-08\r\n] 2006.147.07:40:08.85#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:08.85#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:08.85#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.07:40:08.85#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:08.85#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:08.97#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:08.97#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:08.99#ibcon#[25=USB\r\n] 2006.147.07:40:09.02#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:09.02#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:09.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:40:09.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:40:09.02$vc4f8/valo=4,832.99 2006.147.07:40:09.02#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.07:40:09.02#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.07:40:09.02#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:09.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:09.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:09.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:09.04#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:40:09.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:09.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:09.08#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:40:09.08#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:40:09.08$vc4f8/va=4,7 2006.147.07:40:09.08#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.07:40:09.08#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.07:40:09.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:09.08#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:09.14#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:09.14#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:09.16#ibcon#[25=AT04-07\r\n] 2006.147.07:40:09.19#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:09.19#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:09.19#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.07:40:09.19#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:09.19#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:09.31#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:09.31#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:09.33#ibcon#[25=USB\r\n] 2006.147.07:40:09.36#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:09.36#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:09.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:40:09.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:40:09.36$vc4f8/valo=5,652.99 2006.147.07:40:09.36#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:40:09.36#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:40:09.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:09.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:09.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:09.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:09.38#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:40:09.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:09.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:09.42#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:40:09.42#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:40:09.42$vc4f8/va=5,6 2006.147.07:40:09.42#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:40:09.42#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:40:09.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:09.42#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:09.47#abcon#<5=/07 3.2 6.3 19.85 801011.4\r\n> 2006.147.07:40:09.48#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:09.48#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:09.49#abcon#{5=INTERFACE CLEAR} 2006.147.07:40:09.50#ibcon#[25=AT05-06\r\n] 2006.147.07:40:09.53#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:09.53#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:09.53#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:40:09.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:09.53#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:09.55#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:40:09.65#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:09.65#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:09.67#ibcon#[25=USB\r\n] 2006.147.07:40:09.70#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:09.70#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:09.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:40:09.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:40:09.70$vc4f8/valo=6,772.99 2006.147.07:40:09.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.07:40:09.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.07:40:09.70#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:09.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:09.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:09.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:09.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:40:09.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:09.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:09.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:40:09.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:40:09.76$vc4f8/va=6,5 2006.147.07:40:09.76#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.07:40:09.76#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.07:40:09.76#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:09.76#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:09.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:09.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:09.84#ibcon#[25=AT06-05\r\n] 2006.147.07:40:09.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:09.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:09.87#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.07:40:09.87#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:09.87#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:40:09.99#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:40:09.99#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:40:10.01#ibcon#[25=USB\r\n] 2006.147.07:40:10.04#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:40:10.04#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:40:10.04#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:40:10.04#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:40:10.04$vc4f8/valo=7,832.99 2006.147.07:40:10.04#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.07:40:10.04#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.07:40:10.04#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:10.04#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:40:10.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:40:10.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:40:10.06#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:40:10.10#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:40:10.10#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:40:10.10#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:40:10.10#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:40:10.10$vc4f8/va=7,5 2006.147.07:40:10.10#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.07:40:10.10#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.07:40:10.10#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:10.10#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:40:10.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:40:10.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:40:10.18#ibcon#[25=AT07-05\r\n] 2006.147.07:40:10.21#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:40:10.21#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:40:10.21#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.07:40:10.21#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:10.21#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:40:10.33#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:40:10.33#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:40:10.35#ibcon#[25=USB\r\n] 2006.147.07:40:10.38#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:40:10.38#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:40:10.38#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:40:10.38#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:40:10.38$vc4f8/valo=8,852.99 2006.147.07:40:10.38#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:40:10.38#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:40:10.38#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:10.38#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:40:10.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:40:10.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:40:10.40#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:40:10.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:40:10.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:40:10.44#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:40:10.44#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:40:10.44$vc4f8/va=8,5 2006.147.07:40:10.44#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.07:40:10.44#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.07:40:10.44#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:10.44#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:40:10.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:40:10.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:40:10.52#ibcon#[25=AT08-05\r\n] 2006.147.07:40:10.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:40:10.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:40:10.55#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.07:40:10.55#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:10.55#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:40:10.67#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:40:10.67#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:40:10.69#ibcon#[25=USB\r\n] 2006.147.07:40:10.72#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:40:10.72#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:40:10.72#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:40:10.72#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:40:10.72$vc4f8/vblo=1,632.99 2006.147.07:40:10.72#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:40:10.72#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:40:10.72#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:10.72#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:10.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:10.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:10.74#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:40:10.78#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:10.78#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:40:10.78#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:40:10.78#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:40:10.78$vc4f8/vb=1,4 2006.147.07:40:10.78#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.07:40:10.78#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.07:40:10.78#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:10.78#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:10.78#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:10.78#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:10.80#ibcon#[27=AT01-04\r\n] 2006.147.07:40:10.83#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:10.83#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:40:10.83#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.07:40:10.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:10.83#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:10.95#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:10.95#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:10.97#ibcon#[27=USB\r\n] 2006.147.07:40:11.00#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:11.00#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:40:11.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:40:11.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:40:11.00$vc4f8/vblo=2,640.99 2006.147.07:40:11.00#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.07:40:11.00#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.07:40:11.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:11.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:11.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:11.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:11.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:40:11.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:11.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:40:11.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:40:11.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:40:11.06$vc4f8/vb=2,4 2006.147.07:40:11.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.07:40:11.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.07:40:11.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:11.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:11.12#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:11.12#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:11.14#ibcon#[27=AT02-04\r\n] 2006.147.07:40:11.17#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:11.17#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:40:11.17#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.07:40:11.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:11.17#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:11.29#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:11.29#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:11.31#ibcon#[27=USB\r\n] 2006.147.07:40:11.34#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:11.34#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:40:11.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:40:11.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:40:11.34$vc4f8/vblo=3,656.99 2006.147.07:40:11.34#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.07:40:11.34#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.07:40:11.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:11.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:11.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:11.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:11.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:40:11.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:11.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:40:11.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:40:11.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:40:11.40$vc4f8/vb=3,4 2006.147.07:40:11.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.07:40:11.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.07:40:11.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:11.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:11.46#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:11.46#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:11.48#ibcon#[27=AT03-04\r\n] 2006.147.07:40:11.51#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:11.51#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:40:11.51#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.07:40:11.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:11.51#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:11.63#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:11.63#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:11.65#ibcon#[27=USB\r\n] 2006.147.07:40:11.68#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:11.68#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:40:11.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:40:11.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:40:11.68$vc4f8/vblo=4,712.99 2006.147.07:40:11.68#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.07:40:11.68#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.07:40:11.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:11.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:11.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:11.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:11.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:40:11.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:11.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:40:11.74#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:40:11.74#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:40:11.74$vc4f8/vb=4,4 2006.147.07:40:11.74#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.07:40:11.74#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.07:40:11.74#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:11.74#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:11.80#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:11.80#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:11.82#ibcon#[27=AT04-04\r\n] 2006.147.07:40:11.85#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:11.85#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:40:11.85#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.07:40:11.85#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:11.85#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:11.97#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:11.97#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:11.99#ibcon#[27=USB\r\n] 2006.147.07:40:12.02#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:12.02#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:40:12.02#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:40:12.02#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:40:12.02$vc4f8/vblo=5,744.99 2006.147.07:40:12.02#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:40:12.02#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:40:12.02#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:12.02#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:12.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:12.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:12.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:40:12.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:12.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:40:12.08#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:40:12.08#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:40:12.08$vc4f8/vb=5,3 2006.147.07:40:12.08#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:40:12.08#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:40:12.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:12.08#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:12.14#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:12.14#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:12.16#ibcon#[27=AT05-03\r\n] 2006.147.07:40:12.19#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:12.19#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:40:12.19#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:40:12.19#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:12.19#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:12.31#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:12.31#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:12.33#ibcon#[27=USB\r\n] 2006.147.07:40:12.36#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:12.36#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:40:12.36#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:40:12.36#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:40:12.36$vc4f8/vblo=6,752.99 2006.147.07:40:12.36#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:40:12.36#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:40:12.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:40:12.36#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:40:12.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:40:12.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:40:12.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:40:12.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:40:12.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:40:12.42#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:40:12.42#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:40:12.42$vc4f8/vb=6,4 2006.147.07:40:12.42#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.07:40:12.42#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.07:40:12.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:40:12.42#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:40:12.48#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:40:12.48#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:40:12.50#ibcon#[27=AT06-04\r\n] 2006.147.07:40:12.53#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:40:12.53#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:40:12.53#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.07:40:12.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:40:12.53#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:40:12.65#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:40:12.65#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:40:12.67#ibcon#[27=USB\r\n] 2006.147.07:40:12.70#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:40:12.70#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:40:12.70#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:40:12.70#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:40:12.70$vc4f8/vabw=wide 2006.147.07:40:12.70#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.07:40:12.70#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.07:40:12.70#ibcon#ireg 8 cls_cnt 0 2006.147.07:40:12.70#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:12.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:12.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:12.72#ibcon#[25=BW32\r\n] 2006.147.07:40:12.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:12.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:40:12.75#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:40:12.75#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:40:12.75$vc4f8/vbbw=wide 2006.147.07:40:12.75#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:40:12.75#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:40:12.75#ibcon#ireg 8 cls_cnt 0 2006.147.07:40:12.75#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:40:12.82#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:40:12.82#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:40:12.84#ibcon#[27=BW32\r\n] 2006.147.07:40:12.87#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:40:12.87#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:40:12.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:40:12.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:40:12.87$4f8m12a/ifd4f 2006.147.07:40:12.87$ifd4f/lo= 2006.147.07:40:12.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:40:12.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:40:12.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:40:12.87$ifd4f/patch= 2006.147.07:40:12.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:40:12.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:40:12.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:40:12.88$4f8m12a/"form=m,16.000,1:2 2006.147.07:40:12.88$4f8m12a/"tpicd 2006.147.07:40:12.88$4f8m12a/echo=off 2006.147.07:40:12.88$4f8m12a/xlog=off 2006.147.07:40:12.88:!2006.147.07:40:50 2006.147.07:40:28.14#trakl#Source acquired 2006.147.07:40:28.14#flagr#flagr/antenna,acquired 2006.147.07:40:50.01:preob 2006.147.07:40:51.13/onsource/TRACKING 2006.147.07:40:51.13:!2006.147.07:41:00 2006.147.07:41:00.00:data_valid=on 2006.147.07:41:00.00:midob 2006.147.07:41:00.13/onsource/TRACKING 2006.147.07:41:00.13/wx/19.84,1011.4,80 2006.147.07:41:00.32/cable/+6.5349E-03 2006.147.07:41:01.41/va/01,08,usb,yes,30,32 2006.147.07:41:01.41/va/02,07,usb,yes,31,32 2006.147.07:41:01.41/va/03,08,usb,yes,23,23 2006.147.07:41:01.41/va/04,07,usb,yes,31,34 2006.147.07:41:01.41/va/05,06,usb,yes,35,37 2006.147.07:41:01.41/va/06,05,usb,yes,35,35 2006.147.07:41:01.41/va/07,05,usb,yes,35,35 2006.147.07:41:01.41/va/08,05,usb,yes,38,37 2006.147.07:41:01.64/valo/01,532.99,yes,locked 2006.147.07:41:01.64/valo/02,572.99,yes,locked 2006.147.07:41:01.64/valo/03,672.99,yes,locked 2006.147.07:41:01.64/valo/04,832.99,yes,locked 2006.147.07:41:01.64/valo/05,652.99,yes,locked 2006.147.07:41:01.64/valo/06,772.99,yes,locked 2006.147.07:41:01.64/valo/07,832.99,yes,locked 2006.147.07:41:01.64/valo/08,852.99,yes,locked 2006.147.07:41:02.73/vb/01,04,usb,yes,28,27 2006.147.07:41:02.73/vb/02,04,usb,yes,30,32 2006.147.07:41:02.73/vb/03,04,usb,yes,27,30 2006.147.07:41:02.73/vb/04,04,usb,yes,27,28 2006.147.07:41:02.73/vb/05,03,usb,yes,33,37 2006.147.07:41:02.73/vb/06,04,usb,yes,27,30 2006.147.07:41:02.73/vb/07,04,usb,yes,29,29 2006.147.07:41:02.73/vb/08,03,usb,yes,33,37 2006.147.07:41:02.96/vblo/01,632.99,yes,locked 2006.147.07:41:02.96/vblo/02,640.99,yes,locked 2006.147.07:41:02.96/vblo/03,656.99,yes,locked 2006.147.07:41:02.96/vblo/04,712.99,yes,locked 2006.147.07:41:02.96/vblo/05,744.99,yes,locked 2006.147.07:41:02.96/vblo/06,752.99,yes,locked 2006.147.07:41:02.96/vblo/07,734.99,yes,locked 2006.147.07:41:02.96/vblo/08,744.99,yes,locked 2006.147.07:41:03.11/vabw/8 2006.147.07:41:03.26/vbbw/8 2006.147.07:41:03.36/xfe/off,on,15.2 2006.147.07:41:03.75/ifatt/23,28,28,28 2006.147.07:41:04.07/fmout-gps/S +4.92E-07 2006.147.07:41:04.11:!2006.147.07:42:00 2006.147.07:42:00.01:data_valid=off 2006.147.07:42:00.02:postob 2006.147.07:42:00.21/cable/+6.5377E-03 2006.147.07:42:00.22/wx/19.83,1011.4,80 2006.147.07:42:01.07/fmout-gps/S +4.93E-07 2006.147.07:42:01.08:scan_name=147-0742,k06147,60 2006.147.07:42:01.08:source=0955+476,095819.67,472507.8,2000.0,cw 2006.147.07:42:02.13#flagr#flagr/antenna,new-source 2006.147.07:42:02.14:checkk5 2006.147.07:42:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:42:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:42:03.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:42:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:42:04.05/chk_obsdata//k5ts1/k06147_ts1_147-0741*_20??1470741??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:42:04.42/chk_obsdata//k5ts2/k06147_ts2_147-0741*_20??1470741??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:42:04.80/chk_obsdata//k5ts3/k06147_ts3_147-0741*_20??1470741??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:42:05.18/chk_obsdata//k5ts4/k06147_ts4_147-0741*_20??1470741??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:42:05.88/k5log//k5ts1_log_newline 2006.147.07:42:06.57/k5log//k5ts2_log_newline 2006.147.07:42:07.26/k5log//k5ts3_log_newline 2006.147.07:42:07.95/k5log//k5ts4_log_newline 2006.147.07:42:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:42:07.97:4f8m12a=1 2006.147.07:42:07.97$4f8m12a/echo=on 2006.147.07:42:07.97$4f8m12a/pcalon 2006.147.07:42:07.97$pcalon/"no phase cal control is implemented here 2006.147.07:42:07.97$4f8m12a/"tpicd=stop 2006.147.07:42:07.97$4f8m12a/vc4f8 2006.147.07:42:07.97$vc4f8/valo=1,532.99 2006.147.07:42:07.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:42:07.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:42:07.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:07.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:07.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:07.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:42:08.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:08.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:08.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:42:08.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:42:08.07$vc4f8/va=1,8 2006.147.07:42:08.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.07:42:08.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.07:42:08.07#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:08.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:08.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:08.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:08.10#ibcon#[25=AT01-08\r\n] 2006.147.07:42:08.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:08.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:08.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.07:42:08.13#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:08.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:08.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:08.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:08.27#ibcon#[25=USB\r\n] 2006.147.07:42:08.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:08.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:08.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:42:08.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:42:08.30$vc4f8/valo=2,572.99 2006.147.07:42:08.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.07:42:08.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.07:42:08.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:08.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:08.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:08.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:08.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:42:08.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:08.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:08.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:42:08.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:42:08.38$vc4f8/va=2,7 2006.147.07:42:08.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.07:42:08.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.07:42:08.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:08.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:08.43#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:08.43#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:08.44#ibcon#[25=AT02-07\r\n] 2006.147.07:42:08.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:08.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:08.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.07:42:08.47#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:08.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:08.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:08.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:08.61#ibcon#[25=USB\r\n] 2006.147.07:42:08.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:08.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:08.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:42:08.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:42:08.64$vc4f8/valo=3,672.99 2006.147.07:42:08.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.07:42:08.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.07:42:08.64#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:08.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:08.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:08.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:08.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:42:08.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:08.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:08.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:42:08.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:42:08.72$vc4f8/va=3,8 2006.147.07:42:08.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.07:42:08.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.07:42:08.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:08.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:08.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:08.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:08.78#ibcon#[25=AT03-08\r\n] 2006.147.07:42:08.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:08.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:08.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.07:42:08.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:08.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:08.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:08.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:08.95#ibcon#[25=USB\r\n] 2006.147.07:42:08.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:08.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:08.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:42:08.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:42:08.98$vc4f8/valo=4,832.99 2006.147.07:42:08.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.07:42:08.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.07:42:08.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:08.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:42:08.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:42:08.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:42:09.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:42:09.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:42:09.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:42:09.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:42:09.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:42:09.04$vc4f8/va=4,7 2006.147.07:42:09.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.07:42:09.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.07:42:09.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:09.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:42:09.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:42:09.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:42:09.12#ibcon#[25=AT04-07\r\n] 2006.147.07:42:09.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:42:09.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:42:09.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.07:42:09.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:09.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:42:09.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:42:09.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:42:09.29#ibcon#[25=USB\r\n] 2006.147.07:42:09.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:42:09.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:42:09.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:42:09.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:42:09.32$vc4f8/valo=5,652.99 2006.147.07:42:09.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:42:09.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:42:09.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:09.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:09.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:09.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:09.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:42:09.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:09.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:09.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:42:09.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:42:09.38$vc4f8/va=5,6 2006.147.07:42:09.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:42:09.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:42:09.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:09.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:09.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:09.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:09.46#ibcon#[25=AT05-06\r\n] 2006.147.07:42:09.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:09.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:09.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:42:09.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:09.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:09.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:09.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:09.63#ibcon#[25=USB\r\n] 2006.147.07:42:09.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:09.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:09.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:42:09.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:42:09.66$vc4f8/valo=6,772.99 2006.147.07:42:09.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:42:09.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:42:09.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:09.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:09.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:09.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:09.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:42:09.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:09.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:09.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:42:09.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:42:09.72$vc4f8/va=6,5 2006.147.07:42:09.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:42:09.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:42:09.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:09.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:09.78#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:09.78#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:09.80#ibcon#[25=AT06-05\r\n] 2006.147.07:42:09.83#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:09.83#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:09.83#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:42:09.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:09.83#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:09.95#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:09.95#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:09.97#ibcon#[25=USB\r\n] 2006.147.07:42:10.00#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:10.00#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:10.00#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:42:10.00#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:42:10.00$vc4f8/valo=7,832.99 2006.147.07:42:10.00#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:42:10.00#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:42:10.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:10.00#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:10.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:10.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:10.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:42:10.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:10.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:10.06#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:42:10.06#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:42:10.06$vc4f8/va=7,5 2006.147.07:42:10.06#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.07:42:10.06#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.07:42:10.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:10.06#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:10.12#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:10.12#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:10.14#ibcon#[25=AT07-05\r\n] 2006.147.07:42:10.17#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:10.17#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:10.17#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.07:42:10.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:10.17#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:42:10.29#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:42:10.29#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:42:10.31#ibcon#[25=USB\r\n] 2006.147.07:42:10.34#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:42:10.34#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:42:10.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:42:10.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:42:10.34$vc4f8/valo=8,852.99 2006.147.07:42:10.34#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:42:10.34#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:42:10.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:10.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:42:10.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:42:10.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:42:10.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:42:10.41#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:42:10.41#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:42:10.41#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:42:10.41#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:42:10.41$vc4f8/va=8,5 2006.147.07:42:10.41#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.07:42:10.41#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.07:42:10.41#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:10.41#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:42:10.46#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:42:10.46#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:42:10.48#ibcon#[25=AT08-05\r\n] 2006.147.07:42:10.51#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:42:10.51#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:42:10.51#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.07:42:10.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:10.51#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:42:10.63#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:42:10.63#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:42:10.65#ibcon#[25=USB\r\n] 2006.147.07:42:10.68#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:42:10.68#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:42:10.68#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:42:10.68#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:42:10.68$vc4f8/vblo=1,632.99 2006.147.07:42:10.68#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:42:10.68#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:42:10.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:10.68#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:42:10.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:42:10.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:42:10.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:42:10.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:42:10.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:42:10.74#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:42:10.74#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:42:10.74$vc4f8/vb=1,4 2006.147.07:42:10.74#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.07:42:10.74#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.07:42:10.74#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:10.74#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:42:10.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:42:10.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:42:10.76#ibcon#[27=AT01-04\r\n] 2006.147.07:42:10.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:42:10.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:42:10.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.07:42:10.79#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:10.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:42:10.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:42:10.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:42:10.93#ibcon#[27=USB\r\n] 2006.147.07:42:10.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:42:10.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:42:10.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:42:10.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:42:10.96$vc4f8/vblo=2,640.99 2006.147.07:42:10.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:42:10.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:42:10.96#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:10.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:10.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:10.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:10.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:42:11.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:11.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:42:11.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:42:11.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:42:11.02$vc4f8/vb=2,4 2006.147.07:42:11.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.07:42:11.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.07:42:11.02#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:11.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:11.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:11.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:11.10#ibcon#[27=AT02-04\r\n] 2006.147.07:42:11.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:11.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:42:11.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.07:42:11.13#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:11.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:11.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:11.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:11.27#ibcon#[27=USB\r\n] 2006.147.07:42:11.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:11.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:42:11.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:42:11.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:42:11.30$vc4f8/vblo=3,656.99 2006.147.07:42:11.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.07:42:11.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.07:42:11.30#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:11.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:11.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:11.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:11.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:42:11.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:11.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:42:11.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:42:11.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:42:11.36$vc4f8/vb=3,4 2006.147.07:42:11.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.07:42:11.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.07:42:11.36#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:11.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:11.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:11.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:11.44#ibcon#[27=AT03-04\r\n] 2006.147.07:42:11.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:11.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:42:11.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.07:42:11.47#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:11.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:11.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:11.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:11.61#ibcon#[27=USB\r\n] 2006.147.07:42:11.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:11.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:42:11.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:42:11.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:42:11.64$vc4f8/vblo=4,712.99 2006.147.07:42:11.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.07:42:11.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.07:42:11.64#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:11.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:11.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:11.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:11.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:42:11.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:11.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:42:11.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:42:11.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:42:11.70$vc4f8/vb=4,4 2006.147.07:42:11.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.07:42:11.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.07:42:11.70#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:11.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:11.76#abcon#<5=/07 3.1 5.9 19.83 801011.4\r\n> 2006.147.07:42:11.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:11.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:11.78#ibcon#[27=AT04-04\r\n] 2006.147.07:42:11.78#abcon#{5=INTERFACE CLEAR} 2006.147.07:42:11.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:11.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:42:11.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.07:42:11.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:11.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:11.84#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:42:11.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:11.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:11.95#ibcon#[27=USB\r\n] 2006.147.07:42:11.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:11.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:42:11.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:42:11.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:42:11.98$vc4f8/vblo=5,744.99 2006.147.07:42:11.98#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:42:11.98#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:42:11.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:11.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:11.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:11.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:12.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:42:12.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:12.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:42:12.04#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:42:12.04#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:42:12.04$vc4f8/vb=5,3 2006.147.07:42:12.04#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:42:12.04#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:42:12.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:12.04#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:12.10#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:12.10#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:12.12#ibcon#[27=AT05-03\r\n] 2006.147.07:42:12.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:12.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:42:12.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:42:12.16#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:12.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:12.27#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:12.27#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:12.29#ibcon#[27=USB\r\n] 2006.147.07:42:12.32#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:12.32#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:42:12.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:42:12.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:42:12.32$vc4f8/vblo=6,752.99 2006.147.07:42:12.32#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:42:12.32#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:42:12.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:42:12.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:12.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:12.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:12.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:42:12.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:12.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:42:12.38#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:42:12.38#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:42:12.38$vc4f8/vb=6,4 2006.147.07:42:12.38#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:42:12.38#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:42:12.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:42:12.38#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:12.44#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:12.44#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:12.46#ibcon#[27=AT06-04\r\n] 2006.147.07:42:12.49#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:12.49#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:42:12.49#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:42:12.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:42:12.49#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:12.61#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:12.61#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:12.63#ibcon#[27=USB\r\n] 2006.147.07:42:12.66#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:12.66#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:42:12.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:42:12.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:42:12.66$vc4f8/vabw=wide 2006.147.07:42:12.66#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:42:12.66#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:42:12.66#ibcon#ireg 8 cls_cnt 0 2006.147.07:42:12.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:12.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:12.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:12.68#ibcon#[25=BW32\r\n] 2006.147.07:42:12.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:12.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:42:12.71#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:42:12.71#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:42:12.71$vc4f8/vbbw=wide 2006.147.07:42:12.71#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:42:12.71#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:42:12.71#ibcon#ireg 8 cls_cnt 0 2006.147.07:42:12.71#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:42:12.78#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:42:12.78#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:42:12.80#ibcon#[27=BW32\r\n] 2006.147.07:42:12.83#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:42:12.83#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:42:12.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:42:12.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:42:12.83$4f8m12a/ifd4f 2006.147.07:42:12.83$ifd4f/lo= 2006.147.07:42:12.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:42:12.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:42:12.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:42:12.83$ifd4f/patch= 2006.147.07:42:12.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:42:12.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:42:12.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:42:12.83$4f8m12a/"form=m,16.000,1:2 2006.147.07:42:12.83$4f8m12a/"tpicd 2006.147.07:42:12.84$4f8m12a/echo=off 2006.147.07:42:12.84$4f8m12a/xlog=off 2006.147.07:42:12.84:!2006.147.07:42:40 2006.147.07:42:24.13#trakl#Source acquired 2006.147.07:42:24.13#flagr#flagr/antenna,acquired 2006.147.07:42:40.01:preob 2006.147.07:42:41.13/onsource/TRACKING 2006.147.07:42:41.13:!2006.147.07:42:50 2006.147.07:42:50.00:data_valid=on 2006.147.07:42:50.00:midob 2006.147.07:42:50.14/onsource/TRACKING 2006.147.07:42:50.14/wx/19.82,1011.4,81 2006.147.07:42:50.29/cable/+6.5372E-03 2006.147.07:42:51.38/va/01,08,usb,yes,29,31 2006.147.07:42:51.38/va/02,07,usb,yes,29,31 2006.147.07:42:51.38/va/03,08,usb,yes,22,22 2006.147.07:42:51.38/va/04,07,usb,yes,30,32 2006.147.07:42:51.38/va/05,06,usb,yes,34,36 2006.147.07:42:51.38/va/06,05,usb,yes,34,34 2006.147.07:42:51.38/va/07,05,usb,yes,34,34 2006.147.07:42:51.38/va/08,05,usb,yes,37,36 2006.147.07:42:51.61/valo/01,532.99,yes,locked 2006.147.07:42:51.61/valo/02,572.99,yes,locked 2006.147.07:42:51.61/valo/03,672.99,yes,locked 2006.147.07:42:51.61/valo/04,832.99,yes,locked 2006.147.07:42:51.61/valo/05,652.99,yes,locked 2006.147.07:42:51.61/valo/06,772.99,yes,locked 2006.147.07:42:51.61/valo/07,832.99,yes,locked 2006.147.07:42:51.61/valo/08,852.99,yes,locked 2006.147.07:42:52.70/vb/01,04,usb,yes,28,27 2006.147.07:42:52.70/vb/02,04,usb,yes,30,31 2006.147.07:42:52.70/vb/03,04,usb,yes,26,30 2006.147.07:42:52.70/vb/04,04,usb,yes,28,27 2006.147.07:42:52.70/vb/05,03,usb,yes,32,37 2006.147.07:42:52.70/vb/06,04,usb,yes,27,29 2006.147.07:42:52.70/vb/07,04,usb,yes,29,29 2006.147.07:42:52.70/vb/08,03,usb,yes,33,36 2006.147.07:42:52.93/vblo/01,632.99,yes,locked 2006.147.07:42:52.93/vblo/02,640.99,yes,locked 2006.147.07:42:52.93/vblo/03,656.99,yes,locked 2006.147.07:42:52.93/vblo/04,712.99,yes,locked 2006.147.07:42:52.93/vblo/05,744.99,yes,locked 2006.147.07:42:52.93/vblo/06,752.99,yes,locked 2006.147.07:42:52.93/vblo/07,734.99,yes,locked 2006.147.07:42:52.93/vblo/08,744.99,yes,locked 2006.147.07:42:53.08/vabw/8 2006.147.07:42:53.23/vbbw/8 2006.147.07:42:53.32/xfe/off,on,14.5 2006.147.07:42:53.71/ifatt/23,28,28,28 2006.147.07:42:54.07/fmout-gps/S +4.92E-07 2006.147.07:42:54.11:!2006.147.07:43:50 2006.147.07:43:50.01:data_valid=off 2006.147.07:43:50.02:postob 2006.147.07:43:50.09/cable/+6.5369E-03 2006.147.07:43:50.09/wx/19.81,1011.4,81 2006.147.07:43:51.07/fmout-gps/S +4.92E-07 2006.147.07:43:51.08:scan_name=147-0745,k06147,70 2006.147.07:43:51.08:source=0536+145,053942.37,143345.6,2000.0,ccw 2006.147.07:43:52.14#flagr#flagr/antenna,new-source 2006.147.07:43:52.15:checkk5 2006.147.07:43:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:43:52.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:43:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:43:53.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:43:54.05/chk_obsdata//k5ts1/k06147_ts1_147-0742*_20??1470742??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:43:54.42/chk_obsdata//k5ts2/k06147_ts2_147-0742*_20??1470742??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:43:54.80/chk_obsdata//k5ts3/k06147_ts3_147-0742*_20??1470742??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:43:55.19/chk_obsdata//k5ts4/k06147_ts4_147-0742*_20??1470742??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:43:55.88/k5log//k5ts1_log_newline 2006.147.07:43:56.57/k5log//k5ts2_log_newline 2006.147.07:43:57.26/k5log//k5ts3_log_newline 2006.147.07:43:57.95/k5log//k5ts4_log_newline 2006.147.07:43:57.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:43:57.97:4f8m12a=1 2006.147.07:43:57.97$4f8m12a/echo=on 2006.147.07:43:57.97$4f8m12a/pcalon 2006.147.07:43:57.97$pcalon/"no phase cal control is implemented here 2006.147.07:43:57.97$4f8m12a/"tpicd=stop 2006.147.07:43:57.97$4f8m12a/vc4f8 2006.147.07:43:57.97$vc4f8/valo=1,532.99 2006.147.07:43:57.98#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:43:57.98#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:43:57.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:57.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:43:57.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:43:57.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:43:58.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:43:58.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:43:58.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:43:58.06#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:43:58.06#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:43:58.10$vc4f8/va=1,8 2006.147.07:43:58.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.07:43:58.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.07:43:58.10#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:58.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:43:58.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:43:58.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:43:58.11#ibcon#[25=AT01-08\r\n] 2006.147.07:43:58.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:43:58.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:43:58.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.07:43:58.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:58.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:43:58.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:43:58.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:43:58.28#ibcon#[25=USB\r\n] 2006.147.07:43:58.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:43:58.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:43:58.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:43:58.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:43:58.33$vc4f8/valo=2,572.99 2006.147.07:43:58.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:43:58.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:43:58.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:58.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:43:58.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:43:58.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:43:58.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:43:58.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:43:58.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:43:58.40#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:43:58.40#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:43:58.41$vc4f8/va=2,7 2006.147.07:43:58.41#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.07:43:58.41#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.07:43:58.41#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:58.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:43:58.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:43:58.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:43:58.46#ibcon#[25=AT02-07\r\n] 2006.147.07:43:58.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:43:58.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:43:58.50#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.07:43:58.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:58.50#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:43:58.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:43:58.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:43:58.63#ibcon#[25=USB\r\n] 2006.147.07:43:58.66#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:43:58.66#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:43:58.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:43:58.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:43:58.66$vc4f8/valo=3,672.99 2006.147.07:43:58.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:43:58.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:43:58.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:58.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:43:58.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:43:58.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:43:58.70#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:43:58.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:43:58.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:43:58.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:43:58.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:43:58.73$vc4f8/va=3,8 2006.147.07:43:58.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.07:43:58.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.07:43:58.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:58.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:43:58.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:43:58.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:43:58.80#ibcon#[25=AT03-08\r\n] 2006.147.07:43:58.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:43:58.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:43:58.83#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.07:43:58.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:58.83#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:43:58.95#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:43:58.95#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:43:58.97#ibcon#[25=USB\r\n] 2006.147.07:43:59.00#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:43:59.00#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:43:59.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:43:59.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:43:59.00$vc4f8/valo=4,832.99 2006.147.07:43:59.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:43:59.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:43:59.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:59.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:43:59.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:43:59.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:43:59.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:43:59.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:43:59.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:43:59.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:43:59.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:43:59.06$vc4f8/va=4,7 2006.147.07:43:59.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:43:59.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:43:59.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:59.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:43:59.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:43:59.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:43:59.14#ibcon#[25=AT04-07\r\n] 2006.147.07:43:59.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:43:59.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:43:59.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:43:59.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:59.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:43:59.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:43:59.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:43:59.31#ibcon#[25=USB\r\n] 2006.147.07:43:59.34#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:43:59.34#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:43:59.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:43:59.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:43:59.34$vc4f8/valo=5,652.99 2006.147.07:43:59.34#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:43:59.34#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:43:59.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:59.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:43:59.34#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:43:59.34#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:43:59.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:43:59.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:43:59.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:43:59.40#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:43:59.40#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:43:59.40$vc4f8/va=5,6 2006.147.07:43:59.40#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:43:59.40#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:43:59.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:59.40#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:43:59.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:43:59.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:43:59.48#ibcon#[25=AT05-06\r\n] 2006.147.07:43:59.51#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:43:59.51#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:43:59.51#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:43:59.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:59.51#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:43:59.63#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:43:59.63#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:43:59.65#ibcon#[25=USB\r\n] 2006.147.07:43:59.68#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:43:59.68#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:43:59.68#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:43:59.68#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:43:59.68$vc4f8/valo=6,772.99 2006.147.07:43:59.68#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:43:59.68#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:43:59.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:43:59.68#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:43:59.68#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:43:59.68#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:43:59.72#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:43:59.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:43:59.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:43:59.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:43:59.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:43:59.75$vc4f8/va=6,5 2006.147.07:43:59.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:43:59.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:43:59.75#ibcon#ireg 11 cls_cnt 2 2006.147.07:43:59.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:43:59.80#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:43:59.80#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:43:59.82#ibcon#[25=AT06-05\r\n] 2006.147.07:43:59.85#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:43:59.85#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:43:59.85#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:43:59.85#ibcon#ireg 7 cls_cnt 0 2006.147.07:43:59.85#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:43:59.97#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:43:59.97#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:43:59.99#ibcon#[25=USB\r\n] 2006.147.07:44:00.02#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:44:00.02#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:44:00.02#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:44:00.02#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:44:00.02$vc4f8/valo=7,832.99 2006.147.07:44:00.02#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:44:00.02#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:44:00.02#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:00.02#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:44:00.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:44:00.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:44:00.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:44:00.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:44:00.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:44:00.08#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:44:00.08#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:44:00.08$vc4f8/va=7,5 2006.147.07:44:00.08#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:44:00.08#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:44:00.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:00.08#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:44:00.14#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:44:00.14#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:44:00.16#ibcon#[25=AT07-05\r\n] 2006.147.07:44:00.19#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:44:00.19#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:44:00.19#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:44:00.19#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:00.19#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:44:00.31#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:44:00.31#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:44:00.33#ibcon#[25=USB\r\n] 2006.147.07:44:00.36#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:44:00.36#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:44:00.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:44:00.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:44:00.36$vc4f8/valo=8,852.99 2006.147.07:44:00.36#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:44:00.36#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:44:00.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:00.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:44:00.36#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:44:00.36#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:44:00.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:44:00.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:44:00.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:44:00.42#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:44:00.42#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:44:00.42$vc4f8/va=8,5 2006.147.07:44:00.42#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:44:00.42#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:44:00.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:00.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:44:00.48#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:44:00.48#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:44:00.50#ibcon#[25=AT08-05\r\n] 2006.147.07:44:00.53#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:44:00.53#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:44:00.53#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:44:00.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:00.53#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:44:00.65#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:44:00.65#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:44:00.67#ibcon#[25=USB\r\n] 2006.147.07:44:00.70#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:44:00.70#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:44:00.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:44:00.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:44:00.70$vc4f8/vblo=1,632.99 2006.147.07:44:00.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:44:00.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:44:00.70#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:00.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:44:00.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:44:00.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:44:00.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:44:00.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:44:00.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:44:00.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:44:00.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:44:00.76$vc4f8/vb=1,4 2006.147.07:44:00.76#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.07:44:00.76#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.07:44:00.76#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:00.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:44:00.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:44:00.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:44:00.78#ibcon#[27=AT01-04\r\n] 2006.147.07:44:00.81#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:44:00.81#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:44:00.81#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.07:44:00.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:00.81#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:44:00.93#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:44:00.93#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:44:00.95#ibcon#[27=USB\r\n] 2006.147.07:44:00.98#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:44:00.98#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:44:00.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:44:00.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:44:00.98$vc4f8/vblo=2,640.99 2006.147.07:44:00.98#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:44:00.98#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:44:00.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:00.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:44:00.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:44:00.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:44:01.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:44:01.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:44:01.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:44:01.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:44:01.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:44:01.04$vc4f8/vb=2,4 2006.147.07:44:01.04#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.07:44:01.04#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.07:44:01.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:01.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:44:01.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:44:01.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:44:01.12#ibcon#[27=AT02-04\r\n] 2006.147.07:44:01.15#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:44:01.15#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:44:01.15#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.07:44:01.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:01.15#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:44:01.27#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:44:01.27#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:44:01.29#ibcon#[27=USB\r\n] 2006.147.07:44:01.32#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:44:01.32#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:44:01.32#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:44:01.32#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:44:01.32$vc4f8/vblo=3,656.99 2006.147.07:44:01.32#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:44:01.32#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:44:01.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:01.32#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:44:01.32#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:44:01.32#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:44:01.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:44:01.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:44:01.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:44:01.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:44:01.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:44:01.38$vc4f8/vb=3,4 2006.147.07:44:01.38#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.07:44:01.38#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.07:44:01.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:01.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:44:01.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:44:01.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:44:01.46#ibcon#[27=AT03-04\r\n] 2006.147.07:44:01.49#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:44:01.49#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:44:01.49#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.07:44:01.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:01.49#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:44:01.61#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:44:01.61#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:44:01.63#ibcon#[27=USB\r\n] 2006.147.07:44:01.66#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:44:01.66#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:44:01.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:44:01.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:44:01.66$vc4f8/vblo=4,712.99 2006.147.07:44:01.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:44:01.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:44:01.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:01.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:44:01.66#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:44:01.66#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:44:01.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:44:01.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:44:01.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:44:01.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:44:01.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:44:01.72$vc4f8/vb=4,4 2006.147.07:44:01.72#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.07:44:01.72#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.07:44:01.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:01.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:44:01.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:44:01.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:44:01.80#ibcon#[27=AT04-04\r\n] 2006.147.07:44:01.83#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:44:01.83#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:44:01.83#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.07:44:01.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:01.83#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:44:01.95#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:44:01.95#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:44:01.97#ibcon#[27=USB\r\n] 2006.147.07:44:02.00#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:44:02.00#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:44:02.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:44:02.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:44:02.00$vc4f8/vblo=5,744.99 2006.147.07:44:02.00#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:44:02.00#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:44:02.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:02.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:44:02.00#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:44:02.00#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:44:02.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:44:02.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:44:02.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:44:02.06#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:44:02.06#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:44:02.06$vc4f8/vb=5,3 2006.147.07:44:02.06#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:44:02.06#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:44:02.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:02.06#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:44:02.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:44:02.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:44:02.14#ibcon#[27=AT05-03\r\n] 2006.147.07:44:02.17#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:44:02.17#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:44:02.17#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:44:02.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:02.17#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:44:02.29#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:44:02.29#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:44:02.31#ibcon#[27=USB\r\n] 2006.147.07:44:02.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:44:02.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:44:02.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:44:02.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:44:02.36$vc4f8/vblo=6,752.99 2006.147.07:44:02.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:44:02.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:44:02.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:44:02.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:44:02.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:44:02.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:44:02.38#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:44:02.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:44:02.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:44:02.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:44:02.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:44:02.42$vc4f8/vb=6,4 2006.147.07:44:02.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:44:02.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:44:02.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:44:02.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:44:02.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:44:02.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:44:02.50#ibcon#[27=AT06-04\r\n] 2006.147.07:44:02.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:44:02.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:44:02.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:44:02.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:44:02.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:44:02.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:44:02.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:44:02.67#ibcon#[27=USB\r\n] 2006.147.07:44:02.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:44:02.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:44:02.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:44:02.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:44:02.70$vc4f8/vabw=wide 2006.147.07:44:02.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:44:02.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:44:02.70#ibcon#ireg 8 cls_cnt 0 2006.147.07:44:02.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:44:02.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:44:02.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:44:02.72#ibcon#[25=BW32\r\n] 2006.147.07:44:02.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:44:02.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:44:02.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:44:02.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:44:02.75$vc4f8/vbbw=wide 2006.147.07:44:02.75#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:44:02.75#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:44:02.75#ibcon#ireg 8 cls_cnt 0 2006.147.07:44:02.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:44:02.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:44:02.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:44:02.84#ibcon#[27=BW32\r\n] 2006.147.07:44:02.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:44:02.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:44:02.87#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:44:02.87#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:44:02.87$4f8m12a/ifd4f 2006.147.07:44:02.87$ifd4f/lo= 2006.147.07:44:02.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:44:02.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:44:02.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:44:02.87$ifd4f/patch= 2006.147.07:44:02.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:44:02.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:44:02.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:44:02.87$4f8m12a/"form=m,16.000,1:2 2006.147.07:44:02.87$4f8m12a/"tpicd 2006.147.07:44:02.87$4f8m12a/echo=off 2006.147.07:44:02.87$4f8m12a/xlog=off 2006.147.07:44:02.87:!2006.147.07:45:00 2006.147.07:44:40.14#trakl#Source acquired 2006.147.07:44:41.14#flagr#flagr/antenna,acquired 2006.147.07:45:00.00:preob 2006.147.07:45:00.14/onsource/TRACKING 2006.147.07:45:00.14:!2006.147.07:45:10 2006.147.07:45:10.00:data_valid=on 2006.147.07:45:10.00:midob 2006.147.07:45:11.14/onsource/TRACKING 2006.147.07:45:11.14/wx/19.79,1011.4,81 2006.147.07:45:11.20/cable/+6.5358E-03 2006.147.07:45:12.29/va/01,08,usb,yes,31,33 2006.147.07:45:12.29/va/02,07,usb,yes,31,33 2006.147.07:45:12.29/va/03,08,usb,yes,23,24 2006.147.07:45:12.29/va/04,07,usb,yes,32,34 2006.147.07:45:12.29/va/05,06,usb,yes,35,37 2006.147.07:45:12.29/va/06,05,usb,yes,36,35 2006.147.07:45:12.29/va/07,05,usb,yes,36,35 2006.147.07:45:12.29/va/08,05,usb,yes,38,38 2006.147.07:45:12.52/valo/01,532.99,yes,locked 2006.147.07:45:12.52/valo/02,572.99,yes,locked 2006.147.07:45:12.52/valo/03,672.99,yes,locked 2006.147.07:45:12.52/valo/04,832.99,yes,locked 2006.147.07:45:12.52/valo/05,652.99,yes,locked 2006.147.07:45:12.52/valo/06,772.99,yes,locked 2006.147.07:45:12.52/valo/07,832.99,yes,locked 2006.147.07:45:12.52/valo/08,852.99,yes,locked 2006.147.07:45:13.61/vb/01,04,usb,yes,29,28 2006.147.07:45:13.61/vb/02,04,usb,yes,31,32 2006.147.07:45:13.61/vb/03,04,usb,yes,27,31 2006.147.07:45:13.61/vb/04,04,usb,yes,28,28 2006.147.07:45:13.61/vb/05,03,usb,yes,33,38 2006.147.07:45:13.61/vb/06,04,usb,yes,28,30 2006.147.07:45:13.61/vb/07,04,usb,yes,30,30 2006.147.07:45:13.61/vb/08,03,usb,yes,34,38 2006.147.07:45:13.85/vblo/01,632.99,yes,locked 2006.147.07:45:13.85/vblo/02,640.99,yes,locked 2006.147.07:45:13.85/vblo/03,656.99,yes,locked 2006.147.07:45:13.85/vblo/04,712.99,yes,locked 2006.147.07:45:13.85/vblo/05,744.99,yes,locked 2006.147.07:45:13.85/vblo/06,752.99,yes,locked 2006.147.07:45:13.85/vblo/07,734.99,yes,locked 2006.147.07:45:13.85/vblo/08,744.99,yes,locked 2006.147.07:45:14.00/vabw/8 2006.147.07:45:14.15/vbbw/8 2006.147.07:45:14.24/xfe/off,on,14.5 2006.147.07:45:14.61/ifatt/23,28,28,28 2006.147.07:45:15.07/fmout-gps/S +4.92E-07 2006.147.07:45:15.11:!2006.147.07:46:20 2006.147.07:46:20.01:data_valid=off 2006.147.07:46:20.02:postob 2006.147.07:46:20.17/cable/+6.5387E-03 2006.147.07:46:20.18/wx/19.78,1011.5,81 2006.147.07:46:21.07/fmout-gps/S +4.91E-07 2006.147.07:46:21.08:scan_name=147-0747,k06147,60 2006.147.07:46:21.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.147.07:46:22.14#flagr#flagr/antenna,new-source 2006.147.07:46:22.15:checkk5 2006.147.07:46:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:46:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:46:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:46:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:46:24.06/chk_obsdata//k5ts1/k06147_ts1_147-0745*_20??1470745??.k5 file size is correct (nominal:560MB, actual:560MB). 2006.147.07:46:24.43/chk_obsdata//k5ts2/k06147_ts2_147-0745*_20??1470745??.k5 file size is correct (nominal:560MB, actual:560MB). 2006.147.07:46:24.81/chk_obsdata//k5ts3/k06147_ts3_147-0745*_20??1470745??.k5 file size is correct (nominal:560MB, actual:560MB). 2006.147.07:46:25.19/chk_obsdata//k5ts4/k06147_ts4_147-0745*_20??1470745??.k5 file size is correct (nominal:560MB, actual:560MB). 2006.147.07:46:25.88/k5log//k5ts1_log_newline 2006.147.07:46:26.57/k5log//k5ts2_log_newline 2006.147.07:46:27.26/k5log//k5ts3_log_newline 2006.147.07:46:27.95/k5log//k5ts4_log_newline 2006.147.07:46:27.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:46:27.97:4f8m12a=1 2006.147.07:46:27.97$4f8m12a/echo=on 2006.147.07:46:27.97$4f8m12a/pcalon 2006.147.07:46:27.97$pcalon/"no phase cal control is implemented here 2006.147.07:46:27.97$4f8m12a/"tpicd=stop 2006.147.07:46:27.97$4f8m12a/vc4f8 2006.147.07:46:27.97$vc4f8/valo=1,532.99 2006.147.07:46:27.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:46:27.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:46:27.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:27.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:27.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:27.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:27.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:46:28.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:28.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:28.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:46:28.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:46:28.04$vc4f8/va=1,8 2006.147.07:46:28.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:46:28.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:46:28.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:28.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:28.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:28.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:28.06#ibcon#[25=AT01-08\r\n] 2006.147.07:46:28.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:28.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:28.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:46:28.10#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:28.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:28.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:28.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:28.23#ibcon#[25=USB\r\n] 2006.147.07:46:28.28#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:28.28#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:28.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:46:28.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:46:28.29$vc4f8/valo=2,572.99 2006.147.07:46:28.29#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:46:28.29#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:46:28.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:28.29#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:28.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:28.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:28.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:46:28.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:28.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:28.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:46:28.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:46:28.34$vc4f8/va=2,7 2006.147.07:46:28.34#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:46:28.34#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:46:28.34#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:28.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:28.40#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:28.40#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:28.42#ibcon#[25=AT02-07\r\n] 2006.147.07:46:28.47#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:28.47#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:28.47#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:46:28.47#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:28.47#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:28.58#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:28.58#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:28.60#ibcon#[25=USB\r\n] 2006.147.07:46:28.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:28.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:28.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:46:28.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:46:28.66$vc4f8/valo=3,672.99 2006.147.07:46:28.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:46:28.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:46:28.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:28.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:28.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:28.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:28.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:46:28.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:28.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:28.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:46:28.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:46:28.73$vc4f8/va=3,8 2006.147.07:46:28.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:46:28.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:46:28.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:28.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:28.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:28.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:28.80#ibcon#[25=AT03-08\r\n] 2006.147.07:46:28.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:28.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:28.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:46:28.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:28.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:28.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:28.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:28.97#ibcon#[25=USB\r\n] 2006.147.07:46:29.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:29.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:29.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:46:29.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:46:29.00$vc4f8/valo=4,832.99 2006.147.07:46:29.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.07:46:29.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.07:46:29.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:29.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:29.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:29.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:29.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:46:29.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:29.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:29.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:46:29.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:46:29.06$vc4f8/va=4,7 2006.147.07:46:29.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.07:46:29.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.07:46:29.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:29.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:29.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:29.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:29.14#ibcon#[25=AT04-07\r\n] 2006.147.07:46:29.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:29.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:29.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.07:46:29.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:29.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:29.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:29.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:29.31#ibcon#[25=USB\r\n] 2006.147.07:46:29.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:29.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:29.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:46:29.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:46:29.34$vc4f8/valo=5,652.99 2006.147.07:46:29.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:46:29.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:46:29.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:29.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:29.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:29.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:29.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:46:29.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:29.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:29.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:46:29.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:46:29.40$vc4f8/va=5,6 2006.147.07:46:29.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:46:29.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:46:29.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:29.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:29.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:29.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:29.48#ibcon#[25=AT05-06\r\n] 2006.147.07:46:29.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:29.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:29.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:46:29.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:29.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:29.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:29.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:29.65#ibcon#[25=USB\r\n] 2006.147.07:46:29.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:29.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:29.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:46:29.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:46:29.68$vc4f8/valo=6,772.99 2006.147.07:46:29.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:46:29.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:46:29.68#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:29.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:29.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:29.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:29.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:46:29.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:29.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:29.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:46:29.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:46:29.74$vc4f8/va=6,5 2006.147.07:46:29.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:46:29.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:46:29.74#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:29.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:29.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:29.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:29.82#ibcon#[25=AT06-05\r\n] 2006.147.07:46:29.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:29.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:29.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:46:29.85#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:29.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:46:29.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:46:29.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:46:29.99#ibcon#[25=USB\r\n] 2006.147.07:46:30.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:46:30.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:46:30.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:46:30.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:46:30.02$vc4f8/valo=7,832.99 2006.147.07:46:30.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:46:30.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:46:30.02#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:30.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:46:30.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:46:30.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:46:30.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:46:30.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:46:30.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:46:30.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:46:30.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:46:30.08$vc4f8/va=7,5 2006.147.07:46:30.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:46:30.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:46:30.08#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:30.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:46:30.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:46:30.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:46:30.16#ibcon#[25=AT07-05\r\n] 2006.147.07:46:30.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:46:30.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:46:30.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:46:30.19#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:30.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:46:30.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:46:30.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:46:30.33#ibcon#[25=USB\r\n] 2006.147.07:46:30.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:46:30.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:46:30.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:46:30.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:46:30.36$vc4f8/valo=8,852.99 2006.147.07:46:30.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:46:30.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:46:30.36#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:30.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:46:30.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:46:30.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:46:30.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:46:30.42#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:46:30.42#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:46:30.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:46:30.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:46:30.42$vc4f8/va=8,5 2006.147.07:46:30.42#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:46:30.42#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:46:30.42#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:30.42#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:46:30.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:46:30.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:46:30.50#ibcon#[25=AT08-05\r\n] 2006.147.07:46:30.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:46:30.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:46:30.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:46:30.53#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:30.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:46:30.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:46:30.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:46:30.67#ibcon#[25=USB\r\n] 2006.147.07:46:30.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:46:30.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:46:30.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:46:30.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:46:30.70$vc4f8/vblo=1,632.99 2006.147.07:46:30.70#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:46:30.70#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:46:30.70#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:30.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:46:30.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:46:30.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:46:30.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:46:30.76#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:46:30.76#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:46:30.76#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:46:30.76#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:46:30.76$vc4f8/vb=1,4 2006.147.07:46:30.76#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:46:30.76#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:46:30.76#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:30.76#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:46:30.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:46:30.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:46:30.79#ibcon#[27=AT01-04\r\n] 2006.147.07:46:30.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:46:30.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:46:30.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:46:30.81#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:30.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:46:30.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:46:30.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:46:30.95#ibcon#[27=USB\r\n] 2006.147.07:46:30.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:46:30.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:46:30.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:46:30.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:46:30.98$vc4f8/vblo=2,640.99 2006.147.07:46:30.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:46:30.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:46:30.98#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:30.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:30.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:30.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:31.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:46:31.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:31.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:46:31.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:46:31.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:46:31.04$vc4f8/vb=2,4 2006.147.07:46:31.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:46:31.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:46:31.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:31.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:31.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:31.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:31.12#ibcon#[27=AT02-04\r\n] 2006.147.07:46:31.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:31.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:46:31.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:46:31.15#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:31.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:31.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:31.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:31.29#ibcon#[27=USB\r\n] 2006.147.07:46:31.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:31.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:46:31.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:46:31.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:46:31.32$vc4f8/vblo=3,656.99 2006.147.07:46:31.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:46:31.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:46:31.32#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:31.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:31.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:31.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:31.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:46:31.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:31.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:46:31.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:46:31.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:46:31.38$vc4f8/vb=3,4 2006.147.07:46:31.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:46:31.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:46:31.38#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:31.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:31.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:31.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:31.46#ibcon#[27=AT03-04\r\n] 2006.147.07:46:31.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:31.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:46:31.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:46:31.49#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:31.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:31.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:31.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:31.63#ibcon#[27=USB\r\n] 2006.147.07:46:31.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:31.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:46:31.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:46:31.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:46:31.66$vc4f8/vblo=4,712.99 2006.147.07:46:31.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:46:31.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:46:31.66#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:31.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:31.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:31.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:31.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:46:31.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:31.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:46:31.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:46:31.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:46:31.72$vc4f8/vb=4,4 2006.147.07:46:31.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:46:31.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:46:31.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:31.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:31.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:31.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:31.80#ibcon#[27=AT04-04\r\n] 2006.147.07:46:31.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:31.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:46:31.83#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:46:31.83#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:31.83#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:31.95#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:31.95#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:31.97#ibcon#[27=USB\r\n] 2006.147.07:46:32.00#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:32.00#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:46:32.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:46:32.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:46:32.00$vc4f8/vblo=5,744.99 2006.147.07:46:32.00#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.07:46:32.00#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.07:46:32.00#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:32.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:32.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:32.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:32.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:46:32.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:32.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.07:46:32.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:46:32.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:46:32.06$vc4f8/vb=5,3 2006.147.07:46:32.06#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.07:46:32.06#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.07:46:32.06#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:32.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:32.12#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:32.12#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:32.14#ibcon#[27=AT05-03\r\n] 2006.147.07:46:32.17#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:32.17#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.07:46:32.17#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.07:46:32.17#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:32.17#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:32.29#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:32.29#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:32.31#ibcon#[27=USB\r\n] 2006.147.07:46:32.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:32.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.07:46:32.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:46:32.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:46:32.34$vc4f8/vblo=6,752.99 2006.147.07:46:32.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:46:32.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:46:32.34#ibcon#ireg 17 cls_cnt 0 2006.147.07:46:32.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:32.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:32.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:46:32.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:32.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:46:32.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:46:32.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:46:32.40$vc4f8/vb=6,4 2006.147.07:46:32.40#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:46:32.40#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:46:32.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:46:32.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:32.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:32.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:32.48#ibcon#[27=AT06-04\r\n] 2006.147.07:46:32.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:32.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:46:32.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:46:32.51#ibcon#ireg 7 cls_cnt 0 2006.147.07:46:32.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:32.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:32.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:32.65#ibcon#[27=USB\r\n] 2006.147.07:46:32.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:32.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:46:32.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:46:32.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:46:32.68$vc4f8/vabw=wide 2006.147.07:46:32.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:46:32.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:46:32.68#ibcon#ireg 8 cls_cnt 0 2006.147.07:46:32.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:32.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:32.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:32.70#ibcon#[25=BW32\r\n] 2006.147.07:46:32.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:32.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:46:32.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:46:32.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:46:32.73$vc4f8/vbbw=wide 2006.147.07:46:32.73#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:46:32.73#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:46:32.73#ibcon#ireg 8 cls_cnt 0 2006.147.07:46:32.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:46:32.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:46:32.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:46:32.82#ibcon#[27=BW32\r\n] 2006.147.07:46:32.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:46:32.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:46:32.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:46:32.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:46:32.85$4f8m12a/ifd4f 2006.147.07:46:32.85$ifd4f/lo= 2006.147.07:46:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:46:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:46:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:46:32.85$ifd4f/patch= 2006.147.07:46:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:46:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:46:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:46:32.85$4f8m12a/"form=m,16.000,1:2 2006.147.07:46:32.85$4f8m12a/"tpicd 2006.147.07:46:32.85$4f8m12a/echo=off 2006.147.07:46:32.85$4f8m12a/xlog=off 2006.147.07:46:32.85:!2006.147.07:47:30 2006.147.07:47:11.14#trakl#Source acquired 2006.147.07:47:11.14#flagr#flagr/antenna,acquired 2006.147.07:47:30.00:preob 2006.147.07:47:30.14/onsource/TRACKING 2006.147.07:47:30.14:!2006.147.07:47:40 2006.147.07:47:40.00:data_valid=on 2006.147.07:47:40.00:midob 2006.147.07:47:41.14/onsource/TRACKING 2006.147.07:47:41.14/wx/19.76,1011.4,81 2006.147.07:47:41.24/cable/+6.5380E-03 2006.147.07:47:42.33/va/01,08,usb,yes,39,41 2006.147.07:47:42.33/va/02,07,usb,yes,40,41 2006.147.07:47:42.33/va/03,08,usb,yes,30,30 2006.147.07:47:42.33/va/04,07,usb,yes,40,43 2006.147.07:47:42.33/va/05,06,usb,yes,46,49 2006.147.07:47:42.33/va/06,05,usb,yes,47,46 2006.147.07:47:42.33/va/07,05,usb,yes,47,46 2006.147.07:47:42.33/va/08,05,usb,yes,50,49 2006.147.07:47:42.56/valo/01,532.99,yes,locked 2006.147.07:47:42.56/valo/02,572.99,yes,locked 2006.147.07:47:42.56/valo/03,672.99,yes,locked 2006.147.07:47:42.56/valo/04,832.99,yes,locked 2006.147.07:47:42.56/valo/05,652.99,yes,locked 2006.147.07:47:42.56/valo/06,772.99,yes,locked 2006.147.07:47:42.56/valo/07,832.99,yes,locked 2006.147.07:47:42.56/valo/08,852.99,yes,locked 2006.147.07:47:43.65/vb/01,04,usb,yes,32,30 2006.147.07:47:43.65/vb/02,04,usb,yes,34,35 2006.147.07:47:43.65/vb/03,04,usb,yes,30,34 2006.147.07:47:43.65/vb/04,04,usb,yes,31,31 2006.147.07:47:43.65/vb/05,03,usb,yes,36,41 2006.147.07:47:43.65/vb/06,04,usb,yes,30,33 2006.147.07:47:43.65/vb/07,04,usb,yes,32,32 2006.147.07:47:43.65/vb/08,03,usb,yes,37,41 2006.147.07:47:43.88/vblo/01,632.99,yes,locked 2006.147.07:47:43.88/vblo/02,640.99,yes,locked 2006.147.07:47:43.88/vblo/03,656.99,yes,locked 2006.147.07:47:43.88/vblo/04,712.99,yes,locked 2006.147.07:47:43.88/vblo/05,744.99,yes,locked 2006.147.07:47:43.88/vblo/06,752.99,yes,locked 2006.147.07:47:43.88/vblo/07,734.99,yes,locked 2006.147.07:47:43.88/vblo/08,744.99,yes,locked 2006.147.07:47:44.03/vabw/8 2006.147.07:47:44.18/vbbw/8 2006.147.07:47:44.27/xfe/off,on,14.7 2006.147.07:47:44.66/ifatt/23,28,28,28 2006.147.07:47:45.07/fmout-gps/S +4.92E-07 2006.147.07:47:45.11:!2006.147.07:48:40 2006.147.07:48:40.01:data_valid=off 2006.147.07:48:40.02:postob 2006.147.07:48:40.16/cable/+6.5375E-03 2006.147.07:48:40.17/wx/19.75,1011.4,81 2006.147.07:48:41.07/fmout-gps/S +4.92E-07 2006.147.07:48:41.08:scan_name=147-0749,k06147,60 2006.147.07:48:41.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.147.07:48:41.14#flagr#flagr/antenna,new-source 2006.147.07:48:42.14:checkk5 2006.147.07:48:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:48:42.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:48:43.29/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:48:43.67/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:48:44.03/chk_obsdata//k5ts1/k06147_ts1_147-0747*_20??1470747??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:48:44.41/chk_obsdata//k5ts2/k06147_ts2_147-0747*_20??1470747??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:48:44.79/chk_obsdata//k5ts3/k06147_ts3_147-0747*_20??1470747??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:48:45.17/chk_obsdata//k5ts4/k06147_ts4_147-0747*_20??1470747??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:48:45.86/k5log//k5ts1_log_newline 2006.147.07:48:46.55/k5log//k5ts2_log_newline 2006.147.07:48:47.24/k5log//k5ts3_log_newline 2006.147.07:48:47.93/k5log//k5ts4_log_newline 2006.147.07:48:47.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:48:47.95:4f8m12a=1 2006.147.07:48:47.95$4f8m12a/echo=on 2006.147.07:48:47.95$4f8m12a/pcalon 2006.147.07:48:47.95$pcalon/"no phase cal control is implemented here 2006.147.07:48:47.95$4f8m12a/"tpicd=stop 2006.147.07:48:47.95$4f8m12a/vc4f8 2006.147.07:48:47.95$vc4f8/valo=1,532.99 2006.147.07:48:47.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:48:47.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:48:47.95#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:47.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:47.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:47.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:48.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:48:48.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:48.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:48.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:48:48.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:48:48.04$vc4f8/va=1,8 2006.147.07:48:48.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:48:48.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:48:48.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:48.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:48.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:48.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:48.07#ibcon#[25=AT01-08\r\n] 2006.147.07:48:48.10#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:48.10#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:48.10#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:48:48.10#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:48.10#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:48.22#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:48.22#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:48.24#ibcon#[25=USB\r\n] 2006.147.07:48:48.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:48.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:48.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:48:48.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:48:48.29$vc4f8/valo=2,572.99 2006.147.07:48:48.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:48:48.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:48:48.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:48.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:48.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:48.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:48:48.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:48.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:48.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:48:48.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:48:48.36$vc4f8/va=2,7 2006.147.07:48:48.36#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:48:48.36#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:48:48.36#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:48.36#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:48:48.39#abcon#<5=/07 3.0 6.0 19.75 801011.4\r\n> 2006.147.07:48:48.41#abcon#{5=INTERFACE CLEAR} 2006.147.07:48:48.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:48:48.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:48:48.43#ibcon#[25=AT02-07\r\n] 2006.147.07:48:48.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:48:48.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:48:48.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:48:48.46#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:48.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:48:48.47#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:48:48.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:48:48.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:48:48.60#ibcon#[25=USB\r\n] 2006.147.07:48:48.65#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:48:48.65#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:48:48.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:48:48.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:48:48.65$vc4f8/valo=3,672.99 2006.147.07:48:48.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.07:48:48.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.07:48:48.65#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:48.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:48.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:48.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:48.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:48:48.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:48.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:48.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:48:48.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:48:48.72$vc4f8/va=3,8 2006.147.07:48:48.72#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.07:48:48.72#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.07:48:48.72#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:48.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:48.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:48.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:48.79#ibcon#[25=AT03-08\r\n] 2006.147.07:48:48.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:48.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:48.82#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.07:48:48.82#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:48.82#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:48.94#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:48.94#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:48.96#ibcon#[25=USB\r\n] 2006.147.07:48:48.99#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:48.99#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:48.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:48:48.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:48:48.99$vc4f8/valo=4,832.99 2006.147.07:48:48.99#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:48:48.99#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:48:48.99#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:48.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:48.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:48.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:49.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:48:49.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:49.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:49.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:48:49.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:48:49.05$vc4f8/va=4,7 2006.147.07:48:49.05#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.07:48:49.05#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.07:48:49.05#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:49.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:49.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:49.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:49.13#ibcon#[25=AT04-07\r\n] 2006.147.07:48:49.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:49.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:49.16#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.07:48:49.16#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:49.16#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:49.28#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:49.28#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:49.30#ibcon#[25=USB\r\n] 2006.147.07:48:49.33#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:49.33#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:49.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:48:49.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:48:49.33$vc4f8/valo=5,652.99 2006.147.07:48:49.33#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:48:49.33#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:48:49.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:49.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:49.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:49.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:49.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:48:49.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:49.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:49.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:48:49.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:48:49.39$vc4f8/va=5,6 2006.147.07:48:49.39#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.07:48:49.39#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.07:48:49.39#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:49.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:49.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:49.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:49.47#ibcon#[25=AT05-06\r\n] 2006.147.07:48:49.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:49.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:49.50#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.07:48:49.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:49.50#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:49.62#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:49.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:49.64#ibcon#[25=USB\r\n] 2006.147.07:48:49.67#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:49.67#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:49.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:48:49.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:48:49.67$vc4f8/valo=6,772.99 2006.147.07:48:49.67#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.07:48:49.67#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.07:48:49.67#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:49.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:49.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:49.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:49.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:48:49.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:49.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:49.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:48:49.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:48:49.73$vc4f8/va=6,5 2006.147.07:48:49.73#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.07:48:49.73#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.07:48:49.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:49.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:49.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:49.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:49.81#ibcon#[25=AT06-05\r\n] 2006.147.07:48:49.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:49.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:49.84#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.07:48:49.84#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:49.84#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:48:49.96#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:48:49.96#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:48:49.98#ibcon#[25=USB\r\n] 2006.147.07:48:50.01#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:48:50.01#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.07:48:50.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:48:50.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:48:50.01$vc4f8/valo=7,832.99 2006.147.07:48:50.01#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.07:48:50.01#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.07:48:50.01#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:50.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:48:50.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:48:50.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:48:50.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:48:50.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:48:50.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.07:48:50.07#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:48:50.07#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:48:50.07$vc4f8/va=7,5 2006.147.07:48:50.07#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.07:48:50.07#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.07:48:50.07#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:50.07#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:48:50.13#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:48:50.13#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:48:50.15#ibcon#[25=AT07-05\r\n] 2006.147.07:48:50.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:48:50.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.07:48:50.18#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.07:48:50.18#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:50.18#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:48:50.30#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:48:50.30#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:48:50.32#ibcon#[25=USB\r\n] 2006.147.07:48:50.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:48:50.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.07:48:50.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:48:50.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:48:50.35$vc4f8/valo=8,852.99 2006.147.07:48:50.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.07:48:50.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.07:48:50.35#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:50.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:48:50.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:48:50.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:48:50.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:48:50.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:48:50.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.07:48:50.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:48:50.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:48:50.41$vc4f8/va=8,5 2006.147.07:48:50.41#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.07:48:50.41#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.07:48:50.41#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:50.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:48:50.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:48:50.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:48:50.49#ibcon#[25=AT08-05\r\n] 2006.147.07:48:50.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:48:50.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.07:48:50.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.07:48:50.52#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:50.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:48:50.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:48:50.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:48:50.66#ibcon#[25=USB\r\n] 2006.147.07:48:50.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:48:50.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.07:48:50.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:48:50.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:48:50.69$vc4f8/vblo=1,632.99 2006.147.07:48:50.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.07:48:50.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.07:48:50.69#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:50.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:50.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:50.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:50.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:48:50.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:50.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.07:48:50.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:48:50.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:48:50.75$vc4f8/vb=1,4 2006.147.07:48:50.75#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.07:48:50.75#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.07:48:50.75#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:50.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:50.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:50.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:50.77#ibcon#[27=AT01-04\r\n] 2006.147.07:48:50.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:50.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.07:48:50.80#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.07:48:50.80#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:50.80#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:50.92#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:50.92#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:50.94#ibcon#[27=USB\r\n] 2006.147.07:48:50.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:50.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.07:48:50.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:48:50.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:48:50.97$vc4f8/vblo=2,640.99 2006.147.07:48:50.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.07:48:50.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.07:48:50.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:50.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:50.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:50.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:50.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:48:51.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:51.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.07:48:51.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:48:51.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:48:51.03$vc4f8/vb=2,4 2006.147.07:48:51.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.07:48:51.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.07:48:51.03#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:51.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:48:51.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:48:51.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:48:51.11#ibcon#[27=AT02-04\r\n] 2006.147.07:48:51.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:48:51.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.07:48:51.14#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.07:48:51.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:51.14#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:48:51.26#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:48:51.26#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:48:51.28#ibcon#[27=USB\r\n] 2006.147.07:48:51.31#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:48:51.31#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.07:48:51.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:48:51.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:48:51.31$vc4f8/vblo=3,656.99 2006.147.07:48:51.31#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.07:48:51.31#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.07:48:51.31#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:51.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:48:51.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:48:51.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:48:51.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:48:51.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:48:51.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.07:48:51.37#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:48:51.37#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:48:51.37$vc4f8/vb=3,4 2006.147.07:48:51.37#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.07:48:51.37#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.07:48:51.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:51.37#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:48:51.43#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:48:51.43#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:48:51.46#ibcon#[27=AT03-04\r\n] 2006.147.07:48:51.48#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:48:51.48#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.07:48:51.48#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.07:48:51.48#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:51.48#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:48:51.60#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:48:51.60#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:48:51.62#ibcon#[27=USB\r\n] 2006.147.07:48:51.65#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:48:51.65#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.07:48:51.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:48:51.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:48:51.65$vc4f8/vblo=4,712.99 2006.147.07:48:51.65#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.07:48:51.65#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.07:48:51.65#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:51.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:51.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:51.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:51.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:48:51.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:51.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.07:48:51.71#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:48:51.71#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:48:51.71$vc4f8/vb=4,4 2006.147.07:48:51.71#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.07:48:51.71#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.07:48:51.71#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:51.71#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:51.77#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:51.77#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:51.79#ibcon#[27=AT04-04\r\n] 2006.147.07:48:51.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:51.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.07:48:51.82#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.07:48:51.82#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:51.82#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:51.94#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:51.94#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:51.96#ibcon#[27=USB\r\n] 2006.147.07:48:51.99#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:51.99#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.07:48:51.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:48:51.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:48:51.99$vc4f8/vblo=5,744.99 2006.147.07:48:51.99#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:48:51.99#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:48:51.99#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:51.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:51.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:51.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:52.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:48:52.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:52.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:48:52.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:48:52.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:48:52.05$vc4f8/vb=5,3 2006.147.07:48:52.05#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.07:48:52.05#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.07:48:52.05#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:52.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:52.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:52.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:52.13#ibcon#[27=AT05-03\r\n] 2006.147.07:48:52.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:52.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.07:48:52.16#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.07:48:52.16#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:52.16#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:52.28#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:52.28#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:52.30#ibcon#[27=USB\r\n] 2006.147.07:48:52.33#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:52.33#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.07:48:52.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:48:52.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:48:52.33$vc4f8/vblo=6,752.99 2006.147.07:48:52.33#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:48:52.33#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:48:52.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:48:52.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:52.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:52.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:52.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:48:52.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:52.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:48:52.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:48:52.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:48:52.39$vc4f8/vb=6,4 2006.147.07:48:52.39#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.07:48:52.39#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.07:48:52.39#ibcon#ireg 11 cls_cnt 2 2006.147.07:48:52.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:52.45#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:52.45#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:52.47#ibcon#[27=AT06-04\r\n] 2006.147.07:48:52.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:52.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.07:48:52.50#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.07:48:52.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:48:52.50#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:52.62#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:52.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:52.64#ibcon#[27=USB\r\n] 2006.147.07:48:52.67#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:52.67#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.07:48:52.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:48:52.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:48:52.67$vc4f8/vabw=wide 2006.147.07:48:52.67#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.07:48:52.67#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.07:48:52.67#ibcon#ireg 8 cls_cnt 0 2006.147.07:48:52.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:52.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:52.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:52.69#ibcon#[25=BW32\r\n] 2006.147.07:48:52.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:52.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.07:48:52.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:48:52.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:48:52.72$vc4f8/vbbw=wide 2006.147.07:48:52.72#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:48:52.72#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:48:52.72#ibcon#ireg 8 cls_cnt 0 2006.147.07:48:52.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:48:52.79#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:48:52.79#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:48:52.81#ibcon#[27=BW32\r\n] 2006.147.07:48:52.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:48:52.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:48:52.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:48:52.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:48:52.84$4f8m12a/ifd4f 2006.147.07:48:52.84$ifd4f/lo= 2006.147.07:48:52.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:48:52.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:48:52.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:48:52.84$ifd4f/patch= 2006.147.07:48:52.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:48:52.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:48:52.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:48:52.84$4f8m12a/"form=m,16.000,1:2 2006.147.07:48:52.84$4f8m12a/"tpicd 2006.147.07:48:52.84$4f8m12a/echo=off 2006.147.07:48:52.84$4f8m12a/xlog=off 2006.147.07:48:52.84:!2006.147.07:49:20 2006.147.07:49:06.13#trakl#Source acquired 2006.147.07:49:08.13#flagr#flagr/antenna,acquired 2006.147.07:49:20.00:preob 2006.147.07:49:21.13/onsource/TRACKING 2006.147.07:49:21.13:!2006.147.07:49:30 2006.147.07:49:30.00:data_valid=on 2006.147.07:49:30.00:midob 2006.147.07:49:30.13/onsource/TRACKING 2006.147.07:49:30.13/wx/19.74,1011.4,81 2006.147.07:49:30.28/cable/+6.5410E-03 2006.147.07:49:31.37/va/01,08,usb,yes,30,32 2006.147.07:49:31.37/va/02,07,usb,yes,30,31 2006.147.07:49:31.37/va/03,08,usb,yes,22,23 2006.147.07:49:31.37/va/04,07,usb,yes,31,33 2006.147.07:49:31.37/va/05,06,usb,yes,35,37 2006.147.07:49:31.37/va/06,05,usb,yes,35,35 2006.147.07:49:31.37/va/07,05,usb,yes,35,35 2006.147.07:49:31.37/va/08,05,usb,yes,38,37 2006.147.07:49:31.60/valo/01,532.99,yes,locked 2006.147.07:49:31.60/valo/02,572.99,yes,locked 2006.147.07:49:31.60/valo/03,672.99,yes,locked 2006.147.07:49:31.60/valo/04,832.99,yes,locked 2006.147.07:49:31.60/valo/05,652.99,yes,locked 2006.147.07:49:31.60/valo/06,772.99,yes,locked 2006.147.07:49:31.60/valo/07,832.99,yes,locked 2006.147.07:49:31.60/valo/08,852.99,yes,locked 2006.147.07:49:32.69/vb/01,04,usb,yes,28,27 2006.147.07:49:32.69/vb/02,04,usb,yes,30,31 2006.147.07:49:32.69/vb/03,04,usb,yes,27,30 2006.147.07:49:32.69/vb/04,04,usb,yes,27,28 2006.147.07:49:32.69/vb/05,03,usb,yes,33,37 2006.147.07:49:32.69/vb/06,04,usb,yes,27,30 2006.147.07:49:32.69/vb/07,04,usb,yes,29,29 2006.147.07:49:32.69/vb/08,03,usb,yes,33,37 2006.147.07:49:32.93/vblo/01,632.99,yes,locked 2006.147.07:49:32.93/vblo/02,640.99,yes,locked 2006.147.07:49:32.93/vblo/03,656.99,yes,locked 2006.147.07:49:32.93/vblo/04,712.99,yes,locked 2006.147.07:49:32.93/vblo/05,744.99,yes,locked 2006.147.07:49:32.93/vblo/06,752.99,yes,locked 2006.147.07:49:32.93/vblo/07,734.99,yes,locked 2006.147.07:49:32.93/vblo/08,744.99,yes,locked 2006.147.07:49:33.08/vabw/8 2006.147.07:49:33.23/vbbw/8 2006.147.07:49:33.32/xfe/off,on,15.0 2006.147.07:49:33.69/ifatt/23,28,28,28 2006.147.07:49:34.07/fmout-gps/S +4.92E-07 2006.147.07:49:34.11:!2006.147.07:50:30 2006.147.07:50:30.01:data_valid=off 2006.147.07:50:30.02:postob 2006.147.07:50:30.13/cable/+6.5364E-03 2006.147.07:50:30.13/wx/19.73,1011.4,81 2006.147.07:50:31.07/fmout-gps/S +4.92E-07 2006.147.07:50:31.07:scan_name=147-0751,k06147,60 2006.147.07:50:31.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.147.07:50:31.13#flagr#flagr/antenna,new-source 2006.147.07:50:32.13:checkk5 2006.147.07:50:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:50:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:50:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:50:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:50:34.03/chk_obsdata//k5ts1/k06147_ts1_147-0749*_20??1470749??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:50:34.40/chk_obsdata//k5ts2/k06147_ts2_147-0749*_20??1470749??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:50:34.77/chk_obsdata//k5ts3/k06147_ts3_147-0749*_20??1470749??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:50:35.14/chk_obsdata//k5ts4/k06147_ts4_147-0749*_20??1470749??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:50:35.83/k5log//k5ts1_log_newline 2006.147.07:50:36.52/k5log//k5ts2_log_newline 2006.147.07:50:37.22/k5log//k5ts3_log_newline 2006.147.07:50:37.90/k5log//k5ts4_log_newline 2006.147.07:50:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:50:37.92:4f8m12a=1 2006.147.07:50:37.92$4f8m12a/echo=on 2006.147.07:50:37.93$4f8m12a/pcalon 2006.147.07:50:37.93$pcalon/"no phase cal control is implemented here 2006.147.07:50:37.93$4f8m12a/"tpicd=stop 2006.147.07:50:37.93$4f8m12a/vc4f8 2006.147.07:50:37.93$vc4f8/valo=1,532.99 2006.147.07:50:37.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:50:37.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:50:37.93#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:37.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:37.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:37.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:50:37.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:37.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:37.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:50:37.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:50:37.99$vc4f8/va=1,8 2006.147.07:50:37.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:50:37.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:50:37.99#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:37.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:37.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:37.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:38.01#ibcon#[25=AT01-08\r\n] 2006.147.07:50:38.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:38.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:38.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:50:38.05#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:38.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:38.16#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:38.16#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:38.18#ibcon#[25=USB\r\n] 2006.147.07:50:38.21#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:38.21#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:38.21#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:50:38.21#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:50:38.21$vc4f8/valo=2,572.99 2006.147.07:50:38.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:50:38.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:50:38.21#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:38.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:38.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:38.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:50:38.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:38.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:38.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:50:38.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:50:38.29$vc4f8/va=2,7 2006.147.07:50:38.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:50:38.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:50:38.29#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:38.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:38.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:38.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:38.35#ibcon#[25=AT02-07\r\n] 2006.147.07:50:38.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:38.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:38.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:50:38.38#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:38.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:38.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:38.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:38.53#ibcon#[25=USB\r\n] 2006.147.07:50:38.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:38.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:38.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:50:38.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:50:38.56$vc4f8/valo=3,672.99 2006.147.07:50:38.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:50:38.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:50:38.56#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:38.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:38.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:38.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:50:38.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:38.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:38.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:50:38.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:50:38.63$vc4f8/va=3,8 2006.147.07:50:38.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:50:38.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:50:38.63#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:38.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:38.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:38.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:38.70#ibcon#[25=AT03-08\r\n] 2006.147.07:50:38.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:38.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:38.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:50:38.73#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:38.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:38.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:38.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:38.87#ibcon#[25=USB\r\n] 2006.147.07:50:38.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:38.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:38.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:50:38.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:50:38.90$vc4f8/valo=4,832.99 2006.147.07:50:38.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:50:38.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:50:38.90#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:38.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:38.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:38.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:50:38.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:38.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:38.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:50:38.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:50:38.96$vc4f8/va=4,7 2006.147.07:50:38.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:50:38.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:50:38.96#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:38.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:39.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:39.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:39.04#ibcon#[25=AT04-07\r\n] 2006.147.07:50:39.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:39.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:39.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:50:39.07#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:39.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:39.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:39.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:39.21#ibcon#[25=USB\r\n] 2006.147.07:50:39.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:39.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:39.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:50:39.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:50:39.24$vc4f8/valo=5,652.99 2006.147.07:50:39.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:50:39.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:50:39.24#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:39.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:39.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:39.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:50:39.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:39.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:39.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:50:39.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:50:39.30$vc4f8/va=5,6 2006.147.07:50:39.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:50:39.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:50:39.30#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:39.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:39.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:39.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:39.38#ibcon#[25=AT05-06\r\n] 2006.147.07:50:39.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:39.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:39.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:50:39.41#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:39.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:39.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:39.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:39.55#ibcon#[25=USB\r\n] 2006.147.07:50:39.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:39.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:39.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:50:39.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:50:39.58$vc4f8/valo=6,772.99 2006.147.07:50:39.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:50:39.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:50:39.58#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:39.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:39.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:39.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:50:39.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:39.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:39.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:50:39.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:50:39.64$vc4f8/va=6,5 2006.147.07:50:39.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.07:50:39.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.07:50:39.64#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:39.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:39.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:39.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:39.73#ibcon#[25=AT06-05\r\n] 2006.147.07:50:39.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:39.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:39.76#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.07:50:39.76#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:39.76#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:50:39.88#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:50:39.88#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:50:39.90#ibcon#[25=USB\r\n] 2006.147.07:50:39.93#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:50:39.93#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:50:39.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:50:39.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:50:39.93$vc4f8/valo=7,832.99 2006.147.07:50:39.93#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:50:39.93#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:50:39.93#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:39.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:50:39.93#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:50:39.93#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:50:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:50:39.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:50:39.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:50:39.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:50:39.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:50:39.99$vc4f8/va=7,5 2006.147.07:50:39.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.07:50:39.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.07:50:39.99#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:39.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:50:40.05#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:50:40.05#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:50:40.07#ibcon#[25=AT07-05\r\n] 2006.147.07:50:40.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:50:40.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:50:40.10#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.07:50:40.10#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:40.10#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:50:40.22#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:50:40.22#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:50:40.24#ibcon#[25=USB\r\n] 2006.147.07:50:40.27#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:50:40.27#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:50:40.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:50:40.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:50:40.27$vc4f8/valo=8,852.99 2006.147.07:50:40.27#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:50:40.27#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:50:40.27#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:40.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:50:40.27#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:50:40.27#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:50:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:50:40.33#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:50:40.33#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:50:40.33#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:50:40.33#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:50:40.33$vc4f8/va=8,5 2006.147.07:50:40.33#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.07:50:40.33#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.07:50:40.33#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:40.33#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:50:40.39#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:50:40.39#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:50:40.41#ibcon#[25=AT08-05\r\n] 2006.147.07:50:40.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:50:40.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:50:40.44#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.07:50:40.44#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:40.44#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:50:40.56#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:50:40.56#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:50:40.58#ibcon#[25=USB\r\n] 2006.147.07:50:40.61#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:50:40.61#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:50:40.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:50:40.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:50:40.61$vc4f8/vblo=1,632.99 2006.147.07:50:40.61#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:50:40.61#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:50:40.61#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:40.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:50:40.61#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:50:40.61#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:50:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:50:40.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:50:40.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:50:40.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:50:40.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:50:40.67$vc4f8/vb=1,4 2006.147.07:50:40.67#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.07:50:40.67#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.07:50:40.67#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:40.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:50:40.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:50:40.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:50:40.69#ibcon#[27=AT01-04\r\n] 2006.147.07:50:40.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:50:40.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:50:40.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.07:50:40.72#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:40.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:50:40.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:50:40.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:50:40.86#ibcon#[27=USB\r\n] 2006.147.07:50:40.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:50:40.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:50:40.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:50:40.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:50:40.89$vc4f8/vblo=2,640.99 2006.147.07:50:40.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:50:40.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:50:40.89#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:40.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:40.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:40.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:50:40.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:40.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:50:40.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:50:40.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:50:40.95$vc4f8/vb=2,4 2006.147.07:50:40.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:50:40.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:50:40.95#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:40.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:41.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:41.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:41.03#ibcon#[27=AT02-04\r\n] 2006.147.07:50:41.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:41.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:50:41.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:50:41.06#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:41.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:41.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:41.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:41.20#ibcon#[27=USB\r\n] 2006.147.07:50:41.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:41.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:50:41.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:50:41.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:50:41.23$vc4f8/vblo=3,656.99 2006.147.07:50:41.23#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:50:41.23#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:50:41.23#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:41.23#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:41.23#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:41.23#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:50:41.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:41.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:50:41.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:50:41.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:50:41.29$vc4f8/vb=3,4 2006.147.07:50:41.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:50:41.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:50:41.29#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:41.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:41.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:41.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:41.37#ibcon#[27=AT03-04\r\n] 2006.147.07:50:41.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:41.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:50:41.40#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:50:41.40#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:41.40#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:41.52#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:41.52#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:41.54#ibcon#[27=USB\r\n] 2006.147.07:50:41.57#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:41.57#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:50:41.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:50:41.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:50:41.57$vc4f8/vblo=4,712.99 2006.147.07:50:41.57#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:50:41.57#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:50:41.57#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:41.57#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:41.57#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:41.57#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:50:41.63#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:41.63#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:50:41.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:50:41.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:50:41.63$vc4f8/vb=4,4 2006.147.07:50:41.63#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:50:41.63#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:50:41.63#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:41.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:41.69#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:41.69#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:41.71#ibcon#[27=AT04-04\r\n] 2006.147.07:50:41.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:41.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:50:41.74#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:50:41.74#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:41.74#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:41.86#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:41.86#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:41.88#ibcon#[27=USB\r\n] 2006.147.07:50:41.91#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:41.91#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:50:41.91#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:50:41.91#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:50:41.91$vc4f8/vblo=5,744.99 2006.147.07:50:41.91#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:50:41.91#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:50:41.91#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:41.91#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:41.91#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:41.91#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:50:41.97#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:41.97#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:50:41.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:50:41.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:50:41.97$vc4f8/vb=5,3 2006.147.07:50:41.97#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:50:41.97#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:50:41.97#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:41.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:42.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:42.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:42.05#ibcon#[27=AT05-03\r\n] 2006.147.07:50:42.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:42.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:50:42.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:50:42.08#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:42.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:42.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:42.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:42.22#ibcon#[27=USB\r\n] 2006.147.07:50:42.25#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:42.25#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:50:42.25#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:50:42.25#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:50:42.25$vc4f8/vblo=6,752.99 2006.147.07:50:42.25#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:50:42.25#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:50:42.25#ibcon#ireg 17 cls_cnt 0 2006.147.07:50:42.25#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:42.25#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:42.25#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:50:42.31#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:42.31#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:50:42.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:50:42.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:50:42.31$vc4f8/vb=6,4 2006.147.07:50:42.31#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:50:42.31#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:50:42.31#ibcon#ireg 11 cls_cnt 2 2006.147.07:50:42.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:42.37#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:42.37#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:42.39#ibcon#[27=AT06-04\r\n] 2006.147.07:50:42.42#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:42.42#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:50:42.42#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:50:42.42#ibcon#ireg 7 cls_cnt 0 2006.147.07:50:42.42#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:42.54#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:42.54#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:42.56#ibcon#[27=USB\r\n] 2006.147.07:50:42.59#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:42.59#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:50:42.59#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:50:42.59#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:50:42.59$vc4f8/vabw=wide 2006.147.07:50:42.59#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:50:42.59#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:50:42.59#ibcon#ireg 8 cls_cnt 0 2006.147.07:50:42.59#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:42.59#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:42.59#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:42.61#ibcon#[25=BW32\r\n] 2006.147.07:50:42.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:42.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:50:42.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:50:42.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:50:42.64$vc4f8/vbbw=wide 2006.147.07:50:42.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.07:50:42.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.07:50:42.64#ibcon#ireg 8 cls_cnt 0 2006.147.07:50:42.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:50:42.71#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:50:42.71#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:50:42.73#ibcon#[27=BW32\r\n] 2006.147.07:50:42.76#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:50:42.76#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.07:50:42.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:50:42.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:50:42.76$4f8m12a/ifd4f 2006.147.07:50:42.76$ifd4f/lo= 2006.147.07:50:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:50:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:50:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:50:42.76$ifd4f/patch= 2006.147.07:50:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:50:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:50:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:50:42.76$4f8m12a/"form=m,16.000,1:2 2006.147.07:50:42.76$4f8m12a/"tpicd 2006.147.07:50:42.76$4f8m12a/echo=off 2006.147.07:50:42.76$4f8m12a/xlog=off 2006.147.07:50:42.76:!2006.147.07:51:40 2006.147.07:51:15.14#trakl#Source acquired 2006.147.07:51:16.14#flagr#flagr/antenna,acquired 2006.147.07:51:40.00:preob 2006.147.07:51:41.14/onsource/TRACKING 2006.147.07:51:41.14:!2006.147.07:51:50 2006.147.07:51:50.00:data_valid=on 2006.147.07:51:50.00:midob 2006.147.07:51:50.14/onsource/TRACKING 2006.147.07:51:50.14/wx/19.71,1011.4,82 2006.147.07:51:50.33/cable/+6.5378E-03 2006.147.07:51:51.42/va/01,08,usb,yes,30,32 2006.147.07:51:51.42/va/02,07,usb,yes,30,32 2006.147.07:51:51.42/va/03,08,usb,yes,22,23 2006.147.07:51:51.42/va/04,07,usb,yes,31,33 2006.147.07:51:51.42/va/05,06,usb,yes,34,37 2006.147.07:51:51.42/va/06,05,usb,yes,35,35 2006.147.07:51:51.42/va/07,05,usb,yes,35,34 2006.147.07:51:51.42/va/08,05,usb,yes,37,37 2006.147.07:51:51.65/valo/01,532.99,yes,locked 2006.147.07:51:51.65/valo/02,572.99,yes,locked 2006.147.07:51:51.65/valo/03,672.99,yes,locked 2006.147.07:51:51.65/valo/04,832.99,yes,locked 2006.147.07:51:51.65/valo/05,652.99,yes,locked 2006.147.07:51:51.65/valo/06,772.99,yes,locked 2006.147.07:51:51.65/valo/07,832.99,yes,locked 2006.147.07:51:51.65/valo/08,852.99,yes,locked 2006.147.07:51:52.74/vb/01,04,usb,yes,29,28 2006.147.07:51:52.74/vb/02,04,usb,yes,31,32 2006.147.07:51:52.74/vb/03,04,usb,yes,27,31 2006.147.07:51:52.74/vb/04,04,usb,yes,28,28 2006.147.07:51:52.74/vb/05,03,usb,yes,33,37 2006.147.07:51:52.74/vb/06,04,usb,yes,28,30 2006.147.07:51:52.74/vb/07,04,usb,yes,29,29 2006.147.07:51:52.74/vb/08,03,usb,yes,34,37 2006.147.07:51:52.97/vblo/01,632.99,yes,locked 2006.147.07:51:52.97/vblo/02,640.99,yes,locked 2006.147.07:51:52.97/vblo/03,656.99,yes,locked 2006.147.07:51:52.97/vblo/04,712.99,yes,locked 2006.147.07:51:52.97/vblo/05,744.99,yes,locked 2006.147.07:51:52.97/vblo/06,752.99,yes,locked 2006.147.07:51:52.97/vblo/07,734.99,yes,locked 2006.147.07:51:52.97/vblo/08,744.99,yes,locked 2006.147.07:51:53.12/vabw/8 2006.147.07:51:53.27/vbbw/8 2006.147.07:51:53.43/xfe/off,on,15.0 2006.147.07:51:53.83/ifatt/23,28,28,28 2006.147.07:51:54.07/fmout-gps/S +4.92E-07 2006.147.07:51:54.11:!2006.147.07:52:50 2006.147.07:52:50.00:data_valid=off 2006.147.07:52:50.00:postob 2006.147.07:52:50.12/cable/+6.5383E-03 2006.147.07:52:50.12/wx/19.69,1011.4,82 2006.147.07:52:51.07/fmout-gps/S +4.91E-07 2006.147.07:52:51.07:scan_name=147-0753,k06147,60 2006.147.07:52:51.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.147.07:52:51.14#flagr#flagr/antenna,new-source 2006.147.07:52:52.14:checkk5 2006.147.07:52:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:52:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:52:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:52:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:52:54.01/chk_obsdata//k5ts1/k06147_ts1_147-0751*_20??1470751??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:52:54.38/chk_obsdata//k5ts2/k06147_ts2_147-0751*_20??1470751??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:52:54.76/chk_obsdata//k5ts3/k06147_ts3_147-0751*_20??1470751??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:52:55.14/chk_obsdata//k5ts4/k06147_ts4_147-0751*_20??1470751??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.07:52:55.83/k5log//k5ts1_log_newline 2006.147.07:52:56.52/k5log//k5ts2_log_newline 2006.147.07:52:57.21/k5log//k5ts3_log_newline 2006.147.07:52:57.90/k5log//k5ts4_log_newline 2006.147.07:52:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:52:57.92:4f8m12a=1 2006.147.07:52:57.92$4f8m12a/echo=on 2006.147.07:52:57.92$4f8m12a/pcalon 2006.147.07:52:57.92$pcalon/"no phase cal control is implemented here 2006.147.07:52:57.92$4f8m12a/"tpicd=stop 2006.147.07:52:57.92$4f8m12a/vc4f8 2006.147.07:52:57.93$vc4f8/valo=1,532.99 2006.147.07:52:57.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:52:57.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:52:57.93#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:57.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:52:57.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:52:57.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:52:57.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:52:58.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:52:58.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:52:58.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:52:58.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:52:58.02$vc4f8/va=1,8 2006.147.07:52:58.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:52:58.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:52:58.02#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:58.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:52:58.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:52:58.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:52:58.05#ibcon#[25=AT01-08\r\n] 2006.147.07:52:58.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:52:58.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:52:58.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:52:58.08#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:58.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:52:58.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:52:58.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:52:58.24#ibcon#[25=USB\r\n] 2006.147.07:52:58.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:52:58.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:52:58.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:52:58.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:52:58.26$vc4f8/valo=2,572.99 2006.147.07:52:58.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:52:58.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:52:58.26#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:58.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:52:58.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:52:58.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:52:58.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:52:58.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:52:58.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:52:58.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:52:58.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:52:58.32$vc4f8/va=2,7 2006.147.07:52:58.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:52:58.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:52:58.32#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:58.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:52:58.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:52:58.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:52:58.41#ibcon#[25=AT02-07\r\n] 2006.147.07:52:58.44#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:52:58.44#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:52:58.44#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:52:58.44#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:58.44#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:52:58.56#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:52:58.56#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:52:58.58#ibcon#[25=USB\r\n] 2006.147.07:52:58.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:52:58.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:52:58.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:52:58.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:52:58.63$vc4f8/valo=3,672.99 2006.147.07:52:58.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:52:58.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:52:58.63#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:58.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:52:58.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:52:58.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:52:58.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:52:58.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:52:58.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:52:58.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:52:58.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:52:58.69$vc4f8/va=3,8 2006.147.07:52:58.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.07:52:58.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.07:52:58.69#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:58.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:52:58.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:52:58.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:52:58.77#ibcon#[25=AT03-08\r\n] 2006.147.07:52:58.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:52:58.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:52:58.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.07:52:58.80#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:58.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:52:58.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:52:58.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:52:58.94#ibcon#[25=USB\r\n] 2006.147.07:52:58.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:52:58.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:52:58.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:52:58.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:52:58.97$vc4f8/valo=4,832.99 2006.147.07:52:58.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:52:58.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:52:58.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:58.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:52:58.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:52:58.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:52:58.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:52:59.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:52:59.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:52:59.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:52:59.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:52:59.03$vc4f8/va=4,7 2006.147.07:52:59.03#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.07:52:59.03#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.07:52:59.03#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:59.03#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:52:59.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:52:59.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:52:59.11#ibcon#[25=AT04-07\r\n] 2006.147.07:52:59.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:52:59.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:52:59.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.07:52:59.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:59.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:52:59.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:52:59.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:52:59.28#ibcon#[25=USB\r\n] 2006.147.07:52:59.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:52:59.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:52:59.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:52:59.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:52:59.31$vc4f8/valo=5,652.99 2006.147.07:52:59.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:52:59.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:52:59.31#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:59.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:52:59.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:52:59.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:52:59.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:52:59.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:52:59.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:52:59.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:52:59.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:52:59.37$vc4f8/va=5,6 2006.147.07:52:59.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.07:52:59.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.07:52:59.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:59.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:52:59.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:52:59.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:52:59.45#ibcon#[25=AT05-06\r\n] 2006.147.07:52:59.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:52:59.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:52:59.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.07:52:59.48#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:59.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:52:59.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:52:59.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:52:59.62#ibcon#[25=USB\r\n] 2006.147.07:52:59.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:52:59.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:52:59.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:52:59.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:52:59.65$vc4f8/valo=6,772.99 2006.147.07:52:59.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:52:59.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:52:59.65#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:59.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:52:59.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:52:59.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:52:59.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:52:59.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:52:59.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:52:59.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:52:59.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:52:59.71$vc4f8/va=6,5 2006.147.07:52:59.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.07:52:59.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.07:52:59.71#ibcon#ireg 11 cls_cnt 2 2006.147.07:52:59.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:52:59.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:52:59.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:52:59.79#ibcon#[25=AT06-05\r\n] 2006.147.07:52:59.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:52:59.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.07:52:59.82#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.07:52:59.82#ibcon#ireg 7 cls_cnt 0 2006.147.07:52:59.82#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:52:59.94#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:52:59.94#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:52:59.96#ibcon#[25=USB\r\n] 2006.147.07:52:59.99#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:52:59.99#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.07:52:59.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:52:59.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:52:59.99$vc4f8/valo=7,832.99 2006.147.07:52:59.99#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.07:52:59.99#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.07:52:59.99#ibcon#ireg 17 cls_cnt 0 2006.147.07:52:59.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:52:59.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:52:59.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:53:00.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:53:00.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:53:00.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.07:53:00.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:53:00.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:53:00.05$vc4f8/va=7,5 2006.147.07:53:00.05#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.07:53:00.05#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.07:53:00.05#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:00.05#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:53:00.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:53:00.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:53:00.13#ibcon#[25=AT07-05\r\n] 2006.147.07:53:00.16#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:53:00.16#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.07:53:00.16#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.07:53:00.16#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:00.16#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:53:00.28#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:53:00.28#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:53:00.30#ibcon#[25=USB\r\n] 2006.147.07:53:00.33#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:53:00.33#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.07:53:00.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:53:00.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:53:00.33$vc4f8/valo=8,852.99 2006.147.07:53:00.33#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.07:53:00.33#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.07:53:00.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:00.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:53:00.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:53:00.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:53:00.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:53:00.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:53:00.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.07:53:00.40#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:53:00.40#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:53:00.40$vc4f8/va=8,5 2006.147.07:53:00.40#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.07:53:00.40#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.07:53:00.40#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:00.40#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:53:00.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:53:00.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:53:00.47#ibcon#[25=AT08-05\r\n] 2006.147.07:53:00.50#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:53:00.50#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.07:53:00.50#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.07:53:00.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:00.50#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:53:00.62#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:53:00.62#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:53:00.64#ibcon#[25=USB\r\n] 2006.147.07:53:00.67#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:53:00.67#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.07:53:00.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:53:00.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:53:00.67$vc4f8/vblo=1,632.99 2006.147.07:53:00.67#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.07:53:00.67#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.07:53:00.67#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:00.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:53:00.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:53:00.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:53:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:53:00.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:53:00.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.07:53:00.73#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:53:00.73#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:53:00.73$vc4f8/vb=1,4 2006.147.07:53:00.73#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.07:53:00.73#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.07:53:00.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:00.73#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:53:00.73#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:53:00.73#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:53:00.75#ibcon#[27=AT01-04\r\n] 2006.147.07:53:00.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:53:00.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.07:53:00.78#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.07:53:00.78#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:00.78#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:53:00.90#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:53:00.90#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:53:00.92#ibcon#[27=USB\r\n] 2006.147.07:53:00.95#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:53:00.95#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.07:53:00.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:53:00.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:53:00.95$vc4f8/vblo=2,640.99 2006.147.07:53:00.95#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.07:53:00.95#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.07:53:00.95#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:00.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:53:00.95#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:53:00.95#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:53:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:53:01.01#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:53:01.01#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.07:53:01.01#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:53:01.01#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:53:01.01$vc4f8/vb=2,4 2006.147.07:53:01.01#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.07:53:01.01#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.07:53:01.01#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:01.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:53:01.07#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:53:01.07#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:53:01.09#ibcon#[27=AT02-04\r\n] 2006.147.07:53:01.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:53:01.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.07:53:01.12#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.07:53:01.12#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:01.12#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:53:01.24#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:53:01.24#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:53:01.26#ibcon#[27=USB\r\n] 2006.147.07:53:01.29#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:53:01.29#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.07:53:01.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:53:01.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:53:01.29$vc4f8/vblo=3,656.99 2006.147.07:53:01.29#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:53:01.29#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:53:01.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:01.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:53:01.29#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:53:01.29#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:53:01.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:53:01.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:53:01.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:53:01.35#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:53:01.35#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:53:01.35$vc4f8/vb=3,4 2006.147.07:53:01.35#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.07:53:01.35#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.07:53:01.35#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:01.35#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:53:01.41#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:53:01.41#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:53:01.43#ibcon#[27=AT03-04\r\n] 2006.147.07:53:01.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:53:01.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.07:53:01.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.07:53:01.46#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:01.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:53:01.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:53:01.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:53:01.60#ibcon#[27=USB\r\n] 2006.147.07:53:01.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:53:01.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.07:53:01.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.07:53:01.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.07:53:01.63$vc4f8/vblo=4,712.99 2006.147.07:53:01.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.07:53:01.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.07:53:01.63#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:01.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:53:01.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:53:01.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:53:01.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:53:01.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:53:01.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.07:53:01.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.07:53:01.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.07:53:01.69$vc4f8/vb=4,4 2006.147.07:53:01.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.07:53:01.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.07:53:01.69#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:01.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:53:01.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:53:01.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:53:01.77#ibcon#[27=AT04-04\r\n] 2006.147.07:53:01.80#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:53:01.80#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.07:53:01.80#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.07:53:01.80#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:01.80#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:53:01.92#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:53:01.92#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:53:01.94#ibcon#[27=USB\r\n] 2006.147.07:53:01.97#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:53:01.97#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.07:53:01.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:53:01.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:53:01.97$vc4f8/vblo=5,744.99 2006.147.07:53:01.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.07:53:01.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.07:53:01.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:01.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:53:01.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:53:01.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:53:02.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:53:02.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:53:02.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.07:53:02.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:53:02.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:53:02.04$vc4f8/vb=5,3 2006.147.07:53:02.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.07:53:02.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.07:53:02.04#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:02.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:53:02.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:53:02.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:53:02.11#ibcon#[27=AT05-03\r\n] 2006.147.07:53:02.14#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:53:02.14#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.07:53:02.14#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.07:53:02.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:02.14#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:53:02.26#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:53:02.26#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:53:02.28#ibcon#[27=USB\r\n] 2006.147.07:53:02.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:53:02.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.07:53:02.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:53:02.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:53:02.31$vc4f8/vblo=6,752.99 2006.147.07:53:02.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.07:53:02.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.07:53:02.31#ibcon#ireg 17 cls_cnt 0 2006.147.07:53:02.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:53:02.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:53:02.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:53:02.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:53:02.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:53:02.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.07:53:02.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:53:02.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:53:02.37$vc4f8/vb=6,4 2006.147.07:53:02.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.07:53:02.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.07:53:02.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:53:02.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:53:02.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:53:02.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:53:02.45#ibcon#[27=AT06-04\r\n] 2006.147.07:53:02.48#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:53:02.48#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.07:53:02.48#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.07:53:02.48#ibcon#ireg 7 cls_cnt 0 2006.147.07:53:02.48#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:53:02.60#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:53:02.60#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:53:02.62#ibcon#[27=USB\r\n] 2006.147.07:53:02.65#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:53:02.65#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.07:53:02.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:53:02.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:53:02.65$vc4f8/vabw=wide 2006.147.07:53:02.65#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.07:53:02.65#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.07:53:02.65#ibcon#ireg 8 cls_cnt 0 2006.147.07:53:02.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:53:02.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:53:02.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:53:02.67#ibcon#[25=BW32\r\n] 2006.147.07:53:02.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:53:02.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.07:53:02.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:53:02.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:53:02.70$vc4f8/vbbw=wide 2006.147.07:53:02.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:53:02.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:53:02.70#ibcon#ireg 8 cls_cnt 0 2006.147.07:53:02.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:53:02.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:53:02.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:53:02.79#ibcon#[27=BW32\r\n] 2006.147.07:53:02.82#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:53:02.82#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:53:02.82#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:53:02.82#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:53:02.82$4f8m12a/ifd4f 2006.147.07:53:02.82$ifd4f/lo= 2006.147.07:53:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:53:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:53:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:53:02.82$ifd4f/patch= 2006.147.07:53:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:53:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:53:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:53:02.82$4f8m12a/"form=m,16.000,1:2 2006.147.07:53:02.82$4f8m12a/"tpicd 2006.147.07:53:02.82$4f8m12a/echo=off 2006.147.07:53:02.82$4f8m12a/xlog=off 2006.147.07:53:02.82:!2006.147.07:53:30 2006.147.07:53:11.14#trakl#Source acquired 2006.147.07:53:12.14#flagr#flagr/antenna,acquired 2006.147.07:53:30.00:preob 2006.147.07:53:31.14/onsource/TRACKING 2006.147.07:53:31.14:!2006.147.07:53:40 2006.147.07:53:40.00:data_valid=on 2006.147.07:53:40.00:midob 2006.147.07:53:40.14/onsource/TRACKING 2006.147.07:53:40.14/wx/19.68,1011.4,82 2006.147.07:53:40.21/cable/+6.5369E-03 2006.147.07:53:41.30/va/01,08,usb,yes,29,31 2006.147.07:53:41.30/va/02,07,usb,yes,30,31 2006.147.07:53:41.30/va/03,08,usb,yes,22,22 2006.147.07:53:41.30/va/04,07,usb,yes,30,32 2006.147.07:53:41.30/va/05,06,usb,yes,34,36 2006.147.07:53:41.30/va/06,05,usb,yes,34,34 2006.147.07:53:41.30/va/07,05,usb,yes,34,34 2006.147.07:53:41.30/va/08,05,usb,yes,37,36 2006.147.07:53:41.53/valo/01,532.99,yes,locked 2006.147.07:53:41.53/valo/02,572.99,yes,locked 2006.147.07:53:41.53/valo/03,672.99,yes,locked 2006.147.07:53:41.53/valo/04,832.99,yes,locked 2006.147.07:53:41.53/valo/05,652.99,yes,locked 2006.147.07:53:41.53/valo/06,772.99,yes,locked 2006.147.07:53:41.53/valo/07,832.99,yes,locked 2006.147.07:53:41.53/valo/08,852.99,yes,locked 2006.147.07:53:42.62/vb/01,04,usb,yes,28,27 2006.147.07:53:42.62/vb/02,04,usb,yes,30,31 2006.147.07:53:42.62/vb/03,04,usb,yes,26,30 2006.147.07:53:42.62/vb/04,04,usb,yes,28,27 2006.147.07:53:42.62/vb/05,03,usb,yes,32,36 2006.147.07:53:42.62/vb/06,04,usb,yes,27,29 2006.147.07:53:42.62/vb/07,04,usb,yes,28,29 2006.147.07:53:42.62/vb/08,03,usb,yes,33,36 2006.147.07:53:42.85/vblo/01,632.99,yes,locked 2006.147.07:53:42.85/vblo/02,640.99,yes,locked 2006.147.07:53:42.85/vblo/03,656.99,yes,locked 2006.147.07:53:42.85/vblo/04,712.99,yes,locked 2006.147.07:53:42.85/vblo/05,744.99,yes,locked 2006.147.07:53:42.85/vblo/06,752.99,yes,locked 2006.147.07:53:42.85/vblo/07,734.99,yes,locked 2006.147.07:53:42.85/vblo/08,744.99,yes,locked 2006.147.07:53:43.00/vabw/8 2006.147.07:53:43.15/vbbw/8 2006.147.07:53:43.24/xfe/off,on,14.5 2006.147.07:53:43.63/ifatt/23,28,28,28 2006.147.07:53:44.07/fmout-gps/S +4.92E-07 2006.147.07:53:44.11:!2006.147.07:54:40 2006.147.07:54:40.00:data_valid=off 2006.147.07:54:40.00:postob 2006.147.07:54:40.20/cable/+6.5380E-03 2006.147.07:54:40.20/wx/19.67,1011.4,82 2006.147.07:54:41.07/fmout-gps/S +4.92E-07 2006.147.07:54:41.07:scan_name=147-0756,k06147,60 2006.147.07:54:41.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.147.07:54:41.14#flagr#flagr/antenna,new-source 2006.147.07:54:42.14:checkk5 2006.147.07:54:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:54:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:54:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:54:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:54:44.02/chk_obsdata//k5ts1/k06147_ts1_147-0753*_20??1470753??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:54:44.39/chk_obsdata//k5ts2/k06147_ts2_147-0753*_20??1470753??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:54:44.77/chk_obsdata//k5ts3/k06147_ts3_147-0753*_20??1470753??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:54:45.14/chk_obsdata//k5ts4/k06147_ts4_147-0753*_20??1470753??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:54:45.84/k5log//k5ts1_log_newline 2006.147.07:54:46.52/k5log//k5ts2_log_newline 2006.147.07:54:47.21/k5log//k5ts3_log_newline 2006.147.07:54:47.89/k5log//k5ts4_log_newline 2006.147.07:54:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:54:47.92:4f8m12a=2 2006.147.07:54:47.92$4f8m12a/echo=on 2006.147.07:54:47.92$4f8m12a/pcalon 2006.147.07:54:47.92$pcalon/"no phase cal control is implemented here 2006.147.07:54:47.92$4f8m12a/"tpicd=stop 2006.147.07:54:47.92$4f8m12a/vc4f8 2006.147.07:54:47.92$vc4f8/valo=1,532.99 2006.147.07:54:47.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:54:47.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:54:47.92#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:47.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:47.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:47.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:54:48.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:48.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:48.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:54:48.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:54:48.01$vc4f8/va=1,8 2006.147.07:54:48.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:54:48.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:54:48.01#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:48.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:48.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:48.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:48.04#ibcon#[25=AT01-08\r\n] 2006.147.07:54:48.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:48.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:48.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:54:48.07#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:48.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:48.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:48.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:48.23#ibcon#[25=USB\r\n] 2006.147.07:54:48.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:48.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:48.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:54:48.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:54:48.25$vc4f8/valo=2,572.99 2006.147.07:54:48.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:54:48.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:54:48.25#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:48.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:48.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:48.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:48.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:54:48.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:48.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:48.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:54:48.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:54:48.32$vc4f8/va=2,7 2006.147.07:54:48.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:54:48.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:54:48.32#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:48.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:48.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:48.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:48.39#ibcon#[25=AT02-07\r\n] 2006.147.07:54:48.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:48.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:48.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:54:48.42#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:48.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:48.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:48.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:48.56#ibcon#[25=USB\r\n] 2006.147.07:54:48.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:48.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:48.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:54:48.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:54:48.61$vc4f8/valo=3,672.99 2006.147.07:54:48.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:54:48.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:54:48.61#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:48.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:48.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:48.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:48.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:54:48.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:48.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:48.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:54:48.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:54:48.68$vc4f8/va=3,8 2006.147.07:54:48.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:54:48.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:54:48.68#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:48.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:48.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:48.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:48.75#ibcon#[25=AT03-08\r\n] 2006.147.07:54:48.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:48.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:48.78#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:54:48.78#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:48.78#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:48.90#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:48.90#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:48.92#ibcon#[25=USB\r\n] 2006.147.07:54:48.95#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:48.95#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:48.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:54:48.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:54:48.95$vc4f8/valo=4,832.99 2006.147.07:54:48.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:54:48.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:54:48.95#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:48.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:48.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:48.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:48.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:54:49.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:49.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:49.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:54:49.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:54:49.01$vc4f8/va=4,7 2006.147.07:54:49.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:54:49.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:54:49.01#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:49.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:49.07#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:49.07#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:49.09#ibcon#[25=AT04-07\r\n] 2006.147.07:54:49.12#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:49.12#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:49.12#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:54:49.12#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:49.12#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:49.24#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:49.24#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:49.26#ibcon#[25=USB\r\n] 2006.147.07:54:49.29#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:49.29#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:49.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:54:49.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:54:49.29$vc4f8/valo=5,652.99 2006.147.07:54:49.29#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:54:49.29#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:54:49.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:49.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:49.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:49.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:54:49.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:49.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:49.35#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:54:49.35#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:54:49.35$vc4f8/va=5,6 2006.147.07:54:49.35#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.07:54:49.35#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.07:54:49.35#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:49.35#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:49.41#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:49.41#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:49.43#ibcon#[25=AT05-06\r\n] 2006.147.07:54:49.46#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:49.46#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:49.46#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.07:54:49.46#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:49.46#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:49.58#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:49.58#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:49.60#ibcon#[25=USB\r\n] 2006.147.07:54:49.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:49.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:49.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:54:49.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:54:49.65$vc4f8/valo=6,772.99 2006.147.07:54:49.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:54:49.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:54:49.65#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:49.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:49.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:49.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:54:49.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:49.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:49.71#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:54:49.71#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:54:49.71$vc4f8/va=6,5 2006.147.07:54:49.71#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.07:54:49.71#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.07:54:49.71#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:49.71#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:49.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:49.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:49.79#ibcon#[25=AT06-05\r\n] 2006.147.07:54:49.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:49.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:49.82#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.07:54:49.82#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:49.82#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:54:49.94#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:54:49.94#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:54:49.96#ibcon#[25=USB\r\n] 2006.147.07:54:49.99#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:54:49.99#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.07:54:49.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:54:49.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:54:49.99$vc4f8/valo=7,832.99 2006.147.07:54:49.99#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.07:54:49.99#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.07:54:49.99#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:49.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:54:49.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:54:49.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:54:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:54:50.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:54:50.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.07:54:50.05#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.07:54:50.05#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.07:54:50.05$vc4f8/va=7,5 2006.147.07:54:50.05#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.07:54:50.05#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.07:54:50.05#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:50.05#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:54:50.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:54:50.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:54:50.13#ibcon#[25=AT07-05\r\n] 2006.147.07:54:50.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:54:50.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.07:54:50.16#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.07:54:50.16#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:50.16#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:54:50.28#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:54:50.28#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:54:50.30#ibcon#[25=USB\r\n] 2006.147.07:54:50.33#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:54:50.33#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.07:54:50.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.07:54:50.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.07:54:50.33$vc4f8/valo=8,852.99 2006.147.07:54:50.33#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.07:54:50.33#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.07:54:50.33#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:50.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:54:50.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:54:50.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:54:50.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:54:50.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:54:50.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.07:54:50.39#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.07:54:50.39#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.07:54:50.39$vc4f8/va=8,5 2006.147.07:54:50.39#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.07:54:50.39#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.07:54:50.39#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:50.39#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:54:50.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:54:50.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:54:50.47#ibcon#[25=AT08-05\r\n] 2006.147.07:54:50.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:54:50.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.07:54:50.50#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.07:54:50.50#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:50.50#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:54:50.62#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:54:50.62#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:54:50.64#ibcon#[25=USB\r\n] 2006.147.07:54:50.67#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:54:50.67#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.07:54:50.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.07:54:50.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.07:54:50.67$vc4f8/vblo=1,632.99 2006.147.07:54:50.67#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.07:54:50.67#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.07:54:50.67#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:50.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:54:50.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:54:50.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:54:50.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:54:50.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:54:50.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.07:54:50.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.07:54:50.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.07:54:50.73$vc4f8/vb=1,4 2006.147.07:54:50.73#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.07:54:50.73#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.07:54:50.73#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:50.73#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:54:50.73#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:54:50.73#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:54:50.75#ibcon#[27=AT01-04\r\n] 2006.147.07:54:50.78#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:54:50.78#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.07:54:50.78#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.07:54:50.78#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:50.78#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:54:50.90#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:54:50.90#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:54:50.92#ibcon#[27=USB\r\n] 2006.147.07:54:50.95#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:54:50.95#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.07:54:50.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.07:54:50.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.07:54:50.95$vc4f8/vblo=2,640.99 2006.147.07:54:50.95#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.07:54:50.95#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.07:54:50.95#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:50.95#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:50.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:50.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:50.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:54:51.01#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:51.01#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.07:54:51.01#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.07:54:51.01#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.07:54:51.01$vc4f8/vb=2,4 2006.147.07:54:51.01#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.07:54:51.01#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.07:54:51.01#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:51.01#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:51.07#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:51.07#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:51.09#ibcon#[27=AT02-04\r\n] 2006.147.07:54:51.12#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:51.12#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.07:54:51.12#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.07:54:51.12#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:51.12#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:51.24#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:51.24#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:51.26#ibcon#[27=USB\r\n] 2006.147.07:54:51.29#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:51.29#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.07:54:51.29#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.07:54:51.29#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.07:54:51.29$vc4f8/vblo=3,656.99 2006.147.07:54:51.29#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.07:54:51.29#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.07:54:51.29#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:51.29#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:51.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:51.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:51.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:54:51.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:51.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.07:54:51.37#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.07:54:51.37#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.07:54:51.37$vc4f8/vb=3,4 2006.147.07:54:51.37#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.07:54:51.37#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.07:54:51.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:51.37#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:51.41#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:51.41#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:51.43#ibcon#[27=AT03-04\r\n] 2006.147.07:54:51.46#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:51.46#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.07:54:51.46#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.07:54:51.46#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:51.46#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:51.58#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:51.58#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:51.60#ibcon#[27=USB\r\n] 2006.147.07:54:51.63#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:51.63#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.07:54:51.63#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.07:54:51.63#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.07:54:51.63$vc4f8/vblo=4,712.99 2006.147.07:54:51.63#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.07:54:51.63#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.07:54:51.63#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:51.63#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:51.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:51.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:54:51.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:51.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.07:54:51.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.07:54:51.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.07:54:51.69$vc4f8/vb=4,4 2006.147.07:54:51.69#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.07:54:51.69#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.07:54:51.69#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:51.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:51.75#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:51.75#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:51.77#ibcon#[27=AT04-04\r\n] 2006.147.07:54:51.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:51.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.07:54:51.80#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.07:54:51.80#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:51.80#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:51.92#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:51.92#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:51.94#ibcon#[27=USB\r\n] 2006.147.07:54:51.97#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:51.97#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.07:54:51.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.07:54:51.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.07:54:51.97$vc4f8/vblo=5,744.99 2006.147.07:54:51.97#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.07:54:51.97#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.07:54:51.97#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:51.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:51.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:51.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:54:52.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:52.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.07:54:52.03#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.07:54:52.03#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.07:54:52.03$vc4f8/vb=5,3 2006.147.07:54:52.03#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.07:54:52.03#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.07:54:52.03#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:52.03#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:52.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:52.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:52.11#ibcon#[27=AT05-03\r\n] 2006.147.07:54:52.14#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:52.14#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.07:54:52.14#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.07:54:52.14#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:52.14#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:52.26#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:52.26#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:52.28#ibcon#[27=USB\r\n] 2006.147.07:54:52.31#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:52.31#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.07:54:52.31#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.07:54:52.31#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.07:54:52.31$vc4f8/vblo=6,752.99 2006.147.07:54:52.31#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.07:54:52.31#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.07:54:52.31#ibcon#ireg 17 cls_cnt 0 2006.147.07:54:52.31#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:52.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:52.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:54:52.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:52.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.07:54:52.37#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.07:54:52.37#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.07:54:52.37$vc4f8/vb=6,4 2006.147.07:54:52.37#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.07:54:52.37#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.07:54:52.37#ibcon#ireg 11 cls_cnt 2 2006.147.07:54:52.37#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:52.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:52.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:52.45#ibcon#[27=AT06-04\r\n] 2006.147.07:54:52.48#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:52.48#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.07:54:52.48#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.07:54:52.48#ibcon#ireg 7 cls_cnt 0 2006.147.07:54:52.48#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:52.60#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:52.60#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:52.62#ibcon#[27=USB\r\n] 2006.147.07:54:52.65#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:52.65#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.07:54:52.65#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.07:54:52.65#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.07:54:52.65$vc4f8/vabw=wide 2006.147.07:54:52.65#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.07:54:52.65#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.07:54:52.65#ibcon#ireg 8 cls_cnt 0 2006.147.07:54:52.65#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:52.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:52.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:52.67#ibcon#[25=BW32\r\n] 2006.147.07:54:52.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:52.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.07:54:52.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.07:54:52.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.07:54:52.70$vc4f8/vbbw=wide 2006.147.07:54:52.70#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.07:54:52.70#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.07:54:52.70#ibcon#ireg 8 cls_cnt 0 2006.147.07:54:52.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:54:52.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:54:52.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:54:52.79#ibcon#[27=BW32\r\n] 2006.147.07:54:52.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:54:52.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.07:54:52.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.07:54:52.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.07:54:52.82$4f8m12a/ifd4f 2006.147.07:54:52.82$ifd4f/lo= 2006.147.07:54:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:54:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:54:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:54:52.82$ifd4f/patch= 2006.147.07:54:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:54:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:54:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:54:52.82$4f8m12a/"form=m,16.000,1:2 2006.147.07:54:52.82$4f8m12a/"tpicd 2006.147.07:54:52.82$4f8m12a/echo=off 2006.147.07:54:52.82$4f8m12a/xlog=off 2006.147.07:54:52.82:!2006.147.07:56:20 2006.147.07:55:10.14#trakl#Source acquired 2006.147.07:55:11.14#flagr#flagr/antenna,acquired 2006.147.07:56:20.00:preob 2006.147.07:56:21.14/onsource/TRACKING 2006.147.07:56:21.14:!2006.147.07:56:30 2006.147.07:56:30.00:data_valid=on 2006.147.07:56:30.00:midob 2006.147.07:56:30.14/onsource/TRACKING 2006.147.07:56:30.14/wx/19.66,1011.4,82 2006.147.07:56:30.20/cable/+6.5384E-03 2006.147.07:56:31.29/va/01,08,usb,yes,32,33 2006.147.07:56:31.29/va/02,07,usb,yes,32,33 2006.147.07:56:31.29/va/03,08,usb,yes,24,24 2006.147.07:56:31.29/va/04,07,usb,yes,33,35 2006.147.07:56:31.29/va/05,06,usb,yes,36,39 2006.147.07:56:31.29/va/06,05,usb,yes,37,36 2006.147.07:56:31.29/va/07,05,usb,yes,37,36 2006.147.07:56:31.29/va/08,05,usb,yes,40,39 2006.147.07:56:31.52/valo/01,532.99,yes,locked 2006.147.07:56:31.52/valo/02,572.99,yes,locked 2006.147.07:56:31.52/valo/03,672.99,yes,locked 2006.147.07:56:31.52/valo/04,832.99,yes,locked 2006.147.07:56:31.52/valo/05,652.99,yes,locked 2006.147.07:56:31.52/valo/06,772.99,yes,locked 2006.147.07:56:31.52/valo/07,832.99,yes,locked 2006.147.07:56:31.52/valo/08,852.99,yes,locked 2006.147.07:56:32.61/vb/01,04,usb,yes,29,28 2006.147.07:56:32.61/vb/02,04,usb,yes,31,33 2006.147.07:56:32.61/vb/03,04,usb,yes,28,31 2006.147.07:56:32.61/vb/04,04,usb,yes,28,29 2006.147.07:56:32.61/vb/05,03,usb,yes,34,38 2006.147.07:56:32.61/vb/06,04,usb,yes,28,31 2006.147.07:56:32.61/vb/07,04,usb,yes,30,30 2006.147.07:56:32.61/vb/08,03,usb,yes,34,38 2006.147.07:56:32.84/vblo/01,632.99,yes,locked 2006.147.07:56:32.84/vblo/02,640.99,yes,locked 2006.147.07:56:32.84/vblo/03,656.99,yes,locked 2006.147.07:56:32.84/vblo/04,712.99,yes,locked 2006.147.07:56:32.84/vblo/05,744.99,yes,locked 2006.147.07:56:32.84/vblo/06,752.99,yes,locked 2006.147.07:56:32.84/vblo/07,734.99,yes,locked 2006.147.07:56:32.84/vblo/08,744.99,yes,locked 2006.147.07:56:32.99/vabw/8 2006.147.07:56:33.14/vbbw/8 2006.147.07:56:33.23/xfe/off,on,14.7 2006.147.07:56:33.61/ifatt/23,28,28,28 2006.147.07:56:34.08/fmout-gps/S +4.91E-07 2006.147.07:56:34.12:!2006.147.07:57:30 2006.147.07:57:30.00:data_valid=off 2006.147.07:57:30.00:postob 2006.147.07:57:30.09/cable/+6.5375E-03 2006.147.07:57:30.09/wx/19.64,1011.5,83 2006.147.07:57:31.08/fmout-gps/S +4.89E-07 2006.147.07:57:31.08:scan_name=147-0800,k06147,60 2006.147.07:57:31.09:source=1418+546,141946.60,542314.8,2000.0,cw 2006.147.07:57:31.13#flagr#flagr/antenna,new-source 2006.147.07:57:32.13:checkk5 2006.147.07:57:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.147.07:57:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.147.07:57:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.147.07:57:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.147.07:57:34.00/chk_obsdata//k5ts1/k06147_ts1_147-0756*_20??1470756??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:57:34.37/chk_obsdata//k5ts2/k06147_ts2_147-0756*_20??1470756??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:57:34.74/chk_obsdata//k5ts3/k06147_ts3_147-0756*_20??1470756??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:57:35.11/chk_obsdata//k5ts4/k06147_ts4_147-0756*_20??1470756??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.07:57:35.80/k5log//k5ts1_log_newline 2006.147.07:57:36.48/k5log//k5ts2_log_newline 2006.147.07:57:37.17/k5log//k5ts3_log_newline 2006.147.07:57:37.85/k5log//k5ts4_log_newline 2006.147.07:57:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.07:57:37.88:4f8m12a=2 2006.147.07:57:37.88$4f8m12a/echo=on 2006.147.07:57:37.88$4f8m12a/pcalon 2006.147.07:57:37.88$pcalon/"no phase cal control is implemented here 2006.147.07:57:37.88$4f8m12a/"tpicd=stop 2006.147.07:57:37.88$4f8m12a/vc4f8 2006.147.07:57:37.88$vc4f8/valo=1,532.99 2006.147.07:57:37.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:57:37.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:57:37.88#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:37.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:37.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:37.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:37.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.07:57:37.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:37.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:37.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:57:37.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:57:37.97$vc4f8/va=1,8 2006.147.07:57:37.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:57:37.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:57:37.97#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:37.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:37.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:37.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:38.00#ibcon#[25=AT01-08\r\n] 2006.147.07:57:38.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:38.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:38.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:57:38.03#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:38.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:38.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:38.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:38.17#ibcon#[25=USB\r\n] 2006.147.07:57:38.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:38.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:38.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:57:38.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:57:38.20$vc4f8/valo=2,572.99 2006.147.07:57:38.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:57:38.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:57:38.20#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:38.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:38.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:38.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.07:57:38.26#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:38.26#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:38.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:57:38.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:57:38.26$vc4f8/va=2,7 2006.147.07:57:38.26#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:57:38.26#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:57:38.26#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:38.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:38.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:38.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:38.34#ibcon#[25=AT02-07\r\n] 2006.147.07:57:38.37#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:38.37#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:38.37#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:57:38.37#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:38.37#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:38.49#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:38.49#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:38.51#ibcon#[25=USB\r\n] 2006.147.07:57:38.54#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:38.54#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:38.54#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:57:38.54#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:57:38.54$vc4f8/valo=3,672.99 2006.147.07:57:38.54#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:57:38.54#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:57:38.54#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:38.54#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:38.54#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:38.54#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.07:57:38.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:38.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:38.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:57:38.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:57:38.61$vc4f8/va=3,8 2006.147.07:57:38.61#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:57:38.61#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:57:38.61#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:38.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:38.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:38.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:38.68#ibcon#[25=AT03-08\r\n] 2006.147.07:57:38.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:38.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:38.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:57:38.71#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:38.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:38.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:38.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:38.85#ibcon#[25=USB\r\n] 2006.147.07:57:38.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:38.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:38.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:57:38.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:57:38.88$vc4f8/valo=4,832.99 2006.147.07:57:38.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:57:38.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:57:38.88#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:38.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:38.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:38.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.07:57:38.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:38.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:38.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:57:38.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:57:38.94$vc4f8/va=4,7 2006.147.07:57:38.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:57:38.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:57:38.94#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:38.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:39.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:39.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:39.02#ibcon#[25=AT04-07\r\n] 2006.147.07:57:39.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:39.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:39.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:57:39.05#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:39.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:39.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:39.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:39.19#ibcon#[25=USB\r\n] 2006.147.07:57:39.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:39.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:39.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:57:39.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:57:39.22$vc4f8/valo=5,652.99 2006.147.07:57:39.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:57:39.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:57:39.22#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:39.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:39.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:39.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.07:57:39.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:39.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:39.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:57:39.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:57:39.28$vc4f8/va=5,6 2006.147.07:57:39.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:57:39.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:57:39.28#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:39.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:39.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:39.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:39.36#ibcon#[25=AT05-06\r\n] 2006.147.07:57:39.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:39.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:39.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:57:39.39#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:39.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:39.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:39.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:39.53#ibcon#[25=USB\r\n] 2006.147.07:57:39.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:39.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:39.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:57:39.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:57:39.56$vc4f8/valo=6,772.99 2006.147.07:57:39.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:57:39.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:57:39.56#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:39.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:39.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:39.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.07:57:39.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:39.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:39.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:57:39.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:57:39.63$vc4f8/va=6,5 2006.147.07:57:39.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:57:39.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:57:39.63#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:39.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:39.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:39.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:39.70#ibcon#[25=AT06-05\r\n] 2006.147.07:57:39.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:39.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:39.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:57:39.73#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:39.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:39.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:39.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:39.87#ibcon#[25=USB\r\n] 2006.147.07:57:39.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:39.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:39.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:57:39.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:57:39.90$vc4f8/valo=7,832.99 2006.147.07:57:39.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:57:39.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:57:39.90#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:39.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:39.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:39.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.07:57:39.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:39.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:39.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:57:39.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:57:39.96$vc4f8/va=7,5 2006.147.07:57:39.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.07:57:39.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.07:57:39.96#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:39.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:40.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:40.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:40.04#ibcon#[25=AT07-05\r\n] 2006.147.07:57:40.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:40.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:40.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.07:57:40.07#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:40.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:57:40.14#abcon#<5=/07 3.0 6.2 19.64 831011.5\r\n> 2006.147.07:57:40.16#abcon#{5=INTERFACE CLEAR} 2006.147.07:57:40.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:57:40.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:57:40.21#ibcon#[25=USB\r\n] 2006.147.07:57:40.22#abcon#[5=S1D000X0/0*\r\n] 2006.147.07:57:40.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:57:40.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.07:57:40.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:57:40.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:57:40.24$vc4f8/valo=8,852.99 2006.147.07:57:40.24#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.07:57:40.24#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.07:57:40.24#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:40.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:57:40.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:57:40.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:57:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.07:57:40.30#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:57:40.30#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.07:57:40.30#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.07:57:40.30#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.07:57:40.30$vc4f8/va=8,5 2006.147.07:57:40.30#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.07:57:40.30#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.07:57:40.30#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:40.30#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:57:40.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:57:40.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:57:40.40#ibcon#[25=AT08-05\r\n] 2006.147.07:57:40.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:57:40.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.07:57:40.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.07:57:40.43#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:40.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:57:40.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:57:40.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:57:40.57#ibcon#[25=USB\r\n] 2006.147.07:57:40.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:57:40.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.07:57:40.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.07:57:40.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.07:57:40.60$vc4f8/vblo=1,632.99 2006.147.07:57:40.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.07:57:40.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.07:57:40.60#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:40.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:40.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:40.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.07:57:40.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:40.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.07:57:40.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.07:57:40.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.07:57:40.66$vc4f8/vb=1,4 2006.147.07:57:40.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.07:57:40.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.07:57:40.66#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:40.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:40.66#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:40.66#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:40.68#ibcon#[27=AT01-04\r\n] 2006.147.07:57:40.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:40.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.07:57:40.71#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.07:57:40.71#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:40.71#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:40.83#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:40.83#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:40.85#ibcon#[27=USB\r\n] 2006.147.07:57:40.88#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:40.88#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.07:57:40.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.07:57:40.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.07:57:40.88$vc4f8/vblo=2,640.99 2006.147.07:57:40.88#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.07:57:40.88#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.07:57:40.88#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:40.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:40.88#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:40.88#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.07:57:40.94#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:40.94#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.07:57:40.94#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.07:57:40.94#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.07:57:40.94$vc4f8/vb=2,4 2006.147.07:57:40.94#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.07:57:40.94#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.07:57:40.94#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:40.94#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:41.00#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:41.00#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:41.02#ibcon#[27=AT02-04\r\n] 2006.147.07:57:41.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:41.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.07:57:41.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.07:57:41.05#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:41.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:41.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:41.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:41.21#ibcon#[27=USB\r\n] 2006.147.07:57:41.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:41.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.07:57:41.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.07:57:41.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.07:57:41.24$vc4f8/vblo=3,656.99 2006.147.07:57:41.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.07:57:41.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.07:57:41.24#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:41.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:41.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:41.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.07:57:41.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:41.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.07:57:41.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.07:57:41.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.07:57:41.30$vc4f8/vb=3,4 2006.147.07:57:41.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.07:57:41.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.07:57:41.30#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:41.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:41.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:41.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:41.38#ibcon#[27=AT03-04\r\n] 2006.147.07:57:41.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:41.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.07:57:41.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.07:57:41.41#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:41.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:41.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:41.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:41.55#ibcon#[27=USB\r\n] 2006.147.07:57:41.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:41.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.07:57:41.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.07:57:41.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.07:57:41.58$vc4f8/vblo=4,712.99 2006.147.07:57:41.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.07:57:41.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.07:57:41.58#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:41.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:41.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:41.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.07:57:41.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:41.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.07:57:41.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.07:57:41.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.07:57:41.64$vc4f8/vb=4,4 2006.147.07:57:41.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.07:57:41.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.07:57:41.64#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:41.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:41.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:41.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:41.72#ibcon#[27=AT04-04\r\n] 2006.147.07:57:41.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:41.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.07:57:41.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.07:57:41.75#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:41.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:41.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:41.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:41.89#ibcon#[27=USB\r\n] 2006.147.07:57:41.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:41.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.07:57:41.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.07:57:41.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.07:57:41.92$vc4f8/vblo=5,744.99 2006.147.07:57:41.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.07:57:41.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.07:57:41.92#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:41.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:41.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:41.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.07:57:41.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:41.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.07:57:41.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.07:57:41.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.07:57:41.98$vc4f8/vb=5,3 2006.147.07:57:41.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.07:57:41.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.07:57:41.98#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:41.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:42.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:42.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:42.06#ibcon#[27=AT05-03\r\n] 2006.147.07:57:42.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:42.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.07:57:42.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.07:57:42.09#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:42.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:42.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:42.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:42.23#ibcon#[27=USB\r\n] 2006.147.07:57:42.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:42.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.07:57:42.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.07:57:42.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.07:57:42.26$vc4f8/vblo=6,752.99 2006.147.07:57:42.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.07:57:42.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.07:57:42.26#ibcon#ireg 17 cls_cnt 0 2006.147.07:57:42.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:42.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:42.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.07:57:42.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:42.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.07:57:42.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.07:57:42.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.07:57:42.32$vc4f8/vb=6,4 2006.147.07:57:42.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.07:57:42.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.07:57:42.32#ibcon#ireg 11 cls_cnt 2 2006.147.07:57:42.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:42.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:42.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:42.40#ibcon#[27=AT06-04\r\n] 2006.147.07:57:42.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:42.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.07:57:42.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.07:57:42.43#ibcon#ireg 7 cls_cnt 0 2006.147.07:57:42.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:42.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:42.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:42.57#ibcon#[27=USB\r\n] 2006.147.07:57:42.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:42.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.07:57:42.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.07:57:42.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.07:57:42.60$vc4f8/vabw=wide 2006.147.07:57:42.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.07:57:42.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.07:57:42.60#ibcon#ireg 8 cls_cnt 0 2006.147.07:57:42.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:42.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:42.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:42.62#ibcon#[25=BW32\r\n] 2006.147.07:57:42.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:42.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.07:57:42.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.07:57:42.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.07:57:42.65$vc4f8/vbbw=wide 2006.147.07:57:42.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.07:57:42.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.07:57:42.65#ibcon#ireg 8 cls_cnt 0 2006.147.07:57:42.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:57:42.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:57:42.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:57:42.74#ibcon#[27=BW32\r\n] 2006.147.07:57:42.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:57:42.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.07:57:42.77#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.07:57:42.77#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.07:57:42.77$4f8m12a/ifd4f 2006.147.07:57:42.77$ifd4f/lo= 2006.147.07:57:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.07:57:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.07:57:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.07:57:42.77$ifd4f/patch= 2006.147.07:57:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.07:57:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.07:57:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.07:57:42.77$4f8m12a/"form=m,16.000,1:2 2006.147.07:57:42.77$4f8m12a/"tpicd 2006.147.07:57:42.77$4f8m12a/echo=off 2006.147.07:57:42.77$4f8m12a/xlog=off 2006.147.07:57:42.77:!2006.147.07:59:50 2006.147.07:58:25.13#trakl#Source acquired 2006.147.07:58:25.13#flagr#flagr/antenna,acquired 2006.147.07:59:50.00:preob 2006.147.07:59:50.14/onsource/TRACKING 2006.147.07:59:50.14:!2006.147.08:00:00 2006.147.08:00:00.00:data_valid=on 2006.147.08:00:00.00:midob 2006.147.08:00:01.14/onsource/TRACKING 2006.147.08:00:01.14/wx/19.62,1011.5,83 2006.147.08:00:01.21/cable/+6.5374E-03 2006.147.08:00:02.30/va/01,08,usb,yes,32,33 2006.147.08:00:02.30/va/02,07,usb,yes,32,33 2006.147.08:00:02.30/va/03,08,usb,yes,24,24 2006.147.08:00:02.30/va/04,07,usb,yes,32,35 2006.147.08:00:02.30/va/05,06,usb,yes,37,39 2006.147.08:00:02.30/va/06,05,usb,yes,37,37 2006.147.08:00:02.30/va/07,05,usb,yes,37,37 2006.147.08:00:02.30/va/08,05,usb,yes,40,39 2006.147.08:00:02.53/valo/01,532.99,yes,locked 2006.147.08:00:02.53/valo/02,572.99,yes,locked 2006.147.08:00:02.53/valo/03,672.99,yes,locked 2006.147.08:00:02.53/valo/04,832.99,yes,locked 2006.147.08:00:02.53/valo/05,652.99,yes,locked 2006.147.08:00:02.53/valo/06,772.99,yes,locked 2006.147.08:00:02.53/valo/07,832.99,yes,locked 2006.147.08:00:02.53/valo/08,852.99,yes,locked 2006.147.08:00:03.62/vb/01,04,usb,yes,30,28 2006.147.08:00:03.62/vb/02,04,usb,yes,32,32 2006.147.08:00:03.62/vb/03,04,usb,yes,27,31 2006.147.08:00:03.62/vb/04,04,usb,yes,28,28 2006.147.08:00:03.62/vb/05,03,usb,yes,33,37 2006.147.08:00:03.62/vb/06,04,usb,yes,27,30 2006.147.08:00:03.62/vb/07,04,usb,yes,29,29 2006.147.08:00:03.62/vb/08,03,usb,yes,34,37 2006.147.08:00:03.86/vblo/01,632.99,yes,locked 2006.147.08:00:03.86/vblo/02,640.99,yes,locked 2006.147.08:00:03.86/vblo/03,656.99,yes,locked 2006.147.08:00:03.86/vblo/04,712.99,yes,locked 2006.147.08:00:03.86/vblo/05,744.99,yes,locked 2006.147.08:00:03.86/vblo/06,752.99,yes,locked 2006.147.08:00:03.86/vblo/07,734.99,yes,locked 2006.147.08:00:03.86/vblo/08,744.99,yes,locked 2006.147.08:00:04.01/vabw/8 2006.147.08:00:04.16/vbbw/8 2006.147.08:00:04.25/xfe/off,on,15.0 2006.147.08:00:04.62/ifatt/23,28,28,28 2006.147.08:00:05.08/fmout-gps/S +4.89E-07 2006.147.08:00:05.12:!2006.147.08:01:00 2006.147.08:01:00.01:data_valid=off 2006.147.08:01:00.01:postob 2006.147.08:01:00.10/cable/+6.5371E-03 2006.147.08:01:00.10/wx/19.61,1011.5,83 2006.147.08:01:01.08/fmout-gps/S +4.88E-07 2006.147.08:01:01.08:scan_name=147-0801,k06147,60 2006.147.08:01:01.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.147.08:01:01.14#flagr#flagr/antenna,new-source 2006.147.08:01:02.14:checkk5 2006.147.08:01:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:01:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:01:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:01:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:01:04.03/chk_obsdata//k5ts1/k06147_ts1_147-0800*_20??1470800??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:01:04.41/chk_obsdata//k5ts2/k06147_ts2_147-0800*_20??1470800??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:01:04.79/chk_obsdata//k5ts3/k06147_ts3_147-0800*_20??1470800??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:01:05.16/chk_obsdata//k5ts4/k06147_ts4_147-0800*_20??1470800??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:01:05.86/k5log//k5ts1_log_newline 2006.147.08:01:06.56/k5log//k5ts2_log_newline 2006.147.08:01:07.25/k5log//k5ts3_log_newline 2006.147.08:01:07.94/k5log//k5ts4_log_newline 2006.147.08:01:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:01:07.97:4f8m12a=2 2006.147.08:01:07.97$4f8m12a/echo=on 2006.147.08:01:07.97$4f8m12a/pcalon 2006.147.08:01:07.97$pcalon/"no phase cal control is implemented here 2006.147.08:01:07.97$4f8m12a/"tpicd=stop 2006.147.08:01:07.97$4f8m12a/vc4f8 2006.147.08:01:07.97$vc4f8/valo=1,532.99 2006.147.08:01:07.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:01:07.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:01:07.97#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:07.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:07.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:07.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:01:08.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:08.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:08.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:01:08.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:01:08.07$vc4f8/va=1,8 2006.147.08:01:08.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:01:08.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:01:08.07#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:08.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:08.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:08.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:08.11#ibcon#[25=AT01-08\r\n] 2006.147.08:01:08.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:08.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:08.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:01:08.14#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:08.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:08.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:08.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:08.28#ibcon#[25=USB\r\n] 2006.147.08:01:08.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:08.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:08.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:01:08.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:01:08.31$vc4f8/valo=2,572.99 2006.147.08:01:08.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:01:08.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:01:08.31#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:08.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:08.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:08.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:08.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:01:08.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:08.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:08.39#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:01:08.39#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:01:08.39$vc4f8/va=2,7 2006.147.08:01:08.39#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:01:08.39#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:01:08.39#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:08.39#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:08.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:08.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:08.45#ibcon#[25=AT02-07\r\n] 2006.147.08:01:08.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:08.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:08.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:01:08.48#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:08.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:08.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:08.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:08.62#ibcon#[25=USB\r\n] 2006.147.08:01:08.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:08.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:08.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:01:08.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:01:08.65$vc4f8/valo=3,672.99 2006.147.08:01:08.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:01:08.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:01:08.65#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:08.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:08.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:08.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:08.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:01:08.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:08.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:08.73#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:01:08.73#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:01:08.73$vc4f8/va=3,8 2006.147.08:01:08.73#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:01:08.73#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:01:08.73#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:08.73#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:08.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:08.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:08.79#ibcon#[25=AT03-08\r\n] 2006.147.08:01:08.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:08.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:08.82#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:01:08.82#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:08.82#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:08.94#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:08.94#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:08.96#ibcon#[25=USB\r\n] 2006.147.08:01:08.99#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:08.99#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:08.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:01:08.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:01:08.99$vc4f8/valo=4,832.99 2006.147.08:01:08.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:01:08.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:01:08.99#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:08.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:08.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:08.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:09.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:01:09.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:09.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:09.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:01:09.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:01:09.05$vc4f8/va=4,7 2006.147.08:01:09.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:01:09.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:01:09.05#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:09.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:09.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:09.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:09.13#ibcon#[25=AT04-07\r\n] 2006.147.08:01:09.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:09.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:09.16#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:01:09.16#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:09.16#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:09.28#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:09.28#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:09.30#ibcon#[25=USB\r\n] 2006.147.08:01:09.33#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:09.33#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:09.33#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:01:09.33#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:01:09.33$vc4f8/valo=5,652.99 2006.147.08:01:09.33#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:01:09.33#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:01:09.33#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:09.33#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:09.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:09.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:09.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:01:09.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:09.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:09.39#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:01:09.39#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:01:09.39$vc4f8/va=5,6 2006.147.08:01:09.39#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:01:09.39#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:01:09.39#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:09.39#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:09.45#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:09.45#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:09.47#ibcon#[25=AT05-06\r\n] 2006.147.08:01:09.50#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:09.50#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:09.50#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:01:09.50#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:09.50#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:09.62#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:09.62#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:09.64#ibcon#[25=USB\r\n] 2006.147.08:01:09.67#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:09.67#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:09.67#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:01:09.67#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:01:09.67$vc4f8/valo=6,772.99 2006.147.08:01:09.67#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:01:09.67#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:01:09.67#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:09.67#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:09.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:09.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:09.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:01:09.75#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:09.75#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:09.75#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:01:09.75#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:01:09.75$vc4f8/va=6,5 2006.147.08:01:09.75#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.08:01:09.75#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.08:01:09.75#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:09.75#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:09.79#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:09.79#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:09.81#ibcon#[25=AT06-05\r\n] 2006.147.08:01:09.84#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:09.84#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:09.84#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.08:01:09.84#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:09.84#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:01:09.96#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:01:09.96#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:01:09.98#ibcon#[25=USB\r\n] 2006.147.08:01:10.01#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:01:10.01#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:01:10.01#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:01:10.01#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:01:10.01$vc4f8/valo=7,832.99 2006.147.08:01:10.01#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.08:01:10.01#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.08:01:10.01#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:10.01#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:01:10.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:01:10.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:01:10.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:01:10.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:01:10.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:01:10.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:01:10.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:01:10.07$vc4f8/va=7,5 2006.147.08:01:10.07#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.08:01:10.07#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.08:01:10.07#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:10.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:01:10.13#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:01:10.13#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:01:10.15#ibcon#[25=AT07-05\r\n] 2006.147.08:01:10.18#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:01:10.18#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:01:10.18#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.08:01:10.18#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:10.18#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:01:10.30#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:01:10.30#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:01:10.32#ibcon#[25=USB\r\n] 2006.147.08:01:10.35#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:01:10.35#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:01:10.35#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:01:10.35#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:01:10.35$vc4f8/valo=8,852.99 2006.147.08:01:10.35#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.08:01:10.35#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.08:01:10.35#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:10.35#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:01:10.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:01:10.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:01:10.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:01:10.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:01:10.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:01:10.41#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:01:10.41#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:01:10.41$vc4f8/va=8,5 2006.147.08:01:10.41#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.08:01:10.41#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.08:01:10.41#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:10.41#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:01:10.47#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:01:10.47#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:01:10.49#ibcon#[25=AT08-05\r\n] 2006.147.08:01:10.52#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:01:10.52#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:01:10.52#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.08:01:10.52#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:10.52#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:01:10.64#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:01:10.64#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:01:10.66#ibcon#[25=USB\r\n] 2006.147.08:01:10.69#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:01:10.69#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:01:10.69#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:01:10.69#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:01:10.69$vc4f8/vblo=1,632.99 2006.147.08:01:10.69#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:01:10.69#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:01:10.69#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:10.69#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:01:10.69#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:01:10.69#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:01:10.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:01:10.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:01:10.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:01:10.75#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:01:10.75#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:01:10.75$vc4f8/vb=1,4 2006.147.08:01:10.75#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.08:01:10.75#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.08:01:10.75#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:10.75#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:01:10.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:01:10.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:01:10.77#ibcon#[27=AT01-04\r\n] 2006.147.08:01:10.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:01:10.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:01:10.80#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.08:01:10.80#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:10.80#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:01:10.92#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:01:10.92#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:01:10.94#ibcon#[27=USB\r\n] 2006.147.08:01:10.97#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:01:10.97#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:01:10.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:01:10.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:01:10.97$vc4f8/vblo=2,640.99 2006.147.08:01:10.97#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:01:10.97#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:01:10.97#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:10.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:10.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:10.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:10.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:01:11.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:11.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:01:11.03#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:01:11.03#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:01:11.03$vc4f8/vb=2,4 2006.147.08:01:11.03#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:01:11.03#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:01:11.03#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:11.03#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:11.09#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:11.09#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:11.11#ibcon#[27=AT02-04\r\n] 2006.147.08:01:11.14#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:11.14#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:01:11.14#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:01:11.14#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:11.14#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:11.26#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:11.26#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:11.28#ibcon#[27=USB\r\n] 2006.147.08:01:11.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:11.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:01:11.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:01:11.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:01:11.31$vc4f8/vblo=3,656.99 2006.147.08:01:11.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:01:11.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:01:11.31#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:11.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:11.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:11.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:11.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:01:11.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:11.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:01:11.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:01:11.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:01:11.37$vc4f8/vb=3,4 2006.147.08:01:11.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:01:11.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:01:11.37#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:11.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:11.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:11.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:11.46#ibcon#[27=AT03-04\r\n] 2006.147.08:01:11.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:11.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:01:11.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:01:11.49#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:11.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:11.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:11.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:11.63#ibcon#[27=USB\r\n] 2006.147.08:01:11.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:11.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:01:11.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:01:11.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:01:11.66$vc4f8/vblo=4,712.99 2006.147.08:01:11.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:01:11.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:01:11.66#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:11.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:11.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:11.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:11.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:01:11.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:11.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:01:11.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:01:11.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:01:11.72$vc4f8/vb=4,4 2006.147.08:01:11.72#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:01:11.72#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:01:11.72#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:11.72#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:11.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:11.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:11.80#ibcon#[27=AT04-04\r\n] 2006.147.08:01:11.83#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:11.83#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:01:11.83#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:01:11.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:11.83#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:11.95#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:11.95#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:11.97#ibcon#[27=USB\r\n] 2006.147.08:01:12.00#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:12.00#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:01:12.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:01:12.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:01:12.00$vc4f8/vblo=5,744.99 2006.147.08:01:12.00#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:01:12.00#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:01:12.00#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:12.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:12.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:12.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:12.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:01:12.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:12.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:01:12.06#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:01:12.06#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:01:12.06$vc4f8/vb=5,3 2006.147.08:01:12.06#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:01:12.06#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:01:12.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:12.06#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:12.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:12.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:12.14#ibcon#[27=AT05-03\r\n] 2006.147.08:01:12.17#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:12.17#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:01:12.17#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:01:12.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:12.17#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:12.29#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:12.29#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:12.31#ibcon#[27=USB\r\n] 2006.147.08:01:12.34#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:12.34#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:01:12.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:01:12.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:01:12.34$vc4f8/vblo=6,752.99 2006.147.08:01:12.34#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:01:12.34#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:01:12.34#ibcon#ireg 17 cls_cnt 0 2006.147.08:01:12.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:12.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:12.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:12.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:01:12.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:12.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:01:12.40#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:01:12.40#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:01:12.40$vc4f8/vb=6,4 2006.147.08:01:12.40#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:01:12.40#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:01:12.40#ibcon#ireg 11 cls_cnt 2 2006.147.08:01:12.40#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:12.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:12.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:12.48#ibcon#[27=AT06-04\r\n] 2006.147.08:01:12.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:12.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:01:12.51#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:01:12.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:01:12.51#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:12.63#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:12.63#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:12.65#ibcon#[27=USB\r\n] 2006.147.08:01:12.68#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:12.68#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:01:12.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:01:12.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:01:12.68$vc4f8/vabw=wide 2006.147.08:01:12.68#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:01:12.68#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:01:12.68#ibcon#ireg 8 cls_cnt 0 2006.147.08:01:12.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:12.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:12.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:12.70#ibcon#[25=BW32\r\n] 2006.147.08:01:12.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:12.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:01:12.73#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:01:12.73#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:01:12.73$vc4f8/vbbw=wide 2006.147.08:01:12.73#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:01:12.73#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:01:12.73#ibcon#ireg 8 cls_cnt 0 2006.147.08:01:12.73#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:01:12.80#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:01:12.80#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:01:12.82#ibcon#[27=BW32\r\n] 2006.147.08:01:12.85#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:01:12.85#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:01:12.85#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:01:12.85#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:01:12.85$4f8m12a/ifd4f 2006.147.08:01:12.85$ifd4f/lo= 2006.147.08:01:12.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:01:12.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:01:12.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:01:12.85$ifd4f/patch= 2006.147.08:01:12.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:01:12.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:01:12.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:01:12.85$4f8m12a/"form=m,16.000,1:2 2006.147.08:01:12.85$4f8m12a/"tpicd 2006.147.08:01:12.85$4f8m12a/echo=off 2006.147.08:01:12.85$4f8m12a/xlog=off 2006.147.08:01:12.85:!2006.147.08:01:40 2006.147.08:01:20.14#trakl#Source acquired 2006.147.08:01:22.14#flagr#flagr/antenna,acquired 2006.147.08:01:40.00:preob 2006.147.08:01:41.14/onsource/TRACKING 2006.147.08:01:41.14:!2006.147.08:01:50 2006.147.08:01:50.00:data_valid=on 2006.147.08:01:50.00:midob 2006.147.08:01:50.14/onsource/TRACKING 2006.147.08:01:50.14/wx/19.61,1011.6,84 2006.147.08:01:50.28/cable/+6.5360E-03 2006.147.08:01:51.37/va/01,08,usb,yes,34,35 2006.147.08:01:51.37/va/02,07,usb,yes,34,35 2006.147.08:01:51.37/va/03,08,usb,yes,25,26 2006.147.08:01:51.37/va/04,07,usb,yes,35,37 2006.147.08:01:51.37/va/05,06,usb,yes,39,41 2006.147.08:01:51.37/va/06,05,usb,yes,40,39 2006.147.08:01:51.37/va/07,05,usb,yes,40,39 2006.147.08:01:51.37/va/08,05,usb,yes,43,42 2006.147.08:01:51.60/valo/01,532.99,yes,locked 2006.147.08:01:51.60/valo/02,572.99,yes,locked 2006.147.08:01:51.60/valo/03,672.99,yes,locked 2006.147.08:01:51.60/valo/04,832.99,yes,locked 2006.147.08:01:51.60/valo/05,652.99,yes,locked 2006.147.08:01:51.60/valo/06,772.99,yes,locked 2006.147.08:01:51.60/valo/07,832.99,yes,locked 2006.147.08:01:51.60/valo/08,852.99,yes,locked 2006.147.08:01:52.69/vb/01,04,usb,yes,30,29 2006.147.08:01:52.69/vb/02,04,usb,yes,32,33 2006.147.08:01:52.69/vb/03,04,usb,yes,28,32 2006.147.08:01:52.69/vb/04,04,usb,yes,29,29 2006.147.08:01:52.69/vb/05,03,usb,yes,35,39 2006.147.08:01:52.69/vb/06,04,usb,yes,29,32 2006.147.08:01:52.69/vb/07,04,usb,yes,31,31 2006.147.08:01:52.69/vb/08,03,usb,yes,36,40 2006.147.08:01:52.93/vblo/01,632.99,yes,locked 2006.147.08:01:52.93/vblo/02,640.99,yes,locked 2006.147.08:01:52.93/vblo/03,656.99,yes,locked 2006.147.08:01:52.93/vblo/04,712.99,yes,locked 2006.147.08:01:52.93/vblo/05,744.99,yes,locked 2006.147.08:01:52.93/vblo/06,752.99,yes,locked 2006.147.08:01:52.93/vblo/07,734.99,yes,locked 2006.147.08:01:52.93/vblo/08,744.99,yes,locked 2006.147.08:01:53.08/vabw/8 2006.147.08:01:53.23/vbbw/8 2006.147.08:01:53.32/xfe/off,on,13.7 2006.147.08:01:53.71/ifatt/23,28,28,28 2006.147.08:01:54.08/fmout-gps/S +4.88E-07 2006.147.08:01:54.12:!2006.147.08:02:50 2006.147.08:02:50.01:data_valid=off 2006.147.08:02:50.01:postob 2006.147.08:02:50.21/cable/+6.5377E-03 2006.147.08:02:50.21/wx/19.60,1011.6,84 2006.147.08:02:51.08/fmout-gps/S +4.88E-07 2006.147.08:02:51.08:scan_name=147-0804,k06147,100 2006.147.08:02:51.09:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.147.08:02:51.14#flagr#flagr/antenna,new-source 2006.147.08:02:52.14:checkk5 2006.147.08:02:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:02:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:02:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:02:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:02:54.02/chk_obsdata//k5ts1/k06147_ts1_147-0801*_20??1470801??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:02:54.39/chk_obsdata//k5ts2/k06147_ts2_147-0801*_20??1470801??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:02:54.77/chk_obsdata//k5ts3/k06147_ts3_147-0801*_20??1470801??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:02:55.15/chk_obsdata//k5ts4/k06147_ts4_147-0801*_20??1470801??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:02:55.85/k5log//k5ts1_log_newline 2006.147.08:02:56.54/k5log//k5ts2_log_newline 2006.147.08:02:57.24/k5log//k5ts3_log_newline 2006.147.08:02:57.93/k5log//k5ts4_log_newline 2006.147.08:02:57.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:02:57.96:4f8m12a=2 2006.147.08:02:57.96$4f8m12a/echo=on 2006.147.08:02:57.96$4f8m12a/pcalon 2006.147.08:02:57.96$pcalon/"no phase cal control is implemented here 2006.147.08:02:57.96$4f8m12a/"tpicd=stop 2006.147.08:02:57.96$4f8m12a/vc4f8 2006.147.08:02:57.96$vc4f8/valo=1,532.99 2006.147.08:02:57.97#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:02:57.97#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:02:57.97#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:57.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:02:57.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:02:57.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:02:58.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:02:58.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:02:58.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:02:58.06#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:02:58.06#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:02:58.06$vc4f8/va=1,8 2006.147.08:02:58.06#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:02:58.06#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:02:58.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:58.06#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:02:58.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:02:58.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:02:58.10#ibcon#[25=AT01-08\r\n] 2006.147.08:02:58.13#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:02:58.13#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:02:58.13#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:02:58.13#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:58.13#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:02:58.25#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:02:58.25#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:02:58.27#ibcon#[25=USB\r\n] 2006.147.08:02:58.32#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:02:58.32#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:02:58.32#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:02:58.32#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:02:58.32$vc4f8/valo=2,572.99 2006.147.08:02:58.32#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:02:58.32#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:02:58.32#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:58.32#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:02:58.32#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:02:58.32#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:02:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:02:58.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:02:58.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:02:58.38#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:02:58.38#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:02:58.38$vc4f8/va=2,7 2006.147.08:02:58.38#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:02:58.38#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:02:58.38#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:58.38#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:02:58.44#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:02:58.44#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:02:58.46#ibcon#[25=AT02-07\r\n] 2006.147.08:02:58.51#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:02:58.51#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:02:58.51#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:02:58.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:58.51#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:02:58.63#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:02:58.63#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:02:58.65#ibcon#[25=USB\r\n] 2006.147.08:02:58.70#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:02:58.70#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:02:58.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:02:58.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:02:58.70$vc4f8/valo=3,672.99 2006.147.08:02:58.70#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:02:58.70#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:02:58.70#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:58.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:02:58.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:02:58.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:02:58.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:02:58.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:02:58.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:02:58.76#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:02:58.76#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:02:58.76$vc4f8/va=3,8 2006.147.08:02:58.76#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:02:58.76#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:02:58.76#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:58.76#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:02:58.82#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:02:58.82#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:02:58.84#ibcon#[25=AT03-08\r\n] 2006.147.08:02:58.87#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:02:58.87#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:02:58.87#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:02:58.87#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:58.87#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:02:58.99#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:02:58.99#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:02:59.01#ibcon#[25=USB\r\n] 2006.147.08:02:59.04#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:02:59.04#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:02:59.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:02:59.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:02:59.04$vc4f8/valo=4,832.99 2006.147.08:02:59.04#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:02:59.04#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:02:59.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:59.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:02:59.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:02:59.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:02:59.06#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:02:59.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:02:59.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:02:59.10#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:02:59.10#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:02:59.10$vc4f8/va=4,7 2006.147.08:02:59.10#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:02:59.10#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:02:59.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:59.10#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:02:59.16#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:02:59.16#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:02:59.18#ibcon#[25=AT04-07\r\n] 2006.147.08:02:59.21#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:02:59.21#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:02:59.21#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:02:59.21#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:59.21#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:02:59.33#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:02:59.33#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:02:59.35#ibcon#[25=USB\r\n] 2006.147.08:02:59.38#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:02:59.38#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:02:59.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:02:59.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:02:59.38$vc4f8/valo=5,652.99 2006.147.08:02:59.38#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:02:59.38#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:02:59.38#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:59.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:02:59.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:02:59.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:02:59.40#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:02:59.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:02:59.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:02:59.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:02:59.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:02:59.44$vc4f8/va=5,6 2006.147.08:02:59.44#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:02:59.44#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:02:59.44#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:59.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:02:59.50#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:02:59.50#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:02:59.52#ibcon#[25=AT05-06\r\n] 2006.147.08:02:59.55#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:02:59.55#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:02:59.55#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:02:59.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:59.55#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:02:59.67#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:02:59.67#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:02:59.69#ibcon#[25=USB\r\n] 2006.147.08:02:59.72#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:02:59.72#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:02:59.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:02:59.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:02:59.72$vc4f8/valo=6,772.99 2006.147.08:02:59.72#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:02:59.72#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:02:59.72#ibcon#ireg 17 cls_cnt 0 2006.147.08:02:59.72#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:02:59.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:02:59.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:02:59.74#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:02:59.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:02:59.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:02:59.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:02:59.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:02:59.78$vc4f8/va=6,5 2006.147.08:02:59.78#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.08:02:59.78#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.08:02:59.78#ibcon#ireg 11 cls_cnt 2 2006.147.08:02:59.78#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:02:59.84#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:02:59.84#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:02:59.86#ibcon#[25=AT06-05\r\n] 2006.147.08:02:59.89#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:02:59.89#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:02:59.89#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.08:02:59.89#ibcon#ireg 7 cls_cnt 0 2006.147.08:02:59.89#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:03:00.01#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:03:00.01#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:03:00.03#ibcon#[25=USB\r\n] 2006.147.08:03:00.06#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:03:00.06#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:03:00.06#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:03:00.06#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:03:00.06$vc4f8/valo=7,832.99 2006.147.08:03:00.06#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.08:03:00.06#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.08:03:00.06#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:00.06#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:03:00.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:03:00.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:03:00.08#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:03:00.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:03:00.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:03:00.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:03:00.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:03:00.12$vc4f8/va=7,5 2006.147.08:03:00.12#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.08:03:00.12#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.08:03:00.12#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:00.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:03:00.18#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:03:00.18#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:03:00.20#ibcon#[25=AT07-05\r\n] 2006.147.08:03:00.23#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:03:00.23#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:03:00.23#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.08:03:00.23#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:00.23#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:03:00.35#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:03:00.35#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:03:00.37#ibcon#[25=USB\r\n] 2006.147.08:03:00.40#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:03:00.40#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:03:00.40#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:03:00.40#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:03:00.40$vc4f8/valo=8,852.99 2006.147.08:03:00.40#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.08:03:00.40#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.08:03:00.40#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:00.40#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:03:00.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:03:00.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:03:00.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:03:00.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:03:00.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:03:00.46#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:03:00.46#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:03:00.46$vc4f8/va=8,5 2006.147.08:03:00.46#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.08:03:00.46#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.08:03:00.46#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:00.46#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:03:00.52#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:03:00.52#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:03:00.54#ibcon#[25=AT08-05\r\n] 2006.147.08:03:00.57#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:03:00.57#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:03:00.57#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.08:03:00.57#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:00.57#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:03:00.69#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:03:00.69#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:03:00.71#ibcon#[25=USB\r\n] 2006.147.08:03:00.74#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:03:00.74#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:03:00.74#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:03:00.74#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:03:00.74$vc4f8/vblo=1,632.99 2006.147.08:03:00.74#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.08:03:00.74#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.08:03:00.74#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:00.74#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:03:00.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:03:00.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:03:00.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:03:00.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:03:00.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:03:00.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:03:00.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:03:00.80$vc4f8/vb=1,4 2006.147.08:03:00.80#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.08:03:00.80#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.08:03:00.80#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:00.80#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:03:00.80#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:03:00.80#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:03:00.82#ibcon#[27=AT01-04\r\n] 2006.147.08:03:00.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:03:00.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:03:00.85#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.08:03:00.85#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:00.85#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:03:00.97#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:03:00.97#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:03:00.99#ibcon#[27=USB\r\n] 2006.147.08:03:01.04#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:03:01.04#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:03:01.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:03:01.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:03:01.04$vc4f8/vblo=2,640.99 2006.147.08:03:01.04#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:03:01.04#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:03:01.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:01.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:03:01.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:03:01.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:03:01.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:03:01.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:03:01.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:03:01.10#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:03:01.10#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:03:01.10$vc4f8/vb=2,4 2006.147.08:03:01.10#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:03:01.10#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:03:01.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:01.10#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:03:01.16#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:03:01.16#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:03:01.18#ibcon#[27=AT02-04\r\n] 2006.147.08:03:01.21#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:03:01.21#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:03:01.21#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:03:01.21#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:01.21#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:03:01.33#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:03:01.33#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:03:01.35#ibcon#[27=USB\r\n] 2006.147.08:03:01.38#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:03:01.38#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:03:01.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:03:01.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:03:01.38$vc4f8/vblo=3,656.99 2006.147.08:03:01.38#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:03:01.38#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:03:01.38#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:01.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:03:01.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:03:01.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:03:01.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:03:01.44#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:03:01.44#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:03:01.44#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:03:01.44#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:03:01.44$vc4f8/vb=3,4 2006.147.08:03:01.44#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:03:01.44#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:03:01.44#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:01.44#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:03:01.50#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:03:01.50#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:03:01.52#ibcon#[27=AT03-04\r\n] 2006.147.08:03:01.55#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:03:01.55#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:03:01.55#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:03:01.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:01.55#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:03:01.67#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:03:01.67#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:03:01.69#ibcon#[27=USB\r\n] 2006.147.08:03:01.72#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:03:01.72#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:03:01.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:03:01.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:03:01.72$vc4f8/vblo=4,712.99 2006.147.08:03:01.72#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:03:01.72#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:03:01.72#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:01.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:03:01.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:03:01.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:03:01.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:03:01.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:03:01.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:03:01.78#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:03:01.78#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:03:01.78$vc4f8/vb=4,4 2006.147.08:03:01.78#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:03:01.78#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:03:01.78#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:01.78#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:03:01.84#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:03:01.84#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:03:01.86#ibcon#[27=AT04-04\r\n] 2006.147.08:03:01.89#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:03:01.89#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:03:01.89#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:03:01.89#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:01.89#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:03:02.01#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:03:02.01#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:03:02.03#ibcon#[27=USB\r\n] 2006.147.08:03:02.06#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:03:02.06#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:03:02.06#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:03:02.06#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:03:02.06$vc4f8/vblo=5,744.99 2006.147.08:03:02.06#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:03:02.06#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:03:02.06#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:02.06#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:03:02.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:03:02.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:03:02.08#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:03:02.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:03:02.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:03:02.12#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:03:02.12#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:03:02.12$vc4f8/vb=5,3 2006.147.08:03:02.12#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:03:02.12#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:03:02.12#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:02.12#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:03:02.18#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:03:02.18#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:03:02.20#ibcon#[27=AT05-03\r\n] 2006.147.08:03:02.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:03:02.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:03:02.23#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:03:02.23#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:02.23#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:03:02.35#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:03:02.35#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:03:02.37#ibcon#[27=USB\r\n] 2006.147.08:03:02.40#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:03:02.40#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:03:02.40#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:03:02.40#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:03:02.40$vc4f8/vblo=6,752.99 2006.147.08:03:02.40#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:03:02.40#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:03:02.40#ibcon#ireg 17 cls_cnt 0 2006.147.08:03:02.40#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:03:02.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:03:02.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:03:02.42#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:03:02.48#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:03:02.48#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:03:02.48#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:03:02.48#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:03:02.48$vc4f8/vb=6,4 2006.147.08:03:02.48#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:03:02.48#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:03:02.48#ibcon#ireg 11 cls_cnt 2 2006.147.08:03:02.48#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:03:02.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:03:02.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:03:02.54#ibcon#[27=AT06-04\r\n] 2006.147.08:03:02.57#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:03:02.57#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:03:02.57#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:03:02.57#ibcon#ireg 7 cls_cnt 0 2006.147.08:03:02.57#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:03:02.69#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:03:02.69#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:03:02.71#ibcon#[27=USB\r\n] 2006.147.08:03:02.74#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:03:02.74#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:03:02.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:03:02.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:03:02.74$vc4f8/vabw=wide 2006.147.08:03:02.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:03:02.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:03:02.74#ibcon#ireg 8 cls_cnt 0 2006.147.08:03:02.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:03:02.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:03:02.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:03:02.76#ibcon#[25=BW32\r\n] 2006.147.08:03:02.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:03:02.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:03:02.79#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:03:02.79#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:03:02.79$vc4f8/vbbw=wide 2006.147.08:03:02.79#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:03:02.79#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:03:02.79#ibcon#ireg 8 cls_cnt 0 2006.147.08:03:02.79#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:03:02.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:03:02.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:03:02.88#ibcon#[27=BW32\r\n] 2006.147.08:03:02.91#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:03:02.91#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:03:02.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:03:02.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:03:02.91$4f8m12a/ifd4f 2006.147.08:03:02.91$ifd4f/lo= 2006.147.08:03:02.91$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:03:02.91$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:03:02.91$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:03:02.91$ifd4f/patch= 2006.147.08:03:02.91$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:03:02.91$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:03:02.91$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:03:02.91$4f8m12a/"form=m,16.000,1:2 2006.147.08:03:02.91$4f8m12a/"tpicd 2006.147.08:03:02.91$4f8m12a/echo=off 2006.147.08:03:02.91$4f8m12a/xlog=off 2006.147.08:03:02.91:!2006.147.08:04:00 2006.147.08:03:39.14#trakl#Source acquired 2006.147.08:03:39.14#flagr#flagr/antenna,acquired 2006.147.08:04:00.00:preob 2006.147.08:04:01.14/onsource/TRACKING 2006.147.08:04:01.14:!2006.147.08:04:10 2006.147.08:04:10.00:data_valid=on 2006.147.08:04:10.00:midob 2006.147.08:04:10.14/onsource/TRACKING 2006.147.08:04:10.14/wx/19.59,1011.6,84 2006.147.08:04:10.20/cable/+6.5375E-03 2006.147.08:04:11.29/va/01,08,usb,yes,37,39 2006.147.08:04:11.29/va/02,07,usb,yes,38,39 2006.147.08:04:11.29/va/03,08,usb,yes,29,29 2006.147.08:04:11.29/va/04,07,usb,yes,39,42 2006.147.08:04:11.29/va/05,06,usb,yes,43,46 2006.147.08:04:11.29/va/06,05,usb,yes,44,44 2006.147.08:04:11.29/va/07,05,usb,yes,44,44 2006.147.08:04:11.29/va/08,05,usb,yes,47,47 2006.147.08:04:11.52/valo/01,532.99,yes,locked 2006.147.08:04:11.52/valo/02,572.99,yes,locked 2006.147.08:04:11.52/valo/03,672.99,yes,locked 2006.147.08:04:11.52/valo/04,832.99,yes,locked 2006.147.08:04:11.52/valo/05,652.99,yes,locked 2006.147.08:04:11.52/valo/06,772.99,yes,locked 2006.147.08:04:11.52/valo/07,832.99,yes,locked 2006.147.08:04:11.52/valo/08,852.99,yes,locked 2006.147.08:04:12.61/vb/01,04,usb,yes,30,29 2006.147.08:04:12.61/vb/02,04,usb,yes,32,33 2006.147.08:04:12.61/vb/03,04,usb,yes,28,32 2006.147.08:04:12.61/vb/04,04,usb,yes,29,29 2006.147.08:04:12.61/vb/05,03,usb,yes,35,39 2006.147.08:04:12.61/vb/06,04,usb,yes,29,32 2006.147.08:04:12.61/vb/07,04,usb,yes,31,31 2006.147.08:04:12.61/vb/08,03,usb,yes,35,39 2006.147.08:04:12.85/vblo/01,632.99,yes,locked 2006.147.08:04:12.85/vblo/02,640.99,yes,locked 2006.147.08:04:12.85/vblo/03,656.99,yes,locked 2006.147.08:04:12.85/vblo/04,712.99,yes,locked 2006.147.08:04:12.85/vblo/05,744.99,yes,locked 2006.147.08:04:12.85/vblo/06,752.99,yes,locked 2006.147.08:04:12.85/vblo/07,734.99,yes,locked 2006.147.08:04:12.85/vblo/08,744.99,yes,locked 2006.147.08:04:13.00/vabw/8 2006.147.08:04:13.15/vbbw/8 2006.147.08:04:13.24/xfe/off,on,14.7 2006.147.08:04:13.61/ifatt/23,28,28,28 2006.147.08:04:14.08/fmout-gps/S +4.88E-07 2006.147.08:04:14.16:!2006.147.08:05:50 2006.147.08:05:50.01:data_valid=off 2006.147.08:05:50.01:postob 2006.147.08:05:50.14/cable/+6.5383E-03 2006.147.08:05:50.14/wx/19.57,1011.6,87 2006.147.08:05:51.08/fmout-gps/S +4.87E-07 2006.147.08:05:51.08:scan_name=147-0807,k06147,60 2006.147.08:05:51.09:source=0955+476,095819.67,472507.8,2000.0,cw 2006.147.08:05:52.13#flagr#flagr/antenna,new-source 2006.147.08:05:52.13:checkk5 2006.147.08:05:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:05:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:05:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:05:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:05:54.02/chk_obsdata//k5ts1/k06147_ts1_147-0804*_20??1470804??.k5 file size is correct (nominal:800MB, actual:792MB). 2006.147.08:05:54.40/chk_obsdata//k5ts2/k06147_ts2_147-0804*_20??1470804??.k5 file size is correct (nominal:800MB, actual:792MB). 2006.147.08:05:54.77/chk_obsdata//k5ts3/k06147_ts3_147-0804*_20??1470804??.k5 file size is correct (nominal:800MB, actual:792MB). 2006.147.08:05:55.15/chk_obsdata//k5ts4/k06147_ts4_147-0804*_20??1470804??.k5 file size is correct (nominal:800MB, actual:792MB). 2006.147.08:05:55.85/k5log//k5ts1_log_newline 2006.147.08:05:56.54/k5log//k5ts2_log_newline 2006.147.08:05:57.24/k5log//k5ts3_log_newline 2006.147.08:05:57.93/k5log//k5ts4_log_newline 2006.147.08:05:57.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:05:57.96:4f8m12a=2 2006.147.08:05:57.96$4f8m12a/echo=on 2006.147.08:05:57.96$4f8m12a/pcalon 2006.147.08:05:57.96$pcalon/"no phase cal control is implemented here 2006.147.08:05:57.96$4f8m12a/"tpicd=stop 2006.147.08:05:57.96$4f8m12a/vc4f8 2006.147.08:05:57.96$vc4f8/valo=1,532.99 2006.147.08:05:57.96#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.08:05:57.96#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.08:05:57.96#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:57.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:05:57.96#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:05:57.96#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:05:58.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:05:58.06#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:05:58.06#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:05:58.06#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:05:58.06#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:05:58.06$vc4f8/va=1,8 2006.147.08:05:58.06#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.08:05:58.06#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.08:05:58.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:58.06#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:05:58.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:05:58.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:05:58.10#ibcon#[25=AT01-08\r\n] 2006.147.08:05:58.13#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:05:58.13#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:05:58.13#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.08:05:58.13#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:58.13#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:05:58.25#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:05:58.25#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:05:58.27#ibcon#[25=USB\r\n] 2006.147.08:05:58.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:05:58.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:05:58.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:05:58.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:05:58.30$vc4f8/valo=2,572.99 2006.147.08:05:58.30#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:05:58.30#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:05:58.30#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:58.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:05:58.30#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:05:58.30#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:05:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:05:58.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:05:58.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:05:58.38#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:05:58.38#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:05:58.38$vc4f8/va=2,7 2006.147.08:05:58.38#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.08:05:58.38#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.08:05:58.38#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:58.38#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:05:58.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:05:58.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:05:58.44#ibcon#[25=AT02-07\r\n] 2006.147.08:05:58.47#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:05:58.47#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:05:58.47#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.08:05:58.47#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:58.47#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:05:58.57#abcon#<5=/07 2.8 7.2 19.56 871011.6\r\n> 2006.147.08:05:58.59#abcon#{5=INTERFACE CLEAR} 2006.147.08:05:58.59#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:05:58.59#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:05:58.61#ibcon#[25=USB\r\n] 2006.147.08:05:58.65#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:05:58.65#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:05:58.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:05:58.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:05:58.65$vc4f8/valo=3,672.99 2006.147.08:05:58.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.08:05:58.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.08:05:58.65#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:58.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:05:58.65#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:05:58.65#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:05:58.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:05:58.67#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:05:58.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:05:58.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:05:58.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:05:58.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:05:58.73$vc4f8/va=3,8 2006.147.08:05:58.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.08:05:58.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.08:05:58.73#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:58.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:05:58.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:05:58.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:05:58.79#ibcon#[25=AT03-08\r\n] 2006.147.08:05:58.82#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:05:58.82#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:05:58.82#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.08:05:58.82#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:58.82#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:05:58.94#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:05:58.94#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:05:58.96#ibcon#[25=USB\r\n] 2006.147.08:05:58.99#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:05:58.99#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:05:58.99#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:05:58.99#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:05:58.99$vc4f8/valo=4,832.99 2006.147.08:05:58.99#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.08:05:58.99#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.08:05:58.99#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:58.99#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:05:58.99#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:05:58.99#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:05:59.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:05:59.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:05:59.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:05:59.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:05:59.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:05:59.05$vc4f8/va=4,7 2006.147.08:05:59.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.08:05:59.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.08:05:59.05#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:59.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:05:59.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:05:59.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:05:59.13#ibcon#[25=AT04-07\r\n] 2006.147.08:05:59.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:05:59.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:05:59.16#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.08:05:59.16#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:59.16#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:05:59.28#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:05:59.28#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:05:59.30#ibcon#[25=USB\r\n] 2006.147.08:05:59.33#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:05:59.33#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:05:59.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:05:59.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:05:59.33$vc4f8/valo=5,652.99 2006.147.08:05:59.33#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.08:05:59.33#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.08:05:59.33#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:59.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:05:59.33#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:05:59.33#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:05:59.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:05:59.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:05:59.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:05:59.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:05:59.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:05:59.39$vc4f8/va=5,6 2006.147.08:05:59.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.08:05:59.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.08:05:59.39#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:59.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:05:59.45#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:05:59.45#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:05:59.47#ibcon#[25=AT05-06\r\n] 2006.147.08:05:59.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:05:59.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:05:59.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.08:05:59.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:59.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:05:59.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:05:59.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:05:59.65#ibcon#[25=USB\r\n] 2006.147.08:05:59.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:05:59.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:05:59.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:05:59.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:05:59.68$vc4f8/valo=6,772.99 2006.147.08:05:59.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:05:59.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:05:59.68#ibcon#ireg 17 cls_cnt 0 2006.147.08:05:59.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:05:59.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:05:59.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:05:59.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:05:59.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:05:59.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:05:59.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:05:59.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:05:59.74$vc4f8/va=6,5 2006.147.08:05:59.74#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.08:05:59.74#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.08:05:59.74#ibcon#ireg 11 cls_cnt 2 2006.147.08:05:59.74#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:05:59.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:05:59.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:05:59.82#ibcon#[25=AT06-05\r\n] 2006.147.08:05:59.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:05:59.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:05:59.85#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.08:05:59.85#ibcon#ireg 7 cls_cnt 0 2006.147.08:05:59.85#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:05:59.97#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:05:59.97#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:05:59.99#ibcon#[25=USB\r\n] 2006.147.08:06:00.02#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:06:00.02#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:06:00.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:06:00.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:06:00.02$vc4f8/valo=7,832.99 2006.147.08:06:00.02#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.08:06:00.02#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.08:06:00.02#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:00.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:06:00.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:06:00.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:06:00.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:06:00.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:06:00.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:06:00.08#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:06:00.08#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:06:00.08$vc4f8/va=7,5 2006.147.08:06:00.08#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.08:06:00.08#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.08:06:00.08#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:00.08#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:06:00.14#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:06:00.14#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:06:00.16#ibcon#[25=AT07-05\r\n] 2006.147.08:06:00.19#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:06:00.19#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:06:00.19#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.08:06:00.19#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:00.19#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:06:00.31#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:06:00.31#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:06:00.33#ibcon#[25=USB\r\n] 2006.147.08:06:00.36#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:06:00.36#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:06:00.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:06:00.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:06:00.36$vc4f8/valo=8,852.99 2006.147.08:06:00.36#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:06:00.36#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:06:00.36#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:00.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:06:00.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:06:00.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:06:00.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:06:00.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:06:00.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:06:00.42#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:06:00.42#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:06:00.42$vc4f8/va=8,5 2006.147.08:06:00.42#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.08:06:00.42#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.08:06:00.42#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:00.42#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:06:00.48#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:06:00.48#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:06:00.50#ibcon#[25=AT08-05\r\n] 2006.147.08:06:00.53#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:06:00.53#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:06:00.53#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.08:06:00.53#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:00.53#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:06:00.65#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:06:00.65#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:06:00.67#ibcon#[25=USB\r\n] 2006.147.08:06:00.70#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:06:00.70#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:06:00.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:06:00.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:06:00.70$vc4f8/vblo=1,632.99 2006.147.08:06:00.70#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.08:06:00.70#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.08:06:00.70#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:00.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:06:00.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:06:00.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:06:00.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:06:00.76#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:06:00.76#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:06:00.76#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:06:00.76#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:06:00.76$vc4f8/vb=1,4 2006.147.08:06:00.76#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.08:06:00.76#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.08:06:00.76#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:00.76#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:06:00.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:06:00.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:06:00.78#ibcon#[27=AT01-04\r\n] 2006.147.08:06:00.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:06:00.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:06:00.81#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.08:06:00.81#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:00.81#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:06:00.93#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:06:00.93#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:06:00.95#ibcon#[27=USB\r\n] 2006.147.08:06:00.98#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:06:00.98#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:06:00.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:06:00.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:06:00.98$vc4f8/vblo=2,640.99 2006.147.08:06:00.98#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:06:00.98#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:06:00.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:00.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:06:00.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:06:00.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:06:01.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:06:01.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:06:01.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:06:01.04#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:06:01.04#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:06:01.04$vc4f8/vb=2,4 2006.147.08:06:01.04#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.08:06:01.04#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.08:06:01.04#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:01.04#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:06:01.10#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:06:01.10#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:06:01.12#ibcon#[27=AT02-04\r\n] 2006.147.08:06:01.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:06:01.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:06:01.15#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.08:06:01.15#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:01.15#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:06:01.27#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:06:01.27#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:06:01.29#ibcon#[27=USB\r\n] 2006.147.08:06:01.32#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:06:01.32#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:06:01.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:06:01.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:06:01.32$vc4f8/vblo=3,656.99 2006.147.08:06:01.32#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.08:06:01.32#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.08:06:01.32#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:01.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:06:01.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:06:01.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:06:01.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:06:01.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:06:01.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:06:01.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:06:01.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:06:01.41$vc4f8/vb=3,4 2006.147.08:06:01.41#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.08:06:01.41#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.08:06:01.41#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:01.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:06:01.44#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:06:01.44#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:06:01.46#ibcon#[27=AT03-04\r\n] 2006.147.08:06:01.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:06:01.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:06:01.49#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.08:06:01.49#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:01.49#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:06:01.61#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:06:01.61#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:06:01.63#ibcon#[27=USB\r\n] 2006.147.08:06:01.66#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:06:01.66#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:06:01.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:06:01.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:06:01.66$vc4f8/vblo=4,712.99 2006.147.08:06:01.66#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.08:06:01.66#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.08:06:01.66#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:01.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:06:01.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:06:01.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:06:01.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:06:01.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:06:01.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:06:01.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:06:01.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:06:01.72$vc4f8/vb=4,4 2006.147.08:06:01.72#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.08:06:01.72#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.08:06:01.72#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:01.72#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:06:01.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:06:01.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:06:01.80#ibcon#[27=AT04-04\r\n] 2006.147.08:06:01.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:06:01.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:06:01.83#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.08:06:01.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:01.83#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:06:01.95#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:06:01.95#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:06:01.97#ibcon#[27=USB\r\n] 2006.147.08:06:02.00#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:06:02.00#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:06:02.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:06:02.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:06:02.00$vc4f8/vblo=5,744.99 2006.147.08:06:02.00#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.08:06:02.00#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.08:06:02.00#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:02.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:06:02.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:06:02.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:06:02.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:06:02.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:06:02.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:06:02.08#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:06:02.08#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:06:02.08$vc4f8/vb=5,3 2006.147.08:06:02.08#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.08:06:02.08#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.08:06:02.08#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:02.08#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:06:02.12#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:06:02.12#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:06:02.14#ibcon#[27=AT05-03\r\n] 2006.147.08:06:02.17#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:06:02.17#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:06:02.17#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.08:06:02.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:02.17#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:06:02.29#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:06:02.29#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:06:02.31#ibcon#[27=USB\r\n] 2006.147.08:06:02.34#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:06:02.34#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:06:02.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:06:02.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:06:02.34$vc4f8/vblo=6,752.99 2006.147.08:06:02.34#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.08:06:02.34#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.08:06:02.34#ibcon#ireg 17 cls_cnt 0 2006.147.08:06:02.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:06:02.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:06:02.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:06:02.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:06:02.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:06:02.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:06:02.40#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:06:02.40#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:06:02.40$vc4f8/vb=6,4 2006.147.08:06:02.40#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.08:06:02.40#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.08:06:02.40#ibcon#ireg 11 cls_cnt 2 2006.147.08:06:02.40#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:06:02.46#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:06:02.46#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:06:02.48#ibcon#[27=AT06-04\r\n] 2006.147.08:06:02.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:06:02.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:06:02.51#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.08:06:02.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:06:02.51#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:06:02.63#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:06:02.63#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:06:02.65#ibcon#[27=USB\r\n] 2006.147.08:06:02.68#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:06:02.68#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:06:02.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:06:02.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:06:02.68$vc4f8/vabw=wide 2006.147.08:06:02.68#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:06:02.68#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:06:02.68#ibcon#ireg 8 cls_cnt 0 2006.147.08:06:02.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:06:02.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:06:02.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:06:02.70#ibcon#[25=BW32\r\n] 2006.147.08:06:02.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:06:02.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:06:02.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:06:02.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:06:02.73$vc4f8/vbbw=wide 2006.147.08:06:02.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:06:02.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:06:02.73#ibcon#ireg 8 cls_cnt 0 2006.147.08:06:02.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:06:02.80#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:06:02.80#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:06:02.82#ibcon#[27=BW32\r\n] 2006.147.08:06:02.85#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:06:02.85#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:06:02.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:06:02.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:06:02.85$4f8m12a/ifd4f 2006.147.08:06:02.85$ifd4f/lo= 2006.147.08:06:02.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:06:02.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:06:02.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:06:02.85$ifd4f/patch= 2006.147.08:06:02.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:06:02.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:06:02.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:06:02.85$4f8m12a/"form=m,16.000,1:2 2006.147.08:06:02.85$4f8m12a/"tpicd 2006.147.08:06:02.85$4f8m12a/echo=off 2006.147.08:06:02.85$4f8m12a/xlog=off 2006.147.08:06:02.85:!2006.147.08:07:00 2006.147.08:06:38.13#trakl#Source acquired 2006.147.08:06:38.13#flagr#flagr/antenna,acquired 2006.147.08:07:00.00:preob 2006.147.08:07:00.13/onsource/TRACKING 2006.147.08:07:00.13:!2006.147.08:07:10 2006.147.08:07:10.00:data_valid=on 2006.147.08:07:10.00:midob 2006.147.08:07:11.13/onsource/TRACKING 2006.147.08:07:11.13/wx/19.54,1011.7,90 2006.147.08:07:11.24/cable/+6.5371E-03 2006.147.08:07:12.33/va/01,08,usb,yes,53,56 2006.147.08:07:12.33/va/02,07,usb,yes,54,56 2006.147.08:07:12.33/va/03,08,usb,yes,41,42 2006.147.08:07:12.33/va/04,07,usb,yes,55,59 2006.147.08:07:12.33/va/05,06,usb,yes,62,66 2006.147.08:07:12.33/va/06,05,usb,yes,63,63 2006.147.08:07:12.33/va/07,05,usb,yes,63,63 2006.147.08:07:12.33/va/08,05,usb,yes,67,66 2006.147.08:07:12.56/valo/01,532.99,yes,locked 2006.147.08:07:12.56/valo/02,572.99,yes,locked 2006.147.08:07:12.56/valo/03,672.99,yes,locked 2006.147.08:07:12.56/valo/04,832.99,yes,locked 2006.147.08:07:12.56/valo/05,652.99,yes,locked 2006.147.08:07:12.56/valo/06,772.99,yes,locked 2006.147.08:07:12.56/valo/07,832.99,yes,locked 2006.147.08:07:12.56/valo/08,852.99,yes,locked 2006.147.08:07:13.65/vb/01,04,usb,yes,31,30 2006.147.08:07:13.65/vb/02,04,usb,yes,33,34 2006.147.08:07:13.65/vb/03,04,usb,yes,29,33 2006.147.08:07:13.65/vb/04,04,usb,yes,31,30 2006.147.08:07:13.65/vb/05,03,usb,yes,36,40 2006.147.08:07:13.65/vb/06,04,usb,yes,30,33 2006.147.08:07:13.65/vb/07,04,usb,yes,32,32 2006.147.08:07:13.65/vb/08,03,usb,yes,36,40 2006.147.08:07:13.89/vblo/01,632.99,yes,locked 2006.147.08:07:13.89/vblo/02,640.99,yes,locked 2006.147.08:07:13.89/vblo/03,656.99,yes,locked 2006.147.08:07:13.89/vblo/04,712.99,yes,locked 2006.147.08:07:13.89/vblo/05,744.99,yes,locked 2006.147.08:07:13.89/vblo/06,752.99,yes,locked 2006.147.08:07:13.89/vblo/07,734.99,yes,locked 2006.147.08:07:13.89/vblo/08,744.99,yes,locked 2006.147.08:07:14.04/vabw/8 2006.147.08:07:14.19/vbbw/8 2006.147.08:07:14.37/xfe/off,on,15.0 2006.147.08:07:14.77/ifatt/23,28,28,28 2006.147.08:07:15.08/fmout-gps/S +4.86E-07 2006.147.08:07:15.12:!2006.147.08:08:10 2006.147.08:08:10.01:data_valid=off 2006.147.08:08:10.01:postob 2006.147.08:08:10.14/cable/+6.5385E-03 2006.147.08:08:10.14/wx/19.50,1011.6,90 2006.147.08:08:11.08/fmout-gps/S +4.88E-07 2006.147.08:08:11.08:scan_name=147-0809,k06147,60 2006.147.08:08:11.08:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.147.08:08:11.16#flagr#flagr/antenna,new-source 2006.147.08:08:12.14:checkk5 2006.147.08:08:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:08:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:08:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:08:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:08:14.04/chk_obsdata//k5ts1/k06147_ts1_147-0807*_20??1470807??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:08:14.42/chk_obsdata//k5ts2/k06147_ts2_147-0807*_20??1470807??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:08:17.47/chk_obsdata//k5ts3/k06147_ts3_147-0807*_20??1470807??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:08:17.85/chk_obsdata//k5ts4/k06147_ts4_147-0807*_20??1470807??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:08:18.54/k5log//k5ts1_log_newline 2006.147.08:08:19.24/k5log//k5ts2_log_newline 2006.147.08:08:19.94/k5log//k5ts3_log_newline 2006.147.08:08:20.63/k5log//k5ts4_log_newline 2006.147.08:08:20.66/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:08:20.66:4f8m12a=2 2006.147.08:08:20.66$4f8m12a/echo=on 2006.147.08:08:20.66$4f8m12a/pcalon 2006.147.08:08:20.66$pcalon/"no phase cal control is implemented here 2006.147.08:08:20.66$4f8m12a/"tpicd=stop 2006.147.08:08:20.66$4f8m12a/vc4f8 2006.147.08:08:20.66$vc4f8/valo=1,532.99 2006.147.08:08:20.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.08:08:20.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.08:08:20.66#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:20.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:20.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:20.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:20.71#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:08:20.76#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:20.76#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:20.76#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:08:20.76#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:08:20.76$vc4f8/va=1,8 2006.147.08:08:20.76#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.08:08:20.76#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.08:08:20.76#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:20.76#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:20.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:20.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:20.80#ibcon#[25=AT01-08\r\n] 2006.147.08:08:20.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:20.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:20.83#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.08:08:20.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:20.83#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:20.95#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:20.95#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:20.97#ibcon#[25=USB\r\n] 2006.147.08:08:21.00#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:21.00#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:21.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:08:21.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:08:21.00$vc4f8/valo=2,572.99 2006.147.08:08:21.00#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.08:08:21.00#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.08:08:21.00#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:21.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:21.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:21.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:21.04#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:08:21.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:21.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:21.08#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:08:21.08#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:08:21.08$vc4f8/va=2,7 2006.147.08:08:21.08#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.08:08:21.08#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.08:08:21.08#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:21.08#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:21.12#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:21.12#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:21.14#ibcon#[25=AT02-07\r\n] 2006.147.08:08:21.17#abcon#<5=/07 3.0 8.0 19.49 911011.6\r\n> 2006.147.08:08:21.17#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:21.17#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:21.17#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.08:08:21.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:21.17#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:21.19#abcon#{5=INTERFACE CLEAR} 2006.147.08:08:21.25#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:08:21.29#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:21.29#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:21.33#ibcon#[25=USB\r\n] 2006.147.08:08:21.36#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:21.36#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:21.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:08:21.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:08:21.36$vc4f8/valo=3,672.99 2006.147.08:08:21.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:08:21.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:08:21.36#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:21.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:21.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:21.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:21.38#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:08:21.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:21.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:21.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:08:21.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:08:21.42$vc4f8/va=3,8 2006.147.08:08:21.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:08:21.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:08:21.42#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:21.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:21.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:21.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:21.50#ibcon#[25=AT03-08\r\n] 2006.147.08:08:21.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:21.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:21.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:08:21.53#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:21.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:21.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:21.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:21.67#ibcon#[25=USB\r\n] 2006.147.08:08:21.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:21.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:21.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:08:21.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:08:21.70$vc4f8/valo=4,832.99 2006.147.08:08:21.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:08:21.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:08:21.70#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:21.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:21.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:21.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:21.72#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:08:21.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:21.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:21.76#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:08:21.76#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:08:21.76$vc4f8/va=4,7 2006.147.08:08:21.76#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:08:21.76#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:08:21.76#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:21.76#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:21.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:21.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:21.84#ibcon#[25=AT04-07\r\n] 2006.147.08:08:21.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:21.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:21.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:08:21.87#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:21.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:21.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:21.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:22.01#ibcon#[25=USB\r\n] 2006.147.08:08:22.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:22.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:22.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:08:22.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:08:22.04$vc4f8/valo=5,652.99 2006.147.08:08:22.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:08:22.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:08:22.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:22.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:22.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:22.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:22.06#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:08:22.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:22.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:22.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:08:22.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:08:22.10$vc4f8/va=5,6 2006.147.08:08:22.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:08:22.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:08:22.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:22.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:22.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:22.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:22.18#ibcon#[25=AT05-06\r\n] 2006.147.08:08:22.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:22.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:22.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:08:22.21#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:22.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:22.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:22.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:22.35#ibcon#[25=USB\r\n] 2006.147.08:08:22.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:22.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:22.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:08:22.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:08:22.38$vc4f8/valo=6,772.99 2006.147.08:08:22.38#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.08:08:22.38#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.08:08:22.38#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:22.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:22.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:22.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:22.40#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:08:22.44#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:22.44#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:22.44#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:08:22.44#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:08:22.44$vc4f8/va=6,5 2006.147.08:08:22.44#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.08:08:22.44#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.08:08:22.44#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:22.44#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:22.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:22.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:22.52#ibcon#[25=AT06-05\r\n] 2006.147.08:08:22.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:22.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:22.55#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.08:08:22.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:22.55#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:08:22.67#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:08:22.67#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:08:22.69#ibcon#[25=USB\r\n] 2006.147.08:08:22.72#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:08:22.72#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:08:22.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:08:22.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:08:22.72$vc4f8/valo=7,832.99 2006.147.08:08:22.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:08:22.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:08:22.72#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:22.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:08:22.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:08:22.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:08:22.74#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:08:22.78#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:08:22.78#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:08:22.78#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:08:22.78#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:08:22.78$vc4f8/va=7,5 2006.147.08:08:22.78#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.08:08:22.78#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.08:08:22.78#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:22.78#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:08:22.84#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:08:22.84#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:08:22.86#ibcon#[25=AT07-05\r\n] 2006.147.08:08:22.89#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:08:22.89#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:08:22.89#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.08:08:22.89#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:22.89#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:08:23.01#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:08:23.01#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:08:23.03#ibcon#[25=USB\r\n] 2006.147.08:08:23.06#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:08:23.06#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:08:23.06#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:08:23.06#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:08:23.06$vc4f8/valo=8,852.99 2006.147.08:08:23.06#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.08:08:23.06#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.08:08:23.06#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:23.06#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:08:23.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:08:23.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:08:23.08#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:08:23.12#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:08:23.12#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:08:23.12#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:08:23.12#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:08:23.12$vc4f8/va=8,5 2006.147.08:08:23.12#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.08:08:23.12#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.08:08:23.12#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:23.12#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:08:23.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:08:23.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:08:23.20#ibcon#[25=AT08-05\r\n] 2006.147.08:08:23.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:08:23.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:08:23.23#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.08:08:23.23#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:23.23#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:08:23.35#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:08:23.35#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:08:23.37#ibcon#[25=USB\r\n] 2006.147.08:08:23.40#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:08:23.40#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:08:23.40#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:08:23.40#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:08:23.40$vc4f8/vblo=1,632.99 2006.147.08:08:23.40#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.08:08:23.40#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.08:08:23.40#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:23.40#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:23.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:23.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:23.42#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:08:23.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:23.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:08:23.46#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:08:23.46#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:08:23.46$vc4f8/vb=1,4 2006.147.08:08:23.46#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.08:08:23.46#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.08:08:23.46#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:23.46#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:23.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:23.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:23.48#ibcon#[27=AT01-04\r\n] 2006.147.08:08:23.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:23.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:08:23.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.08:08:23.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:23.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:23.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:23.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:23.65#ibcon#[27=USB\r\n] 2006.147.08:08:23.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:23.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:08:23.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:08:23.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:08:23.68$vc4f8/vblo=2,640.99 2006.147.08:08:23.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.08:08:23.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.08:08:23.68#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:23.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:23.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:23.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:23.70#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:08:23.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:23.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:08:23.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:08:23.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:08:23.74$vc4f8/vb=2,4 2006.147.08:08:23.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.08:08:23.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.08:08:23.74#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:23.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:23.80#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:23.80#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:23.82#ibcon#[27=AT02-04\r\n] 2006.147.08:08:23.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:23.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:08:23.85#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.08:08:23.85#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:23.85#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:23.97#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:23.97#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:23.99#ibcon#[27=USB\r\n] 2006.147.08:08:24.02#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:24.02#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:08:24.02#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:08:24.02#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:08:24.02$vc4f8/vblo=3,656.99 2006.147.08:08:24.02#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.08:08:24.02#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.08:08:24.02#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:24.02#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:08:24.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:08:24.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:08:24.04#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:08:24.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:08:24.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:08:24.08#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:08:24.08#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:08:24.08$vc4f8/vb=3,4 2006.147.08:08:24.08#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.08:08:24.08#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.08:08:24.08#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:24.08#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:08:24.14#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:08:24.14#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:08:24.16#ibcon#[27=AT03-04\r\n] 2006.147.08:08:24.19#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:08:24.19#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:08:24.19#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.08:08:24.19#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:24.19#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:08:24.31#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:08:24.31#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:08:24.33#ibcon#[27=USB\r\n] 2006.147.08:08:24.36#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:08:24.36#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:08:24.36#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:08:24.36#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:08:24.36$vc4f8/vblo=4,712.99 2006.147.08:08:24.36#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:08:24.36#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:08:24.36#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:24.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:24.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:24.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:24.38#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:08:24.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:24.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:08:24.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:08:24.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:08:24.42$vc4f8/vb=4,4 2006.147.08:08:24.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:08:24.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:08:24.42#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:24.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:24.48#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:24.48#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:24.50#ibcon#[27=AT04-04\r\n] 2006.147.08:08:24.53#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:24.53#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:08:24.53#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:08:24.53#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:24.53#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:24.65#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:24.65#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:24.67#ibcon#[27=USB\r\n] 2006.147.08:08:24.70#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:24.70#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:08:24.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:08:24.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:08:24.70$vc4f8/vblo=5,744.99 2006.147.08:08:24.70#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:08:24.70#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:08:24.70#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:24.70#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:24.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:24.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:24.74#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:08:24.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:24.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:08:24.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:08:24.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:08:24.78$vc4f8/vb=5,3 2006.147.08:08:24.78#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:08:24.78#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:08:24.78#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:24.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:24.82#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:24.82#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:24.84#ibcon#[27=AT05-03\r\n] 2006.147.08:08:24.87#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:24.87#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:08:24.87#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:08:24.87#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:24.87#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:24.99#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:24.99#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:25.01#ibcon#[27=USB\r\n] 2006.147.08:08:25.04#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:25.04#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:08:25.04#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:08:25.04#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:08:25.04$vc4f8/vblo=6,752.99 2006.147.08:08:25.04#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:08:25.04#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:08:25.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:08:25.04#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:25.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:25.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:25.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:08:25.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:25.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:08:25.10#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:08:25.10#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:08:25.10$vc4f8/vb=6,4 2006.147.08:08:25.10#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:08:25.10#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:08:25.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:08:25.10#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:25.16#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:25.16#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:25.18#ibcon#[27=AT06-04\r\n] 2006.147.08:08:25.21#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:25.21#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:08:25.21#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:08:25.21#ibcon#ireg 7 cls_cnt 0 2006.147.08:08:25.21#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:25.33#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:25.33#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:25.35#ibcon#[27=USB\r\n] 2006.147.08:08:25.38#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:25.38#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:08:25.38#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:08:25.38#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:08:25.38$vc4f8/vabw=wide 2006.147.08:08:25.38#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.08:08:25.38#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.08:08:25.38#ibcon#ireg 8 cls_cnt 0 2006.147.08:08:25.38#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:25.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:25.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:25.40#ibcon#[25=BW32\r\n] 2006.147.08:08:25.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:25.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:08:25.43#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:08:25.43#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:08:25.43$vc4f8/vbbw=wide 2006.147.08:08:25.43#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:08:25.43#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:08:25.43#ibcon#ireg 8 cls_cnt 0 2006.147.08:08:25.43#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:08:25.50#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:08:25.50#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:08:25.52#ibcon#[27=BW32\r\n] 2006.147.08:08:25.55#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:08:25.55#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:08:25.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:08:25.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:08:25.55$4f8m12a/ifd4f 2006.147.08:08:25.55$ifd4f/lo= 2006.147.08:08:25.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:08:25.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:08:25.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:08:25.55$ifd4f/patch= 2006.147.08:08:25.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:08:25.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:08:25.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:08:25.55$4f8m12a/"form=m,16.000,1:2 2006.147.08:08:25.55$4f8m12a/"tpicd 2006.147.08:08:25.55$4f8m12a/echo=off 2006.147.08:08:25.55$4f8m12a/xlog=off 2006.147.08:08:25.55:!2006.147.08:09:00 2006.147.08:08:40.14#trakl#Source acquired 2006.147.08:08:41.14#flagr#flagr/antenna,acquired 2006.147.08:09:00.00:preob 2006.147.08:09:00.14/onsource/TRACKING 2006.147.08:09:00.14:!2006.147.08:09:10 2006.147.08:09:10.00:data_valid=on 2006.147.08:09:10.00:midob 2006.147.08:09:11.14/onsource/TRACKING 2006.147.08:09:11.14/wx/19.45,1011.6,91 2006.147.08:09:11.34/cable/+6.5379E-03 2006.147.08:09:12.43/va/01,08,usb,yes,60,63 2006.147.08:09:12.43/va/02,07,usb,yes,60,63 2006.147.08:09:12.43/va/03,08,usb,yes,47,48 2006.147.08:09:12.43/va/04,07,usb,yes,61,66 2006.147.08:09:12.43/va/05,06,usb,yes,70,74 2006.147.08:09:12.43/va/06,05,usb,yes,72,71 2006.147.08:09:12.43/va/07,05,usb,yes,72,71 2006.147.08:09:12.43/va/08,05,usb,yes,76,75 2006.147.08:09:12.66/valo/01,532.99,yes,locked 2006.147.08:09:12.66/valo/02,572.99,yes,locked 2006.147.08:09:12.66/valo/03,672.99,yes,locked 2006.147.08:09:12.66/valo/04,832.99,yes,locked 2006.147.08:09:12.66/valo/05,652.99,yes,locked 2006.147.08:09:12.66/valo/06,772.99,yes,locked 2006.147.08:09:12.66/valo/07,832.99,yes,locked 2006.147.08:09:12.66/valo/08,852.99,yes,locked 2006.147.08:09:13.75/vb/01,04,usb,yes,33,32 2006.147.08:09:13.75/vb/02,04,usb,yes,35,37 2006.147.08:09:13.75/vb/03,04,usb,yes,31,36 2006.147.08:09:13.75/vb/04,04,usb,yes,33,33 2006.147.08:09:13.75/vb/05,03,usb,yes,38,43 2006.147.08:09:13.75/vb/06,04,usb,yes,32,35 2006.147.08:09:13.75/vb/07,04,usb,yes,34,34 2006.147.08:09:13.75/vb/08,03,usb,yes,39,43 2006.147.08:09:13.98/vblo/01,632.99,yes,locked 2006.147.08:09:13.98/vblo/02,640.99,yes,locked 2006.147.08:09:13.98/vblo/03,656.99,yes,locked 2006.147.08:09:13.98/vblo/04,712.99,yes,locked 2006.147.08:09:13.98/vblo/05,744.99,yes,locked 2006.147.08:09:13.98/vblo/06,752.99,yes,locked 2006.147.08:09:13.98/vblo/07,734.99,yes,locked 2006.147.08:09:13.98/vblo/08,744.99,yes,locked 2006.147.08:09:14.13/vabw/8 2006.147.08:09:14.28/vbbw/8 2006.147.08:09:14.37/xfe/off,on,14.5 2006.147.08:09:14.75/ifatt/23,28,28,28 2006.147.08:09:15.08/fmout-gps/S +4.88E-07 2006.147.08:09:15.12:!2006.147.08:10:10 2006.147.08:10:10.00:data_valid=off 2006.147.08:10:10.00:postob 2006.147.08:10:10.09/cable/+6.5394E-03 2006.147.08:10:10.09/wx/19.39,1011.6,91 2006.147.08:10:11.08/fmout-gps/S +4.88E-07 2006.147.08:10:11.08:scan_name=147-0811,k06147,60 2006.147.08:10:11.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.147.08:10:11.14#flagr#flagr/antenna,new-source 2006.147.08:10:12.14:checkk5 2006.147.08:10:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:10:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:10:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:10:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:10:14.04/chk_obsdata//k5ts1/k06147_ts1_147-0809*_20??1470809??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:10:14.42/chk_obsdata//k5ts2/k06147_ts2_147-0809*_20??1470809??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:10:14.79/chk_obsdata//k5ts3/k06147_ts3_147-0809*_20??1470809??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:10:15.18/chk_obsdata//k5ts4/k06147_ts4_147-0809*_20??1470809??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:10:15.87/k5log//k5ts1_log_newline 2006.147.08:10:16.57/k5log//k5ts2_log_newline 2006.147.08:10:17.26/k5log//k5ts3_log_newline 2006.147.08:10:17.95/k5log//k5ts4_log_newline 2006.147.08:10:17.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:10:17.98:4f8m12a=2 2006.147.08:10:17.98$4f8m12a/echo=on 2006.147.08:10:17.98$4f8m12a/pcalon 2006.147.08:10:17.98$pcalon/"no phase cal control is implemented here 2006.147.08:10:17.98$4f8m12a/"tpicd=stop 2006.147.08:10:17.98$4f8m12a/vc4f8 2006.147.08:10:17.98$vc4f8/valo=1,532.99 2006.147.08:10:17.98#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.08:10:17.98#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.08:10:17.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:17.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:17.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:17.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:10:18.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:18.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:18.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:10:18.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:10:18.05$vc4f8/va=1,8 2006.147.08:10:18.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.08:10:18.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.08:10:18.05#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:18.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:18.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:18.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:18.07#ibcon#[25=AT01-08\r\n] 2006.147.08:10:18.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:18.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:18.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.08:10:18.11#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:18.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:18.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:18.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:18.25#ibcon#[25=USB\r\n] 2006.147.08:10:18.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:18.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:18.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:10:18.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:10:18.28$vc4f8/valo=2,572.99 2006.147.08:10:18.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:10:18.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:10:18.28#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:18.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:18.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:18.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:18.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:10:18.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:18.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:18.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:10:18.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:10:18.36$vc4f8/va=2,7 2006.147.08:10:18.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.08:10:18.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.08:10:18.36#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:18.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:18.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:18.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:18.42#ibcon#[25=AT02-07\r\n] 2006.147.08:10:18.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:18.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:18.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.08:10:18.45#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:18.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:18.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:18.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:18.59#ibcon#[25=USB\r\n] 2006.147.08:10:18.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:18.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:18.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:10:18.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:10:18.64$vc4f8/valo=3,672.99 2006.147.08:10:18.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:10:18.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:10:18.64#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:18.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:18.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:18.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:18.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:10:18.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:18.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:18.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:10:18.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:10:18.70$vc4f8/va=3,8 2006.147.08:10:18.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:10:18.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:10:18.70#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:18.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:18.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:18.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:18.78#ibcon#[25=AT03-08\r\n] 2006.147.08:10:18.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:18.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:18.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:10:18.81#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:18.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:18.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:18.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:18.95#ibcon#[25=USB\r\n] 2006.147.08:10:18.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:18.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:18.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:10:18.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:10:18.98$vc4f8/valo=4,832.99 2006.147.08:10:18.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:10:18.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:10:18.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:18.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:18.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:18.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:19.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:10:19.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:19.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:19.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:10:19.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:10:19.04$vc4f8/va=4,7 2006.147.08:10:19.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:10:19.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:10:19.04#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:19.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:19.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:19.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:19.12#ibcon#[25=AT04-07\r\n] 2006.147.08:10:19.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:19.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:19.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:10:19.15#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:19.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:19.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:19.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:19.29#ibcon#[25=USB\r\n] 2006.147.08:10:19.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:19.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:19.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:10:19.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:10:19.32$vc4f8/valo=5,652.99 2006.147.08:10:19.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:10:19.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:10:19.32#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:19.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:19.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:19.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:19.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:10:19.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:19.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:19.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:10:19.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:10:19.38$vc4f8/va=5,6 2006.147.08:10:19.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:10:19.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:10:19.38#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:19.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:19.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:19.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:19.46#ibcon#[25=AT05-06\r\n] 2006.147.08:10:19.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:19.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:19.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:10:19.49#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:19.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:19.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:19.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:19.63#ibcon#[25=USB\r\n] 2006.147.08:10:19.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:19.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:19.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:10:19.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:10:19.66$vc4f8/valo=6,772.99 2006.147.08:10:19.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:10:19.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:10:19.66#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:19.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:19.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:19.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:19.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:10:19.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:19.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:19.72#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:10:19.72#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:10:19.72$vc4f8/va=6,5 2006.147.08:10:19.72#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:10:19.72#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:10:19.72#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:19.72#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:19.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:19.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:19.80#ibcon#[25=AT06-05\r\n] 2006.147.08:10:19.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:19.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:19.83#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:10:19.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:19.83#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:10:19.95#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:10:19.95#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:10:19.97#ibcon#[25=USB\r\n] 2006.147.08:10:20.00#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:10:20.00#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:10:20.00#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:10:20.00#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:10:20.00$vc4f8/valo=7,832.99 2006.147.08:10:20.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:10:20.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:10:20.00#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:20.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:10:20.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:10:20.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:10:20.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:10:20.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:10:20.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:10:20.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:10:20.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:10:20.06$vc4f8/va=7,5 2006.147.08:10:20.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:10:20.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:10:20.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:20.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:10:20.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:10:20.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:10:20.14#ibcon#[25=AT07-05\r\n] 2006.147.08:10:20.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:10:20.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:10:20.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:10:20.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:20.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:10:20.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:10:20.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:10:20.31#ibcon#[25=USB\r\n] 2006.147.08:10:20.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:10:20.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:10:20.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:10:20.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:10:20.34$vc4f8/valo=8,852.99 2006.147.08:10:20.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:10:20.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:10:20.34#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:20.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:10:20.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:10:20.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:10:20.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:10:20.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:10:20.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:10:20.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:10:20.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:10:20.40$vc4f8/va=8,5 2006.147.08:10:20.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.08:10:20.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.08:10:20.40#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:20.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:10:20.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:10:20.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:10:20.48#ibcon#[25=AT08-05\r\n] 2006.147.08:10:20.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:10:20.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:10:20.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.08:10:20.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:20.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:10:20.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:10:20.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:10:20.65#ibcon#[25=USB\r\n] 2006.147.08:10:20.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:10:20.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:10:20.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:10:20.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:10:20.68$vc4f8/vblo=1,632.99 2006.147.08:10:20.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.08:10:20.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.08:10:20.68#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:20.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:10:20.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:10:20.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:10:20.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:10:20.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:10:20.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:10:20.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:10:20.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:10:20.74$vc4f8/vb=1,4 2006.147.08:10:20.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.08:10:20.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.08:10:20.74#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:20.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:10:20.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:10:20.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:10:20.76#ibcon#[27=AT01-04\r\n] 2006.147.08:10:20.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:10:20.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:10:20.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.08:10:20.79#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:20.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:10:20.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:10:20.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:10:20.93#ibcon#[27=USB\r\n] 2006.147.08:10:20.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:10:20.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:10:20.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:10:20.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:10:20.96$vc4f8/vblo=2,640.99 2006.147.08:10:20.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.08:10:20.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.08:10:20.96#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:20.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:20.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:20.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:20.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:10:21.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:21.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:10:21.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:10:21.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:10:21.02$vc4f8/vb=2,4 2006.147.08:10:21.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.08:10:21.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.08:10:21.02#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:21.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:21.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:21.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:21.10#ibcon#[27=AT02-04\r\n] 2006.147.08:10:21.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:21.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:10:21.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.08:10:21.13#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:21.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:21.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:21.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:21.27#ibcon#[27=USB\r\n] 2006.147.08:10:21.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:21.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:10:21.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:10:21.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:10:21.30$vc4f8/vblo=3,656.99 2006.147.08:10:21.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:10:21.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:10:21.30#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:21.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:21.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:21.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:21.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:10:21.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:21.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:10:21.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:10:21.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:10:21.36$vc4f8/vb=3,4 2006.147.08:10:21.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.08:10:21.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.08:10:21.36#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:21.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:21.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:21.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:21.44#ibcon#[27=AT03-04\r\n] 2006.147.08:10:21.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:21.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:10:21.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.08:10:21.47#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:21.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:21.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:21.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:21.61#ibcon#[27=USB\r\n] 2006.147.08:10:21.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:21.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:10:21.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:10:21.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:10:21.64$vc4f8/vblo=4,712.99 2006.147.08:10:21.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:10:21.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:10:21.64#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:21.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:21.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:21.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:21.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:10:21.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:21.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:10:21.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:10:21.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:10:21.70$vc4f8/vb=4,4 2006.147.08:10:21.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:10:21.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:10:21.70#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:21.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:21.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:21.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:21.78#ibcon#[27=AT04-04\r\n] 2006.147.08:10:21.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:21.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:10:21.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:10:21.81#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:21.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:21.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:21.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:21.95#ibcon#[27=USB\r\n] 2006.147.08:10:21.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:21.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:10:21.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:10:21.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:10:21.98$vc4f8/vblo=5,744.99 2006.147.08:10:21.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:10:21.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:10:21.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:21.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:21.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:21.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:22.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:10:22.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:22.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:10:22.06#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:10:22.06#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:10:22.06$vc4f8/vb=5,3 2006.147.08:10:22.06#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:10:22.06#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:10:22.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:22.06#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:22.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:22.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:22.12#ibcon#[27=AT05-03\r\n] 2006.147.08:10:22.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:22.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:10:22.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:10:22.15#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:22.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:22.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:22.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:22.29#ibcon#[27=USB\r\n] 2006.147.08:10:22.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:22.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:10:22.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:10:22.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:10:22.32$vc4f8/vblo=6,752.99 2006.147.08:10:22.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:10:22.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:10:22.32#ibcon#ireg 17 cls_cnt 0 2006.147.08:10:22.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:22.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:22.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:22.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:10:22.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:22.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:10:22.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:10:22.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:10:22.38$vc4f8/vb=6,4 2006.147.08:10:22.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:10:22.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:10:22.38#ibcon#ireg 11 cls_cnt 2 2006.147.08:10:22.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:22.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:22.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:22.46#ibcon#[27=AT06-04\r\n] 2006.147.08:10:22.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:22.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:10:22.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:10:22.49#ibcon#ireg 7 cls_cnt 0 2006.147.08:10:22.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:22.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:22.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:22.63#ibcon#[27=USB\r\n] 2006.147.08:10:22.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:22.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:10:22.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:10:22.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:10:22.66$vc4f8/vabw=wide 2006.147.08:10:22.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:10:22.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:10:22.66#ibcon#ireg 8 cls_cnt 0 2006.147.08:10:22.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:22.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:22.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:22.68#ibcon#[25=BW32\r\n] 2006.147.08:10:22.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:22.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:10:22.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:10:22.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:10:22.71$vc4f8/vbbw=wide 2006.147.08:10:22.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:10:22.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:10:22.71#ibcon#ireg 8 cls_cnt 0 2006.147.08:10:22.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:10:22.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:10:22.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:10:22.80#ibcon#[27=BW32\r\n] 2006.147.08:10:22.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:10:22.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:10:22.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:10:22.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:10:22.83$4f8m12a/ifd4f 2006.147.08:10:22.83$ifd4f/lo= 2006.147.08:10:22.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:10:22.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:10:22.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:10:22.83$ifd4f/patch= 2006.147.08:10:22.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:10:22.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:10:22.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:10:22.83$4f8m12a/"form=m,16.000,1:2 2006.147.08:10:22.83$4f8m12a/"tpicd 2006.147.08:10:22.83$4f8m12a/echo=off 2006.147.08:10:22.83$4f8m12a/xlog=off 2006.147.08:10:22.83:!2006.147.08:11:10 2006.147.08:10:48.14#trakl#Source acquired 2006.147.08:10:50.14#flagr#flagr/antenna,acquired 2006.147.08:11:10.00:preob 2006.147.08:11:10.14/onsource/TRACKING 2006.147.08:11:10.14:!2006.147.08:11:20 2006.147.08:11:20.00:data_valid=on 2006.147.08:11:20.00:midob 2006.147.08:11:20.14/onsource/TRACKING 2006.147.08:11:20.14/wx/19.31,1011.6,93 2006.147.08:11:20.29/cable/+6.5358E-03 2006.147.08:11:21.38/va/01,08,usb,yes,52,55 2006.147.08:11:21.38/va/02,07,usb,yes,53,55 2006.147.08:11:21.38/va/03,08,usb,yes,41,41 2006.147.08:11:21.38/va/04,07,usb,yes,54,58 2006.147.08:11:21.38/va/05,06,usb,yes,61,65 2006.147.08:11:21.38/va/06,05,usb,yes,63,62 2006.147.08:11:21.38/va/07,05,usb,yes,62,62 2006.147.08:11:21.38/va/08,05,usb,yes,66,65 2006.147.08:11:21.61/valo/01,532.99,yes,locked 2006.147.08:11:21.61/valo/02,572.99,yes,locked 2006.147.08:11:21.61/valo/03,672.99,yes,locked 2006.147.08:11:21.61/valo/04,832.99,yes,locked 2006.147.08:11:21.61/valo/05,652.99,yes,locked 2006.147.08:11:21.61/valo/06,772.99,yes,locked 2006.147.08:11:21.61/valo/07,832.99,yes,locked 2006.147.08:11:21.61/valo/08,852.99,yes,locked 2006.147.08:11:22.70/vb/01,04,usb,yes,33,31 2006.147.08:11:22.70/vb/02,04,usb,yes,35,36 2006.147.08:11:22.70/vb/03,04,usb,yes,31,35 2006.147.08:11:22.70/vb/04,04,usb,yes,32,32 2006.147.08:11:22.70/vb/05,03,usb,yes,38,43 2006.147.08:11:22.70/vb/06,04,usb,yes,31,34 2006.147.08:11:22.70/vb/07,04,usb,yes,33,33 2006.147.08:11:22.70/vb/08,03,usb,yes,38,42 2006.147.08:11:22.93/vblo/01,632.99,yes,locked 2006.147.08:11:22.93/vblo/02,640.99,yes,locked 2006.147.08:11:22.93/vblo/03,656.99,yes,locked 2006.147.08:11:22.93/vblo/04,712.99,yes,locked 2006.147.08:11:22.93/vblo/05,744.99,yes,locked 2006.147.08:11:22.93/vblo/06,752.99,yes,locked 2006.147.08:11:22.93/vblo/07,734.99,yes,locked 2006.147.08:11:22.93/vblo/08,744.99,yes,locked 2006.147.08:11:23.08/vabw/8 2006.147.08:11:23.23/vbbw/8 2006.147.08:11:23.34/xfe/off,on,13.7 2006.147.08:11:23.71/ifatt/23,28,28,28 2006.147.08:11:24.08/fmout-gps/S +4.88E-07 2006.147.08:11:24.16:!2006.147.08:12:20 2006.147.08:12:20.02:data_valid=off 2006.147.08:12:20.02:postob 2006.147.08:12:20.12/cable/+6.5379E-03 2006.147.08:12:20.12/wx/19.24,1011.6,93 2006.147.08:12:21.08/fmout-gps/S +4.87E-07 2006.147.08:12:21.08:scan_name=147-0815,k06147,60 2006.147.08:12:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.147.08:12:21.15#flagr#flagr/antenna,new-source 2006.147.08:12:22.14:checkk5 2006.147.08:12:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:12:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:12:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:12:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:12:24.03/chk_obsdata//k5ts1/k06147_ts1_147-0811*_20??1470811??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:12:24.41/chk_obsdata//k5ts2/k06147_ts2_147-0811*_20??1470811??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:12:24.79/chk_obsdata//k5ts3/k06147_ts3_147-0811*_20??1470811??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:12:25.17/chk_obsdata//k5ts4/k06147_ts4_147-0811*_20??1470811??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:12:25.87/k5log//k5ts1_log_newline 2006.147.08:12:26.57/k5log//k5ts2_log_newline 2006.147.08:12:27.26/k5log//k5ts3_log_newline 2006.147.08:12:27.95/k5log//k5ts4_log_newline 2006.147.08:12:27.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:12:27.98:4f8m12a=2 2006.147.08:12:27.98$4f8m12a/echo=on 2006.147.08:12:27.98$4f8m12a/pcalon 2006.147.08:12:27.98$pcalon/"no phase cal control is implemented here 2006.147.08:12:27.98$4f8m12a/"tpicd=stop 2006.147.08:12:27.98$4f8m12a/vc4f8 2006.147.08:12:27.98$vc4f8/valo=1,532.99 2006.147.08:12:27.98#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:12:27.98#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:12:27.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:27.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:27.98#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:27.98#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:27.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:12:28.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:28.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:28.04#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:12:28.04#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:12:28.05$vc4f8/va=1,8 2006.147.08:12:28.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:12:28.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:12:28.05#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:28.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:28.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:28.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:28.06#ibcon#[25=AT01-08\r\n] 2006.147.08:12:28.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:28.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:28.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:12:28.11#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:28.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:28.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:28.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:28.24#ibcon#[25=USB\r\n] 2006.147.08:12:28.27#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:28.27#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:28.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:12:28.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:12:28.28$vc4f8/valo=2,572.99 2006.147.08:12:28.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:12:28.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:12:28.28#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:28.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:28.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:28.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:28.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:12:28.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:28.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:28.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:12:28.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:12:28.36$vc4f8/va=2,7 2006.147.08:12:28.36#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:12:28.36#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:12:28.36#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:28.36#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:28.39#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:28.39#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:28.40#ibcon#[25=AT02-07\r\n] 2006.147.08:12:28.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:28.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:28.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:12:28.44#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:28.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:28.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:28.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:28.57#ibcon#[25=USB\r\n] 2006.147.08:12:28.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:28.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:28.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:12:28.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:12:28.61$vc4f8/valo=3,672.99 2006.147.08:12:28.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:12:28.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:12:28.61#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:28.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:28.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:28.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:28.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:12:28.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:28.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:28.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:12:28.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:12:28.69$vc4f8/va=3,8 2006.147.08:12:28.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:12:28.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:12:28.69#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:28.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:28.72#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:28.72#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:28.74#ibcon#[25=AT03-08\r\n] 2006.147.08:12:28.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:28.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:28.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:12:28.76#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:28.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:28.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:28.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:28.90#ibcon#[25=USB\r\n] 2006.147.08:12:28.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:28.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:28.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:12:28.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:12:28.94$vc4f8/valo=4,832.99 2006.147.08:12:28.94#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:12:28.94#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:12:28.94#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:28.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:28.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:28.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:28.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:12:28.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:28.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:28.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:12:29.00#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:12:29.00$vc4f8/va=4,7 2006.147.08:12:29.00#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:12:29.00#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:12:29.00#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:29.00#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:29.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:29.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:29.06#ibcon#[25=AT04-07\r\n] 2006.147.08:12:29.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:29.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:29.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:12:29.09#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:29.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:29.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:29.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:29.23#ibcon#[25=USB\r\n] 2006.147.08:12:29.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:29.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:29.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:12:29.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:12:29.27$vc4f8/valo=5,652.99 2006.147.08:12:29.27#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:12:29.27#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:12:29.27#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:29.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:29.27#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:29.27#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:12:29.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:29.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:29.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:12:29.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:12:29.33$vc4f8/va=5,6 2006.147.08:12:29.33#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:12:29.33#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:12:29.33#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:29.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:29.37#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:29.37#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:29.39#ibcon#[25=AT05-06\r\n] 2006.147.08:12:29.42#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:29.42#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:29.42#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:12:29.42#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:29.42#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:29.54#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:29.54#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:29.56#ibcon#[25=USB\r\n] 2006.147.08:12:29.59#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:29.59#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:29.59#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:12:29.59#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:12:29.60$vc4f8/valo=6,772.99 2006.147.08:12:29.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:12:29.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:12:29.60#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:29.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:29.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:29.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:12:29.65#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:29.65#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:29.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:12:29.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:12:29.66$vc4f8/va=6,5 2006.147.08:12:29.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.08:12:29.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.08:12:29.66#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:29.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:29.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:29.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:29.72#ibcon#[25=AT06-05\r\n] 2006.147.08:12:29.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:29.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:29.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.08:12:29.75#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:29.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:12:29.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:12:29.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:12:29.89#ibcon#[25=USB\r\n] 2006.147.08:12:29.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:12:29.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:12:29.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:12:29.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:12:29.93$vc4f8/valo=7,832.99 2006.147.08:12:29.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.08:12:29.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.08:12:29.93#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:29.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:12:29.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:12:29.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:12:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:12:29.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:12:29.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:12:29.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:12:29.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:12:29.99$vc4f8/va=7,5 2006.147.08:12:29.99#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.08:12:29.99#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.08:12:29.99#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:29.99#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:12:30.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:12:30.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:12:30.05#ibcon#[25=AT07-05\r\n] 2006.147.08:12:30.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:12:30.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:12:30.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.08:12:30.08#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:30.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:12:30.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:12:30.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:12:30.22#ibcon#[25=USB\r\n] 2006.147.08:12:30.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:12:30.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:12:30.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:12:30.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:12:30.26$vc4f8/valo=8,852.99 2006.147.08:12:30.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.08:12:30.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.08:12:30.26#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:30.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:12:30.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:12:30.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:12:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:12:30.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:12:30.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:12:30.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:12:30.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:12:30.32$vc4f8/va=8,5 2006.147.08:12:30.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.08:12:30.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.08:12:30.32#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:30.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:12:30.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:12:30.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:12:30.38#ibcon#[25=AT08-05\r\n] 2006.147.08:12:30.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:12:30.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:12:30.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.08:12:30.41#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:30.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:12:30.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:12:30.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:12:30.55#ibcon#[25=USB\r\n] 2006.147.08:12:30.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:12:30.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:12:30.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:12:30.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:12:30.59$vc4f8/vblo=1,632.99 2006.147.08:12:30.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.08:12:30.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.08:12:30.59#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:30.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:12:30.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:12:30.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:12:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:12:30.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:12:30.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:12:30.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:12:30.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:12:30.65$vc4f8/vb=1,4 2006.147.08:12:30.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.08:12:30.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.08:12:30.65#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:30.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:12:30.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:12:30.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:12:30.66#ibcon#[27=AT01-04\r\n] 2006.147.08:12:30.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:12:30.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:12:30.69#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.08:12:30.69#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:30.69#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:12:30.81#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:12:30.81#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:12:30.83#ibcon#[27=USB\r\n] 2006.147.08:12:30.86#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:12:30.86#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:12:30.86#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:12:30.86#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:12:30.87$vc4f8/vblo=2,640.99 2006.147.08:12:30.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:12:30.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:12:30.87#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:30.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:30.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:30.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:12:30.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:30.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:12:30.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:12:30.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:12:30.93$vc4f8/vb=2,4 2006.147.08:12:30.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:12:30.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:12:30.93#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:30.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:30.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:30.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:30.99#ibcon#[27=AT02-04\r\n] 2006.147.08:12:31.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:31.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:12:31.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:12:31.03#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:31.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:31.14#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:31.14#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:31.16#ibcon#[27=USB\r\n] 2006.147.08:12:31.19#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:31.19#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:12:31.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:12:31.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:12:31.20$vc4f8/vblo=3,656.99 2006.147.08:12:31.20#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:12:31.20#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:12:31.20#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:31.20#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:31.20#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:31.20#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:31.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:12:31.25#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:31.25#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:12:31.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:12:31.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:12:31.26$vc4f8/vb=3,4 2006.147.08:12:31.26#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:12:31.26#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:12:31.26#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:31.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:31.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:31.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:31.32#ibcon#[27=AT03-04\r\n] 2006.147.08:12:31.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:31.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:12:31.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:12:31.35#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:31.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:31.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:31.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:31.49#ibcon#[27=USB\r\n] 2006.147.08:12:31.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:31.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:12:31.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:12:31.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:12:31.53$vc4f8/vblo=4,712.99 2006.147.08:12:31.53#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:12:31.53#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:12:31.53#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:31.53#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:31.53#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:31.53#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:31.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:12:31.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:31.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:12:31.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:12:31.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:12:31.59$vc4f8/vb=4,4 2006.147.08:12:31.59#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:12:31.59#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:12:31.59#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:31.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:31.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:31.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:31.65#ibcon#[27=AT04-04\r\n] 2006.147.08:12:31.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:31.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:12:31.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:12:31.68#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:31.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:31.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:31.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:31.82#ibcon#[27=USB\r\n] 2006.147.08:12:31.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:31.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:12:31.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:12:31.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:12:31.86$vc4f8/vblo=5,744.99 2006.147.08:12:31.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:12:31.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:12:31.86#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:31.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:31.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:31.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:31.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:12:31.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:31.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:12:31.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:12:31.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:12:31.92$vc4f8/vb=5,3 2006.147.08:12:31.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:12:31.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:12:31.92#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:31.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:31.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:31.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:31.98#ibcon#[27=AT05-03\r\n] 2006.147.08:12:32.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:32.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:12:32.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:12:32.01#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:32.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:32.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:32.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:32.15#ibcon#[27=USB\r\n] 2006.147.08:12:32.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:32.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:12:32.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:12:32.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:12:32.19$vc4f8/vblo=6,752.99 2006.147.08:12:32.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:12:32.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:12:32.19#ibcon#ireg 17 cls_cnt 0 2006.147.08:12:32.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:32.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:32.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:32.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:12:32.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:32.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:12:32.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:12:32.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:12:32.25$vc4f8/vb=6,4 2006.147.08:12:32.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:12:32.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:12:32.25#ibcon#ireg 11 cls_cnt 2 2006.147.08:12:32.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:32.29#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:32.29#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:32.31#ibcon#[27=AT06-04\r\n] 2006.147.08:12:32.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:32.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:12:32.34#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:12:32.34#ibcon#ireg 7 cls_cnt 0 2006.147.08:12:32.34#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:32.46#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:32.46#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:32.48#ibcon#[27=USB\r\n] 2006.147.08:12:32.51#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:32.51#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:12:32.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:12:32.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:12:32.52$vc4f8/vabw=wide 2006.147.08:12:32.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:12:32.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:12:32.52#ibcon#ireg 8 cls_cnt 0 2006.147.08:12:32.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:32.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:32.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:32.53#ibcon#[25=BW32\r\n] 2006.147.08:12:32.57#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:32.57#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:12:32.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:12:32.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:12:32.57$vc4f8/vbbw=wide 2006.147.08:12:32.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:12:32.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:12:32.57#ibcon#ireg 8 cls_cnt 0 2006.147.08:12:32.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:12:32.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:12:32.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:12:32.64#ibcon#[27=BW32\r\n] 2006.147.08:12:32.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:12:32.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:12:32.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:12:32.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:12:32.68$4f8m12a/ifd4f 2006.147.08:12:32.68$ifd4f/lo= 2006.147.08:12:32.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:12:32.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:12:32.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:12:32.68$ifd4f/patch= 2006.147.08:12:32.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:12:32.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:12:32.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:12:32.68$4f8m12a/"form=m,16.000,1:2 2006.147.08:12:32.68$4f8m12a/"tpicd 2006.147.08:12:32.68$4f8m12a/echo=off 2006.147.08:12:32.68$4f8m12a/xlog=off 2006.147.08:12:32.68:!2006.147.08:15:10 2006.147.08:12:45.14#trakl#Source acquired 2006.147.08:12:45.15#flagr#flagr/antenna,acquired 2006.147.08:15:10.01:preob 2006.147.08:15:11.13/onsource/TRACKING 2006.147.08:15:11.13:!2006.147.08:15:20 2006.147.08:15:20.01:data_valid=on 2006.147.08:15:20.02:midob 2006.147.08:15:21.13/onsource/TRACKING 2006.147.08:15:21.14/wx/19.02,1011.5,94 2006.147.08:15:21.24/cable/+6.5379E-03 2006.147.08:15:22.33/va/01,08,usb,yes,40,42 2006.147.08:15:22.33/va/02,07,usb,yes,40,42 2006.147.08:15:22.33/va/03,08,usb,yes,31,31 2006.147.08:15:22.33/va/04,07,usb,yes,41,44 2006.147.08:15:22.33/va/05,06,usb,yes,47,50 2006.147.08:15:22.33/va/06,05,usb,yes,48,47 2006.147.08:15:22.33/va/07,05,usb,yes,48,47 2006.147.08:15:22.33/va/08,05,usb,yes,51,50 2006.147.08:15:22.56/valo/01,532.99,yes,locked 2006.147.08:15:22.56/valo/02,572.99,yes,locked 2006.147.08:15:22.56/valo/03,672.99,yes,locked 2006.147.08:15:22.56/valo/04,832.99,yes,locked 2006.147.08:15:22.56/valo/05,652.99,yes,locked 2006.147.08:15:22.56/valo/06,772.99,yes,locked 2006.147.08:15:22.56/valo/07,832.99,yes,locked 2006.147.08:15:22.56/valo/08,852.99,yes,locked 2006.147.08:15:23.65/vb/01,04,usb,yes,29,28 2006.147.08:15:23.65/vb/02,04,usb,yes,31,32 2006.147.08:15:23.65/vb/03,04,usb,yes,27,31 2006.147.08:15:23.65/vb/04,04,usb,yes,28,28 2006.147.08:15:23.65/vb/05,03,usb,yes,33,37 2006.147.08:15:23.65/vb/06,04,usb,yes,27,30 2006.147.08:15:23.65/vb/07,04,usb,yes,29,29 2006.147.08:15:23.65/vb/08,03,usb,yes,33,37 2006.147.08:15:23.89/vblo/01,632.99,yes,locked 2006.147.08:15:23.89/vblo/02,640.99,yes,locked 2006.147.08:15:23.89/vblo/03,656.99,yes,locked 2006.147.08:15:23.89/vblo/04,712.99,yes,locked 2006.147.08:15:23.89/vblo/05,744.99,yes,locked 2006.147.08:15:23.89/vblo/06,752.99,yes,locked 2006.147.08:15:23.89/vblo/07,734.99,yes,locked 2006.147.08:15:23.89/vblo/08,744.99,yes,locked 2006.147.08:15:24.04/vabw/8 2006.147.08:15:24.19/vbbw/8 2006.147.08:15:24.28/xfe/off,on,15.0 2006.147.08:15:24.66/ifatt/23,28,28,28 2006.147.08:15:25.07/fmout-gps/S +4.85E-07 2006.147.08:15:25.16:!2006.147.08:16:20 2006.147.08:16:20.01:data_valid=off 2006.147.08:16:20.02:postob 2006.147.08:16:20.17/cable/+6.5381E-03 2006.147.08:16:20.18/wx/18.96,1011.5,93 2006.147.08:16:21.07/fmout-gps/S +4.84E-07 2006.147.08:16:21.08:scan_name=147-0817,k06147,60 2006.147.08:16:21.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.147.08:16:22.14#flagr#flagr/antenna,new-source 2006.147.08:16:22.15:checkk5 2006.147.08:16:22.54/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:16:22.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:16:23.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:16:23.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:16:24.06/chk_obsdata//k5ts1/k06147_ts1_147-0815*_20??1470815??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:16:24.44/chk_obsdata//k5ts2/k06147_ts2_147-0815*_20??1470815??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:16:24.82/chk_obsdata//k5ts3/k06147_ts3_147-0815*_20??1470815??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:16:25.21/chk_obsdata//k5ts4/k06147_ts4_147-0815*_20??1470815??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:16:25.90/k5log//k5ts1_log_newline 2006.147.08:16:26.60/k5log//k5ts2_log_newline 2006.147.08:16:27.29/k5log//k5ts3_log_newline 2006.147.08:16:27.98/k5log//k5ts4_log_newline 2006.147.08:16:28.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:16:28.01:4f8m12a=2 2006.147.08:16:28.01$4f8m12a/echo=on 2006.147.08:16:28.01$4f8m12a/pcalon 2006.147.08:16:28.01$pcalon/"no phase cal control is implemented here 2006.147.08:16:28.01$4f8m12a/"tpicd=stop 2006.147.08:16:28.01$4f8m12a/vc4f8 2006.147.08:16:28.01$vc4f8/valo=1,532.99 2006.147.08:16:28.02#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:16:28.02#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:16:28.02#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:28.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:28.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:28.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:28.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:16:28.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:28.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:28.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:16:28.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:16:28.11$vc4f8/va=1,8 2006.147.08:16:28.11#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.08:16:28.11#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.08:16:28.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:28.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:28.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:28.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:28.15#ibcon#[25=AT01-08\r\n] 2006.147.08:16:28.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:28.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:28.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.08:16:28.18#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:28.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:28.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:28.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:28.32#ibcon#[25=USB\r\n] 2006.147.08:16:28.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:28.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:28.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:16:28.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:16:28.35$vc4f8/valo=2,572.99 2006.147.08:16:28.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.08:16:28.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.08:16:28.35#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:28.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:28.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:28.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:28.40#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:16:28.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:28.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:28.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:16:28.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:16:28.43$vc4f8/va=2,7 2006.147.08:16:28.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.08:16:28.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.08:16:28.43#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:28.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:28.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:28.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:28.50#ibcon#[25=AT02-07\r\n] 2006.147.08:16:28.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:28.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:28.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.08:16:28.52#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:28.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:28.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:28.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:28.66#ibcon#[25=USB\r\n] 2006.147.08:16:28.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:28.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:28.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:16:28.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:16:28.69$vc4f8/valo=3,672.99 2006.147.08:16:28.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:16:28.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:16:28.69#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:28.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:28.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:28.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:28.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:16:28.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:28.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:28.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:16:28.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:16:28.77$vc4f8/va=3,8 2006.147.08:16:28.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.08:16:28.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.08:16:28.77#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:28.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:28.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:28.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:28.83#ibcon#[25=AT03-08\r\n] 2006.147.08:16:28.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:28.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:28.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.08:16:28.86#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:28.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:28.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:28.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:29.00#ibcon#[25=USB\r\n] 2006.147.08:16:29.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:29.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:29.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:16:29.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:16:29.03$vc4f8/valo=4,832.99 2006.147.08:16:29.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.08:16:29.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.08:16:29.03#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:29.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:29.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:29.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:29.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:16:29.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:29.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:29.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:16:29.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:16:29.09$vc4f8/va=4,7 2006.147.08:16:29.09#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.08:16:29.09#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.08:16:29.09#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:29.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:29.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:29.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:29.17#ibcon#[25=AT04-07\r\n] 2006.147.08:16:29.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:29.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:29.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.08:16:29.20#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:29.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:29.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:29.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:29.34#ibcon#[25=USB\r\n] 2006.147.08:16:29.36#abcon#<5=/06 3.5 8.0 18.95 931011.5\r\n> 2006.147.08:16:29.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:29.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:29.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:16:29.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:16:29.37$vc4f8/valo=5,652.99 2006.147.08:16:29.37#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.08:16:29.37#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.08:16:29.37#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:29.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:16:29.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:16:29.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:16:29.38#abcon#{5=INTERFACE CLEAR} 2006.147.08:16:29.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:16:29.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:16:29.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:16:29.43#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:16:29.43#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:16:29.43$vc4f8/va=5,6 2006.147.08:16:29.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.08:16:29.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.08:16:29.43#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:29.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:29.44#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:16:29.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:29.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:29.51#ibcon#[25=AT05-06\r\n] 2006.147.08:16:29.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:29.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:29.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.08:16:29.54#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:29.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:29.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:29.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:29.68#ibcon#[25=USB\r\n] 2006.147.08:16:29.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:29.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:29.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:16:29.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:16:29.71$vc4f8/valo=6,772.99 2006.147.08:16:29.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.08:16:29.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.08:16:29.71#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:29.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:29.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:29.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:29.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:16:29.77#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:29.77#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:29.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:16:29.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:16:29.77$vc4f8/va=6,5 2006.147.08:16:29.77#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.08:16:29.77#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.08:16:29.77#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:29.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:29.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:29.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:29.85#ibcon#[25=AT06-05\r\n] 2006.147.08:16:29.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:29.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:29.88#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.08:16:29.88#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:29.88#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:16:30.00#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:16:30.00#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:16:30.02#ibcon#[25=USB\r\n] 2006.147.08:16:30.05#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:16:30.05#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:16:30.05#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:16:30.05#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:16:30.05$vc4f8/valo=7,832.99 2006.147.08:16:30.05#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.08:16:30.05#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.08:16:30.05#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:30.05#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:16:30.05#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:16:30.05#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:16:30.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:16:30.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:16:30.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:16:30.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:16:30.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:16:30.11$vc4f8/va=7,5 2006.147.08:16:30.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.08:16:30.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.08:16:30.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:30.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:16:30.17#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:16:30.17#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:16:30.19#ibcon#[25=AT07-05\r\n] 2006.147.08:16:30.22#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:16:30.22#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:16:30.22#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.08:16:30.22#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:30.22#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:16:30.34#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:16:30.34#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:16:30.36#ibcon#[25=USB\r\n] 2006.147.08:16:30.39#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:16:30.39#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:16:30.39#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:16:30.39#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:16:30.39$vc4f8/valo=8,852.99 2006.147.08:16:30.39#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.08:16:30.39#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.08:16:30.39#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:30.39#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:16:30.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:16:30.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:16:30.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:16:30.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:16:30.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:16:30.45#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:16:30.45#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:16:30.45$vc4f8/va=8,5 2006.147.08:16:30.45#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.08:16:30.45#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.08:16:30.45#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:30.45#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:16:30.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:16:30.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:16:30.53#ibcon#[25=AT08-05\r\n] 2006.147.08:16:30.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:16:30.56#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:16:30.56#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.08:16:30.56#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:30.56#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:16:30.68#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:16:30.68#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:16:30.70#ibcon#[25=USB\r\n] 2006.147.08:16:30.73#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:16:30.73#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:16:30.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:16:30.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:16:30.73$vc4f8/vblo=1,632.99 2006.147.08:16:30.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:16:30.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:16:30.73#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:30.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:30.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:30.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:30.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:16:30.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:30.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:16:30.79#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:16:30.79#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:16:30.79$vc4f8/vb=1,4 2006.147.08:16:30.79#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.08:16:30.79#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.08:16:30.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:30.79#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:30.79#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:30.79#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:30.81#ibcon#[27=AT01-04\r\n] 2006.147.08:16:30.84#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:30.84#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:16:30.84#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.08:16:30.84#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:30.84#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:30.96#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:30.96#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:30.98#ibcon#[27=USB\r\n] 2006.147.08:16:31.01#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:31.01#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:16:31.01#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:16:31.01#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:16:31.01$vc4f8/vblo=2,640.99 2006.147.08:16:31.01#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.08:16:31.01#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.08:16:31.01#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:31.01#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:31.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:31.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:31.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:16:31.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:31.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:16:31.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:16:31.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:16:31.07$vc4f8/vb=2,4 2006.147.08:16:31.07#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.08:16:31.07#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.08:16:31.07#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:31.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:31.13#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:31.13#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:31.15#ibcon#[27=AT02-04\r\n] 2006.147.08:16:31.18#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:31.18#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:16:31.18#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.08:16:31.18#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:31.18#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:31.30#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:31.30#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:31.32#ibcon#[27=USB\r\n] 2006.147.08:16:31.35#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:31.35#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:16:31.35#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:16:31.35#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:16:31.35$vc4f8/vblo=3,656.99 2006.147.08:16:31.35#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:16:31.35#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:16:31.35#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:31.35#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:31.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:31.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:31.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:16:31.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:31.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:16:31.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:16:31.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:16:31.41$vc4f8/vb=3,4 2006.147.08:16:31.41#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.08:16:31.41#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.08:16:31.41#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:31.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:31.47#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:31.47#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:31.49#ibcon#[27=AT03-04\r\n] 2006.147.08:16:31.52#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:31.52#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:16:31.52#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.08:16:31.52#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:31.52#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:31.64#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:31.64#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:31.66#ibcon#[27=USB\r\n] 2006.147.08:16:31.69#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:31.69#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:16:31.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:16:31.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:16:31.69$vc4f8/vblo=4,712.99 2006.147.08:16:31.69#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.08:16:31.69#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.08:16:31.69#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:31.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:31.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:31.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:31.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:16:31.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:31.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:16:31.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:16:31.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:16:31.75$vc4f8/vb=4,4 2006.147.08:16:31.75#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.08:16:31.75#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.08:16:31.75#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:31.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:31.81#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:31.81#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:31.83#ibcon#[27=AT04-04\r\n] 2006.147.08:16:31.86#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:31.86#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:16:31.86#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.08:16:31.86#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:31.86#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:31.98#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:31.98#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:32.00#ibcon#[27=USB\r\n] 2006.147.08:16:32.03#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:32.03#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:16:32.03#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:16:32.03#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:16:32.03$vc4f8/vblo=5,744.99 2006.147.08:16:32.03#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:16:32.03#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:16:32.03#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:32.03#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:16:32.03#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:16:32.03#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:16:32.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:16:32.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:16:32.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:16:32.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:16:32.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:16:32.09$vc4f8/vb=5,3 2006.147.08:16:32.09#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.08:16:32.09#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.08:16:32.09#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:32.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:16:32.15#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:16:32.15#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:16:32.17#ibcon#[27=AT05-03\r\n] 2006.147.08:16:32.20#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:16:32.20#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:16:32.20#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.08:16:32.20#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:32.20#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:16:32.32#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:16:32.32#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:16:32.34#ibcon#[27=USB\r\n] 2006.147.08:16:32.37#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:16:32.37#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:16:32.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:16:32.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:16:32.37$vc4f8/vblo=6,752.99 2006.147.08:16:32.37#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.08:16:32.37#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.08:16:32.37#ibcon#ireg 17 cls_cnt 0 2006.147.08:16:32.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:16:32.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:16:32.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:16:32.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:16:32.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:16:32.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:16:32.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:16:32.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:16:32.43$vc4f8/vb=6,4 2006.147.08:16:32.43#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.08:16:32.43#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.08:16:32.43#ibcon#ireg 11 cls_cnt 2 2006.147.08:16:32.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:32.49#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:32.49#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:32.51#ibcon#[27=AT06-04\r\n] 2006.147.08:16:32.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:32.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:16:32.54#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.08:16:32.54#ibcon#ireg 7 cls_cnt 0 2006.147.08:16:32.54#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:32.66#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:32.66#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:32.68#ibcon#[27=USB\r\n] 2006.147.08:16:32.71#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:32.71#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:16:32.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:16:32.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:16:32.71$vc4f8/vabw=wide 2006.147.08:16:32.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.08:16:32.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.08:16:32.71#ibcon#ireg 8 cls_cnt 0 2006.147.08:16:32.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:32.71#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:32.71#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:32.73#ibcon#[25=BW32\r\n] 2006.147.08:16:32.76#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:32.76#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:16:32.76#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:16:32.76#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:16:32.76$vc4f8/vbbw=wide 2006.147.08:16:32.76#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:16:32.76#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:16:32.76#ibcon#ireg 8 cls_cnt 0 2006.147.08:16:32.76#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:16:32.83#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:16:32.83#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:16:32.86#ibcon#[27=BW32\r\n] 2006.147.08:16:32.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:16:32.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:16:32.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:16:32.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:16:32.88$4f8m12a/ifd4f 2006.147.08:16:32.88$ifd4f/lo= 2006.147.08:16:32.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:16:32.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:16:32.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:16:32.89$ifd4f/patch= 2006.147.08:16:32.89$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:16:32.89$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:16:32.89$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:16:32.89$4f8m12a/"form=m,16.000,1:2 2006.147.08:16:32.89$4f8m12a/"tpicd 2006.147.08:16:32.89$4f8m12a/echo=off 2006.147.08:16:32.89$4f8m12a/xlog=off 2006.147.08:16:32.89:!2006.147.08:17:00 2006.147.08:16:40.14#trakl#Source acquired 2006.147.08:16:42.14#flagr#flagr/antenna,acquired 2006.147.08:17:00.01:preob 2006.147.08:17:01.14/onsource/TRACKING 2006.147.08:17:01.14:!2006.147.08:17:10 2006.147.08:17:10.00:data_valid=on 2006.147.08:17:10.00:midob 2006.147.08:17:10.14/onsource/TRACKING 2006.147.08:17:10.14/wx/18.90,1011.4,93 2006.147.08:17:10.36/cable/+6.5399E-03 2006.147.08:17:11.45/va/01,08,usb,yes,39,41 2006.147.08:17:11.45/va/02,07,usb,yes,40,41 2006.147.08:17:11.45/va/03,08,usb,yes,30,31 2006.147.08:17:11.45/va/04,07,usb,yes,41,44 2006.147.08:17:11.45/va/05,06,usb,yes,46,49 2006.147.08:17:11.45/va/06,05,usb,yes,47,46 2006.147.08:17:11.45/va/07,05,usb,yes,47,46 2006.147.08:17:11.45/va/08,05,usb,yes,50,49 2006.147.08:17:11.68/valo/01,532.99,yes,locked 2006.147.08:17:11.68/valo/02,572.99,yes,locked 2006.147.08:17:11.68/valo/03,672.99,yes,locked 2006.147.08:17:11.68/valo/04,832.99,yes,locked 2006.147.08:17:11.68/valo/05,652.99,yes,locked 2006.147.08:17:11.68/valo/06,772.99,yes,locked 2006.147.08:17:11.68/valo/07,832.99,yes,locked 2006.147.08:17:11.68/valo/08,852.99,yes,locked 2006.147.08:17:12.77/vb/01,04,usb,yes,30,28 2006.147.08:17:12.77/vb/02,04,usb,yes,31,33 2006.147.08:17:12.77/vb/03,04,usb,yes,28,31 2006.147.08:17:12.77/vb/04,04,usb,yes,29,29 2006.147.08:17:12.77/vb/05,03,usb,yes,34,38 2006.147.08:17:12.77/vb/06,04,usb,yes,28,31 2006.147.08:17:12.77/vb/07,04,usb,yes,30,30 2006.147.08:17:12.77/vb/08,03,usb,yes,35,38 2006.147.08:17:13.00/vblo/01,632.99,yes,locked 2006.147.08:17:13.00/vblo/02,640.99,yes,locked 2006.147.08:17:13.00/vblo/03,656.99,yes,locked 2006.147.08:17:13.00/vblo/04,712.99,yes,locked 2006.147.08:17:13.00/vblo/05,744.99,yes,locked 2006.147.08:17:13.00/vblo/06,752.99,yes,locked 2006.147.08:17:13.00/vblo/07,734.99,yes,locked 2006.147.08:17:13.00/vblo/08,744.99,yes,locked 2006.147.08:17:13.15/vabw/8 2006.147.08:17:13.30/vbbw/8 2006.147.08:17:13.39/xfe/off,on,15.5 2006.147.08:17:13.77/ifatt/23,28,28,28 2006.147.08:17:14.07/fmout-gps/S +4.85E-07 2006.147.08:17:14.12:!2006.147.08:18:10 2006.147.08:18:10.01:data_valid=off 2006.147.08:18:10.02:postob 2006.147.08:18:10.20/cable/+6.5389E-03 2006.147.08:18:10.21/wx/18.85,1011.4,93 2006.147.08:18:10.29/fmout-gps/S +4.85E-07 2006.147.08:18:10.29:scan_name=147-0819,k06147,60 2006.147.08:18:10.29:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.147.08:18:11.14#flagr#flagr/antenna,new-source 2006.147.08:18:11.15:checkk5 2006.147.08:18:11.54/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:18:11.91/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:18:12.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:18:12.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:18:13.06/chk_obsdata//k5ts1/k06147_ts1_147-0817*_20??1470817??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:18:13.44/chk_obsdata//k5ts2/k06147_ts2_147-0817*_20??1470817??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:18:13.81/chk_obsdata//k5ts3/k06147_ts3_147-0817*_20??1470817??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:18:14.19/chk_obsdata//k5ts4/k06147_ts4_147-0817*_20??1470817??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:18:14.89/k5log//k5ts1_log_newline 2006.147.08:18:15.58/k5log//k5ts2_log_newline 2006.147.08:18:16.27/k5log//k5ts3_log_newline 2006.147.08:18:16.96/k5log//k5ts4_log_newline 2006.147.08:18:16.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:18:16.99:4f8m12a=2 2006.147.08:18:16.99$4f8m12a/echo=on 2006.147.08:18:16.99$4f8m12a/pcalon 2006.147.08:18:16.99$pcalon/"no phase cal control is implemented here 2006.147.08:18:16.99$4f8m12a/"tpicd=stop 2006.147.08:18:16.99$4f8m12a/vc4f8 2006.147.08:18:16.99$vc4f8/valo=1,532.99 2006.147.08:18:16.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:18:16.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:18:16.99#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:16.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:16.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:16.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:17.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:18:17.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:17.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:17.09#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:18:17.09#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:18:17.09$vc4f8/va=1,8 2006.147.08:18:17.09#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:18:17.09#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:18:17.09#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:17.09#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:17.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:17.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:17.13#ibcon#[25=AT01-08\r\n] 2006.147.08:18:17.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:17.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:17.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:18:17.16#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:17.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:17.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:17.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:17.30#ibcon#[25=USB\r\n] 2006.147.08:18:17.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:17.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:17.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:18:17.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:18:17.36$vc4f8/valo=2,572.99 2006.147.08:18:17.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:18:17.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:18:17.36#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:17.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:17.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:17.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:17.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:18:17.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:17.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:17.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:18:17.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:18:17.41$vc4f8/va=2,7 2006.147.08:18:17.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:18:17.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:18:17.41#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:17.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:17.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:17.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:17.50#ibcon#[25=AT02-07\r\n] 2006.147.08:18:17.54#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:17.54#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:17.54#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:18:17.54#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:17.54#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:17.66#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:17.66#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:17.68#ibcon#[25=USB\r\n] 2006.147.08:18:17.74#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:17.74#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:17.74#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:18:17.74#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:18:17.74$vc4f8/valo=3,672.99 2006.147.08:18:17.74#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:18:17.74#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:18:17.74#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:17.74#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:17.74#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:17.74#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:17.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:18:17.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:17.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:17.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:18:17.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:18:17.79$vc4f8/va=3,8 2006.147.08:18:17.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:18:17.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:18:17.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:17.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:17.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:17.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:17.88#ibcon#[25=AT03-08\r\n] 2006.147.08:18:17.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:17.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:17.91#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:18:17.91#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:17.91#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:18.03#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:18.03#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:18.05#ibcon#[25=USB\r\n] 2006.147.08:18:18.08#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:18.08#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:18.08#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:18:18.08#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:18:18.08$vc4f8/valo=4,832.99 2006.147.08:18:18.08#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.08:18:18.08#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.08:18:18.08#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:18.08#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:18.08#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:18.08#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:18.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:18:18.14#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:18.14#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:18.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:18:18.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:18:18.14$vc4f8/va=4,7 2006.147.08:18:18.14#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.08:18:18.14#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.08:18:18.14#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:18.14#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:18.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:18.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:18.22#ibcon#[25=AT04-07\r\n] 2006.147.08:18:18.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:18.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:18.25#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.08:18:18.25#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:18.25#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:18.37#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:18.37#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:18.39#ibcon#[25=USB\r\n] 2006.147.08:18:18.45#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:18.45#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:18.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:18:18.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:18:18.45$vc4f8/valo=5,652.99 2006.147.08:18:18.45#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:18:18.45#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:18:18.45#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:18.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:18:18.45#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:18:18.45#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:18:18.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:18:18.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:18:18.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:18:18.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:18:18.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:18:18.50$vc4f8/va=5,6 2006.147.08:18:18.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.08:18:18.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.08:18:18.50#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:18.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:18:18.57#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:18:18.57#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:18:18.59#ibcon#[25=AT05-06\r\n] 2006.147.08:18:18.62#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:18:18.62#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:18:18.62#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.08:18:18.62#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:18.62#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:18:18.74#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:18:18.74#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:18:18.76#ibcon#[25=USB\r\n] 2006.147.08:18:18.79#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:18:18.79#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:18:18.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:18:18.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:18:18.79$vc4f8/valo=6,772.99 2006.147.08:18:18.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.08:18:18.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.08:18:18.79#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:18.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:18.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:18.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:18.81#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:18:18.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:18.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:18.85#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:18:18.85#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:18:18.85$vc4f8/va=6,5 2006.147.08:18:18.85#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.08:18:18.85#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.08:18:18.85#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:18.85#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:18.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:18.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:18.93#ibcon#[25=AT06-05\r\n] 2006.147.08:18:18.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:18.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:18.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.08:18:18.96#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:18.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:19.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:19.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:19.13#ibcon#[25=USB\r\n] 2006.147.08:18:19.16#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:19.16#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:19.16#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:18:19.16#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:18:19.16$vc4f8/valo=7,832.99 2006.147.08:18:19.16#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.08:18:19.16#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.08:18:19.16#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:19.16#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:19.16#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:19.16#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:19.18#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:18:19.22#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:19.22#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:19.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:18:19.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:18:19.22$vc4f8/va=7,5 2006.147.08:18:19.22#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.08:18:19.22#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.08:18:19.22#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:19.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:19.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:19.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:19.30#ibcon#[25=AT07-05\r\n] 2006.147.08:18:19.33#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:19.33#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:19.33#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.08:18:19.33#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:19.33#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:18:19.45#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:18:19.45#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:18:19.47#ibcon#[25=USB\r\n] 2006.147.08:18:19.50#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:18:19.50#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:18:19.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:18:19.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:18:19.50$vc4f8/valo=8,852.99 2006.147.08:18:19.50#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.08:18:19.50#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.08:18:19.50#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:19.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:18:19.50#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:18:19.50#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:18:19.52#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:18:19.56#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:18:19.56#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:18:19.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:18:19.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:18:19.56$vc4f8/va=8,5 2006.147.08:18:19.56#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.08:18:19.56#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.08:18:19.56#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:19.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:18:19.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:18:19.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:18:19.64#ibcon#[25=AT08-05\r\n] 2006.147.08:18:19.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:18:19.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:18:19.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.08:18:19.67#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:19.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:18:19.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:18:19.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:18:19.81#ibcon#[25=USB\r\n] 2006.147.08:18:19.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:18:19.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:18:19.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:18:19.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:18:19.84$vc4f8/vblo=1,632.99 2006.147.08:18:19.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.08:18:19.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.08:18:19.84#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:19.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:18:19.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:18:19.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:18:19.86#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:18:19.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:18:19.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:18:19.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:18:19.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:18:19.90$vc4f8/vb=1,4 2006.147.08:18:19.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.08:18:19.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.08:18:19.90#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:19.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:18:19.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:18:19.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:18:19.92#ibcon#[27=AT01-04\r\n] 2006.147.08:18:19.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:18:19.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:18:19.95#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.08:18:19.95#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:19.95#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:18:20.07#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:18:20.07#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:18:20.09#ibcon#[27=USB\r\n] 2006.147.08:18:20.12#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:18:20.12#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:18:20.12#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:18:20.12#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:18:20.12$vc4f8/vblo=2,640.99 2006.147.08:18:20.12#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:18:20.12#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:18:20.12#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:20.12#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:20.12#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:20.12#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:20.14#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:18:20.18#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:20.18#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:18:20.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:18:20.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:18:20.18$vc4f8/vb=2,4 2006.147.08:18:20.18#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:18:20.18#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:18:20.18#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:20.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:20.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:20.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:20.26#ibcon#[27=AT02-04\r\n] 2006.147.08:18:20.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:20.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:18:20.29#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:18:20.29#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:20.29#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:20.41#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:20.41#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:20.43#ibcon#[27=USB\r\n] 2006.147.08:18:20.46#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:20.46#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:18:20.46#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:18:20.46#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:18:20.46$vc4f8/vblo=3,656.99 2006.147.08:18:20.46#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:18:20.46#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:18:20.46#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:20.46#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:20.46#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:20.46#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:20.48#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:18:20.52#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:20.52#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:18:20.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:18:20.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:18:20.52$vc4f8/vb=3,4 2006.147.08:18:20.52#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:18:20.52#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:18:20.52#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:20.52#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:20.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:20.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:20.60#ibcon#[27=AT03-04\r\n] 2006.147.08:18:20.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:20.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:18:20.63#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:18:20.63#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:20.63#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:20.75#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:20.75#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:20.77#ibcon#[27=USB\r\n] 2006.147.08:18:20.80#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:20.80#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:18:20.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:18:20.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:18:20.80$vc4f8/vblo=4,712.99 2006.147.08:18:20.80#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:18:20.80#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:18:20.80#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:20.80#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:20.80#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:20.80#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:20.82#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:18:20.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:20.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:18:20.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:18:20.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:18:20.86$vc4f8/vb=4,4 2006.147.08:18:20.86#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:18:20.86#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:18:20.86#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:20.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:20.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:20.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:20.94#ibcon#[27=AT04-04\r\n] 2006.147.08:18:20.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:20.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:18:20.97#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:18:20.97#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:20.97#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:21.09#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:21.09#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:21.11#ibcon#[27=USB\r\n] 2006.147.08:18:21.14#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:21.14#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:18:21.14#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:18:21.14#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:18:21.14$vc4f8/vblo=5,744.99 2006.147.08:18:21.14#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.08:18:21.14#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.08:18:21.14#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:21.14#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:21.14#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:21.14#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:21.16#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:18:21.20#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:21.20#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:18:21.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:18:21.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:18:21.20$vc4f8/vb=5,3 2006.147.08:18:21.20#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.08:18:21.20#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.08:18:21.20#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:21.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:21.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:21.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:21.28#ibcon#[27=AT05-03\r\n] 2006.147.08:18:21.31#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:21.31#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:18:21.31#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.08:18:21.31#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:21.31#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:21.41#abcon#<5=/06 3.3 6.1 18.83 931011.5\r\n> 2006.147.08:18:21.43#abcon#{5=INTERFACE CLEAR} 2006.147.08:18:21.43#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:21.43#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:21.45#ibcon#[27=USB\r\n] 2006.147.08:18:21.48#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:21.48#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:18:21.48#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:18:21.48#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:18:21.48$vc4f8/vblo=6,752.99 2006.147.08:18:21.48#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.08:18:21.48#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.08:18:21.48#ibcon#ireg 17 cls_cnt 0 2006.147.08:18:21.48#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:21.48#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:21.48#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:21.49#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:18:21.50#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:18:21.54#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:21.54#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:18:21.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:18:21.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:18:21.54$vc4f8/vb=6,4 2006.147.08:18:21.54#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.08:18:21.54#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.08:18:21.54#ibcon#ireg 11 cls_cnt 2 2006.147.08:18:21.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:21.60#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:21.60#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:21.62#ibcon#[27=AT06-04\r\n] 2006.147.08:18:21.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:21.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:18:21.65#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.08:18:21.65#ibcon#ireg 7 cls_cnt 0 2006.147.08:18:21.65#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:21.77#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:21.77#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:21.79#ibcon#[27=USB\r\n] 2006.147.08:18:21.82#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:21.82#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:18:21.82#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:18:21.82#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:18:21.82$vc4f8/vabw=wide 2006.147.08:18:21.82#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.08:18:21.82#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.08:18:21.82#ibcon#ireg 8 cls_cnt 0 2006.147.08:18:21.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:21.82#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:21.82#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:21.84#ibcon#[25=BW32\r\n] 2006.147.08:18:21.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:21.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:18:21.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:18:21.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:18:21.87$vc4f8/vbbw=wide 2006.147.08:18:21.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.08:18:21.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.08:18:21.87#ibcon#ireg 8 cls_cnt 0 2006.147.08:18:21.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:18:21.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:18:21.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:18:21.96#ibcon#[27=BW32\r\n] 2006.147.08:18:21.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:18:21.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:18:21.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:18:21.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:18:21.99$4f8m12a/ifd4f 2006.147.08:18:21.99$ifd4f/lo= 2006.147.08:18:21.99$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:18:21.99$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:18:21.99$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:18:21.99$ifd4f/patch= 2006.147.08:18:21.99$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:18:21.99$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:18:22.00$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:18:22.00$4f8m12a/"form=m,16.000,1:2 2006.147.08:18:22.00$4f8m12a/"tpicd 2006.147.08:18:22.00$4f8m12a/echo=off 2006.147.08:18:22.00$4f8m12a/xlog=off 2006.147.08:18:22.00:!2006.147.08:18:50 2006.147.08:18:30.14#trakl#Source acquired 2006.147.08:18:31.14#flagr#flagr/antenna,acquired 2006.147.08:18:50.01:preob 2006.147.08:18:51.14/onsource/TRACKING 2006.147.08:18:51.14:!2006.147.08:19:00 2006.147.08:19:00.00:data_valid=on 2006.147.08:19:00.00:midob 2006.147.08:19:00.14/onsource/TRACKING 2006.147.08:19:00.14/wx/18.80,1011.5,94 2006.147.08:19:00.21/cable/+6.5379E-03 2006.147.08:19:01.31/va/01,08,usb,yes,37,39 2006.147.08:19:01.31/va/02,07,usb,yes,37,39 2006.147.08:19:01.31/va/03,08,usb,yes,28,28 2006.147.08:19:01.31/va/04,07,usb,yes,38,41 2006.147.08:19:01.31/va/05,06,usb,yes,43,46 2006.147.08:19:01.31/va/06,05,usb,yes,44,44 2006.147.08:19:01.31/va/07,05,usb,yes,44,43 2006.147.08:19:01.31/va/08,05,usb,yes,47,46 2006.147.08:19:01.54/valo/01,532.99,yes,locked 2006.147.08:19:01.54/valo/02,572.99,yes,locked 2006.147.08:19:01.54/valo/03,672.99,yes,locked 2006.147.08:19:01.54/valo/04,832.99,yes,locked 2006.147.08:19:01.54/valo/05,652.99,yes,locked 2006.147.08:19:01.54/valo/06,772.99,yes,locked 2006.147.08:19:01.54/valo/07,832.99,yes,locked 2006.147.08:19:01.54/valo/08,852.99,yes,locked 2006.147.08:19:02.63/vb/01,04,usb,yes,29,27 2006.147.08:19:02.63/vb/02,04,usb,yes,31,32 2006.147.08:19:02.63/vb/03,04,usb,yes,27,31 2006.147.08:19:02.63/vb/04,04,usb,yes,28,28 2006.147.08:19:02.63/vb/05,03,usb,yes,33,37 2006.147.08:19:02.63/vb/06,04,usb,yes,27,30 2006.147.08:19:02.63/vb/07,04,usb,yes,29,29 2006.147.08:19:02.63/vb/08,03,usb,yes,33,37 2006.147.08:19:02.86/vblo/01,632.99,yes,locked 2006.147.08:19:02.86/vblo/02,640.99,yes,locked 2006.147.08:19:02.86/vblo/03,656.99,yes,locked 2006.147.08:19:02.86/vblo/04,712.99,yes,locked 2006.147.08:19:02.86/vblo/05,744.99,yes,locked 2006.147.08:19:02.86/vblo/06,752.99,yes,locked 2006.147.08:19:02.86/vblo/07,734.99,yes,locked 2006.147.08:19:02.86/vblo/08,744.99,yes,locked 2006.147.08:19:03.01/vabw/8 2006.147.08:19:03.16/vbbw/8 2006.147.08:19:03.25/xfe/off,on,14.2 2006.147.08:19:03.64/ifatt/23,28,28,28 2006.147.08:19:04.07/fmout-gps/S +4.85E-07 2006.147.08:19:04.12:!2006.147.08:20:00 2006.147.08:20:00.01:data_valid=off 2006.147.08:20:00.02:postob 2006.147.08:20:00.11/cable/+6.5375E-03 2006.147.08:20:00.11/wx/18.75,1011.5,93 2006.147.08:20:00.20/fmout-gps/S +4.86E-07 2006.147.08:20:00.20:scan_name=147-0820,k06147,60 2006.147.08:20:00.20:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.147.08:20:02.14#flagr#flagr/antenna,new-source 2006.147.08:20:02.15:checkk5 2006.147.08:20:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:20:02.92/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:20:06.29/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:20:06.67/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:20:07.05/chk_obsdata//k5ts1/k06147_ts1_147-0819*_20??1470819??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:20:07.42/chk_obsdata//k5ts2/k06147_ts2_147-0819*_20??1470819??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:20:07.79/chk_obsdata//k5ts3/k06147_ts3_147-0819*_20??1470819??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:20:08.16/chk_obsdata//k5ts4/k06147_ts4_147-0819*_20??1470819??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:20:08.86/k5log//k5ts1_log_newline 2006.147.08:20:09.56/k5log//k5ts2_log_newline 2006.147.08:20:10.32/k5log//k5ts3_log_newline 2006.147.08:20:11.01/k5log//k5ts4_log_newline 2006.147.08:20:11.04/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:20:11.04:4f8m12a=2 2006.147.08:20:11.04$4f8m12a/echo=on 2006.147.08:20:11.04$4f8m12a/pcalon 2006.147.08:20:11.04$pcalon/"no phase cal control is implemented here 2006.147.08:20:11.04$4f8m12a/"tpicd=stop 2006.147.08:20:11.04$4f8m12a/vc4f8 2006.147.08:20:11.04$vc4f8/valo=1,532.99 2006.147.08:20:11.04#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:20:11.04#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:20:11.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:11.04#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:11.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:11.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:11.09#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:20:11.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:11.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:11.13#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:20:11.13#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:20:11.13$vc4f8/va=1,8 2006.147.08:20:11.13#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:20:11.13#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:20:11.13#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:11.13#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:11.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:11.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:11.17#ibcon#[25=AT01-08\r\n] 2006.147.08:20:11.20#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:11.20#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:11.20#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:20:11.20#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:11.20#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:11.32#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:11.32#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:11.34#ibcon#[25=USB\r\n] 2006.147.08:20:11.37#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:11.37#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:11.37#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:20:11.37#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:20:11.37$vc4f8/valo=2,572.99 2006.147.08:20:11.37#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:20:11.37#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:20:11.37#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:11.37#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:11.37#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:11.37#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:11.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:20:11.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:11.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:11.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:20:11.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:20:11.45$vc4f8/va=2,7 2006.147.08:20:11.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:20:11.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:20:11.45#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:11.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:11.49#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:11.49#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:11.52#ibcon#[25=AT02-07\r\n] 2006.147.08:20:11.54#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:11.54#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:11.54#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:20:11.54#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:11.54#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:11.66#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:11.66#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:11.68#ibcon#[25=USB\r\n] 2006.147.08:20:11.71#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:11.71#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:11.71#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:20:11.71#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:20:11.71$vc4f8/valo=3,672.99 2006.147.08:20:11.71#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:20:11.71#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:20:11.71#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:11.71#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:11.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:11.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:11.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:20:11.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:11.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:11.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:20:11.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:20:11.79$vc4f8/va=3,8 2006.147.08:20:11.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:20:11.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:20:11.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:11.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:11.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:11.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:11.85#ibcon#[25=AT03-08\r\n] 2006.147.08:20:11.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:11.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:11.88#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:20:11.88#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:11.88#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:12.00#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:12.00#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:12.02#ibcon#[25=USB\r\n] 2006.147.08:20:12.05#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:12.05#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:12.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:20:12.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:20:12.05$vc4f8/valo=4,832.99 2006.147.08:20:12.05#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:20:12.05#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:20:12.05#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:12.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:12.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:12.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:12.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:20:12.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:12.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:12.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:20:12.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:20:12.11$vc4f8/va=4,7 2006.147.08:20:12.11#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:20:12.11#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:20:12.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:12.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:12.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:12.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:12.19#ibcon#[25=AT04-07\r\n] 2006.147.08:20:12.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:12.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:12.22#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:20:12.22#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:12.22#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:12.34#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:12.34#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:12.36#ibcon#[25=USB\r\n] 2006.147.08:20:12.39#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:12.39#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:12.39#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:20:12.39#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:20:12.39$vc4f8/valo=5,652.99 2006.147.08:20:12.39#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:20:12.39#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:20:12.39#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:12.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:12.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:12.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:12.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:20:12.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:12.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:12.45#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:20:12.45#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:20:12.45$vc4f8/va=5,6 2006.147.08:20:12.45#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:20:12.45#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:20:12.45#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:12.45#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:12.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:12.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:12.53#ibcon#[25=AT05-06\r\n] 2006.147.08:20:12.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:12.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:12.56#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:20:12.56#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:12.56#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:12.68#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:12.68#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:12.70#ibcon#[25=USB\r\n] 2006.147.08:20:12.73#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:12.73#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:12.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:20:12.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:20:12.73$vc4f8/valo=6,772.99 2006.147.08:20:12.73#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:20:12.73#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:20:12.73#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:12.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:12.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:12.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:12.75#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:20:12.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:12.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:12.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:20:12.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:20:12.79$vc4f8/va=6,5 2006.147.08:20:12.79#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.08:20:12.79#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.08:20:12.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:12.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:12.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:12.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:12.87#ibcon#[25=AT06-05\r\n] 2006.147.08:20:12.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:12.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:12.90#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.08:20:12.90#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:12.90#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:13.02#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:13.02#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:13.04#ibcon#[25=USB\r\n] 2006.147.08:20:13.07#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:13.07#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:13.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:20:13.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:20:13.07$vc4f8/valo=7,832.99 2006.147.08:20:13.07#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.08:20:13.07#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.08:20:13.07#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:13.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:13.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:13.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:13.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:20:13.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:13.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:13.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:20:13.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:20:13.13$vc4f8/va=7,5 2006.147.08:20:13.13#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.08:20:13.13#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.08:20:13.13#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:13.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:13.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:13.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:13.21#ibcon#[25=AT07-05\r\n] 2006.147.08:20:13.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:13.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:13.24#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.08:20:13.24#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:13.24#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:20:13.28#abcon#<5=/06 3.2 6.0 18.73 931011.4\r\n> 2006.147.08:20:13.30#abcon#{5=INTERFACE CLEAR} 2006.147.08:20:13.36#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:20:13.36#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:20:13.36#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:20:13.40#ibcon#[25=USB\r\n] 2006.147.08:20:13.42#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:20:13.42#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:20:13.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:20:13.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:20:13.42$vc4f8/valo=8,852.99 2006.147.08:20:13.42#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:20:13.42#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:20:13.42#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:13.42#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:20:13.42#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:20:13.42#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:20:13.44#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:20:13.48#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:20:13.48#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:20:13.48#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:20:13.48#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:20:13.48$vc4f8/va=8,5 2006.147.08:20:13.48#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.08:20:13.48#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.08:20:13.48#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:13.48#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:20:13.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:20:13.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:20:13.56#ibcon#[25=AT08-05\r\n] 2006.147.08:20:13.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:20:13.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:20:13.59#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.08:20:13.59#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:13.59#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:20:13.71#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:20:13.71#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:20:13.73#ibcon#[25=USB\r\n] 2006.147.08:20:13.76#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:20:13.76#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:20:13.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:20:13.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:20:13.76$vc4f8/vblo=1,632.99 2006.147.08:20:13.76#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:20:13.76#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:20:13.76#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:13.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:13.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:13.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:13.78#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:20:13.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:13.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:20:13.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:20:13.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:20:13.82$vc4f8/vb=1,4 2006.147.08:20:13.82#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:20:13.82#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:20:13.82#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:13.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:13.82#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:13.82#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:13.84#ibcon#[27=AT01-04\r\n] 2006.147.08:20:13.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:13.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:20:13.87#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:20:13.87#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:13.87#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:13.99#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:13.99#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:14.01#ibcon#[27=USB\r\n] 2006.147.08:20:14.04#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:14.04#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:20:14.04#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:20:14.04#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:20:14.04$vc4f8/vblo=2,640.99 2006.147.08:20:14.04#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:20:14.04#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:20:14.04#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:14.04#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:14.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:14.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:14.06#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:20:14.10#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:14.10#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:20:14.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:20:14.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:20:14.10$vc4f8/vb=2,4 2006.147.08:20:14.10#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:20:14.10#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:20:14.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:14.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:14.16#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:14.16#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:14.18#ibcon#[27=AT02-04\r\n] 2006.147.08:20:14.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:14.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:20:14.21#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:20:14.21#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:14.21#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:14.33#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:14.33#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:14.35#ibcon#[27=USB\r\n] 2006.147.08:20:14.38#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:14.38#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:20:14.38#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:20:14.38#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:20:14.38$vc4f8/vblo=3,656.99 2006.147.08:20:14.38#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:20:14.38#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:20:14.38#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:14.38#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:14.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:14.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:14.40#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:20:14.44#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:14.44#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:20:14.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:20:14.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:20:14.44$vc4f8/vb=3,4 2006.147.08:20:14.44#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:20:14.44#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:20:14.44#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:14.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:14.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:14.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:14.52#ibcon#[27=AT03-04\r\n] 2006.147.08:20:14.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:14.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:20:14.55#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:20:14.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:14.55#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:14.67#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:14.67#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:14.69#ibcon#[27=USB\r\n] 2006.147.08:20:14.72#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:14.72#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:20:14.72#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:20:14.72#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:20:14.72$vc4f8/vblo=4,712.99 2006.147.08:20:14.72#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:20:14.72#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:20:14.72#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:14.72#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:14.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:14.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:14.74#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:20:14.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:14.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:20:14.79#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:20:14.79#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:20:14.79$vc4f8/vb=4,4 2006.147.08:20:14.79#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:20:14.79#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:20:14.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:14.79#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:14.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:14.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:14.85#ibcon#[27=AT04-04\r\n] 2006.147.08:20:14.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:14.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:20:14.88#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:20:14.88#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:14.88#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:15.00#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:15.00#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:15.02#ibcon#[27=USB\r\n] 2006.147.08:20:15.05#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:15.05#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:20:15.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:20:15.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:20:15.05$vc4f8/vblo=5,744.99 2006.147.08:20:15.05#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:20:15.05#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:20:15.05#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:15.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:15.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:15.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:15.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:20:15.11#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:15.11#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:20:15.11#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:20:15.11#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:20:15.11$vc4f8/vb=5,3 2006.147.08:20:15.11#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:20:15.11#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:20:15.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:15.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:15.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:15.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:15.19#ibcon#[27=AT05-03\r\n] 2006.147.08:20:15.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:15.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:20:15.22#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:20:15.22#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:15.22#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:15.34#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:15.34#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:15.36#ibcon#[27=USB\r\n] 2006.147.08:20:15.39#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:15.39#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:20:15.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:20:15.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:20:15.39$vc4f8/vblo=6,752.99 2006.147.08:20:15.39#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:20:15.39#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:20:15.39#ibcon#ireg 17 cls_cnt 0 2006.147.08:20:15.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:15.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:15.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:15.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:20:15.45#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:15.45#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:20:15.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:20:15.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:20:15.45$vc4f8/vb=6,4 2006.147.08:20:15.45#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.08:20:15.45#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.08:20:15.45#ibcon#ireg 11 cls_cnt 2 2006.147.08:20:15.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:15.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:15.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:15.53#ibcon#[27=AT06-04\r\n] 2006.147.08:20:15.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:15.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:20:15.56#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.08:20:15.56#ibcon#ireg 7 cls_cnt 0 2006.147.08:20:15.56#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:15.68#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:15.68#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:15.70#ibcon#[27=USB\r\n] 2006.147.08:20:15.73#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:15.73#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:20:15.73#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:20:15.73#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:20:15.73$vc4f8/vabw=wide 2006.147.08:20:15.73#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.08:20:15.73#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.08:20:15.73#ibcon#ireg 8 cls_cnt 0 2006.147.08:20:15.73#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:15.73#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:15.73#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:15.75#ibcon#[25=BW32\r\n] 2006.147.08:20:15.78#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:15.78#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:20:15.78#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:20:15.78#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:20:15.78$vc4f8/vbbw=wide 2006.147.08:20:15.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.08:20:15.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.08:20:15.78#ibcon#ireg 8 cls_cnt 0 2006.147.08:20:15.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:20:15.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:20:15.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:20:15.87#ibcon#[27=BW32\r\n] 2006.147.08:20:15.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:20:15.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:20:15.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:20:15.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:20:15.90$4f8m12a/ifd4f 2006.147.08:20:15.90$ifd4f/lo= 2006.147.08:20:15.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:20:15.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:20:15.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:20:15.90$ifd4f/patch= 2006.147.08:20:15.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:20:15.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:20:15.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:20:15.90$4f8m12a/"form=m,16.000,1:2 2006.147.08:20:15.91$4f8m12a/"tpicd 2006.147.08:20:15.91$4f8m12a/echo=off 2006.147.08:20:15.91$4f8m12a/xlog=off 2006.147.08:20:15.91:!2006.147.08:20:40 2006.147.08:20:18.14#trakl#Source acquired 2006.147.08:20:18.14#flagr#flagr/antenna,acquired 2006.147.08:20:40.01:preob 2006.147.08:20:41.14/onsource/TRACKING 2006.147.08:20:41.14:!2006.147.08:20:50 2006.147.08:20:50.00:data_valid=on 2006.147.08:20:50.00:midob 2006.147.08:20:50.14/onsource/TRACKING 2006.147.08:20:50.14/wx/18.71,1011.4,93 2006.147.08:20:50.36/cable/+6.5365E-03 2006.147.08:20:51.45/va/01,08,usb,yes,36,38 2006.147.08:20:51.45/va/02,07,usb,yes,36,38 2006.147.08:20:51.45/va/03,08,usb,yes,27,27 2006.147.08:20:51.45/va/04,07,usb,yes,37,40 2006.147.08:20:51.45/va/05,06,usb,yes,42,45 2006.147.08:20:51.45/va/06,05,usb,yes,43,42 2006.147.08:20:51.45/va/07,05,usb,yes,43,42 2006.147.08:20:51.45/va/08,05,usb,yes,46,45 2006.147.08:20:51.68/valo/01,532.99,yes,locked 2006.147.08:20:51.68/valo/02,572.99,yes,locked 2006.147.08:20:51.68/valo/03,672.99,yes,locked 2006.147.08:20:51.68/valo/04,832.99,yes,locked 2006.147.08:20:51.68/valo/05,652.99,yes,locked 2006.147.08:20:51.68/valo/06,772.99,yes,locked 2006.147.08:20:51.68/valo/07,832.99,yes,locked 2006.147.08:20:51.68/valo/08,852.99,yes,locked 2006.147.08:20:52.77/vb/01,04,usb,yes,29,27 2006.147.08:20:52.77/vb/02,04,usb,yes,30,32 2006.147.08:20:52.77/vb/03,04,usb,yes,27,30 2006.147.08:20:52.77/vb/04,04,usb,yes,28,28 2006.147.08:20:52.77/vb/05,03,usb,yes,33,37 2006.147.08:20:52.77/vb/06,04,usb,yes,27,30 2006.147.08:20:52.77/vb/07,04,usb,yes,29,29 2006.147.08:20:52.77/vb/08,03,usb,yes,33,37 2006.147.08:20:53.00/vblo/01,632.99,yes,locked 2006.147.08:20:53.00/vblo/02,640.99,yes,locked 2006.147.08:20:53.00/vblo/03,656.99,yes,locked 2006.147.08:20:53.00/vblo/04,712.99,yes,locked 2006.147.08:20:53.00/vblo/05,744.99,yes,locked 2006.147.08:20:53.00/vblo/06,752.99,yes,locked 2006.147.08:20:53.00/vblo/07,734.99,yes,locked 2006.147.08:20:53.00/vblo/08,744.99,yes,locked 2006.147.08:20:53.15/vabw/8 2006.147.08:20:53.30/vbbw/8 2006.147.08:20:53.39/xfe/off,on,14.0 2006.147.08:20:53.77/ifatt/23,28,28,28 2006.147.08:20:54.07/fmout-gps/S +4.85E-07 2006.147.08:20:54.11:!2006.147.08:21:50 2006.147.08:21:50.01:data_valid=off 2006.147.08:21:50.02:postob 2006.147.08:21:50.12/cable/+6.5379E-03 2006.147.08:21:50.13/wx/18.67,1011.4,93 2006.147.08:21:50.19/fmout-gps/S +4.85E-07 2006.147.08:21:50.20:scan_name=147-0822,k06147,60 2006.147.08:21:50.20:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.147.08:21:52.14#flagr#flagr/antenna,new-source 2006.147.08:21:52.15:checkk5 2006.147.08:21:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:21:52.92/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:21:53.55/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:21:53.93/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:21:54.31/chk_obsdata//k5ts1/k06147_ts1_147-0820*_20??1470820??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:21:54.68/chk_obsdata//k5ts2/k06147_ts2_147-0820*_20??1470820??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:21:55.05/chk_obsdata//k5ts3/k06147_ts3_147-0820*_20??1470820??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:21:55.44/chk_obsdata//k5ts4/k06147_ts4_147-0820*_20??1470820??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:21:56.14/k5log//k5ts1_log_newline 2006.147.08:21:56.83/k5log//k5ts2_log_newline 2006.147.08:21:57.52/k5log//k5ts3_log_newline 2006.147.08:21:58.22/k5log//k5ts4_log_newline 2006.147.08:21:58.24/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:21:58.24:4f8m12a=2 2006.147.08:21:58.24$4f8m12a/echo=on 2006.147.08:21:58.24$4f8m12a/pcalon 2006.147.08:21:58.24$pcalon/"no phase cal control is implemented here 2006.147.08:21:58.24$4f8m12a/"tpicd=stop 2006.147.08:21:58.24$4f8m12a/vc4f8 2006.147.08:21:58.24$vc4f8/valo=1,532.99 2006.147.08:21:58.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:21:58.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:21:58.25#ibcon#ireg 17 cls_cnt 0 2006.147.08:21:58.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:21:58.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:21:58.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:21:58.29#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:21:58.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:21:58.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:21:58.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:21:58.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:21:58.34$vc4f8/va=1,8 2006.147.08:21:58.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:21:58.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:21:58.34#ibcon#ireg 11 cls_cnt 2 2006.147.08:21:58.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:21:58.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:21:58.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:21:58.39#ibcon#[25=AT01-08\r\n] 2006.147.08:21:58.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:21:58.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:21:58.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:21:58.41#ibcon#ireg 7 cls_cnt 0 2006.147.08:21:58.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:21:58.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:21:58.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:21:58.55#ibcon#[25=USB\r\n] 2006.147.08:21:58.61#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:21:58.61#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:21:58.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:21:58.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:21:58.61$vc4f8/valo=2,572.99 2006.147.08:21:58.61#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:21:58.61#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:21:58.61#ibcon#ireg 17 cls_cnt 0 2006.147.08:21:58.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:21:58.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:21:58.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:21:58.62#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:21:58.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:21:58.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:21:58.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:21:58.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:21:58.66$vc4f8/va=2,7 2006.147.08:21:58.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:21:58.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:21:58.66#ibcon#ireg 11 cls_cnt 2 2006.147.08:21:58.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:21:58.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:21:58.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:21:58.75#ibcon#[25=AT02-07\r\n] 2006.147.08:21:58.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:21:58.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:21:58.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:21:58.79#ibcon#ireg 7 cls_cnt 0 2006.147.08:21:58.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:21:58.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:21:58.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:21:58.92#ibcon#[25=USB\r\n] 2006.147.08:21:58.98#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:21:58.98#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:21:58.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:21:58.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:21:58.98$vc4f8/valo=3,672.99 2006.147.08:21:58.98#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:21:58.98#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:21:58.98#ibcon#ireg 17 cls_cnt 0 2006.147.08:21:58.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:21:58.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:21:58.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:21:58.99#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:21:59.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:21:59.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:21:59.03#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:21:59.03#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:21:59.03$vc4f8/va=3,8 2006.147.08:21:59.03#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:21:59.03#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:21:59.03#ibcon#ireg 11 cls_cnt 2 2006.147.08:21:59.03#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:21:59.10#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:21:59.10#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:21:59.12#ibcon#[25=AT03-08\r\n] 2006.147.08:21:59.15#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:21:59.15#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:21:59.15#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:21:59.15#ibcon#ireg 7 cls_cnt 0 2006.147.08:21:59.15#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:21:59.27#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:21:59.27#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:21:59.29#ibcon#[25=USB\r\n] 2006.147.08:21:59.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:21:59.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:21:59.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:21:59.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:21:59.32$vc4f8/valo=4,832.99 2006.147.08:21:59.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:21:59.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:21:59.32#ibcon#ireg 17 cls_cnt 0 2006.147.08:21:59.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:21:59.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:21:59.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:21:59.34#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:21:59.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:21:59.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:21:59.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:21:59.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:21:59.38$vc4f8/va=4,7 2006.147.08:21:59.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:21:59.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:21:59.38#ibcon#ireg 11 cls_cnt 2 2006.147.08:21:59.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:21:59.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:21:59.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:21:59.46#ibcon#[25=AT04-07\r\n] 2006.147.08:21:59.49#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:21:59.49#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:21:59.49#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:21:59.49#ibcon#ireg 7 cls_cnt 0 2006.147.08:21:59.49#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:21:59.61#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:21:59.61#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:21:59.63#ibcon#[25=USB\r\n] 2006.147.08:21:59.66#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:21:59.66#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:21:59.66#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:21:59.66#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:21:59.66$vc4f8/valo=5,652.99 2006.147.08:21:59.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:21:59.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:21:59.66#ibcon#ireg 17 cls_cnt 0 2006.147.08:21:59.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:21:59.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:21:59.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:21:59.68#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:21:59.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:21:59.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:21:59.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:21:59.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:21:59.72$vc4f8/va=5,6 2006.147.08:21:59.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:21:59.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:21:59.72#ibcon#ireg 11 cls_cnt 2 2006.147.08:21:59.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:21:59.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:21:59.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:21:59.80#ibcon#[25=AT05-06\r\n] 2006.147.08:21:59.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:21:59.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:21:59.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:21:59.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:21:59.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:21:59.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:21:59.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:21:59.97#ibcon#[25=USB\r\n] 2006.147.08:22:00.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:00.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:00.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:22:00.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:22:00.00$vc4f8/valo=6,772.99 2006.147.08:22:00.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:22:00.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:22:00.00#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:00.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:00.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:00.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:00.02#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:22:00.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:00.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:00.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:22:00.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:22:00.06$vc4f8/va=6,5 2006.147.08:22:00.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.147.08:22:00.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.147.08:22:00.06#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:00.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:00.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:00.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:00.14#ibcon#[25=AT06-05\r\n] 2006.147.08:22:00.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:00.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:00.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.147.08:22:00.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:00.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:22:00.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:22:00.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:22:00.31#ibcon#[25=USB\r\n] 2006.147.08:22:00.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:22:00.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.147.08:22:00.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:22:00.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:22:00.34$vc4f8/valo=7,832.99 2006.147.08:22:00.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.147.08:22:00.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.147.08:22:00.34#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:00.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:22:00.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:22:00.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:22:00.36#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:22:00.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:22:00.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.147.08:22:00.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:22:00.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:22:00.40$vc4f8/va=7,5 2006.147.08:22:00.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.147.08:22:00.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.147.08:22:00.40#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:00.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:22:00.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:22:00.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:22:00.48#ibcon#[25=AT07-05\r\n] 2006.147.08:22:00.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:22:00.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.147.08:22:00.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.147.08:22:00.51#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:00.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:22:00.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:22:00.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:22:00.65#ibcon#[25=USB\r\n] 2006.147.08:22:00.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:22:00.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.147.08:22:00.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:22:00.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:22:00.68$vc4f8/valo=8,852.99 2006.147.08:22:00.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.08:22:00.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.08:22:00.68#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:00.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:22:00.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:22:00.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:22:00.70#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:22:00.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:22:00.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:22:00.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:22:00.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:22:00.74$vc4f8/va=8,5 2006.147.08:22:00.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.147.08:22:00.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.147.08:22:00.74#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:00.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:22:00.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:22:00.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:22:00.82#ibcon#[25=AT08-05\r\n] 2006.147.08:22:00.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:22:00.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.147.08:22:00.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.147.08:22:00.85#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:00.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:22:00.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:22:00.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:22:00.99#ibcon#[25=USB\r\n] 2006.147.08:22:01.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:22:01.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.147.08:22:01.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:22:01.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:22:01.02$vc4f8/vblo=1,632.99 2006.147.08:22:01.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.147.08:22:01.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.147.08:22:01.02#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:01.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:22:01.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:22:01.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:22:01.04#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:22:01.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:22:01.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.147.08:22:01.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:22:01.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:22:01.08$vc4f8/vb=1,4 2006.147.08:22:01.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.147.08:22:01.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.147.08:22:01.08#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:01.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:22:01.08#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:22:01.08#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:22:01.11#ibcon#[27=AT01-04\r\n] 2006.147.08:22:01.14#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:22:01.14#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.147.08:22:01.14#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.147.08:22:01.14#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:01.14#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:22:01.26#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:22:01.26#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:22:01.28#ibcon#[27=USB\r\n] 2006.147.08:22:01.31#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:22:01.31#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.147.08:22:01.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:22:01.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:22:01.31$vc4f8/vblo=2,640.99 2006.147.08:22:01.31#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.147.08:22:01.31#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.147.08:22:01.31#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:01.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:22:01.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:22:01.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:22:01.33#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:22:01.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:22:01.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.147.08:22:01.37#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:22:01.37#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:22:01.37$vc4f8/vb=2,4 2006.147.08:22:01.37#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.147.08:22:01.37#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.147.08:22:01.37#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:01.37#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:22:01.43#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:22:01.43#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:22:01.45#ibcon#[27=AT02-04\r\n] 2006.147.08:22:01.48#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:22:01.48#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.147.08:22:01.48#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.147.08:22:01.48#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:01.48#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:22:01.60#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:22:01.60#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:22:01.62#ibcon#[27=USB\r\n] 2006.147.08:22:01.65#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:22:01.65#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.147.08:22:01.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:22:01.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:22:01.65$vc4f8/vblo=3,656.99 2006.147.08:22:01.65#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.147.08:22:01.65#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.147.08:22:01.65#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:01.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:22:01.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:22:01.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:22:01.67#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:22:01.71#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:22:01.71#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.147.08:22:01.71#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:22:01.71#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:22:01.71$vc4f8/vb=3,4 2006.147.08:22:01.71#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.147.08:22:01.71#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.147.08:22:01.71#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:01.71#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:22:01.77#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:22:01.77#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:22:01.79#ibcon#[27=AT03-04\r\n] 2006.147.08:22:01.82#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:22:01.82#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.147.08:22:01.82#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.147.08:22:01.82#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:01.82#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:22:01.94#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:22:01.94#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:22:01.96#ibcon#[27=USB\r\n] 2006.147.08:22:01.99#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:22:01.99#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.147.08:22:01.99#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:22:01.99#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:22:01.99$vc4f8/vblo=4,712.99 2006.147.08:22:01.99#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.147.08:22:01.99#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.147.08:22:01.99#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:01.99#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:22:01.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:22:01.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:22:02.01#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:22:02.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:22:02.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.147.08:22:02.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:22:02.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:22:02.07$vc4f8/vb=4,4 2006.147.08:22:02.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.147.08:22:02.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.147.08:22:02.07#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:02.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:22:02.11#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:22:02.11#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:22:02.13#ibcon#[27=AT04-04\r\n] 2006.147.08:22:02.16#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:22:02.16#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.147.08:22:02.16#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.147.08:22:02.16#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:02.16#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:22:02.28#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:22:02.28#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:22:02.30#ibcon#[27=USB\r\n] 2006.147.08:22:02.33#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:22:02.33#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.147.08:22:02.33#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:22:02.33#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:22:02.33$vc4f8/vblo=5,744.99 2006.147.08:22:02.33#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.147.08:22:02.33#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.147.08:22:02.33#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:02.33#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:22:02.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:22:02.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:22:02.35#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:22:02.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:22:02.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.147.08:22:02.39#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:22:02.39#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:22:02.39$vc4f8/vb=5,3 2006.147.08:22:02.39#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.147.08:22:02.39#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.147.08:22:02.39#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:02.39#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:22:02.45#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:22:02.45#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:22:02.47#ibcon#[27=AT05-03\r\n] 2006.147.08:22:02.50#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:22:02.50#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.147.08:22:02.50#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.147.08:22:02.50#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:02.50#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:22:02.62#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:22:02.62#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:22:02.64#ibcon#[27=USB\r\n] 2006.147.08:22:02.67#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:22:02.67#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.147.08:22:02.67#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:22:02.67#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:22:02.67$vc4f8/vblo=6,752.99 2006.147.08:22:02.67#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.147.08:22:02.67#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.147.08:22:02.67#ibcon#ireg 17 cls_cnt 0 2006.147.08:22:02.67#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:22:02.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:22:02.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:22:02.69#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:22:02.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:22:02.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.147.08:22:02.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:22:02.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:22:02.76$vc4f8/vb=6,4 2006.147.08:22:02.76#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.147.08:22:02.76#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.147.08:22:02.76#ibcon#ireg 11 cls_cnt 2 2006.147.08:22:02.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:22:02.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:22:02.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:22:02.80#ibcon#[27=AT06-04\r\n] 2006.147.08:22:02.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:22:02.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.147.08:22:02.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.147.08:22:02.83#ibcon#ireg 7 cls_cnt 0 2006.147.08:22:02.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:02.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:02.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:02.97#ibcon#[27=USB\r\n] 2006.147.08:22:03.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:03.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.147.08:22:03.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:22:03.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:22:03.00$vc4f8/vabw=wide 2006.147.08:22:03.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.147.08:22:03.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.147.08:22:03.00#ibcon#ireg 8 cls_cnt 0 2006.147.08:22:03.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:03.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:03.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:03.02#ibcon#[25=BW32\r\n] 2006.147.08:22:03.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:03.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.147.08:22:03.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:22:03.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:22:03.05$vc4f8/vbbw=wide 2006.147.08:22:03.05#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:22:03.05#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:22:03.05#ibcon#ireg 8 cls_cnt 0 2006.147.08:22:03.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:22:03.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:22:03.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:22:03.14#ibcon#[27=BW32\r\n] 2006.147.08:22:03.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:22:03.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:22:03.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:22:03.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:22:03.17$4f8m12a/ifd4f 2006.147.08:22:03.17$ifd4f/lo= 2006.147.08:22:03.17$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:22:03.17$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:22:03.17$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:22:03.17$ifd4f/patch= 2006.147.08:22:03.17$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:22:03.17$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:22:03.17$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:22:03.17$4f8m12a/"form=m,16.000,1:2 2006.147.08:22:03.17$4f8m12a/"tpicd 2006.147.08:22:03.17$4f8m12a/echo=off 2006.147.08:22:03.17$4f8m12a/xlog=off 2006.147.08:22:03.17:!2006.147.08:22:30 2006.147.08:22:09.14#trakl#Source acquired 2006.147.08:22:11.14#flagr#flagr/antenna,acquired 2006.147.08:22:30.00:preob 2006.147.08:22:30.13/onsource/TRACKING 2006.147.08:22:30.13:!2006.147.08:22:40 2006.147.08:22:40.00:data_valid=on 2006.147.08:22:40.00:midob 2006.147.08:22:41.13/onsource/TRACKING 2006.147.08:22:41.13/wx/18.64,1011.4,94 2006.147.08:22:41.21/cable/+6.5371E-03 2006.147.08:22:42.30/va/01,08,usb,yes,36,38 2006.147.08:22:42.30/va/02,07,usb,yes,36,38 2006.147.08:22:42.30/va/03,08,usb,yes,27,28 2006.147.08:22:42.30/va/04,07,usb,yes,37,40 2006.147.08:22:42.30/va/05,06,usb,yes,42,45 2006.147.08:22:42.30/va/06,05,usb,yes,43,42 2006.147.08:22:42.30/va/07,05,usb,yes,43,43 2006.147.08:22:42.30/va/08,05,usb,yes,46,45 2006.147.08:22:42.53/valo/01,532.99,yes,locked 2006.147.08:22:42.53/valo/02,572.99,yes,locked 2006.147.08:22:42.53/valo/03,672.99,yes,locked 2006.147.08:22:42.53/valo/04,832.99,yes,locked 2006.147.08:22:42.53/valo/05,652.99,yes,locked 2006.147.08:22:42.53/valo/06,772.99,yes,locked 2006.147.08:22:42.53/valo/07,832.99,yes,locked 2006.147.08:22:42.53/valo/08,852.99,yes,locked 2006.147.08:22:43.62/vb/01,04,usb,yes,29,28 2006.147.08:22:43.62/vb/02,04,usb,yes,31,32 2006.147.08:22:43.62/vb/03,04,usb,yes,27,31 2006.147.08:22:43.62/vb/04,04,usb,yes,28,28 2006.147.08:22:43.62/vb/05,03,usb,yes,33,38 2006.147.08:22:43.62/vb/06,04,usb,yes,28,30 2006.147.08:22:43.62/vb/07,04,usb,yes,30,30 2006.147.08:22:43.62/vb/08,03,usb,yes,34,38 2006.147.08:22:43.86/vblo/01,632.99,yes,locked 2006.147.08:22:43.86/vblo/02,640.99,yes,locked 2006.147.08:22:43.86/vblo/03,656.99,yes,locked 2006.147.08:22:43.86/vblo/04,712.99,yes,locked 2006.147.08:22:43.86/vblo/05,744.99,yes,locked 2006.147.08:22:43.86/vblo/06,752.99,yes,locked 2006.147.08:22:43.86/vblo/07,734.99,yes,locked 2006.147.08:22:43.86/vblo/08,744.99,yes,locked 2006.147.08:22:44.01/vabw/8 2006.147.08:22:44.16/vbbw/8 2006.147.08:22:44.25/xfe/off,on,14.0 2006.147.08:22:44.62/ifatt/23,28,28,28 2006.147.08:22:45.07/fmout-gps/S +4.85E-07 2006.147.08:22:45.11:!2006.147.08:23:40 2006.147.08:23:40.01:data_valid=off 2006.147.08:23:40.02:postob 2006.147.08:23:40.20/cable/+6.5397E-03 2006.147.08:23:40.21/wx/18.62,1011.4,94 2006.147.08:23:40.29/fmout-gps/S +4.85E-07 2006.147.08:23:40.30:scan_name=147-0825,k06147,60 2006.147.08:23:40.30:source=1739+522,174036.98,521143.4,2000.0,cw 2006.147.08:23:41.13#flagr#flagr/antenna,new-source 2006.147.08:23:41.14:checkk5 2006.147.08:23:41.53/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:23:41.92/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:23:42.31/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:23:42.70/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:23:43.08/chk_obsdata//k5ts1/k06147_ts1_147-0822*_20??1470822??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:23:43.46/chk_obsdata//k5ts2/k06147_ts2_147-0822*_20??1470822??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:23:43.84/chk_obsdata//k5ts3/k06147_ts3_147-0822*_20??1470822??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:23:44.23/chk_obsdata//k5ts4/k06147_ts4_147-0822*_20??1470822??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:23:44.92/k5log//k5ts1_log_newline 2006.147.08:23:45.61/k5log//k5ts2_log_newline 2006.147.08:23:46.30/k5log//k5ts3_log_newline 2006.147.08:23:46.99/k5log//k5ts4_log_newline 2006.147.08:23:47.02/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:23:47.02:4f8m12a=3 2006.147.08:23:47.02$4f8m12a/echo=on 2006.147.08:23:47.02$4f8m12a/pcalon 2006.147.08:23:47.02$pcalon/"no phase cal control is implemented here 2006.147.08:23:47.02$4f8m12a/"tpicd=stop 2006.147.08:23:47.02$4f8m12a/vc4f8 2006.147.08:23:47.02$vc4f8/valo=1,532.99 2006.147.08:23:47.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.08:23:47.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.08:23:47.03#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:47.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:47.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:47.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:47.07#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:23:47.12#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:47.12#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:47.12#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:23:47.12#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:23:47.12$vc4f8/va=1,8 2006.147.08:23:47.12#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.08:23:47.12#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.08:23:47.12#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:47.12#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:47.12#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:47.12#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:47.16#ibcon#[25=AT01-08\r\n] 2006.147.08:23:47.19#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:47.19#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:47.19#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.08:23:47.19#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:47.19#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:47.31#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:47.31#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:47.33#ibcon#[25=USB\r\n] 2006.147.08:23:47.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:47.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:47.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:23:47.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:23:47.39$vc4f8/valo=2,572.99 2006.147.08:23:47.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.08:23:47.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.08:23:47.39#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:47.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:47.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:47.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:47.40#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:23:47.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:47.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:47.44#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:23:47.44#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:23:47.44$vc4f8/va=2,7 2006.147.08:23:47.44#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.08:23:47.44#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.08:23:47.44#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:47.44#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:47.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:47.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:47.53#ibcon#[25=AT02-07\r\n] 2006.147.08:23:47.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:47.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:47.57#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.08:23:47.57#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:47.57#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:47.69#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:47.69#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:47.71#ibcon#[25=USB\r\n] 2006.147.08:23:47.74#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:47.74#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:47.74#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:23:47.74#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:23:47.74$vc4f8/valo=3,672.99 2006.147.08:23:47.74#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.08:23:47.74#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.08:23:47.74#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:47.74#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:47.74#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:47.74#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:47.76#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:23:47.80#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:47.80#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:47.80#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:23:47.80#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:23:47.80$vc4f8/va=3,8 2006.147.08:23:47.80#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.08:23:47.80#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.08:23:47.80#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:47.80#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:47.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:47.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:47.88#ibcon#[25=AT03-08\r\n] 2006.147.08:23:47.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:47.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:47.91#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.08:23:47.91#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:47.91#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:48.03#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:48.03#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:48.05#ibcon#[25=USB\r\n] 2006.147.08:23:48.08#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:48.08#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:48.08#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:23:48.08#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:23:48.08$vc4f8/valo=4,832.99 2006.147.08:23:48.08#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:23:48.08#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:23:48.08#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:48.08#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:48.08#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:48.08#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:48.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:23:48.14#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:48.14#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:48.14#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:23:48.14#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:23:48.14$vc4f8/va=4,7 2006.147.08:23:48.14#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.08:23:48.14#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.08:23:48.14#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:48.14#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:48.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:48.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:48.22#ibcon#[25=AT04-07\r\n] 2006.147.08:23:48.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:48.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:48.25#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.08:23:48.25#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:48.25#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:48.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:48.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:48.41#ibcon#[25=USB\r\n] 2006.147.08:23:48.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:48.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:48.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:23:48.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:23:48.44$vc4f8/valo=5,652.99 2006.147.08:23:48.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.08:23:48.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.08:23:48.44#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:48.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:48.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:48.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:48.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:23:48.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:48.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:48.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:23:48.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:23:48.50$vc4f8/va=5,6 2006.147.08:23:48.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.08:23:48.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.08:23:48.50#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:48.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:48.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:48.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:48.58#ibcon#[25=AT05-06\r\n] 2006.147.08:23:48.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:48.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:48.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.08:23:48.61#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:48.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:48.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:48.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:48.75#ibcon#[25=USB\r\n] 2006.147.08:23:48.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:48.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:48.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:23:48.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:23:48.78$vc4f8/valo=6,772.99 2006.147.08:23:48.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:23:48.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:23:48.78#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:48.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:48.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:48.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:48.80#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:23:48.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:48.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:48.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:23:48.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:23:48.84$vc4f8/va=6,5 2006.147.08:23:48.84#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.147.08:23:48.84#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.147.08:23:48.84#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:48.84#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:48.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:48.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:48.92#ibcon#[25=AT06-05\r\n] 2006.147.08:23:48.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:48.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:48.95#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.147.08:23:48.95#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:48.95#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:23:49.07#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:23:49.07#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:23:49.09#ibcon#[25=USB\r\n] 2006.147.08:23:49.12#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:23:49.12#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.147.08:23:49.12#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:23:49.12#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:23:49.12$vc4f8/valo=7,832.99 2006.147.08:23:49.12#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.147.08:23:49.12#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.147.08:23:49.12#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:49.12#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:23:49.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:23:49.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:23:49.14#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:23:49.21#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:23:49.21#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.147.08:23:49.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:23:49.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:23:49.21$vc4f8/va=7,5 2006.147.08:23:49.21#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.147.08:23:49.21#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.147.08:23:49.21#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:49.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:23:49.23#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:23:49.23#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:23:49.25#ibcon#[25=AT07-05\r\n] 2006.147.08:23:49.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:23:49.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.147.08:23:49.28#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.147.08:23:49.28#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:49.28#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:23:49.40#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:23:49.40#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:23:49.42#ibcon#[25=USB\r\n] 2006.147.08:23:49.45#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:23:49.45#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.147.08:23:49.45#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:23:49.45#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:23:49.45$vc4f8/valo=8,852.99 2006.147.08:23:49.45#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:23:49.45#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:23:49.45#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:49.45#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:23:49.45#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:23:49.45#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:23:49.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:23:49.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:23:49.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:23:49.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:23:49.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:23:49.51$vc4f8/va=8,5 2006.147.08:23:49.51#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.147.08:23:49.51#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.147.08:23:49.51#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:49.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:23:49.57#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:23:49.57#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:23:49.59#ibcon#[25=AT08-05\r\n] 2006.147.08:23:49.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:23:49.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.147.08:23:49.62#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.147.08:23:49.62#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:49.62#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:23:49.74#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:23:49.74#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:23:49.76#ibcon#[25=USB\r\n] 2006.147.08:23:49.79#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:23:49.79#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.147.08:23:49.79#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:23:49.79#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:23:49.79$vc4f8/vblo=1,632.99 2006.147.08:23:49.79#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.147.08:23:49.79#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.147.08:23:49.79#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:49.79#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:23:49.79#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:23:49.79#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:23:49.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:23:49.85#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:23:49.85#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.147.08:23:49.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:23:49.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:23:49.85$vc4f8/vb=1,4 2006.147.08:23:49.85#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.147.08:23:49.85#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.147.08:23:49.85#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:49.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:23:49.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:23:49.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:23:49.87#ibcon#[27=AT01-04\r\n] 2006.147.08:23:49.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:23:49.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.147.08:23:49.90#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.147.08:23:49.90#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:49.90#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:23:50.02#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:23:50.02#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:23:50.04#ibcon#[27=USB\r\n] 2006.147.08:23:50.07#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:23:50.07#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.147.08:23:50.07#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:23:50.07#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:23:50.07$vc4f8/vblo=2,640.99 2006.147.08:23:50.07#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.147.08:23:50.07#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.147.08:23:50.07#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:50.07#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:50.07#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:50.07#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:50.09#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:23:50.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:50.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.147.08:23:50.13#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:23:50.13#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:23:50.13$vc4f8/vb=2,4 2006.147.08:23:50.13#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.147.08:23:50.13#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.147.08:23:50.13#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:50.13#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:50.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:50.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:50.21#ibcon#[27=AT02-04\r\n] 2006.147.08:23:50.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:50.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.147.08:23:50.24#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.147.08:23:50.24#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:50.24#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:50.36#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:50.36#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:50.38#ibcon#[27=USB\r\n] 2006.147.08:23:50.41#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:50.41#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.147.08:23:50.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:23:50.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:23:50.41$vc4f8/vblo=3,656.99 2006.147.08:23:50.41#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.147.08:23:50.41#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.147.08:23:50.41#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:50.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:50.41#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:50.41#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:50.43#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:23:50.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:50.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.147.08:23:50.47#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:23:50.47#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:23:50.47$vc4f8/vb=3,4 2006.147.08:23:50.47#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.147.08:23:50.47#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.147.08:23:50.47#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:50.47#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:50.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:50.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:50.55#ibcon#[27=AT03-04\r\n] 2006.147.08:23:50.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:50.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.147.08:23:50.58#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.147.08:23:50.58#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:50.58#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:50.72#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:50.72#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:50.73#ibcon#[27=USB\r\n] 2006.147.08:23:50.76#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:50.76#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.147.08:23:50.76#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:23:50.76#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:23:50.76$vc4f8/vblo=4,712.99 2006.147.08:23:50.76#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.147.08:23:50.76#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.147.08:23:50.76#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:50.76#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:50.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:50.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:50.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:23:50.82#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:50.82#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.147.08:23:50.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:23:50.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:23:50.82$vc4f8/vb=4,4 2006.147.08:23:50.82#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.147.08:23:50.82#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.147.08:23:50.82#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:50.82#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:50.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:50.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:50.90#ibcon#[27=AT04-04\r\n] 2006.147.08:23:50.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:50.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.147.08:23:50.93#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.147.08:23:50.93#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:50.93#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:51.05#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:51.05#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:51.07#ibcon#[27=USB\r\n] 2006.147.08:23:51.10#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:51.10#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.147.08:23:51.10#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:23:51.10#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:23:51.10$vc4f8/vblo=5,744.99 2006.147.08:23:51.10#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.147.08:23:51.10#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.147.08:23:51.10#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:51.10#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:51.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:51.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:51.12#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:23:51.16#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:51.16#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.147.08:23:51.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:23:51.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:23:51.16$vc4f8/vb=5,3 2006.147.08:23:51.16#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.147.08:23:51.16#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.147.08:23:51.16#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:51.16#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:51.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:51.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:51.24#ibcon#[27=AT05-03\r\n] 2006.147.08:23:51.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:51.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.147.08:23:51.27#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.147.08:23:51.27#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:51.27#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:51.39#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:51.39#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:51.41#ibcon#[27=USB\r\n] 2006.147.08:23:51.44#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:51.44#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.147.08:23:51.44#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:23:51.44#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:23:51.44$vc4f8/vblo=6,752.99 2006.147.08:23:51.44#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.147.08:23:51.44#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.147.08:23:51.44#ibcon#ireg 17 cls_cnt 0 2006.147.08:23:51.44#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:51.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:51.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:51.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:23:51.50#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:51.50#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.147.08:23:51.50#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:23:51.50#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:23:51.50$vc4f8/vb=6,4 2006.147.08:23:51.50#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.147.08:23:51.50#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.147.08:23:51.50#ibcon#ireg 11 cls_cnt 2 2006.147.08:23:51.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:51.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:51.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:51.58#ibcon#[27=AT06-04\r\n] 2006.147.08:23:51.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:51.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.147.08:23:51.61#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.147.08:23:51.61#ibcon#ireg 7 cls_cnt 0 2006.147.08:23:51.61#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:51.73#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:51.73#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:51.75#ibcon#[27=USB\r\n] 2006.147.08:23:51.78#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:51.78#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.147.08:23:51.78#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:23:51.78#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:23:51.78$vc4f8/vabw=wide 2006.147.08:23:51.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.147.08:23:51.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.147.08:23:51.78#ibcon#ireg 8 cls_cnt 0 2006.147.08:23:51.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:51.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:51.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:51.80#ibcon#[25=BW32\r\n] 2006.147.08:23:51.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:51.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.147.08:23:51.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:23:51.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:23:51.83$vc4f8/vbbw=wide 2006.147.08:23:51.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:23:51.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:23:51.83#ibcon#ireg 8 cls_cnt 0 2006.147.08:23:51.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:23:51.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:23:51.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:23:51.92#ibcon#[27=BW32\r\n] 2006.147.08:23:51.95#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:23:51.95#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:23:51.95#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:23:51.95#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:23:51.95$4f8m12a/ifd4f 2006.147.08:23:51.95$ifd4f/lo= 2006.147.08:23:51.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:23:51.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:23:51.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:23:51.95$ifd4f/patch= 2006.147.08:23:51.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:23:51.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:23:51.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:23:51.95$4f8m12a/"form=m,16.000,1:2 2006.147.08:23:51.95$4f8m12a/"tpicd 2006.147.08:23:51.95$4f8m12a/echo=off 2006.147.08:23:51.95$4f8m12a/xlog=off 2006.147.08:23:51.95:!2006.147.08:24:50 2006.147.08:24:22.13#trakl#Source acquired 2006.147.08:24:22.13#flagr#flagr/antenna,acquired 2006.147.08:24:50.00:preob 2006.147.08:24:50.14/onsource/TRACKING 2006.147.08:24:50.14:!2006.147.08:25:00 2006.147.08:25:00.00:data_valid=on 2006.147.08:25:00.00:midob 2006.147.08:25:01.14/onsource/TRACKING 2006.147.08:25:01.14/wx/18.59,1011.4,95 2006.147.08:25:01.32/cable/+6.5402E-03 2006.147.08:25:02.41/va/01,08,usb,yes,39,41 2006.147.08:25:02.41/va/02,07,usb,yes,39,41 2006.147.08:25:02.41/va/03,08,usb,yes,29,30 2006.147.08:25:02.41/va/04,07,usb,yes,40,43 2006.147.08:25:02.41/va/05,06,usb,yes,46,49 2006.147.08:25:02.41/va/06,05,usb,yes,47,46 2006.147.08:25:02.41/va/07,05,usb,yes,47,46 2006.147.08:25:02.41/va/08,05,usb,yes,50,49 2006.147.08:25:02.64/valo/01,532.99,yes,locked 2006.147.08:25:02.64/valo/02,572.99,yes,locked 2006.147.08:25:02.64/valo/03,672.99,yes,locked 2006.147.08:25:02.64/valo/04,832.99,yes,locked 2006.147.08:25:02.64/valo/05,652.99,yes,locked 2006.147.08:25:02.64/valo/06,772.99,yes,locked 2006.147.08:25:02.64/valo/07,832.99,yes,locked 2006.147.08:25:02.64/valo/08,852.99,yes,locked 2006.147.08:25:03.73/vb/01,04,usb,yes,36,53 2006.147.08:25:03.73/vb/02,04,usb,yes,33,58 2006.147.08:25:03.73/vb/03,04,usb,yes,29,33 2006.147.08:25:03.73/vb/04,04,usb,yes,30,30 2006.147.08:25:03.73/vb/05,03,usb,yes,36,41 2006.147.08:25:03.73/vb/06,04,usb,yes,30,33 2006.147.08:25:03.73/vb/07,04,usb,yes,32,32 2006.147.08:25:03.73/vb/08,03,usb,yes,36,40 2006.147.08:25:03.97/vblo/01,632.99,yes,locked 2006.147.08:25:03.97/vblo/02,640.99,yes,locked 2006.147.08:25:03.97/vblo/03,656.99,yes,locked 2006.147.08:25:03.97/vblo/04,712.99,yes,locked 2006.147.08:25:03.97/vblo/05,744.99,yes,locked 2006.147.08:25:03.97/vblo/06,752.99,yes,locked 2006.147.08:25:03.97/vblo/07,734.99,yes,locked 2006.147.08:25:03.97/vblo/08,744.99,yes,locked 2006.147.08:25:04.12/vabw/8 2006.147.08:25:04.27/vbbw/8 2006.147.08:25:04.36/xfe/off,on,14.0 2006.147.08:25:04.75/ifatt/23,28,28,28 2006.147.08:25:05.07/fmout-gps/S +4.86E-07 2006.147.08:25:05.11:!2006.147.08:26:00 2006.147.08:26:00.00:data_valid=off 2006.147.08:26:00.01:postob 2006.147.08:26:00.09/cable/+6.5376E-03 2006.147.08:26:00.10/wx/18.58,1011.4,94 2006.147.08:26:01.07/fmout-gps/S +4.85E-07 2006.147.08:26:01.08:scan_name=147-0828,k06147,60 2006.147.08:26:01.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.147.08:26:01.14#flagr#flagr/antenna,new-source 2006.147.08:26:02.14:checkk5 2006.147.08:26:02.53/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:26:02.92/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:26:03.31/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:26:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:26:04.06/chk_obsdata//k5ts1/k06147_ts1_147-0825*_20??1470825??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:26:04.45/chk_obsdata//k5ts2/k06147_ts2_147-0825*_20??1470825??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:26:04.83/chk_obsdata//k5ts3/k06147_ts3_147-0825*_20??1470825??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:26:05.21/chk_obsdata//k5ts4/k06147_ts4_147-0825*_20??1470825??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:26:05.90/k5log//k5ts1_log_newline 2006.147.08:26:06.59/k5log//k5ts2_log_newline 2006.147.08:26:07.29/k5log//k5ts3_log_newline 2006.147.08:26:07.98/k5log//k5ts4_log_newline 2006.147.08:26:08.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:26:08.00:4f8m12a=3 2006.147.08:26:08.00$4f8m12a/echo=on 2006.147.08:26:08.00$4f8m12a/pcalon 2006.147.08:26:08.00$pcalon/"no phase cal control is implemented here 2006.147.08:26:08.00$4f8m12a/"tpicd=stop 2006.147.08:26:08.00$4f8m12a/vc4f8 2006.147.08:26:08.00$vc4f8/valo=1,532.99 2006.147.08:26:08.01#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.08:26:08.01#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.08:26:08.01#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:08.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:08.01#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:08.01#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:08.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:26:08.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:08.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:08.10#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:26:08.10#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:26:08.10$vc4f8/va=1,8 2006.147.08:26:08.10#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.08:26:08.10#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.08:26:08.10#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:08.10#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:08.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:08.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:08.14#ibcon#[25=AT01-08\r\n] 2006.147.08:26:08.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:08.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:08.17#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.08:26:08.17#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:08.17#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:08.29#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:08.29#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:08.31#ibcon#[25=USB\r\n] 2006.147.08:26:08.37#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:08.37#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:08.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:26:08.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:26:08.37$vc4f8/valo=2,572.99 2006.147.08:26:08.37#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:26:08.37#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:26:08.37#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:08.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:08.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:08.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:08.38#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:26:08.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:08.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:08.42#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:26:08.42#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:26:08.42$vc4f8/va=2,7 2006.147.08:26:08.42#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:26:08.42#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:26:08.42#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:08.42#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:08.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:08.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:08.51#ibcon#[25=AT02-07\r\n] 2006.147.08:26:08.55#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:08.55#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:08.55#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:26:08.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:08.55#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:08.66#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:08.66#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:08.68#ibcon#[25=USB\r\n] 2006.147.08:26:08.74#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:08.74#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:08.74#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:26:08.74#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:26:08.74$vc4f8/valo=3,672.99 2006.147.08:26:08.74#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:26:08.74#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:26:08.74#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:08.74#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:08.74#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:08.74#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:08.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:26:08.79#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:08.79#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:08.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:26:08.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:26:08.79$vc4f8/va=3,8 2006.147.08:26:08.79#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:26:08.79#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:26:08.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:08.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:08.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:08.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:08.88#ibcon#[25=AT03-08\r\n] 2006.147.08:26:08.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:08.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:08.91#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:26:08.91#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:08.91#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:09.03#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:09.03#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:09.05#ibcon#[25=USB\r\n] 2006.147.08:26:09.08#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:09.08#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:09.08#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:26:09.08#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:26:09.08$vc4f8/valo=4,832.99 2006.147.08:26:09.08#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:26:09.08#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:26:09.08#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:09.08#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:09.08#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:09.08#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:09.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:26:09.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:09.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:09.14#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:26:09.14#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:26:09.14$vc4f8/va=4,7 2006.147.08:26:09.14#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:26:09.14#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:26:09.14#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:09.14#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:09.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:09.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:09.22#ibcon#[25=AT04-07\r\n] 2006.147.08:26:09.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:09.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:09.25#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:26:09.25#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:09.25#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:09.26#abcon#<5=/06 2.1 4.3 18.57 941011.4\r\n> 2006.147.08:26:09.28#abcon#{5=INTERFACE CLEAR} 2006.147.08:26:09.34#abcon#[5=S1D000X0/0*\r\n] 2006.147.08:26:09.37#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:09.37#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:09.39#ibcon#[25=USB\r\n] 2006.147.08:26:09.44#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:09.44#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:09.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:26:09.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:26:09.44$vc4f8/valo=5,652.99 2006.147.08:26:09.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:26:09.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:26:09.44#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:09.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:09.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:09.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:09.46#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:26:09.52#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:09.52#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:09.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:26:09.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:26:09.52$vc4f8/va=5,6 2006.147.08:26:09.52#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.08:26:09.52#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.08:26:09.52#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:09.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:09.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:09.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:09.57#ibcon#[25=AT05-06\r\n] 2006.147.08:26:09.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:09.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:09.60#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.08:26:09.60#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:09.60#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:09.72#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:09.72#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:09.74#ibcon#[25=USB\r\n] 2006.147.08:26:09.77#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:09.77#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:09.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:26:09.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:26:09.77$vc4f8/valo=6,772.99 2006.147.08:26:09.77#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.08:26:09.77#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.08:26:09.77#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:09.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:09.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:09.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:09.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:26:09.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:09.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:09.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:26:09.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:26:09.83$vc4f8/va=6,5 2006.147.08:26:09.83#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.147.08:26:09.83#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.147.08:26:09.83#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:09.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:09.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:09.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:09.91#ibcon#[25=AT06-05\r\n] 2006.147.08:26:09.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:09.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:09.94#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.147.08:26:09.94#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:09.94#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:26:10.06#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:26:10.06#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:26:10.08#ibcon#[25=USB\r\n] 2006.147.08:26:10.11#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:26:10.11#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.147.08:26:10.11#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:26:10.11#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:26:10.11$vc4f8/valo=7,832.99 2006.147.08:26:10.11#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.147.08:26:10.11#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.147.08:26:10.11#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:10.11#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:26:10.11#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:26:10.11#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:26:10.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:26:10.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:26:10.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.147.08:26:10.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.147.08:26:10.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.147.08:26:10.17$vc4f8/va=7,5 2006.147.08:26:10.17#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.147.08:26:10.17#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.147.08:26:10.17#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:10.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:26:10.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:26:10.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:26:10.25#ibcon#[25=AT07-05\r\n] 2006.147.08:26:10.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:26:10.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.147.08:26:10.28#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.147.08:26:10.28#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:10.28#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:26:10.40#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:26:10.40#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:26:10.42#ibcon#[25=USB\r\n] 2006.147.08:26:10.45#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:26:10.45#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.147.08:26:10.45#ibcon#about to clear, iclass 19 cls_cnt 0 2006.147.08:26:10.45#ibcon#cleared, iclass 19 cls_cnt 0 2006.147.08:26:10.45$vc4f8/valo=8,852.99 2006.147.08:26:10.45#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.147.08:26:10.45#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.147.08:26:10.45#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:10.45#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:26:10.45#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:26:10.45#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:26:10.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:26:10.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:26:10.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.147.08:26:10.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.147.08:26:10.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.147.08:26:10.51$vc4f8/va=8,5 2006.147.08:26:10.51#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.147.08:26:10.51#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.147.08:26:10.51#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:10.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:26:10.57#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:26:10.57#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:26:10.59#ibcon#[25=AT08-05\r\n] 2006.147.08:26:10.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:26:10.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.147.08:26:10.62#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.147.08:26:10.62#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:10.62#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:26:10.74#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:26:10.74#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:26:10.76#ibcon#[25=USB\r\n] 2006.147.08:26:10.79#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:26:10.79#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.147.08:26:10.79#ibcon#about to clear, iclass 23 cls_cnt 0 2006.147.08:26:10.79#ibcon#cleared, iclass 23 cls_cnt 0 2006.147.08:26:10.79$vc4f8/vblo=1,632.99 2006.147.08:26:10.79#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.147.08:26:10.79#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.147.08:26:10.79#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:10.79#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:10.79#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:10.79#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:10.81#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:26:10.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:10.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.147.08:26:10.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.147.08:26:10.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.147.08:26:10.87$vc4f8/vb=1,4 2006.147.08:26:10.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.147.08:26:10.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.147.08:26:10.87#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:10.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:10.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:10.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:10.89#ibcon#[27=AT01-04\r\n] 2006.147.08:26:10.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:10.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.147.08:26:10.92#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.147.08:26:10.92#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:10.92#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:11.04#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:11.04#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:11.06#ibcon#[27=USB\r\n] 2006.147.08:26:11.09#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:11.09#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.147.08:26:11.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.147.08:26:11.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.147.08:26:11.09$vc4f8/vblo=2,640.99 2006.147.08:26:11.09#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.147.08:26:11.09#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.147.08:26:11.09#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:11.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:11.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:11.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:11.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:26:11.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:11.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.147.08:26:11.15#ibcon#about to clear, iclass 29 cls_cnt 0 2006.147.08:26:11.15#ibcon#cleared, iclass 29 cls_cnt 0 2006.147.08:26:11.15$vc4f8/vb=2,4 2006.147.08:26:11.15#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.147.08:26:11.15#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.147.08:26:11.15#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:11.15#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:11.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:11.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:11.23#ibcon#[27=AT02-04\r\n] 2006.147.08:26:11.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:11.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.147.08:26:11.26#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.147.08:26:11.26#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:11.26#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:11.38#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:11.38#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:11.40#ibcon#[27=USB\r\n] 2006.147.08:26:11.43#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:11.43#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.147.08:26:11.43#ibcon#about to clear, iclass 31 cls_cnt 0 2006.147.08:26:11.43#ibcon#cleared, iclass 31 cls_cnt 0 2006.147.08:26:11.43$vc4f8/vblo=3,656.99 2006.147.08:26:11.43#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.147.08:26:11.43#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.147.08:26:11.43#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:11.43#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:11.43#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:11.43#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:11.45#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:26:11.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:11.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.147.08:26:11.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.147.08:26:11.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.147.08:26:11.50$vc4f8/vb=3,4 2006.147.08:26:11.50#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.147.08:26:11.50#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.147.08:26:11.50#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:11.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:11.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:11.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:11.56#ibcon#[27=AT03-04\r\n] 2006.147.08:26:11.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:11.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.147.08:26:11.59#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.147.08:26:11.59#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:11.59#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:11.71#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:11.71#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:11.73#ibcon#[27=USB\r\n] 2006.147.08:26:11.76#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:11.76#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.147.08:26:11.76#ibcon#about to clear, iclass 35 cls_cnt 0 2006.147.08:26:11.76#ibcon#cleared, iclass 35 cls_cnt 0 2006.147.08:26:11.76$vc4f8/vblo=4,712.99 2006.147.08:26:11.76#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.147.08:26:11.76#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.147.08:26:11.76#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:11.76#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:11.76#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:11.76#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:11.78#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:26:11.82#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:11.82#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.147.08:26:11.82#ibcon#about to clear, iclass 37 cls_cnt 0 2006.147.08:26:11.82#ibcon#cleared, iclass 37 cls_cnt 0 2006.147.08:26:11.82$vc4f8/vb=4,4 2006.147.08:26:11.82#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.147.08:26:11.82#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.147.08:26:11.82#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:11.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:11.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:11.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:11.90#ibcon#[27=AT04-04\r\n] 2006.147.08:26:11.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:11.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.147.08:26:11.93#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.147.08:26:11.93#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:11.93#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:12.05#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:12.05#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:12.07#ibcon#[27=USB\r\n] 2006.147.08:26:12.10#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:12.10#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.147.08:26:12.10#ibcon#about to clear, iclass 39 cls_cnt 0 2006.147.08:26:12.10#ibcon#cleared, iclass 39 cls_cnt 0 2006.147.08:26:12.10$vc4f8/vblo=5,744.99 2006.147.08:26:12.10#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.147.08:26:12.10#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.147.08:26:12.10#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:12.10#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:26:12.10#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:26:12.10#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:26:12.14#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:26:12.18#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:26:12.18#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.147.08:26:12.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.147.08:26:12.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.147.08:26:12.18$vc4f8/vb=5,3 2006.147.08:26:12.18#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.147.08:26:12.18#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.147.08:26:12.18#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:12.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:26:12.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:26:12.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:26:12.24#ibcon#[27=AT05-03\r\n] 2006.147.08:26:12.27#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:26:12.27#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.147.08:26:12.27#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.147.08:26:12.27#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:12.27#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:26:12.39#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:26:12.39#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:26:12.41#ibcon#[27=USB\r\n] 2006.147.08:26:12.44#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:26:12.44#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.147.08:26:12.44#ibcon#about to clear, iclass 5 cls_cnt 0 2006.147.08:26:12.44#ibcon#cleared, iclass 5 cls_cnt 0 2006.147.08:26:12.44$vc4f8/vblo=6,752.99 2006.147.08:26:12.44#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.147.08:26:12.44#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.147.08:26:12.44#ibcon#ireg 17 cls_cnt 0 2006.147.08:26:12.44#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:12.44#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:12.44#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:12.46#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:26:12.50#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:12.50#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.147.08:26:12.50#ibcon#about to clear, iclass 7 cls_cnt 0 2006.147.08:26:12.50#ibcon#cleared, iclass 7 cls_cnt 0 2006.147.08:26:12.50$vc4f8/vb=6,4 2006.147.08:26:12.50#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.147.08:26:12.50#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.147.08:26:12.50#ibcon#ireg 11 cls_cnt 2 2006.147.08:26:12.50#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:12.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:12.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:12.58#ibcon#[27=AT06-04\r\n] 2006.147.08:26:12.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:12.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.147.08:26:12.61#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.147.08:26:12.61#ibcon#ireg 7 cls_cnt 0 2006.147.08:26:12.61#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:12.73#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:12.73#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:12.75#ibcon#[27=USB\r\n] 2006.147.08:26:12.78#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:12.78#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.147.08:26:12.78#ibcon#about to clear, iclass 11 cls_cnt 0 2006.147.08:26:12.78#ibcon#cleared, iclass 11 cls_cnt 0 2006.147.08:26:12.78$vc4f8/vabw=wide 2006.147.08:26:12.78#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.147.08:26:12.78#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.147.08:26:12.78#ibcon#ireg 8 cls_cnt 0 2006.147.08:26:12.78#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:12.78#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:12.78#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:12.80#ibcon#[25=BW32\r\n] 2006.147.08:26:12.83#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:12.83#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.147.08:26:12.83#ibcon#about to clear, iclass 13 cls_cnt 0 2006.147.08:26:12.83#ibcon#cleared, iclass 13 cls_cnt 0 2006.147.08:26:12.83$vc4f8/vbbw=wide 2006.147.08:26:12.83#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.147.08:26:12.83#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.147.08:26:12.83#ibcon#ireg 8 cls_cnt 0 2006.147.08:26:12.83#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:26:12.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:26:12.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:26:12.92#ibcon#[27=BW32\r\n] 2006.147.08:26:12.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:26:12.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.147.08:26:12.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.147.08:26:12.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.147.08:26:12.95$4f8m12a/ifd4f 2006.147.08:26:12.95$ifd4f/lo= 2006.147.08:26:12.95$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:26:12.95$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:26:12.95$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:26:12.95$ifd4f/patch= 2006.147.08:26:12.95$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:26:12.95$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:26:12.95$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:26:12.95$4f8m12a/"form=m,16.000,1:2 2006.147.08:26:12.95$4f8m12a/"tpicd 2006.147.08:26:12.95$4f8m12a/echo=off 2006.147.08:26:12.95$4f8m12a/xlog=off 2006.147.08:26:12.95:!2006.147.08:28:20 2006.147.08:26:17.14#trakl#Source acquired 2006.147.08:26:19.14#flagr#flagr/antenna,acquired 2006.147.08:28:20.00:preob 2006.147.08:28:20.14/onsource/TRACKING 2006.147.08:28:20.14:!2006.147.08:28:30 2006.147.08:28:30.00:data_valid=on 2006.147.08:28:30.00:midob 2006.147.08:28:31.14/onsource/TRACKING 2006.147.08:28:31.14/wx/18.52,1011.3,93 2006.147.08:28:31.24/cable/+6.5371E-03 2006.147.08:28:32.33/va/01,08,usb,yes,35,37 2006.147.08:28:32.33/va/02,07,usb,yes,35,37 2006.147.08:28:32.33/va/03,08,usb,yes,27,27 2006.147.08:28:32.33/va/04,07,usb,yes,36,39 2006.147.08:28:32.33/va/05,06,usb,yes,41,44 2006.147.08:28:32.33/va/06,05,usb,yes,42,42 2006.147.08:28:32.33/va/07,05,usb,yes,42,42 2006.147.08:28:32.33/va/08,05,usb,yes,45,44 2006.147.08:28:32.56/valo/01,532.99,yes,locked 2006.147.08:28:32.56/valo/02,572.99,yes,locked 2006.147.08:28:32.56/valo/03,672.99,yes,locked 2006.147.08:28:32.56/valo/04,832.99,yes,locked 2006.147.08:28:32.56/valo/05,652.99,yes,locked 2006.147.08:28:32.56/valo/06,772.99,yes,locked 2006.147.08:28:32.56/valo/07,832.99,yes,locked 2006.147.08:28:32.56/valo/08,852.99,yes,locked 2006.147.08:28:33.65/vb/01,04,usb,yes,30,28 2006.147.08:28:33.65/vb/02,04,usb,yes,31,33 2006.147.08:28:33.65/vb/03,04,usb,yes,28,32 2006.147.08:28:33.65/vb/04,04,usb,yes,29,29 2006.147.08:28:33.65/vb/05,03,usb,yes,34,39 2006.147.08:28:33.65/vb/06,04,usb,yes,28,31 2006.147.08:28:33.65/vb/07,04,usb,yes,30,30 2006.147.08:28:33.65/vb/08,03,usb,yes,35,39 2006.147.08:28:33.88/vblo/01,632.99,yes,locked 2006.147.08:28:33.88/vblo/02,640.99,yes,locked 2006.147.08:28:33.88/vblo/03,656.99,yes,locked 2006.147.08:28:33.88/vblo/04,712.99,yes,locked 2006.147.08:28:33.88/vblo/05,744.99,yes,locked 2006.147.08:28:33.88/vblo/06,752.99,yes,locked 2006.147.08:28:33.88/vblo/07,734.99,yes,locked 2006.147.08:28:33.88/vblo/08,744.99,yes,locked 2006.147.08:28:34.03/vabw/8 2006.147.08:28:34.18/vbbw/8 2006.147.08:28:34.27/xfe/off,on,14.5 2006.147.08:28:34.66/ifatt/23,28,28,28 2006.147.08:28:35.07/fmout-gps/S +4.87E-07 2006.147.08:28:35.11:!2006.147.08:29:30 2006.147.08:29:30.01:data_valid=off 2006.147.08:29:30.02:postob 2006.147.08:29:30.13/cable/+6.5371E-03 2006.147.08:29:30.14/wx/18.50,1011.3,93 2006.147.08:29:30.19/fmout-gps/S +4.87E-07 2006.147.08:29:30.19:scan_name=147-0830,k06147,60 2006.147.08:29:30.20:source=1803+784,180045.68,782804.0,2000.0,cw 2006.147.08:29:31.14#flagr#flagr/antenna,new-source 2006.147.08:29:31.15:checkk5 2006.147.08:29:31.52/chk_autoobs//k5ts1/ autoobs is running! 2006.147.08:29:31.90/chk_autoobs//k5ts2/ autoobs is running! 2006.147.08:29:32.30/chk_autoobs//k5ts3/ autoobs is running! 2006.147.08:29:32.67/chk_autoobs//k5ts4/ autoobs is running! 2006.147.08:29:33.06/chk_obsdata//k5ts1/k06147_ts1_147-0828*_20??1470828??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:29:33.44/chk_obsdata//k5ts2/k06147_ts2_147-0828*_20??1470828??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:29:33.82/chk_obsdata//k5ts3/k06147_ts3_147-0828*_20??1470828??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:29:34.21/chk_obsdata//k5ts4/k06147_ts4_147-0828*_20??1470828??.k5 file size is correct (nominal:480MB, actual:472MB). 2006.147.08:29:34.91/k5log//k5ts1_log_newline 2006.147.08:29:35.60/k5log//k5ts2_log_newline 2006.147.08:29:36.30/k5log//k5ts3_log_newline 2006.147.08:29:36.99/k5log//k5ts4_log_newline 2006.147.08:29:37.01/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:29:37.01:4f8m12a=3 2006.147.08:29:37.01$4f8m12a/echo=on 2006.147.08:29:37.01$4f8m12a/pcalon 2006.147.08:29:37.01$pcalon/"no phase cal control is implemented here 2006.147.08:29:37.01$4f8m12a/"tpicd=stop 2006.147.08:29:37.01$4f8m12a/vc4f8 2006.147.08:29:37.01$vc4f8/valo=1,532.99 2006.147.08:29:37.02#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:29:37.02#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:29:37.02#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:37.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:37.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:37.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:37.06#ibcon#[26=FRQ=01,532.99\r\n] 2006.147.08:29:37.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:37.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:37.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:29:37.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:29:37.11$vc4f8/va=1,8 2006.147.08:29:37.11#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:29:37.11#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:29:37.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:37.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:37.11#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:37.11#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:37.15#ibcon#[25=AT01-08\r\n] 2006.147.08:29:37.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:37.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:37.18#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:29:37.18#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:37.18#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:37.30#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:37.30#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:37.32#ibcon#[25=USB\r\n] 2006.147.08:29:37.38#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:37.38#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:37.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:29:37.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:29:37.38$vc4f8/valo=2,572.99 2006.147.08:29:37.38#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:29:37.38#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:29:37.38#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:37.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:37.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:37.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:37.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.147.08:29:37.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:37.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:37.43#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:29:37.43#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:29:37.43$vc4f8/va=2,7 2006.147.08:29:37.43#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:29:37.43#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:29:37.43#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:37.43#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:37.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:37.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:37.52#ibcon#[25=AT02-07\r\n] 2006.147.08:29:37.55#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:37.55#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:37.55#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:29:37.55#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:37.55#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:37.69#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:37.69#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:37.70#ibcon#[25=USB\r\n] 2006.147.08:29:37.73#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:37.73#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:37.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:29:37.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:29:37.73$vc4f8/valo=3,672.99 2006.147.08:29:37.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:29:37.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:29:37.73#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:37.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:37.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:37.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:37.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.147.08:29:37.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:37.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:37.79#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:29:37.79#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:29:37.79$vc4f8/va=3,8 2006.147.08:29:37.79#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:29:37.79#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:29:37.79#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:37.79#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:37.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:37.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:37.87#ibcon#[25=AT03-08\r\n] 2006.147.08:29:37.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:37.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:37.90#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:29:37.90#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:37.90#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:38.02#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:38.02#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:38.04#ibcon#[25=USB\r\n] 2006.147.08:29:38.07#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:38.07#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:38.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:29:38.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:29:38.07$vc4f8/valo=4,832.99 2006.147.08:29:38.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:29:38.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:29:38.07#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:38.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:38.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:38.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:38.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.147.08:29:38.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:38.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:38.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:29:38.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:29:38.13$vc4f8/va=4,7 2006.147.08:29:38.13#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:29:38.13#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:29:38.13#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:38.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:38.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:38.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:38.21#ibcon#[25=AT04-07\r\n] 2006.147.08:29:38.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:38.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:38.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:29:38.24#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:38.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:38.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:38.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:38.38#ibcon#[25=USB\r\n] 2006.147.08:29:38.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:38.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:38.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:29:38.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:29:38.41$vc4f8/valo=5,652.99 2006.147.08:29:38.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:29:38.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:29:38.41#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:38.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:38.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:38.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:38.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.147.08:29:38.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:38.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:38.47#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:29:38.47#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:29:38.47$vc4f8/va=5,6 2006.147.08:29:38.47#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:29:38.47#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:29:38.47#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:38.47#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:38.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:38.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:38.55#ibcon#[25=AT05-06\r\n] 2006.147.08:29:38.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:38.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:38.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:29:38.58#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:38.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:38.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:38.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:38.72#ibcon#[25=USB\r\n] 2006.147.08:29:38.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:38.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:38.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:29:38.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:29:38.75$vc4f8/valo=6,772.99 2006.147.08:29:38.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:29:38.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:29:38.75#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:38.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:38.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:38.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:38.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.147.08:29:38.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:38.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:38.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:29:38.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:29:38.81$vc4f8/va=6,5 2006.147.08:29:38.81#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.147.08:29:38.81#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.147.08:29:38.81#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:38.81#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:38.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:38.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:38.89#ibcon#[25=AT06-05\r\n] 2006.147.08:29:38.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:38.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:38.92#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.147.08:29:38.92#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:38.92#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:29:39.04#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:29:39.04#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:29:39.06#ibcon#[25=USB\r\n] 2006.147.08:29:39.09#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:29:39.09#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.147.08:29:39.09#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:29:39.09#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:29:39.09$vc4f8/valo=7,832.99 2006.147.08:29:39.09#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.147.08:29:39.09#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.147.08:29:39.09#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:39.09#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:29:39.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:29:39.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:29:39.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.147.08:29:39.15#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:29:39.15#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.147.08:29:39.15#ibcon#about to clear, iclass 14 cls_cnt 0 2006.147.08:29:39.15#ibcon#cleared, iclass 14 cls_cnt 0 2006.147.08:29:39.15$vc4f8/va=7,5 2006.147.08:29:39.15#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.147.08:29:39.15#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.147.08:29:39.15#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:39.15#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:29:39.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:29:39.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:29:39.23#ibcon#[25=AT07-05\r\n] 2006.147.08:29:39.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:29:39.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.147.08:29:39.26#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.147.08:29:39.26#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:39.26#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:29:39.38#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:29:39.38#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:29:39.40#ibcon#[25=USB\r\n] 2006.147.08:29:39.43#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:29:39.43#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.147.08:29:39.43#ibcon#about to clear, iclass 16 cls_cnt 0 2006.147.08:29:39.43#ibcon#cleared, iclass 16 cls_cnt 0 2006.147.08:29:39.43$vc4f8/valo=8,852.99 2006.147.08:29:39.43#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.147.08:29:39.43#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.147.08:29:39.43#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:39.43#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:29:39.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:29:39.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:29:39.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.147.08:29:39.49#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:29:39.49#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.147.08:29:39.49#ibcon#about to clear, iclass 18 cls_cnt 0 2006.147.08:29:39.49#ibcon#cleared, iclass 18 cls_cnt 0 2006.147.08:29:39.49$vc4f8/va=8,5 2006.147.08:29:39.49#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.147.08:29:39.49#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.147.08:29:39.49#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:39.49#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:29:39.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:29:39.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:29:39.57#ibcon#[25=AT08-05\r\n] 2006.147.08:29:39.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:29:39.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.147.08:29:39.60#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.147.08:29:39.60#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:39.60#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:29:39.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:29:39.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:29:39.74#ibcon#[25=USB\r\n] 2006.147.08:29:39.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:29:39.77#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.147.08:29:39.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.147.08:29:39.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.147.08:29:39.77$vc4f8/vblo=1,632.99 2006.147.08:29:39.77#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.147.08:29:39.77#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.147.08:29:39.77#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:39.77#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:29:39.77#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:29:39.77#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:29:39.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.147.08:29:39.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:29:39.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.147.08:29:39.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.147.08:29:39.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.147.08:29:39.83$vc4f8/vb=1,4 2006.147.08:29:39.83#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.147.08:29:39.83#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.147.08:29:39.83#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:39.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:29:39.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:29:39.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:29:39.85#ibcon#[27=AT01-04\r\n] 2006.147.08:29:39.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:29:39.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.147.08:29:39.88#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.147.08:29:39.88#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:39.88#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:29:40.00#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:29:40.00#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:29:40.02#ibcon#[27=USB\r\n] 2006.147.08:29:40.05#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:29:40.05#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.147.08:29:40.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.147.08:29:40.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.147.08:29:40.05$vc4f8/vblo=2,640.99 2006.147.08:29:40.05#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.147.08:29:40.05#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.147.08:29:40.05#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:40.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:40.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:40.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:40.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.147.08:29:40.11#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:40.11#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.147.08:29:40.11#ibcon#about to clear, iclass 26 cls_cnt 0 2006.147.08:29:40.11#ibcon#cleared, iclass 26 cls_cnt 0 2006.147.08:29:40.11$vc4f8/vb=2,4 2006.147.08:29:40.11#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.147.08:29:40.11#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.147.08:29:40.11#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:40.11#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:40.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:40.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:40.19#ibcon#[27=AT02-04\r\n] 2006.147.08:29:40.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:40.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.147.08:29:40.22#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.147.08:29:40.22#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:40.22#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:40.34#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:40.34#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:40.36#ibcon#[27=USB\r\n] 2006.147.08:29:40.39#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:40.39#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.147.08:29:40.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.147.08:29:40.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.147.08:29:40.39$vc4f8/vblo=3,656.99 2006.147.08:29:40.39#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.147.08:29:40.39#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.147.08:29:40.39#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:40.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:40.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:40.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:40.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.147.08:29:40.45#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:40.45#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.147.08:29:40.45#ibcon#about to clear, iclass 30 cls_cnt 0 2006.147.08:29:40.45#ibcon#cleared, iclass 30 cls_cnt 0 2006.147.08:29:40.45$vc4f8/vb=3,4 2006.147.08:29:40.45#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.147.08:29:40.45#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.147.08:29:40.45#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:40.45#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:40.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:40.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:40.53#ibcon#[27=AT03-04\r\n] 2006.147.08:29:40.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:40.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.147.08:29:40.56#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.147.08:29:40.56#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:40.56#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:40.68#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:40.68#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:40.70#ibcon#[27=USB\r\n] 2006.147.08:29:40.73#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:40.73#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.147.08:29:40.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.147.08:29:40.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.147.08:29:40.73$vc4f8/vblo=4,712.99 2006.147.08:29:40.73#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.147.08:29:40.73#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.147.08:29:40.73#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:40.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:40.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:40.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:40.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.147.08:29:40.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:40.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.147.08:29:40.81#ibcon#about to clear, iclass 34 cls_cnt 0 2006.147.08:29:40.81#ibcon#cleared, iclass 34 cls_cnt 0 2006.147.08:29:40.81$vc4f8/vb=4,4 2006.147.08:29:40.81#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.147.08:29:40.81#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.147.08:29:40.81#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:40.81#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:40.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:40.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:40.87#ibcon#[27=AT04-04\r\n] 2006.147.08:29:40.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:40.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.147.08:29:40.90#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.147.08:29:40.90#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:40.90#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:41.02#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:41.02#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:41.04#ibcon#[27=USB\r\n] 2006.147.08:29:41.07#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:41.07#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.147.08:29:41.07#ibcon#about to clear, iclass 36 cls_cnt 0 2006.147.08:29:41.07#ibcon#cleared, iclass 36 cls_cnt 0 2006.147.08:29:41.07$vc4f8/vblo=5,744.99 2006.147.08:29:41.07#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.147.08:29:41.07#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.147.08:29:41.07#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:41.07#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:41.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:41.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:41.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.147.08:29:41.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:41.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.147.08:29:41.13#ibcon#about to clear, iclass 38 cls_cnt 0 2006.147.08:29:41.13#ibcon#cleared, iclass 38 cls_cnt 0 2006.147.08:29:41.13$vc4f8/vb=5,3 2006.147.08:29:41.13#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.147.08:29:41.13#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.147.08:29:41.13#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:41.13#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:41.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:41.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:41.21#ibcon#[27=AT05-03\r\n] 2006.147.08:29:41.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:41.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.147.08:29:41.24#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.147.08:29:41.24#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:41.24#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:41.36#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:41.36#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:41.38#ibcon#[27=USB\r\n] 2006.147.08:29:41.41#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:41.41#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.147.08:29:41.41#ibcon#about to clear, iclass 40 cls_cnt 0 2006.147.08:29:41.41#ibcon#cleared, iclass 40 cls_cnt 0 2006.147.08:29:41.41$vc4f8/vblo=6,752.99 2006.147.08:29:41.41#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.147.08:29:41.41#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.147.08:29:41.41#ibcon#ireg 17 cls_cnt 0 2006.147.08:29:41.41#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:41.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:41.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:41.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.147.08:29:41.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:41.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.147.08:29:41.49#ibcon#about to clear, iclass 4 cls_cnt 0 2006.147.08:29:41.49#ibcon#cleared, iclass 4 cls_cnt 0 2006.147.08:29:41.49$vc4f8/vb=6,4 2006.147.08:29:41.49#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.147.08:29:41.49#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.147.08:29:41.49#ibcon#ireg 11 cls_cnt 2 2006.147.08:29:41.49#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:41.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:41.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:41.55#ibcon#[27=AT06-04\r\n] 2006.147.08:29:41.58#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:41.58#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.147.08:29:41.58#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.147.08:29:41.58#ibcon#ireg 7 cls_cnt 0 2006.147.08:29:41.58#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:41.70#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:41.70#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:41.72#ibcon#[27=USB\r\n] 2006.147.08:29:41.75#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:41.75#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.147.08:29:41.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.147.08:29:41.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.147.08:29:41.75$vc4f8/vabw=wide 2006.147.08:29:41.75#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.147.08:29:41.75#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.147.08:29:41.75#ibcon#ireg 8 cls_cnt 0 2006.147.08:29:41.75#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:41.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:41.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:41.77#ibcon#[25=BW32\r\n] 2006.147.08:29:41.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:41.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.147.08:29:41.80#ibcon#about to clear, iclass 10 cls_cnt 0 2006.147.08:29:41.80#ibcon#cleared, iclass 10 cls_cnt 0 2006.147.08:29:41.80$vc4f8/vbbw=wide 2006.147.08:29:41.80#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.147.08:29:41.80#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.147.08:29:41.80#ibcon#ireg 8 cls_cnt 0 2006.147.08:29:41.80#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:29:41.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:29:41.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:29:41.89#ibcon#[27=BW32\r\n] 2006.147.08:29:41.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:29:41.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.147.08:29:41.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.147.08:29:41.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.147.08:29:41.92$4f8m12a/ifd4f 2006.147.08:29:41.92$ifd4f/lo= 2006.147.08:29:41.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.147.08:29:41.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.147.08:29:41.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.147.08:29:41.92$ifd4f/patch= 2006.147.08:29:41.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.147.08:29:41.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.147.08:29:41.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.147.08:29:41.92$4f8m12a/"form=m,16.000,1:2 2006.147.08:29:41.92$4f8m12a/"tpicd 2006.147.08:29:41.92$4f8m12a/echo=off 2006.147.08:29:41.92$4f8m12a/xlog=off 2006.147.08:29:41.92:!2006.147.08:30:10 2006.147.08:29:44.14#trakl#Source acquired 2006.147.08:29:45.14#flagr#flagr/antenna,acquired 2006.147.08:30:10.00:preob 2006.147.08:30:10.14/onsource/TRACKING 2006.147.08:30:10.14:!2006.147.08:30:20 2006.147.08:30:20.00:data_valid=on 2006.147.08:30:20.00:midob 2006.147.08:30:21.14/onsource/TRACKING 2006.147.08:30:21.14/wx/18.49,1011.3,93 2006.147.08:30:21.25/cable/+6.5382E-03 2006.147.08:30:22.34/va/01,08,usb,yes,34,36 2006.147.08:30:22.34/va/02,07,usb,yes,35,36 2006.147.08:30:22.34/va/03,08,usb,yes,26,26 2006.147.08:30:22.34/va/04,07,usb,yes,35,38 2006.147.08:30:22.34/va/05,06,usb,yes,40,43 2006.147.08:30:22.34/va/06,05,usb,yes,41,41 2006.147.08:30:22.34/va/07,05,usb,yes,41,41 2006.147.08:30:22.34/va/08,05,usb,yes,44,43 2006.147.08:30:22.57/valo/01,532.99,yes,locked 2006.147.08:30:22.57/valo/02,572.99,yes,locked 2006.147.08:30:22.57/valo/03,672.99,yes,locked 2006.147.08:30:22.57/valo/04,832.99,yes,locked 2006.147.08:30:22.57/valo/05,652.99,yes,locked 2006.147.08:30:22.57/valo/06,772.99,yes,locked 2006.147.08:30:22.57/valo/07,832.99,yes,locked 2006.147.08:30:22.57/valo/08,852.99,yes,locked 2006.147.08:30:23.66/vb/01,04,usb,yes,29,28 2006.147.08:30:23.66/vb/02,04,usb,yes,31,32 2006.147.08:30:23.66/vb/03,04,usb,yes,27,31 2006.147.08:30:23.66/vb/04,04,usb,yes,28,28 2006.147.08:30:23.66/vb/05,03,usb,yes,34,38 2006.147.08:30:23.66/vb/06,04,usb,yes,28,31 2006.147.08:30:23.66/vb/07,04,usb,yes,30,30 2006.147.08:30:23.66/vb/08,03,usb,yes,34,38 2006.147.08:30:23.90/vblo/01,632.99,yes,locked 2006.147.08:30:23.90/vblo/02,640.99,yes,locked 2006.147.08:30:23.90/vblo/03,656.99,yes,locked 2006.147.08:30:23.90/vblo/04,712.99,yes,locked 2006.147.08:30:23.90/vblo/05,744.99,yes,locked 2006.147.08:30:23.90/vblo/06,752.99,yes,locked 2006.147.08:30:23.90/vblo/07,734.99,yes,locked 2006.147.08:30:23.90/vblo/08,744.99,yes,locked 2006.147.08:30:24.05/vabw/8 2006.147.08:30:24.20/vbbw/8 2006.147.08:30:24.29/xfe/off,on,15.0 2006.147.08:30:24.66/ifatt/23,28,28,28 2006.147.08:30:25.07/fmout-gps/S +4.88E-07 2006.147.08:30:25.11:!2006.147.08:31:20 2006.147.08:31:20.00:data_valid=off 2006.147.08:31:20.00:postob 2006.147.08:31:20.20/cable/+6.5379E-03 2006.147.08:31:20.20/wx/18.47,1011.3,94 2006.147.08:31:21.07/fmout-gps/S +4.87E-07 2006.147.08:31:21.07:checkk5last 2006.147.08:31:21.08&checkk5last/chk_obsdata=1 2006.147.08:31:21.08&checkk5last/chk_obsdata=2 2006.147.08:31:21.09&checkk5last/chk_obsdata=3 2006.147.08:31:21.09&checkk5last/chk_obsdata=4 2006.147.08:31:21.09&checkk5last/k5log=1 2006.147.08:31:21.10&checkk5last/k5log=2 2006.147.08:31:21.10&checkk5last/k5log=3 2006.147.08:31:21.11&checkk5last/k5log=4 2006.147.08:31:21.16&checkk5last/obsinfo 2006.147.08:31:21.54/chk_obsdata//k5ts1/k06147_ts1_147-0830*_20??1470830??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:31:21.93/chk_obsdata//k5ts2/k06147_ts2_147-0830*_20??1470830??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:31:22.32/chk_obsdata//k5ts3/k06147_ts3_147-0830*_20??1470830??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:31:22.70/chk_obsdata//k5ts4/k06147_ts4_147-0830*_20??1470830??.k5 file size is correct (nominal:480MB, actual:480MB). 2006.147.08:31:23.40/k5log//k5ts1_log_newline 2006.147.08:31:24.11/k5log//k5ts2_log_newline 2006.147.08:31:24.80/k5log//k5ts3_log_newline 2006.147.08:31:25.49/k5log//k5ts4_log_newline 2006.147.08:31:25.51/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.147.08:31:25.51:"sched_end 2006.147.08:31:25.51:source=idle 2006.147.08:31:26.13:stow 2006.147.08:31:26.13&stow/source=idle 2006.147.08:31:26.13&stow/"this is stow command. 2006.147.08:31:26.13&stow/antenna=m3 2006.147.08:31:26.13#flagr#flagr/antenna,new-source 2006.147.08:31:29.01:!+10m 2006.147.08:41:29.02:standby 2006.147.08:41:29.02&standby/"this is standby command. 2006.147.08:41:29.02&standby/antenna=m0 2006.147.08:41:30.01:sy=cp /usr2/log/k06147ts.log /usr2/log_backup/ 2006.147.08:41:30.05:log=k06148ts