2006.140.21:40:07.11:Log Opened: Mark IV Field System Version 9.7.7 2006.140.21:40:07.11:location,TSUKUB32,-140.09,36.10,61.0 2006.140.21:40:07.12:horizon1,0.,5.,360. 2006.140.21:40:07.12:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.140.21:40:07.12:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.140.21:40:07.13:drivev11,330,270,no 2006.140.21:40:07.13:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.140.21:40:07.14:drivev13,15.000,268,10.000,10.000,10.000 2006.140.21:40:07.14:drivev21,330,270,no 2006.140.21:40:07.14:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.140.21:40:07.20:drivev23,15.000,268,10.000,10.000,10.000 2006.140.21:40:07.20:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.140.21:40:07.20:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.140.21:40:07.21:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.140.21:40:07.21:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.140.21:40:07.22:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.140.21:40:07.22:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.140.21:40:07.22:time,-0.364,101.533,rate 2006.140.21:40:07.23:flagr,200 2006.140.21:40:07.23:proc=k06141ts 2006.140.21:40:07.28:" k06141 2006 tsukub32 t ts 2006.140.21:40:07.29:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.140.21:40:07.29:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.140.21:40:07.30:" 108 tsukub32 14 17400 2006.140.21:40:07.30:" drudg version 050216 compiled under fs 9.7.07 2006.140.21:40:07.30:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.140.21:40:07.31:!2006.141.07:19:50 2006.141.07:19:50.00:unstow 2006.141.07:19:50.00&unstow/antenna=e 2006.141.07:19:50.00&unstow/!+10s 2006.141.07:19:50.00&unstow/antenna=m2 2006.141.07:20:02.01:scan_name=141-0730,k06141,60 2006.141.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.141.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.141.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.141.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.141.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.141.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.141.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.141.07:20:04.14:ready_k5 2006.141.07:20:04.14&ready_k5/obsinfo=st 2006.141.07:20:04.14&ready_k5/autoobs=1 2006.141.07:20:04.14&ready_k5/autoobs=2 2006.141.07:20:04.14&ready_k5/autoobs=3 2006.141.07:20:04.14&ready_k5/autoobs=4 2006.141.07:20:04.14&ready_k5/obsinfo 2006.141.07:20:04.14#flagr#flagr/antenna,new-source 2006.141.07:20:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.141.07:20:07.33/autoobs//k5ts1/ autoobs started! 2006.141.07:20:10.47/autoobs//k5ts2/ autoobs started! 2006.141.07:20:13.57/autoobs//k5ts3/ autoobs started! 2006.141.07:20:16.71/autoobs//k5ts4/ autoobs started! 2006.141.07:20:16.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:20:16.73:4f8m12a=1 2006.141.07:20:16.73&4f8m12a/xlog=on 2006.141.07:20:16.73&4f8m12a/echo=on 2006.141.07:20:16.73&4f8m12a/pcalon 2006.141.07:20:16.73&4f8m12a/"tpicd=stop 2006.141.07:20:16.73&4f8m12a/vc4f8 2006.141.07:20:16.73&4f8m12a/ifd4f 2006.141.07:20:16.73&4f8m12a/"form=m,16.000,1:2 2006.141.07:20:16.73&4f8m12a/"tpicd 2006.141.07:20:16.73&4f8m12a/echo=off 2006.141.07:20:16.73&4f8m12a/xlog=off 2006.141.07:20:16.73$4f8m12a/echo=on 2006.141.07:20:16.73$4f8m12a/pcalon 2006.141.07:20:16.73&pcalon/"no phase cal control is implemented here 2006.141.07:20:16.73$pcalon/"no phase cal control is implemented here 2006.141.07:20:16.74$4f8m12a/"tpicd=stop 2006.141.07:20:16.74$4f8m12a/vc4f8 2006.141.07:20:16.74&vc4f8/valo=1,532.99 2006.141.07:20:16.74&vc4f8/va=1,8 2006.141.07:20:16.74&vc4f8/valo=2,572.99 2006.141.07:20:16.74&vc4f8/va=2,7 2006.141.07:20:16.74&vc4f8/valo=3,672.99 2006.141.07:20:16.74&vc4f8/va=3,6 2006.141.07:20:16.74&vc4f8/valo=4,832.99 2006.141.07:20:16.74&vc4f8/va=4,7 2006.141.07:20:16.74&vc4f8/valo=5,652.99 2006.141.07:20:16.74&vc4f8/va=5,7 2006.141.07:20:16.74&vc4f8/valo=6,772.99 2006.141.07:20:16.74&vc4f8/va=6,6 2006.141.07:20:16.74&vc4f8/valo=7,832.99 2006.141.07:20:16.74&vc4f8/va=7,6 2006.141.07:20:16.74&vc4f8/valo=8,852.99 2006.141.07:20:16.74&vc4f8/va=8,6 2006.141.07:20:16.74&vc4f8/vblo=1,632.99 2006.141.07:20:16.74&vc4f8/vb=1,4 2006.141.07:20:16.74&vc4f8/vblo=2,640.99 2006.141.07:20:16.74&vc4f8/vb=2,4 2006.141.07:20:16.74&vc4f8/vblo=3,656.99 2006.141.07:20:16.74&vc4f8/vb=3,4 2006.141.07:20:16.74&vc4f8/vblo=4,712.99 2006.141.07:20:16.74&vc4f8/vb=4,4 2006.141.07:20:16.74&vc4f8/vblo=5,744.99 2006.141.07:20:16.74&vc4f8/vb=5,4 2006.141.07:20:16.74&vc4f8/vblo=6,752.99 2006.141.07:20:16.74&vc4f8/vb=6,4 2006.141.07:20:16.74&vc4f8/vabw=wide 2006.141.07:20:16.74&vc4f8/vbbw=wide 2006.141.07:20:16.74$vc4f8/valo=1,532.99 2006.141.07:20:16.78#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:20:16.78#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:20:16.78#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:16.78#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:16.78#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:16.78#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:16.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:20:16.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:16.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:16.86#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:20:16.86#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:20:16.86$vc4f8/va=1,8 2006.141.07:20:16.86#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.07:20:16.86#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.07:20:16.86#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:16.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:16.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:16.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:16.88#ibcon#[25=AT01-08\r\n] 2006.141.07:20:16.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:16.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:16.91#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.07:20:16.91#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:16.91#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:17.03#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:17.03#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:17.05#ibcon#[25=USB\r\n] 2006.141.07:20:17.08#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:17.08#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:17.08#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:20:17.08#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:20:17.08$vc4f8/valo=2,572.99 2006.141.07:20:17.08#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:20:17.08#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:20:17.08#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:17.08#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:17.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:17.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:17.12#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:20:17.16#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:17.16#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:17.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:20:17.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:20:17.16$vc4f8/va=2,7 2006.141.07:20:17.16#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:20:17.16#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:20:17.16#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:17.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:17.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:17.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:17.22#ibcon#[25=AT02-07\r\n] 2006.141.07:20:17.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:17.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:17.25#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:20:17.25#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:17.25#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:17.37#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:17.37#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:17.39#ibcon#[25=USB\r\n] 2006.141.07:20:17.42#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:17.42#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:17.42#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:20:17.42#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:20:17.42$vc4f8/valo=3,672.99 2006.141.07:20:17.42#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:20:17.42#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:20:17.42#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:17.42#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:17.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:17.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:17.46#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:20:17.50#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:17.50#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:17.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:20:17.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:20:17.50$vc4f8/va=3,6 2006.141.07:20:17.50#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:20:17.50#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:20:17.50#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:17.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:17.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:17.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:17.56#ibcon#[25=AT03-06\r\n] 2006.141.07:20:17.59#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:17.59#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:17.59#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:20:17.59#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:17.59#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:17.71#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:17.71#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:17.73#ibcon#[25=USB\r\n] 2006.141.07:20:17.76#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:17.76#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:17.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:20:17.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:20:17.76$vc4f8/valo=4,832.99 2006.141.07:20:17.76#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:20:17.76#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:20:17.76#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:17.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:17.76#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:17.76#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:17.78#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:20:17.82#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:17.82#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:17.82#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:20:17.82#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:20:17.82$vc4f8/va=4,7 2006.141.07:20:17.82#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:20:17.82#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:20:17.82#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:17.82#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:17.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:17.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:17.90#ibcon#[25=AT04-07\r\n] 2006.141.07:20:17.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:17.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:17.93#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:20:17.93#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:17.93#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:18.05#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:18.05#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:18.07#ibcon#[25=USB\r\n] 2006.141.07:20:18.10#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:18.10#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:18.10#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:20:18.10#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:20:18.10$vc4f8/valo=5,652.99 2006.141.07:20:18.10#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:20:18.10#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:20:18.10#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:18.10#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:18.10#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:18.10#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:18.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:20:18.16#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:18.16#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:18.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:20:18.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:20:18.16$vc4f8/va=5,7 2006.141.07:20:18.16#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:20:18.16#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:20:18.16#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:18.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:18.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:18.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:18.24#ibcon#[25=AT05-07\r\n] 2006.141.07:20:18.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:18.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:18.27#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:20:18.27#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:18.27#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:18.39#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:18.39#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:18.41#ibcon#[25=USB\r\n] 2006.141.07:20:18.44#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:18.44#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:18.44#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:20:18.44#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:20:18.44$vc4f8/valo=6,772.99 2006.141.07:20:18.44#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:20:18.44#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:20:18.44#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:18.44#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:18.44#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:18.44#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:18.46#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:20:18.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:18.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:18.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:20:18.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:20:18.50$vc4f8/va=6,6 2006.141.07:20:18.50#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:20:18.50#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:20:18.50#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:18.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:18.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:18.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:18.58#ibcon#[25=AT06-06\r\n] 2006.141.07:20:18.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:18.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:18.61#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:20:18.61#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:18.61#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:20:18.73#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:20:18.73#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:20:18.75#ibcon#[25=USB\r\n] 2006.141.07:20:18.78#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:20:18.78#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:20:18.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:20:18.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:20:18.78$vc4f8/valo=7,832.99 2006.141.07:20:18.78#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:20:18.78#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:20:18.78#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:18.78#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:20:18.78#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:20:18.78#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:20:18.80#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:20:18.84#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:20:18.84#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:20:18.84#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:20:18.84#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:20:18.84$vc4f8/va=7,6 2006.141.07:20:18.84#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:20:18.84#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:20:18.84#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:18.84#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:20:18.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:20:18.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:20:18.92#ibcon#[25=AT07-06\r\n] 2006.141.07:20:18.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:20:18.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:20:18.95#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:20:18.95#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:18.95#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:20:19.07#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:20:19.07#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:20:19.09#ibcon#[25=USB\r\n] 2006.141.07:20:19.12#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:20:19.12#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:20:19.12#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:20:19.12#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:20:19.12$vc4f8/valo=8,852.99 2006.141.07:20:19.12#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:20:19.12#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:20:19.12#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:19.12#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:20:19.12#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:20:19.12#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:20:19.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:20:19.18#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:20:19.18#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:20:19.18#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:20:19.18#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:20:19.18$vc4f8/va=8,6 2006.141.07:20:19.18#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.07:20:19.18#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.07:20:19.18#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:19.18#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:20:19.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:20:19.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:20:19.26#ibcon#[25=AT08-06\r\n] 2006.141.07:20:19.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:20:19.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:20:19.29#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.07:20:19.29#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:19.29#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:20:19.41#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:20:19.41#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:20:19.43#ibcon#[25=USB\r\n] 2006.141.07:20:19.46#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:20:19.46#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:20:19.46#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:20:19.46#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:20:19.46$vc4f8/vblo=1,632.99 2006.141.07:20:19.46#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:20:19.46#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:20:19.46#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:19.46#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:20:19.46#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:20:19.46#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:20:19.48#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:20:19.52#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:20:19.52#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:20:19.52#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:20:19.52#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:20:19.52$vc4f8/vb=1,4 2006.141.07:20:19.52#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.07:20:19.52#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.07:20:19.52#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:19.52#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:20:19.52#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:20:19.52#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:20:19.54#ibcon#[27=AT01-04\r\n] 2006.141.07:20:19.57#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:20:19.57#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:20:19.57#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.07:20:19.57#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:19.57#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:20:19.69#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:20:19.69#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:20:19.71#ibcon#[27=USB\r\n] 2006.141.07:20:19.74#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:20:19.74#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:20:19.74#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:20:19.74#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:20:19.74$vc4f8/vblo=2,640.99 2006.141.07:20:19.74#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:20:19.74#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:20:19.74#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:19.74#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:19.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:19.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:19.76#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:20:19.80#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:19.80#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:20:19.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:20:19.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:20:19.80$vc4f8/vb=2,4 2006.141.07:20:19.80#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.07:20:19.80#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.07:20:19.80#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:19.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:19.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:19.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:19.89#ibcon#[27=AT02-04\r\n] 2006.141.07:20:19.92#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:19.92#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:20:19.92#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.07:20:19.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:19.92#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:20.04#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:20.04#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:20.06#ibcon#[27=USB\r\n] 2006.141.07:20:20.09#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:20.09#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:20:20.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:20:20.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:20:20.09$vc4f8/vblo=3,656.99 2006.141.07:20:20.09#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:20:20.09#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:20:20.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:20.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:20.09#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:20.09#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:20.11#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:20:20.15#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:20.15#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:20:20.15#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:20:20.15#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:20:20.15$vc4f8/vb=3,4 2006.141.07:20:20.15#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:20:20.15#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:20:20.15#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:20.15#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:20.21#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:20.21#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:20.23#ibcon#[27=AT03-04\r\n] 2006.141.07:20:20.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:20.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:20:20.26#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:20:20.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:20.26#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:20.38#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:20.38#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:20.40#ibcon#[27=USB\r\n] 2006.141.07:20:20.43#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:20.43#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:20:20.43#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:20:20.43#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:20:20.43$vc4f8/vblo=4,712.99 2006.141.07:20:20.43#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:20:20.43#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:20:20.43#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:20.43#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:20.43#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:20.43#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:20.45#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:20:20.49#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:20.49#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:20:20.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:20:20.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:20:20.49$vc4f8/vb=4,4 2006.141.07:20:20.49#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:20:20.49#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:20:20.49#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:20.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:20.55#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:20.55#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:20.57#ibcon#[27=AT04-04\r\n] 2006.141.07:20:20.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:20.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:20:20.60#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:20:20.60#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:20.60#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:20.72#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:20.72#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:20.74#ibcon#[27=USB\r\n] 2006.141.07:20:20.77#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:20.77#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:20:20.77#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:20:20.77#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:20:20.77$vc4f8/vblo=5,744.99 2006.141.07:20:20.77#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:20:20.77#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:20:20.77#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:20.77#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:20.77#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:20.77#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:20.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:20:20.83#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:20.83#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:20:20.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:20:20.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:20:20.83$vc4f8/vb=5,4 2006.141.07:20:20.83#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:20:20.83#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:20:20.83#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:20.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:20.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:20.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:20.91#ibcon#[27=AT05-04\r\n] 2006.141.07:20:20.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:20.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:20:20.94#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:20:20.94#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:20.94#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:21.06#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:21.06#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:21.08#ibcon#[27=USB\r\n] 2006.141.07:20:21.11#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:21.11#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:20:21.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:20:21.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:20:21.11$vc4f8/vblo=6,752.99 2006.141.07:20:21.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:20:21.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:20:21.11#ibcon#ireg 17 cls_cnt 0 2006.141.07:20:21.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:21.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:21.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:21.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:20:21.17#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:21.17#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:20:21.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:20:21.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:20:21.17$vc4f8/vb=6,4 2006.141.07:20:21.17#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:20:21.17#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:20:21.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:20:21.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:21.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:21.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:21.25#ibcon#[27=AT06-04\r\n] 2006.141.07:20:21.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:21.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:20:21.28#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:20:21.28#ibcon#ireg 7 cls_cnt 0 2006.141.07:20:21.28#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:21.40#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:21.40#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:21.42#ibcon#[27=USB\r\n] 2006.141.07:20:21.45#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:21.45#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:20:21.45#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:20:21.45#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:20:21.45$vc4f8/vabw=wide 2006.141.07:20:21.45#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:20:21.45#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:20:21.45#ibcon#ireg 8 cls_cnt 0 2006.141.07:20:21.45#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:21.45#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:21.45#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:21.47#ibcon#[25=BW32\r\n] 2006.141.07:20:21.50#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:21.50#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:20:21.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:20:21.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:20:21.50$vc4f8/vbbw=wide 2006.141.07:20:21.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.07:20:21.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.07:20:21.50#ibcon#ireg 8 cls_cnt 0 2006.141.07:20:21.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:20:21.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:20:21.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:20:21.59#ibcon#[27=BW32\r\n] 2006.141.07:20:21.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:20:21.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:20:21.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:20:21.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:20:21.62$4f8m12a/ifd4f 2006.141.07:20:21.62&ifd4f/lo= 2006.141.07:20:21.62&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:20:21.62&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:20:21.62&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:20:21.62&ifd4f/patch= 2006.141.07:20:21.62&ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:20:21.62&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:20:21.62&ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:20:21.62$ifd4f/lo= 2006.141.07:20:21.62$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:20:21.62$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:20:21.62$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:20:21.62$ifd4f/patch= 2006.141.07:20:21.62$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:20:21.62$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:20:21.62$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:20:21.62$4f8m12a/"form=m,16.000,1:2 2006.141.07:20:21.62$4f8m12a/"tpicd 2006.141.07:20:21.62$4f8m12a/echo=off 2006.141.07:20:21.62$4f8m12a/xlog=off 2006.141.07:20:21.62:!2006.141.07:29:50 2006.141.07:20:40.13#trakl#Source acquired 2006.141.07:20:41.13#flagr#flagr/antenna,acquired 2006.141.07:21:49.13#trakl#Off source 2006.141.07:21:49.13?ERROR st -7 Antenna off-source! 2006.141.07:21:49.13#trakl#az 12.895 el 19.406 azerr*cos(el) 0.0088 elerr 0.0194 2006.141.07:21:50.13#flagr#flagr/antenna,off-source 2006.141.07:21:55.13#trakl#Source re-acquired 2006.141.07:21:56.13#flagr#flagr/antenna,re-acquired 2006.141.07:26:38.14#trakl#Off source 2006.141.07:26:38.14?ERROR st -7 Antenna off-source! 2006.141.07:26:38.14#trakl#az 13.269 el 19.626 azerr*cos(el) -0.0002 elerr 0.0170 2006.141.07:26:38.14#flagr#flagr/antenna,off-source 2006.141.07:26:44.14#trakl#Source re-acquired 2006.141.07:26:44.14#flagr#flagr/antenna,re-acquired 2006.141.07:29:50.00:preob 2006.141.07:29:50.00&preob/onsource 2006.141.07:29:51.13/onsource/TRACKING 2006.141.07:29:51.13:!2006.141.07:30:00 2006.141.07:30:00.00:data_valid=on 2006.141.07:30:00.00:midob 2006.141.07:30:00.00&midob/onsource 2006.141.07:30:00.00&midob/wx 2006.141.07:30:00.00&midob/cable 2006.141.07:30:00.00&midob/va 2006.141.07:30:00.00&midob/valo 2006.141.07:30:00.00&midob/vb 2006.141.07:30:00.00&midob/vblo 2006.141.07:30:00.00&midob/vabw 2006.141.07:30:00.00&midob/vbbw 2006.141.07:30:00.00&midob/"form 2006.141.07:30:00.00&midob/xfe 2006.141.07:30:00.00&midob/ifatt 2006.141.07:30:00.00&midob/clockoff 2006.141.07:30:00.00&midob/sy=logmail 2006.141.07:30:00.00&midob/"sy=run setcl adapt & 2006.141.07:30:00.13/onsource/TRACKING 2006.141.07:30:00.13/wx/22.04,1012.4,72 2006.141.07:30:00.24/cable/+6.5174E-03 2006.141.07:30:01.33/va/01,08,usb,yes,30,32 2006.141.07:30:01.33/va/02,07,usb,yes,30,32 2006.141.07:30:01.33/va/03,06,usb,yes,32,32 2006.141.07:30:01.33/va/04,07,usb,yes,31,33 2006.141.07:30:01.33/va/05,07,usb,yes,30,31 2006.141.07:30:01.33/va/06,06,usb,yes,29,28 2006.141.07:30:01.33/va/07,06,usb,yes,29,29 2006.141.07:30:01.33/va/08,06,usb,yes,31,31 2006.141.07:30:01.56/valo/01,532.99,yes,locked 2006.141.07:30:01.56/valo/02,572.99,yes,locked 2006.141.07:30:01.56/valo/03,672.99,yes,locked 2006.141.07:30:01.56/valo/04,832.99,yes,locked 2006.141.07:30:01.56/valo/05,652.99,yes,locked 2006.141.07:30:01.56/valo/06,772.99,yes,locked 2006.141.07:30:01.56/valo/07,832.99,yes,locked 2006.141.07:30:01.56/valo/08,852.99,yes,locked 2006.141.07:30:02.65/vb/01,04,usb,yes,29,37 2006.141.07:30:02.65/vb/02,04,usb,yes,31,40 2006.141.07:30:02.65/vb/03,04,usb,yes,28,32 2006.141.07:30:02.65/vb/04,04,usb,yes,29,29 2006.141.07:30:02.65/vb/05,04,usb,yes,27,32 2006.141.07:30:02.65/vb/06,04,usb,yes,29,31 2006.141.07:30:02.65/vb/07,04,usb,yes,30,31 2006.141.07:30:02.65/vb/08,04,usb,yes,28,32 2006.141.07:30:02.88/vblo/01,632.99,yes,locked 2006.141.07:30:02.88/vblo/02,640.99,yes,locked 2006.141.07:30:02.88/vblo/03,656.99,yes,locked 2006.141.07:30:02.88/vblo/04,712.99,yes,locked 2006.141.07:30:02.88/vblo/05,744.99,yes,locked 2006.141.07:30:02.88/vblo/06,752.99,yes,locked 2006.141.07:30:02.88/vblo/07,734.99,yes,locked 2006.141.07:30:02.88/vblo/08,744.99,yes,locked 2006.141.07:30:03.03/vabw/8 2006.141.07:30:03.18/vbbw/8 2006.141.07:30:03.29/xfe/off,on,15.2 2006.141.07:30:03.68/ifatt/23,28,28,28 2006.141.07:30:03.68&clockoff/"gps-fmout=1p 2006.141.07:30:03.68&clockoff/fmout-gps=1p 2006.141.07:30:04.11/fmout-gps/S +1.00E-07 2006.141.07:30:04.19:!2006.141.07:31:00 2006.141.07:31:00.00:data_valid=off 2006.141.07:31:00.00:postob 2006.141.07:31:00.00&postob/cable 2006.141.07:31:00.01&postob/wx 2006.141.07:31:00.01&postob/clockoff 2006.141.07:31:00.12/cable/+6.5159E-03 2006.141.07:31:00.12/wx/22.02,1012.4,71 2006.141.07:31:01.11/fmout-gps/S +9.9E-08 2006.141.07:31:01.11:scan_name=141-0733,k06141,60 2006.141.07:31:01.11:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.141.07:31:01.13#flagr#flagr/antenna,new-source 2006.141.07:31:02.13:checkk5 2006.141.07:31:02.13&checkk5/chk_autoobs=1 2006.141.07:31:02.13&checkk5/chk_autoobs=2 2006.141.07:31:02.14&checkk5/chk_autoobs=3 2006.141.07:31:02.14&checkk5/chk_autoobs=4 2006.141.07:31:02.15&checkk5/chk_obsdata=1 2006.141.07:31:02.15&checkk5/chk_obsdata=2 2006.141.07:31:02.15&checkk5/chk_obsdata=3 2006.141.07:31:02.16&checkk5/chk_obsdata=4 2006.141.07:31:02.16&checkk5/k5log=1 2006.141.07:31:02.17&checkk5/k5log=2 2006.141.07:31:02.22&checkk5/k5log=3 2006.141.07:31:02.22&checkk5/k5log=4 2006.141.07:31:02.22&checkk5/obsinfo 2006.141.07:31:02.60/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:31:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:31:03.38/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:31:03.76/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:31:04.14/chk_obsdata//k5ts1/T1410730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:31:04.52/chk_obsdata//k5ts2/T1410730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:31:04.89/chk_obsdata//k5ts3/T1410730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:31:05.26/chk_obsdata//k5ts4/T1410730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:31:05.97/k5log//k5ts1_log_newline 2006.141.07:31:06.66/k5log//k5ts2_log_newline 2006.141.07:31:07.35/k5log//k5ts3_log_newline 2006.141.07:31:08.04/k5log//k5ts4_log_newline 2006.141.07:31:08.07/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:31:08.07:4f8m12a=1 2006.141.07:31:08.07$4f8m12a/echo=on 2006.141.07:31:08.07$4f8m12a/pcalon 2006.141.07:31:08.07$pcalon/"no phase cal control is implemented here 2006.141.07:31:08.07$4f8m12a/"tpicd=stop 2006.141.07:31:08.07$4f8m12a/vc4f8 2006.141.07:31:08.07$vc4f8/valo=1,532.99 2006.141.07:31:08.07#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:31:08.07#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:31:08.07#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:08.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:08.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:08.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:08.12#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:31:08.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:08.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:08.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:31:08.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:31:08.17$vc4f8/va=1,8 2006.141.07:31:08.17#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:31:08.17#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:31:08.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:08.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:08.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:08.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:08.21#ibcon#[25=AT01-08\r\n] 2006.141.07:31:08.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:08.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:08.25#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:31:08.25#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:08.25#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:08.37#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:08.37#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:08.39#ibcon#[25=USB\r\n] 2006.141.07:31:08.44#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:08.44#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:08.44#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:31:08.44#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:31:08.44$vc4f8/valo=2,572.99 2006.141.07:31:08.44#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:31:08.44#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:31:08.44#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:08.44#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:08.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:08.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:08.46#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:31:08.50#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:08.50#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:08.50#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:31:08.50#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:31:08.50$vc4f8/va=2,7 2006.141.07:31:08.50#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:31:08.50#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:31:08.50#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:08.50#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:08.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:08.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:08.58#ibcon#[25=AT02-07\r\n] 2006.141.07:31:08.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:08.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:08.63#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:31:08.63#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:08.63#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:08.75#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:08.75#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:08.77#ibcon#[25=USB\r\n] 2006.141.07:31:08.82#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:08.82#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:08.82#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:31:08.82#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:31:08.82$vc4f8/valo=3,672.99 2006.141.07:31:08.82#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:31:08.82#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:31:08.82#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:08.82#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:08.82#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:08.82#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:08.84#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:31:08.88#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:08.88#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:08.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:31:08.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:31:08.88$vc4f8/va=3,6 2006.141.07:31:08.88#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:31:08.88#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:31:08.88#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:08.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:08.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:08.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:08.96#ibcon#[25=AT03-06\r\n] 2006.141.07:31:08.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:08.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:08.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:31:08.99#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:08.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:09.11#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:09.11#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:09.13#ibcon#[25=USB\r\n] 2006.141.07:31:09.16#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:09.16#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:09.16#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:31:09.16#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:31:09.16$vc4f8/valo=4,832.99 2006.141.07:31:09.16#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:31:09.16#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:31:09.16#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:09.16#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:09.16#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:09.16#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:09.18#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:31:09.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:09.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:09.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:31:09.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:31:09.22$vc4f8/va=4,7 2006.141.07:31:09.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:31:09.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:31:09.22#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:09.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:09.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:09.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:09.30#ibcon#[25=AT04-07\r\n] 2006.141.07:31:09.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:09.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:09.33#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:31:09.33#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:09.33#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:09.45#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:09.45#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:09.47#ibcon#[25=USB\r\n] 2006.141.07:31:09.50#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:09.50#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:09.50#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:31:09.50#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:31:09.50$vc4f8/valo=5,652.99 2006.141.07:31:09.50#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:31:09.50#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:31:09.50#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:09.50#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:09.50#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:09.50#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:09.52#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:31:09.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:09.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:09.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:31:09.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:31:09.56$vc4f8/va=5,7 2006.141.07:31:09.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:31:09.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:31:09.56#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:09.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:09.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:09.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:09.64#ibcon#[25=AT05-07\r\n] 2006.141.07:31:09.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:09.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:09.67#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:31:09.67#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:09.67#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:09.79#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:09.79#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:09.81#ibcon#[25=USB\r\n] 2006.141.07:31:09.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:09.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:09.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:31:09.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:31:09.84$vc4f8/valo=6,772.99 2006.141.07:31:09.84#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:31:09.84#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:31:09.84#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:09.84#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:09.84#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:09.84#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:09.86#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:31:09.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:09.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:09.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:31:09.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:31:09.90$vc4f8/va=6,6 2006.141.07:31:09.90#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:31:09.90#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:31:09.90#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:09.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:09.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:09.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:09.98#ibcon#[25=AT06-06\r\n] 2006.141.07:31:10.01#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:10.01#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:10.01#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:31:10.01#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:10.01#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:31:10.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:31:10.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:31:10.15#ibcon#[25=USB\r\n] 2006.141.07:31:10.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:31:10.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:31:10.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:31:10.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:31:10.18$vc4f8/valo=7,832.99 2006.141.07:31:10.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:31:10.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:31:10.18#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:10.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:31:10.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:31:10.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:31:10.20#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:31:10.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:31:10.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:31:10.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:31:10.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:31:10.26$vc4f8/va=7,6 2006.141.07:31:10.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:31:10.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:31:10.26#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:10.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:31:10.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:31:10.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:31:10.32#ibcon#[25=AT07-06\r\n] 2006.141.07:31:10.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:31:10.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:31:10.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:31:10.35#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:10.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:31:10.47#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:31:10.47#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:31:10.49#ibcon#[25=USB\r\n] 2006.141.07:31:10.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:31:10.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:31:10.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:31:10.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:31:10.52$vc4f8/valo=8,852.99 2006.141.07:31:10.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:31:10.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:31:10.52#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:10.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:31:10.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:31:10.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:31:10.54#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:31:10.58#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:31:10.58#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:31:10.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:31:10.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:31:10.58$vc4f8/va=8,6 2006.141.07:31:10.58#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:31:10.58#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:31:10.58#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:10.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:31:10.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:31:10.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:31:10.66#ibcon#[25=AT08-06\r\n] 2006.141.07:31:10.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:31:10.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:31:10.69#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:31:10.69#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:10.69#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:31:10.81#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:31:10.81#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:31:10.83#ibcon#[25=USB\r\n] 2006.141.07:31:10.86#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:31:10.86#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:31:10.86#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:31:10.86#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:31:10.86$vc4f8/vblo=1,632.99 2006.141.07:31:10.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:31:10.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:31:10.86#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:10.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:31:10.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:31:10.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:31:10.88#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:31:10.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:31:10.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:31:10.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:31:10.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:31:10.92$vc4f8/vb=1,4 2006.141.07:31:10.92#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:31:10.92#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:31:10.92#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:10.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:31:10.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:31:10.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:31:10.94#ibcon#[27=AT01-04\r\n] 2006.141.07:31:10.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:31:10.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:31:10.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:31:10.98#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:10.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:31:11.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:31:11.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:31:11.12#ibcon#[27=USB\r\n] 2006.141.07:31:11.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:31:11.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:31:11.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:31:11.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:31:11.15$vc4f8/vblo=2,640.99 2006.141.07:31:11.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:31:11.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:31:11.15#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:11.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:11.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:11.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:11.17#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:31:11.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:11.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:31:11.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:31:11.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:31:11.21$vc4f8/vb=2,4 2006.141.07:31:11.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:31:11.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:31:11.21#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:11.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:11.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:11.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:11.29#ibcon#[27=AT02-04\r\n] 2006.141.07:31:11.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:11.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:31:11.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:31:11.32#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:11.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:11.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:11.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:11.46#ibcon#[27=USB\r\n] 2006.141.07:31:11.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:11.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:31:11.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:31:11.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:31:11.49$vc4f8/vblo=3,656.99 2006.141.07:31:11.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:31:11.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:31:11.49#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:11.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:11.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:11.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:11.51#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:31:11.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:11.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:31:11.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:31:11.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:31:11.55$vc4f8/vb=3,4 2006.141.07:31:11.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:31:11.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:31:11.55#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:11.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:11.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:11.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:11.63#ibcon#[27=AT03-04\r\n] 2006.141.07:31:11.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:11.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:31:11.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:31:11.66#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:11.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:11.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:11.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:11.80#ibcon#[27=USB\r\n] 2006.141.07:31:11.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:11.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:31:11.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:31:11.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:31:11.83$vc4f8/vblo=4,712.99 2006.141.07:31:11.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:31:11.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:31:11.83#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:11.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:11.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:11.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:11.85#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:31:11.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:11.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:31:11.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:31:11.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:31:11.89$vc4f8/vb=4,4 2006.141.07:31:11.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:31:11.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:31:11.89#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:11.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:11.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:11.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:11.97#ibcon#[27=AT04-04\r\n] 2006.141.07:31:12.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:12.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:31:12.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:31:12.00#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:12.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:12.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:12.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:12.14#ibcon#[27=USB\r\n] 2006.141.07:31:12.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:12.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:31:12.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:31:12.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:31:12.17$vc4f8/vblo=5,744.99 2006.141.07:31:12.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:31:12.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:31:12.17#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:12.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:12.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:12.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:12.19#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:31:12.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:12.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:31:12.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:31:12.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:31:12.23$vc4f8/vb=5,4 2006.141.07:31:12.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:31:12.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:31:12.23#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:12.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:12.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:12.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:12.31#ibcon#[27=AT05-04\r\n] 2006.141.07:31:12.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:12.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:31:12.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:31:12.34#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:12.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:12.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:12.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:12.48#ibcon#[27=USB\r\n] 2006.141.07:31:12.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:12.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:31:12.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:31:12.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:31:12.51$vc4f8/vblo=6,752.99 2006.141.07:31:12.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:31:12.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:31:12.51#ibcon#ireg 17 cls_cnt 0 2006.141.07:31:12.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:12.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:12.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:12.53#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:31:12.57#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:12.57#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:31:12.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:31:12.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:31:12.57$vc4f8/vb=6,4 2006.141.07:31:12.57#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:31:12.57#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:31:12.57#ibcon#ireg 11 cls_cnt 2 2006.141.07:31:12.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:12.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:12.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:12.65#ibcon#[27=AT06-04\r\n] 2006.141.07:31:12.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:12.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:31:12.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:31:12.68#ibcon#ireg 7 cls_cnt 0 2006.141.07:31:12.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:12.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:12.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:12.82#ibcon#[27=USB\r\n] 2006.141.07:31:12.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:12.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:31:12.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:31:12.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:31:12.85$vc4f8/vabw=wide 2006.141.07:31:12.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:31:12.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:31:12.85#ibcon#ireg 8 cls_cnt 0 2006.141.07:31:12.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:12.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:12.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:12.87#ibcon#[25=BW32\r\n] 2006.141.07:31:12.90#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:12.90#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:31:12.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:31:12.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:31:12.90$vc4f8/vbbw=wide 2006.141.07:31:12.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:31:12.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:31:12.90#ibcon#ireg 8 cls_cnt 0 2006.141.07:31:12.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:31:12.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:31:12.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:31:12.99#ibcon#[27=BW32\r\n] 2006.141.07:31:13.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:31:13.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:31:13.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:31:13.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:31:13.02$4f8m12a/ifd4f 2006.141.07:31:13.02$ifd4f/lo= 2006.141.07:31:13.02$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:31:13.02$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:31:13.02$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:31:13.02$ifd4f/patch= 2006.141.07:31:13.02$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:31:13.02$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:31:13.02$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:31:13.02$4f8m12a/"form=m,16.000,1:2 2006.141.07:31:13.02$4f8m12a/"tpicd 2006.141.07:31:13.02$4f8m12a/echo=off 2006.141.07:31:13.02$4f8m12a/xlog=off 2006.141.07:31:13.02:!2006.141.07:33:20 2006.141.07:31:47.14#trakl#Source acquired 2006.141.07:31:49.14#flagr#flagr/antenna,acquired 2006.141.07:33:20.00:preob 2006.141.07:33:20.14/onsource/TRACKING 2006.141.07:33:20.14:!2006.141.07:33:30 2006.141.07:33:30.00:data_valid=on 2006.141.07:33:30.00:midob 2006.141.07:33:31.14/onsource/TRACKING 2006.141.07:33:31.14/wx/21.98,1012.5,71 2006.141.07:33:31.32/cable/+6.5218E-03 2006.141.07:33:32.41/va/01,08,usb,yes,34,36 2006.141.07:33:32.41/va/02,07,usb,yes,34,36 2006.141.07:33:32.41/va/03,06,usb,yes,36,36 2006.141.07:33:32.41/va/04,07,usb,yes,35,37 2006.141.07:33:32.41/va/05,07,usb,yes,33,35 2006.141.07:33:32.41/va/06,06,usb,yes,32,32 2006.141.07:33:32.41/va/07,06,usb,yes,33,33 2006.141.07:33:32.41/va/08,06,usb,yes,35,34 2006.141.07:33:32.64/valo/01,532.99,yes,locked 2006.141.07:33:32.64/valo/02,572.99,yes,locked 2006.141.07:33:32.64/valo/03,672.99,yes,locked 2006.141.07:33:32.64/valo/04,832.99,yes,locked 2006.141.07:33:32.64/valo/05,652.99,yes,locked 2006.141.07:33:32.64/valo/06,772.99,yes,locked 2006.141.07:33:32.64/valo/07,832.99,yes,locked 2006.141.07:33:32.64/valo/08,852.99,yes,locked 2006.141.07:33:33.73/vb/01,04,usb,yes,30,29 2006.141.07:33:33.73/vb/02,04,usb,yes,32,33 2006.141.07:33:33.73/vb/03,04,usb,yes,28,32 2006.141.07:33:33.73/vb/04,04,usb,yes,29,29 2006.141.07:33:33.73/vb/05,04,usb,yes,27,31 2006.141.07:33:33.73/vb/06,04,usb,yes,28,31 2006.141.07:33:33.73/vb/07,04,usb,yes,30,30 2006.141.07:33:33.73/vb/08,04,usb,yes,28,31 2006.141.07:33:33.97/vblo/01,632.99,yes,locked 2006.141.07:33:33.97/vblo/02,640.99,yes,locked 2006.141.07:33:33.97/vblo/03,656.99,yes,locked 2006.141.07:33:33.97/vblo/04,712.99,yes,locked 2006.141.07:33:33.97/vblo/05,744.99,yes,locked 2006.141.07:33:33.97/vblo/06,752.99,yes,locked 2006.141.07:33:33.97/vblo/07,734.99,yes,locked 2006.141.07:33:33.97/vblo/08,744.99,yes,locked 2006.141.07:33:34.12/vabw/8 2006.141.07:33:34.27/vbbw/8 2006.141.07:33:34.36/xfe/off,on,14.7 2006.141.07:33:34.75/ifatt/23,28,28,28 2006.141.07:33:35.11/fmout-gps/S +1.01E-07 2006.141.07:33:35.15:!2006.141.07:34:30 2006.141.07:34:30.00:data_valid=off 2006.141.07:34:30.00:postob 2006.141.07:34:30.08/cable/+6.5235E-03 2006.141.07:34:30.08/wx/21.95,1012.6,72 2006.141.07:34:31.11/fmout-gps/S +1.01E-07 2006.141.07:34:31.11:scan_name=141-0735,k06141,60 2006.141.07:34:31.11:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.141.07:34:31.14#flagr#flagr/antenna,new-source 2006.141.07:34:32.14:checkk5 2006.141.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:34:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:34:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:34:34.03/chk_obsdata//k5ts1/T1410733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:34:34.41/chk_obsdata//k5ts2/T1410733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:34:34.78/chk_obsdata//k5ts3/T1410733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:34:35.15/chk_obsdata//k5ts4/T1410733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:34:35.84/k5log//k5ts1_log_newline 2006.141.07:34:36.53/k5log//k5ts2_log_newline 2006.141.07:34:37.22/k5log//k5ts3_log_newline 2006.141.07:34:37.91/k5log//k5ts4_log_newline 2006.141.07:34:37.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:34:37.94:4f8m12a=1 2006.141.07:34:37.94$4f8m12a/echo=on 2006.141.07:34:37.94$4f8m12a/pcalon 2006.141.07:34:37.94$pcalon/"no phase cal control is implemented here 2006.141.07:34:37.94$4f8m12a/"tpicd=stop 2006.141.07:34:37.94$4f8m12a/vc4f8 2006.141.07:34:37.94$vc4f8/valo=1,532.99 2006.141.07:34:37.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.07:34:37.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.07:34:37.94#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:37.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:37.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:37.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:37.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:34:38.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:38.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:38.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:34:38.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:34:38.01$vc4f8/va=1,8 2006.141.07:34:38.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.07:34:38.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.07:34:38.01#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:38.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:38.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:38.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:38.03#ibcon#[25=AT01-08\r\n] 2006.141.07:34:38.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:38.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:38.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.07:34:38.07#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:38.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:38.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:38.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:38.21#ibcon#[25=USB\r\n] 2006.141.07:34:38.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:38.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:38.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:34:38.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:34:38.24$vc4f8/valo=2,572.99 2006.141.07:34:38.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:34:38.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:34:38.24#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:38.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:38.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:38.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:38.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:34:38.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:38.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:38.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:34:38.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:34:38.32$vc4f8/va=2,7 2006.141.07:34:38.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.07:34:38.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.07:34:38.32#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:38.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:38.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:38.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:38.38#ibcon#[25=AT02-07\r\n] 2006.141.07:34:38.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:38.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:38.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.07:34:38.41#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:38.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:38.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:38.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:38.55#ibcon#[25=USB\r\n] 2006.141.07:34:38.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:38.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:38.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:34:38.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:34:38.60$vc4f8/valo=3,672.99 2006.141.07:34:38.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.07:34:38.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.07:34:38.60#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:38.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:38.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:38.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:38.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:34:38.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:38.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:38.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:34:38.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:34:38.66$vc4f8/va=3,6 2006.141.07:34:38.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.07:34:38.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.07:34:38.66#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:38.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:38.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:38.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:38.74#ibcon#[25=AT03-06\r\n] 2006.141.07:34:38.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:38.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:38.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.07:34:38.77#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:38.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:38.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:38.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:38.91#ibcon#[25=USB\r\n] 2006.141.07:34:38.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:38.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:38.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:34:38.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:34:38.94$vc4f8/valo=4,832.99 2006.141.07:34:38.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:34:38.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:34:38.94#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:38.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:38.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:38.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:38.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:34:39.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:39.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:39.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:34:39.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:34:39.00$vc4f8/va=4,7 2006.141.07:34:39.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:34:39.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:34:39.00#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:39.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:39.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:39.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:39.08#ibcon#[25=AT04-07\r\n] 2006.141.07:34:39.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:39.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:39.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:34:39.11#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:39.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:39.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:39.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:39.25#ibcon#[25=USB\r\n] 2006.141.07:34:39.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:39.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:39.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:34:39.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:34:39.28$vc4f8/valo=5,652.99 2006.141.07:34:39.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:34:39.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:34:39.28#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:39.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:39.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:39.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:39.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:34:39.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:39.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:39.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:34:39.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:34:39.34$vc4f8/va=5,7 2006.141.07:34:39.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:34:39.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:34:39.34#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:39.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:39.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:39.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:39.42#ibcon#[25=AT05-07\r\n] 2006.141.07:34:39.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:39.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:39.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:34:39.45#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:39.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:39.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:39.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:39.59#ibcon#[25=USB\r\n] 2006.141.07:34:39.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:39.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:39.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:34:39.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:34:39.62$vc4f8/valo=6,772.99 2006.141.07:34:39.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.07:34:39.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.07:34:39.62#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:39.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:39.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:39.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:39.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:34:39.68#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:39.68#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:39.68#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:34:39.68#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:34:39.68$vc4f8/va=6,6 2006.141.07:34:39.68#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.07:34:39.68#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.07:34:39.68#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:39.68#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:39.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:39.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:39.76#ibcon#[25=AT06-06\r\n] 2006.141.07:34:39.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:39.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:39.79#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.07:34:39.79#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:39.79#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:34:39.91#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:34:39.91#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:34:39.93#ibcon#[25=USB\r\n] 2006.141.07:34:39.96#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:34:39.96#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:34:39.96#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:34:39.96#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:34:39.96$vc4f8/valo=7,832.99 2006.141.07:34:39.96#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.07:34:39.96#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.07:34:39.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:39.96#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:34:39.96#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:34:39.96#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:34:39.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:34:40.02#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:34:40.02#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:34:40.02#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:34:40.02#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:34:40.02$vc4f8/va=7,6 2006.141.07:34:40.02#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.07:34:40.02#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.07:34:40.02#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:40.02#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:34:40.08#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:34:40.08#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:34:40.10#ibcon#[25=AT07-06\r\n] 2006.141.07:34:40.13#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:34:40.13#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:34:40.13#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.07:34:40.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:40.13#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:34:40.25#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:34:40.25#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:34:40.27#ibcon#[25=USB\r\n] 2006.141.07:34:40.30#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:34:40.30#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:34:40.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:34:40.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:34:40.30$vc4f8/valo=8,852.99 2006.141.07:34:40.30#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.07:34:40.30#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.07:34:40.30#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:40.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:34:40.30#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:34:40.30#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:34:40.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:34:40.36#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:34:40.36#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:34:40.36#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:34:40.36#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:34:40.36$vc4f8/va=8,6 2006.141.07:34:40.36#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.07:34:40.36#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.07:34:40.36#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:40.36#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:34:40.42#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:34:40.42#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:34:40.44#ibcon#[25=AT08-06\r\n] 2006.141.07:34:40.47#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:34:40.47#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:34:40.47#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.07:34:40.47#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:40.47#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:34:40.59#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:34:40.59#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:34:40.61#ibcon#[25=USB\r\n] 2006.141.07:34:40.64#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:34:40.64#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:34:40.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:34:40.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:34:40.64$vc4f8/vblo=1,632.99 2006.141.07:34:40.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.07:34:40.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.07:34:40.64#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:40.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:34:40.64#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:34:40.64#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:34:40.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:34:40.70#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:34:40.70#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:34:40.70#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:34:40.70#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:34:40.70$vc4f8/vb=1,4 2006.141.07:34:40.70#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.07:34:40.70#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.07:34:40.70#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:40.70#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:34:40.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:34:40.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:34:40.72#ibcon#[27=AT01-04\r\n] 2006.141.07:34:40.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:34:40.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:34:40.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.07:34:40.75#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:40.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:34:40.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:34:40.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:34:40.89#ibcon#[27=USB\r\n] 2006.141.07:34:40.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:34:40.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:34:40.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:34:40.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:34:40.92$vc4f8/vblo=2,640.99 2006.141.07:34:40.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.07:34:40.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.07:34:40.92#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:40.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:40.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:40.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:40.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:34:40.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:40.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:34:40.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:34:40.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:34:40.98$vc4f8/vb=2,4 2006.141.07:34:40.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.07:34:40.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.07:34:40.98#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:40.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:41.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:41.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:41.06#ibcon#[27=AT02-04\r\n] 2006.141.07:34:41.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:41.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:34:41.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.07:34:41.09#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:41.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:41.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:41.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:41.23#ibcon#[27=USB\r\n] 2006.141.07:34:41.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:41.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:34:41.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:34:41.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:34:41.26$vc4f8/vblo=3,656.99 2006.141.07:34:41.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:34:41.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:34:41.26#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:41.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:41.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:41.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:41.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:34:41.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:41.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:34:41.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:34:41.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:34:41.32$vc4f8/vb=3,4 2006.141.07:34:41.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.07:34:41.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.07:34:41.32#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:41.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:41.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:41.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:41.40#ibcon#[27=AT03-04\r\n] 2006.141.07:34:41.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:41.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:34:41.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.07:34:41.43#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:41.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:41.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:41.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:41.57#ibcon#[27=USB\r\n] 2006.141.07:34:41.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:41.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:34:41.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:34:41.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:34:41.60$vc4f8/vblo=4,712.99 2006.141.07:34:41.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.07:34:41.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.07:34:41.60#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:41.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:41.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:41.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:41.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:34:41.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:41.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:34:41.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:34:41.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:34:41.66$vc4f8/vb=4,4 2006.141.07:34:41.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.07:34:41.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.07:34:41.66#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:41.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:41.72#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:41.72#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:41.74#ibcon#[27=AT04-04\r\n] 2006.141.07:34:41.77#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:41.77#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:34:41.77#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.07:34:41.77#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:41.77#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:41.89#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:41.89#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:41.91#ibcon#[27=USB\r\n] 2006.141.07:34:41.94#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:41.94#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:34:41.94#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:34:41.94#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:34:41.94$vc4f8/vblo=5,744.99 2006.141.07:34:41.94#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:34:41.94#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:34:41.94#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:41.94#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:41.94#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:41.94#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:41.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:34:42.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:42.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:34:42.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:34:42.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:34:42.00$vc4f8/vb=5,4 2006.141.07:34:42.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:34:42.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:34:42.00#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:42.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:42.06#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:42.06#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:42.08#ibcon#[27=AT05-04\r\n] 2006.141.07:34:42.11#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:42.11#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:34:42.11#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:34:42.11#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:42.11#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:42.23#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:42.23#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:42.25#ibcon#[27=USB\r\n] 2006.141.07:34:42.28#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:42.28#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:34:42.28#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:34:42.28#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:34:42.28$vc4f8/vblo=6,752.99 2006.141.07:34:42.28#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:34:42.28#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:34:42.28#ibcon#ireg 17 cls_cnt 0 2006.141.07:34:42.28#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:42.28#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:42.28#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:42.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:34:42.34#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:42.34#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:34:42.34#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:34:42.34#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:34:42.34$vc4f8/vb=6,4 2006.141.07:34:42.34#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:34:42.34#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:34:42.34#ibcon#ireg 11 cls_cnt 2 2006.141.07:34:42.34#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:42.40#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:42.40#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:42.42#ibcon#[27=AT06-04\r\n] 2006.141.07:34:42.45#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:42.45#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:34:42.45#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:34:42.45#ibcon#ireg 7 cls_cnt 0 2006.141.07:34:42.45#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:42.57#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:42.57#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:42.59#ibcon#[27=USB\r\n] 2006.141.07:34:42.62#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:42.62#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:34:42.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:34:42.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:34:42.62$vc4f8/vabw=wide 2006.141.07:34:42.62#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.07:34:42.62#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.07:34:42.62#ibcon#ireg 8 cls_cnt 0 2006.141.07:34:42.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:42.62#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:42.62#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:42.64#ibcon#[25=BW32\r\n] 2006.141.07:34:42.67#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:42.67#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:34:42.67#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:34:42.67#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:34:42.67$vc4f8/vbbw=wide 2006.141.07:34:42.67#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:34:42.67#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:34:42.67#ibcon#ireg 8 cls_cnt 0 2006.141.07:34:42.67#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:34:42.74#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:34:42.74#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:34:42.76#ibcon#[27=BW32\r\n] 2006.141.07:34:42.79#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:34:42.79#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:34:42.79#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:34:42.79#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:34:42.79$4f8m12a/ifd4f 2006.141.07:34:42.79$ifd4f/lo= 2006.141.07:34:42.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:34:42.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:34:42.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:34:42.79$ifd4f/patch= 2006.141.07:34:42.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:34:42.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:34:42.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:34:42.79$4f8m12a/"form=m,16.000,1:2 2006.141.07:34:42.79$4f8m12a/"tpicd 2006.141.07:34:42.79$4f8m12a/echo=off 2006.141.07:34:42.79$4f8m12a/xlog=off 2006.141.07:34:42.79:!2006.141.07:35:10 2006.141.07:34:53.14#trakl#Source acquired 2006.141.07:34:55.14#flagr#flagr/antenna,acquired 2006.141.07:35:10.00:preob 2006.141.07:35:11.14/onsource/TRACKING 2006.141.07:35:11.14:!2006.141.07:35:20 2006.141.07:35:20.00:data_valid=on 2006.141.07:35:20.00:midob 2006.141.07:35:20.14/onsource/TRACKING 2006.141.07:35:20.14/wx/21.94,1012.6,72 2006.141.07:35:20.31/cable/+6.5191E-03 2006.141.07:35:21.40/va/01,08,usb,yes,29,31 2006.141.07:35:21.40/va/02,07,usb,yes,29,30 2006.141.07:35:21.40/va/03,06,usb,yes,31,31 2006.141.07:35:21.40/va/04,07,usb,yes,30,32 2006.141.07:35:21.40/va/05,07,usb,yes,28,29 2006.141.07:35:21.40/va/06,06,usb,yes,27,27 2006.141.07:35:21.40/va/07,06,usb,yes,27,27 2006.141.07:35:21.40/va/08,06,usb,yes,29,29 2006.141.07:35:21.63/valo/01,532.99,yes,locked 2006.141.07:35:21.63/valo/02,572.99,yes,locked 2006.141.07:35:21.63/valo/03,672.99,yes,locked 2006.141.07:35:21.63/valo/04,832.99,yes,locked 2006.141.07:35:21.63/valo/05,652.99,yes,locked 2006.141.07:35:21.63/valo/06,772.99,yes,locked 2006.141.07:35:21.63/valo/07,832.99,yes,locked 2006.141.07:35:21.63/valo/08,852.99,yes,locked 2006.141.07:35:22.72/vb/01,04,usb,yes,29,28 2006.141.07:35:22.72/vb/02,04,usb,yes,31,32 2006.141.07:35:22.72/vb/03,04,usb,yes,27,31 2006.141.07:35:22.72/vb/04,04,usb,yes,28,28 2006.141.07:35:22.72/vb/05,04,usb,yes,27,31 2006.141.07:35:22.72/vb/06,04,usb,yes,28,30 2006.141.07:35:22.72/vb/07,04,usb,yes,30,29 2006.141.07:35:22.72/vb/08,04,usb,yes,27,31 2006.141.07:35:22.96/vblo/01,632.99,yes,locked 2006.141.07:35:22.96/vblo/02,640.99,yes,locked 2006.141.07:35:22.96/vblo/03,656.99,yes,locked 2006.141.07:35:22.96/vblo/04,712.99,yes,locked 2006.141.07:35:22.96/vblo/05,744.99,yes,locked 2006.141.07:35:22.96/vblo/06,752.99,yes,locked 2006.141.07:35:22.96/vblo/07,734.99,yes,locked 2006.141.07:35:22.96/vblo/08,744.99,yes,locked 2006.141.07:35:23.11/vabw/8 2006.141.07:35:23.26/vbbw/8 2006.141.07:35:23.35/xfe/off,on,14.7 2006.141.07:35:23.72/ifatt/23,28,28,28 2006.141.07:35:24.12/fmout-gps/S +1.01E-07 2006.141.07:35:24.20:!2006.141.07:36:20 2006.141.07:36:20.00:data_valid=off 2006.141.07:36:20.00:postob 2006.141.07:36:20.17/cable/+6.5198E-03 2006.141.07:36:20.17/wx/21.92,1012.6,71 2006.141.07:36:21.11/fmout-gps/S +1.02E-07 2006.141.07:36:21.11:scan_name=141-0737,k06141,60 2006.141.07:36:21.11:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.141.07:36:21.14#flagr#flagr/antenna,new-source 2006.141.07:36:22.14:checkk5 2006.141.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:36:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:36:25.13/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:36:25.51/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:36:25.88/chk_obsdata//k5ts1/T1410735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:36:26.26/chk_obsdata//k5ts2/T1410735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:36:26.62/chk_obsdata//k5ts3/T1410735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:36:27.00/chk_obsdata//k5ts4/T1410735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:36:27.69/k5log//k5ts1_log_newline 2006.141.07:36:28.38/k5log//k5ts2_log_newline 2006.141.07:36:29.07/k5log//k5ts3_log_newline 2006.141.07:36:29.76/k5log//k5ts4_log_newline 2006.141.07:36:29.79/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:36:29.79:4f8m12a=1 2006.141.07:36:29.79$4f8m12a/echo=on 2006.141.07:36:29.79$4f8m12a/pcalon 2006.141.07:36:29.79$pcalon/"no phase cal control is implemented here 2006.141.07:36:29.79$4f8m12a/"tpicd=stop 2006.141.07:36:29.79$4f8m12a/vc4f8 2006.141.07:36:29.79$vc4f8/valo=1,532.99 2006.141.07:36:29.79#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:36:29.79#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:36:29.79#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:29.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:29.79#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:29.79#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:29.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:36:29.86#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:29.86#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:29.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:36:29.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:36:29.86$vc4f8/va=1,8 2006.141.07:36:29.86#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:36:29.86#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:36:29.86#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:29.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:29.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:29.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:29.88#ibcon#[25=AT01-08\r\n] 2006.141.07:36:29.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:29.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:29.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:36:29.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:29.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:30.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:30.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:30.06#ibcon#[25=USB\r\n] 2006.141.07:36:30.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:30.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:30.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:36:30.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:36:30.09$vc4f8/valo=2,572.99 2006.141.07:36:30.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:36:30.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:36:30.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:30.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:30.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:30.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:30.13#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:36:30.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:30.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:30.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:36:30.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:36:30.17$vc4f8/va=2,7 2006.141.07:36:30.17#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:36:30.17#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:36:30.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:30.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:30.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:30.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:30.23#ibcon#[25=AT02-07\r\n] 2006.141.07:36:30.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:30.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:30.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:36:30.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:30.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:30.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:30.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:30.40#ibcon#[25=USB\r\n] 2006.141.07:36:30.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:30.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:30.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:36:30.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:36:30.43$vc4f8/valo=3,672.99 2006.141.07:36:30.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:36:30.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:36:30.43#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:30.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:30.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:30.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:30.47#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:36:30.51#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:30.51#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:30.51#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:36:30.51#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:36:30.51$vc4f8/va=3,6 2006.141.07:36:30.51#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:36:30.51#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:36:30.51#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:30.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:30.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:30.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:30.57#ibcon#[25=AT03-06\r\n] 2006.141.07:36:30.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:30.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:30.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:36:30.60#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:30.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:30.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:30.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:30.74#ibcon#[25=USB\r\n] 2006.141.07:36:30.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:30.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:30.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:36:30.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:36:30.77$vc4f8/valo=4,832.99 2006.141.07:36:30.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:36:30.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:36:30.77#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:30.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:30.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:30.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:30.79#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:36:30.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:30.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:30.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:36:30.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:36:30.83$vc4f8/va=4,7 2006.141.07:36:30.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:36:30.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:36:30.83#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:30.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:30.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:30.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:30.91#ibcon#[25=AT04-07\r\n] 2006.141.07:36:30.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:30.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:30.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:36:30.94#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:30.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:31.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:31.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:31.08#ibcon#[25=USB\r\n] 2006.141.07:36:31.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:31.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:31.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:36:31.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:36:31.11$vc4f8/valo=5,652.99 2006.141.07:36:31.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:36:31.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:36:31.11#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:31.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:31.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:31.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:31.13#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:36:31.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:31.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:31.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:36:31.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:36:31.17$vc4f8/va=5,7 2006.141.07:36:31.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.07:36:31.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.07:36:31.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:31.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:31.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:31.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:31.25#ibcon#[25=AT05-07\r\n] 2006.141.07:36:31.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:31.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:31.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.07:36:31.28#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:31.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:31.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:31.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:31.42#ibcon#[25=USB\r\n] 2006.141.07:36:31.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:31.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:31.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:36:31.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:36:31.45$vc4f8/valo=6,772.99 2006.141.07:36:31.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.07:36:31.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.07:36:31.45#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:31.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:31.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:31.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:31.47#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:36:31.51#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:31.51#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:31.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:36:31.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:36:31.51$vc4f8/va=6,6 2006.141.07:36:31.51#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.07:36:31.51#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.07:36:31.51#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:31.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:31.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:31.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:31.59#ibcon#[25=AT06-06\r\n] 2006.141.07:36:31.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:31.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:31.62#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.07:36:31.62#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:31.62#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:36:31.74#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:36:31.74#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:36:31.76#ibcon#[25=USB\r\n] 2006.141.07:36:31.79#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:36:31.79#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:36:31.79#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:36:31.79#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:36:31.79$vc4f8/valo=7,832.99 2006.141.07:36:31.79#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:36:31.79#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:36:31.79#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:31.79#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:36:31.79#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:36:31.79#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:36:31.81#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:36:31.85#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:36:31.85#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:36:31.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:36:31.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:36:31.85$vc4f8/va=7,6 2006.141.07:36:31.85#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.07:36:31.85#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.07:36:31.85#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:31.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:36:31.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:36:31.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:36:31.93#ibcon#[25=AT07-06\r\n] 2006.141.07:36:31.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:36:31.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:36:31.96#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.07:36:31.96#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:31.96#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:36:32.08#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:36:32.08#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:36:32.10#ibcon#[25=USB\r\n] 2006.141.07:36:32.13#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:36:32.13#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:36:32.13#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:36:32.13#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:36:32.13$vc4f8/valo=8,852.99 2006.141.07:36:32.13#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.07:36:32.13#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.07:36:32.13#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:32.13#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:36:32.13#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:36:32.13#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:36:32.15#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:36:32.19#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:36:32.19#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:36:32.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:36:32.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:36:32.19$vc4f8/va=8,6 2006.141.07:36:32.19#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.07:36:32.19#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.07:36:32.19#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:32.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:36:32.25#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:36:32.25#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:36:32.27#ibcon#[25=AT08-06\r\n] 2006.141.07:36:32.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:36:32.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:36:32.30#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.07:36:32.30#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:32.30#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:36:32.42#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:36:32.42#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:36:32.44#ibcon#[25=USB\r\n] 2006.141.07:36:32.47#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:36:32.47#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:36:32.47#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:36:32.47#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:36:32.47$vc4f8/vblo=1,632.99 2006.141.07:36:32.47#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.07:36:32.47#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.07:36:32.47#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:32.47#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:36:32.47#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:36:32.47#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:36:32.49#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:36:32.53#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:36:32.53#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:36:32.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:36:32.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:36:32.53$vc4f8/vb=1,4 2006.141.07:36:32.53#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.07:36:32.53#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.07:36:32.53#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:32.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:36:32.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:36:32.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:36:32.55#ibcon#[27=AT01-04\r\n] 2006.141.07:36:32.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:36:32.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:36:32.58#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.07:36:32.58#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:32.58#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:36:32.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:36:32.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:36:32.72#ibcon#[27=USB\r\n] 2006.141.07:36:32.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:36:32.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:36:32.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:36:32.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:36:32.75$vc4f8/vblo=2,640.99 2006.141.07:36:32.75#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:36:32.75#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:36:32.75#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:32.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:32.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:32.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:32.77#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:36:32.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:32.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:36:32.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:36:32.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:36:32.81$vc4f8/vb=2,4 2006.141.07:36:32.81#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:36:32.81#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:36:32.81#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:32.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:32.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:32.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:32.89#ibcon#[27=AT02-04\r\n] 2006.141.07:36:32.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:32.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:36:32.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:36:32.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:32.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:33.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:33.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:33.06#ibcon#[27=USB\r\n] 2006.141.07:36:33.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:33.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:36:33.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:36:33.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:36:33.09$vc4f8/vblo=3,656.99 2006.141.07:36:33.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:36:33.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:36:33.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:33.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:33.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:33.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:33.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:36:33.17#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:33.17#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:36:33.17#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:36:33.17#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:36:33.17$vc4f8/vb=3,4 2006.141.07:36:33.17#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:36:33.17#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:36:33.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:33.17#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:33.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:33.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:33.23#ibcon#[27=AT03-04\r\n] 2006.141.07:36:33.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:33.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:36:33.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:36:33.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:33.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:33.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:33.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:33.40#ibcon#[27=USB\r\n] 2006.141.07:36:33.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:33.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:36:33.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:36:33.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:36:33.43$vc4f8/vblo=4,712.99 2006.141.07:36:33.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:36:33.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:36:33.43#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:33.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:33.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:33.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:33.45#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:36:33.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:33.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:36:33.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:36:33.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:36:33.49$vc4f8/vb=4,4 2006.141.07:36:33.49#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:36:33.49#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:36:33.49#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:33.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:33.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:33.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:33.57#ibcon#[27=AT04-04\r\n] 2006.141.07:36:33.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:33.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:36:33.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:36:33.60#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:33.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:33.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:33.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:33.74#ibcon#[27=USB\r\n] 2006.141.07:36:33.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:33.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:36:33.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:36:33.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:36:33.77$vc4f8/vblo=5,744.99 2006.141.07:36:33.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:36:33.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:36:33.77#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:33.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:33.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:33.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:33.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:36:33.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:33.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:36:33.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:36:33.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:36:33.83$vc4f8/vb=5,4 2006.141.07:36:33.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:36:33.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:36:33.83#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:33.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:33.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:33.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:33.91#ibcon#[27=AT05-04\r\n] 2006.141.07:36:33.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:33.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:36:33.94#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:36:33.94#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:33.94#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:34.06#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:34.06#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:34.08#ibcon#[27=USB\r\n] 2006.141.07:36:34.11#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:34.11#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:36:34.11#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:36:34.11#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:36:34.11$vc4f8/vblo=6,752.99 2006.141.07:36:34.11#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:36:34.11#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:36:34.11#ibcon#ireg 17 cls_cnt 0 2006.141.07:36:34.11#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:34.11#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:34.11#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:34.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:36:34.17#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:34.17#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:36:34.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:36:34.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:36:34.17$vc4f8/vb=6,4 2006.141.07:36:34.17#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.07:36:34.17#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.07:36:34.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:36:34.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:34.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:34.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:34.25#ibcon#[27=AT06-04\r\n] 2006.141.07:36:34.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:34.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:36:34.28#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.07:36:34.28#ibcon#ireg 7 cls_cnt 0 2006.141.07:36:34.28#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:34.40#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:34.40#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:34.42#ibcon#[27=USB\r\n] 2006.141.07:36:34.45#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:34.45#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:36:34.45#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:36:34.45#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:36:34.45$vc4f8/vabw=wide 2006.141.07:36:34.45#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.07:36:34.45#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.07:36:34.45#ibcon#ireg 8 cls_cnt 0 2006.141.07:36:34.45#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:34.45#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:34.45#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:34.47#ibcon#[25=BW32\r\n] 2006.141.07:36:34.50#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:34.50#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:36:34.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:36:34.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:36:34.50$vc4f8/vbbw=wide 2006.141.07:36:34.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:36:34.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:36:34.50#ibcon#ireg 8 cls_cnt 0 2006.141.07:36:34.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:36:34.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:36:34.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:36:34.59#ibcon#[27=BW32\r\n] 2006.141.07:36:34.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:36:34.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:36:34.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:36:34.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:36:34.62$4f8m12a/ifd4f 2006.141.07:36:34.62$ifd4f/lo= 2006.141.07:36:34.62$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:36:34.62$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:36:34.62$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:36:34.62$ifd4f/patch= 2006.141.07:36:34.62$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:36:34.62$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:36:34.62$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:36:34.62$4f8m12a/"form=m,16.000,1:2 2006.141.07:36:34.62$4f8m12a/"tpicd 2006.141.07:36:34.62$4f8m12a/echo=off 2006.141.07:36:34.62$4f8m12a/xlog=off 2006.141.07:36:34.62:!2006.141.07:37:00 2006.141.07:36:42.14#trakl#Source acquired 2006.141.07:36:42.14#flagr#flagr/antenna,acquired 2006.141.07:37:00.00:preob 2006.141.07:37:01.14/onsource/TRACKING 2006.141.07:37:01.14:!2006.141.07:37:10 2006.141.07:37:10.00:data_valid=on 2006.141.07:37:10.00:midob 2006.141.07:37:10.13/onsource/TRACKING 2006.141.07:37:10.13/wx/21.91,1012.6,70 2006.141.07:37:10.20/cable/+6.5213E-03 2006.141.07:37:11.29/va/01,08,usb,yes,29,30 2006.141.07:37:11.29/va/02,07,usb,yes,29,30 2006.141.07:37:11.29/va/03,06,usb,yes,30,30 2006.141.07:37:11.29/va/04,07,usb,yes,29,31 2006.141.07:37:11.29/va/05,07,usb,yes,28,29 2006.141.07:37:11.29/va/06,06,usb,yes,27,27 2006.141.07:37:11.29/va/07,06,usb,yes,27,27 2006.141.07:37:11.29/va/08,06,usb,yes,29,29 2006.141.07:37:11.52/valo/01,532.99,yes,locked 2006.141.07:37:11.52/valo/02,572.99,yes,locked 2006.141.07:37:11.52/valo/03,672.99,yes,locked 2006.141.07:37:11.52/valo/04,832.99,yes,locked 2006.141.07:37:11.52/valo/05,652.99,yes,locked 2006.141.07:37:11.52/valo/06,772.99,yes,locked 2006.141.07:37:11.52/valo/07,832.99,yes,locked 2006.141.07:37:11.52/valo/08,852.99,yes,locked 2006.141.07:37:12.61/vb/01,04,usb,yes,29,28 2006.141.07:37:12.61/vb/02,04,usb,yes,31,32 2006.141.07:37:12.61/vb/03,04,usb,yes,27,31 2006.141.07:37:12.61/vb/04,04,usb,yes,28,28 2006.141.07:37:12.61/vb/05,04,usb,yes,26,30 2006.141.07:37:12.61/vb/06,04,usb,yes,27,30 2006.141.07:37:12.61/vb/07,04,usb,yes,29,29 2006.141.07:37:12.61/vb/08,04,usb,yes,27,30 2006.141.07:37:12.84/vblo/01,632.99,yes,locked 2006.141.07:37:12.84/vblo/02,640.99,yes,locked 2006.141.07:37:12.84/vblo/03,656.99,yes,locked 2006.141.07:37:12.84/vblo/04,712.99,yes,locked 2006.141.07:37:12.84/vblo/05,744.99,yes,locked 2006.141.07:37:12.84/vblo/06,752.99,yes,locked 2006.141.07:37:12.84/vblo/07,734.99,yes,locked 2006.141.07:37:12.84/vblo/08,744.99,yes,locked 2006.141.07:37:12.99/vabw/8 2006.141.07:37:13.14/vbbw/8 2006.141.07:37:13.23/xfe/off,on,15.2 2006.141.07:37:13.62/ifatt/23,28,28,28 2006.141.07:37:14.11/fmout-gps/S +1.01E-07 2006.141.07:37:14.15:!2006.141.07:38:10 2006.141.07:38:10.00:data_valid=off 2006.141.07:38:10.00:postob 2006.141.07:38:10.12/cable/+6.5208E-03 2006.141.07:38:10.12/wx/21.88,1012.6,70 2006.141.07:38:11.11/fmout-gps/S +1.01E-07 2006.141.07:38:11.11:scan_name=141-0739,k06141,60 2006.141.07:38:11.11:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.141.07:38:11.13#flagr#flagr/antenna,new-source 2006.141.07:38:12.13:checkk5 2006.141.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:38:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:38:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:38:14.02/chk_obsdata//k5ts1/T1410737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:38:14.40/chk_obsdata//k5ts2/T1410737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:38:17.77/chk_obsdata//k5ts3/T1410737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:38:18.14/chk_obsdata//k5ts4/T1410737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:38:18.83/k5log//k5ts1_log_newline 2006.141.07:38:19.53/k5log//k5ts2_log_newline 2006.141.07:38:20.22/k5log//k5ts3_log_newline 2006.141.07:38:20.91/k5log//k5ts4_log_newline 2006.141.07:38:20.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:38:20.93:4f8m12a=1 2006.141.07:38:20.93$4f8m12a/echo=on 2006.141.07:38:20.93$4f8m12a/pcalon 2006.141.07:38:20.93$pcalon/"no phase cal control is implemented here 2006.141.07:38:20.93$4f8m12a/"tpicd=stop 2006.141.07:38:20.93$4f8m12a/vc4f8 2006.141.07:38:20.93$vc4f8/valo=1,532.99 2006.141.07:38:20.94#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:38:20.94#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:38:20.94#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:20.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:20.94#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:20.94#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:20.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:38:21.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:21.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:21.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:38:21.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:38:21.03$vc4f8/va=1,8 2006.141.07:38:21.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:38:21.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:38:21.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:21.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:21.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:21.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:21.06#ibcon#[25=AT01-08\r\n] 2006.141.07:38:21.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:21.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:21.10#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:38:21.10#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:21.10#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:21.22#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:21.22#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:21.24#ibcon#[25=USB\r\n] 2006.141.07:38:21.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:21.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:21.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:38:21.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:38:21.29$vc4f8/valo=2,572.99 2006.141.07:38:21.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:38:21.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:38:21.29#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:21.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:21.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:21.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:21.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:38:21.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:21.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:21.35#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:38:21.35#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:38:21.35$vc4f8/va=2,7 2006.141.07:38:21.35#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:38:21.35#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:38:21.35#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:21.35#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:21.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:21.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:21.43#ibcon#[25=AT02-07\r\n] 2006.141.07:38:21.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:21.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:21.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:38:21.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:21.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:21.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:21.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:21.62#ibcon#[25=USB\r\n] 2006.141.07:38:21.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:21.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:21.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:38:21.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:38:21.67$vc4f8/valo=3,672.99 2006.141.07:38:21.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:38:21.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:38:21.67#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:21.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:21.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:21.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:21.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:38:21.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:21.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:21.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:38:21.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:38:21.73$vc4f8/va=3,6 2006.141.07:38:21.73#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:38:21.73#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:38:21.73#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:21.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:21.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:21.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:21.81#ibcon#[25=AT03-06\r\n] 2006.141.07:38:21.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:21.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:21.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:38:21.84#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:21.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:21.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:21.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:21.98#ibcon#[25=USB\r\n] 2006.141.07:38:22.01#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:22.01#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:22.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:38:22.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:38:22.01$vc4f8/valo=4,832.99 2006.141.07:38:22.01#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:38:22.01#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:38:22.01#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:22.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:22.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:22.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:22.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:38:22.07#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:22.07#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:22.07#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:38:22.07#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:38:22.07$vc4f8/va=4,7 2006.141.07:38:22.07#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:38:22.07#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:38:22.07#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:22.07#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:22.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:22.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:22.15#ibcon#[25=AT04-07\r\n] 2006.141.07:38:22.18#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:22.18#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:22.18#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:38:22.18#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:22.18#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:22.30#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:22.30#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:22.32#ibcon#[25=USB\r\n] 2006.141.07:38:22.35#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:22.35#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:22.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:38:22.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:38:22.35$vc4f8/valo=5,652.99 2006.141.07:38:22.35#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:38:22.35#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:38:22.35#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:22.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:22.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:22.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:22.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:38:22.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:22.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:22.43#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:38:22.43#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:38:22.43$vc4f8/va=5,7 2006.141.07:38:22.43#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:38:22.43#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:38:22.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:22.43#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:22.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:22.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:22.49#ibcon#[25=AT05-07\r\n] 2006.141.07:38:22.52#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:22.52#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:22.52#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:38:22.52#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:22.52#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:22.64#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:22.64#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:22.66#ibcon#[25=USB\r\n] 2006.141.07:38:22.69#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:22.69#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:22.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:38:22.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:38:22.69$vc4f8/valo=6,772.99 2006.141.07:38:22.69#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:38:22.69#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:38:22.69#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:22.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:22.69#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:22.69#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:22.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:38:22.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:22.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:22.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:38:22.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:38:22.75$vc4f8/va=6,6 2006.141.07:38:22.75#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:38:22.75#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:38:22.75#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:22.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:22.81#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:22.81#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:22.83#ibcon#[25=AT06-06\r\n] 2006.141.07:38:22.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:22.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:22.86#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:38:22.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:22.86#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:38:22.98#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:38:22.98#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:38:23.00#ibcon#[25=USB\r\n] 2006.141.07:38:23.03#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:38:23.03#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:38:23.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:38:23.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:38:23.03$vc4f8/valo=7,832.99 2006.141.07:38:23.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:38:23.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:38:23.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:23.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:38:23.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:38:23.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:38:23.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:38:23.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:38:23.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:38:23.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:38:23.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:38:23.09$vc4f8/va=7,6 2006.141.07:38:23.09#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:38:23.09#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:38:23.09#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:23.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:38:23.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:38:23.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:38:23.17#ibcon#[25=AT07-06\r\n] 2006.141.07:38:23.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:38:23.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:38:23.20#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:38:23.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:23.20#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:38:23.32#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:38:23.32#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:38:23.34#ibcon#[25=USB\r\n] 2006.141.07:38:23.37#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:38:23.37#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:38:23.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:38:23.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:38:23.37$vc4f8/valo=8,852.99 2006.141.07:38:23.37#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:38:23.37#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:38:23.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:23.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:38:23.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:38:23.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:38:23.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:38:23.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:38:23.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:38:23.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:38:23.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:38:23.43$vc4f8/va=8,6 2006.141.07:38:23.43#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:38:23.43#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:38:23.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:23.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:38:23.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:38:23.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:38:23.51#ibcon#[25=AT08-06\r\n] 2006.141.07:38:23.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:38:23.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:38:23.54#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:38:23.54#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:23.54#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:38:23.66#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:38:23.66#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:38:23.68#ibcon#[25=USB\r\n] 2006.141.07:38:23.71#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:38:23.71#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:38:23.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:38:23.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:38:23.71$vc4f8/vblo=1,632.99 2006.141.07:38:23.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:38:23.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:38:23.71#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:23.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:38:23.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:38:23.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:38:23.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:38:23.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:38:23.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:38:23.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:38:23.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:38:23.77$vc4f8/vb=1,4 2006.141.07:38:23.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:38:23.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:38:23.77#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:23.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:38:23.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:38:23.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:38:23.79#ibcon#[27=AT01-04\r\n] 2006.141.07:38:23.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:38:23.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:38:23.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:38:23.82#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:23.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:38:23.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:38:23.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:38:23.97#ibcon#[27=USB\r\n] 2006.141.07:38:24.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:38:24.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:38:24.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:38:24.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:38:24.00$vc4f8/vblo=2,640.99 2006.141.07:38:24.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:38:24.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:38:24.00#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:24.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:24.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:24.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:24.02#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:38:24.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:24.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:38:24.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:38:24.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:38:24.06$vc4f8/vb=2,4 2006.141.07:38:24.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:38:24.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:38:24.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:24.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:24.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:24.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:24.14#ibcon#[27=AT02-04\r\n] 2006.141.07:38:24.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:24.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:38:24.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:38:24.17#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:24.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:24.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:24.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:24.31#ibcon#[27=USB\r\n] 2006.141.07:38:24.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:24.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:38:24.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:38:24.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:38:24.34$vc4f8/vblo=3,656.99 2006.141.07:38:24.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:38:24.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:38:24.34#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:24.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:24.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:24.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:24.36#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:38:24.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:24.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:38:24.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:38:24.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:38:24.40$vc4f8/vb=3,4 2006.141.07:38:24.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:38:24.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:38:24.40#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:24.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:24.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:24.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:24.48#ibcon#[27=AT03-04\r\n] 2006.141.07:38:24.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:24.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:38:24.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:38:24.51#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:24.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:24.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:24.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:24.65#ibcon#[27=USB\r\n] 2006.141.07:38:24.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:24.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:38:24.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:38:24.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:38:24.68$vc4f8/vblo=4,712.99 2006.141.07:38:24.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:38:24.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:38:24.68#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:24.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:24.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:24.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:24.70#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:38:24.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:24.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:38:24.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:38:24.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:38:24.74$vc4f8/vb=4,4 2006.141.07:38:24.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:38:24.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:38:24.74#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:24.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:24.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:24.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:24.82#ibcon#[27=AT04-04\r\n] 2006.141.07:38:24.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:24.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:38:24.85#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:38:24.85#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:24.85#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:24.97#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:24.97#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:24.99#ibcon#[27=USB\r\n] 2006.141.07:38:25.02#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:25.02#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:38:25.02#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:38:25.02#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:38:25.02$vc4f8/vblo=5,744.99 2006.141.07:38:25.02#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:38:25.02#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:38:25.02#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:25.02#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:25.02#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:25.02#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:25.04#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:38:25.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:25.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:38:25.08#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:38:25.08#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:38:25.08$vc4f8/vb=5,4 2006.141.07:38:25.08#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:38:25.08#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:38:25.08#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:25.08#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:25.14#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:25.14#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:25.16#ibcon#[27=AT05-04\r\n] 2006.141.07:38:25.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:25.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:38:25.19#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:38:25.19#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:25.19#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:25.31#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:25.31#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:25.33#ibcon#[27=USB\r\n] 2006.141.07:38:25.36#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:25.36#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:38:25.36#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:38:25.36#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:38:25.36$vc4f8/vblo=6,752.99 2006.141.07:38:25.36#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:38:25.36#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:38:25.36#ibcon#ireg 17 cls_cnt 0 2006.141.07:38:25.36#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:25.36#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:25.36#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:25.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:38:25.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:25.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:38:25.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:38:25.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:38:25.45$vc4f8/vb=6,4 2006.141.07:38:25.45#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:38:25.45#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:38:25.45#ibcon#ireg 11 cls_cnt 2 2006.141.07:38:25.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:25.48#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:25.48#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:25.50#ibcon#[27=AT06-04\r\n] 2006.141.07:38:25.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:25.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:38:25.53#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:38:25.53#ibcon#ireg 7 cls_cnt 0 2006.141.07:38:25.53#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:25.65#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:25.65#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:25.67#ibcon#[27=USB\r\n] 2006.141.07:38:25.70#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:25.70#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:38:25.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:38:25.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:38:25.70$vc4f8/vabw=wide 2006.141.07:38:25.70#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:38:25.70#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:38:25.70#ibcon#ireg 8 cls_cnt 0 2006.141.07:38:25.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:25.70#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:25.70#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:25.72#ibcon#[25=BW32\r\n] 2006.141.07:38:25.75#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:25.75#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:38:25.75#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:38:25.75#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:38:25.75$vc4f8/vbbw=wide 2006.141.07:38:25.75#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:38:25.75#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:38:25.75#ibcon#ireg 8 cls_cnt 0 2006.141.07:38:25.75#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:38:25.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:38:25.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:38:25.84#ibcon#[27=BW32\r\n] 2006.141.07:38:25.87#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:38:25.87#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:38:25.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:38:25.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:38:25.87$4f8m12a/ifd4f 2006.141.07:38:25.87$ifd4f/lo= 2006.141.07:38:25.87$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:38:25.87$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:38:25.87$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:38:25.87$ifd4f/patch= 2006.141.07:38:25.87$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:38:25.87$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:38:25.87$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:38:25.87$4f8m12a/"form=m,16.000,1:2 2006.141.07:38:25.87$4f8m12a/"tpicd 2006.141.07:38:25.87$4f8m12a/echo=off 2006.141.07:38:25.87$4f8m12a/xlog=off 2006.141.07:38:25.87:!2006.141.07:38:50 2006.141.07:38:27.13#trakl#Source acquired 2006.141.07:38:29.13#flagr#flagr/antenna,acquired 2006.141.07:38:50.00:preob 2006.141.07:38:51.13/onsource/TRACKING 2006.141.07:38:51.13:!2006.141.07:39:00 2006.141.07:39:00.00:data_valid=on 2006.141.07:39:00.00:midob 2006.141.07:39:00.13/onsource/TRACKING 2006.141.07:39:00.13/wx/21.86,1012.6,71 2006.141.07:39:00.33/cable/+6.5210E-03 2006.141.07:39:01.42/va/01,08,usb,yes,28,30 2006.141.07:39:01.42/va/02,07,usb,yes,29,30 2006.141.07:39:01.42/va/03,06,usb,yes,30,30 2006.141.07:39:01.42/va/04,07,usb,yes,29,31 2006.141.07:39:01.42/va/05,07,usb,yes,28,29 2006.141.07:39:01.42/va/06,06,usb,yes,27,27 2006.141.07:39:01.42/va/07,06,usb,yes,27,27 2006.141.07:39:01.42/va/08,06,usb,yes,29,29 2006.141.07:39:01.65/valo/01,532.99,yes,locked 2006.141.07:39:01.65/valo/02,572.99,yes,locked 2006.141.07:39:01.65/valo/03,672.99,yes,locked 2006.141.07:39:01.65/valo/04,832.99,yes,locked 2006.141.07:39:01.65/valo/05,652.99,yes,locked 2006.141.07:39:01.65/valo/06,772.99,yes,locked 2006.141.07:39:01.65/valo/07,832.99,yes,locked 2006.141.07:39:01.65/valo/08,852.99,yes,locked 2006.141.07:39:02.74/vb/01,04,usb,yes,29,28 2006.141.07:39:02.74/vb/02,04,usb,yes,31,32 2006.141.07:39:02.74/vb/03,04,usb,yes,27,30 2006.141.07:39:02.74/vb/04,04,usb,yes,28,28 2006.141.07:39:02.74/vb/05,04,usb,yes,26,30 2006.141.07:39:02.74/vb/06,04,usb,yes,27,30 2006.141.07:39:02.74/vb/07,04,usb,yes,29,29 2006.141.07:39:02.74/vb/08,04,usb,yes,27,30 2006.141.07:39:02.97/vblo/01,632.99,yes,locked 2006.141.07:39:02.97/vblo/02,640.99,yes,locked 2006.141.07:39:02.97/vblo/03,656.99,yes,locked 2006.141.07:39:02.97/vblo/04,712.99,yes,locked 2006.141.07:39:02.97/vblo/05,744.99,yes,locked 2006.141.07:39:02.97/vblo/06,752.99,yes,locked 2006.141.07:39:02.97/vblo/07,734.99,yes,locked 2006.141.07:39:02.97/vblo/08,744.99,yes,locked 2006.141.07:39:03.12/vabw/8 2006.141.07:39:03.27/vbbw/8 2006.141.07:39:03.41/xfe/off,on,15.7 2006.141.07:39:03.79/ifatt/23,28,28,28 2006.141.07:39:04.11/fmout-gps/S +1.01E-07 2006.141.07:39:04.19:!2006.141.07:40:00 2006.141.07:40:00.00:data_valid=off 2006.141.07:40:00.00:postob 2006.141.07:40:00.12/cable/+6.5190E-03 2006.141.07:40:00.12/wx/21.83,1012.6,72 2006.141.07:40:01.11/fmout-gps/S +1.02E-07 2006.141.07:40:01.11:scan_name=141-0740,k06141,60 2006.141.07:40:01.11:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.141.07:40:01.14#flagr#flagr/antenna,new-source 2006.141.07:40:02.14:checkk5 2006.141.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:40:02.91/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:40:03.30/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:40:03.68/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:40:04.05/chk_obsdata//k5ts1/T1410739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:40:04.43/chk_obsdata//k5ts2/T1410739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:40:04.80/chk_obsdata//k5ts3/T1410739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:40:05.17/chk_obsdata//k5ts4/T1410739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:40:05.86/k5log//k5ts1_log_newline 2006.141.07:40:06.56/k5log//k5ts2_log_newline 2006.141.07:40:07.25/k5log//k5ts3_log_newline 2006.141.07:40:07.94/k5log//k5ts4_log_newline 2006.141.07:40:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:40:07.96:4f8m12a=1 2006.141.07:40:07.96$4f8m12a/echo=on 2006.141.07:40:07.96$4f8m12a/pcalon 2006.141.07:40:07.96$pcalon/"no phase cal control is implemented here 2006.141.07:40:07.96$4f8m12a/"tpicd=stop 2006.141.07:40:07.96$4f8m12a/vc4f8 2006.141.07:40:07.96$vc4f8/valo=1,532.99 2006.141.07:40:07.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:40:07.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:40:07.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:07.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:07.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:07.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:40:08.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:08.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:08.06#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:40:08.06#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:40:08.06$vc4f8/va=1,8 2006.141.07:40:08.06#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:40:08.06#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:40:08.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:08.06#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:08.06#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:08.06#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:08.10#ibcon#[25=AT01-08\r\n] 2006.141.07:40:08.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:08.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:08.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:40:08.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:08.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:08.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:08.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:08.27#ibcon#[25=USB\r\n] 2006.141.07:40:08.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:08.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:08.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:40:08.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:40:08.30$vc4f8/valo=2,572.99 2006.141.07:40:08.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:40:08.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:40:08.30#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:08.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:08.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:08.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:08.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:40:08.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:08.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:08.38#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:40:08.38#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:40:08.38$vc4f8/va=2,7 2006.141.07:40:08.38#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:40:08.38#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:40:08.38#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:08.38#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:08.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:08.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:08.44#ibcon#[25=AT02-07\r\n] 2006.141.07:40:08.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:08.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:08.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:40:08.47#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:08.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:08.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:08.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:08.61#ibcon#[25=USB\r\n] 2006.141.07:40:08.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:08.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:08.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:40:08.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:40:08.64$vc4f8/valo=3,672.99 2006.141.07:40:08.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:40:08.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:40:08.64#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:08.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:08.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:08.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:08.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:40:08.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:08.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:08.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:40:08.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:40:08.72$vc4f8/va=3,6 2006.141.07:40:08.72#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:40:08.72#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:40:08.72#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:08.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:08.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:08.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:08.78#ibcon#[25=AT03-06\r\n] 2006.141.07:40:08.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:08.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:08.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:40:08.81#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:08.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:08.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:08.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:08.95#ibcon#[25=USB\r\n] 2006.141.07:40:08.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:08.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:08.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:40:08.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:40:08.98$vc4f8/valo=4,832.99 2006.141.07:40:08.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:40:08.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:40:08.98#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:08.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:08.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:08.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:09.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:40:09.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:09.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:09.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:40:09.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:40:09.04$vc4f8/va=4,7 2006.141.07:40:09.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.07:40:09.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.07:40:09.04#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:09.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:09.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:09.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:09.12#ibcon#[25=AT04-07\r\n] 2006.141.07:40:09.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:09.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:09.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.07:40:09.15#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:09.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:09.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:09.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:09.29#ibcon#[25=USB\r\n] 2006.141.07:40:09.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:09.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:09.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:40:09.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:40:09.32$vc4f8/valo=5,652.99 2006.141.07:40:09.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:40:09.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:40:09.32#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:09.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:09.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:09.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:09.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:40:09.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:09.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:09.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:40:09.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:40:09.38$vc4f8/va=5,7 2006.141.07:40:09.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.07:40:09.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.07:40:09.38#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:09.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:09.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:09.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:09.46#ibcon#[25=AT05-07\r\n] 2006.141.07:40:09.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:09.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:09.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.07:40:09.49#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:09.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:09.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:09.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:09.63#ibcon#[25=USB\r\n] 2006.141.07:40:09.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:09.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:09.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:40:09.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:40:09.66$vc4f8/valo=6,772.99 2006.141.07:40:09.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:40:09.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:40:09.66#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:09.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:09.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:09.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:09.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:40:09.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:09.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:09.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:40:09.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:40:09.72$vc4f8/va=6,6 2006.141.07:40:09.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.07:40:09.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.07:40:09.72#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:09.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:09.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:09.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:09.80#ibcon#[25=AT06-06\r\n] 2006.141.07:40:09.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:09.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:09.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.07:40:09.83#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:09.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:40:09.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:40:09.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:40:09.97#ibcon#[25=USB\r\n] 2006.141.07:40:10.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:40:10.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:40:10.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:40:10.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:40:10.00$vc4f8/valo=7,832.99 2006.141.07:40:10.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:40:10.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:40:10.00#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:10.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:40:10.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:40:10.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:40:10.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:40:10.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:40:10.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:40:10.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:40:10.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:40:10.06$vc4f8/va=7,6 2006.141.07:40:10.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:40:10.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:40:10.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:10.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:40:10.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:40:10.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:40:10.14#ibcon#[25=AT07-06\r\n] 2006.141.07:40:10.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:40:10.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:40:10.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:40:10.17#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:10.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:40:10.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:40:10.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:40:10.31#ibcon#[25=USB\r\n] 2006.141.07:40:10.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:40:10.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:40:10.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:40:10.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:40:10.34$vc4f8/valo=8,852.99 2006.141.07:40:10.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:40:10.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:40:10.34#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:10.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:40:10.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:40:10.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:40:10.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:40:10.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:40:10.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:40:10.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:40:10.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:40:10.40$vc4f8/va=8,6 2006.141.07:40:10.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:40:10.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:40:10.40#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:10.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:40:10.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:40:10.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:40:10.48#ibcon#[25=AT08-06\r\n] 2006.141.07:40:10.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:40:10.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:40:10.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:40:10.51#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:10.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:40:10.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:40:10.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:40:10.65#ibcon#[25=USB\r\n] 2006.141.07:40:10.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:40:10.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:40:10.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:40:10.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:40:10.68$vc4f8/vblo=1,632.99 2006.141.07:40:10.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:40:10.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:40:10.68#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:10.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:40:10.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:40:10.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:40:10.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:40:10.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:40:10.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:40:10.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:40:10.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:40:10.74$vc4f8/vb=1,4 2006.141.07:40:10.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:40:10.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:40:10.74#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:10.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:40:10.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:40:10.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:40:10.76#ibcon#[27=AT01-04\r\n] 2006.141.07:40:10.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:40:10.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:40:10.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:40:10.79#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:10.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:40:10.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:40:10.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:40:10.93#ibcon#[27=USB\r\n] 2006.141.07:40:10.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:40:10.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:40:10.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:40:10.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:40:10.96$vc4f8/vblo=2,640.99 2006.141.07:40:10.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:40:10.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:40:10.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:10.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:10.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:10.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:10.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:40:11.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:11.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:40:11.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:40:11.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:40:11.02$vc4f8/vb=2,4 2006.141.07:40:11.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:40:11.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:40:11.02#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:11.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:11.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:11.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:11.10#ibcon#[27=AT02-04\r\n] 2006.141.07:40:11.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:11.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:40:11.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:40:11.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:11.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:11.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:11.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:11.27#ibcon#[27=USB\r\n] 2006.141.07:40:11.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:11.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:40:11.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:40:11.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:40:11.30$vc4f8/vblo=3,656.99 2006.141.07:40:11.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:40:11.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:40:11.30#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:11.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:11.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:11.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:11.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:40:11.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:11.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:40:11.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:40:11.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:40:11.36$vc4f8/vb=3,4 2006.141.07:40:11.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:40:11.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:40:11.36#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:11.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:11.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:11.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:11.44#ibcon#[27=AT03-04\r\n] 2006.141.07:40:11.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:11.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:40:11.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:40:11.47#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:11.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:11.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:11.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:11.61#ibcon#[27=USB\r\n] 2006.141.07:40:11.64#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:11.64#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:40:11.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:40:11.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:40:11.64$vc4f8/vblo=4,712.99 2006.141.07:40:11.64#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:40:11.64#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:40:11.64#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:11.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:11.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:11.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:11.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:40:11.70#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:11.70#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:40:11.70#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:40:11.70#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:40:11.70$vc4f8/vb=4,4 2006.141.07:40:11.70#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:40:11.70#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:40:11.70#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:11.70#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:11.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:11.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:11.78#ibcon#[27=AT04-04\r\n] 2006.141.07:40:11.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:11.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:40:11.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:40:11.81#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:11.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:11.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:11.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:11.95#ibcon#[27=USB\r\n] 2006.141.07:40:11.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:11.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:40:11.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:40:11.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:40:11.98$vc4f8/vblo=5,744.99 2006.141.07:40:11.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:40:11.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:40:11.98#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:11.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:11.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:11.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:12.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:40:12.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:12.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:40:12.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:40:12.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:40:12.04$vc4f8/vb=5,4 2006.141.07:40:12.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.07:40:12.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.07:40:12.04#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:12.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:12.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:12.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:12.12#ibcon#[27=AT05-04\r\n] 2006.141.07:40:12.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:12.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:40:12.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.07:40:12.15#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:12.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:12.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:12.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:12.29#ibcon#[27=USB\r\n] 2006.141.07:40:12.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:12.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:40:12.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:40:12.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:40:12.32$vc4f8/vblo=6,752.99 2006.141.07:40:12.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:40:12.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:40:12.32#ibcon#ireg 17 cls_cnt 0 2006.141.07:40:12.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:12.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:12.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:12.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:40:12.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:12.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:40:12.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:40:12.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:40:12.38$vc4f8/vb=6,4 2006.141.07:40:12.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.07:40:12.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.07:40:12.38#ibcon#ireg 11 cls_cnt 2 2006.141.07:40:12.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:12.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:12.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:12.46#ibcon#[27=AT06-04\r\n] 2006.141.07:40:12.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:12.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:40:12.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.07:40:12.49#ibcon#ireg 7 cls_cnt 0 2006.141.07:40:12.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:12.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:12.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:12.63#ibcon#[27=USB\r\n] 2006.141.07:40:12.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:12.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:40:12.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:40:12.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:40:12.66$vc4f8/vabw=wide 2006.141.07:40:12.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:40:12.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:40:12.66#ibcon#ireg 8 cls_cnt 0 2006.141.07:40:12.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:12.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:12.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:12.68#ibcon#[25=BW32\r\n] 2006.141.07:40:12.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:12.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:40:12.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:40:12.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:40:12.71$vc4f8/vbbw=wide 2006.141.07:40:12.71#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:40:12.71#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:40:12.71#ibcon#ireg 8 cls_cnt 0 2006.141.07:40:12.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:40:12.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:40:12.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:40:12.80#ibcon#[27=BW32\r\n] 2006.141.07:40:12.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:40:12.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:40:12.83#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:40:12.83#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:40:12.83$4f8m12a/ifd4f 2006.141.07:40:12.83$ifd4f/lo= 2006.141.07:40:12.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:40:12.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:40:12.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:40:12.83$ifd4f/patch= 2006.141.07:40:12.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:40:12.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:40:12.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:40:12.83$4f8m12a/"form=m,16.000,1:2 2006.141.07:40:12.83$4f8m12a/"tpicd 2006.141.07:40:12.83$4f8m12a/echo=off 2006.141.07:40:12.83$4f8m12a/xlog=off 2006.141.07:40:12.83:!2006.141.07:40:40 2006.141.07:40:22.14#trakl#Source acquired 2006.141.07:40:22.14#flagr#flagr/antenna,acquired 2006.141.07:40:40.00:preob 2006.141.07:40:41.14/onsource/TRACKING 2006.141.07:40:41.14:!2006.141.07:40:50 2006.141.07:40:50.00:data_valid=on 2006.141.07:40:50.00:midob 2006.141.07:40:50.14/onsource/TRACKING 2006.141.07:40:50.14/wx/21.80,1012.5,71 2006.141.07:40:50.32/cable/+6.5208E-03 2006.141.07:40:51.41/va/01,08,usb,yes,28,30 2006.141.07:40:51.41/va/02,07,usb,yes,28,30 2006.141.07:40:51.41/va/03,06,usb,yes,30,30 2006.141.07:40:51.41/va/04,07,usb,yes,29,31 2006.141.07:40:51.41/va/05,07,usb,yes,28,29 2006.141.07:40:51.41/va/06,06,usb,yes,27,26 2006.141.07:40:51.41/va/07,06,usb,yes,27,27 2006.141.07:40:51.41/va/08,06,usb,yes,29,28 2006.141.07:40:51.64/valo/01,532.99,yes,locked 2006.141.07:40:51.64/valo/02,572.99,yes,locked 2006.141.07:40:51.64/valo/03,672.99,yes,locked 2006.141.07:40:51.64/valo/04,832.99,yes,locked 2006.141.07:40:51.64/valo/05,652.99,yes,locked 2006.141.07:40:51.64/valo/06,772.99,yes,locked 2006.141.07:40:51.64/valo/07,832.99,yes,locked 2006.141.07:40:51.64/valo/08,852.99,yes,locked 2006.141.07:40:52.73/vb/01,04,usb,yes,29,28 2006.141.07:40:52.73/vb/02,04,usb,yes,31,32 2006.141.07:40:52.73/vb/03,04,usb,yes,27,30 2006.141.07:40:52.73/vb/04,04,usb,yes,28,28 2006.141.07:40:52.73/vb/05,04,usb,yes,26,30 2006.141.07:40:52.73/vb/06,04,usb,yes,27,30 2006.141.07:40:52.73/vb/07,04,usb,yes,29,29 2006.141.07:40:52.73/vb/08,04,usb,yes,27,30 2006.141.07:40:52.97/vblo/01,632.99,yes,locked 2006.141.07:40:52.97/vblo/02,640.99,yes,locked 2006.141.07:40:52.97/vblo/03,656.99,yes,locked 2006.141.07:40:52.97/vblo/04,712.99,yes,locked 2006.141.07:40:52.97/vblo/05,744.99,yes,locked 2006.141.07:40:52.97/vblo/06,752.99,yes,locked 2006.141.07:40:52.97/vblo/07,734.99,yes,locked 2006.141.07:40:52.97/vblo/08,744.99,yes,locked 2006.141.07:40:53.12/vabw/8 2006.141.07:40:53.27/vbbw/8 2006.141.07:40:53.36/xfe/off,on,15.0 2006.141.07:40:53.74/ifatt/23,28,28,28 2006.141.07:40:54.11/fmout-gps/S +1.01E-07 2006.141.07:40:54.15:!2006.141.07:41:50 2006.141.07:41:50.00:data_valid=off 2006.141.07:41:50.00:postob 2006.141.07:41:50.24/cable/+6.5216E-03 2006.141.07:41:50.24/wx/21.77,1012.6,72 2006.141.07:41:51.11/fmout-gps/S +1.01E-07 2006.141.07:41:51.11:scan_name=141-0742,k06141,60 2006.141.07:41:51.11:source=1044+719,104827.62,714335.9,2000.0,cw 2006.141.07:41:51.14#flagr#flagr/antenna,new-source 2006.141.07:41:52.14:checkk5 2006.141.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:41:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:41:53.29/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:41:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:41:54.03/chk_obsdata//k5ts1/T1410740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:41:54.41/chk_obsdata//k5ts2/T1410740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:41:54.78/chk_obsdata//k5ts3/T1410740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:41:55.16/chk_obsdata//k5ts4/T1410740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:41:55.85/k5log//k5ts1_log_newline 2006.141.07:41:56.54/k5log//k5ts2_log_newline 2006.141.07:41:57.23/k5log//k5ts3_log_newline 2006.141.07:41:57.93/k5log//k5ts4_log_newline 2006.141.07:41:57.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:41:57.95:4f8m12a=1 2006.141.07:41:57.95$4f8m12a/echo=on 2006.141.07:41:57.95$4f8m12a/pcalon 2006.141.07:41:57.95$pcalon/"no phase cal control is implemented here 2006.141.07:41:57.95$4f8m12a/"tpicd=stop 2006.141.07:41:57.95$4f8m12a/vc4f8 2006.141.07:41:57.95$vc4f8/valo=1,532.99 2006.141.07:41:57.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:41:57.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:41:57.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:57.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:41:57.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:41:57.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:41:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:41:58.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:41:58.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:41:58.06#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:41:58.06#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:41:58.06$vc4f8/va=1,8 2006.141.07:41:58.06#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:41:58.06#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:41:58.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:58.06#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:41:58.06#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:41:58.06#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:41:58.09#ibcon#[25=AT01-08\r\n] 2006.141.07:41:58.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:41:58.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:41:58.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:41:58.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:58.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:41:58.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:41:58.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:41:58.27#ibcon#[25=USB\r\n] 2006.141.07:41:58.32#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:41:58.32#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:41:58.32#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:41:58.32#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:41:58.32$vc4f8/valo=2,572.99 2006.141.07:41:58.32#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:41:58.32#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:41:58.32#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:58.32#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:41:58.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:41:58.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:41:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:41:58.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:41:58.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:41:58.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:41:58.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:41:58.38$vc4f8/va=2,7 2006.141.07:41:58.38#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:41:58.38#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:41:58.38#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:58.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:41:58.44#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:41:58.44#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:41:58.46#ibcon#[25=AT02-07\r\n] 2006.141.07:41:58.51#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:41:58.51#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:41:58.51#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:41:58.51#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:58.51#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:41:58.63#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:41:58.63#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:41:58.65#ibcon#[25=USB\r\n] 2006.141.07:41:58.70#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:41:58.70#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:41:58.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:41:58.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:41:58.70$vc4f8/valo=3,672.99 2006.141.07:41:58.70#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:41:58.70#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:41:58.70#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:58.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:41:58.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:41:58.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:41:58.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:41:58.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:41:58.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:41:58.76#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:41:58.76#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:41:58.76$vc4f8/va=3,6 2006.141.07:41:58.76#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:41:58.76#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:41:58.76#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:58.76#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:41:58.82#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:41:58.82#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:41:58.84#ibcon#[25=AT03-06\r\n] 2006.141.07:41:58.87#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:41:58.87#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:41:58.87#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:41:58.87#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:58.87#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:41:58.99#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:41:58.99#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:41:59.01#ibcon#[25=USB\r\n] 2006.141.07:41:59.04#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:41:59.04#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:41:59.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:41:59.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:41:59.04$vc4f8/valo=4,832.99 2006.141.07:41:59.04#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:41:59.04#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:41:59.04#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:59.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:41:59.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:41:59.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:41:59.06#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:41:59.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:41:59.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:41:59.10#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:41:59.10#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:41:59.10$vc4f8/va=4,7 2006.141.07:41:59.10#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:41:59.10#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:41:59.10#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:59.10#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:41:59.16#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:41:59.16#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:41:59.18#ibcon#[25=AT04-07\r\n] 2006.141.07:41:59.21#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:41:59.21#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:41:59.21#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:41:59.21#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:59.21#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:41:59.33#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:41:59.33#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:41:59.35#ibcon#[25=USB\r\n] 2006.141.07:41:59.38#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:41:59.38#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:41:59.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:41:59.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:41:59.38$vc4f8/valo=5,652.99 2006.141.07:41:59.38#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:41:59.38#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:41:59.38#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:59.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:41:59.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:41:59.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:41:59.40#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:41:59.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:41:59.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:41:59.44#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:41:59.44#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:41:59.44$vc4f8/va=5,7 2006.141.07:41:59.44#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:41:59.44#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:41:59.44#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:59.44#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:41:59.50#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:41:59.50#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:41:59.52#ibcon#[25=AT05-07\r\n] 2006.141.07:41:59.55#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:41:59.55#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:41:59.55#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:41:59.55#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:59.55#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:41:59.67#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:41:59.67#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:41:59.69#ibcon#[25=USB\r\n] 2006.141.07:41:59.72#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:41:59.72#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:41:59.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:41:59.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:41:59.72$vc4f8/valo=6,772.99 2006.141.07:41:59.72#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:41:59.72#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:41:59.72#ibcon#ireg 17 cls_cnt 0 2006.141.07:41:59.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:41:59.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:41:59.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:41:59.74#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:41:59.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:41:59.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:41:59.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:41:59.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:41:59.78$vc4f8/va=6,6 2006.141.07:41:59.78#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:41:59.78#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:41:59.78#ibcon#ireg 11 cls_cnt 2 2006.141.07:41:59.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:41:59.84#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:41:59.84#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:41:59.86#ibcon#[25=AT06-06\r\n] 2006.141.07:41:59.89#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:41:59.89#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:41:59.89#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:41:59.89#ibcon#ireg 7 cls_cnt 0 2006.141.07:41:59.89#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:42:00.01#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:42:00.01#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:42:00.03#ibcon#[25=USB\r\n] 2006.141.07:42:00.06#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:42:00.06#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:42:00.06#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:42:00.06#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:42:00.06$vc4f8/valo=7,832.99 2006.141.07:42:00.06#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:42:00.06#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:42:00.06#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:00.06#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:42:00.06#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:42:00.06#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:42:00.08#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:42:00.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:42:00.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:42:00.12#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:42:00.12#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:42:00.12$vc4f8/va=7,6 2006.141.07:42:00.12#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:42:00.12#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:42:00.12#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:00.12#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:42:00.18#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:42:00.18#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:42:00.20#ibcon#[25=AT07-06\r\n] 2006.141.07:42:00.23#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:42:00.23#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:42:00.23#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:42:00.23#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:00.23#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:42:00.35#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:42:00.35#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:42:00.37#ibcon#[25=USB\r\n] 2006.141.07:42:00.40#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:42:00.40#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:42:00.40#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:42:00.40#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:42:00.40$vc4f8/valo=8,852.99 2006.141.07:42:00.40#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:42:00.40#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:42:00.40#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:00.40#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:42:00.40#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:42:00.40#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:42:00.42#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:42:00.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:42:00.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:42:00.46#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:42:00.46#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:42:00.46$vc4f8/va=8,6 2006.141.07:42:00.46#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:42:00.46#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:42:00.46#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:00.46#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:42:00.52#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:42:00.52#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:42:00.54#ibcon#[25=AT08-06\r\n] 2006.141.07:42:00.57#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:42:00.57#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:42:00.57#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:42:00.57#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:00.57#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:42:00.69#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:42:00.69#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:42:00.71#ibcon#[25=USB\r\n] 2006.141.07:42:00.74#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:42:00.74#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:42:00.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:42:00.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:42:00.74$vc4f8/vblo=1,632.99 2006.141.07:42:00.74#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:42:00.74#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:42:00.74#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:00.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:42:00.74#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:42:00.74#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:42:00.76#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:42:00.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:42:00.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:42:00.80#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:42:00.80#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:42:00.80$vc4f8/vb=1,4 2006.141.07:42:00.80#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:42:00.80#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:42:00.80#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:00.80#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:42:00.80#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:42:00.80#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:42:00.82#ibcon#[27=AT01-04\r\n] 2006.141.07:42:00.86#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:42:00.86#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:42:00.86#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:42:00.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:00.86#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:42:00.98#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:42:00.98#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:42:01.00#ibcon#[27=USB\r\n] 2006.141.07:42:01.03#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:42:01.03#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:42:01.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:42:01.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:42:01.03$vc4f8/vblo=2,640.99 2006.141.07:42:01.03#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:42:01.03#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:42:01.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:01.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:42:01.03#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:42:01.03#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:42:01.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:42:01.09#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:42:01.09#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:42:01.09#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:42:01.09#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:42:01.09$vc4f8/vb=2,4 2006.141.07:42:01.09#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:42:01.09#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:42:01.09#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:01.09#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:42:01.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:42:01.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:42:01.17#ibcon#[27=AT02-04\r\n] 2006.141.07:42:01.20#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:42:01.20#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:42:01.20#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:42:01.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:01.20#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:42:01.32#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:42:01.32#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:42:01.34#ibcon#[27=USB\r\n] 2006.141.07:42:01.37#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:42:01.37#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:42:01.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:42:01.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:42:01.37$vc4f8/vblo=3,656.99 2006.141.07:42:01.37#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:42:01.37#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:42:01.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:01.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:42:01.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:42:01.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:42:01.39#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:42:01.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:42:01.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:42:01.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:42:01.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:42:01.43$vc4f8/vb=3,4 2006.141.07:42:01.43#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:42:01.43#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:42:01.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:01.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:42:01.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:42:01.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:42:01.51#ibcon#[27=AT03-04\r\n] 2006.141.07:42:01.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:42:01.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:42:01.54#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:42:01.54#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:01.54#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:42:01.66#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:42:01.66#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:42:01.68#ibcon#[27=USB\r\n] 2006.141.07:42:01.71#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:42:01.71#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:42:01.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:42:01.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:42:01.71$vc4f8/vblo=4,712.99 2006.141.07:42:01.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:42:01.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:42:01.71#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:01.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:42:01.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:42:01.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:42:01.73#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:42:01.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:42:01.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:42:01.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:42:01.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:42:01.77$vc4f8/vb=4,4 2006.141.07:42:01.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:42:01.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:42:01.77#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:01.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:42:01.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:42:01.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:42:01.85#ibcon#[27=AT04-04\r\n] 2006.141.07:42:01.88#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:42:01.88#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:42:01.88#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:42:01.88#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:01.88#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:42:02.00#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:42:02.00#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:42:02.02#ibcon#[27=USB\r\n] 2006.141.07:42:02.05#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:42:02.05#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:42:02.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:42:02.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:42:02.05$vc4f8/vblo=5,744.99 2006.141.07:42:02.05#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:42:02.05#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:42:02.05#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:02.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:42:02.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:42:02.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:42:02.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:42:02.11#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:42:02.11#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:42:02.11#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:42:02.11#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:42:02.11$vc4f8/vb=5,4 2006.141.07:42:02.11#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:42:02.11#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:42:02.11#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:02.11#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:42:02.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:42:02.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:42:02.19#ibcon#[27=AT05-04\r\n] 2006.141.07:42:02.22#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:42:02.22#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:42:02.22#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:42:02.22#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:02.22#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:42:02.34#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:42:02.34#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:42:02.36#ibcon#[27=USB\r\n] 2006.141.07:42:02.39#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:42:02.39#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:42:02.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:42:02.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:42:02.39$vc4f8/vblo=6,752.99 2006.141.07:42:02.39#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:42:02.39#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:42:02.39#ibcon#ireg 17 cls_cnt 0 2006.141.07:42:02.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:42:02.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:42:02.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:42:02.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:42:02.45#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:42:02.45#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:42:02.45#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:42:02.45#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:42:02.45$vc4f8/vb=6,4 2006.141.07:42:02.45#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:42:02.45#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:42:02.45#ibcon#ireg 11 cls_cnt 2 2006.141.07:42:02.45#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:42:02.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:42:02.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:42:02.53#ibcon#[27=AT06-04\r\n] 2006.141.07:42:02.56#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:42:02.56#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:42:02.56#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:42:02.56#ibcon#ireg 7 cls_cnt 0 2006.141.07:42:02.56#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:42:02.68#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:42:02.68#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:42:02.70#ibcon#[27=USB\r\n] 2006.141.07:42:02.73#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:42:02.73#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:42:02.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:42:02.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:42:02.73$vc4f8/vabw=wide 2006.141.07:42:02.73#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:42:02.73#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:42:02.73#ibcon#ireg 8 cls_cnt 0 2006.141.07:42:02.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:42:02.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:42:02.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:42:02.75#ibcon#[25=BW32\r\n] 2006.141.07:42:02.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:42:02.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:42:02.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:42:02.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:42:02.78$vc4f8/vbbw=wide 2006.141.07:42:02.78#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:42:02.78#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:42:02.78#ibcon#ireg 8 cls_cnt 0 2006.141.07:42:02.78#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:42:02.85#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:42:02.85#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:42:02.87#ibcon#[27=BW32\r\n] 2006.141.07:42:02.90#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:42:02.90#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:42:02.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:42:02.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:42:02.90$4f8m12a/ifd4f 2006.141.07:42:02.90$ifd4f/lo= 2006.141.07:42:02.90$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:42:02.90$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:42:02.90$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:42:02.90$ifd4f/patch= 2006.141.07:42:02.90$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:42:02.90$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:42:02.90$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:42:02.90$4f8m12a/"form=m,16.000,1:2 2006.141.07:42:02.90$4f8m12a/"tpicd 2006.141.07:42:02.90$4f8m12a/echo=off 2006.141.07:42:02.90$4f8m12a/xlog=off 2006.141.07:42:02.90:!2006.141.07:42:30 2006.141.07:42:14.14#trakl#Source acquired 2006.141.07:42:15.14#flagr#flagr/antenna,acquired 2006.141.07:42:30.00:preob 2006.141.07:42:31.14/onsource/TRACKING 2006.141.07:42:31.14:!2006.141.07:42:40 2006.141.07:42:40.00:data_valid=on 2006.141.07:42:40.00:midob 2006.141.07:42:40.14/onsource/TRACKING 2006.141.07:42:40.14/wx/21.76,1012.6,72 2006.141.07:42:40.32/cable/+6.5210E-03 2006.141.07:42:41.41/va/01,08,usb,yes,28,30 2006.141.07:42:41.41/va/02,07,usb,yes,29,30 2006.141.07:42:41.41/va/03,06,usb,yes,30,30 2006.141.07:42:41.41/va/04,07,usb,yes,29,31 2006.141.07:42:41.41/va/05,07,usb,yes,28,29 2006.141.07:42:41.41/va/06,06,usb,yes,27,26 2006.141.07:42:41.41/va/07,06,usb,yes,27,27 2006.141.07:42:41.41/va/08,06,usb,yes,29,29 2006.141.07:42:41.64/valo/01,532.99,yes,locked 2006.141.07:42:41.64/valo/02,572.99,yes,locked 2006.141.07:42:41.64/valo/03,672.99,yes,locked 2006.141.07:42:41.64/valo/04,832.99,yes,locked 2006.141.07:42:41.64/valo/05,652.99,yes,locked 2006.141.07:42:41.64/valo/06,772.99,yes,locked 2006.141.07:42:41.64/valo/07,832.99,yes,locked 2006.141.07:42:41.64/valo/08,852.99,yes,locked 2006.141.07:42:42.73/vb/01,04,usb,yes,29,28 2006.141.07:42:42.73/vb/02,04,usb,yes,31,32 2006.141.07:42:42.73/vb/03,04,usb,yes,27,31 2006.141.07:42:42.73/vb/04,04,usb,yes,28,28 2006.141.07:42:42.73/vb/05,04,usb,yes,26,30 2006.141.07:42:42.73/vb/06,04,usb,yes,27,30 2006.141.07:42:42.73/vb/07,04,usb,yes,29,29 2006.141.07:42:42.73/vb/08,04,usb,yes,27,30 2006.141.07:42:42.96/vblo/01,632.99,yes,locked 2006.141.07:42:42.96/vblo/02,640.99,yes,locked 2006.141.07:42:42.96/vblo/03,656.99,yes,locked 2006.141.07:42:42.96/vblo/04,712.99,yes,locked 2006.141.07:42:42.96/vblo/05,744.99,yes,locked 2006.141.07:42:42.96/vblo/06,752.99,yes,locked 2006.141.07:42:42.96/vblo/07,734.99,yes,locked 2006.141.07:42:42.96/vblo/08,744.99,yes,locked 2006.141.07:42:43.11/vabw/8 2006.141.07:42:43.26/vbbw/8 2006.141.07:42:43.35/xfe/off,on,15.2 2006.141.07:42:43.72/ifatt/23,28,28,28 2006.141.07:42:44.11/fmout-gps/S +1.01E-07 2006.141.07:42:44.15:!2006.141.07:43:40 2006.141.07:43:40.00:data_valid=off 2006.141.07:43:40.00:postob 2006.141.07:43:40.12/cable/+6.5216E-03 2006.141.07:43:40.12/wx/21.74,1012.6,72 2006.141.07:43:41.12/fmout-gps/S +1.01E-07 2006.141.07:43:41.12:scan_name=141-0745,k06141,100 2006.141.07:43:41.12:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.141.07:43:41.14#flagr#flagr/antenna,new-source 2006.141.07:43:42.14:checkk5 2006.141.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:43:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:43:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:43:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:43:44.04/chk_obsdata//k5ts1/T1410742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:43:44.41/chk_obsdata//k5ts2/T1410742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:43:44.78/chk_obsdata//k5ts3/T1410742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:43:45.16/chk_obsdata//k5ts4/T1410742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:43:45.86/k5log//k5ts1_log_newline 2006.141.07:43:46.55/k5log//k5ts2_log_newline 2006.141.07:43:47.24/k5log//k5ts3_log_newline 2006.141.07:43:47.94/k5log//k5ts4_log_newline 2006.141.07:43:47.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:43:47.96:4f8m12a=1 2006.141.07:43:47.96$4f8m12a/echo=on 2006.141.07:43:47.96$4f8m12a/pcalon 2006.141.07:43:47.96$pcalon/"no phase cal control is implemented here 2006.141.07:43:47.96$4f8m12a/"tpicd=stop 2006.141.07:43:47.96$4f8m12a/vc4f8 2006.141.07:43:47.96$vc4f8/valo=1,532.99 2006.141.07:43:47.97#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.07:43:47.97#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.07:43:47.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:47.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:47.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:47.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:48.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:43:48.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:48.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:48.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:43:48.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:43:48.07$vc4f8/va=1,8 2006.141.07:43:48.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.07:43:48.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.07:43:48.07#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:48.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:48.07#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:48.07#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:48.10#ibcon#[25=AT01-08\r\n] 2006.141.07:43:48.14#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:48.14#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:48.14#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.07:43:48.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:48.14#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:48.26#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:48.26#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:48.28#ibcon#[25=USB\r\n] 2006.141.07:43:48.31#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:48.31#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:48.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:43:48.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:43:48.31$vc4f8/valo=2,572.99 2006.141.07:43:48.31#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:43:48.31#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:43:48.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:48.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:48.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:48.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:48.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:43:48.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:48.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:48.39#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:43:48.39#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:43:48.39$vc4f8/va=2,7 2006.141.07:43:48.39#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:43:48.39#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:43:48.39#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:48.39#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:48.43#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:48.43#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:48.45#ibcon#[25=AT02-07\r\n] 2006.141.07:43:48.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:48.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:48.48#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:43:48.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:48.48#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:48.60#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:48.60#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:48.62#ibcon#[25=USB\r\n] 2006.141.07:43:48.65#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:48.65#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:48.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:43:48.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:43:48.65$vc4f8/valo=3,672.99 2006.141.07:43:48.65#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:43:48.65#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:43:48.65#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:48.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:48.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:48.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:48.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:43:48.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:48.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:48.73#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:43:48.73#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:43:48.73$vc4f8/va=3,6 2006.141.07:43:48.73#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:43:48.73#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:43:48.73#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:48.73#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:48.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:48.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:48.79#ibcon#[25=AT03-06\r\n] 2006.141.07:43:48.82#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:48.82#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:48.82#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:43:48.82#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:48.82#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:48.94#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:48.94#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:48.96#ibcon#[25=USB\r\n] 2006.141.07:43:48.99#abcon#<5=/04 4.7 8.9 21.74 721012.6\r\n> 2006.141.07:43:48.99#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:48.99#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:48.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:43:48.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:43:48.99$vc4f8/valo=4,832.99 2006.141.07:43:48.99#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:43:48.99#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:43:48.99#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:48.99#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:43:48.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:43:48.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:43:49.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:43:49.01#abcon#{5=INTERFACE CLEAR} 2006.141.07:43:49.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:43:49.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:43:49.05#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:43:49.05#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:43:49.05$vc4f8/va=4,7 2006.141.07:43:49.05#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:43:49.05#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:43:49.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:49.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:43:49.07#abcon#[5=S1D000X0/0*\r\n] 2006.141.07:43:49.11#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:43:49.11#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:43:49.13#ibcon#[25=AT04-07\r\n] 2006.141.07:43:49.16#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:43:49.16#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:43:49.16#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:43:49.16#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:49.16#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:43:49.28#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:43:49.28#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:43:49.30#ibcon#[25=USB\r\n] 2006.141.07:43:49.33#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:43:49.33#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:43:49.33#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:43:49.33#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:43:49.33$vc4f8/valo=5,652.99 2006.141.07:43:49.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.07:43:49.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.07:43:49.33#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:49.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:49.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:49.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:49.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:43:49.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:49.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:49.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:43:49.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:43:49.39$vc4f8/va=5,7 2006.141.07:43:49.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.07:43:49.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.07:43:49.39#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:49.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:49.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:49.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:49.47#ibcon#[25=AT05-07\r\n] 2006.141.07:43:49.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:49.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:49.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.07:43:49.50#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:49.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:49.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:49.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:49.64#ibcon#[25=USB\r\n] 2006.141.07:43:49.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:49.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:49.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:43:49.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:43:49.67$vc4f8/valo=6,772.99 2006.141.07:43:49.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.07:43:49.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.07:43:49.67#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:49.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:49.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:49.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:49.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:43:49.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:49.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:49.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:43:49.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:43:49.75$vc4f8/va=6,6 2006.141.07:43:49.75#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.07:43:49.75#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.07:43:49.75#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:49.75#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:49.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:49.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:49.81#ibcon#[25=AT06-06\r\n] 2006.141.07:43:49.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:49.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:49.84#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.07:43:49.84#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:49.84#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:43:49.96#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:43:49.96#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:43:49.98#ibcon#[25=USB\r\n] 2006.141.07:43:50.01#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:43:50.01#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:43:50.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:43:50.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:43:50.01$vc4f8/valo=7,832.99 2006.141.07:43:50.01#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.07:43:50.01#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.07:43:50.01#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:50.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:43:50.01#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:43:50.01#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:43:50.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:43:50.07#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:43:50.07#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:43:50.07#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:43:50.07#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:43:50.07$vc4f8/va=7,6 2006.141.07:43:50.07#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.07:43:50.07#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.07:43:50.07#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:50.07#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:43:50.13#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:43:50.13#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:43:50.15#ibcon#[25=AT07-06\r\n] 2006.141.07:43:50.18#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:43:50.18#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:43:50.18#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.07:43:50.18#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:50.18#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:43:50.30#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:43:50.30#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:43:50.32#ibcon#[25=USB\r\n] 2006.141.07:43:50.35#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:43:50.35#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:43:50.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:43:50.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:43:50.35$vc4f8/valo=8,852.99 2006.141.07:43:50.35#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:43:50.35#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:43:50.35#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:50.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:43:50.35#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:43:50.35#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:43:50.37#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:43:50.41#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:43:50.41#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:43:50.41#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:43:50.41#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:43:50.41$vc4f8/va=8,6 2006.141.07:43:50.41#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.07:43:50.41#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.07:43:50.41#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:50.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:43:50.47#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:43:50.47#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:43:50.49#ibcon#[25=AT08-06\r\n] 2006.141.07:43:50.52#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:43:50.52#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:43:50.52#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.07:43:50.52#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:50.52#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:43:50.64#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:43:50.64#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:43:50.66#ibcon#[25=USB\r\n] 2006.141.07:43:50.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:43:50.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:43:50.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:43:50.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:43:50.69$vc4f8/vblo=1,632.99 2006.141.07:43:50.69#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.07:43:50.69#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.07:43:50.69#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:50.69#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:50.69#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:50.69#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:50.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:43:50.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:50.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:43:50.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:43:50.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:43:50.75$vc4f8/vb=1,4 2006.141.07:43:50.75#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.07:43:50.75#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.07:43:50.75#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:50.75#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:50.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:50.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:50.77#ibcon#[27=AT01-04\r\n] 2006.141.07:43:50.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:50.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:43:50.80#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.07:43:50.80#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:50.80#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:50.92#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:50.92#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:50.94#ibcon#[27=USB\r\n] 2006.141.07:43:50.97#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:50.97#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:43:50.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:43:50.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:43:50.97$vc4f8/vblo=2,640.99 2006.141.07:43:50.97#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:43:50.97#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:43:50.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:50.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:50.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:50.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:50.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:43:51.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:51.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:43:51.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:43:51.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:43:51.03$vc4f8/vb=2,4 2006.141.07:43:51.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:43:51.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:43:51.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:51.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:51.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:51.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:51.11#ibcon#[27=AT02-04\r\n] 2006.141.07:43:51.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:51.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:43:51.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:43:51.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:51.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:51.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:51.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:51.28#ibcon#[27=USB\r\n] 2006.141.07:43:51.31#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:51.31#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:43:51.31#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:43:51.31#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:43:51.31$vc4f8/vblo=3,656.99 2006.141.07:43:51.31#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:43:51.31#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:43:51.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:51.31#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:51.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:51.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:51.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:43:51.37#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:51.37#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:43:51.37#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:43:51.37#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:43:51.37$vc4f8/vb=3,4 2006.141.07:43:51.37#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:43:51.37#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:43:51.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:51.37#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:51.43#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:51.43#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:51.45#ibcon#[27=AT03-04\r\n] 2006.141.07:43:51.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:51.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:43:51.48#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:43:51.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:51.48#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:51.60#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:51.60#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:51.62#ibcon#[27=USB\r\n] 2006.141.07:43:51.65#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:51.65#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:43:51.65#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:43:51.65#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:43:51.65$vc4f8/vblo=4,712.99 2006.141.07:43:51.65#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.07:43:51.65#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.07:43:51.65#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:51.65#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:43:51.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:43:51.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:43:51.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:43:51.71#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:43:51.71#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:43:51.71#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:43:51.71#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:43:51.71$vc4f8/vb=4,4 2006.141.07:43:51.71#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.07:43:51.71#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.07:43:51.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:51.71#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:43:51.77#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:43:51.77#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:43:51.79#ibcon#[27=AT04-04\r\n] 2006.141.07:43:51.82#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:43:51.82#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:43:51.82#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.07:43:51.82#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:51.82#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:43:51.94#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:43:51.94#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:43:51.96#ibcon#[27=USB\r\n] 2006.141.07:43:51.99#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:43:51.99#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:43:51.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:43:51.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:43:51.99$vc4f8/vblo=5,744.99 2006.141.07:43:51.99#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.07:43:51.99#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.07:43:51.99#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:51.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:43:51.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:43:51.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:43:52.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:43:52.05#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:43:52.05#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:43:52.05#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:43:52.05#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:43:52.05$vc4f8/vb=5,4 2006.141.07:43:52.05#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.07:43:52.05#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.07:43:52.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:52.05#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:43:52.11#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:43:52.11#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:43:52.13#ibcon#[27=AT05-04\r\n] 2006.141.07:43:52.16#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:43:52.16#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:43:52.16#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.07:43:52.16#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:52.16#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:43:52.28#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:43:52.28#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:43:52.30#ibcon#[27=USB\r\n] 2006.141.07:43:52.33#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:43:52.33#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:43:52.33#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:43:52.33#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:43:52.33$vc4f8/vblo=6,752.99 2006.141.07:43:52.33#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.07:43:52.33#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.07:43:52.33#ibcon#ireg 17 cls_cnt 0 2006.141.07:43:52.33#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:52.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:52.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:52.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:43:52.39#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:52.39#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:43:52.39#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:43:52.39#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:43:52.39$vc4f8/vb=6,4 2006.141.07:43:52.39#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.07:43:52.39#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.07:43:52.39#ibcon#ireg 11 cls_cnt 2 2006.141.07:43:52.39#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:52.45#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:52.45#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:52.47#ibcon#[27=AT06-04\r\n] 2006.141.07:43:52.50#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:52.50#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:43:52.50#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.07:43:52.50#ibcon#ireg 7 cls_cnt 0 2006.141.07:43:52.50#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:52.62#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:52.62#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:52.64#ibcon#[27=USB\r\n] 2006.141.07:43:52.67#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:52.67#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:43:52.67#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:43:52.67#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:43:52.67$vc4f8/vabw=wide 2006.141.07:43:52.67#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.07:43:52.67#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.07:43:52.67#ibcon#ireg 8 cls_cnt 0 2006.141.07:43:52.67#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:52.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:52.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:52.69#ibcon#[25=BW32\r\n] 2006.141.07:43:52.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:52.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:43:52.72#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:43:52.72#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:43:52.72$vc4f8/vbbw=wide 2006.141.07:43:52.72#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:43:52.72#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:43:52.72#ibcon#ireg 8 cls_cnt 0 2006.141.07:43:52.72#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:43:52.79#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:43:52.79#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:43:52.81#ibcon#[27=BW32\r\n] 2006.141.07:43:52.84#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:43:52.84#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:43:52.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:43:52.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:43:52.84$4f8m12a/ifd4f 2006.141.07:43:52.84$ifd4f/lo= 2006.141.07:43:52.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:43:52.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:43:52.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:43:52.84$ifd4f/patch= 2006.141.07:43:52.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:43:52.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:43:52.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:43:52.84$4f8m12a/"form=m,16.000,1:2 2006.141.07:43:52.84$4f8m12a/"tpicd 2006.141.07:43:52.84$4f8m12a/echo=off 2006.141.07:43:52.84$4f8m12a/xlog=off 2006.141.07:43:52.84:!2006.141.07:44:50 2006.141.07:44:30.14#trakl#Source acquired 2006.141.07:44:32.14#flagr#flagr/antenna,acquired 2006.141.07:44:50.00:preob 2006.141.07:44:51.14/onsource/TRACKING 2006.141.07:44:51.14:!2006.141.07:45:00 2006.141.07:45:00.00:data_valid=on 2006.141.07:45:00.00:midob 2006.141.07:45:00.14/onsource/TRACKING 2006.141.07:45:00.14/wx/21.73,1012.6,70 2006.141.07:45:00.29/cable/+6.5218E-03 2006.141.07:45:01.38/va/01,08,usb,yes,30,32 2006.141.07:45:01.38/va/02,07,usb,yes,30,31 2006.141.07:45:01.38/va/03,06,usb,yes,32,32 2006.141.07:45:01.38/va/04,07,usb,yes,31,33 2006.141.07:45:01.38/va/05,07,usb,yes,29,31 2006.141.07:45:01.38/va/06,06,usb,yes,28,28 2006.141.07:45:01.38/va/07,06,usb,yes,29,28 2006.141.07:45:01.38/va/08,06,usb,yes,31,30 2006.141.07:45:01.61/valo/01,532.99,yes,locked 2006.141.07:45:01.61/valo/02,572.99,yes,locked 2006.141.07:45:01.61/valo/03,672.99,yes,locked 2006.141.07:45:01.61/valo/04,832.99,yes,locked 2006.141.07:45:01.61/valo/05,652.99,yes,locked 2006.141.07:45:01.61/valo/06,772.99,yes,locked 2006.141.07:45:01.61/valo/07,832.99,yes,locked 2006.141.07:45:01.61/valo/08,852.99,yes,locked 2006.141.07:45:02.70/vb/01,04,usb,yes,30,29 2006.141.07:45:02.70/vb/02,04,usb,yes,32,33 2006.141.07:45:02.70/vb/03,04,usb,yes,28,32 2006.141.07:45:02.70/vb/04,04,usb,yes,29,29 2006.141.07:45:02.70/vb/05,04,usb,yes,27,31 2006.141.07:45:02.70/vb/06,04,usb,yes,28,31 2006.141.07:45:02.70/vb/07,04,usb,yes,30,30 2006.141.07:45:02.70/vb/08,04,usb,yes,28,31 2006.141.07:45:02.94/vblo/01,632.99,yes,locked 2006.141.07:45:02.94/vblo/02,640.99,yes,locked 2006.141.07:45:02.94/vblo/03,656.99,yes,locked 2006.141.07:45:02.94/vblo/04,712.99,yes,locked 2006.141.07:45:02.94/vblo/05,744.99,yes,locked 2006.141.07:45:02.94/vblo/06,752.99,yes,locked 2006.141.07:45:02.94/vblo/07,734.99,yes,locked 2006.141.07:45:02.94/vblo/08,744.99,yes,locked 2006.141.07:45:03.09/vabw/8 2006.141.07:45:03.24/vbbw/8 2006.141.07:45:03.33/xfe/off,on,15.5 2006.141.07:45:03.71/ifatt/23,28,28,28 2006.141.07:45:04.12/fmout-gps/S +1.01E-07 2006.141.07:45:04.16:!2006.141.07:46:40 2006.141.07:46:40.00:data_valid=off 2006.141.07:46:40.00:postob 2006.141.07:46:40.17/cable/+6.5228E-03 2006.141.07:46:40.17/wx/21.70,1012.7,72 2006.141.07:46:41.11/fmout-gps/S +1.01E-07 2006.141.07:46:41.11:scan_name=141-0748,k06141,60 2006.141.07:46:41.11:source=0955+476,095819.67,472507.8,2000.0,cw 2006.141.07:46:42.13#flagr#flagr/antenna,new-source 2006.141.07:46:42.13:checkk5 2006.141.07:46:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:46:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:46:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:46:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:46:44.03/chk_obsdata//k5ts1/T1410745??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.141.07:46:44.40/chk_obsdata//k5ts2/T1410745??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.141.07:46:44.77/chk_obsdata//k5ts3/T1410745??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.141.07:46:45.15/chk_obsdata//k5ts4/T1410745??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.141.07:46:45.85/k5log//k5ts1_log_newline 2006.141.07:46:46.56/k5log//k5ts2_log_newline 2006.141.07:46:47.27/k5log//k5ts3_log_newline 2006.141.07:46:47.98/k5log//k5ts4_log_newline 2006.141.07:46:48.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:46:48.00:4f8m12a=1 2006.141.07:46:48.00$4f8m12a/echo=on 2006.141.07:46:48.00$4f8m12a/pcalon 2006.141.07:46:48.00$pcalon/"no phase cal control is implemented here 2006.141.07:46:48.00$4f8m12a/"tpicd=stop 2006.141.07:46:48.00$4f8m12a/vc4f8 2006.141.07:46:48.00$vc4f8/valo=1,532.99 2006.141.07:46:48.01#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:46:48.01#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:46:48.01#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:48.01#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:48.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:48.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:48.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:46:48.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:48.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:48.11#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:46:48.11#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:46:48.11$vc4f8/va=1,8 2006.141.07:46:48.11#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:46:48.11#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:46:48.11#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:48.11#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:48.11#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:48.11#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:48.14#ibcon#[25=AT01-08\r\n] 2006.141.07:46:48.18#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:48.18#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:48.18#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:46:48.18#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:48.18#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:48.30#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:48.30#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:48.32#ibcon#[25=USB\r\n] 2006.141.07:46:48.37#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:48.37#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:48.37#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:46:48.37#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:46:48.37$vc4f8/valo=2,572.99 2006.141.07:46:48.37#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:46:48.37#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:46:48.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:48.37#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:48.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:48.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:48.39#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:46:48.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:48.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:48.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:46:48.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:46:48.43$vc4f8/va=2,7 2006.141.07:46:48.43#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:46:48.43#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:46:48.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:48.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:48.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:48.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:48.51#ibcon#[25=AT02-07\r\n] 2006.141.07:46:48.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:48.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:48.56#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:46:48.56#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:48.56#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:48.68#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:48.68#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:48.70#ibcon#[25=USB\r\n] 2006.141.07:46:48.75#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:48.75#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:48.75#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:46:48.75#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:46:48.75$vc4f8/valo=3,672.99 2006.141.07:46:48.75#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:46:48.75#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:46:48.75#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:48.75#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:48.75#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:48.75#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:48.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:46:48.81#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:48.81#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:48.81#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:46:48.81#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:46:48.81$vc4f8/va=3,6 2006.141.07:46:48.81#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:46:48.81#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:46:48.81#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:48.81#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:48.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:48.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:48.89#ibcon#[25=AT03-06\r\n] 2006.141.07:46:48.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:48.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:48.92#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:46:48.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:48.92#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:49.04#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:49.04#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:49.06#ibcon#[25=USB\r\n] 2006.141.07:46:49.09#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:49.09#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:49.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:46:49.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:46:49.09$vc4f8/valo=4,832.99 2006.141.07:46:49.09#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:46:49.09#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:46:49.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:49.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:49.09#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:49.09#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:49.11#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:46:49.15#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:49.15#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:49.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:46:49.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:46:49.15$vc4f8/va=4,7 2006.141.07:46:49.15#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:46:49.15#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:46:49.15#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:49.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:49.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:49.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:49.23#ibcon#[25=AT04-07\r\n] 2006.141.07:46:49.26#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:49.26#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:49.26#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:46:49.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:49.26#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:49.38#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:49.38#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:49.40#ibcon#[25=USB\r\n] 2006.141.07:46:49.43#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:49.43#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:49.43#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:46:49.43#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:46:49.43$vc4f8/valo=5,652.99 2006.141.07:46:49.43#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:46:49.43#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:46:49.43#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:49.43#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:46:49.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:46:49.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:46:49.45#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:46:49.49#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:46:49.49#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:46:49.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:46:49.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:46:49.49$vc4f8/va=5,7 2006.141.07:46:49.49#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.07:46:49.49#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.07:46:49.49#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:49.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:46:49.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:46:49.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:46:49.57#ibcon#[25=AT05-07\r\n] 2006.141.07:46:49.60#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:46:49.60#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:46:49.60#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.07:46:49.60#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:49.60#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:46:49.72#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:46:49.72#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:46:49.74#ibcon#[25=USB\r\n] 2006.141.07:46:49.77#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:46:49.77#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:46:49.77#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:46:49.77#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:46:49.77$vc4f8/valo=6,772.99 2006.141.07:46:49.77#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.07:46:49.77#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.07:46:49.77#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:49.77#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:49.77#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:49.77#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:49.79#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:46:49.83#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:49.83#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:49.83#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:46:49.83#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:46:49.83$vc4f8/va=6,6 2006.141.07:46:49.83#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.07:46:49.83#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.07:46:49.83#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:49.83#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:49.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:49.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:49.91#ibcon#[25=AT06-06\r\n] 2006.141.07:46:49.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:49.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:49.94#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.07:46:49.94#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:49.94#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:50.06#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:50.06#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:50.08#ibcon#[25=USB\r\n] 2006.141.07:46:50.11#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:50.11#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:50.11#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:46:50.11#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:46:50.11$vc4f8/valo=7,832.99 2006.141.07:46:50.11#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:46:50.11#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:46:50.11#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:50.11#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:50.11#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:50.11#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:50.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:46:50.17#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:50.17#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:50.17#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:46:50.17#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:46:50.17$vc4f8/va=7,6 2006.141.07:46:50.17#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.07:46:50.17#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.07:46:50.17#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:50.17#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:50.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:50.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:50.25#ibcon#[25=AT07-06\r\n] 2006.141.07:46:50.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:50.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:50.28#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.07:46:50.28#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:50.28#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:46:50.40#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:46:50.40#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:46:50.42#ibcon#[25=USB\r\n] 2006.141.07:46:50.45#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:46:50.45#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:46:50.45#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:46:50.45#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:46:50.45$vc4f8/valo=8,852.99 2006.141.07:46:50.45#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.07:46:50.45#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.07:46:50.45#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:50.45#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:46:50.45#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:46:50.45#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:46:50.47#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:46:50.51#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:46:50.51#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:46:50.51#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:46:50.51#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:46:50.51$vc4f8/va=8,6 2006.141.07:46:50.51#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.07:46:50.51#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.07:46:50.51#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:50.51#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:46:50.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:46:50.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:46:50.59#ibcon#[25=AT08-06\r\n] 2006.141.07:46:50.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:46:50.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:46:50.62#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.07:46:50.62#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:50.62#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:46:50.74#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:46:50.74#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:46:50.76#ibcon#[25=USB\r\n] 2006.141.07:46:50.81#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:46:50.81#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:46:50.81#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:46:50.81#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:46:50.81$vc4f8/vblo=1,632.99 2006.141.07:46:50.81#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.07:46:50.81#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.07:46:50.81#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:50.81#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:46:50.81#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:46:50.81#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:46:50.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:46:50.87#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:46:50.87#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:46:50.87#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:46:50.87#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:46:50.87$vc4f8/vb=1,4 2006.141.07:46:50.87#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.07:46:50.87#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.07:46:50.87#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:50.87#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:46:50.87#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:46:50.87#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:46:50.89#ibcon#[27=AT01-04\r\n] 2006.141.07:46:50.92#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:46:50.92#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:46:50.92#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.07:46:50.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:50.92#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:46:51.04#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:46:51.04#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:46:51.06#ibcon#[27=USB\r\n] 2006.141.07:46:51.09#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:46:51.09#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:46:51.09#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:46:51.09#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:46:51.09$vc4f8/vblo=2,640.99 2006.141.07:46:51.09#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:46:51.09#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:46:51.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:51.09#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:51.09#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:51.09#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:51.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:46:51.15#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:51.15#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:46:51.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:46:51.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:46:51.15$vc4f8/vb=2,4 2006.141.07:46:51.15#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:46:51.15#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:46:51.15#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:51.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:51.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:51.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:51.23#ibcon#[27=AT02-04\r\n] 2006.141.07:46:51.26#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:51.26#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:46:51.26#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:46:51.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:51.26#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:51.38#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:51.38#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:51.40#ibcon#[27=USB\r\n] 2006.141.07:46:51.45#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:51.45#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:46:51.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:46:51.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:46:51.45$vc4f8/vblo=3,656.99 2006.141.07:46:51.45#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:46:51.45#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:46:51.45#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:51.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:51.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:51.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:51.47#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:46:51.51#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:51.51#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:46:51.51#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:46:51.51#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:46:51.51$vc4f8/vb=3,4 2006.141.07:46:51.51#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:46:51.51#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:46:51.51#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:51.51#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:51.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:51.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:51.59#ibcon#[27=AT03-04\r\n] 2006.141.07:46:51.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:51.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:46:51.62#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:46:51.62#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:51.62#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:51.74#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:51.74#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:51.76#ibcon#[27=USB\r\n] 2006.141.07:46:51.79#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:51.79#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:46:51.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:46:51.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:46:51.79$vc4f8/vblo=4,712.99 2006.141.07:46:51.79#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:46:51.79#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:46:51.79#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:51.79#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:51.79#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:51.79#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:51.81#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:46:51.85#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:51.85#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:46:51.85#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:46:51.85#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:46:51.85$vc4f8/vb=4,4 2006.141.07:46:51.85#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:46:51.85#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:46:51.85#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:51.85#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:51.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:51.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:51.93#ibcon#[27=AT04-04\r\n] 2006.141.07:46:51.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:51.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:46:51.96#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:46:51.96#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:51.96#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:52.08#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:52.08#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:52.10#ibcon#[27=USB\r\n] 2006.141.07:46:52.13#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:52.13#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:46:52.13#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:46:52.13#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:46:52.13$vc4f8/vblo=5,744.99 2006.141.07:46:52.13#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:46:52.13#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:46:52.13#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:52.13#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:52.13#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:52.13#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:52.15#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:46:52.19#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:52.19#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:46:52.19#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:46:52.19#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:46:52.19$vc4f8/vb=5,4 2006.141.07:46:52.19#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:46:52.19#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:46:52.19#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:52.19#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:52.25#abcon#<5=/05 4.8 8.3 21.69 711012.7\r\n> 2006.141.07:46:52.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:52.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:52.27#ibcon#[27=AT05-04\r\n] 2006.141.07:46:52.27#abcon#{5=INTERFACE CLEAR} 2006.141.07:46:52.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:52.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:46:52.30#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:46:52.30#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:52.30#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:52.33#abcon#[5=S1D000X0/0*\r\n] 2006.141.07:46:52.42#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:52.42#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:52.44#ibcon#[27=USB\r\n] 2006.141.07:46:52.47#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:52.47#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:46:52.47#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:46:52.47#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:46:52.47$vc4f8/vblo=6,752.99 2006.141.07:46:52.47#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.07:46:52.47#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.07:46:52.47#ibcon#ireg 17 cls_cnt 0 2006.141.07:46:52.47#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:52.47#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:52.47#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:52.49#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:46:52.53#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:52.53#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:46:52.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:46:52.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:46:52.53$vc4f8/vb=6,4 2006.141.07:46:52.53#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.07:46:52.53#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.07:46:52.53#ibcon#ireg 11 cls_cnt 2 2006.141.07:46:52.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:52.59#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:52.59#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:52.61#ibcon#[27=AT06-04\r\n] 2006.141.07:46:52.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:52.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:46:52.64#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.07:46:52.64#ibcon#ireg 7 cls_cnt 0 2006.141.07:46:52.64#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:52.76#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:52.76#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:52.78#ibcon#[27=USB\r\n] 2006.141.07:46:52.81#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:52.81#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:46:52.81#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:46:52.81#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:46:52.81$vc4f8/vabw=wide 2006.141.07:46:52.81#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:46:52.81#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:46:52.81#ibcon#ireg 8 cls_cnt 0 2006.141.07:46:52.81#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:52.81#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:52.81#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:52.83#ibcon#[25=BW32\r\n] 2006.141.07:46:52.86#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:52.86#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:46:52.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:46:52.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:46:52.86$vc4f8/vbbw=wide 2006.141.07:46:52.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:46:52.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:46:52.86#ibcon#ireg 8 cls_cnt 0 2006.141.07:46:52.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:46:52.93#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:46:52.93#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:46:52.95#ibcon#[27=BW32\r\n] 2006.141.07:46:52.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:46:52.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:46:52.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:46:52.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:46:52.98$4f8m12a/ifd4f 2006.141.07:46:52.98$ifd4f/lo= 2006.141.07:46:52.98$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:46:52.98$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:46:52.98$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:46:52.98$ifd4f/patch= 2006.141.07:46:52.98$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:46:52.98$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:46:52.98$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:46:52.98$4f8m12a/"form=m,16.000,1:2 2006.141.07:46:52.98$4f8m12a/"tpicd 2006.141.07:46:52.98$4f8m12a/echo=off 2006.141.07:46:52.98$4f8m12a/xlog=off 2006.141.07:46:52.98:!2006.141.07:48:00 2006.141.07:47:37.13#trakl#Source acquired 2006.141.07:47:37.13#flagr#flagr/antenna,acquired 2006.141.07:48:00.00:preob 2006.141.07:48:00.13/onsource/TRACKING 2006.141.07:48:00.13:!2006.141.07:48:10 2006.141.07:48:10.00:data_valid=on 2006.141.07:48:10.00:midob 2006.141.07:48:10.14/onsource/TRACKING 2006.141.07:48:10.14/wx/21.68,1012.7,71 2006.141.07:48:10.28/cable/+6.5189E-03 2006.141.07:48:11.37/va/01,08,usb,yes,28,30 2006.141.07:48:11.37/va/02,07,usb,yes,28,30 2006.141.07:48:11.37/va/03,06,usb,yes,30,30 2006.141.07:48:11.37/va/04,07,usb,yes,29,31 2006.141.07:48:11.37/va/05,07,usb,yes,28,29 2006.141.07:48:11.37/va/06,06,usb,yes,27,27 2006.141.07:48:11.37/va/07,06,usb,yes,27,27 2006.141.07:48:11.37/va/08,06,usb,yes,29,29 2006.141.07:48:11.60/valo/01,532.99,yes,locked 2006.141.07:48:11.60/valo/02,572.99,yes,locked 2006.141.07:48:11.60/valo/03,672.99,yes,locked 2006.141.07:48:11.60/valo/04,832.99,yes,locked 2006.141.07:48:11.60/valo/05,652.99,yes,locked 2006.141.07:48:11.60/valo/06,772.99,yes,locked 2006.141.07:48:11.60/valo/07,832.99,yes,locked 2006.141.07:48:11.60/valo/08,852.99,yes,locked 2006.141.07:48:12.69/vb/01,04,usb,yes,28,27 2006.141.07:48:12.69/vb/02,04,usb,yes,30,31 2006.141.07:48:12.69/vb/03,04,usb,yes,26,30 2006.141.07:48:12.69/vb/04,04,usb,yes,27,27 2006.141.07:48:12.69/vb/05,04,usb,yes,26,30 2006.141.07:48:12.69/vb/06,04,usb,yes,27,30 2006.141.07:48:12.69/vb/07,04,usb,yes,29,29 2006.141.07:48:12.69/vb/08,04,usb,yes,26,30 2006.141.07:48:12.92/vblo/01,632.99,yes,locked 2006.141.07:48:12.92/vblo/02,640.99,yes,locked 2006.141.07:48:12.92/vblo/03,656.99,yes,locked 2006.141.07:48:12.92/vblo/04,712.99,yes,locked 2006.141.07:48:12.92/vblo/05,744.99,yes,locked 2006.141.07:48:12.92/vblo/06,752.99,yes,locked 2006.141.07:48:12.92/vblo/07,734.99,yes,locked 2006.141.07:48:12.92/vblo/08,744.99,yes,locked 2006.141.07:48:13.07/vabw/8 2006.141.07:48:13.22/vbbw/8 2006.141.07:48:13.31/xfe/off,on,15.0 2006.141.07:48:13.69/ifatt/23,28,28,28 2006.141.07:48:14.11/fmout-gps/S +1.02E-07 2006.141.07:48:14.15:!2006.141.07:49:10 2006.141.07:49:10.00:data_valid=off 2006.141.07:49:10.00:postob 2006.141.07:49:10.09/cable/+6.5196E-03 2006.141.07:49:10.09/wx/21.67,1012.7,72 2006.141.07:49:11.12/fmout-gps/S +1.03E-07 2006.141.07:49:11.12:scan_name=141-0750,k06141,60 2006.141.07:49:11.12:source=1357+769,135755.37,764321.1,2000.0,cw 2006.141.07:49:11.14#flagr#flagr/antenna,new-source 2006.141.07:49:12.14:checkk5 2006.141.07:49:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:49:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:49:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:49:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:49:14.03/chk_obsdata//k5ts1/T1410748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:49:14.40/chk_obsdata//k5ts2/T1410748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:49:14.78/chk_obsdata//k5ts3/T1410748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:49:15.15/chk_obsdata//k5ts4/T1410748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:49:15.84/k5log//k5ts1_log_newline 2006.141.07:49:16.53/k5log//k5ts2_log_newline 2006.141.07:49:17.22/k5log//k5ts3_log_newline 2006.141.07:49:17.92/k5log//k5ts4_log_newline 2006.141.07:49:17.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:49:17.94:4f8m12a=1 2006.141.07:49:17.94$4f8m12a/echo=on 2006.141.07:49:17.94$4f8m12a/pcalon 2006.141.07:49:17.95$pcalon/"no phase cal control is implemented here 2006.141.07:49:17.95$4f8m12a/"tpicd=stop 2006.141.07:49:17.95$4f8m12a/vc4f8 2006.141.07:49:17.95$vc4f8/valo=1,532.99 2006.141.07:49:17.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:49:17.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:49:17.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:17.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:17.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:17.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:49:18.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:18.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:18.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:49:18.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:49:18.05$vc4f8/va=1,8 2006.141.07:49:18.05#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:49:18.05#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:49:18.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:18.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:18.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:18.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:18.09#ibcon#[25=AT01-08\r\n] 2006.141.07:49:18.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:18.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:18.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:49:18.12#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:18.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:18.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:18.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:18.26#ibcon#[25=USB\r\n] 2006.141.07:49:18.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:18.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:18.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:49:18.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:49:18.31$vc4f8/valo=2,572.99 2006.141.07:49:18.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:49:18.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:49:18.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:18.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:18.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:18.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:18.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:49:18.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:18.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:18.37#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:49:18.37#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:49:18.37$vc4f8/va=2,7 2006.141.07:49:18.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:49:18.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:49:18.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:18.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:18.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:18.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:18.45#ibcon#[25=AT02-07\r\n] 2006.141.07:49:18.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:18.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:18.50#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:49:18.50#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:18.50#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:18.62#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:18.62#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:18.64#ibcon#[25=USB\r\n] 2006.141.07:49:18.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:18.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:18.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:49:18.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:49:18.69$vc4f8/valo=3,672.99 2006.141.07:49:18.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:49:18.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:49:18.69#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:18.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:18.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:18.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:18.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:49:18.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:18.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:18.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:49:18.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:49:18.75$vc4f8/va=3,6 2006.141.07:49:18.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:49:18.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:49:18.75#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:18.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:18.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:18.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:18.83#ibcon#[25=AT03-06\r\n] 2006.141.07:49:18.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:18.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:18.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:49:18.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:18.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:18.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:18.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:19.00#ibcon#[25=USB\r\n] 2006.141.07:49:19.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:19.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:19.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:49:19.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:49:19.03$vc4f8/valo=4,832.99 2006.141.07:49:19.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:49:19.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:49:19.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:19.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:19.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:19.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:19.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:49:19.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:19.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:19.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:49:19.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:49:19.09$vc4f8/va=4,7 2006.141.07:49:19.09#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:49:19.09#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:49:19.09#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:19.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:19.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:19.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:19.17#ibcon#[25=AT04-07\r\n] 2006.141.07:49:19.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:19.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:19.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:49:19.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:19.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:19.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:19.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:19.34#ibcon#[25=USB\r\n] 2006.141.07:49:19.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:19.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:19.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:49:19.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:49:19.37$vc4f8/valo=5,652.99 2006.141.07:49:19.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:49:19.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:49:19.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:19.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:19.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:19.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:19.41#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:49:19.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:19.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:19.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:49:19.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:49:19.46$vc4f8/va=5,7 2006.141.07:49:19.46#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:49:19.46#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:49:19.46#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:19.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:19.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:19.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:19.51#ibcon#[25=AT05-07\r\n] 2006.141.07:49:19.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:19.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:19.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:49:19.54#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:19.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:19.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:19.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:19.68#ibcon#[25=USB\r\n] 2006.141.07:49:19.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:19.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:19.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:49:19.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:49:19.71$vc4f8/valo=6,772.99 2006.141.07:49:19.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:49:19.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:49:19.71#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:19.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:19.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:19.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:19.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:49:19.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:19.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:19.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:49:19.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:49:19.77$vc4f8/va=6,6 2006.141.07:49:19.77#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.07:49:19.77#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.07:49:19.77#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:19.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:19.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:19.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:19.85#ibcon#[25=AT06-06\r\n] 2006.141.07:49:19.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:19.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:19.88#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.07:49:19.88#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:19.88#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:49:20.00#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:49:20.00#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:49:20.02#ibcon#[25=USB\r\n] 2006.141.07:49:20.05#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:49:20.05#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:49:20.05#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:49:20.05#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:49:20.05$vc4f8/valo=7,832.99 2006.141.07:49:20.05#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:49:20.05#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:49:20.05#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:20.05#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:49:20.05#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:49:20.05#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:49:20.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:49:20.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:49:20.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:49:20.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:49:20.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:49:20.11$vc4f8/va=7,6 2006.141.07:49:20.11#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.07:49:20.11#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.07:49:20.11#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:20.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:49:20.17#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:49:20.17#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:49:20.19#ibcon#[25=AT07-06\r\n] 2006.141.07:49:20.22#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:49:20.22#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:49:20.22#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.07:49:20.22#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:20.22#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:49:20.34#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:49:20.34#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:49:20.36#ibcon#[25=USB\r\n] 2006.141.07:49:20.39#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:49:20.39#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:49:20.39#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:49:20.39#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:49:20.39$vc4f8/valo=8,852.99 2006.141.07:49:20.39#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:49:20.39#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:49:20.39#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:20.39#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:49:20.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:49:20.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:49:20.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:49:20.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:49:20.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:49:20.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:49:20.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:49:20.45$vc4f8/va=8,6 2006.141.07:49:20.45#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.07:49:20.45#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.07:49:20.45#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:20.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:49:20.51#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:49:20.51#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:49:20.53#ibcon#[25=AT08-06\r\n] 2006.141.07:49:20.56#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:49:20.56#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:49:20.56#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.07:49:20.56#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:20.56#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:49:20.68#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:49:20.68#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:49:20.70#ibcon#[25=USB\r\n] 2006.141.07:49:20.73#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:49:20.73#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:49:20.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:49:20.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:49:20.73$vc4f8/vblo=1,632.99 2006.141.07:49:20.73#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:49:20.73#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:49:20.73#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:20.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:49:20.73#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:49:20.73#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:49:20.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:49:20.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:49:20.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:49:20.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:49:20.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:49:20.79$vc4f8/vb=1,4 2006.141.07:49:20.79#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:49:20.79#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:49:20.79#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:20.79#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:49:20.79#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:49:20.79#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:49:20.81#ibcon#[27=AT01-04\r\n] 2006.141.07:49:20.84#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:49:20.84#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:49:20.84#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:49:20.84#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:20.84#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:49:20.96#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:49:20.96#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:49:20.98#ibcon#[27=USB\r\n] 2006.141.07:49:21.01#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:49:21.01#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:49:21.01#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:49:21.01#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:49:21.01$vc4f8/vblo=2,640.99 2006.141.07:49:21.01#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:49:21.01#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:49:21.01#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:21.01#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:21.01#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:21.01#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:21.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:49:21.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:21.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:49:21.07#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:49:21.07#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:49:21.07$vc4f8/vb=2,4 2006.141.07:49:21.07#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:49:21.07#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:49:21.07#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:21.07#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:21.13#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:21.13#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:21.15#ibcon#[27=AT02-04\r\n] 2006.141.07:49:21.18#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:21.18#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:49:21.18#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:49:21.18#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:21.18#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:21.30#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:21.30#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:21.32#ibcon#[27=USB\r\n] 2006.141.07:49:21.35#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:21.35#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:49:21.35#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:49:21.35#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:49:21.35$vc4f8/vblo=3,656.99 2006.141.07:49:21.35#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:49:21.35#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:49:21.35#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:21.35#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:21.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:21.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:21.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:49:21.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:21.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:49:21.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:49:21.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:49:21.41$vc4f8/vb=3,4 2006.141.07:49:21.41#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:49:21.41#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:49:21.41#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:21.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:21.47#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:21.47#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:21.49#ibcon#[27=AT03-04\r\n] 2006.141.07:49:21.52#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:21.52#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:49:21.52#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:49:21.52#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:21.52#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:21.64#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:21.64#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:21.66#ibcon#[27=USB\r\n] 2006.141.07:49:21.69#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:21.69#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:49:21.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:49:21.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:49:21.69$vc4f8/vblo=4,712.99 2006.141.07:49:21.69#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:49:21.69#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:49:21.69#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:21.69#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:21.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:21.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:21.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:49:21.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:21.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:49:21.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:49:21.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:49:21.75$vc4f8/vb=4,4 2006.141.07:49:21.75#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:49:21.75#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:49:21.75#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:21.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:21.81#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:21.81#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:21.83#ibcon#[27=AT04-04\r\n] 2006.141.07:49:21.86#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:21.86#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:49:21.86#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:49:21.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:21.86#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:21.98#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:21.98#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:22.00#ibcon#[27=USB\r\n] 2006.141.07:49:22.03#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:22.03#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:49:22.03#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:49:22.03#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:49:22.03$vc4f8/vblo=5,744.99 2006.141.07:49:22.03#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:49:22.03#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:49:22.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:22.03#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:22.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:22.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:22.07#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:49:22.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:22.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:49:22.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:49:22.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:49:22.12$vc4f8/vb=5,4 2006.141.07:49:22.12#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:49:22.12#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:49:22.12#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:22.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:22.15#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:22.15#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:22.17#ibcon#[27=AT05-04\r\n] 2006.141.07:49:22.20#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:22.20#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:49:22.20#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:49:22.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:22.20#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:22.32#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:22.32#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:22.34#ibcon#[27=USB\r\n] 2006.141.07:49:22.37#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:22.37#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:49:22.37#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:49:22.37#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:49:22.37$vc4f8/vblo=6,752.99 2006.141.07:49:22.37#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:49:22.37#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:49:22.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:49:22.37#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:22.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:22.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:22.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:49:22.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:22.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:49:22.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:49:22.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:49:22.43$vc4f8/vb=6,4 2006.141.07:49:22.43#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:49:22.43#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:49:22.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:49:22.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:22.49#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:22.49#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:22.51#ibcon#[27=AT06-04\r\n] 2006.141.07:49:22.54#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:22.54#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:49:22.54#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:49:22.54#ibcon#ireg 7 cls_cnt 0 2006.141.07:49:22.54#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:22.66#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:22.66#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:22.68#ibcon#[27=USB\r\n] 2006.141.07:49:22.71#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:22.71#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:49:22.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:49:22.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:49:22.71$vc4f8/vabw=wide 2006.141.07:49:22.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:49:22.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:49:22.71#ibcon#ireg 8 cls_cnt 0 2006.141.07:49:22.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:22.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:22.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:22.73#ibcon#[25=BW32\r\n] 2006.141.07:49:22.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:22.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:49:22.76#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:49:22.76#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:49:22.76$vc4f8/vbbw=wide 2006.141.07:49:22.76#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.07:49:22.76#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.07:49:22.76#ibcon#ireg 8 cls_cnt 0 2006.141.07:49:22.76#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:49:22.83#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:49:22.83#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:49:22.85#ibcon#[27=BW32\r\n] 2006.141.07:49:22.88#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:49:22.88#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:49:22.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:49:22.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:49:22.88$4f8m12a/ifd4f 2006.141.07:49:22.88$ifd4f/lo= 2006.141.07:49:22.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:49:22.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:49:22.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:49:22.88$ifd4f/patch= 2006.141.07:49:22.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:49:22.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:49:22.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:49:22.88$4f8m12a/"form=m,16.000,1:2 2006.141.07:49:22.88$4f8m12a/"tpicd 2006.141.07:49:22.88$4f8m12a/echo=off 2006.141.07:49:22.88$4f8m12a/xlog=off 2006.141.07:49:22.88:!2006.141.07:49:50 2006.141.07:49:36.14#trakl#Source acquired 2006.141.07:49:38.14#flagr#flagr/antenna,acquired 2006.141.07:49:50.00:preob 2006.141.07:49:51.14/onsource/TRACKING 2006.141.07:49:51.14:!2006.141.07:50:00 2006.141.07:50:00.00:data_valid=on 2006.141.07:50:00.00:midob 2006.141.07:50:00.14/onsource/TRACKING 2006.141.07:50:00.14/wx/21.67,1012.7,72 2006.141.07:50:00.33/cable/+6.5228E-03 2006.141.07:50:01.42/va/01,08,usb,yes,29,30 2006.141.07:50:01.42/va/02,07,usb,yes,29,30 2006.141.07:50:01.42/va/03,06,usb,yes,30,31 2006.141.07:50:01.42/va/04,07,usb,yes,29,32 2006.141.07:50:01.42/va/05,07,usb,yes,28,30 2006.141.07:50:01.42/va/06,06,usb,yes,27,27 2006.141.07:50:01.42/va/07,06,usb,yes,28,27 2006.141.07:50:01.42/va/08,06,usb,yes,30,29 2006.141.07:50:01.65/valo/01,532.99,yes,locked 2006.141.07:50:01.65/valo/02,572.99,yes,locked 2006.141.07:50:01.65/valo/03,672.99,yes,locked 2006.141.07:50:01.65/valo/04,832.99,yes,locked 2006.141.07:50:01.65/valo/05,652.99,yes,locked 2006.141.07:50:01.65/valo/06,772.99,yes,locked 2006.141.07:50:01.65/valo/07,832.99,yes,locked 2006.141.07:50:01.65/valo/08,852.99,yes,locked 2006.141.07:50:02.74/vb/01,04,usb,yes,29,28 2006.141.07:50:02.74/vb/02,04,usb,yes,31,32 2006.141.07:50:02.74/vb/03,04,usb,yes,27,31 2006.141.07:50:02.74/vb/04,04,usb,yes,28,28 2006.141.07:50:02.74/vb/05,04,usb,yes,27,30 2006.141.07:50:02.74/vb/06,04,usb,yes,28,30 2006.141.07:50:02.74/vb/07,04,usb,yes,29,29 2006.141.07:50:02.74/vb/08,04,usb,yes,27,30 2006.141.07:50:02.98/vblo/01,632.99,yes,locked 2006.141.07:50:02.98/vblo/02,640.99,yes,locked 2006.141.07:50:02.98/vblo/03,656.99,yes,locked 2006.141.07:50:02.98/vblo/04,712.99,yes,locked 2006.141.07:50:02.98/vblo/05,744.99,yes,locked 2006.141.07:50:02.98/vblo/06,752.99,yes,locked 2006.141.07:50:02.98/vblo/07,734.99,yes,locked 2006.141.07:50:02.98/vblo/08,744.99,yes,locked 2006.141.07:50:03.13/vabw/8 2006.141.07:50:03.28/vbbw/8 2006.141.07:50:03.37/xfe/off,on,15.0 2006.141.07:50:03.75/ifatt/23,28,28,28 2006.141.07:50:04.12/fmout-gps/S +1.03E-07 2006.141.07:50:04.16:!2006.141.07:51:00 2006.141.07:51:00.00:data_valid=off 2006.141.07:51:00.00:postob 2006.141.07:51:00.16/cable/+6.5226E-03 2006.141.07:51:00.16/wx/21.67,1012.7,71 2006.141.07:51:01.12/fmout-gps/S +1.03E-07 2006.141.07:51:01.12:scan_name=141-0751,k06141,60 2006.141.07:51:01.12:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.141.07:51:01.14#flagr#flagr/antenna,new-source 2006.141.07:51:02.14:checkk5 2006.141.07:51:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:51:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:51:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:51:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:51:04.03/chk_obsdata//k5ts1/T1410750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:51:04.40/chk_obsdata//k5ts2/T1410750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:51:04.78/chk_obsdata//k5ts3/T1410750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:51:05.15/chk_obsdata//k5ts4/T1410750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:51:05.84/k5log//k5ts1_log_newline 2006.141.07:51:06.53/k5log//k5ts2_log_newline 2006.141.07:51:07.23/k5log//k5ts3_log_newline 2006.141.07:51:07.92/k5log//k5ts4_log_newline 2006.141.07:51:07.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:51:07.94:4f8m12a=1 2006.141.07:51:07.95$4f8m12a/echo=on 2006.141.07:51:07.95$4f8m12a/pcalon 2006.141.07:51:07.95$pcalon/"no phase cal control is implemented here 2006.141.07:51:07.95$4f8m12a/"tpicd=stop 2006.141.07:51:07.95$4f8m12a/vc4f8 2006.141.07:51:07.95$vc4f8/valo=1,532.99 2006.141.07:51:07.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:51:07.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:51:07.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:07.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:07.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:07.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:51:08.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:08.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:08.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:51:08.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:51:08.05$vc4f8/va=1,8 2006.141.07:51:08.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:51:08.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:51:08.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:08.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:08.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:08.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:08.08#ibcon#[25=AT01-08\r\n] 2006.141.07:51:08.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:08.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:08.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:51:08.12#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:08.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:08.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:08.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:08.26#ibcon#[25=USB\r\n] 2006.141.07:51:08.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:08.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:08.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:51:08.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:51:08.29$vc4f8/valo=2,572.99 2006.141.07:51:08.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:51:08.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:51:08.29#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:08.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:08.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:08.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:08.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:51:08.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:08.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:08.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:51:08.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:51:08.37$vc4f8/va=2,7 2006.141.07:51:08.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:51:08.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:51:08.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:08.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:08.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:08.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:08.43#ibcon#[25=AT02-07\r\n] 2006.141.07:51:08.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:08.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:08.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:51:08.46#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:08.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:08.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:08.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:08.60#ibcon#[25=USB\r\n] 2006.141.07:51:08.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:08.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:08.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:51:08.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:51:08.63$vc4f8/valo=3,672.99 2006.141.07:51:08.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:51:08.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:51:08.63#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:08.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:08.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:08.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:08.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:51:08.71#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:08.71#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:08.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:51:08.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:51:08.71$vc4f8/va=3,6 2006.141.07:51:08.71#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:51:08.71#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:51:08.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:08.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:08.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:08.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:08.77#ibcon#[25=AT03-06\r\n] 2006.141.07:51:08.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:08.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:08.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:51:08.80#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:08.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:08.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:08.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:08.94#ibcon#[25=USB\r\n] 2006.141.07:51:08.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:08.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:08.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:51:08.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:51:08.97$vc4f8/valo=4,832.99 2006.141.07:51:08.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:51:08.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:51:08.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:08.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:08.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:08.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:08.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:51:09.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:09.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:09.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:51:09.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:51:09.03$vc4f8/va=4,7 2006.141.07:51:09.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:51:09.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:51:09.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:09.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:09.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:09.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:09.11#ibcon#[25=AT04-07\r\n] 2006.141.07:51:09.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:09.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:09.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:51:09.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:09.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:09.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:09.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:09.28#ibcon#[25=USB\r\n] 2006.141.07:51:09.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:09.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:09.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:51:09.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:51:09.31$vc4f8/valo=5,652.99 2006.141.07:51:09.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:51:09.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:51:09.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:09.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:09.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:09.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:09.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:51:09.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:09.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:09.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:51:09.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:51:09.37$vc4f8/va=5,7 2006.141.07:51:09.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:51:09.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:51:09.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:09.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:09.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:09.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:09.45#ibcon#[25=AT05-07\r\n] 2006.141.07:51:09.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:09.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:09.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:51:09.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:09.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:09.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:09.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:09.62#ibcon#[25=USB\r\n] 2006.141.07:51:09.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:09.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:09.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:51:09.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:51:09.65$vc4f8/valo=6,772.99 2006.141.07:51:09.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:51:09.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:51:09.65#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:09.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:09.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:09.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:09.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:51:09.71#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:09.71#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:09.71#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:51:09.71#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:51:09.71$vc4f8/va=6,6 2006.141.07:51:09.71#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.07:51:09.71#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.07:51:09.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:09.71#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:09.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:09.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:09.79#ibcon#[25=AT06-06\r\n] 2006.141.07:51:09.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:09.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:09.82#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.07:51:09.82#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:09.82#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:51:09.94#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:51:09.94#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:51:09.96#ibcon#[25=USB\r\n] 2006.141.07:51:09.99#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:51:09.99#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.07:51:09.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:51:09.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:51:09.99$vc4f8/valo=7,832.99 2006.141.07:51:09.99#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.07:51:09.99#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.07:51:09.99#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:09.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:51:09.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:51:09.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:51:10.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:51:10.05#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:51:10.05#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.07:51:10.05#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:51:10.05#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:51:10.05$vc4f8/va=7,6 2006.141.07:51:10.05#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.07:51:10.05#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.07:51:10.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:10.05#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:51:10.11#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:51:10.11#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:51:10.13#ibcon#[25=AT07-06\r\n] 2006.141.07:51:10.16#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:51:10.16#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.07:51:10.16#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.07:51:10.16#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:10.16#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:51:10.28#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:51:10.28#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:51:10.30#ibcon#[25=USB\r\n] 2006.141.07:51:10.33#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:51:10.33#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.07:51:10.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:51:10.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:51:10.33$vc4f8/valo=8,852.99 2006.141.07:51:10.33#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.07:51:10.33#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.07:51:10.33#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:10.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:51:10.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:51:10.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:51:10.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:51:10.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:51:10.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.07:51:10.39#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:51:10.39#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:51:10.39$vc4f8/va=8,6 2006.141.07:51:10.39#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.07:51:10.39#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.07:51:10.39#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:10.39#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:51:10.45#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:51:10.45#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:51:10.47#ibcon#[25=AT08-06\r\n] 2006.141.07:51:10.50#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:51:10.50#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.07:51:10.50#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.07:51:10.50#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:10.50#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:51:10.62#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:51:10.62#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:51:10.64#ibcon#[25=USB\r\n] 2006.141.07:51:10.67#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:51:10.67#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.07:51:10.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:51:10.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:51:10.67$vc4f8/vblo=1,632.99 2006.141.07:51:10.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.07:51:10.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.07:51:10.67#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:10.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:51:10.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:51:10.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:51:10.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:51:10.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:51:10.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.07:51:10.73#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:51:10.73#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:51:10.73$vc4f8/vb=1,4 2006.141.07:51:10.73#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.07:51:10.73#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.07:51:10.73#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:10.73#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:51:10.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:51:10.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:51:10.75#ibcon#[27=AT01-04\r\n] 2006.141.07:51:10.78#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:51:10.78#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.07:51:10.78#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.07:51:10.78#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:10.78#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:51:10.90#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:51:10.90#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:51:10.92#ibcon#[27=USB\r\n] 2006.141.07:51:10.95#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:51:10.95#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.07:51:10.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:51:10.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:51:10.95$vc4f8/vblo=2,640.99 2006.141.07:51:10.95#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.07:51:10.95#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.07:51:10.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:10.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:10.95#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:10.95#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:10.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:51:11.01#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:11.01#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.07:51:11.01#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:51:11.01#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:51:11.01$vc4f8/vb=2,4 2006.141.07:51:11.01#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.07:51:11.01#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.07:51:11.01#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:11.01#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:11.07#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:11.07#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:11.09#ibcon#[27=AT02-04\r\n] 2006.141.07:51:11.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:11.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.07:51:11.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.07:51:11.12#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:11.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:11.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:11.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:11.26#ibcon#[27=USB\r\n] 2006.141.07:51:11.29#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:11.29#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.07:51:11.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:51:11.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:51:11.29$vc4f8/vblo=3,656.99 2006.141.07:51:11.29#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.07:51:11.29#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.07:51:11.29#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:11.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:11.29#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:11.29#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:11.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:51:11.35#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:11.35#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.07:51:11.35#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:51:11.35#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:51:11.35$vc4f8/vb=3,4 2006.141.07:51:11.35#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.07:51:11.35#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.07:51:11.35#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:11.35#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:11.41#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:11.41#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:11.43#ibcon#[27=AT03-04\r\n] 2006.141.07:51:11.46#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:11.46#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.07:51:11.46#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.07:51:11.46#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:11.46#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:11.58#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:11.58#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:11.60#ibcon#[27=USB\r\n] 2006.141.07:51:11.63#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:11.63#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.07:51:11.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:51:11.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:51:11.63$vc4f8/vblo=4,712.99 2006.141.07:51:11.63#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.07:51:11.63#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.07:51:11.63#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:11.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:11.63#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:11.63#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:11.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:51:11.69#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:11.69#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.07:51:11.69#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:51:11.69#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:51:11.69$vc4f8/vb=4,4 2006.141.07:51:11.69#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.07:51:11.69#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.07:51:11.69#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:11.69#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:11.75#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:11.75#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:11.77#ibcon#[27=AT04-04\r\n] 2006.141.07:51:11.80#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:11.80#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.07:51:11.80#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.07:51:11.80#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:11.80#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:11.92#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:11.92#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:11.94#ibcon#[27=USB\r\n] 2006.141.07:51:11.97#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:11.97#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.07:51:11.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:51:11.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:51:11.97$vc4f8/vblo=5,744.99 2006.141.07:51:11.97#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.07:51:11.97#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.07:51:11.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:11.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:11.97#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:11.97#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:11.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:51:12.03#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:12.03#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.07:51:12.03#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:51:12.03#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:51:12.03$vc4f8/vb=5,4 2006.141.07:51:12.03#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.07:51:12.03#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.07:51:12.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:12.03#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:12.09#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:12.09#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:12.11#ibcon#[27=AT05-04\r\n] 2006.141.07:51:12.14#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:12.14#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.07:51:12.14#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.07:51:12.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:12.14#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:12.26#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:12.26#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:12.28#ibcon#[27=USB\r\n] 2006.141.07:51:12.31#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:12.31#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.07:51:12.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:51:12.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:51:12.31$vc4f8/vblo=6,752.99 2006.141.07:51:12.31#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:51:12.31#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:51:12.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:51:12.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:12.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:12.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:12.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:51:12.37#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:12.37#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:51:12.37#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:51:12.37#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:51:12.37$vc4f8/vb=6,4 2006.141.07:51:12.37#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.07:51:12.37#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.07:51:12.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:51:12.37#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:12.43#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:12.43#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:12.45#ibcon#[27=AT06-04\r\n] 2006.141.07:51:12.48#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:12.48#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.07:51:12.48#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.07:51:12.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:51:12.48#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:12.60#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:12.60#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:12.62#ibcon#[27=USB\r\n] 2006.141.07:51:12.65#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:12.65#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.07:51:12.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:51:12.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:51:12.65$vc4f8/vabw=wide 2006.141.07:51:12.65#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.07:51:12.65#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.07:51:12.65#ibcon#ireg 8 cls_cnt 0 2006.141.07:51:12.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:12.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:12.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:12.69#ibcon#[25=BW32\r\n] 2006.141.07:51:12.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:12.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.07:51:12.72#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:51:12.72#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:51:12.72$vc4f8/vbbw=wide 2006.141.07:51:12.72#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.07:51:12.72#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.07:51:12.72#ibcon#ireg 8 cls_cnt 0 2006.141.07:51:12.72#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:51:12.77#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:51:12.77#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:51:12.79#ibcon#[27=BW32\r\n] 2006.141.07:51:12.82#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:51:12.82#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:51:12.82#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:51:12.82#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:51:12.82$4f8m12a/ifd4f 2006.141.07:51:12.82$ifd4f/lo= 2006.141.07:51:12.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:51:12.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:51:12.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:51:12.82$ifd4f/patch= 2006.141.07:51:12.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:51:12.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:51:12.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:51:12.82$4f8m12a/"form=m,16.000,1:2 2006.141.07:51:12.82$4f8m12a/"tpicd 2006.141.07:51:12.82$4f8m12a/echo=off 2006.141.07:51:12.82$4f8m12a/xlog=off 2006.141.07:51:12.82:!2006.141.07:51:40 2006.141.07:51:25.14#trakl#Source acquired 2006.141.07:51:25.14#flagr#flagr/antenna,acquired 2006.141.07:51:40.00:preob 2006.141.07:51:41.14/onsource/TRACKING 2006.141.07:51:41.14:!2006.141.07:51:50 2006.141.07:51:50.00:data_valid=on 2006.141.07:51:50.00:midob 2006.141.07:51:50.14/onsource/TRACKING 2006.141.07:51:50.14/wx/21.67,1012.7,70 2006.141.07:51:50.33/cable/+6.5214E-03 2006.141.07:51:51.42/va/01,08,usb,yes,28,30 2006.141.07:51:51.42/va/02,07,usb,yes,29,30 2006.141.07:51:51.42/va/03,06,usb,yes,30,30 2006.141.07:51:51.42/va/04,07,usb,yes,29,31 2006.141.07:51:51.42/va/05,07,usb,yes,28,30 2006.141.07:51:51.42/va/06,06,usb,yes,27,27 2006.141.07:51:51.42/va/07,06,usb,yes,27,27 2006.141.07:51:51.42/va/08,06,usb,yes,29,29 2006.141.07:51:51.65/valo/01,532.99,yes,locked 2006.141.07:51:51.65/valo/02,572.99,yes,locked 2006.141.07:51:51.65/valo/03,672.99,yes,locked 2006.141.07:51:51.65/valo/04,832.99,yes,locked 2006.141.07:51:51.65/valo/05,652.99,yes,locked 2006.141.07:51:51.65/valo/06,772.99,yes,locked 2006.141.07:51:51.65/valo/07,832.99,yes,locked 2006.141.07:51:51.65/valo/08,852.99,yes,locked 2006.141.07:51:52.74/vb/01,04,usb,yes,29,28 2006.141.07:51:52.74/vb/02,04,usb,yes,30,32 2006.141.07:51:52.74/vb/03,04,usb,yes,27,30 2006.141.07:51:52.74/vb/04,04,usb,yes,28,28 2006.141.07:51:52.74/vb/05,04,usb,yes,26,30 2006.141.07:51:52.74/vb/06,04,usb,yes,28,30 2006.141.07:51:52.74/vb/07,04,usb,yes,29,29 2006.141.07:51:52.74/vb/08,04,usb,yes,27,30 2006.141.07:51:52.97/vblo/01,632.99,yes,locked 2006.141.07:51:52.97/vblo/02,640.99,yes,locked 2006.141.07:51:52.97/vblo/03,656.99,yes,locked 2006.141.07:51:52.97/vblo/04,712.99,yes,locked 2006.141.07:51:52.97/vblo/05,744.99,yes,locked 2006.141.07:51:52.97/vblo/06,752.99,yes,locked 2006.141.07:51:52.97/vblo/07,734.99,yes,locked 2006.141.07:51:52.97/vblo/08,744.99,yes,locked 2006.141.07:51:53.12/vabw/8 2006.141.07:51:53.27/vbbw/8 2006.141.07:51:53.36/xfe/off,on,15.5 2006.141.07:51:53.73/ifatt/23,28,28,28 2006.141.07:51:54.12/fmout-gps/S +1.04E-07 2006.141.07:51:54.16:!2006.141.07:52:50 2006.141.07:52:50.00:data_valid=off 2006.141.07:52:50.00:postob 2006.141.07:52:50.12/cable/+6.5220E-03 2006.141.07:52:50.12/wx/21.65,1012.7,71 2006.141.07:52:51.11/fmout-gps/S +1.04E-07 2006.141.07:52:51.11:scan_name=141-0753,k06141,60 2006.141.07:52:51.11:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.141.07:52:51.14#flagr#flagr/antenna,new-source 2006.141.07:52:52.14:checkk5 2006.141.07:52:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:52:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:52:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:52:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:52:54.03/chk_obsdata//k5ts1/T1410751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:52:54.40/chk_obsdata//k5ts2/T1410751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:52:54.77/chk_obsdata//k5ts3/T1410751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:52:55.14/chk_obsdata//k5ts4/T1410751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:52:55.84/k5log//k5ts1_log_newline 2006.141.07:52:56.53/k5log//k5ts2_log_newline 2006.141.07:52:57.23/k5log//k5ts3_log_newline 2006.141.07:52:57.92/k5log//k5ts4_log_newline 2006.141.07:52:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:52:57.94:4f8m12a=1 2006.141.07:52:57.94$4f8m12a/echo=on 2006.141.07:52:57.94$4f8m12a/pcalon 2006.141.07:52:57.94$pcalon/"no phase cal control is implemented here 2006.141.07:52:57.95$4f8m12a/"tpicd=stop 2006.141.07:52:57.95$4f8m12a/vc4f8 2006.141.07:52:57.95$vc4f8/valo=1,532.99 2006.141.07:52:57.95#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.07:52:57.95#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.07:52:57.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:57.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:52:57.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:52:57.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:52:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:52:58.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:52:58.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:52:58.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:52:58.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:52:58.06$vc4f8/va=1,8 2006.141.07:52:58.06#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.07:52:58.06#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.07:52:58.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:58.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:52:58.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:52:58.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:52:58.09#ibcon#[25=AT01-08\r\n] 2006.141.07:52:58.13#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:52:58.13#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:52:58.13#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.07:52:58.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:58.13#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:52:58.25#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:52:58.25#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:52:58.27#ibcon#[25=USB\r\n] 2006.141.07:52:58.32#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:52:58.32#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:52:58.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:52:58.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:52:58.32$vc4f8/valo=2,572.99 2006.141.07:52:58.32#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:52:58.32#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:52:58.32#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:58.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:52:58.32#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:52:58.32#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:52:58.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:52:58.38#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:52:58.38#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:52:58.38#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:52:58.38#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:52:58.38$vc4f8/va=2,7 2006.141.07:52:58.38#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.07:52:58.38#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.07:52:58.38#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:58.38#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:52:58.44#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:52:58.44#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:52:58.46#ibcon#[25=AT02-07\r\n] 2006.141.07:52:58.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:52:58.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:52:58.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.07:52:58.51#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:58.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:52:58.56#abcon#<5=/05 4.6 8.3 21.65 711012.6\r\n> 2006.141.07:52:58.60#abcon#{5=INTERFACE CLEAR} 2006.141.07:52:58.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:52:58.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:52:58.65#ibcon#[25=USB\r\n] 2006.141.07:52:58.66#abcon#[5=S1D000X0/0*\r\n] 2006.141.07:52:58.69#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:52:58.69#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:52:58.69#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:52:58.69#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:52:58.70$vc4f8/valo=3,672.99 2006.141.07:52:58.70#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:52:58.70#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:52:58.70#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:58.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:52:58.70#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:52:58.70#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:52:58.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:52:58.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:52:58.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:52:58.76#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:52:58.76#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:52:58.76$vc4f8/va=3,6 2006.141.07:52:58.76#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:52:58.76#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:52:58.76#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:58.76#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:52:58.81#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:52:58.81#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:52:58.83#ibcon#[25=AT03-06\r\n] 2006.141.07:52:58.86#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:52:58.86#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:52:58.86#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:52:58.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:58.86#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:52:58.98#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:52:58.98#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:52:59.00#ibcon#[25=USB\r\n] 2006.141.07:52:59.03#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:52:59.03#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:52:59.03#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:52:59.03#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:52:59.03$vc4f8/valo=4,832.99 2006.141.07:52:59.03#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:52:59.03#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:52:59.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:59.03#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:52:59.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:52:59.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:52:59.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:52:59.09#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:52:59.09#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:52:59.09#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:52:59.09#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:52:59.09$vc4f8/va=4,7 2006.141.07:52:59.09#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:52:59.09#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:52:59.09#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:59.09#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:52:59.15#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:52:59.15#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:52:59.17#ibcon#[25=AT04-07\r\n] 2006.141.07:52:59.20#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:52:59.20#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:52:59.20#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:52:59.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:59.20#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:52:59.32#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:52:59.32#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:52:59.34#ibcon#[25=USB\r\n] 2006.141.07:52:59.37#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:52:59.37#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:52:59.37#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:52:59.37#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:52:59.37$vc4f8/valo=5,652.99 2006.141.07:52:59.37#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.07:52:59.37#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.07:52:59.37#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:59.37#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:52:59.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:52:59.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:52:59.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:52:59.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:52:59.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:52:59.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:52:59.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:52:59.43$vc4f8/va=5,7 2006.141.07:52:59.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.07:52:59.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.07:52:59.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:59.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:52:59.49#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:52:59.49#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:52:59.51#ibcon#[25=AT05-07\r\n] 2006.141.07:52:59.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:52:59.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:52:59.54#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.07:52:59.54#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:59.54#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:52:59.66#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:52:59.66#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:52:59.68#ibcon#[25=USB\r\n] 2006.141.07:52:59.71#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:52:59.71#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:52:59.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:52:59.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:52:59.71$vc4f8/valo=6,772.99 2006.141.07:52:59.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.07:52:59.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.07:52:59.71#ibcon#ireg 17 cls_cnt 0 2006.141.07:52:59.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:52:59.71#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:52:59.71#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:52:59.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:52:59.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:52:59.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:52:59.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:52:59.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:52:59.77$vc4f8/va=6,6 2006.141.07:52:59.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.07:52:59.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.07:52:59.77#ibcon#ireg 11 cls_cnt 2 2006.141.07:52:59.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:52:59.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:52:59.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:52:59.85#ibcon#[25=AT06-06\r\n] 2006.141.07:52:59.88#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:52:59.88#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.07:52:59.88#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.07:52:59.88#ibcon#ireg 7 cls_cnt 0 2006.141.07:52:59.88#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:53:00.00#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:53:00.00#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:53:00.02#ibcon#[25=USB\r\n] 2006.141.07:53:00.05#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:53:00.05#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.07:53:00.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:53:00.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:53:00.05$vc4f8/valo=7,832.99 2006.141.07:53:00.05#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.07:53:00.05#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.07:53:00.05#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:00.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:53:00.05#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:53:00.05#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:53:00.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:53:00.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:53:00.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:53:00.13#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:53:00.13#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:53:00.13$vc4f8/va=7,6 2006.141.07:53:00.13#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.07:53:00.13#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.07:53:00.13#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:00.13#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:53:00.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:53:00.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:53:00.19#ibcon#[25=AT07-06\r\n] 2006.141.07:53:00.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:53:00.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.07:53:00.22#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.07:53:00.22#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:00.22#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:53:00.34#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:53:00.34#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:53:00.36#ibcon#[25=USB\r\n] 2006.141.07:53:00.39#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:53:00.39#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.07:53:00.39#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:53:00.39#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:53:00.39$vc4f8/valo=8,852.99 2006.141.07:53:00.39#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.07:53:00.39#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.07:53:00.39#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:00.39#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:53:00.39#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:53:00.39#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:53:00.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:53:00.45#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:53:00.45#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.07:53:00.45#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:53:00.45#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:53:00.45$vc4f8/va=8,6 2006.141.07:53:00.45#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.07:53:00.45#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.07:53:00.45#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:00.45#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:53:00.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:53:00.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:53:00.53#ibcon#[25=AT08-06\r\n] 2006.141.07:53:00.56#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:53:00.56#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.07:53:00.56#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.07:53:00.56#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:00.56#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:53:00.68#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:53:00.68#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:53:00.70#ibcon#[25=USB\r\n] 2006.141.07:53:00.75#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:53:00.75#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.07:53:00.75#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:53:00.75#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:53:00.75$vc4f8/vblo=1,632.99 2006.141.07:53:00.75#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.07:53:00.75#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.07:53:00.75#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:00.75#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:53:00.75#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:53:00.75#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:53:00.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:53:00.81#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:53:00.81#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.07:53:00.81#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:53:00.81#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:53:00.81$vc4f8/vb=1,4 2006.141.07:53:00.81#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.07:53:00.81#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.07:53:00.81#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:00.81#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:53:00.81#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:53:00.81#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:53:00.83#ibcon#[27=AT01-04\r\n] 2006.141.07:53:00.86#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:53:00.86#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.07:53:00.86#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.07:53:00.86#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:00.86#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:53:00.98#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:53:00.98#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:53:01.00#ibcon#[27=USB\r\n] 2006.141.07:53:01.03#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:53:01.03#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.07:53:01.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:53:01.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:53:01.03$vc4f8/vblo=2,640.99 2006.141.07:53:01.03#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.07:53:01.03#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.07:53:01.03#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:01.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:53:01.03#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:53:01.03#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:53:01.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:53:01.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:53:01.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.07:53:01.09#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:53:01.09#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:53:01.09$vc4f8/vb=2,4 2006.141.07:53:01.09#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.07:53:01.09#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.07:53:01.09#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:01.09#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:53:01.15#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:53:01.15#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:53:01.17#ibcon#[27=AT02-04\r\n] 2006.141.07:53:01.20#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:53:01.20#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.07:53:01.20#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.07:53:01.20#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:01.20#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:53:01.32#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:53:01.32#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:53:01.34#ibcon#[27=USB\r\n] 2006.141.07:53:01.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:53:01.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.07:53:01.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:53:01.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:53:01.39$vc4f8/vblo=3,656.99 2006.141.07:53:01.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.07:53:01.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.07:53:01.39#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:01.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:53:01.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:53:01.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:53:01.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:53:01.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:53:01.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.07:53:01.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:53:01.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:53:01.45$vc4f8/vb=3,4 2006.141.07:53:01.45#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.07:53:01.45#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.07:53:01.45#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:01.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:53:01.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:53:01.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:53:01.53#ibcon#[27=AT03-04\r\n] 2006.141.07:53:01.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:53:01.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.07:53:01.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.07:53:01.56#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:01.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:53:01.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:53:01.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:53:01.70#ibcon#[27=USB\r\n] 2006.141.07:53:01.75#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:53:01.75#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.07:53:01.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:53:01.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:53:01.75$vc4f8/vblo=4,712.99 2006.141.07:53:01.75#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.07:53:01.75#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.07:53:01.75#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:01.75#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:53:01.75#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:53:01.75#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:53:01.77#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:53:01.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:53:01.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.07:53:01.81#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:53:01.81#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:53:01.81$vc4f8/vb=4,4 2006.141.07:53:01.81#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.07:53:01.81#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.07:53:01.81#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:01.81#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:53:01.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:53:01.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:53:01.89#ibcon#[27=AT04-04\r\n] 2006.141.07:53:01.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:53:01.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.07:53:01.92#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.07:53:01.92#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:01.92#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:53:02.04#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:53:02.04#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:53:02.06#ibcon#[27=USB\r\n] 2006.141.07:53:02.09#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:53:02.09#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.07:53:02.09#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:53:02.09#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:53:02.09$vc4f8/vblo=5,744.99 2006.141.07:53:02.09#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.07:53:02.09#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.07:53:02.09#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:02.09#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:53:02.09#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:53:02.09#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:53:02.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:53:02.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:53:02.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.07:53:02.15#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:53:02.15#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:53:02.15$vc4f8/vb=5,4 2006.141.07:53:02.15#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.07:53:02.15#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.07:53:02.15#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:02.15#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:53:02.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:53:02.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:53:02.23#ibcon#[27=AT05-04\r\n] 2006.141.07:53:02.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:53:02.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.07:53:02.26#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.07:53:02.26#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:02.26#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:53:02.38#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:53:02.38#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:53:02.40#ibcon#[27=USB\r\n] 2006.141.07:53:02.43#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:53:02.43#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.07:53:02.43#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:53:02.43#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:53:02.43$vc4f8/vblo=6,752.99 2006.141.07:53:02.43#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.07:53:02.43#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.07:53:02.43#ibcon#ireg 17 cls_cnt 0 2006.141.07:53:02.43#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:53:02.43#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:53:02.43#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:53:02.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:53:02.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:53:02.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.07:53:02.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:53:02.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:53:02.49$vc4f8/vb=6,4 2006.141.07:53:02.49#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.07:53:02.49#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.07:53:02.49#ibcon#ireg 11 cls_cnt 2 2006.141.07:53:02.49#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:53:02.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:53:02.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:53:02.57#ibcon#[27=AT06-04\r\n] 2006.141.07:53:02.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:53:02.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.07:53:02.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.07:53:02.60#ibcon#ireg 7 cls_cnt 0 2006.141.07:53:02.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:53:02.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:53:02.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:53:02.74#ibcon#[27=USB\r\n] 2006.141.07:53:02.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:53:02.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.07:53:02.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:53:02.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:53:02.77$vc4f8/vabw=wide 2006.141.07:53:02.77#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.07:53:02.77#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.07:53:02.77#ibcon#ireg 8 cls_cnt 0 2006.141.07:53:02.77#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:53:02.77#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:53:02.77#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:53:02.79#ibcon#[25=BW32\r\n] 2006.141.07:53:02.82#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:53:02.82#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.07:53:02.82#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:53:02.82#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:53:02.82$vc4f8/vbbw=wide 2006.141.07:53:02.82#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:53:02.82#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:53:02.82#ibcon#ireg 8 cls_cnt 0 2006.141.07:53:02.82#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:53:02.89#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:53:02.89#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:53:02.91#ibcon#[27=BW32\r\n] 2006.141.07:53:02.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:53:02.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:53:02.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:53:02.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:53:02.94$4f8m12a/ifd4f 2006.141.07:53:02.94$ifd4f/lo= 2006.141.07:53:02.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:53:02.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:53:02.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:53:02.94$ifd4f/patch= 2006.141.07:53:02.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:53:02.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:53:02.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:53:02.94$4f8m12a/"form=m,16.000,1:2 2006.141.07:53:02.94$4f8m12a/"tpicd 2006.141.07:53:02.94$4f8m12a/echo=off 2006.141.07:53:02.94$4f8m12a/xlog=off 2006.141.07:53:02.94:!2006.141.07:53:30 2006.141.07:53:13.14#trakl#Source acquired 2006.141.07:53:15.14#flagr#flagr/antenna,acquired 2006.141.07:53:30.00:preob 2006.141.07:53:31.14/onsource/TRACKING 2006.141.07:53:31.14:!2006.141.07:53:40 2006.141.07:53:40.00:data_valid=on 2006.141.07:53:40.00:midob 2006.141.07:53:40.14/onsource/TRACKING 2006.141.07:53:40.14/wx/21.64,1012.7,71 2006.141.07:53:40.32/cable/+6.5218E-03 2006.141.07:53:41.41/va/01,08,usb,yes,28,30 2006.141.07:53:41.41/va/02,07,usb,yes,29,30 2006.141.07:53:41.41/va/03,06,usb,yes,30,30 2006.141.07:53:41.41/va/04,07,usb,yes,29,31 2006.141.07:53:41.41/va/05,07,usb,yes,28,30 2006.141.07:53:41.41/va/06,06,usb,yes,27,27 2006.141.07:53:41.41/va/07,06,usb,yes,27,27 2006.141.07:53:41.41/va/08,06,usb,yes,29,29 2006.141.07:53:41.64/valo/01,532.99,yes,locked 2006.141.07:53:41.64/valo/02,572.99,yes,locked 2006.141.07:53:41.64/valo/03,672.99,yes,locked 2006.141.07:53:41.64/valo/04,832.99,yes,locked 2006.141.07:53:41.64/valo/05,652.99,yes,locked 2006.141.07:53:41.64/valo/06,772.99,yes,locked 2006.141.07:53:41.64/valo/07,832.99,yes,locked 2006.141.07:53:41.64/valo/08,852.99,yes,locked 2006.141.07:53:42.73/vb/01,04,usb,yes,29,28 2006.141.07:53:42.73/vb/02,04,usb,yes,30,32 2006.141.07:53:42.73/vb/03,04,usb,yes,27,30 2006.141.07:53:42.73/vb/04,04,usb,yes,28,28 2006.141.07:53:42.73/vb/05,04,usb,yes,26,30 2006.141.07:53:42.73/vb/06,04,usb,yes,27,30 2006.141.07:53:42.73/vb/07,04,usb,yes,29,29 2006.141.07:53:42.73/vb/08,04,usb,yes,27,30 2006.141.07:53:42.97/vblo/01,632.99,yes,locked 2006.141.07:53:42.97/vblo/02,640.99,yes,locked 2006.141.07:53:42.97/vblo/03,656.99,yes,locked 2006.141.07:53:42.97/vblo/04,712.99,yes,locked 2006.141.07:53:42.97/vblo/05,744.99,yes,locked 2006.141.07:53:42.97/vblo/06,752.99,yes,locked 2006.141.07:53:42.97/vblo/07,734.99,yes,locked 2006.141.07:53:42.97/vblo/08,744.99,yes,locked 2006.141.07:53:43.12/vabw/8 2006.141.07:53:43.27/vbbw/8 2006.141.07:53:43.36/xfe/off,on,14.7 2006.141.07:53:43.74/ifatt/23,28,28,28 2006.141.07:53:44.12/fmout-gps/S +1.05E-07 2006.141.07:53:44.16:!2006.141.07:54:40 2006.141.07:54:40.00:data_valid=off 2006.141.07:54:40.00:postob 2006.141.07:54:40.17/cable/+6.5241E-03 2006.141.07:54:40.17/wx/21.62,1012.7,71 2006.141.07:54:41.12/fmout-gps/S +1.04E-07 2006.141.07:54:41.12:scan_name=141-0756,k06141,60 2006.141.07:54:41.12:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.141.07:54:43.13#flagr#flagr/antenna,new-source 2006.141.07:54:43.13:checkk5 2006.141.07:54:43.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:54:43.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:54:44.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:54:44.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:54:45.02/chk_obsdata//k5ts1/T1410753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:54:45.40/chk_obsdata//k5ts2/T1410753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:54:45.77/chk_obsdata//k5ts3/T1410753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:54:46.14/chk_obsdata//k5ts4/T1410753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.07:54:46.84/k5log//k5ts1_log_newline 2006.141.07:54:47.53/k5log//k5ts2_log_newline 2006.141.07:54:48.23/k5log//k5ts3_log_newline 2006.141.07:54:48.92/k5log//k5ts4_log_newline 2006.141.07:54:48.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:54:48.95:4f8m12a=2 2006.141.07:54:48.95$4f8m12a/echo=on 2006.141.07:54:48.95$4f8m12a/pcalon 2006.141.07:54:48.95$pcalon/"no phase cal control is implemented here 2006.141.07:54:48.95$4f8m12a/"tpicd=stop 2006.141.07:54:48.95$4f8m12a/vc4f8 2006.141.07:54:48.95$vc4f8/valo=1,532.99 2006.141.07:54:48.95#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:54:48.95#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:54:48.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:48.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:48.95#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:48.95#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:49.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:54:49.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:49.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:49.05#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:54:49.05#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:54:49.05$vc4f8/va=1,8 2006.141.07:54:49.05#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:54:49.05#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:54:49.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:49.05#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:49.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:49.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:49.09#ibcon#[25=AT01-08\r\n] 2006.141.07:54:49.12#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:49.12#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:49.12#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:54:49.12#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:49.12#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:49.24#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:49.24#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:49.26#ibcon#[25=USB\r\n] 2006.141.07:54:49.29#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:49.29#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:49.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:54:49.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:54:49.29$vc4f8/valo=2,572.99 2006.141.07:54:49.29#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:54:49.29#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:54:49.29#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:49.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:49.29#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:49.29#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:49.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:54:49.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:49.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:49.37#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:54:49.37#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:54:49.37$vc4f8/va=2,7 2006.141.07:54:49.37#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:54:49.37#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:54:49.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:49.37#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:49.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:49.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:49.43#ibcon#[25=AT02-07\r\n] 2006.141.07:54:49.46#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:49.46#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:49.46#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:54:49.46#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:49.46#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:49.58#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:49.58#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:49.60#ibcon#[25=USB\r\n] 2006.141.07:54:49.63#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:49.63#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:49.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:54:49.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:54:49.63$vc4f8/valo=3,672.99 2006.141.07:54:49.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:54:49.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:54:49.63#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:49.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:49.63#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:49.63#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:49.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:54:49.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:49.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:49.71#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:54:49.71#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:54:49.71$vc4f8/va=3,6 2006.141.07:54:49.71#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:54:49.71#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:54:49.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:49.71#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:49.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:49.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:49.77#ibcon#[25=AT03-06\r\n] 2006.141.07:54:49.80#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:49.80#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:49.80#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:54:49.80#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:49.80#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:49.92#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:49.92#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:49.94#ibcon#[25=USB\r\n] 2006.141.07:54:49.97#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:49.97#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:49.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:54:49.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:54:49.97$vc4f8/valo=4,832.99 2006.141.07:54:49.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:54:49.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:54:49.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:49.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:49.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:49.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:49.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:54:50.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:50.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:50.03#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:54:50.03#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:54:50.03$vc4f8/va=4,7 2006.141.07:54:50.03#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:54:50.03#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:54:50.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:50.03#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:50.09#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:50.09#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:50.11#ibcon#[25=AT04-07\r\n] 2006.141.07:54:50.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:50.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:50.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:54:50.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:50.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:50.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:50.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:50.28#ibcon#[25=USB\r\n] 2006.141.07:54:50.31#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:50.31#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:50.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:54:50.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:54:50.31$vc4f8/valo=5,652.99 2006.141.07:54:50.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:54:50.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:54:50.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:50.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:50.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:50.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:50.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:54:50.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:50.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:50.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:54:50.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:54:50.37$vc4f8/va=5,7 2006.141.07:54:50.37#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.07:54:50.37#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.07:54:50.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:50.37#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:50.43#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:50.43#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:50.45#ibcon#[25=AT05-07\r\n] 2006.141.07:54:50.47#abcon#<5=/04 4.6 8.3 21.61 711012.7\r\n> 2006.141.07:54:50.48#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:50.48#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:50.48#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.07:54:50.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:50.48#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:50.49#abcon#{5=INTERFACE CLEAR} 2006.141.07:54:50.56#abcon#[5=S1D000X0/0*\r\n] 2006.141.07:54:50.60#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:50.60#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:50.62#ibcon#[25=USB\r\n] 2006.141.07:54:50.65#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:50.65#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:50.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:54:50.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:54:50.65$vc4f8/valo=6,772.99 2006.141.07:54:50.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:54:50.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:54:50.65#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:50.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:50.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:50.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:50.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:54:50.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:50.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:50.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:54:50.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:54:50.71$vc4f8/va=6,6 2006.141.07:54:50.71#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.07:54:50.71#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.07:54:50.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:50.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:50.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:50.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:50.79#ibcon#[25=AT06-06\r\n] 2006.141.07:54:50.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:50.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:50.82#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.07:54:50.82#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:50.82#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:54:50.94#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:54:50.94#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:54:50.96#ibcon#[25=USB\r\n] 2006.141.07:54:50.99#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:54:50.99#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.07:54:50.99#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:54:50.99#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:54:50.99$vc4f8/valo=7,832.99 2006.141.07:54:50.99#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.07:54:50.99#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.07:54:50.99#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:50.99#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:54:50.99#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:54:50.99#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:54:51.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:54:51.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:54:51.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.07:54:51.05#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.07:54:51.05#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.07:54:51.05$vc4f8/va=7,6 2006.141.07:54:51.05#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.07:54:51.05#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.07:54:51.05#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:51.05#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:54:51.11#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:54:51.11#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:54:51.13#ibcon#[25=AT07-06\r\n] 2006.141.07:54:51.16#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:54:51.16#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.07:54:51.16#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.07:54:51.16#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:51.16#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:54:51.28#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:54:51.28#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:54:51.30#ibcon#[25=USB\r\n] 2006.141.07:54:51.33#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:54:51.33#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.07:54:51.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.07:54:51.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.07:54:51.33$vc4f8/valo=8,852.99 2006.141.07:54:51.33#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.07:54:51.33#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.07:54:51.33#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:51.33#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:54:51.33#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:54:51.33#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:54:51.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:54:51.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:54:51.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.07:54:51.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.07:54:51.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.07:54:51.39$vc4f8/va=8,6 2006.141.07:54:51.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.07:54:51.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.07:54:51.39#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:51.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:54:51.45#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:54:51.45#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:54:51.47#ibcon#[25=AT08-06\r\n] 2006.141.07:54:51.50#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:54:51.50#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.07:54:51.50#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.07:54:51.50#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:51.50#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:54:51.62#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:54:51.62#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:54:51.64#ibcon#[25=USB\r\n] 2006.141.07:54:51.67#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:54:51.67#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.07:54:51.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.07:54:51.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.07:54:51.67$vc4f8/vblo=1,632.99 2006.141.07:54:51.67#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.07:54:51.67#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.07:54:51.67#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:51.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:51.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:51.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:51.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:54:51.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:51.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.07:54:51.73#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.07:54:51.73#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.07:54:51.73$vc4f8/vb=1,4 2006.141.07:54:51.73#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.07:54:51.73#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.07:54:51.73#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:51.73#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:51.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:51.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:51.75#ibcon#[27=AT01-04\r\n] 2006.141.07:54:51.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:51.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.07:54:51.78#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.07:54:51.78#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:51.78#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:51.90#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:51.90#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:51.92#ibcon#[27=USB\r\n] 2006.141.07:54:51.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:51.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.07:54:51.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.07:54:51.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.07:54:51.95$vc4f8/vblo=2,640.99 2006.141.07:54:51.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.07:54:51.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.07:54:51.95#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:51.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:51.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:51.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:51.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:54:52.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:52.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.07:54:52.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.07:54:52.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.07:54:52.01$vc4f8/vb=2,4 2006.141.07:54:52.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.07:54:52.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.07:54:52.01#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:52.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:52.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:52.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:52.09#ibcon#[27=AT02-04\r\n] 2006.141.07:54:52.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:52.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.07:54:52.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.07:54:52.12#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:52.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:52.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:52.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:52.26#ibcon#[27=USB\r\n] 2006.141.07:54:52.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:52.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.07:54:52.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.07:54:52.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.07:54:52.29$vc4f8/vblo=3,656.99 2006.141.07:54:52.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.07:54:52.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.07:54:52.29#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:52.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:52.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:52.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:52.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:54:52.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:52.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.07:54:52.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.07:54:52.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.07:54:52.35$vc4f8/vb=3,4 2006.141.07:54:52.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.07:54:52.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.07:54:52.35#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:52.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:52.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:52.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:52.43#ibcon#[27=AT03-04\r\n] 2006.141.07:54:52.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:52.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.07:54:52.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.07:54:52.46#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:52.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:52.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:52.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:52.60#ibcon#[27=USB\r\n] 2006.141.07:54:52.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:52.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.07:54:52.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.07:54:52.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.07:54:52.63$vc4f8/vblo=4,712.99 2006.141.07:54:52.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.07:54:52.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.07:54:52.63#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:52.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:52.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:52.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:52.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:54:52.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:52.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.07:54:52.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.07:54:52.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.07:54:52.69$vc4f8/vb=4,4 2006.141.07:54:52.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.07:54:52.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.07:54:52.69#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:52.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:52.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:52.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:52.77#ibcon#[27=AT04-04\r\n] 2006.141.07:54:52.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:52.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.07:54:52.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.07:54:52.80#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:52.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:52.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:52.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:52.94#ibcon#[27=USB\r\n] 2006.141.07:54:52.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:52.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.07:54:52.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.07:54:52.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.07:54:52.97$vc4f8/vblo=5,744.99 2006.141.07:54:52.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.07:54:52.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.07:54:52.97#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:52.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:52.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:52.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:52.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:54:53.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:53.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.07:54:53.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.07:54:53.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.07:54:53.03$vc4f8/vb=5,4 2006.141.07:54:53.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.07:54:53.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.07:54:53.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:53.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:53.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:53.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:53.11#ibcon#[27=AT05-04\r\n] 2006.141.07:54:53.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:53.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.07:54:53.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.07:54:53.14#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:53.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:53.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:53.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:53.28#ibcon#[27=USB\r\n] 2006.141.07:54:53.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:53.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.07:54:53.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.07:54:53.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.07:54:53.31$vc4f8/vblo=6,752.99 2006.141.07:54:53.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.07:54:53.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.07:54:53.31#ibcon#ireg 17 cls_cnt 0 2006.141.07:54:53.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:54:53.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:54:53.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:54:53.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:54:53.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:54:53.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.07:54:53.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.07:54:53.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.07:54:53.37$vc4f8/vb=6,4 2006.141.07:54:53.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.07:54:53.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.07:54:53.37#ibcon#ireg 11 cls_cnt 2 2006.141.07:54:53.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:54:53.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:54:53.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:54:53.45#ibcon#[27=AT06-04\r\n] 2006.141.07:54:53.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:54:53.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.07:54:53.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.07:54:53.48#ibcon#ireg 7 cls_cnt 0 2006.141.07:54:53.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:54:53.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:54:53.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:54:53.62#ibcon#[27=USB\r\n] 2006.141.07:54:53.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:54:53.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.07:54:53.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.07:54:53.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.07:54:53.65$vc4f8/vabw=wide 2006.141.07:54:53.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.07:54:53.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.07:54:53.65#ibcon#ireg 8 cls_cnt 0 2006.141.07:54:53.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:53.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:53.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:53.67#ibcon#[25=BW32\r\n] 2006.141.07:54:53.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:53.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.07:54:53.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.07:54:53.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.07:54:53.70$vc4f8/vbbw=wide 2006.141.07:54:53.70#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.07:54:53.70#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.07:54:53.70#ibcon#ireg 8 cls_cnt 0 2006.141.07:54:53.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:54:53.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:54:53.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:54:53.79#ibcon#[27=BW32\r\n] 2006.141.07:54:53.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:54:53.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.07:54:53.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.07:54:53.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.07:54:53.82$4f8m12a/ifd4f 2006.141.07:54:53.82$ifd4f/lo= 2006.141.07:54:53.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:54:53.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:54:53.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:54:53.82$ifd4f/patch= 2006.141.07:54:53.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:54:53.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:54:53.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:54:53.82$4f8m12a/"form=m,16.000,1:2 2006.141.07:54:53.82$4f8m12a/"tpicd 2006.141.07:54:53.82$4f8m12a/echo=off 2006.141.07:54:53.82$4f8m12a/xlog=off 2006.141.07:54:53.82:!2006.141.07:55:50 2006.141.07:55:05.13#trakl#Source acquired 2006.141.07:55:05.13#flagr#flagr/antenna,acquired 2006.141.07:55:50.00:preob 2006.141.07:55:51.13/onsource/TRACKING 2006.141.07:55:51.13:!2006.141.07:56:00 2006.141.07:56:00.00:data_valid=on 2006.141.07:56:00.00:midob 2006.141.07:56:00.13/onsource/TRACKING 2006.141.07:56:00.13/wx/21.59,1012.7,72 2006.141.07:56:00.20/cable/+6.5215E-03 2006.141.07:56:01.29/va/01,08,usb,yes,29,31 2006.141.07:56:01.29/va/02,07,usb,yes,29,30 2006.141.07:56:01.29/va/03,06,usb,yes,31,31 2006.141.07:56:01.29/va/04,07,usb,yes,30,32 2006.141.07:56:01.29/va/05,07,usb,yes,28,30 2006.141.07:56:01.29/va/06,06,usb,yes,27,27 2006.141.07:56:01.29/va/07,06,usb,yes,28,28 2006.141.07:56:01.29/va/08,06,usb,yes,30,29 2006.141.07:56:01.52/valo/01,532.99,yes,locked 2006.141.07:56:01.52/valo/02,572.99,yes,locked 2006.141.07:56:01.52/valo/03,672.99,yes,locked 2006.141.07:56:01.52/valo/04,832.99,yes,locked 2006.141.07:56:01.52/valo/05,652.99,yes,locked 2006.141.07:56:01.52/valo/06,772.99,yes,locked 2006.141.07:56:01.52/valo/07,832.99,yes,locked 2006.141.07:56:01.52/valo/08,852.99,yes,locked 2006.141.07:56:02.61/vb/01,04,usb,yes,29,28 2006.141.07:56:02.61/vb/02,04,usb,yes,31,32 2006.141.07:56:02.61/vb/03,04,usb,yes,27,31 2006.141.07:56:02.61/vb/04,04,usb,yes,28,28 2006.141.07:56:02.61/vb/05,04,usb,yes,27,31 2006.141.07:56:02.61/vb/06,04,usb,yes,28,31 2006.141.07:56:02.61/vb/07,04,usb,yes,30,30 2006.141.07:56:02.61/vb/08,04,usb,yes,27,31 2006.141.07:56:02.84/vblo/01,632.99,yes,locked 2006.141.07:56:02.84/vblo/02,640.99,yes,locked 2006.141.07:56:02.84/vblo/03,656.99,yes,locked 2006.141.07:56:02.84/vblo/04,712.99,yes,locked 2006.141.07:56:02.84/vblo/05,744.99,yes,locked 2006.141.07:56:02.84/vblo/06,752.99,yes,locked 2006.141.07:56:02.84/vblo/07,734.99,yes,locked 2006.141.07:56:02.84/vblo/08,744.99,yes,locked 2006.141.07:56:02.99/vabw/8 2006.141.07:56:03.14/vbbw/8 2006.141.07:56:03.23/xfe/off,on,15.5 2006.141.07:56:03.62/ifatt/23,28,28,28 2006.141.07:56:04.12/fmout-gps/S +1.05E-07 2006.141.07:56:04.16:!2006.141.07:57:00 2006.141.07:57:00.00:data_valid=off 2006.141.07:57:00.00:postob 2006.141.07:57:00.16/cable/+6.5227E-03 2006.141.07:57:00.16/wx/21.56,1012.7,71 2006.141.07:57:01.12/fmout-gps/S +1.05E-07 2006.141.07:57:01.12:scan_name=141-0759,k06141,60 2006.141.07:57:01.12:source=1739+522,174036.98,521143.4,2000.0,cw 2006.141.07:57:01.14#flagr#flagr/antenna,new-source 2006.141.07:57:02.14:checkk5 2006.141.07:57:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.07:57:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.07:57:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.07:57:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.07:57:04.03/chk_obsdata//k5ts1/T1410756??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:57:04.41/chk_obsdata//k5ts2/T1410756??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:57:04.78/chk_obsdata//k5ts3/T1410756??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:57:05.15/chk_obsdata//k5ts4/T1410756??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.07:57:05.86/k5log//k5ts1_log_newline 2006.141.07:57:06.55/k5log//k5ts2_log_newline 2006.141.07:57:07.24/k5log//k5ts3_log_newline 2006.141.07:57:07.93/k5log//k5ts4_log_newline 2006.141.07:57:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.07:57:07.96:4f8m12a=2 2006.141.07:57:07.96$4f8m12a/echo=on 2006.141.07:57:07.96$4f8m12a/pcalon 2006.141.07:57:07.96$pcalon/"no phase cal control is implemented here 2006.141.07:57:07.96$4f8m12a/"tpicd=stop 2006.141.07:57:07.96$4f8m12a/vc4f8 2006.141.07:57:07.96$vc4f8/valo=1,532.99 2006.141.07:57:07.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:57:07.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:57:07.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:07.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:07.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:07.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:07.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.07:57:08.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:08.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:08.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:57:08.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:57:08.03$vc4f8/va=1,8 2006.141.07:57:08.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:57:08.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:57:08.03#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:08.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:08.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:08.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:08.05#ibcon#[25=AT01-08\r\n] 2006.141.07:57:08.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:08.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:08.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:57:08.09#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:08.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:08.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:08.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:08.23#ibcon#[25=USB\r\n] 2006.141.07:57:08.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:08.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:08.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:57:08.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:57:08.26$vc4f8/valo=2,572.99 2006.141.07:57:08.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:57:08.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:57:08.26#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:08.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:08.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:08.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.07:57:08.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:08.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:08.34#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:57:08.34#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:57:08.34$vc4f8/va=2,7 2006.141.07:57:08.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:57:08.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:57:08.34#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:08.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:08.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:08.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:08.40#ibcon#[25=AT02-07\r\n] 2006.141.07:57:08.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:08.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:08.43#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:57:08.43#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:08.43#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:08.55#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:08.55#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:08.57#ibcon#[25=USB\r\n] 2006.141.07:57:08.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:08.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:08.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:57:08.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:57:08.62$vc4f8/valo=3,672.99 2006.141.07:57:08.62#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:57:08.62#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:57:08.62#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:08.62#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:08.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:08.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.07:57:08.68#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:08.68#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:08.68#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:57:08.68#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:57:08.68$vc4f8/va=3,6 2006.141.07:57:08.68#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:57:08.68#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:57:08.68#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:08.68#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:08.74#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:08.74#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:08.76#ibcon#[25=AT03-06\r\n] 2006.141.07:57:08.79#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:08.79#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:08.79#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:57:08.79#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:08.79#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:08.91#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:08.91#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:08.93#ibcon#[25=USB\r\n] 2006.141.07:57:08.96#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:08.96#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:08.96#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:57:08.96#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:57:08.96$vc4f8/valo=4,832.99 2006.141.07:57:08.96#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:57:08.96#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:57:08.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:08.96#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:08.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:08.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.07:57:09.02#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:09.02#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:09.02#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:57:09.02#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:57:09.02$vc4f8/va=4,7 2006.141.07:57:09.02#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:57:09.02#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:57:09.02#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:09.02#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:09.08#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:09.08#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:09.10#ibcon#[25=AT04-07\r\n] 2006.141.07:57:09.13#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:09.13#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:09.13#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:57:09.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:09.13#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:09.25#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:09.25#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:09.27#ibcon#[25=USB\r\n] 2006.141.07:57:09.30#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:09.30#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:09.30#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:57:09.30#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:57:09.30$vc4f8/valo=5,652.99 2006.141.07:57:09.30#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:57:09.30#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:57:09.30#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:09.30#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:09.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:09.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.07:57:09.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:09.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:09.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:57:09.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:57:09.36$vc4f8/va=5,7 2006.141.07:57:09.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:57:09.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:57:09.36#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:09.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:09.42#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:09.42#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:09.44#ibcon#[25=AT05-07\r\n] 2006.141.07:57:09.47#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:09.47#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:09.47#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:57:09.47#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:09.47#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:09.59#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:09.59#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:09.61#ibcon#[25=USB\r\n] 2006.141.07:57:09.66#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:09.66#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:09.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:57:09.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:57:09.66$vc4f8/valo=6,772.99 2006.141.07:57:09.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:57:09.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:57:09.66#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:09.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:09.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:09.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:09.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.07:57:09.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:09.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:09.72#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:57:09.72#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:57:09.72$vc4f8/va=6,6 2006.141.07:57:09.72#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.07:57:09.72#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.07:57:09.72#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:09.72#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:09.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:09.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:09.80#ibcon#[25=AT06-06\r\n] 2006.141.07:57:09.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:09.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:09.83#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.07:57:09.83#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:09.83#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:57:09.95#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:57:09.95#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:57:09.97#ibcon#[25=USB\r\n] 2006.141.07:57:10.00#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:57:10.00#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.07:57:10.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:57:10.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:57:10.00$vc4f8/valo=7,832.99 2006.141.07:57:10.00#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.07:57:10.00#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.07:57:10.00#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:10.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:57:10.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:57:10.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:57:10.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.07:57:10.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:57:10.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.07:57:10.06#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.07:57:10.06#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.07:57:10.06$vc4f8/va=7,6 2006.141.07:57:10.06#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.07:57:10.06#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.07:57:10.06#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:10.06#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:57:10.12#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:57:10.12#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:57:10.14#ibcon#[25=AT07-06\r\n] 2006.141.07:57:10.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:57:10.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.07:57:10.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.07:57:10.17#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:10.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:57:10.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:57:10.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:57:10.31#ibcon#[25=USB\r\n] 2006.141.07:57:10.34#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:57:10.34#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.07:57:10.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.07:57:10.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.07:57:10.34$vc4f8/valo=8,852.99 2006.141.07:57:10.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.07:57:10.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.07:57:10.34#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:10.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:57:10.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:57:10.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:57:10.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.07:57:10.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:57:10.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.07:57:10.43#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.07:57:10.43#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.07:57:10.43$vc4f8/va=8,6 2006.141.07:57:10.43#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.07:57:10.43#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.07:57:10.43#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:10.43#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:57:10.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:57:10.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:57:10.48#ibcon#[25=AT08-06\r\n] 2006.141.07:57:10.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:57:10.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.07:57:10.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.07:57:10.51#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:10.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:57:10.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:57:10.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:57:10.65#ibcon#[25=USB\r\n] 2006.141.07:57:10.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:57:10.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.07:57:10.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.07:57:10.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.07:57:10.68$vc4f8/vblo=1,632.99 2006.141.07:57:10.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.07:57:10.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.07:57:10.68#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:10.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:57:10.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:57:10.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:57:10.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.07:57:10.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:57:10.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.07:57:10.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.07:57:10.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.07:57:10.74$vc4f8/vb=1,4 2006.141.07:57:10.74#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.07:57:10.74#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.07:57:10.74#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:10.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:57:10.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:57:10.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:57:10.76#ibcon#[27=AT01-04\r\n] 2006.141.07:57:10.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:57:10.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.07:57:10.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.07:57:10.79#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:10.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:57:10.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:57:10.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:57:10.93#ibcon#[27=USB\r\n] 2006.141.07:57:10.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:57:10.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.07:57:10.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.07:57:10.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.07:57:10.96$vc4f8/vblo=2,640.99 2006.141.07:57:10.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.07:57:10.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.07:57:10.96#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:10.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:10.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:10.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:11.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.07:57:11.04#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:11.04#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.07:57:11.04#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.07:57:11.04#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.07:57:11.04$vc4f8/vb=2,4 2006.141.07:57:11.04#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.07:57:11.04#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.07:57:11.04#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:11.04#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:11.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:11.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:11.10#ibcon#[27=AT02-04\r\n] 2006.141.07:57:11.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:11.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.07:57:11.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.07:57:11.13#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:11.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:11.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:11.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:11.27#ibcon#[27=USB\r\n] 2006.141.07:57:11.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:11.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.07:57:11.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.07:57:11.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.07:57:11.30$vc4f8/vblo=3,656.99 2006.141.07:57:11.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.07:57:11.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.07:57:11.30#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:11.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:11.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:11.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:11.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.07:57:11.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:11.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.07:57:11.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.07:57:11.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.07:57:11.36$vc4f8/vb=3,4 2006.141.07:57:11.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.07:57:11.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.07:57:11.36#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:11.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:11.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:11.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:11.44#ibcon#[27=AT03-04\r\n] 2006.141.07:57:11.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:11.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.07:57:11.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.07:57:11.47#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:11.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:11.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:11.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:11.61#ibcon#[27=USB\r\n] 2006.141.07:57:11.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:11.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.07:57:11.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.07:57:11.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.07:57:11.64$vc4f8/vblo=4,712.99 2006.141.07:57:11.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.07:57:11.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.07:57:11.64#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:11.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:11.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:11.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:11.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.07:57:11.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:11.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.07:57:11.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.07:57:11.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.07:57:11.71$vc4f8/vb=4,4 2006.141.07:57:11.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.07:57:11.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.07:57:11.71#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:11.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:11.76#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:11.76#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:11.78#ibcon#[27=AT04-04\r\n] 2006.141.07:57:11.81#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:11.81#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.07:57:11.81#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.07:57:11.81#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:11.81#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:11.93#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:11.93#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:11.95#ibcon#[27=USB\r\n] 2006.141.07:57:11.98#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:11.98#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.07:57:11.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.07:57:11.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.07:57:11.98$vc4f8/vblo=5,744.99 2006.141.07:57:11.98#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.07:57:11.98#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.07:57:11.98#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:11.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:11.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:11.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:12.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.07:57:12.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:12.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.07:57:12.04#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.07:57:12.04#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.07:57:12.04$vc4f8/vb=5,4 2006.141.07:57:12.04#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.07:57:12.04#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.07:57:12.04#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:12.04#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:12.10#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:12.10#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:12.12#ibcon#[27=AT05-04\r\n] 2006.141.07:57:12.15#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:12.15#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.07:57:12.15#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.07:57:12.15#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:12.15#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:12.27#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:12.27#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:12.29#ibcon#[27=USB\r\n] 2006.141.07:57:12.32#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:12.32#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.07:57:12.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.07:57:12.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.07:57:12.32$vc4f8/vblo=6,752.99 2006.141.07:57:12.32#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.07:57:12.32#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.07:57:12.32#ibcon#ireg 17 cls_cnt 0 2006.141.07:57:12.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:12.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:12.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:12.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.07:57:12.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:12.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.07:57:12.40#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.07:57:12.40#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.07:57:12.40$vc4f8/vb=6,4 2006.141.07:57:12.40#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.07:57:12.40#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.07:57:12.40#ibcon#ireg 11 cls_cnt 2 2006.141.07:57:12.40#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:12.44#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:12.44#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:12.46#ibcon#[27=AT06-04\r\n] 2006.141.07:57:12.49#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:12.49#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.07:57:12.49#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.07:57:12.49#ibcon#ireg 7 cls_cnt 0 2006.141.07:57:12.49#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:12.61#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:12.61#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:12.63#ibcon#[27=USB\r\n] 2006.141.07:57:12.66#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:12.66#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.07:57:12.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.07:57:12.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.07:57:12.66$vc4f8/vabw=wide 2006.141.07:57:12.66#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.07:57:12.66#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.07:57:12.66#ibcon#ireg 8 cls_cnt 0 2006.141.07:57:12.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:12.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:12.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:12.68#ibcon#[25=BW32\r\n] 2006.141.07:57:12.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:12.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.07:57:12.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.07:57:12.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.07:57:12.71$vc4f8/vbbw=wide 2006.141.07:57:12.71#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.07:57:12.71#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.07:57:12.71#ibcon#ireg 8 cls_cnt 0 2006.141.07:57:12.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:57:12.78#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:57:12.78#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:57:12.80#ibcon#[27=BW32\r\n] 2006.141.07:57:12.83#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:57:12.83#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.07:57:12.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.07:57:12.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.07:57:12.83$4f8m12a/ifd4f 2006.141.07:57:12.83$ifd4f/lo= 2006.141.07:57:12.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.07:57:12.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.07:57:12.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.07:57:12.83$ifd4f/patch= 2006.141.07:57:12.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.07:57:12.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.07:57:12.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.07:57:12.83$4f8m12a/"form=m,16.000,1:2 2006.141.07:57:12.83$4f8m12a/"tpicd 2006.141.07:57:12.83$4f8m12a/echo=off 2006.141.07:57:12.83$4f8m12a/xlog=off 2006.141.07:57:12.83:!2006.141.07:59:20 2006.141.07:57:51.14#trakl#Source acquired 2006.141.07:57:52.14#flagr#flagr/antenna,acquired 2006.141.07:59:20.00:preob 2006.141.07:59:20.14/onsource/TRACKING 2006.141.07:59:20.14:!2006.141.07:59:30 2006.141.07:59:30.00:data_valid=on 2006.141.07:59:30.00:midob 2006.141.07:59:31.14/onsource/TRACKING 2006.141.07:59:31.14/wx/21.50,1012.7,71 2006.141.07:59:31.36/cable/+6.5204E-03 2006.141.07:59:32.45/va/01,08,usb,yes,34,36 2006.141.07:59:32.45/va/02,07,usb,yes,34,35 2006.141.07:59:32.45/va/03,06,usb,yes,36,36 2006.141.07:59:32.45/va/04,07,usb,yes,35,37 2006.141.07:59:32.45/va/05,07,usb,yes,34,36 2006.141.07:59:32.45/va/06,06,usb,yes,33,33 2006.141.07:59:32.45/va/07,06,usb,yes,33,33 2006.141.07:59:32.45/va/08,06,usb,yes,36,35 2006.141.07:59:32.68/valo/01,532.99,yes,locked 2006.141.07:59:32.68/valo/02,572.99,yes,locked 2006.141.07:59:32.68/valo/03,672.99,yes,locked 2006.141.07:59:32.68/valo/04,832.99,yes,locked 2006.141.07:59:32.68/valo/05,652.99,yes,locked 2006.141.07:59:32.68/valo/06,772.99,yes,locked 2006.141.07:59:32.68/valo/07,832.99,yes,locked 2006.141.07:59:32.68/valo/08,852.99,yes,locked 2006.141.07:59:33.77/vb/01,04,usb,yes,32,32 2006.141.07:59:33.77/vb/02,04,usb,yes,34,36 2006.141.07:59:33.77/vb/03,04,usb,yes,30,34 2006.141.07:59:33.77/vb/04,04,usb,yes,31,31 2006.141.07:59:33.77/vb/05,04,usb,yes,30,34 2006.141.07:59:33.77/vb/06,04,usb,yes,31,34 2006.141.07:59:33.77/vb/07,04,usb,yes,33,33 2006.141.07:59:33.77/vb/08,04,usb,yes,30,34 2006.141.07:59:34.01/vblo/01,632.99,yes,locked 2006.141.07:59:34.01/vblo/02,640.99,yes,locked 2006.141.07:59:34.01/vblo/03,656.99,yes,locked 2006.141.07:59:34.01/vblo/04,712.99,yes,locked 2006.141.07:59:34.01/vblo/05,744.99,yes,locked 2006.141.07:59:34.01/vblo/06,752.99,yes,locked 2006.141.07:59:34.01/vblo/07,734.99,yes,locked 2006.141.07:59:34.01/vblo/08,744.99,yes,locked 2006.141.07:59:34.16/vabw/8 2006.141.07:59:34.31/vbbw/8 2006.141.07:59:34.40/xfe/off,on,14.2 2006.141.07:59:34.77/ifatt/23,28,28,28 2006.141.07:59:35.12/fmout-gps/S +1.06E-07 2006.141.07:59:35.16:!2006.141.08:00:30 2006.141.08:00:30.00:data_valid=off 2006.141.08:00:30.00:postob 2006.141.08:00:30.21/cable/+6.5231E-03 2006.141.08:00:30.21/wx/21.48,1012.8,71 2006.141.08:00:31.12/fmout-gps/S +1.05E-07 2006.141.08:00:31.12:scan_name=141-0801,k06141,60 2006.141.08:00:31.12:source=1418+546,141946.60,542314.8,2000.0,cw 2006.141.08:00:31.14#flagr#flagr/antenna,new-source 2006.141.08:00:32.14:checkk5 2006.141.08:00:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:00:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:00:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:00:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:00:34.03/chk_obsdata//k5ts1/T1410759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:00:34.40/chk_obsdata//k5ts2/T1410759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:00:34.77/chk_obsdata//k5ts3/T1410759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:00:35.14/chk_obsdata//k5ts4/T1410759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:00:35.85/k5log//k5ts1_log_newline 2006.141.08:00:36.54/k5log//k5ts2_log_newline 2006.141.08:00:37.23/k5log//k5ts3_log_newline 2006.141.08:00:37.93/k5log//k5ts4_log_newline 2006.141.08:00:37.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:00:37.95:4f8m12a=2 2006.141.08:00:37.95$4f8m12a/echo=on 2006.141.08:00:37.95$4f8m12a/pcalon 2006.141.08:00:37.95$pcalon/"no phase cal control is implemented here 2006.141.08:00:37.95$4f8m12a/"tpicd=stop 2006.141.08:00:37.95$4f8m12a/vc4f8 2006.141.08:00:37.95$vc4f8/valo=1,532.99 2006.141.08:00:37.96#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:00:37.96#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:00:37.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:37.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:37.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:37.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:38.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:00:38.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:38.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:38.05#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:00:38.05#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:00:38.05$vc4f8/va=1,8 2006.141.08:00:38.05#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:00:38.05#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:00:38.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:38.05#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:38.05#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:38.05#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:38.08#ibcon#[25=AT01-08\r\n] 2006.141.08:00:38.12#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:38.12#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:38.12#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:00:38.12#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:38.12#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:38.24#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:38.24#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:38.26#ibcon#[25=USB\r\n] 2006.141.08:00:38.31#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:38.31#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:38.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:00:38.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:00:38.31$vc4f8/valo=2,572.99 2006.141.08:00:38.31#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:00:38.31#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:00:38.31#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:38.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:38.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:38.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:38.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:00:38.37#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:38.37#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:38.37#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:00:38.37#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:00:38.37$vc4f8/va=2,7 2006.141.08:00:38.37#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.08:00:38.37#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.08:00:38.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:38.37#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:38.43#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:38.43#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:38.45#ibcon#[25=AT02-07\r\n] 2006.141.08:00:38.50#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:38.50#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:38.50#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.08:00:38.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:38.50#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:38.62#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:38.62#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:38.64#ibcon#[25=USB\r\n] 2006.141.08:00:38.69#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:38.69#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:38.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:00:38.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:00:38.69$vc4f8/valo=3,672.99 2006.141.08:00:38.69#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.08:00:38.69#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.08:00:38.69#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:38.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:38.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:38.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:38.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:00:38.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:38.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:38.75#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:00:38.75#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:00:38.75$vc4f8/va=3,6 2006.141.08:00:38.75#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.08:00:38.75#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.08:00:38.75#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:38.75#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:38.81#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:38.81#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:38.83#ibcon#[25=AT03-06\r\n] 2006.141.08:00:38.86#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:38.86#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:38.86#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.08:00:38.86#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:38.86#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:38.98#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:38.98#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:39.00#ibcon#[25=USB\r\n] 2006.141.08:00:39.03#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:39.03#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:39.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:00:39.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:00:39.03$vc4f8/valo=4,832.99 2006.141.08:00:39.03#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.08:00:39.03#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.08:00:39.03#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:39.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:39.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:39.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:39.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:00:39.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:39.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:39.09#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:00:39.09#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:00:39.09$vc4f8/va=4,7 2006.141.08:00:39.09#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.08:00:39.09#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.08:00:39.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:39.09#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:39.15#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:39.15#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:39.17#ibcon#[25=AT04-07\r\n] 2006.141.08:00:39.20#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:39.20#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:39.20#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.08:00:39.20#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:39.20#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:39.32#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:39.32#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:39.34#ibcon#[25=USB\r\n] 2006.141.08:00:39.37#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:39.37#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:39.37#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:00:39.37#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:00:39.37$vc4f8/valo=5,652.99 2006.141.08:00:39.37#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.08:00:39.37#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.08:00:39.37#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:39.37#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:39.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:39.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:39.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:00:39.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:39.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:39.44#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:00:39.44#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:00:39.44$vc4f8/va=5,7 2006.141.08:00:39.44#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.08:00:39.44#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.08:00:39.44#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:39.44#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:39.49#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:39.49#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:39.51#ibcon#[25=AT05-07\r\n] 2006.141.08:00:39.54#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:39.54#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:39.54#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.08:00:39.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:39.54#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:39.66#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:39.66#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:39.68#ibcon#[25=USB\r\n] 2006.141.08:00:39.71#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:39.71#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:39.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:00:39.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:00:39.71$vc4f8/valo=6,772.99 2006.141.08:00:39.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:00:39.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:00:39.71#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:39.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:39.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:39.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:39.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:00:39.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:39.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:39.77#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:00:39.77#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:00:39.77$vc4f8/va=6,6 2006.141.08:00:39.77#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.08:00:39.77#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.08:00:39.77#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:39.77#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:39.83#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:39.83#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:39.85#ibcon#[25=AT06-06\r\n] 2006.141.08:00:39.88#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:39.88#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:39.88#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.08:00:39.88#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:39.88#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:00:40.00#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:00:40.00#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:00:40.02#ibcon#[25=USB\r\n] 2006.141.08:00:40.05#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:00:40.05#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:00:40.05#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:00:40.05#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:00:40.05$vc4f8/valo=7,832.99 2006.141.08:00:40.05#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.08:00:40.05#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.08:00:40.05#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:40.05#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:00:40.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:00:40.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:00:40.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:00:40.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:00:40.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:00:40.12#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:00:40.12#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:00:40.12$vc4f8/va=7,6 2006.141.08:00:40.12#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.08:00:40.12#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.08:00:40.12#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:40.12#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:00:40.17#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:00:40.17#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:00:40.19#ibcon#[25=AT07-06\r\n] 2006.141.08:00:40.22#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:00:40.22#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:00:40.22#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.08:00:40.22#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:40.22#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:00:40.34#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:00:40.34#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:00:40.36#ibcon#[25=USB\r\n] 2006.141.08:00:40.39#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:00:40.39#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:00:40.39#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:00:40.39#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:00:40.39$vc4f8/valo=8,852.99 2006.141.08:00:40.39#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:00:40.39#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:00:40.39#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:40.39#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:00:40.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:00:40.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:00:40.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:00:40.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:00:40.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:00:40.45#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:00:40.45#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:00:40.45$vc4f8/va=8,6 2006.141.08:00:40.45#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.08:00:40.45#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.08:00:40.45#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:40.45#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:00:40.51#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:00:40.51#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:00:40.53#ibcon#[25=AT08-06\r\n] 2006.141.08:00:40.56#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:00:40.56#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:00:40.56#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.08:00:40.56#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:40.56#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:00:40.68#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:00:40.68#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:00:40.70#ibcon#[25=USB\r\n] 2006.141.08:00:40.75#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:00:40.75#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:00:40.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:00:40.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:00:40.75$vc4f8/vblo=1,632.99 2006.141.08:00:40.75#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.08:00:40.75#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.08:00:40.75#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:40.75#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:00:40.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:00:40.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:00:40.77#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:00:40.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:00:40.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:00:40.81#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:00:40.81#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:00:40.81$vc4f8/vb=1,4 2006.141.08:00:40.81#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.08:00:40.81#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.08:00:40.81#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:40.81#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:00:40.81#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:00:40.81#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:00:40.83#ibcon#[27=AT01-04\r\n] 2006.141.08:00:40.86#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:00:40.86#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:00:40.86#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.08:00:40.86#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:40.86#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:00:40.98#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:00:40.98#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:00:41.00#ibcon#[27=USB\r\n] 2006.141.08:00:41.03#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:00:41.03#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:00:41.03#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:00:41.03#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:00:41.03$vc4f8/vblo=2,640.99 2006.141.08:00:41.03#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:00:41.03#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:00:41.03#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:41.03#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:41.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:41.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:41.05#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:00:41.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:41.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:00:41.09#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:00:41.09#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:00:41.09$vc4f8/vb=2,4 2006.141.08:00:41.09#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:00:41.09#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:00:41.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:41.09#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:41.15#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:41.15#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:41.17#ibcon#[27=AT02-04\r\n] 2006.141.08:00:41.20#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:41.20#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:00:41.20#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:00:41.20#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:41.20#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:41.32#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:41.32#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:41.34#ibcon#[27=USB\r\n] 2006.141.08:00:41.39#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:41.39#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:00:41.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:00:41.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:00:41.39$vc4f8/vblo=3,656.99 2006.141.08:00:41.39#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:00:41.39#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:00:41.39#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:41.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:41.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:41.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:41.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:00:41.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:41.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:00:41.45#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:00:41.45#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:00:41.45$vc4f8/vb=3,4 2006.141.08:00:41.45#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.08:00:41.45#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.08:00:41.45#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:41.45#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:41.51#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:41.51#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:41.53#ibcon#[27=AT03-04\r\n] 2006.141.08:00:41.56#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:41.56#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:00:41.56#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.08:00:41.56#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:41.56#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:41.68#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:41.68#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:41.70#ibcon#[27=USB\r\n] 2006.141.08:00:41.73#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:41.73#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:00:41.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:00:41.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:00:41.73$vc4f8/vblo=4,712.99 2006.141.08:00:41.73#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.08:00:41.73#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.08:00:41.73#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:41.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:41.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:41.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:41.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:00:41.79#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:41.79#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:00:41.79#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:00:41.79#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:00:41.79$vc4f8/vb=4,4 2006.141.08:00:41.79#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.08:00:41.79#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.08:00:41.79#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:41.79#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:41.85#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:41.85#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:41.87#ibcon#[27=AT04-04\r\n] 2006.141.08:00:41.90#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:41.90#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:00:41.90#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.08:00:41.90#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:41.90#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:42.02#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:42.02#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:42.04#ibcon#[27=USB\r\n] 2006.141.08:00:42.07#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:42.07#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:00:42.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:00:42.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:00:42.07$vc4f8/vblo=5,744.99 2006.141.08:00:42.07#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.08:00:42.07#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.08:00:42.07#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:42.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:42.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:42.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:42.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:00:42.13#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:42.13#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:00:42.13#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:00:42.13#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:00:42.13$vc4f8/vb=5,4 2006.141.08:00:42.13#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.08:00:42.13#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.08:00:42.13#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:42.13#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:42.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:42.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:42.21#ibcon#[27=AT05-04\r\n] 2006.141.08:00:42.24#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:42.24#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:00:42.24#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.08:00:42.24#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:42.24#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:42.36#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:42.36#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:42.38#ibcon#[27=USB\r\n] 2006.141.08:00:42.41#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:42.41#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:00:42.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:00:42.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:00:42.41$vc4f8/vblo=6,752.99 2006.141.08:00:42.41#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.08:00:42.41#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.08:00:42.41#ibcon#ireg 17 cls_cnt 0 2006.141.08:00:42.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:42.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:42.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:42.43#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:00:42.47#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:42.47#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:00:42.47#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:00:42.47#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:00:42.47$vc4f8/vb=6,4 2006.141.08:00:42.47#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.08:00:42.47#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.08:00:42.47#ibcon#ireg 11 cls_cnt 2 2006.141.08:00:42.47#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:42.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:42.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:42.55#ibcon#[27=AT06-04\r\n] 2006.141.08:00:42.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:42.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:00:42.58#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.08:00:42.58#ibcon#ireg 7 cls_cnt 0 2006.141.08:00:42.58#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:42.70#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:42.70#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:42.72#ibcon#[27=USB\r\n] 2006.141.08:00:42.75#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:42.75#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:00:42.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:00:42.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:00:42.75$vc4f8/vabw=wide 2006.141.08:00:42.75#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:00:42.75#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:00:42.75#ibcon#ireg 8 cls_cnt 0 2006.141.08:00:42.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:42.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:42.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:42.77#ibcon#[25=BW32\r\n] 2006.141.08:00:42.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:42.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:00:42.80#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:00:42.80#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:00:42.80$vc4f8/vbbw=wide 2006.141.08:00:42.80#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:00:42.80#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:00:42.80#ibcon#ireg 8 cls_cnt 0 2006.141.08:00:42.80#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:00:42.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:00:42.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:00:42.89#ibcon#[27=BW32\r\n] 2006.141.08:00:42.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:00:42.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:00:42.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:00:42.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:00:42.92$4f8m12a/ifd4f 2006.141.08:00:42.92$ifd4f/lo= 2006.141.08:00:42.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:00:42.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:00:42.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:00:42.92$ifd4f/patch= 2006.141.08:00:42.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:00:42.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:00:42.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:00:42.92$4f8m12a/"form=m,16.000,1:2 2006.141.08:00:42.92$4f8m12a/"tpicd 2006.141.08:00:42.92$4f8m12a/echo=off 2006.141.08:00:42.92$4f8m12a/xlog=off 2006.141.08:00:42.92:!2006.141.08:01:10 2006.141.08:00:53.14#trakl#Source acquired 2006.141.08:00:55.14#flagr#flagr/antenna,acquired 2006.141.08:01:10.00:preob 2006.141.08:01:11.14/onsource/TRACKING 2006.141.08:01:11.14:!2006.141.08:01:20 2006.141.08:01:20.00:data_valid=on 2006.141.08:01:20.00:midob 2006.141.08:01:20.14/onsource/TRACKING 2006.141.08:01:20.14/wx/21.46,1012.7,71 2006.141.08:01:20.21/cable/+6.5223E-03 2006.141.08:01:21.30/va/01,08,usb,yes,29,31 2006.141.08:01:21.30/va/02,07,usb,yes,29,30 2006.141.08:01:21.30/va/03,06,usb,yes,30,31 2006.141.08:01:21.30/va/04,07,usb,yes,29,32 2006.141.08:01:21.30/va/05,07,usb,yes,29,30 2006.141.08:01:21.30/va/06,06,usb,yes,28,27 2006.141.08:01:21.30/va/07,06,usb,yes,28,28 2006.141.08:01:21.30/va/08,06,usb,yes,30,30 2006.141.08:01:21.53/valo/01,532.99,yes,locked 2006.141.08:01:21.53/valo/02,572.99,yes,locked 2006.141.08:01:21.53/valo/03,672.99,yes,locked 2006.141.08:01:21.53/valo/04,832.99,yes,locked 2006.141.08:01:21.53/valo/05,652.99,yes,locked 2006.141.08:01:21.53/valo/06,772.99,yes,locked 2006.141.08:01:21.53/valo/07,832.99,yes,locked 2006.141.08:01:21.53/valo/08,852.99,yes,locked 2006.141.08:01:22.62/vb/01,04,usb,yes,29,28 2006.141.08:01:22.62/vb/02,04,usb,yes,31,32 2006.141.08:01:22.62/vb/03,04,usb,yes,27,31 2006.141.08:01:22.62/vb/04,04,usb,yes,28,28 2006.141.08:01:22.62/vb/05,04,usb,yes,26,30 2006.141.08:01:22.62/vb/06,04,usb,yes,27,30 2006.141.08:01:22.62/vb/07,04,usb,yes,29,29 2006.141.08:01:22.62/vb/08,04,usb,yes,27,30 2006.141.08:01:22.85/vblo/01,632.99,yes,locked 2006.141.08:01:22.85/vblo/02,640.99,yes,locked 2006.141.08:01:22.85/vblo/03,656.99,yes,locked 2006.141.08:01:22.85/vblo/04,712.99,yes,locked 2006.141.08:01:22.85/vblo/05,744.99,yes,locked 2006.141.08:01:22.85/vblo/06,752.99,yes,locked 2006.141.08:01:22.85/vblo/07,734.99,yes,locked 2006.141.08:01:22.85/vblo/08,744.99,yes,locked 2006.141.08:01:23.00/vabw/8 2006.141.08:01:23.15/vbbw/8 2006.141.08:01:23.24/xfe/off,on,15.0 2006.141.08:01:23.63/ifatt/23,28,28,28 2006.141.08:01:24.12/fmout-gps/S +1.06E-07 2006.141.08:01:24.16:!2006.141.08:02:20 2006.141.08:02:20.00:data_valid=off 2006.141.08:02:20.00:postob 2006.141.08:02:20.10/cable/+6.5213E-03 2006.141.08:02:20.10/wx/21.45,1012.7,72 2006.141.08:02:21.12/fmout-gps/S +1.05E-07 2006.141.08:02:21.12:scan_name=141-0803,k06141,60 2006.141.08:02:21.12:source=0955+476,095819.67,472507.8,2000.0,cw 2006.141.08:02:23.13#flagr#flagr/antenna,new-source 2006.141.08:02:23.13:checkk5 2006.141.08:02:23.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:02:23.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:02:24.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:02:24.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:02:25.03/chk_obsdata//k5ts1/T1410801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:02:25.40/chk_obsdata//k5ts2/T1410801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:02:25.78/chk_obsdata//k5ts3/T1410801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:02:26.15/chk_obsdata//k5ts4/T1410801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:02:26.84/k5log//k5ts1_log_newline 2006.141.08:02:27.53/k5log//k5ts2_log_newline 2006.141.08:02:28.24/k5log//k5ts3_log_newline 2006.141.08:02:28.93/k5log//k5ts4_log_newline 2006.141.08:02:28.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:02:28.95:4f8m12a=2 2006.141.08:02:28.95$4f8m12a/echo=on 2006.141.08:02:28.95$4f8m12a/pcalon 2006.141.08:02:28.95$pcalon/"no phase cal control is implemented here 2006.141.08:02:28.95$4f8m12a/"tpicd=stop 2006.141.08:02:28.95$4f8m12a/vc4f8 2006.141.08:02:28.95$vc4f8/valo=1,532.99 2006.141.08:02:28.95#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:02:28.95#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:02:28.95#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:28.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:28.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:28.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:28.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:02:29.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:29.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:29.01#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:02:29.01#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:02:29.01$vc4f8/va=1,8 2006.141.08:02:29.01#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:02:29.01#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:02:29.01#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:29.01#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:29.01#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:29.01#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:29.03#ibcon#[25=AT01-08\r\n] 2006.141.08:02:29.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:29.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:29.06#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:02:29.06#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:29.06#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:29.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:29.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:29.21#ibcon#[25=USB\r\n] 2006.141.08:02:29.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:29.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:29.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:02:29.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:02:29.24$vc4f8/valo=2,572.99 2006.141.08:02:29.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:02:29.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:02:29.24#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:29.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:29.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:29.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:29.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:02:29.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:29.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:29.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:02:29.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:02:29.32$vc4f8/va=2,7 2006.141.08:02:29.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:02:29.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:02:29.32#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:29.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:29.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:29.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:29.38#ibcon#[25=AT02-07\r\n] 2006.141.08:02:29.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:29.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:29.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:02:29.41#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:29.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:29.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:29.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:29.55#ibcon#[25=USB\r\n] 2006.141.08:02:29.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:29.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:29.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:02:29.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:02:29.58$vc4f8/valo=3,672.99 2006.141.08:02:29.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:02:29.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:02:29.58#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:29.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:29.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:29.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:29.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:02:29.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:29.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:29.66#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:02:29.66#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:02:29.66$vc4f8/va=3,6 2006.141.08:02:29.66#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:02:29.66#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:02:29.66#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:29.66#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:29.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:29.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:29.72#ibcon#[25=AT03-06\r\n] 2006.141.08:02:29.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:29.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:29.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:02:29.75#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:29.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:29.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:29.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:29.89#ibcon#[25=USB\r\n] 2006.141.08:02:29.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:29.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:29.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:02:29.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:02:29.92$vc4f8/valo=4,832.99 2006.141.08:02:29.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:02:29.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:02:29.92#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:29.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:29.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:29.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:29.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:02:29.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:29.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:29.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:02:29.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:02:29.98$vc4f8/va=4,7 2006.141.08:02:29.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:02:29.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:02:29.98#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:29.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:30.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:30.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:30.06#ibcon#[25=AT04-07\r\n] 2006.141.08:02:30.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:30.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:30.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:02:30.09#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:30.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:30.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:30.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:30.23#ibcon#[25=USB\r\n] 2006.141.08:02:30.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:30.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:30.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:02:30.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:02:30.26$vc4f8/valo=5,652.99 2006.141.08:02:30.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:02:30.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:02:30.26#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:30.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:30.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:30.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:30.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:02:30.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:30.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:30.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:02:30.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:02:30.32$vc4f8/va=5,7 2006.141.08:02:30.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:02:30.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:02:30.32#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:30.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:30.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:30.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:30.40#ibcon#[25=AT05-07\r\n] 2006.141.08:02:30.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:30.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:30.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:02:30.43#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:30.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:30.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:30.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:30.57#ibcon#[25=USB\r\n] 2006.141.08:02:30.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:30.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:30.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:02:30.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:02:30.60$vc4f8/valo=6,772.99 2006.141.08:02:30.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:02:30.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:02:30.60#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:30.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:30.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:30.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:30.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:02:30.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:30.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:30.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:02:30.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:02:30.66$vc4f8/va=6,6 2006.141.08:02:30.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:02:30.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:02:30.66#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:30.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:30.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:30.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:30.74#ibcon#[25=AT06-06\r\n] 2006.141.08:02:30.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:30.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:30.77#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:02:30.77#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:30.77#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:02:30.89#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:02:30.89#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:02:30.91#ibcon#[25=USB\r\n] 2006.141.08:02:30.94#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:02:30.94#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:02:30.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:02:30.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:02:30.94$vc4f8/valo=7,832.99 2006.141.08:02:30.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:02:30.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:02:30.94#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:30.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:02:30.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:02:30.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:02:30.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:02:31.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:02:31.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:02:31.00#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:02:31.00#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:02:31.00$vc4f8/va=7,6 2006.141.08:02:31.00#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.08:02:31.00#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.08:02:31.00#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:31.00#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:02:31.06#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:02:31.06#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:02:31.08#ibcon#[25=AT07-06\r\n] 2006.141.08:02:31.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:02:31.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:02:31.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.08:02:31.11#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:31.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:02:31.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:02:31.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:02:31.25#ibcon#[25=USB\r\n] 2006.141.08:02:31.28#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:02:31.28#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:02:31.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:02:31.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:02:31.28$vc4f8/valo=8,852.99 2006.141.08:02:31.28#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.08:02:31.28#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.08:02:31.28#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:31.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:02:31.28#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:02:31.28#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:02:31.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:02:31.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:02:31.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:02:31.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:02:31.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:02:31.34$vc4f8/va=8,6 2006.141.08:02:31.34#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.08:02:31.34#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.08:02:31.34#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:31.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:02:31.40#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:02:31.40#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:02:31.42#ibcon#[25=AT08-06\r\n] 2006.141.08:02:31.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:02:31.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:02:31.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.08:02:31.45#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:31.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:02:31.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:02:31.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:02:31.59#ibcon#[25=USB\r\n] 2006.141.08:02:31.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:02:31.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:02:31.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:02:31.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:02:31.62$vc4f8/vblo=1,632.99 2006.141.08:02:31.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.08:02:31.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.08:02:31.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:31.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:02:31.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:02:31.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:02:31.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:02:31.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:02:31.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:02:31.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:02:31.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:02:31.68$vc4f8/vb=1,4 2006.141.08:02:31.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.08:02:31.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.08:02:31.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:31.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:02:31.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:02:31.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:02:31.70#ibcon#[27=AT01-04\r\n] 2006.141.08:02:31.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:02:31.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:02:31.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.08:02:31.73#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:31.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:02:31.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:02:31.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:02:31.87#ibcon#[27=USB\r\n] 2006.141.08:02:31.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:02:31.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:02:31.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:02:31.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:02:31.90$vc4f8/vblo=2,640.99 2006.141.08:02:31.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:02:31.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:02:31.90#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:31.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:31.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:31.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:31.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:02:31.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:31.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:02:31.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:02:31.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:02:31.96$vc4f8/vb=2,4 2006.141.08:02:31.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:02:31.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:02:31.96#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:31.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:32.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:32.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:32.04#ibcon#[27=AT02-04\r\n] 2006.141.08:02:32.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:32.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:02:32.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:02:32.07#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:32.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:32.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:32.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:32.21#ibcon#[27=USB\r\n] 2006.141.08:02:32.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:32.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:02:32.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:02:32.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:02:32.24$vc4f8/vblo=3,656.99 2006.141.08:02:32.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:02:32.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:02:32.24#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:32.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:32.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:32.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:32.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:02:32.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:32.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:02:32.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:02:32.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:02:32.30$vc4f8/vb=3,4 2006.141.08:02:32.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:02:32.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:02:32.30#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:32.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:32.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:32.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:32.38#ibcon#[27=AT03-04\r\n] 2006.141.08:02:32.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:32.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:02:32.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:02:32.41#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:32.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:32.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:32.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:32.55#ibcon#[27=USB\r\n] 2006.141.08:02:32.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:32.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:02:32.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:02:32.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:02:32.58$vc4f8/vblo=4,712.99 2006.141.08:02:32.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:02:32.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:02:32.58#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:32.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:32.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:32.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:32.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:02:32.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:32.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:02:32.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:02:32.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:02:32.64$vc4f8/vb=4,4 2006.141.08:02:32.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:02:32.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:02:32.64#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:32.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:32.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:32.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:32.72#ibcon#[27=AT04-04\r\n] 2006.141.08:02:32.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:32.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:02:32.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:02:32.75#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:32.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:32.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:32.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:32.89#ibcon#[27=USB\r\n] 2006.141.08:02:32.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:32.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:02:32.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:02:32.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:02:32.92$vc4f8/vblo=5,744.99 2006.141.08:02:32.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:02:32.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:02:32.92#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:32.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:32.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:32.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:32.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:02:32.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:32.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:02:32.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:02:32.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:02:32.98$vc4f8/vb=5,4 2006.141.08:02:32.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:02:32.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:02:32.98#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:32.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:33.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:33.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:33.06#ibcon#[27=AT05-04\r\n] 2006.141.08:02:33.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:33.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:02:33.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:02:33.09#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:33.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:33.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:33.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:33.23#ibcon#[27=USB\r\n] 2006.141.08:02:33.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:33.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:02:33.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:02:33.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:02:33.26$vc4f8/vblo=6,752.99 2006.141.08:02:33.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:02:33.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:02:33.26#ibcon#ireg 17 cls_cnt 0 2006.141.08:02:33.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:33.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:33.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:33.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:02:33.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:33.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:02:33.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:02:33.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:02:33.32$vc4f8/vb=6,4 2006.141.08:02:33.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:02:33.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:02:33.32#ibcon#ireg 11 cls_cnt 2 2006.141.08:02:33.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:33.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:33.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:33.40#ibcon#[27=AT06-04\r\n] 2006.141.08:02:33.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:33.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:02:33.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:02:33.43#ibcon#ireg 7 cls_cnt 0 2006.141.08:02:33.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:33.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:33.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:33.57#ibcon#[27=USB\r\n] 2006.141.08:02:33.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:33.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:02:33.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:02:33.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:02:33.60$vc4f8/vabw=wide 2006.141.08:02:33.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:02:33.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:02:33.60#ibcon#ireg 8 cls_cnt 0 2006.141.08:02:33.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:33.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:33.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:33.64#ibcon#[25=BW32\r\n] 2006.141.08:02:33.67#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:33.67#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:02:33.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:02:33.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:02:33.67$vc4f8/vbbw=wide 2006.141.08:02:33.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.08:02:33.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.08:02:33.67#ibcon#ireg 8 cls_cnt 0 2006.141.08:02:33.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:02:33.72#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:02:33.72#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:02:33.74#ibcon#[27=BW32\r\n] 2006.141.08:02:33.77#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:02:33.77#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:02:33.77#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:02:33.77#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:02:33.77$4f8m12a/ifd4f 2006.141.08:02:33.77$ifd4f/lo= 2006.141.08:02:33.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:02:33.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:02:33.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:02:33.77$ifd4f/patch= 2006.141.08:02:33.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:02:33.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:02:33.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:02:33.77$4f8m12a/"form=m,16.000,1:2 2006.141.08:02:33.77$4f8m12a/"tpicd 2006.141.08:02:33.77$4f8m12a/echo=off 2006.141.08:02:33.77$4f8m12a/xlog=off 2006.141.08:02:33.77:!2006.141.08:03:00 2006.141.08:02:46.13#trakl#Source acquired 2006.141.08:02:48.13#flagr#flagr/antenna,acquired 2006.141.08:03:00.00:preob 2006.141.08:03:01.13/onsource/TRACKING 2006.141.08:03:01.13:!2006.141.08:03:10 2006.141.08:03:10.00:data_valid=on 2006.141.08:03:10.00:midob 2006.141.08:03:10.13/onsource/TRACKING 2006.141.08:03:10.13/wx/21.45,1012.7,72 2006.141.08:03:10.29/cable/+6.5211E-03 2006.141.08:03:11.38/va/01,08,usb,yes,28,30 2006.141.08:03:11.38/va/02,07,usb,yes,28,29 2006.141.08:03:11.38/va/03,06,usb,yes,30,30 2006.141.08:03:11.38/va/04,07,usb,yes,29,31 2006.141.08:03:11.38/va/05,07,usb,yes,28,29 2006.141.08:03:11.38/va/06,06,usb,yes,27,27 2006.141.08:03:11.38/va/07,06,usb,yes,27,27 2006.141.08:03:11.38/va/08,06,usb,yes,29,29 2006.141.08:03:11.61/valo/01,532.99,yes,locked 2006.141.08:03:11.61/valo/02,572.99,yes,locked 2006.141.08:03:11.61/valo/03,672.99,yes,locked 2006.141.08:03:11.61/valo/04,832.99,yes,locked 2006.141.08:03:11.61/valo/05,652.99,yes,locked 2006.141.08:03:11.61/valo/06,772.99,yes,locked 2006.141.08:03:11.61/valo/07,832.99,yes,locked 2006.141.08:03:11.61/valo/08,852.99,yes,locked 2006.141.08:03:12.70/vb/01,04,usb,yes,29,27 2006.141.08:03:12.70/vb/02,04,usb,yes,30,32 2006.141.08:03:12.70/vb/03,04,usb,yes,27,30 2006.141.08:03:12.70/vb/04,04,usb,yes,28,28 2006.141.08:03:12.70/vb/05,04,usb,yes,26,30 2006.141.08:03:12.70/vb/06,04,usb,yes,27,30 2006.141.08:03:12.70/vb/07,04,usb,yes,29,29 2006.141.08:03:12.70/vb/08,04,usb,yes,27,30 2006.141.08:03:12.94/vblo/01,632.99,yes,locked 2006.141.08:03:12.94/vblo/02,640.99,yes,locked 2006.141.08:03:12.94/vblo/03,656.99,yes,locked 2006.141.08:03:12.94/vblo/04,712.99,yes,locked 2006.141.08:03:12.94/vblo/05,744.99,yes,locked 2006.141.08:03:12.94/vblo/06,752.99,yes,locked 2006.141.08:03:12.94/vblo/07,734.99,yes,locked 2006.141.08:03:12.94/vblo/08,744.99,yes,locked 2006.141.08:03:13.09/vabw/8 2006.141.08:03:13.24/vbbw/8 2006.141.08:03:13.36/xfe/off,on,15.5 2006.141.08:03:13.73/ifatt/23,28,28,28 2006.141.08:03:14.11/fmout-gps/S +1.06E-07 2006.141.08:03:14.15:!2006.141.08:04:10 2006.141.08:04:10.00:data_valid=off 2006.141.08:04:10.00:postob 2006.141.08:04:10.09/cable/+6.5221E-03 2006.141.08:04:10.09/wx/21.44,1012.7,71 2006.141.08:04:11.11/fmout-gps/S +1.06E-07 2006.141.08:04:11.11:scan_name=141-0805,k06141,60 2006.141.08:04:11.11:source=4c39.25,092703.01,390220.9,2000.0,cw 2006.141.08:04:11.13#flagr#flagr/antenna,new-source 2006.141.08:04:12.13:checkk5 2006.141.08:04:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:04:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:04:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:04:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:04:14.03/chk_obsdata//k5ts1/T1410803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:04:14.40/chk_obsdata//k5ts2/T1410803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:04:14.78/chk_obsdata//k5ts3/T1410803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:04:15.16/chk_obsdata//k5ts4/T1410803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:04:15.85/k5log//k5ts1_log_newline 2006.141.08:04:16.55/k5log//k5ts2_log_newline 2006.141.08:04:17.25/k5log//k5ts3_log_newline 2006.141.08:04:17.93/k5log//k5ts4_log_newline 2006.141.08:04:17.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:04:17.96:4f8m12a=2 2006.141.08:04:17.96$4f8m12a/echo=on 2006.141.08:04:17.96$4f8m12a/pcalon 2006.141.08:04:17.96$pcalon/"no phase cal control is implemented here 2006.141.08:04:17.96$4f8m12a/"tpicd=stop 2006.141.08:04:17.96$4f8m12a/vc4f8 2006.141.08:04:17.96$vc4f8/valo=1,532.99 2006.141.08:04:17.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:04:17.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:04:17.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:17.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:17.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:17.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:04:18.03#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:18.03#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:18.03#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:04:18.03#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:04:18.03$vc4f8/va=1,8 2006.141.08:04:18.03#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.08:04:18.03#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.08:04:18.03#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:18.03#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:18.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:18.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:18.05#ibcon#[25=AT01-08\r\n] 2006.141.08:04:18.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:18.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:18.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.08:04:18.08#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:18.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:18.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:18.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:18.23#ibcon#[25=USB\r\n] 2006.141.08:04:18.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:18.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:18.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:04:18.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:04:18.26$vc4f8/valo=2,572.99 2006.141.08:04:18.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.08:04:18.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.08:04:18.26#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:18.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:18.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:18.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:18.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:04:18.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:18.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:18.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:04:18.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:04:18.34$vc4f8/va=2,7 2006.141.08:04:18.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.08:04:18.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.08:04:18.34#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:18.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:18.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:18.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:18.40#ibcon#[25=AT02-07\r\n] 2006.141.08:04:18.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:18.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:18.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.08:04:18.43#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:18.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:18.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:18.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:18.57#ibcon#[25=USB\r\n] 2006.141.08:04:18.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:18.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:18.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:04:18.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:04:18.62$vc4f8/valo=3,672.99 2006.141.08:04:18.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:04:18.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:04:18.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:18.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:18.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:18.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:18.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:04:18.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:18.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:18.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:04:18.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:04:18.68$vc4f8/va=3,6 2006.141.08:04:18.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:04:18.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:04:18.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:18.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:18.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:18.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:18.76#ibcon#[25=AT03-06\r\n] 2006.141.08:04:18.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:18.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:18.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:04:18.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:18.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:18.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:18.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:18.93#ibcon#[25=USB\r\n] 2006.141.08:04:18.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:18.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:18.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:04:18.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:04:18.96$vc4f8/valo=4,832.99 2006.141.08:04:18.96#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:04:18.96#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:04:18.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:18.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:18.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:18.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:18.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:04:19.02#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:19.02#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:19.02#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:04:19.02#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:04:19.02$vc4f8/va=4,7 2006.141.08:04:19.02#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:04:19.02#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:04:19.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:19.02#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:19.08#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:19.08#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:19.10#ibcon#[25=AT04-07\r\n] 2006.141.08:04:19.13#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:19.13#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:19.13#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:04:19.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:19.13#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:19.25#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:19.25#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:19.27#ibcon#[25=USB\r\n] 2006.141.08:04:19.30#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:19.30#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:19.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:04:19.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:04:19.30$vc4f8/valo=5,652.99 2006.141.08:04:19.30#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:04:19.30#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:04:19.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:19.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:19.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:19.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:19.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:04:19.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:19.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:19.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:04:19.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:04:19.36$vc4f8/va=5,7 2006.141.08:04:19.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:04:19.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:04:19.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:19.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:19.42#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:19.42#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:19.44#ibcon#[25=AT05-07\r\n] 2006.141.08:04:19.47#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:19.47#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:19.47#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:04:19.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:19.47#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:19.59#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:19.59#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:19.61#ibcon#[25=USB\r\n] 2006.141.08:04:19.64#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:19.64#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:19.64#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:04:19.64#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:04:19.64$vc4f8/valo=6,772.99 2006.141.08:04:19.64#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:04:19.64#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:04:19.64#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:19.64#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:19.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:19.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:19.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:04:19.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:19.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:19.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:04:19.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:04:19.70$vc4f8/va=6,6 2006.141.08:04:19.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:04:19.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:04:19.70#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:19.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:19.76#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:19.76#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:19.78#ibcon#[25=AT06-06\r\n] 2006.141.08:04:19.81#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:19.81#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:19.81#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:04:19.81#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:19.81#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:19.93#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:19.93#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:19.95#ibcon#[25=USB\r\n] 2006.141.08:04:19.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:19.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:19.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:04:19.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:04:19.98$vc4f8/valo=7,832.99 2006.141.08:04:19.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:04:19.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:04:19.98#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:19.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:19.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:19.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:20.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:04:20.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:20.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:20.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:04:20.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:04:20.04$vc4f8/va=7,6 2006.141.08:04:20.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:04:20.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:04:20.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:20.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:20.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:20.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:20.12#ibcon#[25=AT07-06\r\n] 2006.141.08:04:20.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:20.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:20.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:04:20.15#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:20.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:04:20.18#abcon#<5=/05 4.7 8.3 21.43 711012.7\r\n> 2006.141.08:04:20.20#abcon#{5=INTERFACE CLEAR} 2006.141.08:04:20.26#abcon#[5=S1D000X0/0*\r\n] 2006.141.08:04:20.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:04:20.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:04:20.29#ibcon#[25=USB\r\n] 2006.141.08:04:20.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:04:20.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:04:20.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:04:20.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:04:20.32$vc4f8/valo=8,852.99 2006.141.08:04:20.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:04:20.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:04:20.32#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:20.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:04:20.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:04:20.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:04:20.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:04:20.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:04:20.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:04:20.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:04:20.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:04:20.38$vc4f8/va=8,6 2006.141.08:04:20.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.08:04:20.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.08:04:20.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:20.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:04:20.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:04:20.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:04:20.46#ibcon#[25=AT08-06\r\n] 2006.141.08:04:20.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:04:20.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:04:20.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.08:04:20.49#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:20.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:04:20.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:04:20.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:04:20.63#ibcon#[25=USB\r\n] 2006.141.08:04:20.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:04:20.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:04:20.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:04:20.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:04:20.66$vc4f8/vblo=1,632.99 2006.141.08:04:20.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:04:20.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:04:20.66#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:20.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:20.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:20.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:20.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:04:20.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:20.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:04:20.72#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:04:20.72#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:04:20.72$vc4f8/vb=1,4 2006.141.08:04:20.72#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.08:04:20.72#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.08:04:20.72#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:20.72#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:20.72#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:20.72#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:20.74#ibcon#[27=AT01-04\r\n] 2006.141.08:04:20.77#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:20.77#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:04:20.77#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.08:04:20.77#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:20.77#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:20.89#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:20.89#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:20.91#ibcon#[27=USB\r\n] 2006.141.08:04:20.95#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:20.95#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:04:20.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:04:20.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:04:20.95$vc4f8/vblo=2,640.99 2006.141.08:04:20.95#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.08:04:20.95#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.08:04:20.95#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:20.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:20.95#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:20.95#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:20.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:04:21.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:21.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:04:21.01#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:04:21.01#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:04:21.01$vc4f8/vb=2,4 2006.141.08:04:21.01#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.08:04:21.01#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.08:04:21.01#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:21.01#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:21.07#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:21.07#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:21.09#ibcon#[27=AT02-04\r\n] 2006.141.08:04:21.12#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:21.12#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:04:21.12#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.08:04:21.12#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:21.12#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:21.24#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:21.24#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:21.26#ibcon#[27=USB\r\n] 2006.141.08:04:21.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:21.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:04:21.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:04:21.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:04:21.29$vc4f8/vblo=3,656.99 2006.141.08:04:21.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:04:21.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:04:21.29#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:21.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:21.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:21.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:21.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:04:21.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:21.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:04:21.35#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:04:21.35#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:04:21.35$vc4f8/vb=3,4 2006.141.08:04:21.35#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:04:21.35#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:04:21.35#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:21.35#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:21.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:21.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:21.43#ibcon#[27=AT03-04\r\n] 2006.141.08:04:21.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:21.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:04:21.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:04:21.46#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:21.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:21.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:21.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:21.60#ibcon#[27=USB\r\n] 2006.141.08:04:21.63#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:21.63#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:04:21.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:04:21.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:04:21.63$vc4f8/vblo=4,712.99 2006.141.08:04:21.63#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:04:21.63#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:04:21.63#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:21.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:21.63#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:21.63#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:21.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:04:21.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:21.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:04:21.69#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:04:21.69#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:04:21.69$vc4f8/vb=4,4 2006.141.08:04:21.69#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:04:21.69#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:04:21.69#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:21.69#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:21.75#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:21.75#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:21.77#ibcon#[27=AT04-04\r\n] 2006.141.08:04:21.80#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:21.80#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:04:21.80#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:04:21.80#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:21.80#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:21.92#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:21.92#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:21.94#ibcon#[27=USB\r\n] 2006.141.08:04:21.97#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:21.97#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:04:21.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:04:21.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:04:21.97$vc4f8/vblo=5,744.99 2006.141.08:04:21.97#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:04:21.97#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:04:21.97#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:21.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:21.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:21.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:21.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:04:22.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:22.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:04:22.03#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:04:22.03#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:04:22.03$vc4f8/vb=5,4 2006.141.08:04:22.03#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:04:22.03#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:04:22.03#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:22.03#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:22.09#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:22.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:22.11#ibcon#[27=AT05-04\r\n] 2006.141.08:04:22.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:22.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:04:22.14#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:04:22.14#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:22.14#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:22.26#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:22.26#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:22.28#ibcon#[27=USB\r\n] 2006.141.08:04:22.31#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:22.31#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:04:22.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:04:22.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:04:22.31$vc4f8/vblo=6,752.99 2006.141.08:04:22.31#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:04:22.31#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:04:22.31#ibcon#ireg 17 cls_cnt 0 2006.141.08:04:22.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:22.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:22.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:22.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:04:22.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:22.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:04:22.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:04:22.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:04:22.37$vc4f8/vb=6,4 2006.141.08:04:22.37#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:04:22.37#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:04:22.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:04:22.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:22.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:22.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:22.45#ibcon#[27=AT06-04\r\n] 2006.141.08:04:22.48#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:22.48#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:04:22.48#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:04:22.48#ibcon#ireg 7 cls_cnt 0 2006.141.08:04:22.48#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:22.60#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:22.60#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:22.62#ibcon#[27=USB\r\n] 2006.141.08:04:22.65#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:22.65#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:04:22.65#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:04:22.65#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:04:22.65$vc4f8/vabw=wide 2006.141.08:04:22.65#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:04:22.65#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:04:22.65#ibcon#ireg 8 cls_cnt 0 2006.141.08:04:22.65#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:22.65#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:22.65#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:22.67#ibcon#[25=BW32\r\n] 2006.141.08:04:22.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:22.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:04:22.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:04:22.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:04:22.70$vc4f8/vbbw=wide 2006.141.08:04:22.70#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.08:04:22.70#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.08:04:22.70#ibcon#ireg 8 cls_cnt 0 2006.141.08:04:22.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:04:22.77#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:04:22.77#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:04:22.79#ibcon#[27=BW32\r\n] 2006.141.08:04:22.82#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:04:22.82#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:04:22.82#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:04:22.82#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:04:22.82$4f8m12a/ifd4f 2006.141.08:04:22.82$ifd4f/lo= 2006.141.08:04:22.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:04:22.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:04:22.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:04:22.82$ifd4f/patch= 2006.141.08:04:22.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:04:22.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:04:22.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:04:22.82$4f8m12a/"form=m,16.000,1:2 2006.141.08:04:22.82$4f8m12a/"tpicd 2006.141.08:04:22.82$4f8m12a/echo=off 2006.141.08:04:22.82$4f8m12a/xlog=off 2006.141.08:04:22.82:!2006.141.08:04:50 2006.141.08:04:29.13#trakl#Source acquired 2006.141.08:04:29.13#flagr#flagr/antenna,acquired 2006.141.08:04:50.00:preob 2006.141.08:04:51.14/onsource/TRACKING 2006.141.08:04:51.14:!2006.141.08:05:00 2006.141.08:05:00.00:data_valid=on 2006.141.08:05:00.00:midob 2006.141.08:05:00.14/onsource/TRACKING 2006.141.08:05:00.14/wx/21.43,1012.8,72 2006.141.08:05:00.32/cable/+6.5246E-03 2006.141.08:05:01.41/va/01,08,usb,yes,29,30 2006.141.08:05:01.41/va/02,07,usb,yes,29,30 2006.141.08:05:01.41/va/03,06,usb,yes,30,31 2006.141.08:05:01.41/va/04,07,usb,yes,29,32 2006.141.08:05:01.41/va/05,07,usb,yes,28,30 2006.141.08:05:01.41/va/06,06,usb,yes,27,27 2006.141.08:05:01.41/va/07,06,usb,yes,28,28 2006.141.08:05:01.41/va/08,06,usb,yes,30,29 2006.141.08:05:01.64/valo/01,532.99,yes,locked 2006.141.08:05:01.64/valo/02,572.99,yes,locked 2006.141.08:05:01.64/valo/03,672.99,yes,locked 2006.141.08:05:01.64/valo/04,832.99,yes,locked 2006.141.08:05:01.64/valo/05,652.99,yes,locked 2006.141.08:05:01.64/valo/06,772.99,yes,locked 2006.141.08:05:01.64/valo/07,832.99,yes,locked 2006.141.08:05:01.64/valo/08,852.99,yes,locked 2006.141.08:05:02.73/vb/01,04,usb,yes,29,28 2006.141.08:05:02.73/vb/02,04,usb,yes,31,32 2006.141.08:05:02.73/vb/03,04,usb,yes,27,31 2006.141.08:05:02.73/vb/04,04,usb,yes,28,28 2006.141.08:05:02.73/vb/05,04,usb,yes,27,30 2006.141.08:05:02.73/vb/06,04,usb,yes,28,30 2006.141.08:05:02.73/vb/07,04,usb,yes,29,29 2006.141.08:05:02.73/vb/08,04,usb,yes,27,30 2006.141.08:05:02.96/vblo/01,632.99,yes,locked 2006.141.08:05:02.96/vblo/02,640.99,yes,locked 2006.141.08:05:02.96/vblo/03,656.99,yes,locked 2006.141.08:05:02.96/vblo/04,712.99,yes,locked 2006.141.08:05:02.96/vblo/05,744.99,yes,locked 2006.141.08:05:02.96/vblo/06,752.99,yes,locked 2006.141.08:05:02.96/vblo/07,734.99,yes,locked 2006.141.08:05:02.96/vblo/08,744.99,yes,locked 2006.141.08:05:03.11/vabw/8 2006.141.08:05:03.26/vbbw/8 2006.141.08:05:03.35/xfe/off,on,15.0 2006.141.08:05:03.75/ifatt/23,28,28,28 2006.141.08:05:04.11/fmout-gps/S +1.06E-07 2006.141.08:05:04.15:!2006.141.08:06:00 2006.141.08:06:00.00:data_valid=off 2006.141.08:06:00.00:postob 2006.141.08:06:00.08/cable/+6.5207E-03 2006.141.08:06:00.08/wx/21.42,1012.8,73 2006.141.08:06:01.11/fmout-gps/S +1.06E-07 2006.141.08:06:01.11:scan_name=141-0806,k06141,60 2006.141.08:06:01.11:source=1300+580,130252.47,574837.6,2000.0,cw 2006.141.08:06:01.14#flagr#flagr/antenna,new-source 2006.141.08:06:02.14:checkk5 2006.141.08:06:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:06:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:06:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:06:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:06:04.04/chk_obsdata//k5ts1/T1410805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:06:04.41/chk_obsdata//k5ts2/T1410805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:06:04.79/chk_obsdata//k5ts3/T1410805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:06:05.17/chk_obsdata//k5ts4/T1410805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:06:05.86/k5log//k5ts1_log_newline 2006.141.08:06:06.55/k5log//k5ts2_log_newline 2006.141.08:06:07.24/k5log//k5ts3_log_newline 2006.141.08:06:07.93/k5log//k5ts4_log_newline 2006.141.08:06:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:06:07.95:4f8m12a=2 2006.141.08:06:07.95$4f8m12a/echo=on 2006.141.08:06:07.95$4f8m12a/pcalon 2006.141.08:06:07.95$pcalon/"no phase cal control is implemented here 2006.141.08:06:07.95$4f8m12a/"tpicd=stop 2006.141.08:06:07.95$4f8m12a/vc4f8 2006.141.08:06:07.95$vc4f8/valo=1,532.99 2006.141.08:06:07.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.08:06:07.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.08:06:07.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:07.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:07.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:07.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:06:08.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:08.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:08.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:06:08.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:06:08.05$vc4f8/va=1,8 2006.141.08:06:08.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.08:06:08.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.08:06:08.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:08.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:08.05#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:08.05#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:08.08#ibcon#[25=AT01-08\r\n] 2006.141.08:06:08.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:08.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:08.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.08:06:08.12#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:08.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:08.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:08.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:08.26#ibcon#[25=USB\r\n] 2006.141.08:06:08.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:08.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:08.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:06:08.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:06:08.29$vc4f8/valo=2,572.99 2006.141.08:06:08.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.08:06:08.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.08:06:08.29#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:08.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:08.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:08.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:08.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:06:08.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:08.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:08.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:06:08.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:06:08.37$vc4f8/va=2,7 2006.141.08:06:08.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.08:06:08.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.08:06:08.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:08.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:08.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:08.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:08.43#ibcon#[25=AT02-07\r\n] 2006.141.08:06:08.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:08.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:08.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.08:06:08.46#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:08.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:08.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:08.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:08.60#ibcon#[25=USB\r\n] 2006.141.08:06:08.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:08.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:08.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:06:08.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:06:08.63$vc4f8/valo=3,672.99 2006.141.08:06:08.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.08:06:08.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.08:06:08.63#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:08.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:08.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:08.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:08.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:06:08.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:08.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:08.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:06:08.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:06:08.71$vc4f8/va=3,6 2006.141.08:06:08.71#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.08:06:08.71#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.08:06:08.71#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:08.71#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:08.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:08.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:08.77#ibcon#[25=AT03-06\r\n] 2006.141.08:06:08.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:08.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:08.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.08:06:08.80#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:08.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:08.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:08.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:08.94#ibcon#[25=USB\r\n] 2006.141.08:06:08.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:08.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:08.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:06:08.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:06:08.97$vc4f8/valo=4,832.99 2006.141.08:06:08.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.08:06:08.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.08:06:08.97#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:08.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:08.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:08.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:08.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:06:09.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:09.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:09.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:06:09.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:06:09.03$vc4f8/va=4,7 2006.141.08:06:09.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.08:06:09.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.08:06:09.03#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:09.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:09.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:09.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:09.11#ibcon#[25=AT04-07\r\n] 2006.141.08:06:09.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:09.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:09.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.08:06:09.14#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:09.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:09.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:09.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:09.28#ibcon#[25=USB\r\n] 2006.141.08:06:09.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:09.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:09.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:06:09.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:06:09.31$vc4f8/valo=5,652.99 2006.141.08:06:09.31#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.08:06:09.31#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.08:06:09.31#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:09.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:06:09.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:06:09.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:06:09.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:06:09.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:06:09.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:06:09.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:06:09.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:06:09.37$vc4f8/va=5,7 2006.141.08:06:09.37#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.08:06:09.37#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.08:06:09.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:09.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:06:09.43#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:06:09.43#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:06:09.45#ibcon#[25=AT05-07\r\n] 2006.141.08:06:09.48#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:06:09.48#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:06:09.48#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.08:06:09.48#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:09.48#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:06:09.60#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:06:09.60#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:06:09.62#ibcon#[25=USB\r\n] 2006.141.08:06:09.65#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:06:09.65#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:06:09.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:06:09.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:06:09.65$vc4f8/valo=6,772.99 2006.141.08:06:09.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.08:06:09.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.08:06:09.65#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:09.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:06:09.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:06:09.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:06:09.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:06:09.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:06:09.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:06:09.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:06:09.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:06:09.71$vc4f8/va=6,6 2006.141.08:06:09.71#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.08:06:09.71#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.08:06:09.71#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:09.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:09.77#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:09.77#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:09.79#ibcon#[25=AT06-06\r\n] 2006.141.08:06:09.82#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:09.82#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:09.82#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.08:06:09.82#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:09.82#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:09.94#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:09.94#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:09.96#ibcon#[25=USB\r\n] 2006.141.08:06:09.99#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:09.99#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:09.99#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:06:09.99#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:06:09.99$vc4f8/valo=7,832.99 2006.141.08:06:09.99#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.08:06:09.99#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.08:06:09.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:09.99#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:09.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:09.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:10.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:06:10.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:10.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:10.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:06:10.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:06:10.05$vc4f8/va=7,6 2006.141.08:06:10.05#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.08:06:10.05#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.08:06:10.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:10.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:10.11#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:10.11#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:10.13#ibcon#[25=AT07-06\r\n] 2006.141.08:06:10.16#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:10.16#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:10.16#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.08:06:10.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:10.16#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:06:10.28#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:06:10.28#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:06:10.30#ibcon#[25=USB\r\n] 2006.141.08:06:10.33#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:06:10.33#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:06:10.33#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:06:10.33#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:06:10.33$vc4f8/valo=8,852.99 2006.141.08:06:10.33#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.08:06:10.33#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.08:06:10.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:10.33#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:06:10.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:06:10.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:06:10.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:06:10.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:06:10.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:06:10.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:06:10.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:06:10.39$vc4f8/va=8,6 2006.141.08:06:10.39#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.08:06:10.39#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.08:06:10.39#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:10.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:06:10.45#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:06:10.45#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:06:10.47#ibcon#[25=AT08-06\r\n] 2006.141.08:06:10.50#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:06:10.50#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:06:10.50#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.08:06:10.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:10.50#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:06:10.62#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:06:10.62#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:06:10.64#ibcon#[25=USB\r\n] 2006.141.08:06:10.67#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:06:10.67#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:06:10.67#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:06:10.67#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:06:10.67$vc4f8/vblo=1,632.99 2006.141.08:06:10.67#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.08:06:10.67#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.08:06:10.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:10.67#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:06:10.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:06:10.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:06:10.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:06:10.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:06:10.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:06:10.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:06:10.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:06:10.73$vc4f8/vb=1,4 2006.141.08:06:10.73#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.08:06:10.73#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.08:06:10.73#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:10.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:06:10.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:06:10.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:06:10.75#ibcon#[27=AT01-04\r\n] 2006.141.08:06:10.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:06:10.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:06:10.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.08:06:10.78#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:10.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:06:10.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:06:10.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:06:10.92#ibcon#[27=USB\r\n] 2006.141.08:06:10.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:06:10.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:06:10.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:06:10.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:06:10.95$vc4f8/vblo=2,640.99 2006.141.08:06:10.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.08:06:10.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.08:06:10.95#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:10.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:10.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:10.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:10.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:06:11.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:11.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:06:11.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:06:11.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:06:11.01$vc4f8/vb=2,4 2006.141.08:06:11.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.08:06:11.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.08:06:11.01#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:11.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:11.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:11.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:11.09#ibcon#[27=AT02-04\r\n] 2006.141.08:06:11.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:11.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:06:11.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.08:06:11.12#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:11.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:11.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:11.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:11.26#ibcon#[27=USB\r\n] 2006.141.08:06:11.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:11.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:06:11.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:06:11.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:06:11.29$vc4f8/vblo=3,656.99 2006.141.08:06:11.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.08:06:11.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.08:06:11.29#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:11.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:11.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:11.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:11.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:06:11.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:11.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:06:11.37#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:06:11.37#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:06:11.37$vc4f8/vb=3,4 2006.141.08:06:11.37#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.08:06:11.37#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.08:06:11.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:11.37#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:11.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:11.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:11.43#ibcon#[27=AT03-04\r\n] 2006.141.08:06:11.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:11.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:06:11.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.08:06:11.46#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:11.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:11.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:11.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:11.60#ibcon#[27=USB\r\n] 2006.141.08:06:11.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:11.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:06:11.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:06:11.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:06:11.63$vc4f8/vblo=4,712.99 2006.141.08:06:11.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.08:06:11.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.08:06:11.63#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:11.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:11.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:11.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:11.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:06:11.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:11.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:06:11.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:06:11.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:06:11.69$vc4f8/vb=4,4 2006.141.08:06:11.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.08:06:11.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.08:06:11.69#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:11.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:11.75#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:11.75#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:11.77#ibcon#[27=AT04-04\r\n] 2006.141.08:06:11.80#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:11.80#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:06:11.80#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.08:06:11.80#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:11.80#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:11.92#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:11.92#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:11.94#ibcon#[27=USB\r\n] 2006.141.08:06:11.97#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:11.97#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:06:11.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:06:11.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:06:11.97$vc4f8/vblo=5,744.99 2006.141.08:06:11.97#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.08:06:11.97#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.08:06:11.97#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:11.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:11.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:11.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:11.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:06:12.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:12.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:06:12.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:06:12.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:06:12.03$vc4f8/vb=5,4 2006.141.08:06:12.03#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.08:06:12.03#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.08:06:12.03#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:12.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:12.09#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:12.09#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:12.11#ibcon#[27=AT05-04\r\n] 2006.141.08:06:12.14#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:12.14#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:06:12.14#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.08:06:12.14#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:12.14#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:12.25#abcon#<5=/05 4.4 7.3 21.42 721012.7\r\n> 2006.141.08:06:12.26#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:12.26#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:12.27#abcon#{5=INTERFACE CLEAR} 2006.141.08:06:12.28#ibcon#[27=USB\r\n] 2006.141.08:06:12.31#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:12.31#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:06:12.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:06:12.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:06:12.31$vc4f8/vblo=6,752.99 2006.141.08:06:12.31#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:06:12.31#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:06:12.31#ibcon#ireg 17 cls_cnt 0 2006.141.08:06:12.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:06:12.31#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:06:12.31#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:06:12.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:06:12.33#abcon#[5=S1D000X0/0*\r\n] 2006.141.08:06:12.37#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:06:12.37#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:06:12.37#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:06:12.37#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:06:12.37$vc4f8/vb=6,4 2006.141.08:06:12.37#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.08:06:12.37#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.08:06:12.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:06:12.37#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:12.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:12.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:12.45#ibcon#[27=AT06-04\r\n] 2006.141.08:06:12.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:12.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:06:12.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.08:06:12.48#ibcon#ireg 7 cls_cnt 0 2006.141.08:06:12.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:12.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:12.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:12.62#ibcon#[27=USB\r\n] 2006.141.08:06:12.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:12.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:06:12.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:06:12.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:06:12.65$vc4f8/vabw=wide 2006.141.08:06:12.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.08:06:12.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.08:06:12.65#ibcon#ireg 8 cls_cnt 0 2006.141.08:06:12.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:12.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:12.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:12.67#ibcon#[25=BW32\r\n] 2006.141.08:06:12.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:12.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:06:12.70#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:06:12.70#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:06:12.70$vc4f8/vbbw=wide 2006.141.08:06:12.70#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:06:12.70#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:06:12.70#ibcon#ireg 8 cls_cnt 0 2006.141.08:06:12.70#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:06:12.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:06:12.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:06:12.79#ibcon#[27=BW32\r\n] 2006.141.08:06:12.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:06:12.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:06:12.82#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:06:12.82#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:06:12.82$4f8m12a/ifd4f 2006.141.08:06:12.82$ifd4f/lo= 2006.141.08:06:12.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:06:12.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:06:12.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:06:12.82$ifd4f/patch= 2006.141.08:06:12.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:06:12.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:06:12.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:06:12.82$4f8m12a/"form=m,16.000,1:2 2006.141.08:06:12.82$4f8m12a/"tpicd 2006.141.08:06:12.82$4f8m12a/echo=off 2006.141.08:06:12.82$4f8m12a/xlog=off 2006.141.08:06:12.82:!2006.141.08:06:40 2006.141.08:06:26.14#trakl#Source acquired 2006.141.08:06:28.14#flagr#flagr/antenna,acquired 2006.141.08:06:40.00:preob 2006.141.08:06:41.14/onsource/TRACKING 2006.141.08:06:41.14:!2006.141.08:06:50 2006.141.08:06:50.00:data_valid=on 2006.141.08:06:50.00:midob 2006.141.08:06:50.14/onsource/TRACKING 2006.141.08:06:50.14/wx/21.42,1012.7,71 2006.141.08:06:50.27/cable/+6.5208E-03 2006.141.08:06:51.36/va/01,08,usb,yes,28,30 2006.141.08:06:51.36/va/02,07,usb,yes,28,30 2006.141.08:06:51.36/va/03,06,usb,yes,30,30 2006.141.08:06:51.36/va/04,07,usb,yes,29,31 2006.141.08:06:51.36/va/05,07,usb,yes,28,30 2006.141.08:06:51.36/va/06,06,usb,yes,27,27 2006.141.08:06:51.36/va/07,06,usb,yes,27,27 2006.141.08:06:51.36/va/08,06,usb,yes,29,29 2006.141.08:06:51.59/valo/01,532.99,yes,locked 2006.141.08:06:51.59/valo/02,572.99,yes,locked 2006.141.08:06:51.59/valo/03,672.99,yes,locked 2006.141.08:06:51.59/valo/04,832.99,yes,locked 2006.141.08:06:51.59/valo/05,652.99,yes,locked 2006.141.08:06:51.59/valo/06,772.99,yes,locked 2006.141.08:06:51.59/valo/07,832.99,yes,locked 2006.141.08:06:51.59/valo/08,852.99,yes,locked 2006.141.08:06:52.68/vb/01,04,usb,yes,28,27 2006.141.08:06:52.68/vb/02,04,usb,yes,30,31 2006.141.08:06:52.68/vb/03,04,usb,yes,26,30 2006.141.08:06:52.68/vb/04,04,usb,yes,27,27 2006.141.08:06:52.68/vb/05,04,usb,yes,26,30 2006.141.08:06:52.68/vb/06,04,usb,yes,27,29 2006.141.08:06:52.68/vb/07,04,usb,yes,28,28 2006.141.08:06:52.68/vb/08,04,usb,yes,26,29 2006.141.08:06:52.91/vblo/01,632.99,yes,locked 2006.141.08:06:52.91/vblo/02,640.99,yes,locked 2006.141.08:06:52.91/vblo/03,656.99,yes,locked 2006.141.08:06:52.91/vblo/04,712.99,yes,locked 2006.141.08:06:52.91/vblo/05,744.99,yes,locked 2006.141.08:06:52.91/vblo/06,752.99,yes,locked 2006.141.08:06:52.91/vblo/07,734.99,yes,locked 2006.141.08:06:52.91/vblo/08,744.99,yes,locked 2006.141.08:06:53.06/vabw/8 2006.141.08:06:53.21/vbbw/8 2006.141.08:06:53.33/xfe/off,on,14.2 2006.141.08:06:53.71/ifatt/23,28,28,28 2006.141.08:06:54.11/fmout-gps/S +1.06E-07 2006.141.08:06:54.19:!2006.141.08:07:50 2006.141.08:07:50.00:data_valid=off 2006.141.08:07:50.00:postob 2006.141.08:07:50.17/cable/+6.5221E-03 2006.141.08:07:50.17/wx/21.42,1012.8,72 2006.141.08:07:51.11/fmout-gps/S +1.07E-07 2006.141.08:07:51.11:scan_name=141-0809,k06141,70 2006.141.08:07:51.11:source=0536+145,053942.37,143345.6,2000.0,ccw 2006.141.08:07:51.14#flagr#flagr/antenna,new-source 2006.141.08:07:52.14:checkk5 2006.141.08:07:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:07:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:07:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:07:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:07:54.02/chk_obsdata//k5ts1/T1410806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:07:54.39/chk_obsdata//k5ts2/T1410806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:07:54.77/chk_obsdata//k5ts3/T1410806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:07:55.15/chk_obsdata//k5ts4/T1410806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:07:55.84/k5log//k5ts1_log_newline 2006.141.08:07:56.53/k5log//k5ts2_log_newline 2006.141.08:07:57.22/k5log//k5ts3_log_newline 2006.141.08:07:57.92/k5log//k5ts4_log_newline 2006.141.08:07:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:07:57.94:4f8m12a=2 2006.141.08:07:57.94$4f8m12a/echo=on 2006.141.08:07:57.94$4f8m12a/pcalon 2006.141.08:07:57.94$pcalon/"no phase cal control is implemented here 2006.141.08:07:57.94$4f8m12a/"tpicd=stop 2006.141.08:07:57.94$4f8m12a/vc4f8 2006.141.08:07:57.94$vc4f8/valo=1,532.99 2006.141.08:07:57.95#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:07:57.95#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:07:57.95#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:57.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:07:57.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:07:57.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:07:58.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:07:58.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:07:58.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:07:58.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:07:58.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:07:58.05$vc4f8/va=1,8 2006.141.08:07:58.05#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.08:07:58.05#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.08:07:58.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:58.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:07:58.05#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:07:58.05#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:07:58.08#ibcon#[25=AT01-08\r\n] 2006.141.08:07:58.12#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:07:58.12#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:07:58.12#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.08:07:58.12#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:58.12#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:07:58.24#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:07:58.24#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:07:58.26#ibcon#[25=USB\r\n] 2006.141.08:07:58.29#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:07:58.29#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:07:58.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:07:58.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:07:58.29$vc4f8/valo=2,572.99 2006.141.08:07:58.29#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.08:07:58.29#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.08:07:58.29#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:58.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:07:58.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:07:58.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:07:58.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:07:58.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:07:58.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:07:58.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:07:58.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:07:58.37$vc4f8/va=2,7 2006.141.08:07:58.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.08:07:58.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.08:07:58.37#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:58.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:07:58.41#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:07:58.41#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:07:58.43#ibcon#[25=AT02-07\r\n] 2006.141.08:07:58.46#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:07:58.46#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:07:58.46#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.08:07:58.46#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:58.46#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:07:58.58#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:07:58.58#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:07:58.60#ibcon#[25=USB\r\n] 2006.141.08:07:58.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:07:58.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:07:58.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:07:58.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:07:58.65$vc4f8/valo=3,672.99 2006.141.08:07:58.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:07:58.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:07:58.65#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:58.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:07:58.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:07:58.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:07:58.67#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:07:58.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:07:58.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:07:58.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:07:58.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:07:58.71$vc4f8/va=3,6 2006.141.08:07:58.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.08:07:58.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.08:07:58.71#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:58.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:07:58.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:07:58.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:07:58.79#ibcon#[25=AT03-06\r\n] 2006.141.08:07:58.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:07:58.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:07:58.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.08:07:58.82#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:58.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:07:58.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:07:58.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:07:58.96#ibcon#[25=USB\r\n] 2006.141.08:07:58.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:07:58.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:07:58.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:07:58.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:07:58.99$vc4f8/valo=4,832.99 2006.141.08:07:58.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.08:07:58.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.08:07:58.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:58.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:07:58.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:07:58.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:07:59.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:07:59.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:07:59.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:07:59.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:07:59.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:07:59.05$vc4f8/va=4,7 2006.141.08:07:59.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.08:07:59.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.08:07:59.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:59.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:07:59.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:07:59.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:07:59.13#ibcon#[25=AT04-07\r\n] 2006.141.08:07:59.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:07:59.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:07:59.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.08:07:59.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:59.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:07:59.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:07:59.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:07:59.30#ibcon#[25=USB\r\n] 2006.141.08:07:59.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:07:59.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:07:59.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:07:59.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:07:59.33$vc4f8/valo=5,652.99 2006.141.08:07:59.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:07:59.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:07:59.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:59.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:07:59.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:07:59.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:07:59.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:07:59.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:07:59.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:07:59.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:07:59.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:07:59.39$vc4f8/va=5,7 2006.141.08:07:59.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:07:59.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:07:59.39#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:59.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:07:59.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:07:59.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:07:59.47#ibcon#[25=AT05-07\r\n] 2006.141.08:07:59.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:07:59.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:07:59.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:07:59.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:59.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:07:59.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:07:59.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:07:59.64#ibcon#[25=USB\r\n] 2006.141.08:07:59.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:07:59.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:07:59.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:07:59.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:07:59.67$vc4f8/valo=6,772.99 2006.141.08:07:59.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:07:59.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:07:59.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:07:59.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:07:59.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:07:59.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:07:59.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:07:59.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:07:59.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:07:59.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:07:59.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:07:59.73$vc4f8/va=6,6 2006.141.08:07:59.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.08:07:59.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.08:07:59.73#ibcon#ireg 11 cls_cnt 2 2006.141.08:07:59.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:07:59.79#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:07:59.79#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:07:59.81#ibcon#[25=AT06-06\r\n] 2006.141.08:07:59.84#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:07:59.84#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:07:59.84#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.08:07:59.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:07:59.84#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:07:59.96#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:07:59.96#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:07:59.98#ibcon#[25=USB\r\n] 2006.141.08:08:00.01#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:08:00.01#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:08:00.01#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:08:00.01#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:08:00.01$vc4f8/valo=7,832.99 2006.141.08:08:00.01#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.08:08:00.01#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.08:08:00.01#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:00.01#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:08:00.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:08:00.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:08:00.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:08:00.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:08:00.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:08:00.07#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:08:00.07#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:08:00.07$vc4f8/va=7,6 2006.141.08:08:00.07#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.08:08:00.07#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.08:08:00.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:00.07#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:08:00.13#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:08:00.13#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:08:00.15#ibcon#[25=AT07-06\r\n] 2006.141.08:08:00.18#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:08:00.18#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:08:00.18#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.08:08:00.18#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:00.18#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:08:00.30#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:08:00.30#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:08:00.32#ibcon#[25=USB\r\n] 2006.141.08:08:00.37#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:08:00.37#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:08:00.37#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:08:00.37#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:08:00.37$vc4f8/valo=8,852.99 2006.141.08:08:00.37#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.08:08:00.37#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.08:08:00.37#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:00.37#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:08:00.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:08:00.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:08:00.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:08:00.43#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:08:00.43#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:08:00.43#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:08:00.43#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:08:00.43$vc4f8/va=8,6 2006.141.08:08:00.43#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.08:08:00.43#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.08:08:00.43#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:00.43#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:08:00.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:08:00.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:08:00.51#ibcon#[25=AT08-06\r\n] 2006.141.08:08:00.54#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:08:00.54#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:08:00.54#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.08:08:00.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:00.54#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:08:00.66#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:08:00.66#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:08:00.68#ibcon#[25=USB\r\n] 2006.141.08:08:00.71#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:08:00.71#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:08:00.71#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:08:00.71#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:08:00.71$vc4f8/vblo=1,632.99 2006.141.08:08:00.71#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.08:08:00.71#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.08:08:00.71#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:00.71#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:08:00.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:08:00.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:08:00.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:08:00.77#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:08:00.77#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:08:00.77#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:08:00.77#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:08:00.77$vc4f8/vb=1,4 2006.141.08:08:00.77#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.08:08:00.77#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.08:08:00.77#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:00.77#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:08:00.77#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:08:00.77#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:08:00.79#ibcon#[27=AT01-04\r\n] 2006.141.08:08:00.82#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:08:00.82#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:08:00.82#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.08:08:00.82#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:00.82#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:08:00.94#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:08:00.94#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:08:00.96#ibcon#[27=USB\r\n] 2006.141.08:08:00.99#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:08:00.99#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:08:00.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:08:00.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:08:00.99$vc4f8/vblo=2,640.99 2006.141.08:08:00.99#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:08:00.99#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:08:00.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:00.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:08:00.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:08:00.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:08:01.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:08:01.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:08:01.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:08:01.05#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:08:01.05#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:08:01.05$vc4f8/vb=2,4 2006.141.08:08:01.05#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.08:08:01.05#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.08:08:01.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:01.05#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:08:01.11#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:08:01.11#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:08:01.13#ibcon#[27=AT02-04\r\n] 2006.141.08:08:01.16#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:08:01.16#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:08:01.16#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.08:08:01.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:01.16#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:08:01.28#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:08:01.28#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:08:01.30#ibcon#[27=USB\r\n] 2006.141.08:08:01.33#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:08:01.33#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:08:01.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:08:01.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:08:01.33$vc4f8/vblo=3,656.99 2006.141.08:08:01.33#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.08:08:01.33#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.08:08:01.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:01.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:08:01.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:08:01.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:08:01.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:08:01.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:08:01.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:08:01.39#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:08:01.39#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:08:01.39$vc4f8/vb=3,4 2006.141.08:08:01.39#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.08:08:01.39#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.08:08:01.39#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:01.39#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:08:01.45#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:08:01.45#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:08:01.47#ibcon#[27=AT03-04\r\n] 2006.141.08:08:01.50#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:08:01.50#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:08:01.50#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.08:08:01.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:01.50#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:08:01.62#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:08:01.62#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:08:01.64#ibcon#[27=USB\r\n] 2006.141.08:08:01.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:08:01.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:08:01.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:08:01.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:08:01.67$vc4f8/vblo=4,712.99 2006.141.08:08:01.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:08:01.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:08:01.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:01.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:08:01.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:08:01.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:08:01.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:08:01.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:08:01.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:08:01.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:08:01.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:08:01.74$vc4f8/vb=4,4 2006.141.08:08:01.74#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.08:08:01.74#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.08:08:01.74#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:01.74#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:08:01.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:08:01.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:08:01.81#ibcon#[27=AT04-04\r\n] 2006.141.08:08:01.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:08:01.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:08:01.84#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.08:08:01.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:01.84#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:08:01.96#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:08:01.96#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:08:01.98#ibcon#[27=USB\r\n] 2006.141.08:08:02.03#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:08:02.03#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:08:02.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:08:02.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:08:02.03$vc4f8/vblo=5,744.99 2006.141.08:08:02.03#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.08:08:02.03#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.08:08:02.03#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:02.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:08:02.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:08:02.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:08:02.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:08:02.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:08:02.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:08:02.09#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:08:02.09#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:08:02.09$vc4f8/vb=5,4 2006.141.08:08:02.09#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.08:08:02.09#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.08:08:02.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:02.09#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:08:02.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:08:02.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:08:02.17#ibcon#[27=AT05-04\r\n] 2006.141.08:08:02.22#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:08:02.22#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:08:02.22#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.08:08:02.22#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:02.22#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:08:02.34#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:08:02.34#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:08:02.36#ibcon#[27=USB\r\n] 2006.141.08:08:02.39#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:08:02.39#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:08:02.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:08:02.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:08:02.39$vc4f8/vblo=6,752.99 2006.141.08:08:02.39#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:08:02.39#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:08:02.39#ibcon#ireg 17 cls_cnt 0 2006.141.08:08:02.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:08:02.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:08:02.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:08:02.41#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:08:02.45#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:08:02.45#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:08:02.45#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:08:02.45#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:08:02.45$vc4f8/vb=6,4 2006.141.08:08:02.45#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:08:02.45#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:08:02.45#ibcon#ireg 11 cls_cnt 2 2006.141.08:08:02.45#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:08:02.51#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:08:02.51#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:08:02.53#ibcon#[27=AT06-04\r\n] 2006.141.08:08:02.56#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:08:02.56#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:08:02.56#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:08:02.56#ibcon#ireg 7 cls_cnt 0 2006.141.08:08:02.56#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:08:02.68#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:08:02.68#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:08:02.70#ibcon#[27=USB\r\n] 2006.141.08:08:02.73#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:08:02.73#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:08:02.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:08:02.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:08:02.73$vc4f8/vabw=wide 2006.141.08:08:02.73#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:08:02.73#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:08:02.73#ibcon#ireg 8 cls_cnt 0 2006.141.08:08:02.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:08:02.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:08:02.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:08:02.75#ibcon#[25=BW32\r\n] 2006.141.08:08:02.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:08:02.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:08:02.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:08:02.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:08:02.78$vc4f8/vbbw=wide 2006.141.08:08:02.78#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:08:02.78#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:08:02.78#ibcon#ireg 8 cls_cnt 0 2006.141.08:08:02.78#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:08:02.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:08:02.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:08:02.88#ibcon#[27=BW32\r\n] 2006.141.08:08:02.92#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:08:02.92#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:08:02.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:08:02.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:08:02.92$4f8m12a/ifd4f 2006.141.08:08:02.92$ifd4f/lo= 2006.141.08:08:02.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:08:02.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:08:02.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:08:02.92$ifd4f/patch= 2006.141.08:08:02.92$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:08:02.92$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:08:02.92$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:08:02.92$4f8m12a/"form=m,16.000,1:2 2006.141.08:08:02.92$4f8m12a/"tpicd 2006.141.08:08:02.92$4f8m12a/echo=off 2006.141.08:08:02.92$4f8m12a/xlog=off 2006.141.08:08:02.92:!2006.141.08:09:10 2006.141.08:08:44.14#trakl#Source acquired 2006.141.08:08:45.14#flagr#flagr/antenna,acquired 2006.141.08:09:10.00:preob 2006.141.08:09:10.14/onsource/TRACKING 2006.141.08:09:10.14:!2006.141.08:09:20 2006.141.08:09:20.00:data_valid=on 2006.141.08:09:20.00:midob 2006.141.08:09:21.14/onsource/TRACKING 2006.141.08:09:21.14/wx/21.42,1012.8,71 2006.141.08:09:21.28/cable/+6.5254E-03 2006.141.08:09:22.37/va/01,08,usb,yes,29,30 2006.141.08:09:22.37/va/02,07,usb,yes,29,30 2006.141.08:09:22.37/va/03,06,usb,yes,30,31 2006.141.08:09:22.37/va/04,07,usb,yes,29,32 2006.141.08:09:22.37/va/05,07,usb,yes,28,30 2006.141.08:09:22.37/va/06,06,usb,yes,27,27 2006.141.08:09:22.37/va/07,06,usb,yes,27,27 2006.141.08:09:22.37/va/08,06,usb,yes,29,29 2006.141.08:09:22.60/valo/01,532.99,yes,locked 2006.141.08:09:22.60/valo/02,572.99,yes,locked 2006.141.08:09:22.60/valo/03,672.99,yes,locked 2006.141.08:09:22.60/valo/04,832.99,yes,locked 2006.141.08:09:22.60/valo/05,652.99,yes,locked 2006.141.08:09:22.60/valo/06,772.99,yes,locked 2006.141.08:09:22.60/valo/07,832.99,yes,locked 2006.141.08:09:22.60/valo/08,852.99,yes,locked 2006.141.08:09:23.69/vb/01,04,usb,yes,29,28 2006.141.08:09:23.69/vb/02,04,usb,yes,31,33 2006.141.08:09:23.69/vb/03,04,usb,yes,27,31 2006.141.08:09:23.69/vb/04,04,usb,yes,28,28 2006.141.08:09:23.69/vb/05,04,usb,yes,27,31 2006.141.08:09:23.69/vb/06,04,usb,yes,28,30 2006.141.08:09:23.69/vb/07,04,usb,yes,30,29 2006.141.08:09:23.69/vb/08,04,usb,yes,27,30 2006.141.08:09:23.92/vblo/01,632.99,yes,locked 2006.141.08:09:23.92/vblo/02,640.99,yes,locked 2006.141.08:09:23.92/vblo/03,656.99,yes,locked 2006.141.08:09:23.92/vblo/04,712.99,yes,locked 2006.141.08:09:23.92/vblo/05,744.99,yes,locked 2006.141.08:09:23.92/vblo/06,752.99,yes,locked 2006.141.08:09:23.92/vblo/07,734.99,yes,locked 2006.141.08:09:23.92/vblo/08,744.99,yes,locked 2006.141.08:09:24.07/vabw/8 2006.141.08:09:24.22/vbbw/8 2006.141.08:09:24.31/xfe/off,on,15.0 2006.141.08:09:24.68/ifatt/23,28,28,28 2006.141.08:09:25.11/fmout-gps/S +1.06E-07 2006.141.08:09:25.15:!2006.141.08:10:30 2006.141.08:10:30.00:data_valid=off 2006.141.08:10:30.00:postob 2006.141.08:10:30.17/cable/+6.5225E-03 2006.141.08:10:30.17/wx/21.42,1012.8,70 2006.141.08:10:31.11/fmout-gps/S +1.06E-07 2006.141.08:10:31.11:scan_name=141-0811,k06141,60 2006.141.08:10:31.11:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.141.08:10:32.14#flagr#flagr/antenna,new-source 2006.141.08:10:32.14:checkk5 2006.141.08:10:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:10:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:10:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:10:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:10:34.02/chk_obsdata//k5ts1/T1410809??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.141.08:10:34.40/chk_obsdata//k5ts2/T1410809??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.141.08:10:34.77/chk_obsdata//k5ts3/T1410809??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.141.08:10:35.15/chk_obsdata//k5ts4/T1410809??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.141.08:10:35.85/k5log//k5ts1_log_newline 2006.141.08:10:36.54/k5log//k5ts2_log_newline 2006.141.08:10:37.23/k5log//k5ts3_log_newline 2006.141.08:10:37.93/k5log//k5ts4_log_newline 2006.141.08:10:37.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:10:37.95:4f8m12a=2 2006.141.08:10:37.95$4f8m12a/echo=on 2006.141.08:10:37.95$4f8m12a/pcalon 2006.141.08:10:37.95$pcalon/"no phase cal control is implemented here 2006.141.08:10:37.95$4f8m12a/"tpicd=stop 2006.141.08:10:37.95$4f8m12a/vc4f8 2006.141.08:10:37.95$vc4f8/valo=1,532.99 2006.141.08:10:37.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:10:37.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:10:37.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:37.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:37.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:37.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:38.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:10:38.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:38.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:38.06#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:10:38.06#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:10:38.06$vc4f8/va=1,8 2006.141.08:10:38.06#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:10:38.06#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:10:38.06#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:38.06#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:38.06#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:38.06#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:38.09#ibcon#[25=AT01-08\r\n] 2006.141.08:10:38.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:38.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:38.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:10:38.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:38.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:38.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:38.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:38.27#ibcon#[25=USB\r\n] 2006.141.08:10:38.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:38.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:38.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:10:38.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:10:38.30$vc4f8/valo=2,572.99 2006.141.08:10:38.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:10:38.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:10:38.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:38.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:38.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:38.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:38.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:10:38.38#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:38.38#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:38.38#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:10:38.38#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:10:38.38$vc4f8/va=2,7 2006.141.08:10:38.38#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:10:38.38#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:10:38.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:38.38#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:38.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:38.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:38.44#ibcon#[25=AT02-07\r\n] 2006.141.08:10:38.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:38.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:38.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:10:38.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:38.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:38.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:38.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:38.61#ibcon#[25=USB\r\n] 2006.141.08:10:38.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:38.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:38.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:10:38.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:10:38.64$vc4f8/valo=3,672.99 2006.141.08:10:38.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:10:38.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:10:38.64#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:38.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:38.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:38.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:38.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:10:38.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:38.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:38.72#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:10:38.72#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:10:38.72$vc4f8/va=3,6 2006.141.08:10:38.72#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:10:38.72#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:10:38.72#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:38.72#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:38.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:38.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:38.78#ibcon#[25=AT03-06\r\n] 2006.141.08:10:38.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:38.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:38.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:10:38.81#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:38.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:38.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:38.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:38.95#ibcon#[25=USB\r\n] 2006.141.08:10:38.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:38.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:38.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:10:38.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:10:38.98$vc4f8/valo=4,832.99 2006.141.08:10:38.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:10:38.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:10:38.98#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:38.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:38.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:38.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:39.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:10:39.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:39.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:39.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:10:39.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:10:39.04$vc4f8/va=4,7 2006.141.08:10:39.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:10:39.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:10:39.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:39.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:39.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:39.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:39.12#ibcon#[25=AT04-07\r\n] 2006.141.08:10:39.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:39.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:39.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:10:39.15#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:39.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:39.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:39.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:39.29#ibcon#[25=USB\r\n] 2006.141.08:10:39.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:39.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:39.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:10:39.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:10:39.32$vc4f8/valo=5,652.99 2006.141.08:10:39.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:10:39.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:10:39.32#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:39.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:39.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:39.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:39.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:10:39.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:39.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:39.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:10:39.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:10:39.38$vc4f8/va=5,7 2006.141.08:10:39.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:10:39.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:10:39.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:39.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:39.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:39.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:39.46#ibcon#[25=AT05-07\r\n] 2006.141.08:10:39.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:39.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:39.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:10:39.49#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:39.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:39.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:39.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:39.63#ibcon#[25=USB\r\n] 2006.141.08:10:39.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:39.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:39.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:10:39.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:10:39.66$vc4f8/valo=6,772.99 2006.141.08:10:39.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:10:39.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:10:39.66#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:39.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:39.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:39.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:39.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:10:39.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:39.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:39.72#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:10:39.72#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:10:39.72$vc4f8/va=6,6 2006.141.08:10:39.72#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.08:10:39.72#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.08:10:39.72#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:39.72#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:39.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:39.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:39.80#ibcon#[25=AT06-06\r\n] 2006.141.08:10:39.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:39.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:39.83#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.08:10:39.83#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:39.83#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:10:39.95#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:10:39.95#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:10:39.97#ibcon#[25=USB\r\n] 2006.141.08:10:40.00#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:10:40.00#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:10:40.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:10:40.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:10:40.00$vc4f8/valo=7,832.99 2006.141.08:10:40.00#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.08:10:40.00#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.08:10:40.00#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:40.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:10:40.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:10:40.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:10:40.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:10:40.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:10:40.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:10:40.06#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:10:40.06#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:10:40.06$vc4f8/va=7,6 2006.141.08:10:40.06#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.08:10:40.06#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.08:10:40.06#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:40.06#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:10:40.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:10:40.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:10:40.14#ibcon#[25=AT07-06\r\n] 2006.141.08:10:40.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:10:40.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:10:40.17#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.08:10:40.17#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:40.17#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:10:40.29#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:10:40.29#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:10:40.31#ibcon#[25=USB\r\n] 2006.141.08:10:40.34#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:10:40.34#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:10:40.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:10:40.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:10:40.34$vc4f8/valo=8,852.99 2006.141.08:10:40.34#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.08:10:40.34#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.08:10:40.34#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:40.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:10:40.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:10:40.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:10:40.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:10:40.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:10:40.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:10:40.40#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:10:40.40#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:10:40.40$vc4f8/va=8,6 2006.141.08:10:40.40#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.08:10:40.40#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.08:10:40.40#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:40.40#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:10:40.46#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:10:40.46#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:10:40.48#ibcon#[25=AT08-06\r\n] 2006.141.08:10:40.51#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:10:40.51#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:10:40.51#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.08:10:40.51#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:40.51#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:10:40.63#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:10:40.63#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:10:40.65#ibcon#[25=USB\r\n] 2006.141.08:10:40.68#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:10:40.68#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:10:40.68#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:10:40.68#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:10:40.68$vc4f8/vblo=1,632.99 2006.141.08:10:40.68#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:10:40.68#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:10:40.68#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:40.68#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:10:40.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:10:40.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:10:40.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:10:40.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:10:40.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:10:40.74#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:10:40.74#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:10:40.74$vc4f8/vb=1,4 2006.141.08:10:40.74#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:10:40.74#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:10:40.74#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:40.74#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:10:40.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:10:40.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:10:40.76#ibcon#[27=AT01-04\r\n] 2006.141.08:10:40.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:10:40.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:10:40.79#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:10:40.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:40.79#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:10:40.91#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:10:40.91#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:10:40.93#ibcon#[27=USB\r\n] 2006.141.08:10:40.96#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:10:40.96#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:10:40.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:10:40.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:10:40.96$vc4f8/vblo=2,640.99 2006.141.08:10:40.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:10:40.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:10:40.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:40.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:40.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:40.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:40.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:10:41.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:41.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:10:41.02#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:10:41.02#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:10:41.02$vc4f8/vb=2,4 2006.141.08:10:41.02#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:10:41.02#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:10:41.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:41.02#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:41.08#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:41.08#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:41.10#ibcon#[27=AT02-04\r\n] 2006.141.08:10:41.13#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:41.13#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:10:41.13#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:10:41.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:41.13#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:41.25#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:41.25#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:41.27#ibcon#[27=USB\r\n] 2006.141.08:10:41.30#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:41.30#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:10:41.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:10:41.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:10:41.30$vc4f8/vblo=3,656.99 2006.141.08:10:41.30#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:10:41.30#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:10:41.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:41.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:41.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:41.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:41.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:10:41.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:41.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:10:41.36#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:10:41.36#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:10:41.36$vc4f8/vb=3,4 2006.141.08:10:41.36#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:10:41.36#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:10:41.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:41.36#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:41.42#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:41.42#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:41.44#ibcon#[27=AT03-04\r\n] 2006.141.08:10:41.47#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:41.47#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:10:41.47#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:10:41.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:41.47#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:41.59#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:41.59#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:41.61#ibcon#[27=USB\r\n] 2006.141.08:10:41.64#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:41.64#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:10:41.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:10:41.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:10:41.64$vc4f8/vblo=4,712.99 2006.141.08:10:41.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:10:41.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:10:41.64#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:41.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:41.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:41.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:41.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:10:41.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:41.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:10:41.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:10:41.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:10:41.70$vc4f8/vb=4,4 2006.141.08:10:41.70#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:10:41.70#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:10:41.70#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:41.70#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:41.76#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:41.76#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:41.78#ibcon#[27=AT04-04\r\n] 2006.141.08:10:41.81#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:41.81#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:10:41.81#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:10:41.81#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:41.81#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:41.93#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:41.93#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:41.95#ibcon#[27=USB\r\n] 2006.141.08:10:41.98#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:41.98#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:10:41.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:10:41.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:10:41.98$vc4f8/vblo=5,744.99 2006.141.08:10:41.98#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:10:41.98#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:10:41.98#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:41.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:41.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:41.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:42.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:10:42.04#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:42.04#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:10:42.04#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:10:42.04#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:10:42.04$vc4f8/vb=5,4 2006.141.08:10:42.04#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:10:42.04#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:10:42.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:42.04#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:42.10#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:42.10#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:42.12#ibcon#[27=AT05-04\r\n] 2006.141.08:10:42.15#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:42.15#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:10:42.15#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:10:42.15#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:42.15#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:42.27#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:42.27#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:42.29#ibcon#[27=USB\r\n] 2006.141.08:10:42.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:42.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:10:42.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:10:42.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:10:42.32$vc4f8/vblo=6,752.99 2006.141.08:10:42.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:10:42.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:10:42.32#ibcon#ireg 17 cls_cnt 0 2006.141.08:10:42.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:42.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:42.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:42.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:10:42.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:42.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:10:42.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:10:42.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:10:42.38$vc4f8/vb=6,4 2006.141.08:10:42.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:10:42.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:10:42.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:10:42.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:42.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:42.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:42.46#ibcon#[27=AT06-04\r\n] 2006.141.08:10:42.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:42.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:10:42.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:10:42.49#ibcon#ireg 7 cls_cnt 0 2006.141.08:10:42.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:42.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:42.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:42.63#ibcon#[27=USB\r\n] 2006.141.08:10:42.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:42.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:10:42.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:10:42.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:10:42.66$vc4f8/vabw=wide 2006.141.08:10:42.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:10:42.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:10:42.66#ibcon#ireg 8 cls_cnt 0 2006.141.08:10:42.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:42.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:42.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:42.68#ibcon#[25=BW32\r\n] 2006.141.08:10:42.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:42.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:10:42.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:10:42.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:10:42.71$vc4f8/vbbw=wide 2006.141.08:10:42.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.08:10:42.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.08:10:42.71#ibcon#ireg 8 cls_cnt 0 2006.141.08:10:42.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:10:42.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:10:42.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:10:42.80#ibcon#[27=BW32\r\n] 2006.141.08:10:42.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:10:42.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:10:42.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:10:42.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:10:42.83$4f8m12a/ifd4f 2006.141.08:10:42.83$ifd4f/lo= 2006.141.08:10:42.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:10:42.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:10:42.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:10:42.83$ifd4f/patch= 2006.141.08:10:42.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:10:42.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:10:42.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:10:42.83$4f8m12a/"form=m,16.000,1:2 2006.141.08:10:42.83$4f8m12a/"tpicd 2006.141.08:10:42.83$4f8m12a/echo=off 2006.141.08:10:42.83$4f8m12a/xlog=off 2006.141.08:10:42.83:!2006.141.08:11:30 2006.141.08:11:02.13#trakl#Source acquired 2006.141.08:11:03.13#flagr#flagr/antenna,acquired 2006.141.08:11:30.00:preob 2006.141.08:11:31.13/onsource/TRACKING 2006.141.08:11:31.13:!2006.141.08:11:40 2006.141.08:11:40.00:data_valid=on 2006.141.08:11:40.00:midob 2006.141.08:11:40.13/onsource/TRACKING 2006.141.08:11:40.13/wx/21.41,1012.8,70 2006.141.08:11:40.29/cable/+6.5236E-03 2006.141.08:11:41.38/va/01,08,usb,yes,33,35 2006.141.08:11:41.38/va/02,07,usb,yes,34,35 2006.141.08:11:41.38/va/03,06,usb,yes,35,36 2006.141.08:11:41.38/va/04,07,usb,yes,34,37 2006.141.08:11:41.38/va/05,07,usb,yes,33,35 2006.141.08:11:41.38/va/06,06,usb,yes,32,32 2006.141.08:11:41.38/va/07,06,usb,yes,33,32 2006.141.08:11:41.38/va/08,06,usb,yes,35,34 2006.141.08:11:41.61/valo/01,532.99,yes,locked 2006.141.08:11:41.61/valo/02,572.99,yes,locked 2006.141.08:11:41.61/valo/03,672.99,yes,locked 2006.141.08:11:41.61/valo/04,832.99,yes,locked 2006.141.08:11:41.61/valo/05,652.99,yes,locked 2006.141.08:11:41.61/valo/06,772.99,yes,locked 2006.141.08:11:41.61/valo/07,832.99,yes,locked 2006.141.08:11:41.61/valo/08,852.99,yes,locked 2006.141.08:11:42.70/vb/01,04,usb,yes,32,31 2006.141.08:11:42.70/vb/02,04,usb,yes,34,35 2006.141.08:11:42.70/vb/03,04,usb,yes,30,34 2006.141.08:11:42.70/vb/04,04,usb,yes,31,31 2006.141.08:11:42.70/vb/05,04,usb,yes,30,34 2006.141.08:11:42.70/vb/06,04,usb,yes,31,34 2006.141.08:11:42.70/vb/07,04,usb,yes,33,33 2006.141.08:11:42.70/vb/08,04,usb,yes,30,34 2006.141.08:11:42.94/vblo/01,632.99,yes,locked 2006.141.08:11:42.94/vblo/02,640.99,yes,locked 2006.141.08:11:42.94/vblo/03,656.99,yes,locked 2006.141.08:11:42.94/vblo/04,712.99,yes,locked 2006.141.08:11:42.94/vblo/05,744.99,yes,locked 2006.141.08:11:42.94/vblo/06,752.99,yes,locked 2006.141.08:11:42.94/vblo/07,734.99,yes,locked 2006.141.08:11:42.94/vblo/08,744.99,yes,locked 2006.141.08:11:43.09/vabw/8 2006.141.08:11:43.24/vbbw/8 2006.141.08:11:43.33/xfe/off,on,15.2 2006.141.08:11:43.71/ifatt/23,28,28,28 2006.141.08:11:44.11/fmout-gps/S +1.06E-07 2006.141.08:11:44.15:!2006.141.08:12:40 2006.141.08:12:40.00:data_valid=off 2006.141.08:12:40.00:postob 2006.141.08:12:40.21/cable/+6.5234E-03 2006.141.08:12:40.21/wx/21.40,1012.9,71 2006.141.08:12:41.11/fmout-gps/S +1.06E-07 2006.141.08:12:41.11:scan_name=141-0813,k06141,60 2006.141.08:12:41.11:source=1803+784,180045.68,782804.0,2000.0,cw 2006.141.08:12:41.13#flagr#flagr/antenna,new-source 2006.141.08:12:42.13:checkk5 2006.141.08:12:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:12:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:12:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:12:43.61/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:12:43.99/chk_obsdata//k5ts1/T1410811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:12:44.37/chk_obsdata//k5ts2/T1410811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:12:44.74/chk_obsdata//k5ts3/T1410811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:12:45.11/chk_obsdata//k5ts4/T1410811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:12:45.86/k5log//k5ts1_log_newline 2006.141.08:12:46.55/k5log//k5ts2_log_newline 2006.141.08:12:47.25/k5log//k5ts3_log_newline 2006.141.08:12:47.94/k5log//k5ts4_log_newline 2006.141.08:12:47.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:12:47.96:4f8m12a=2 2006.141.08:12:47.96$4f8m12a/echo=on 2006.141.08:12:47.96$4f8m12a/pcalon 2006.141.08:12:47.96$pcalon/"no phase cal control is implemented here 2006.141.08:12:47.96$4f8m12a/"tpicd=stop 2006.141.08:12:47.96$4f8m12a/vc4f8 2006.141.08:12:47.96$vc4f8/valo=1,532.99 2006.141.08:12:47.97#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:12:47.97#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:12:47.97#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:47.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:47.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:47.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:48.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:12:48.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:48.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:48.07#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:12:48.07#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:12:48.07$vc4f8/va=1,8 2006.141.08:12:48.07#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:12:48.07#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:12:48.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:48.07#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:48.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:48.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:48.11#ibcon#[25=AT01-08\r\n] 2006.141.08:12:48.14#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:48.14#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:48.14#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:12:48.14#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:48.14#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:48.26#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:48.26#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:48.28#ibcon#[25=USB\r\n] 2006.141.08:12:48.33#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:48.33#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:48.33#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:12:48.33#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:12:48.33$vc4f8/valo=2,572.99 2006.141.08:12:48.33#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:12:48.33#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:12:48.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:48.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:48.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:48.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:48.35#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:12:48.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:48.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:48.39#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:12:48.39#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:12:48.39$vc4f8/va=2,7 2006.141.08:12:48.39#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:12:48.39#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:12:48.39#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:48.39#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:48.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:48.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:48.47#ibcon#[25=AT02-07\r\n] 2006.141.08:12:48.52#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:48.52#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:48.52#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:12:48.52#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:48.52#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:48.64#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:48.64#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:48.66#ibcon#[25=USB\r\n] 2006.141.08:12:48.71#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:48.71#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:48.71#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:12:48.71#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:12:48.71$vc4f8/valo=3,672.99 2006.141.08:12:48.71#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:12:48.71#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:12:48.71#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:48.71#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:48.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:48.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:48.73#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:12:48.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:48.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:48.77#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:12:48.77#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:12:48.77$vc4f8/va=3,6 2006.141.08:12:48.77#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:12:48.77#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:12:48.77#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:48.77#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:48.83#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:48.83#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:48.85#ibcon#[25=AT03-06\r\n] 2006.141.08:12:48.88#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:48.88#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:48.88#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:12:48.88#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:48.88#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:48.89#abcon#<5=/05 4.7 8.1 21.40 701012.9\r\n> 2006.141.08:12:48.91#abcon#{5=INTERFACE CLEAR} 2006.141.08:12:48.97#abcon#[5=S1D000X0/0*\r\n] 2006.141.08:12:49.00#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:49.00#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:49.02#ibcon#[25=USB\r\n] 2006.141.08:12:49.05#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:49.05#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:49.05#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:12:49.05#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:12:49.05$vc4f8/valo=4,832.99 2006.141.08:12:49.05#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:12:49.05#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:12:49.05#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:49.05#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:49.05#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:49.05#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:49.07#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:12:49.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:49.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:49.11#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:12:49.11#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:12:49.11$vc4f8/va=4,7 2006.141.08:12:49.11#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.08:12:49.11#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.08:12:49.11#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:49.11#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:49.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:49.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:49.19#ibcon#[25=AT04-07\r\n] 2006.141.08:12:49.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:49.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:49.22#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.08:12:49.22#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:49.22#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:49.34#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:49.34#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:49.36#ibcon#[25=USB\r\n] 2006.141.08:12:49.41#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:49.41#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:49.41#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:12:49.41#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:12:49.41$vc4f8/valo=5,652.99 2006.141.08:12:49.41#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:12:49.41#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:12:49.41#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:49.41#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:49.41#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:49.41#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:49.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:12:49.47#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:49.47#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:49.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:12:49.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:12:49.47$vc4f8/va=5,7 2006.141.08:12:49.47#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.08:12:49.47#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.08:12:49.47#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:49.47#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:49.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:49.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:49.55#ibcon#[25=AT05-07\r\n] 2006.141.08:12:49.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:49.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:49.58#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.08:12:49.58#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:49.58#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:49.70#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:49.70#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:49.72#ibcon#[25=USB\r\n] 2006.141.08:12:49.75#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:49.75#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:49.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:12:49.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:12:49.75$vc4f8/valo=6,772.99 2006.141.08:12:49.75#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:12:49.75#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:12:49.75#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:49.75#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:49.75#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:49.75#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:49.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:12:49.81#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:49.81#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:49.81#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:12:49.81#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:12:49.81$vc4f8/va=6,6 2006.141.08:12:49.81#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.08:12:49.81#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.08:12:49.81#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:49.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:49.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:49.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:49.89#ibcon#[25=AT06-06\r\n] 2006.141.08:12:49.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:49.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:49.92#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.08:12:49.92#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:49.92#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:12:50.04#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:12:50.04#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:12:50.06#ibcon#[25=USB\r\n] 2006.141.08:12:50.09#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:12:50.09#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:12:50.09#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:12:50.09#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:12:50.09$vc4f8/valo=7,832.99 2006.141.08:12:50.09#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.08:12:50.09#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.08:12:50.09#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:50.09#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:12:50.09#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:12:50.09#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:12:50.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:12:50.18#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:12:50.18#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:12:50.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:12:50.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:12:50.18$vc4f8/va=7,6 2006.141.08:12:50.18#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.08:12:50.18#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.08:12:50.18#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:50.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:12:50.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:12:50.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:12:50.23#ibcon#[25=AT07-06\r\n] 2006.141.08:12:50.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:12:50.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:12:50.26#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.08:12:50.26#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:50.26#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:12:50.38#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:12:50.38#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:12:50.40#ibcon#[25=USB\r\n] 2006.141.08:12:50.43#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:12:50.43#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:12:50.43#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:12:50.43#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:12:50.43$vc4f8/valo=8,852.99 2006.141.08:12:50.43#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:12:50.43#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:12:50.43#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:50.43#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:12:50.43#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:12:50.43#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:12:50.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:12:50.49#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:12:50.49#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:12:50.49#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:12:50.49#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:12:50.49$vc4f8/va=8,6 2006.141.08:12:50.49#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:12:50.49#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:12:50.49#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:50.49#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:12:50.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:12:50.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:12:50.57#ibcon#[25=AT08-06\r\n] 2006.141.08:12:50.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:12:50.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:12:50.60#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:12:50.60#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:50.60#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:12:50.72#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:12:50.72#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:12:50.74#ibcon#[25=USB\r\n] 2006.141.08:12:50.77#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:12:50.77#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:12:50.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:12:50.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:12:50.77$vc4f8/vblo=1,632.99 2006.141.08:12:50.77#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:12:50.77#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:12:50.77#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:50.77#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:50.77#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:50.77#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:50.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:12:50.83#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:50.83#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:12:50.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:12:50.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:12:50.83$vc4f8/vb=1,4 2006.141.08:12:50.83#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:12:50.83#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:12:50.83#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:50.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:50.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:50.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:50.85#ibcon#[27=AT01-04\r\n] 2006.141.08:12:50.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:50.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:12:50.88#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:12:50.88#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:50.88#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:51.00#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:51.00#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:51.02#ibcon#[27=USB\r\n] 2006.141.08:12:51.05#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:51.05#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:12:51.05#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:12:51.05#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:12:51.05$vc4f8/vblo=2,640.99 2006.141.08:12:51.05#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:12:51.05#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:12:51.05#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:51.05#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:51.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:51.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:51.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:12:51.11#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:51.11#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:12:51.11#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:12:51.11#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:12:51.11$vc4f8/vb=2,4 2006.141.08:12:51.11#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:12:51.11#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:12:51.11#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:51.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:51.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:51.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:51.19#ibcon#[27=AT02-04\r\n] 2006.141.08:12:51.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:51.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:12:51.22#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:12:51.22#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:51.22#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:51.34#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:51.34#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:51.36#ibcon#[27=USB\r\n] 2006.141.08:12:51.39#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:51.39#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:12:51.39#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:12:51.39#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:12:51.39$vc4f8/vblo=3,656.99 2006.141.08:12:51.39#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:12:51.39#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:12:51.39#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:51.39#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:51.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:51.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:51.41#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:12:51.46#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:51.46#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:12:51.46#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:12:51.46#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:12:51.46$vc4f8/vb=3,4 2006.141.08:12:51.46#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:12:51.46#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:12:51.46#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:51.46#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:51.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:51.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:51.53#ibcon#[27=AT03-04\r\n] 2006.141.08:12:51.56#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:51.56#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:12:51.56#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:12:51.56#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:51.56#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:51.68#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:51.68#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:51.70#ibcon#[27=USB\r\n] 2006.141.08:12:51.73#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:51.73#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:12:51.73#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:12:51.73#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:12:51.73$vc4f8/vblo=4,712.99 2006.141.08:12:51.73#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:12:51.73#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:12:51.73#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:51.73#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:12:51.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:12:51.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:12:51.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:12:51.79#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:12:51.79#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:12:51.79#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:12:51.79#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:12:51.79$vc4f8/vb=4,4 2006.141.08:12:51.79#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:12:51.79#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:12:51.79#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:51.79#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:12:51.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:12:51.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:12:51.87#ibcon#[27=AT04-04\r\n] 2006.141.08:12:51.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:12:51.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:12:51.90#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:12:51.90#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:51.90#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:12:52.02#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:12:52.02#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:12:52.04#ibcon#[27=USB\r\n] 2006.141.08:12:52.09#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:12:52.09#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:12:52.09#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:12:52.09#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:12:52.09$vc4f8/vblo=5,744.99 2006.141.08:12:52.09#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:12:52.09#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:12:52.09#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:52.09#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:52.09#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:52.09#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:52.11#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:12:52.15#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:52.15#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:12:52.15#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:12:52.15#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:12:52.15$vc4f8/vb=5,4 2006.141.08:12:52.15#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.08:12:52.15#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.08:12:52.15#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:52.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:52.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:52.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:52.23#ibcon#[27=AT05-04\r\n] 2006.141.08:12:52.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:52.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:12:52.26#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.08:12:52.26#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:52.26#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:52.38#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:52.38#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:52.40#ibcon#[27=USB\r\n] 2006.141.08:12:52.43#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:52.43#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:12:52.43#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:12:52.43#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:12:52.43$vc4f8/vblo=6,752.99 2006.141.08:12:52.43#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:12:52.43#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:12:52.43#ibcon#ireg 17 cls_cnt 0 2006.141.08:12:52.43#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:52.43#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:52.43#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:52.45#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:12:52.49#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:52.49#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:12:52.49#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:12:52.49#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:12:52.49$vc4f8/vb=6,4 2006.141.08:12:52.49#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.08:12:52.49#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.08:12:52.49#ibcon#ireg 11 cls_cnt 2 2006.141.08:12:52.49#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:52.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:52.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:52.57#ibcon#[27=AT06-04\r\n] 2006.141.08:12:52.60#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:52.60#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:12:52.60#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.08:12:52.60#ibcon#ireg 7 cls_cnt 0 2006.141.08:12:52.60#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:52.72#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:52.72#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:52.74#ibcon#[27=USB\r\n] 2006.141.08:12:52.77#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:52.77#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:12:52.77#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:12:52.77#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:12:52.77$vc4f8/vabw=wide 2006.141.08:12:52.77#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:12:52.77#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:12:52.77#ibcon#ireg 8 cls_cnt 0 2006.141.08:12:52.77#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:52.77#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:52.77#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:52.79#ibcon#[25=BW32\r\n] 2006.141.08:12:52.82#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:52.82#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:12:52.82#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:12:52.82#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:12:52.82$vc4f8/vbbw=wide 2006.141.08:12:52.82#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:12:52.82#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:12:52.82#ibcon#ireg 8 cls_cnt 0 2006.141.08:12:52.82#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:12:52.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:12:52.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:12:52.91#ibcon#[27=BW32\r\n] 2006.141.08:12:52.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:12:52.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:12:52.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:12:52.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:12:52.94$4f8m12a/ifd4f 2006.141.08:12:52.94$ifd4f/lo= 2006.141.08:12:52.94$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:12:52.94$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:12:52.94$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:12:52.94$ifd4f/patch= 2006.141.08:12:52.94$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:12:52.94$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:12:52.94$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:12:52.94$4f8m12a/"form=m,16.000,1:2 2006.141.08:12:52.94$4f8m12a/"tpicd 2006.141.08:12:52.94$4f8m12a/echo=off 2006.141.08:12:52.94$4f8m12a/xlog=off 2006.141.08:12:52.94:!2006.141.08:13:30 2006.141.08:13:06.13#trakl#Source acquired 2006.141.08:13:08.13#flagr#flagr/antenna,acquired 2006.141.08:13:30.00:preob 2006.141.08:13:30.14/onsource/TRACKING 2006.141.08:13:30.14:!2006.141.08:13:40 2006.141.08:13:40.00:data_valid=on 2006.141.08:13:40.00:midob 2006.141.08:13:41.14/onsource/TRACKING 2006.141.08:13:41.14/wx/21.39,1012.8,71 2006.141.08:13:41.31/cable/+6.5234E-03 2006.141.08:13:42.40/va/01,08,usb,yes,29,31 2006.141.08:13:42.40/va/02,07,usb,yes,30,31 2006.141.08:13:42.40/va/03,06,usb,yes,31,31 2006.141.08:13:42.40/va/04,07,usb,yes,30,32 2006.141.08:13:42.40/va/05,07,usb,yes,29,30 2006.141.08:13:42.40/va/06,06,usb,yes,28,27 2006.141.08:13:42.40/va/07,06,usb,yes,28,28 2006.141.08:13:42.40/va/08,06,usb,yes,30,30 2006.141.08:13:42.63/valo/01,532.99,yes,locked 2006.141.08:13:42.63/valo/02,572.99,yes,locked 2006.141.08:13:42.63/valo/03,672.99,yes,locked 2006.141.08:13:42.63/valo/04,832.99,yes,locked 2006.141.08:13:42.63/valo/05,652.99,yes,locked 2006.141.08:13:42.63/valo/06,772.99,yes,locked 2006.141.08:13:42.63/valo/07,832.99,yes,locked 2006.141.08:13:42.63/valo/08,852.99,yes,locked 2006.141.08:13:43.72/vb/01,04,usb,yes,29,28 2006.141.08:13:43.72/vb/02,04,usb,yes,31,32 2006.141.08:13:43.72/vb/03,04,usb,yes,27,31 2006.141.08:13:43.72/vb/04,04,usb,yes,28,28 2006.141.08:13:43.72/vb/05,04,usb,yes,27,31 2006.141.08:13:43.72/vb/06,04,usb,yes,28,31 2006.141.08:13:43.72/vb/07,04,usb,yes,30,30 2006.141.08:13:43.72/vb/08,04,usb,yes,27,31 2006.141.08:13:43.95/vblo/01,632.99,yes,locked 2006.141.08:13:43.95/vblo/02,640.99,yes,locked 2006.141.08:13:43.95/vblo/03,656.99,yes,locked 2006.141.08:13:43.95/vblo/04,712.99,yes,locked 2006.141.08:13:43.95/vblo/05,744.99,yes,locked 2006.141.08:13:43.95/vblo/06,752.99,yes,locked 2006.141.08:13:43.95/vblo/07,734.99,yes,locked 2006.141.08:13:43.95/vblo/08,744.99,yes,locked 2006.141.08:13:44.10/vabw/8 2006.141.08:13:44.25/vbbw/8 2006.141.08:13:44.34/xfe/off,on,15.2 2006.141.08:13:44.71/ifatt/23,28,28,28 2006.141.08:13:45.11/fmout-gps/S +1.07E-07 2006.141.08:13:45.19:!2006.141.08:14:40 2006.141.08:14:40.00:data_valid=off 2006.141.08:14:40.00:postob 2006.141.08:14:40.16/cable/+6.5245E-03 2006.141.08:14:40.16/wx/21.38,1012.8,71 2006.141.08:14:41.12/fmout-gps/S +1.06E-07 2006.141.08:14:41.12:scan_name=141-0815,k06141,60 2006.141.08:14:41.12:source=1739+522,174036.98,521143.4,2000.0,cw 2006.141.08:14:41.14#flagr#flagr/antenna,new-source 2006.141.08:14:42.14:checkk5 2006.141.08:14:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:14:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:14:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:14:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:14:44.03/chk_obsdata//k5ts1/T1410813??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:14:44.41/chk_obsdata//k5ts2/T1410813??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:14:44.79/chk_obsdata//k5ts3/T1410813??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:14:45.17/chk_obsdata//k5ts4/T1410813??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:14:45.87/k5log//k5ts1_log_newline 2006.141.08:14:46.56/k5log//k5ts2_log_newline 2006.141.08:14:47.27/k5log//k5ts3_log_newline 2006.141.08:14:47.96/k5log//k5ts4_log_newline 2006.141.08:14:47.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:14:47.98:4f8m12a=2 2006.141.08:14:47.98$4f8m12a/echo=on 2006.141.08:14:47.98$4f8m12a/pcalon 2006.141.08:14:47.98$pcalon/"no phase cal control is implemented here 2006.141.08:14:47.98$4f8m12a/"tpicd=stop 2006.141.08:14:47.99$4f8m12a/vc4f8 2006.141.08:14:47.99$vc4f8/valo=1,532.99 2006.141.08:14:47.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:14:47.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:14:47.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:47.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:47.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:47.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:48.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:14:48.09#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:48.09#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:48.09#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:14:48.09#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:14:48.09$vc4f8/va=1,8 2006.141.08:14:48.09#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:14:48.09#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:14:48.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:48.09#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:48.09#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:48.09#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:48.13#ibcon#[25=AT01-08\r\n] 2006.141.08:14:48.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:48.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:48.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:14:48.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:48.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:48.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:48.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:48.30#ibcon#[25=USB\r\n] 2006.141.08:14:48.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:48.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:48.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:14:48.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:14:48.33$vc4f8/valo=2,572.99 2006.141.08:14:48.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:14:48.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:14:48.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:48.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:48.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:48.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:48.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:14:48.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:48.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:48.41#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:14:48.41#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:14:48.41$vc4f8/va=2,7 2006.141.08:14:48.41#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:14:48.41#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:14:48.41#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:48.41#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:48.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:48.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:48.47#ibcon#[25=AT02-07\r\n] 2006.141.08:14:48.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:48.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:48.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:14:48.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:48.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:48.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:48.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:48.64#ibcon#[25=USB\r\n] 2006.141.08:14:48.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:48.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:48.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:14:48.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:14:48.67$vc4f8/valo=3,672.99 2006.141.08:14:48.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:14:48.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:14:48.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:48.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:48.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:48.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:48.71#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:14:48.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:48.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:48.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:14:48.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:14:48.75$vc4f8/va=3,6 2006.141.08:14:48.75#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:14:48.75#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:14:48.75#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:48.75#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:48.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:48.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:48.81#ibcon#[25=AT03-06\r\n] 2006.141.08:14:48.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:48.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:48.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:14:48.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:48.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:48.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:48.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:48.98#ibcon#[25=USB\r\n] 2006.141.08:14:49.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:49.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:49.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:14:49.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:14:49.01$vc4f8/valo=4,832.99 2006.141.08:14:49.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:14:49.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:14:49.01#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:49.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:49.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:49.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:49.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:14:49.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:49.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:49.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:14:49.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:14:49.07$vc4f8/va=4,7 2006.141.08:14:49.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:14:49.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:14:49.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:49.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:49.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:49.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:49.15#ibcon#[25=AT04-07\r\n] 2006.141.08:14:49.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:49.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:49.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:14:49.18#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:49.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:49.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:49.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:49.32#ibcon#[25=USB\r\n] 2006.141.08:14:49.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:49.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:49.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:14:49.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:14:49.35$vc4f8/valo=5,652.99 2006.141.08:14:49.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:14:49.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:14:49.35#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:49.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:49.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:49.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:49.37#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:14:49.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:49.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:49.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:14:49.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:14:49.41$vc4f8/va=5,7 2006.141.08:14:49.41#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:14:49.41#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:14:49.41#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:49.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:49.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:49.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:49.49#ibcon#[25=AT05-07\r\n] 2006.141.08:14:49.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:49.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:49.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:14:49.52#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:49.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:49.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:49.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:49.66#ibcon#[25=USB\r\n] 2006.141.08:14:49.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:49.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:49.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:14:49.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:14:49.69$vc4f8/valo=6,772.99 2006.141.08:14:49.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:14:49.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:14:49.69#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:49.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:49.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:49.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:49.71#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:14:49.75#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:49.75#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:49.75#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:14:49.75#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:14:49.75$vc4f8/va=6,6 2006.141.08:14:49.75#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.08:14:49.75#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.08:14:49.75#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:49.75#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:49.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:49.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:49.83#ibcon#[25=AT06-06\r\n] 2006.141.08:14:49.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:49.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:49.86#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.08:14:49.86#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:49.86#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:14:49.98#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:14:49.98#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:14:50.00#ibcon#[25=USB\r\n] 2006.141.08:14:50.03#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:14:50.03#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:14:50.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:14:50.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:14:50.03$vc4f8/valo=7,832.99 2006.141.08:14:50.03#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:14:50.03#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:14:50.03#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:50.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:14:50.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:14:50.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:14:50.05#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:14:50.09#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:14:50.09#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:14:50.09#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:14:50.09#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:14:50.09$vc4f8/va=7,6 2006.141.08:14:50.09#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.08:14:50.09#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.08:14:50.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:50.09#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:14:50.15#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:14:50.15#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:14:50.17#ibcon#[25=AT07-06\r\n] 2006.141.08:14:50.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:14:50.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:14:50.20#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.08:14:50.20#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:50.20#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:14:50.32#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:14:50.32#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:14:50.34#ibcon#[25=USB\r\n] 2006.141.08:14:50.37#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:14:50.37#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:14:50.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:14:50.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:14:50.37$vc4f8/valo=8,852.99 2006.141.08:14:50.37#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:14:50.37#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:14:50.37#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:50.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:14:50.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:14:50.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:14:50.39#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:14:50.43#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:14:50.43#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:14:50.43#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:14:50.43#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:14:50.43$vc4f8/va=8,6 2006.141.08:14:50.43#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.08:14:50.43#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.08:14:50.43#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:50.43#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:14:50.49#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:14:50.49#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:14:50.51#ibcon#[25=AT08-06\r\n] 2006.141.08:14:50.54#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:14:50.54#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:14:50.54#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.08:14:50.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:50.54#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:14:50.66#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:14:50.66#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:14:50.68#ibcon#[25=USB\r\n] 2006.141.08:14:50.71#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:14:50.71#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:14:50.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:14:50.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:14:50.71$vc4f8/vblo=1,632.99 2006.141.08:14:50.71#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.08:14:50.71#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.08:14:50.71#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:50.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:14:50.71#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:14:50.71#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:14:50.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:14:50.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:14:50.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:14:50.77#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:14:50.77#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:14:50.77$vc4f8/vb=1,4 2006.141.08:14:50.77#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.08:14:50.77#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.08:14:50.77#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:50.77#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:14:50.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:14:50.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:14:50.79#ibcon#[27=AT01-04\r\n] 2006.141.08:14:50.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:14:50.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:14:50.82#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.08:14:50.82#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:50.82#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:14:50.94#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:14:50.94#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:14:50.96#ibcon#[27=USB\r\n] 2006.141.08:14:50.99#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:14:50.99#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:14:50.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:14:50.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:14:50.99$vc4f8/vblo=2,640.99 2006.141.08:14:50.99#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:14:50.99#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:14:50.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:50.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:50.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:50.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:51.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:14:51.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:51.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:14:51.05#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:14:51.05#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:14:51.05$vc4f8/vb=2,4 2006.141.08:14:51.05#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:14:51.05#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:14:51.05#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:51.05#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:51.11#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:51.11#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:51.13#ibcon#[27=AT02-04\r\n] 2006.141.08:14:51.16#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:51.16#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:14:51.16#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:14:51.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:51.16#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:51.28#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:51.28#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:51.30#ibcon#[27=USB\r\n] 2006.141.08:14:51.33#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:51.33#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:14:51.33#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:14:51.33#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:14:51.33$vc4f8/vblo=3,656.99 2006.141.08:14:51.33#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:14:51.33#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:14:51.33#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:51.33#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:51.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:51.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:51.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:14:51.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:51.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:14:51.39#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:14:51.39#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:14:51.39$vc4f8/vb=3,4 2006.141.08:14:51.39#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:14:51.39#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:14:51.39#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:51.39#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:51.45#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:51.45#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:51.47#ibcon#[27=AT03-04\r\n] 2006.141.08:14:51.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:51.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:14:51.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:14:51.50#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:51.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:51.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:51.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:51.64#ibcon#[27=USB\r\n] 2006.141.08:14:51.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:51.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:14:51.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:14:51.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:14:51.67$vc4f8/vblo=4,712.99 2006.141.08:14:51.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:14:51.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:14:51.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:51.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:51.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:51.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:51.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:14:51.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:51.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:14:51.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:14:51.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:14:51.73$vc4f8/vb=4,4 2006.141.08:14:51.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:14:51.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:14:51.73#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:51.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:51.79#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:51.79#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:51.81#ibcon#[27=AT04-04\r\n] 2006.141.08:14:51.84#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:51.84#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:14:51.84#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:14:51.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:51.84#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:51.96#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:51.96#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:51.98#ibcon#[27=USB\r\n] 2006.141.08:14:52.01#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:52.01#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:14:52.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:14:52.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:14:52.01$vc4f8/vblo=5,744.99 2006.141.08:14:52.01#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:14:52.01#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:14:52.01#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:52.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:52.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:52.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:52.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:14:52.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:52.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:14:52.07#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:14:52.07#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:14:52.07$vc4f8/vb=5,4 2006.141.08:14:52.07#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:14:52.07#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:14:52.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:52.07#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:52.13#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:52.13#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:52.15#ibcon#[27=AT05-04\r\n] 2006.141.08:14:52.18#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:52.18#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:14:52.18#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:14:52.18#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:52.18#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:52.30#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:52.30#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:52.32#ibcon#[27=USB\r\n] 2006.141.08:14:52.35#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:52.35#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:14:52.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:14:52.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:14:52.35$vc4f8/vblo=6,752.99 2006.141.08:14:52.35#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:14:52.35#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:14:52.35#ibcon#ireg 17 cls_cnt 0 2006.141.08:14:52.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:52.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:52.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:52.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:14:52.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:52.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:14:52.41#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:14:52.41#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:14:52.41$vc4f8/vb=6,4 2006.141.08:14:52.41#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:14:52.41#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:14:52.41#ibcon#ireg 11 cls_cnt 2 2006.141.08:14:52.41#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:52.47#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:52.47#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:52.49#ibcon#[27=AT06-04\r\n] 2006.141.08:14:52.52#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:52.52#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:14:52.52#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:14:52.52#ibcon#ireg 7 cls_cnt 0 2006.141.08:14:52.52#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:52.64#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:52.64#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:52.66#ibcon#[27=USB\r\n] 2006.141.08:14:52.69#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:52.69#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:14:52.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:14:52.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:14:52.69$vc4f8/vabw=wide 2006.141.08:14:52.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:14:52.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:14:52.69#ibcon#ireg 8 cls_cnt 0 2006.141.08:14:52.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:52.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:52.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:52.71#ibcon#[25=BW32\r\n] 2006.141.08:14:52.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:52.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:14:52.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:14:52.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:14:52.74$vc4f8/vbbw=wide 2006.141.08:14:52.74#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:14:52.74#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:14:52.74#ibcon#ireg 8 cls_cnt 0 2006.141.08:14:52.74#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:14:52.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:14:52.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:14:52.83#ibcon#[27=BW32\r\n] 2006.141.08:14:52.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:14:52.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:14:52.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:14:52.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:14:52.86$4f8m12a/ifd4f 2006.141.08:14:52.86$ifd4f/lo= 2006.141.08:14:52.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:14:52.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:14:52.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:14:52.86$ifd4f/patch= 2006.141.08:14:52.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:14:52.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:14:52.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:14:52.86$4f8m12a/"form=m,16.000,1:2 2006.141.08:14:52.86$4f8m12a/"tpicd 2006.141.08:14:52.86$4f8m12a/echo=off 2006.141.08:14:52.86$4f8m12a/xlog=off 2006.141.08:14:52.86:!2006.141.08:15:20 2006.141.08:15:00.14#trakl#Source acquired 2006.141.08:15:02.14#flagr#flagr/antenna,acquired 2006.141.08:15:20.00:preob 2006.141.08:15:21.14/onsource/TRACKING 2006.141.08:15:21.14:!2006.141.08:15:30 2006.141.08:15:30.00:data_valid=on 2006.141.08:15:30.00:midob 2006.141.08:15:30.14/onsource/TRACKING 2006.141.08:15:30.14/wx/21.35,1012.9,73 2006.141.08:15:30.33/cable/+6.5228E-03 2006.141.08:15:31.42/va/01,08,usb,yes,33,35 2006.141.08:15:31.42/va/02,07,usb,yes,33,34 2006.141.08:15:31.42/va/03,06,usb,yes,35,35 2006.141.08:15:31.42/va/04,07,usb,yes,34,36 2006.141.08:15:31.42/va/05,07,usb,yes,33,35 2006.141.08:15:31.42/va/06,06,usb,yes,32,31 2006.141.08:15:31.42/va/07,06,usb,yes,32,32 2006.141.08:15:31.42/va/08,06,usb,yes,34,34 2006.141.08:15:31.65/valo/01,532.99,yes,locked 2006.141.08:15:31.65/valo/02,572.99,yes,locked 2006.141.08:15:31.65/valo/03,672.99,yes,locked 2006.141.08:15:31.65/valo/04,832.99,yes,locked 2006.141.08:15:31.65/valo/05,652.99,yes,locked 2006.141.08:15:31.65/valo/06,772.99,yes,locked 2006.141.08:15:31.65/valo/07,832.99,yes,locked 2006.141.08:15:31.65/valo/08,852.99,yes,locked 2006.141.08:15:32.74/vb/01,04,usb,yes,32,30 2006.141.08:15:32.74/vb/02,04,usb,yes,34,35 2006.141.08:15:32.74/vb/03,04,usb,yes,30,34 2006.141.08:15:32.74/vb/04,04,usb,yes,31,31 2006.141.08:15:32.74/vb/05,04,usb,yes,29,34 2006.141.08:15:32.74/vb/06,04,usb,yes,30,33 2006.141.08:15:32.74/vb/07,04,usb,yes,32,32 2006.141.08:15:32.74/vb/08,04,usb,yes,30,33 2006.141.08:15:32.98/vblo/01,632.99,yes,locked 2006.141.08:15:32.98/vblo/02,640.99,yes,locked 2006.141.08:15:32.98/vblo/03,656.99,yes,locked 2006.141.08:15:32.98/vblo/04,712.99,yes,locked 2006.141.08:15:32.98/vblo/05,744.99,yes,locked 2006.141.08:15:32.98/vblo/06,752.99,yes,locked 2006.141.08:15:32.98/vblo/07,734.99,yes,locked 2006.141.08:15:32.98/vblo/08,744.99,yes,locked 2006.141.08:15:33.13/vabw/8 2006.141.08:15:33.28/vbbw/8 2006.141.08:15:33.40/xfe/off,on,14.7 2006.141.08:15:33.77/ifatt/23,28,28,28 2006.141.08:15:34.11/fmout-gps/S +1.06E-07 2006.141.08:15:34.15:!2006.141.08:16:30 2006.141.08:16:30.00:data_valid=off 2006.141.08:16:30.00:postob 2006.141.08:16:30.24/cable/+6.5216E-03 2006.141.08:16:30.24/wx/21.33,1012.9,72 2006.141.08:16:31.11/fmout-gps/S +1.06E-07 2006.141.08:16:31.11:scan_name=141-0817,k06141,60 2006.141.08:16:31.11:source=1418+546,141946.60,542314.8,2000.0,cw 2006.141.08:16:31.14#flagr#flagr/antenna,new-source 2006.141.08:16:32.14:checkk5 2006.141.08:16:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:16:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:16:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:16:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:16:34.03/chk_obsdata//k5ts1/T1410815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:16:34.41/chk_obsdata//k5ts2/T1410815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:16:34.78/chk_obsdata//k5ts3/T1410815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:16:35.15/chk_obsdata//k5ts4/T1410815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:16:35.85/k5log//k5ts1_log_newline 2006.141.08:16:36.55/k5log//k5ts2_log_newline 2006.141.08:16:37.26/k5log//k5ts3_log_newline 2006.141.08:16:37.96/k5log//k5ts4_log_newline 2006.141.08:16:37.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:16:37.98:4f8m12a=2 2006.141.08:16:37.98$4f8m12a/echo=on 2006.141.08:16:37.98$4f8m12a/pcalon 2006.141.08:16:37.98$pcalon/"no phase cal control is implemented here 2006.141.08:16:37.98$4f8m12a/"tpicd=stop 2006.141.08:16:37.98$4f8m12a/vc4f8 2006.141.08:16:37.98$vc4f8/valo=1,532.99 2006.141.08:16:37.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.08:16:37.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.08:16:37.99#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:37.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:37.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:37.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:38.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:16:38.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:38.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:38.09#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:16:38.09#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:16:38.09$vc4f8/va=1,8 2006.141.08:16:38.09#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.08:16:38.09#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.08:16:38.09#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:38.09#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:38.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:38.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:38.12#ibcon#[25=AT01-08\r\n] 2006.141.08:16:38.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:38.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:38.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.08:16:38.16#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:38.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:38.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:38.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:38.30#ibcon#[25=USB\r\n] 2006.141.08:16:38.35#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:38.35#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:38.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:16:38.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:16:38.35$vc4f8/valo=2,572.99 2006.141.08:16:38.35#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.08:16:38.35#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.08:16:38.35#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:38.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:38.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:38.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:38.37#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:16:38.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:38.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:38.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:16:38.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:16:38.41$vc4f8/va=2,7 2006.141.08:16:38.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.08:16:38.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.08:16:38.41#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:38.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:38.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:38.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:38.49#ibcon#[25=AT02-07\r\n] 2006.141.08:16:38.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:38.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:38.54#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.08:16:38.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:38.54#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:38.66#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:38.66#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:38.68#ibcon#[25=USB\r\n] 2006.141.08:16:38.73#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:38.73#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:38.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:16:38.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:16:38.73$vc4f8/valo=3,672.99 2006.141.08:16:38.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.08:16:38.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.08:16:38.73#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:38.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:38.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:38.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:38.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:16:38.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:38.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:38.79#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:16:38.79#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:16:38.79$vc4f8/va=3,6 2006.141.08:16:38.79#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.08:16:38.79#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.08:16:38.79#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:38.79#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:38.85#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:38.85#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:38.87#ibcon#[25=AT03-06\r\n] 2006.141.08:16:38.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:38.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:38.90#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.08:16:38.90#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:38.90#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:39.02#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:39.02#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:39.04#ibcon#[25=USB\r\n] 2006.141.08:16:39.07#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:39.07#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:39.07#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:16:39.07#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:16:39.07$vc4f8/valo=4,832.99 2006.141.08:16:39.07#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.08:16:39.07#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.08:16:39.07#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:39.07#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:39.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:39.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:39.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:16:39.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:39.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:39.13#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:16:39.13#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:16:39.13$vc4f8/va=4,7 2006.141.08:16:39.13#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.08:16:39.13#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.08:16:39.13#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:39.13#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:39.19#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:39.19#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:39.21#ibcon#[25=AT04-07\r\n] 2006.141.08:16:39.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:39.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:39.24#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.08:16:39.24#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:39.24#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:39.36#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:39.36#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:39.38#ibcon#[25=USB\r\n] 2006.141.08:16:39.41#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:39.41#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:39.41#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:16:39.41#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:16:39.41$vc4f8/valo=5,652.99 2006.141.08:16:39.41#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.08:16:39.41#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.08:16:39.41#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:39.41#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:39.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:39.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:39.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:16:39.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:39.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:39.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:16:39.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:16:39.48$vc4f8/va=5,7 2006.141.08:16:39.48#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.08:16:39.48#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.08:16:39.48#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:39.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:39.53#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:39.53#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:39.55#ibcon#[25=AT05-07\r\n] 2006.141.08:16:39.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:39.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:39.58#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.08:16:39.58#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:39.58#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:39.70#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:39.70#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:39.72#ibcon#[25=USB\r\n] 2006.141.08:16:39.75#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:39.75#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:39.75#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:16:39.75#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:16:39.75$vc4f8/valo=6,772.99 2006.141.08:16:39.75#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.08:16:39.75#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.08:16:39.75#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:39.75#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:39.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:39.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:39.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:16:39.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:39.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:39.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:16:39.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:16:39.81$vc4f8/va=6,6 2006.141.08:16:39.81#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.141.08:16:39.81#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.141.08:16:39.81#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:39.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:39.87#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:39.87#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:39.89#ibcon#[25=AT06-06\r\n] 2006.141.08:16:39.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:39.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:39.92#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.141.08:16:39.92#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:39.92#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:16:40.04#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:16:40.04#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:16:40.06#ibcon#[25=USB\r\n] 2006.141.08:16:40.09#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:16:40.09#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.141.08:16:40.09#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:16:40.09#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:16:40.09$vc4f8/valo=7,832.99 2006.141.08:16:40.09#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.141.08:16:40.09#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.141.08:16:40.09#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:40.09#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:16:40.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:16:40.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:16:40.11#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:16:40.15#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:16:40.15#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.141.08:16:40.15#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:16:40.15#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:16:40.15$vc4f8/va=7,6 2006.141.08:16:40.15#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.141.08:16:40.15#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.141.08:16:40.15#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:40.15#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:16:40.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:16:40.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:16:40.23#ibcon#[25=AT07-06\r\n] 2006.141.08:16:40.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:16:40.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.141.08:16:40.26#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.141.08:16:40.26#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:40.26#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:16:40.38#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:16:40.38#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:16:40.40#ibcon#[25=USB\r\n] 2006.141.08:16:40.43#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:16:40.43#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.141.08:16:40.43#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:16:40.43#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:16:40.43$vc4f8/valo=8,852.99 2006.141.08:16:40.43#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.08:16:40.43#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.08:16:40.43#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:40.43#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:16:40.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:16:40.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:16:40.45#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:16:40.49#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:16:40.49#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:16:40.49#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:16:40.49#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:16:40.49$vc4f8/va=8,6 2006.141.08:16:40.49#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.141.08:16:40.49#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.141.08:16:40.49#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:40.49#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:16:40.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:16:40.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:16:40.57#ibcon#[25=AT08-06\r\n] 2006.141.08:16:40.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:16:40.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.141.08:16:40.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.141.08:16:40.60#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:40.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:16:40.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:16:40.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:16:40.74#ibcon#[25=USB\r\n] 2006.141.08:16:40.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:16:40.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.141.08:16:40.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:16:40.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:16:40.77$vc4f8/vblo=1,632.99 2006.141.08:16:40.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.141.08:16:40.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.141.08:16:40.77#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:40.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:16:40.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:16:40.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:16:40.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:16:40.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:16:40.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.141.08:16:40.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:16:40.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:16:40.83$vc4f8/vb=1,4 2006.141.08:16:40.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.141.08:16:40.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.141.08:16:40.83#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:40.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:16:40.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:16:40.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:16:40.85#ibcon#[27=AT01-04\r\n] 2006.141.08:16:40.89#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:16:40.89#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.141.08:16:40.89#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.141.08:16:40.89#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:40.89#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:16:41.01#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:16:41.01#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:16:41.03#ibcon#[27=USB\r\n] 2006.141.08:16:41.06#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:16:41.06#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.141.08:16:41.06#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:16:41.06#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:16:41.06$vc4f8/vblo=2,640.99 2006.141.08:16:41.06#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.141.08:16:41.06#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.141.08:16:41.06#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:41.06#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:41.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:41.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:41.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:16:41.12#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:41.12#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.141.08:16:41.12#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:16:41.12#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:16:41.12$vc4f8/vb=2,4 2006.141.08:16:41.12#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.141.08:16:41.12#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.141.08:16:41.12#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:41.12#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:41.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:41.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:41.20#ibcon#[27=AT02-04\r\n] 2006.141.08:16:41.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:41.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.141.08:16:41.23#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.141.08:16:41.23#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:41.23#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:41.35#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:41.35#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:41.37#ibcon#[27=USB\r\n] 2006.141.08:16:41.40#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:41.40#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.141.08:16:41.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:16:41.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:16:41.40$vc4f8/vblo=3,656.99 2006.141.08:16:41.40#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.141.08:16:41.40#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.141.08:16:41.40#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:41.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:41.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:41.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:41.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:16:41.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:41.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.141.08:16:41.46#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:16:41.46#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:16:41.46$vc4f8/vb=3,4 2006.141.08:16:41.46#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.141.08:16:41.46#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.141.08:16:41.46#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:41.46#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:41.52#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:41.52#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:41.54#ibcon#[27=AT03-04\r\n] 2006.141.08:16:41.57#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:41.57#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.141.08:16:41.57#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.141.08:16:41.57#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:41.57#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:41.69#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:41.69#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:41.71#ibcon#[27=USB\r\n] 2006.141.08:16:41.74#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:41.74#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.141.08:16:41.74#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:16:41.74#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:16:41.74$vc4f8/vblo=4,712.99 2006.141.08:16:41.74#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.141.08:16:41.74#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.141.08:16:41.74#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:41.74#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:41.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:41.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:41.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:16:41.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:41.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.141.08:16:41.80#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:16:41.80#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:16:41.80$vc4f8/vb=4,4 2006.141.08:16:41.80#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.141.08:16:41.80#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.141.08:16:41.80#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:41.80#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:41.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:41.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:41.88#ibcon#[27=AT04-04\r\n] 2006.141.08:16:41.91#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:41.91#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.141.08:16:41.91#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.141.08:16:41.91#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:41.91#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:42.03#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:42.03#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:42.05#ibcon#[27=USB\r\n] 2006.141.08:16:42.08#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:42.08#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.141.08:16:42.08#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:16:42.08#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:16:42.08$vc4f8/vblo=5,744.99 2006.141.08:16:42.08#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.141.08:16:42.08#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.141.08:16:42.08#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:42.08#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:42.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:42.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:42.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:16:42.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:42.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.141.08:16:42.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:16:42.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:16:42.14$vc4f8/vb=5,4 2006.141.08:16:42.14#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.141.08:16:42.14#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.141.08:16:42.14#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:42.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:42.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:42.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:42.22#ibcon#[27=AT05-04\r\n] 2006.141.08:16:42.25#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:42.25#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.141.08:16:42.25#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.141.08:16:42.25#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:42.25#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:42.37#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:42.37#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:42.39#ibcon#[27=USB\r\n] 2006.141.08:16:42.42#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:42.42#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.141.08:16:42.42#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:16:42.42#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:16:42.42$vc4f8/vblo=6,752.99 2006.141.08:16:42.42#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.08:16:42.42#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.08:16:42.42#ibcon#ireg 17 cls_cnt 0 2006.141.08:16:42.42#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:42.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:42.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:42.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:16:42.48#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:42.48#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:16:42.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:16:42.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:16:42.48$vc4f8/vb=6,4 2006.141.08:16:42.48#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.141.08:16:42.48#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.141.08:16:42.48#ibcon#ireg 11 cls_cnt 2 2006.141.08:16:42.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:42.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:42.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:42.56#ibcon#[27=AT06-04\r\n] 2006.141.08:16:42.59#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:42.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.141.08:16:42.59#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.141.08:16:42.59#ibcon#ireg 7 cls_cnt 0 2006.141.08:16:42.59#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:42.71#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:42.71#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:42.73#ibcon#[27=USB\r\n] 2006.141.08:16:42.76#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:42.76#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.141.08:16:42.76#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:16:42.76#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:16:42.76$vc4f8/vabw=wide 2006.141.08:16:42.76#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.141.08:16:42.76#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.141.08:16:42.76#ibcon#ireg 8 cls_cnt 0 2006.141.08:16:42.76#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:42.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:42.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:42.78#ibcon#[25=BW32\r\n] 2006.141.08:16:42.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:42.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.141.08:16:42.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:16:42.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:16:42.81$vc4f8/vbbw=wide 2006.141.08:16:42.81#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:16:42.81#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:16:42.81#ibcon#ireg 8 cls_cnt 0 2006.141.08:16:42.81#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:16:42.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:16:42.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:16:42.90#ibcon#[27=BW32\r\n] 2006.141.08:16:42.93#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:16:42.93#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:16:42.93#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:16:42.93#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:16:42.93$4f8m12a/ifd4f 2006.141.08:16:42.93$ifd4f/lo= 2006.141.08:16:42.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:16:42.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:16:42.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:16:42.93$ifd4f/patch= 2006.141.08:16:42.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:16:42.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:16:42.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:16:42.93$4f8m12a/"form=m,16.000,1:2 2006.141.08:16:42.93$4f8m12a/"tpicd 2006.141.08:16:42.93$4f8m12a/echo=off 2006.141.08:16:42.93$4f8m12a/xlog=off 2006.141.08:16:42.93:!2006.141.08:17:10 2006.141.08:16:51.14#trakl#Source acquired 2006.141.08:16:52.14#flagr#flagr/antenna,acquired 2006.141.08:17:10.00:preob 2006.141.08:17:11.14/onsource/TRACKING 2006.141.08:17:11.14:!2006.141.08:17:20 2006.141.08:17:20.00:data_valid=on 2006.141.08:17:20.00:midob 2006.141.08:17:20.14/onsource/TRACKING 2006.141.08:17:20.14/wx/21.31,1012.9,71 2006.141.08:17:20.27/cable/+6.5226E-03 2006.141.08:17:21.36/va/01,08,usb,yes,29,30 2006.141.08:17:21.36/va/02,07,usb,yes,29,30 2006.141.08:17:21.36/va/03,06,usb,yes,30,31 2006.141.08:17:21.36/va/04,07,usb,yes,29,32 2006.141.08:17:21.36/va/05,07,usb,yes,28,30 2006.141.08:17:21.36/va/06,06,usb,yes,28,27 2006.141.08:17:21.36/va/07,06,usb,yes,28,28 2006.141.08:17:21.36/va/08,06,usb,yes,30,29 2006.141.08:17:21.59/valo/01,532.99,yes,locked 2006.141.08:17:21.59/valo/02,572.99,yes,locked 2006.141.08:17:21.59/valo/03,672.99,yes,locked 2006.141.08:17:21.59/valo/04,832.99,yes,locked 2006.141.08:17:21.59/valo/05,652.99,yes,locked 2006.141.08:17:21.59/valo/06,772.99,yes,locked 2006.141.08:17:21.59/valo/07,832.99,yes,locked 2006.141.08:17:21.59/valo/08,852.99,yes,locked 2006.141.08:17:22.68/vb/01,04,usb,yes,29,28 2006.141.08:17:22.68/vb/02,04,usb,yes,31,32 2006.141.08:17:22.68/vb/03,04,usb,yes,27,31 2006.141.08:17:22.68/vb/04,04,usb,yes,28,28 2006.141.08:17:22.68/vb/05,04,usb,yes,27,31 2006.141.08:17:22.68/vb/06,04,usb,yes,28,30 2006.141.08:17:22.68/vb/07,04,usb,yes,30,30 2006.141.08:17:22.68/vb/08,04,usb,yes,27,31 2006.141.08:17:22.92/vblo/01,632.99,yes,locked 2006.141.08:17:22.92/vblo/02,640.99,yes,locked 2006.141.08:17:22.92/vblo/03,656.99,yes,locked 2006.141.08:17:22.92/vblo/04,712.99,yes,locked 2006.141.08:17:22.92/vblo/05,744.99,yes,locked 2006.141.08:17:22.92/vblo/06,752.99,yes,locked 2006.141.08:17:22.92/vblo/07,734.99,yes,locked 2006.141.08:17:22.92/vblo/08,744.99,yes,locked 2006.141.08:17:23.07/vabw/8 2006.141.08:17:23.22/vbbw/8 2006.141.08:17:23.31/xfe/off,on,15.0 2006.141.08:17:23.68/ifatt/23,28,28,28 2006.141.08:17:24.11/fmout-gps/S +1.06E-07 2006.141.08:17:24.15:!2006.141.08:18:20 2006.141.08:18:20.00:data_valid=off 2006.141.08:18:20.00:postob 2006.141.08:18:20.20/cable/+6.5230E-03 2006.141.08:18:20.20/wx/21.28,1012.9,71 2006.141.08:18:21.12/fmout-gps/S +1.07E-07 2006.141.08:18:21.12:scan_name=141-0819,k06141,60 2006.141.08:18:21.12:source=0955+476,095819.67,472507.8,2000.0,cw 2006.141.08:18:21.14#flagr#flagr/antenna,new-source 2006.141.08:18:22.14:checkk5 2006.141.08:18:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:18:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:18:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:18:23.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:18:24.03/chk_obsdata//k5ts1/T1410817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:18:24.40/chk_obsdata//k5ts2/T1410817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:18:24.83/chk_obsdata//k5ts3/T1410817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:18:25.21/chk_obsdata//k5ts4/T1410817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:18:25.91/k5log//k5ts1_log_newline 2006.141.08:18:26.66/k5log//k5ts2_log_newline 2006.141.08:18:27.36/k5log//k5ts3_log_newline 2006.141.08:18:28.06/k5log//k5ts4_log_newline 2006.141.08:18:28.08/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:18:28.08:4f8m12a=2 2006.141.08:18:28.08$4f8m12a/echo=on 2006.141.08:18:28.08$4f8m12a/pcalon 2006.141.08:18:28.08$pcalon/"no phase cal control is implemented here 2006.141.08:18:28.08$4f8m12a/"tpicd=stop 2006.141.08:18:28.08$4f8m12a/vc4f8 2006.141.08:18:28.08$vc4f8/valo=1,532.99 2006.141.08:18:28.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:18:28.09#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:18:28.09#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:28.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:28.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:28.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:28.14#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:18:28.19#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:28.19#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:28.19#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:18:28.19#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:18:28.19$vc4f8/va=1,8 2006.141.08:18:28.19#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.08:18:28.19#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.08:18:28.19#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:28.19#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:28.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:28.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:28.22#ibcon#[25=AT01-08\r\n] 2006.141.08:18:28.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:28.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:28.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.08:18:28.26#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:28.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:28.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:28.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:28.40#ibcon#[25=USB\r\n] 2006.141.08:18:28.43#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:28.43#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:28.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:18:28.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:18:28.43$vc4f8/valo=2,572.99 2006.141.08:18:28.43#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.08:18:28.43#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.08:18:28.43#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:28.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:28.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:28.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:28.47#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:18:28.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:28.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:28.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:18:28.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:18:28.51$vc4f8/va=2,7 2006.141.08:18:28.51#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.08:18:28.51#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.08:18:28.51#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:28.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:28.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:28.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:28.57#ibcon#[25=AT02-07\r\n] 2006.141.08:18:28.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:28.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:28.60#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.08:18:28.60#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:28.60#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:28.72#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:28.72#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:28.74#ibcon#[25=USB\r\n] 2006.141.08:18:28.77#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:28.77#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:28.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:18:28.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:18:28.77$vc4f8/valo=3,672.99 2006.141.08:18:28.77#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:18:28.77#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:18:28.77#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:28.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:28.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:28.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:28.81#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:18:28.85#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:28.85#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:28.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:18:28.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:18:28.85$vc4f8/va=3,6 2006.141.08:18:28.85#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:18:28.85#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:18:28.85#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:28.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:28.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:28.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:28.91#ibcon#[25=AT03-06\r\n] 2006.141.08:18:28.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:28.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:28.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:18:28.94#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:28.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:29.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:29.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:29.08#ibcon#[25=USB\r\n] 2006.141.08:18:29.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:29.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:29.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:18:29.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:18:29.11$vc4f8/valo=4,832.99 2006.141.08:18:29.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:18:29.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:18:29.11#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:29.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:29.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:29.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:29.13#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:18:29.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:29.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:29.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:18:29.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:18:29.17$vc4f8/va=4,7 2006.141.08:18:29.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.08:18:29.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.08:18:29.17#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:29.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:29.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:29.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:29.25#ibcon#[25=AT04-07\r\n] 2006.141.08:18:29.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:29.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:29.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.08:18:29.28#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:29.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:29.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:29.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:29.42#ibcon#[25=USB\r\n] 2006.141.08:18:29.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:29.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:29.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:18:29.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:18:29.45$vc4f8/valo=5,652.99 2006.141.08:18:29.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.08:18:29.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.08:18:29.45#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:29.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:29.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:29.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:29.47#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:18:29.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:29.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:29.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:18:29.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:18:29.51$vc4f8/va=5,7 2006.141.08:18:29.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.08:18:29.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.08:18:29.51#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:29.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:29.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:29.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:29.59#ibcon#[25=AT05-07\r\n] 2006.141.08:18:29.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:29.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:29.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.08:18:29.62#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:29.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:29.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:29.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:29.76#ibcon#[25=USB\r\n] 2006.141.08:18:29.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:29.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:29.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:18:29.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:18:29.79$vc4f8/valo=6,772.99 2006.141.08:18:29.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.08:18:29.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.08:18:29.79#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:29.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:29.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:29.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:29.81#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:18:29.85#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:29.85#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:29.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:18:29.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:18:29.85$vc4f8/va=6,6 2006.141.08:18:29.85#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.141.08:18:29.85#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.141.08:18:29.85#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:29.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:29.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:29.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:29.93#ibcon#[25=AT06-06\r\n] 2006.141.08:18:29.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:29.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:29.96#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.141.08:18:29.96#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:29.96#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:18:30.08#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:18:30.08#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:18:30.10#ibcon#[25=USB\r\n] 2006.141.08:18:30.13#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:18:30.13#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.141.08:18:30.13#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:18:30.13#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:18:30.13$vc4f8/valo=7,832.99 2006.141.08:18:30.13#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.141.08:18:30.13#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.141.08:18:30.13#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:30.13#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:18:30.13#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:18:30.13#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:18:30.15#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:18:30.19#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:18:30.19#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.141.08:18:30.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:18:30.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:18:30.19$vc4f8/va=7,6 2006.141.08:18:30.19#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.141.08:18:30.19#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.141.08:18:30.19#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:30.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:18:30.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:18:30.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:18:30.27#ibcon#[25=AT07-06\r\n] 2006.141.08:18:30.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:18:30.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.141.08:18:30.30#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.141.08:18:30.30#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:30.30#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:18:30.42#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:18:30.42#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:18:30.44#ibcon#[25=USB\r\n] 2006.141.08:18:30.47#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:18:30.47#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.141.08:18:30.47#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:18:30.47#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:18:30.47$vc4f8/valo=8,852.99 2006.141.08:18:30.47#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.141.08:18:30.47#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.141.08:18:30.47#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:30.47#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:18:30.47#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:18:30.47#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:18:30.49#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:18:30.53#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:18:30.53#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.141.08:18:30.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:18:30.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:18:30.53$vc4f8/va=8,6 2006.141.08:18:30.53#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.141.08:18:30.53#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.141.08:18:30.53#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:30.53#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:18:30.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:18:30.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:18:30.61#ibcon#[25=AT08-06\r\n] 2006.141.08:18:30.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:18:30.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.141.08:18:30.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.141.08:18:30.64#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:30.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:18:30.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:18:30.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:18:30.78#ibcon#[25=USB\r\n] 2006.141.08:18:30.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:18:30.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.141.08:18:30.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:18:30.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:18:30.81$vc4f8/vblo=1,632.99 2006.141.08:18:30.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.08:18:30.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.08:18:30.81#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:30.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:18:30.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:18:30.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:18:30.83#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:18:30.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:18:30.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:18:30.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:18:30.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:18:30.87$vc4f8/vb=1,4 2006.141.08:18:30.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.141.08:18:30.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.141.08:18:30.87#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:30.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:18:30.87#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:18:30.87#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:18:30.89#ibcon#[27=AT01-04\r\n] 2006.141.08:18:30.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:18:30.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.141.08:18:30.92#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.141.08:18:30.92#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:30.92#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:18:31.04#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:18:31.04#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:18:31.06#ibcon#[27=USB\r\n] 2006.141.08:18:31.09#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:18:31.09#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.141.08:18:31.09#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:18:31.09#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:18:31.09$vc4f8/vblo=2,640.99 2006.141.08:18:31.09#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:18:31.09#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:18:31.09#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:31.09#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:31.09#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:31.09#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:31.11#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:18:31.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:31.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:18:31.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:18:31.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:18:31.15$vc4f8/vb=2,4 2006.141.08:18:31.15#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.141.08:18:31.15#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.141.08:18:31.15#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:31.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:31.21#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:31.21#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:31.23#ibcon#[27=AT02-04\r\n] 2006.141.08:18:31.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:31.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.141.08:18:31.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.141.08:18:31.26#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:31.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:31.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:31.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:31.40#ibcon#[27=USB\r\n] 2006.141.08:18:31.43#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:31.43#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.141.08:18:31.43#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:18:31.43#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:18:31.43$vc4f8/vblo=3,656.99 2006.141.08:18:31.43#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.141.08:18:31.43#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.141.08:18:31.43#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:31.43#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:31.43#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:31.43#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:31.45#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:18:31.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:31.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.141.08:18:31.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:18:31.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:18:31.49$vc4f8/vb=3,4 2006.141.08:18:31.49#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.141.08:18:31.49#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.141.08:18:31.49#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:31.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:31.55#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:31.55#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:31.57#ibcon#[27=AT03-04\r\n] 2006.141.08:18:31.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:31.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.141.08:18:31.60#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.141.08:18:31.60#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:31.60#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:31.72#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:31.72#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:31.74#ibcon#[27=USB\r\n] 2006.141.08:18:31.77#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:31.77#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.141.08:18:31.77#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:18:31.77#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:18:31.77$vc4f8/vblo=4,712.99 2006.141.08:18:31.77#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.141.08:18:31.77#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.141.08:18:31.77#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:31.77#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:31.77#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:31.77#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:31.79#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:18:31.83#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:31.83#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.141.08:18:31.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:18:31.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:18:31.83$vc4f8/vb=4,4 2006.141.08:18:31.83#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.141.08:18:31.83#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.141.08:18:31.83#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:31.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:31.89#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:31.89#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:31.91#ibcon#[27=AT04-04\r\n] 2006.141.08:18:31.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:31.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.141.08:18:31.94#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.141.08:18:31.94#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:31.94#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:32.06#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:32.06#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:32.08#ibcon#[27=USB\r\n] 2006.141.08:18:32.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:32.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.141.08:18:32.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:18:32.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:18:32.11$vc4f8/vblo=5,744.99 2006.141.08:18:32.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.141.08:18:32.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.141.08:18:32.11#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:32.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:32.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:32.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:32.13#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:18:32.17#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:32.17#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.141.08:18:32.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:18:32.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:18:32.17$vc4f8/vb=5,4 2006.141.08:18:32.17#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.141.08:18:32.17#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.141.08:18:32.17#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:32.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:32.23#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:32.23#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:32.25#ibcon#[27=AT05-04\r\n] 2006.141.08:18:32.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:32.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.141.08:18:32.28#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.141.08:18:32.28#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:32.28#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:32.40#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:32.40#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:32.42#ibcon#[27=USB\r\n] 2006.141.08:18:32.45#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:32.45#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.141.08:18:32.45#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:18:32.45#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:18:32.45$vc4f8/vblo=6,752.99 2006.141.08:18:32.45#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.141.08:18:32.45#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.141.08:18:32.45#ibcon#ireg 17 cls_cnt 0 2006.141.08:18:32.45#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:32.45#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:32.45#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:32.47#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:18:32.51#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:32.51#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.141.08:18:32.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:18:32.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:18:32.51$vc4f8/vb=6,4 2006.141.08:18:32.51#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.141.08:18:32.51#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.141.08:18:32.51#ibcon#ireg 11 cls_cnt 2 2006.141.08:18:32.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:32.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:32.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:32.59#ibcon#[27=AT06-04\r\n] 2006.141.08:18:32.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:32.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.141.08:18:32.62#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.141.08:18:32.62#ibcon#ireg 7 cls_cnt 0 2006.141.08:18:32.62#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:32.74#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:32.74#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:32.76#ibcon#[27=USB\r\n] 2006.141.08:18:32.79#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:32.79#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.141.08:18:32.79#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:18:32.79#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:18:32.79$vc4f8/vabw=wide 2006.141.08:18:32.79#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.141.08:18:32.79#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.141.08:18:32.79#ibcon#ireg 8 cls_cnt 0 2006.141.08:18:32.79#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:32.79#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:32.79#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:32.81#ibcon#[25=BW32\r\n] 2006.141.08:18:32.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:32.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.141.08:18:32.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:18:32.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:18:32.84$vc4f8/vbbw=wide 2006.141.08:18:32.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:18:32.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:18:32.84#ibcon#ireg 8 cls_cnt 0 2006.141.08:18:32.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:18:32.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:18:32.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:18:32.94#ibcon#[27=BW32\r\n] 2006.141.08:18:32.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:18:32.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:18:32.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:18:32.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:18:32.97$4f8m12a/ifd4f 2006.141.08:18:32.97$ifd4f/lo= 2006.141.08:18:32.97$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:18:32.97$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:18:32.97$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:18:32.97$ifd4f/patch= 2006.141.08:18:32.97$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:18:32.97$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:18:32.97$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:18:32.97$4f8m12a/"form=m,16.000,1:2 2006.141.08:18:32.97$4f8m12a/"tpicd 2006.141.08:18:32.97$4f8m12a/echo=off 2006.141.08:18:32.97$4f8m12a/xlog=off 2006.141.08:18:32.97:!2006.141.08:19:00 2006.141.08:18:45.14#trakl#Source acquired 2006.141.08:18:45.14#flagr#flagr/antenna,acquired 2006.141.08:19:00.00:preob 2006.141.08:19:01.13/onsource/TRACKING 2006.141.08:19:01.13:!2006.141.08:19:10 2006.141.08:19:10.00:data_valid=on 2006.141.08:19:10.00:midob 2006.141.08:19:10.13/onsource/TRACKING 2006.141.08:19:10.13/wx/21.25,1012.9,71 2006.141.08:19:10.28/cable/+6.5253E-03 2006.141.08:19:11.37/va/01,08,usb,yes,28,30 2006.141.08:19:11.37/va/02,07,usb,yes,28,29 2006.141.08:19:11.37/va/03,06,usb,yes,30,30 2006.141.08:19:11.37/va/04,07,usb,yes,29,31 2006.141.08:19:11.37/va/05,07,usb,yes,28,29 2006.141.08:19:11.37/va/06,06,usb,yes,27,26 2006.141.08:19:11.37/va/07,06,usb,yes,27,27 2006.141.08:19:11.37/va/08,06,usb,yes,29,29 2006.141.08:19:11.60/valo/01,532.99,yes,locked 2006.141.08:19:11.60/valo/02,572.99,yes,locked 2006.141.08:19:11.60/valo/03,672.99,yes,locked 2006.141.08:19:11.60/valo/04,832.99,yes,locked 2006.141.08:19:11.60/valo/05,652.99,yes,locked 2006.141.08:19:11.60/valo/06,772.99,yes,locked 2006.141.08:19:11.60/valo/07,832.99,yes,locked 2006.141.08:19:11.60/valo/08,852.99,yes,locked 2006.141.08:19:12.69/vb/01,04,usb,yes,29,28 2006.141.08:19:12.69/vb/02,04,usb,yes,30,32 2006.141.08:19:12.69/vb/03,04,usb,yes,27,30 2006.141.08:19:12.69/vb/04,04,usb,yes,28,28 2006.141.08:19:12.69/vb/05,04,usb,yes,26,30 2006.141.08:19:12.69/vb/06,04,usb,yes,27,30 2006.141.08:19:12.69/vb/07,04,usb,yes,29,29 2006.141.08:19:12.69/vb/08,04,usb,yes,27,30 2006.141.08:19:12.93/vblo/01,632.99,yes,locked 2006.141.08:19:12.93/vblo/02,640.99,yes,locked 2006.141.08:19:12.93/vblo/03,656.99,yes,locked 2006.141.08:19:12.93/vblo/04,712.99,yes,locked 2006.141.08:19:12.93/vblo/05,744.99,yes,locked 2006.141.08:19:12.93/vblo/06,752.99,yes,locked 2006.141.08:19:12.93/vblo/07,734.99,yes,locked 2006.141.08:19:12.93/vblo/08,744.99,yes,locked 2006.141.08:19:13.08/vabw/8 2006.141.08:19:13.23/vbbw/8 2006.141.08:19:13.32/xfe/off,on,15.2 2006.141.08:19:13.72/ifatt/23,28,28,28 2006.141.08:19:14.12/fmout-gps/S +1.07E-07 2006.141.08:19:14.16:!2006.141.08:20:10 2006.141.08:20:10.00:data_valid=off 2006.141.08:20:10.00:postob 2006.141.08:20:10.21/cable/+6.5231E-03 2006.141.08:20:10.21/wx/21.22,1012.9,71 2006.141.08:20:11.12/fmout-gps/S +1.07E-07 2006.141.08:20:11.12:scan_name=141-0822,k06141,60 2006.141.08:20:11.12:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.141.08:20:13.13#flagr#flagr/antenna,new-source 2006.141.08:20:13.13:checkk5 2006.141.08:20:13.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:20:13.89/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:20:14.27/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:20:14.65/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:20:15.02/chk_obsdata//k5ts1/T1410819??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:20:15.40/chk_obsdata//k5ts2/T1410819??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:20:15.77/chk_obsdata//k5ts3/T1410819??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:20:16.14/chk_obsdata//k5ts4/T1410819??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:20:16.83/k5log//k5ts1_log_newline 2006.141.08:20:17.53/k5log//k5ts2_log_newline 2006.141.08:20:18.22/k5log//k5ts3_log_newline 2006.141.08:20:18.91/k5log//k5ts4_log_newline 2006.141.08:20:18.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:20:18.94:4f8m12a=3 2006.141.08:20:18.94$4f8m12a/echo=on 2006.141.08:20:18.94$4f8m12a/pcalon 2006.141.08:20:18.94$pcalon/"no phase cal control is implemented here 2006.141.08:20:18.94$4f8m12a/"tpicd=stop 2006.141.08:20:18.94$4f8m12a/vc4f8 2006.141.08:20:18.94$vc4f8/valo=1,532.99 2006.141.08:20:18.94#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:20:18.94#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:20:18.94#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:18.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:18.94#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:18.94#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:18.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:20:19.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:19.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:19.04#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:20:19.04#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:20:19.04$vc4f8/va=1,8 2006.141.08:20:19.04#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.08:20:19.04#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.08:20:19.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:19.04#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:19.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:19.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:19.08#ibcon#[25=AT01-08\r\n] 2006.141.08:20:19.11#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:19.11#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:19.11#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.08:20:19.11#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:19.11#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:19.23#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:19.23#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:19.25#ibcon#[25=USB\r\n] 2006.141.08:20:19.26#abcon#<5=/05 5.2 8.1 21.21 731012.9\r\n> 2006.141.08:20:19.30#abcon#{5=INTERFACE CLEAR} 2006.141.08:20:19.30#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:19.30#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:19.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:20:19.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:20:19.30$vc4f8/valo=2,572.99 2006.141.08:20:19.30#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.141.08:20:19.30#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.141.08:20:19.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:19.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:20:19.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:20:19.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:20:19.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:20:19.36#abcon#[5=S1D000X0/0*\r\n] 2006.141.08:20:19.36#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:20:19.36#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.141.08:20:19.36#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:20:19.36#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:20:19.36$vc4f8/va=2,7 2006.141.08:20:19.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.08:20:19.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.08:20:19.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:19.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:19.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:19.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:19.44#ibcon#[25=AT02-07\r\n] 2006.141.08:20:19.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:19.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:19.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.08:20:19.48#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:19.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:19.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:19.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:19.62#ibcon#[25=USB\r\n] 2006.141.08:20:19.67#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:19.67#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:19.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:20:19.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:20:19.67$vc4f8/valo=3,672.99 2006.141.08:20:19.67#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:20:19.67#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:20:19.67#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:19.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:19.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:19.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:19.69#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:20:19.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:19.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:19.73#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:20:19.73#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:20:19.73$vc4f8/va=3,6 2006.141.08:20:19.73#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:20:19.73#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:20:19.73#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:19.73#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:19.79#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:19.79#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:19.81#ibcon#[25=AT03-06\r\n] 2006.141.08:20:19.84#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:19.84#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:19.84#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:20:19.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:19.84#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:19.96#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:19.96#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:19.98#ibcon#[25=USB\r\n] 2006.141.08:20:20.01#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:20.01#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:20.01#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:20:20.01#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:20:20.01$vc4f8/valo=4,832.99 2006.141.08:20:20.01#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:20:20.01#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:20:20.01#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:20.01#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:20.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:20.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:20.03#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:20:20.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:20.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:20.07#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:20:20.07#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:20:20.07$vc4f8/va=4,7 2006.141.08:20:20.07#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:20:20.07#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:20:20.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:20.07#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:20.13#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:20.13#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:20.15#ibcon#[25=AT04-07\r\n] 2006.141.08:20:20.18#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:20.18#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:20.18#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:20:20.18#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:20.18#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:20.30#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:20.30#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:20.32#ibcon#[25=USB\r\n] 2006.141.08:20:20.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:20.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:20.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:20:20.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:20:20.37$vc4f8/valo=5,652.99 2006.141.08:20:20.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:20:20.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:20:20.37#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:20.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:20.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:20.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:20.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:20:20.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:20.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:20.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:20:20.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:20:20.43$vc4f8/va=5,7 2006.141.08:20:20.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:20:20.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:20:20.43#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:20.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:20.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:20.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:20.51#ibcon#[25=AT05-07\r\n] 2006.141.08:20:20.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:20.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:20.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:20:20.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:20.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:20.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:20.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:20.68#ibcon#[25=USB\r\n] 2006.141.08:20:20.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:20.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:20.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:20:20.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:20:20.71$vc4f8/valo=6,772.99 2006.141.08:20:20.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:20:20.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:20:20.71#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:20.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:20.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:20.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:20.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:20:20.77#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:20.77#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:20.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:20:20.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:20:20.77$vc4f8/va=6,6 2006.141.08:20:20.77#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:20:20.77#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:20:20.77#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:20.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:20.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:20.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:20.85#ibcon#[25=AT06-06\r\n] 2006.141.08:20:20.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:20.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:20.88#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:20:20.88#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:20.88#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:20:21.00#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:20:21.00#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:20:21.02#ibcon#[25=USB\r\n] 2006.141.08:20:21.05#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:20:21.05#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:20:21.05#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:20:21.05#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:20:21.05$vc4f8/valo=7,832.99 2006.141.08:20:21.05#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:20:21.05#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:20:21.05#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:21.05#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:20:21.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:20:21.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:20:21.09#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:20:21.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:20:21.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:20:21.14#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:20:21.14#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:20:21.14$vc4f8/va=7,6 2006.141.08:20:21.14#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:20:21.14#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:20:21.14#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:21.14#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:20:21.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:20:21.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:20:21.19#ibcon#[25=AT07-06\r\n] 2006.141.08:20:21.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:20:21.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:20:21.22#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:20:21.22#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:21.22#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:20:21.34#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:20:21.34#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:20:21.36#ibcon#[25=USB\r\n] 2006.141.08:20:21.39#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:20:21.39#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:20:21.39#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:20:21.39#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:20:21.39$vc4f8/valo=8,852.99 2006.141.08:20:21.39#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:20:21.39#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:20:21.39#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:21.39#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:20:21.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:20:21.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:20:21.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:20:21.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:20:21.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:20:21.45#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:20:21.45#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:20:21.45$vc4f8/va=8,6 2006.141.08:20:21.45#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:20:21.45#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:20:21.45#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:21.45#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:20:21.51#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:20:21.51#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:20:21.53#ibcon#[25=AT08-06\r\n] 2006.141.08:20:21.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:20:21.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:20:21.56#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:20:21.56#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:21.56#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:20:21.68#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:20:21.68#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:20:21.70#ibcon#[25=USB\r\n] 2006.141.08:20:21.73#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:20:21.73#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:20:21.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:20:21.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:20:21.73$vc4f8/vblo=1,632.99 2006.141.08:20:21.73#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:20:21.73#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:20:21.73#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:21.73#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:21.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:21.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:21.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:20:21.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:21.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:20:21.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:20:21.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:20:21.79$vc4f8/vb=1,4 2006.141.08:20:21.79#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.08:20:21.79#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.08:20:21.79#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:21.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:21.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:21.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:21.81#ibcon#[27=AT01-04\r\n] 2006.141.08:20:21.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:21.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:20:21.84#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.08:20:21.84#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:21.84#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:21.96#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:21.96#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:21.98#ibcon#[27=USB\r\n] 2006.141.08:20:22.01#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:22.01#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:20:22.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:20:22.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:20:22.01$vc4f8/vblo=2,640.99 2006.141.08:20:22.01#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.08:20:22.01#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.08:20:22.01#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:22.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:20:22.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:20:22.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:20:22.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:20:22.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:20:22.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:20:22.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:20:22.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:20:22.07$vc4f8/vb=2,4 2006.141.08:20:22.07#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.08:20:22.07#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.08:20:22.07#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:22.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:20:22.13#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:20:22.13#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:20:22.15#ibcon#[27=AT02-04\r\n] 2006.141.08:20:22.18#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:20:22.18#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:20:22.18#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.08:20:22.18#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:22.18#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:20:22.30#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:20:22.30#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:20:22.32#ibcon#[27=USB\r\n] 2006.141.08:20:22.35#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:20:22.35#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:20:22.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:20:22.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:20:22.35$vc4f8/vblo=3,656.99 2006.141.08:20:22.35#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.08:20:22.35#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.08:20:22.35#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:22.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:20:22.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:20:22.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:20:22.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:20:22.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:20:22.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:20:22.42#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:20:22.42#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:20:22.42$vc4f8/vb=3,4 2006.141.08:20:22.42#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.08:20:22.42#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.08:20:22.42#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:22.42#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:22.47#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:22.47#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:22.49#ibcon#[27=AT03-04\r\n] 2006.141.08:20:22.52#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:22.52#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:20:22.52#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.08:20:22.52#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:22.52#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:22.64#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:22.64#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:22.66#ibcon#[27=USB\r\n] 2006.141.08:20:22.69#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:22.69#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:20:22.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:20:22.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:20:22.69$vc4f8/vblo=4,712.99 2006.141.08:20:22.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:20:22.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:20:22.69#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:22.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:22.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:22.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:22.71#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:20:22.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:22.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:20:22.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:20:22.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:20:22.75$vc4f8/vb=4,4 2006.141.08:20:22.75#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:20:22.75#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:20:22.75#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:22.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:22.81#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:22.81#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:22.83#ibcon#[27=AT04-04\r\n] 2006.141.08:20:22.86#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:22.86#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:20:22.86#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:20:22.86#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:22.86#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:22.98#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:22.98#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:23.00#ibcon#[27=USB\r\n] 2006.141.08:20:23.03#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:23.03#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:20:23.03#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:20:23.03#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:20:23.03$vc4f8/vblo=5,744.99 2006.141.08:20:23.03#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:20:23.03#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:20:23.03#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:23.03#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:23.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:23.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:23.05#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:20:23.11#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:23.11#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:20:23.11#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:20:23.11#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:20:23.11$vc4f8/vb=5,4 2006.141.08:20:23.11#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:20:23.11#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:20:23.11#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:23.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:23.15#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:23.15#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:23.17#ibcon#[27=AT05-04\r\n] 2006.141.08:20:23.20#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:23.20#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:20:23.20#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:20:23.20#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:23.20#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:23.32#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:23.32#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:23.34#ibcon#[27=USB\r\n] 2006.141.08:20:23.37#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:23.37#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:20:23.37#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:20:23.37#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:20:23.37$vc4f8/vblo=6,752.99 2006.141.08:20:23.37#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:20:23.37#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:20:23.37#ibcon#ireg 17 cls_cnt 0 2006.141.08:20:23.37#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:23.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:23.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:23.39#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:20:23.43#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:23.43#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:20:23.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:20:23.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:20:23.43$vc4f8/vb=6,4 2006.141.08:20:23.43#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:20:23.43#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:20:23.43#ibcon#ireg 11 cls_cnt 2 2006.141.08:20:23.43#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:23.49#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:23.49#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:23.51#ibcon#[27=AT06-04\r\n] 2006.141.08:20:23.54#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:23.54#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:20:23.54#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:20:23.54#ibcon#ireg 7 cls_cnt 0 2006.141.08:20:23.54#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:23.66#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:23.66#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:23.68#ibcon#[27=USB\r\n] 2006.141.08:20:23.71#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:23.71#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:20:23.71#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:20:23.71#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:20:23.71$vc4f8/vabw=wide 2006.141.08:20:23.71#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:20:23.71#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:20:23.71#ibcon#ireg 8 cls_cnt 0 2006.141.08:20:23.71#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:23.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:23.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:23.73#ibcon#[25=BW32\r\n] 2006.141.08:20:23.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:23.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:20:23.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:20:23.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:20:23.76$vc4f8/vbbw=wide 2006.141.08:20:23.76#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.141.08:20:23.76#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.141.08:20:23.76#ibcon#ireg 8 cls_cnt 0 2006.141.08:20:23.76#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:20:23.83#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:20:23.83#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:20:23.85#ibcon#[27=BW32\r\n] 2006.141.08:20:23.88#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:20:23.88#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.141.08:20:23.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:20:23.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:20:23.88$4f8m12a/ifd4f 2006.141.08:20:23.88$ifd4f/lo= 2006.141.08:20:23.88$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:20:23.88$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:20:23.88$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:20:23.88$ifd4f/patch= 2006.141.08:20:23.88$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:20:23.88$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:20:23.88$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:20:23.88$4f8m12a/"form=m,16.000,1:2 2006.141.08:20:23.88$4f8m12a/"tpicd 2006.141.08:20:23.88$4f8m12a/echo=off 2006.141.08:20:23.88$4f8m12a/xlog=off 2006.141.08:20:23.88:!2006.141.08:21:50 2006.141.08:20:58.13#trakl#Source acquired 2006.141.08:20:59.13#flagr#flagr/antenna,acquired 2006.141.08:21:50.00:preob 2006.141.08:21:51.14/onsource/TRACKING 2006.141.08:21:51.14:!2006.141.08:22:00 2006.141.08:22:00.00:data_valid=on 2006.141.08:22:00.00:midob 2006.141.08:22:00.14/onsource/TRACKING 2006.141.08:22:00.14/wx/21.18,1013.0,71 2006.141.08:22:00.21/cable/+6.5222E-03 2006.141.08:22:01.30/va/01,08,usb,yes,29,31 2006.141.08:22:01.30/va/02,07,usb,yes,29,31 2006.141.08:22:01.30/va/03,06,usb,yes,31,31 2006.141.08:22:01.30/va/04,07,usb,yes,30,32 2006.141.08:22:01.30/va/05,07,usb,yes,29,30 2006.141.08:22:01.30/va/06,06,usb,yes,28,27 2006.141.08:22:01.30/va/07,06,usb,yes,28,28 2006.141.08:22:01.30/va/08,06,usb,yes,30,30 2006.141.08:22:01.53/valo/01,532.99,yes,locked 2006.141.08:22:01.53/valo/02,572.99,yes,locked 2006.141.08:22:01.53/valo/03,672.99,yes,locked 2006.141.08:22:01.53/valo/04,832.99,yes,locked 2006.141.08:22:01.53/valo/05,652.99,yes,locked 2006.141.08:22:01.53/valo/06,772.99,yes,locked 2006.141.08:22:01.53/valo/07,832.99,yes,locked 2006.141.08:22:01.53/valo/08,852.99,yes,locked 2006.141.08:22:02.62/vb/01,04,usb,yes,29,28 2006.141.08:22:02.62/vb/02,04,usb,yes,31,33 2006.141.08:22:02.62/vb/03,04,usb,yes,27,31 2006.141.08:22:02.62/vb/04,04,usb,yes,28,29 2006.141.08:22:02.62/vb/05,04,usb,yes,27,31 2006.141.08:22:02.62/vb/06,04,usb,yes,28,31 2006.141.08:22:02.62/vb/07,04,usb,yes,30,30 2006.141.08:22:02.62/vb/08,04,usb,yes,28,31 2006.141.08:22:02.85/vblo/01,632.99,yes,locked 2006.141.08:22:02.85/vblo/02,640.99,yes,locked 2006.141.08:22:02.85/vblo/03,656.99,yes,locked 2006.141.08:22:02.85/vblo/04,712.99,yes,locked 2006.141.08:22:02.85/vblo/05,744.99,yes,locked 2006.141.08:22:02.85/vblo/06,752.99,yes,locked 2006.141.08:22:02.85/vblo/07,734.99,yes,locked 2006.141.08:22:02.85/vblo/08,744.99,yes,locked 2006.141.08:22:03.00/vabw/8 2006.141.08:22:03.15/vbbw/8 2006.141.08:22:03.24/xfe/off,on,14.2 2006.141.08:22:03.62/ifatt/23,28,28,28 2006.141.08:22:04.12/fmout-gps/S +1.05E-07 2006.141.08:22:04.16:!2006.141.08:23:00 2006.141.08:23:00.00:data_valid=off 2006.141.08:23:00.00:postob 2006.141.08:23:00.16/cable/+6.5233E-03 2006.141.08:23:00.16/wx/21.15,1013.0,72 2006.141.08:23:01.12/fmout-gps/S +1.05E-07 2006.141.08:23:01.12:scan_name=141-0825,k06141,60 2006.141.08:23:01.12:source=3c371,180650.68,694928.1,2000.0,cw 2006.141.08:23:01.14#flagr#flagr/antenna,new-source 2006.141.08:23:02.14:checkk5 2006.141.08:23:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:23:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:23:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:23:03.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:23:04.03/chk_obsdata//k5ts1/T1410822??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:23:04.41/chk_obsdata//k5ts2/T1410822??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:23:04.79/chk_obsdata//k5ts3/T1410822??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:23:05.16/chk_obsdata//k5ts4/T1410822??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:23:05.86/k5log//k5ts1_log_newline 2006.141.08:23:06.55/k5log//k5ts2_log_newline 2006.141.08:23:07.24/k5log//k5ts3_log_newline 2006.141.08:23:07.93/k5log//k5ts4_log_newline 2006.141.08:23:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:23:07.96:4f8m12a=3 2006.141.08:23:07.96$4f8m12a/echo=on 2006.141.08:23:07.96$4f8m12a/pcalon 2006.141.08:23:07.96$pcalon/"no phase cal control is implemented here 2006.141.08:23:07.96$4f8m12a/"tpicd=stop 2006.141.08:23:07.96$4f8m12a/vc4f8 2006.141.08:23:07.96$vc4f8/valo=1,532.99 2006.141.08:23:07.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:23:07.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:23:07.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:07.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:07.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:07.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:07.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:23:08.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:08.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:08.03#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:23:08.03#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:23:08.03$vc4f8/va=1,8 2006.141.08:23:08.03#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:23:08.03#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:23:08.03#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:08.03#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:08.03#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:08.03#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:08.05#ibcon#[25=AT01-08\r\n] 2006.141.08:23:08.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:08.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:08.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:23:08.09#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:08.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:08.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:08.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:08.23#ibcon#[25=USB\r\n] 2006.141.08:23:08.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:08.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:08.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:23:08.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:23:08.26$vc4f8/valo=2,572.99 2006.141.08:23:08.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:23:08.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:23:08.26#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:08.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:08.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:08.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:23:08.34#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:08.34#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:08.34#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:23:08.34#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:23:08.34$vc4f8/va=2,7 2006.141.08:23:08.34#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:23:08.34#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:23:08.34#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:08.34#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:08.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:08.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:08.40#ibcon#[25=AT02-07\r\n] 2006.141.08:23:08.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:08.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:08.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:23:08.43#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:08.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:08.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:08.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:08.57#ibcon#[25=USB\r\n] 2006.141.08:23:08.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:08.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:08.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:23:08.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:23:08.60$vc4f8/valo=3,672.99 2006.141.08:23:08.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:23:08.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:23:08.60#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:08.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:08.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:08.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:23:08.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:08.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:08.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:23:08.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:23:08.68$vc4f8/va=3,6 2006.141.08:23:08.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:23:08.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:23:08.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:08.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:08.72#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:08.72#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:08.74#ibcon#[25=AT03-06\r\n] 2006.141.08:23:08.77#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:08.77#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:08.77#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:23:08.77#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:08.77#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:08.89#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:08.89#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:08.91#ibcon#[25=USB\r\n] 2006.141.08:23:08.94#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:08.94#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:08.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:23:08.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:23:08.94$vc4f8/valo=4,832.99 2006.141.08:23:08.94#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:23:08.94#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:23:08.94#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:08.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:08.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:08.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:08.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:23:09.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:09.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:09.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:23:09.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:23:09.00$vc4f8/va=4,7 2006.141.08:23:09.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:23:09.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:23:09.00#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:09.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:09.06#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:09.06#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:09.08#ibcon#[25=AT04-07\r\n] 2006.141.08:23:09.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:09.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:09.11#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:23:09.11#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:09.11#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:09.23#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:09.23#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:09.25#ibcon#[25=USB\r\n] 2006.141.08:23:09.28#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:09.28#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:09.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:23:09.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:23:09.28$vc4f8/valo=5,652.99 2006.141.08:23:09.28#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:23:09.28#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:23:09.28#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:09.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:09.28#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:09.28#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:09.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:23:09.34#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:09.34#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:09.34#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:23:09.34#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:23:09.34$vc4f8/va=5,7 2006.141.08:23:09.34#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:23:09.34#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:23:09.34#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:09.34#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:09.40#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:09.40#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:09.42#ibcon#[25=AT05-07\r\n] 2006.141.08:23:09.45#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:09.45#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:09.45#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:23:09.45#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:09.45#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:09.57#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:09.57#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:09.59#ibcon#[25=USB\r\n] 2006.141.08:23:09.62#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:09.62#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:09.62#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:23:09.62#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:23:09.62$vc4f8/valo=6,772.99 2006.141.08:23:09.62#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:23:09.62#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:23:09.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:09.62#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:09.62#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:09.62#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:09.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:23:09.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:09.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:09.68#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:23:09.68#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:23:09.68$vc4f8/va=6,6 2006.141.08:23:09.68#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.141.08:23:09.68#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.141.08:23:09.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:09.68#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:09.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:09.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:09.76#ibcon#[25=AT06-06\r\n] 2006.141.08:23:09.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:09.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:09.79#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.141.08:23:09.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:09.79#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:23:09.91#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:23:09.91#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:23:09.93#ibcon#[25=USB\r\n] 2006.141.08:23:09.96#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:23:09.96#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.141.08:23:09.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:23:09.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:23:09.96$vc4f8/valo=7,832.99 2006.141.08:23:09.96#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.141.08:23:09.96#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.141.08:23:09.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:09.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:23:09.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:23:09.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:23:09.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:23:10.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:23:10.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.141.08:23:10.02#ibcon#about to clear, iclass 12 cls_cnt 0 2006.141.08:23:10.02#ibcon#cleared, iclass 12 cls_cnt 0 2006.141.08:23:10.02$vc4f8/va=7,6 2006.141.08:23:10.02#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.141.08:23:10.02#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.141.08:23:10.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:10.02#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:23:10.08#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:23:10.08#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:23:10.10#ibcon#[25=AT07-06\r\n] 2006.141.08:23:10.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:23:10.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.141.08:23:10.13#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.141.08:23:10.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:10.13#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:23:10.25#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:23:10.25#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:23:10.27#ibcon#[25=USB\r\n] 2006.141.08:23:10.30#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:23:10.30#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.141.08:23:10.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.141.08:23:10.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.141.08:23:10.30$vc4f8/valo=8,852.99 2006.141.08:23:10.30#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.141.08:23:10.30#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.141.08:23:10.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:10.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:23:10.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:23:10.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:23:10.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:23:10.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:23:10.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.141.08:23:10.36#ibcon#about to clear, iclass 16 cls_cnt 0 2006.141.08:23:10.36#ibcon#cleared, iclass 16 cls_cnt 0 2006.141.08:23:10.36$vc4f8/va=8,6 2006.141.08:23:10.36#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.141.08:23:10.36#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.141.08:23:10.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:10.36#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:23:10.42#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:23:10.42#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:23:10.44#ibcon#[25=AT08-06\r\n] 2006.141.08:23:10.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:23:10.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.141.08:23:10.47#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.141.08:23:10.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:10.47#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:23:10.59#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:23:10.59#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:23:10.61#ibcon#[25=USB\r\n] 2006.141.08:23:10.64#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:23:10.64#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.141.08:23:10.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.141.08:23:10.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.141.08:23:10.64$vc4f8/vblo=1,632.99 2006.141.08:23:10.64#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.141.08:23:10.64#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.141.08:23:10.64#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:10.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:23:10.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:23:10.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:23:10.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:23:10.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:23:10.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.141.08:23:10.70#ibcon#about to clear, iclass 20 cls_cnt 0 2006.141.08:23:10.70#ibcon#cleared, iclass 20 cls_cnt 0 2006.141.08:23:10.70$vc4f8/vb=1,4 2006.141.08:23:10.70#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.141.08:23:10.70#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.141.08:23:10.70#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:10.70#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:23:10.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:23:10.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:23:10.72#ibcon#[27=AT01-04\r\n] 2006.141.08:23:10.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:23:10.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.141.08:23:10.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.141.08:23:10.75#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:10.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:23:10.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:23:10.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:23:10.89#ibcon#[27=USB\r\n] 2006.141.08:23:10.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:23:10.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.141.08:23:10.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.141.08:23:10.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.141.08:23:10.92$vc4f8/vblo=2,640.99 2006.141.08:23:10.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.141.08:23:10.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.141.08:23:10.92#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:10.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:10.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:10.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:10.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:23:10.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:10.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.141.08:23:10.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.141.08:23:10.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.141.08:23:10.98$vc4f8/vb=2,4 2006.141.08:23:10.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.141.08:23:10.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.141.08:23:10.98#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:10.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:11.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:11.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:11.06#ibcon#[27=AT02-04\r\n] 2006.141.08:23:11.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:11.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.141.08:23:11.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.141.08:23:11.09#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:11.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:11.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:11.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:11.23#ibcon#[27=USB\r\n] 2006.141.08:23:11.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:11.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.141.08:23:11.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.141.08:23:11.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.141.08:23:11.26$vc4f8/vblo=3,656.99 2006.141.08:23:11.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.141.08:23:11.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.141.08:23:11.26#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:11.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:11.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:11.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:11.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:23:11.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:11.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.141.08:23:11.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.141.08:23:11.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.141.08:23:11.32$vc4f8/vb=3,4 2006.141.08:23:11.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.141.08:23:11.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.141.08:23:11.32#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:11.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:11.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:11.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:11.40#ibcon#[27=AT03-04\r\n] 2006.141.08:23:11.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:11.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.141.08:23:11.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.141.08:23:11.43#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:11.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:11.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:11.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:11.57#ibcon#[27=USB\r\n] 2006.141.08:23:11.62#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:11.62#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.141.08:23:11.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.141.08:23:11.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.141.08:23:11.62$vc4f8/vblo=4,712.99 2006.141.08:23:11.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.141.08:23:11.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.141.08:23:11.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:11.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:11.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:11.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:23:11.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:11.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.141.08:23:11.68#ibcon#about to clear, iclass 32 cls_cnt 0 2006.141.08:23:11.68#ibcon#cleared, iclass 32 cls_cnt 0 2006.141.08:23:11.68$vc4f8/vb=4,4 2006.141.08:23:11.68#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.141.08:23:11.68#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.141.08:23:11.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:11.68#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:11.74#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:11.74#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:11.76#ibcon#[27=AT04-04\r\n] 2006.141.08:23:11.79#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:11.79#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.141.08:23:11.79#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.141.08:23:11.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:11.79#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:11.91#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:11.91#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:11.93#ibcon#[27=USB\r\n] 2006.141.08:23:11.96#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:11.96#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.141.08:23:11.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.141.08:23:11.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.141.08:23:11.96$vc4f8/vblo=5,744.99 2006.141.08:23:11.96#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.141.08:23:11.96#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.141.08:23:11.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:11.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:11.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:11.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:23:12.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:12.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.141.08:23:12.02#ibcon#about to clear, iclass 36 cls_cnt 0 2006.141.08:23:12.02#ibcon#cleared, iclass 36 cls_cnt 0 2006.141.08:23:12.02$vc4f8/vb=5,4 2006.141.08:23:12.02#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.141.08:23:12.02#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.141.08:23:12.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:12.02#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:12.08#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:12.08#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:12.10#ibcon#[27=AT05-04\r\n] 2006.141.08:23:12.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:12.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.141.08:23:12.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.141.08:23:12.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:12.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:12.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:12.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:12.27#ibcon#[27=USB\r\n] 2006.141.08:23:12.32#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:12.32#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.141.08:23:12.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.141.08:23:12.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.141.08:23:12.32$vc4f8/vblo=6,752.99 2006.141.08:23:12.32#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.141.08:23:12.32#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.141.08:23:12.32#ibcon#ireg 17 cls_cnt 0 2006.141.08:23:12.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:12.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:12.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:12.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:23:12.38#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:12.38#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.141.08:23:12.38#ibcon#about to clear, iclass 40 cls_cnt 0 2006.141.08:23:12.38#ibcon#cleared, iclass 40 cls_cnt 0 2006.141.08:23:12.38$vc4f8/vb=6,4 2006.141.08:23:12.38#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.141.08:23:12.38#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.141.08:23:12.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:23:12.38#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:12.44#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:12.44#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:12.46#ibcon#[27=AT06-04\r\n] 2006.141.08:23:12.49#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:12.49#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.141.08:23:12.49#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.141.08:23:12.49#ibcon#ireg 7 cls_cnt 0 2006.141.08:23:12.49#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:12.61#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:12.61#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:12.63#ibcon#[27=USB\r\n] 2006.141.08:23:12.66#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:12.66#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.141.08:23:12.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.141.08:23:12.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.141.08:23:12.66$vc4f8/vabw=wide 2006.141.08:23:12.66#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.141.08:23:12.66#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.141.08:23:12.66#ibcon#ireg 8 cls_cnt 0 2006.141.08:23:12.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:12.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:12.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:12.68#ibcon#[25=BW32\r\n] 2006.141.08:23:12.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:12.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.141.08:23:12.71#ibcon#about to clear, iclass 6 cls_cnt 0 2006.141.08:23:12.71#ibcon#cleared, iclass 6 cls_cnt 0 2006.141.08:23:12.71$vc4f8/vbbw=wide 2006.141.08:23:12.71#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.141.08:23:12.71#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.141.08:23:12.71#ibcon#ireg 8 cls_cnt 0 2006.141.08:23:12.71#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:23:12.78#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:23:12.78#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:23:12.80#ibcon#[27=BW32\r\n] 2006.141.08:23:12.83#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:23:12.83#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.141.08:23:12.83#ibcon#about to clear, iclass 10 cls_cnt 0 2006.141.08:23:12.83#ibcon#cleared, iclass 10 cls_cnt 0 2006.141.08:23:12.83$4f8m12a/ifd4f 2006.141.08:23:12.83$ifd4f/lo= 2006.141.08:23:12.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:23:12.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:23:12.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:23:12.83$ifd4f/patch= 2006.141.08:23:12.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:23:12.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:23:12.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:23:12.83$4f8m12a/"form=m,16.000,1:2 2006.141.08:23:12.83$4f8m12a/"tpicd 2006.141.08:23:12.83$4f8m12a/echo=off 2006.141.08:23:12.83$4f8m12a/xlog=off 2006.141.08:23:12.83:!2006.141.08:25:20 2006.141.08:23:46.14#trakl#Source acquired 2006.141.08:23:46.14#flagr#flagr/antenna,acquired 2006.141.08:25:20.00:preob 2006.141.08:25:20.14/onsource/TRACKING 2006.141.08:25:20.14:!2006.141.08:25:30 2006.141.08:25:30.00:data_valid=on 2006.141.08:25:30.00:midob 2006.141.08:25:31.14/onsource/TRACKING 2006.141.08:25:31.14/wx/21.12,1013.1,73 2006.141.08:25:31.25/cable/+6.5211E-03 2006.141.08:25:32.34/va/01,08,usb,yes,30,32 2006.141.08:25:32.34/va/02,07,usb,yes,30,31 2006.141.08:25:32.34/va/03,06,usb,yes,32,32 2006.141.08:25:32.34/va/04,07,usb,yes,31,33 2006.141.08:25:32.34/va/05,07,usb,yes,29,31 2006.141.08:25:32.34/va/06,06,usb,yes,29,28 2006.141.08:25:32.34/va/07,06,usb,yes,29,29 2006.141.08:25:32.34/va/08,06,usb,yes,31,30 2006.141.08:25:32.57/valo/01,532.99,yes,locked 2006.141.08:25:32.57/valo/02,572.99,yes,locked 2006.141.08:25:32.57/valo/03,672.99,yes,locked 2006.141.08:25:32.57/valo/04,832.99,yes,locked 2006.141.08:25:32.57/valo/05,652.99,yes,locked 2006.141.08:25:32.57/valo/06,772.99,yes,locked 2006.141.08:25:32.57/valo/07,832.99,yes,locked 2006.141.08:25:32.57/valo/08,852.99,yes,locked 2006.141.08:25:33.66/vb/01,04,usb,yes,30,29 2006.141.08:25:33.66/vb/02,04,usb,yes,32,33 2006.141.08:25:33.66/vb/03,04,usb,yes,28,32 2006.141.08:25:33.66/vb/04,04,usb,yes,29,29 2006.141.08:25:33.66/vb/05,04,usb,yes,28,32 2006.141.08:25:33.66/vb/06,04,usb,yes,29,31 2006.141.08:25:33.66/vb/07,04,usb,yes,31,31 2006.141.08:25:33.66/vb/08,04,usb,yes,28,32 2006.141.08:25:33.89/vblo/01,632.99,yes,locked 2006.141.08:25:33.89/vblo/02,640.99,yes,locked 2006.141.08:25:33.89/vblo/03,656.99,yes,locked 2006.141.08:25:33.89/vblo/04,712.99,yes,locked 2006.141.08:25:33.89/vblo/05,744.99,yes,locked 2006.141.08:25:33.89/vblo/06,752.99,yes,locked 2006.141.08:25:33.89/vblo/07,734.99,yes,locked 2006.141.08:25:33.89/vblo/08,744.99,yes,locked 2006.141.08:25:34.04/vabw/8 2006.141.08:25:34.19/vbbw/8 2006.141.08:25:34.28/xfe/off,on,15.2 2006.141.08:25:34.65/ifatt/23,28,28,28 2006.141.08:25:35.12/fmout-gps/S +1.05E-07 2006.141.08:25:35.20:!2006.141.08:26:30 2006.141.08:26:30.00:data_valid=off 2006.141.08:26:30.00:postob 2006.141.08:26:30.20/cable/+6.5265E-03 2006.141.08:26:30.20/wx/21.11,1013.1,73 2006.141.08:26:31.11/fmout-gps/S +1.04E-07 2006.141.08:26:31.11:scan_name=141-0827,k06141,60 2006.141.08:26:31.11:source=1739+522,174036.98,521143.4,2000.0,cw 2006.141.08:26:31.14#flagr#flagr/antenna,new-source 2006.141.08:26:32.14:checkk5 2006.141.08:26:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.141.08:26:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.141.08:26:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.141.08:26:33.66/chk_autoobs//k5ts4/ autoobs is running! 2006.141.08:26:34.03/chk_obsdata//k5ts1/T1410825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:26:34.40/chk_obsdata//k5ts2/T1410825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:26:34.78/chk_obsdata//k5ts3/T1410825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:26:35.15/chk_obsdata//k5ts4/T1410825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.141.08:26:35.84/k5log//k5ts1_log_newline 2006.141.08:26:36.53/k5log//k5ts2_log_newline 2006.141.08:26:37.23/k5log//k5ts3_log_newline 2006.141.08:26:37.92/k5log//k5ts4_log_newline 2006.141.08:26:37.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:26:37.95:4f8m12a=3 2006.141.08:26:37.95$4f8m12a/echo=on 2006.141.08:26:37.95$4f8m12a/pcalon 2006.141.08:26:37.95$pcalon/"no phase cal control is implemented here 2006.141.08:26:37.95$4f8m12a/"tpicd=stop 2006.141.08:26:37.95$4f8m12a/vc4f8 2006.141.08:26:37.95$vc4f8/valo=1,532.99 2006.141.08:26:37.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:26:37.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:26:37.95#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:37.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:37.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:37.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.141.08:26:38.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:38.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:38.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:26:38.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:26:38.02$vc4f8/va=1,8 2006.141.08:26:38.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:26:38.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:26:38.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:38.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:38.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:38.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:38.04#ibcon#[25=AT01-08\r\n] 2006.141.08:26:38.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:38.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:38.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:26:38.08#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:38.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:38.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:38.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:38.22#ibcon#[25=USB\r\n] 2006.141.08:26:38.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:38.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:38.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:26:38.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:26:38.25$vc4f8/valo=2,572.99 2006.141.08:26:38.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:26:38.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:26:38.25#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:38.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:38.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:38.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:38.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.141.08:26:38.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:38.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:38.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:26:38.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:26:38.33$vc4f8/va=2,7 2006.141.08:26:38.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:26:38.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:26:38.33#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:38.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:38.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:38.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:38.39#ibcon#[25=AT02-07\r\n] 2006.141.08:26:38.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:38.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:38.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:26:38.42#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:38.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:38.45#abcon#<5=/05 4.3 7.2 21.11 731013.1\r\n> 2006.141.08:26:38.47#abcon#{5=INTERFACE CLEAR} 2006.141.08:26:38.53#abcon#[5=S1D000X0/0*\r\n] 2006.141.08:26:38.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:38.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:38.59#ibcon#[25=USB\r\n] 2006.141.08:26:38.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:38.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:38.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:26:38.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:26:38.62$vc4f8/valo=3,672.99 2006.141.08:26:38.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:26:38.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:26:38.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:38.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:38.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:38.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.141.08:26:38.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:38.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:38.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:26:38.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:26:38.70$vc4f8/va=3,6 2006.141.08:26:38.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:26:38.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:26:38.70#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:38.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:38.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:38.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:38.76#ibcon#[25=AT03-06\r\n] 2006.141.08:26:38.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:38.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:38.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:26:38.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:38.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:38.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:38.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:38.93#ibcon#[25=USB\r\n] 2006.141.08:26:38.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:38.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:38.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:26:38.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:26:38.96$vc4f8/valo=4,832.99 2006.141.08:26:38.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:26:38.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:26:38.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:38.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:38.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:38.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:38.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.141.08:26:39.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:39.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:39.02#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:26:39.02#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:26:39.02$vc4f8/va=4,7 2006.141.08:26:39.02#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:26:39.02#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:26:39.02#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:39.02#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:39.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:39.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:39.10#ibcon#[25=AT04-07\r\n] 2006.141.08:26:39.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:39.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:39.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:26:39.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:39.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:39.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:39.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:39.27#ibcon#[25=USB\r\n] 2006.141.08:26:39.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:39.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:39.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:26:39.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:26:39.30$vc4f8/valo=5,652.99 2006.141.08:26:39.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:26:39.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:26:39.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:39.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:39.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:39.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:39.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.141.08:26:39.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:39.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:39.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:26:39.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:26:39.36$vc4f8/va=5,7 2006.141.08:26:39.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.08:26:39.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.08:26:39.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:39.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:39.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:39.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:39.44#ibcon#[25=AT05-07\r\n] 2006.141.08:26:39.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:39.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:39.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.08:26:39.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:39.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:39.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:39.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:39.61#ibcon#[25=USB\r\n] 2006.141.08:26:39.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:39.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:39.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:26:39.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:26:39.64$vc4f8/valo=6,772.99 2006.141.08:26:39.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:26:39.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:26:39.64#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:39.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:39.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:39.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:39.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.141.08:26:39.70#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:39.70#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:39.70#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:26:39.70#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:26:39.70$vc4f8/va=6,6 2006.141.08:26:39.70#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.141.08:26:39.70#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.141.08:26:39.70#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:39.70#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:39.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:39.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:39.78#ibcon#[25=AT06-06\r\n] 2006.141.08:26:39.81#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:39.81#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:39.81#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.141.08:26:39.81#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:39.81#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:26:39.93#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:26:39.93#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:26:39.95#ibcon#[25=USB\r\n] 2006.141.08:26:39.98#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:26:39.98#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.141.08:26:39.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:26:39.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:26:39.98$vc4f8/valo=7,832.99 2006.141.08:26:39.98#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.141.08:26:39.98#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.141.08:26:39.98#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:39.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:26:39.98#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:26:39.98#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:26:40.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.141.08:26:40.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:26:40.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.141.08:26:40.04#ibcon#about to clear, iclass 13 cls_cnt 0 2006.141.08:26:40.04#ibcon#cleared, iclass 13 cls_cnt 0 2006.141.08:26:40.04$vc4f8/va=7,6 2006.141.08:26:40.04#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.141.08:26:40.04#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.141.08:26:40.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:40.04#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:26:40.10#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:26:40.10#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:26:40.12#ibcon#[25=AT07-06\r\n] 2006.141.08:26:40.15#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:26:40.15#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.141.08:26:40.15#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.141.08:26:40.15#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:40.15#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:26:40.27#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:26:40.27#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:26:40.29#ibcon#[25=USB\r\n] 2006.141.08:26:40.32#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:26:40.32#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.141.08:26:40.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.141.08:26:40.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.141.08:26:40.32$vc4f8/valo=8,852.99 2006.141.08:26:40.32#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.141.08:26:40.32#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.141.08:26:40.32#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:40.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:26:40.32#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:26:40.32#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:26:40.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.141.08:26:40.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:26:40.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.141.08:26:40.38#ibcon#about to clear, iclass 17 cls_cnt 0 2006.141.08:26:40.38#ibcon#cleared, iclass 17 cls_cnt 0 2006.141.08:26:40.38$vc4f8/va=8,6 2006.141.08:26:40.38#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.141.08:26:40.38#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.141.08:26:40.38#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:40.38#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:26:40.44#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:26:40.44#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:26:40.46#ibcon#[25=AT08-06\r\n] 2006.141.08:26:40.49#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:26:40.49#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.141.08:26:40.49#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.141.08:26:40.49#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:40.49#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:26:40.61#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:26:40.61#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:26:40.63#ibcon#[25=USB\r\n] 2006.141.08:26:40.66#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:26:40.66#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.141.08:26:40.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.141.08:26:40.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.141.08:26:40.66$vc4f8/vblo=1,632.99 2006.141.08:26:40.66#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.141.08:26:40.66#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.141.08:26:40.66#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:40.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:40.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:40.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:40.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.141.08:26:40.72#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:40.72#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.141.08:26:40.72#ibcon#about to clear, iclass 21 cls_cnt 0 2006.141.08:26:40.72#ibcon#cleared, iclass 21 cls_cnt 0 2006.141.08:26:40.72$vc4f8/vb=1,4 2006.141.08:26:40.72#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.141.08:26:40.72#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.141.08:26:40.72#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:40.72#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:40.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:40.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:40.74#ibcon#[27=AT01-04\r\n] 2006.141.08:26:40.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:40.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.141.08:26:40.77#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.141.08:26:40.77#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:40.77#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:40.89#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:40.89#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:40.91#ibcon#[27=USB\r\n] 2006.141.08:26:40.94#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:40.94#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.141.08:26:40.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.141.08:26:40.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.141.08:26:40.94$vc4f8/vblo=2,640.99 2006.141.08:26:40.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.141.08:26:40.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.141.08:26:40.94#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:40.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:40.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:40.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:40.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.141.08:26:41.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:41.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.141.08:26:41.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.141.08:26:41.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.141.08:26:41.00$vc4f8/vb=2,4 2006.141.08:26:41.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.141.08:26:41.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.141.08:26:41.00#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:41.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:41.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:41.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:41.08#ibcon#[27=AT02-04\r\n] 2006.141.08:26:41.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:41.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.141.08:26:41.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.141.08:26:41.11#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:41.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:41.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:41.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:41.25#ibcon#[27=USB\r\n] 2006.141.08:26:41.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:41.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.141.08:26:41.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.141.08:26:41.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.141.08:26:41.28$vc4f8/vblo=3,656.99 2006.141.08:26:41.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.141.08:26:41.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.141.08:26:41.28#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:41.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:26:41.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:26:41.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:26:41.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.141.08:26:41.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:26:41.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.141.08:26:41.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.141.08:26:41.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.141.08:26:41.34$vc4f8/vb=3,4 2006.141.08:26:41.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.141.08:26:41.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.141.08:26:41.34#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:41.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:26:41.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:26:41.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:26:41.42#ibcon#[27=AT03-04\r\n] 2006.141.08:26:41.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:26:41.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.141.08:26:41.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.141.08:26:41.45#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:41.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:26:41.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:26:41.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:26:41.59#ibcon#[27=USB\r\n] 2006.141.08:26:41.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:26:41.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.141.08:26:41.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.141.08:26:41.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.141.08:26:41.62$vc4f8/vblo=4,712.99 2006.141.08:26:41.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.141.08:26:41.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.141.08:26:41.62#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:41.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:41.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:41.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:41.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.141.08:26:41.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:41.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.141.08:26:41.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.141.08:26:41.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.141.08:26:41.68$vc4f8/vb=4,4 2006.141.08:26:41.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.141.08:26:41.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.141.08:26:41.68#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:41.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:41.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:41.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:41.76#ibcon#[27=AT04-04\r\n] 2006.141.08:26:41.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:41.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.141.08:26:41.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.141.08:26:41.79#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:41.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:41.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:41.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:41.93#ibcon#[27=USB\r\n] 2006.141.08:26:41.96#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:41.96#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.141.08:26:41.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.141.08:26:41.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.141.08:26:41.96$vc4f8/vblo=5,744.99 2006.141.08:26:41.96#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.141.08:26:41.96#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.141.08:26:41.96#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:41.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:41.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:41.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:42.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.141.08:26:42.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:42.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.141.08:26:42.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.141.08:26:42.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.141.08:26:42.04$vc4f8/vb=5,4 2006.141.08:26:42.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.141.08:26:42.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.141.08:26:42.04#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:42.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:42.08#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:42.08#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:42.10#ibcon#[27=AT05-04\r\n] 2006.141.08:26:42.13#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:42.13#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.141.08:26:42.13#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.141.08:26:42.13#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:42.13#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:42.25#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:42.25#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:42.27#ibcon#[27=USB\r\n] 2006.141.08:26:42.30#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:42.30#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.141.08:26:42.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.141.08:26:42.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.141.08:26:42.30$vc4f8/vblo=6,752.99 2006.141.08:26:42.30#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.141.08:26:42.30#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.141.08:26:42.30#ibcon#ireg 17 cls_cnt 0 2006.141.08:26:42.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:42.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:42.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:42.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.141.08:26:42.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:42.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.141.08:26:42.36#ibcon#about to clear, iclass 3 cls_cnt 0 2006.141.08:26:42.36#ibcon#cleared, iclass 3 cls_cnt 0 2006.141.08:26:42.36$vc4f8/vb=6,4 2006.141.08:26:42.36#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.141.08:26:42.36#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.141.08:26:42.36#ibcon#ireg 11 cls_cnt 2 2006.141.08:26:42.36#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:42.42#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:42.42#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:42.44#ibcon#[27=AT06-04\r\n] 2006.141.08:26:42.47#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:42.47#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.141.08:26:42.47#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.141.08:26:42.47#ibcon#ireg 7 cls_cnt 0 2006.141.08:26:42.47#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:42.59#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:42.59#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:42.61#ibcon#[27=USB\r\n] 2006.141.08:26:42.64#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:42.64#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.141.08:26:42.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.141.08:26:42.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.141.08:26:42.64$vc4f8/vabw=wide 2006.141.08:26:42.64#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.141.08:26:42.64#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.141.08:26:42.64#ibcon#ireg 8 cls_cnt 0 2006.141.08:26:42.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:42.64#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:42.64#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:42.66#ibcon#[25=BW32\r\n] 2006.141.08:26:42.69#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:42.69#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.141.08:26:42.69#ibcon#about to clear, iclass 7 cls_cnt 0 2006.141.08:26:42.69#ibcon#cleared, iclass 7 cls_cnt 0 2006.141.08:26:42.69$vc4f8/vbbw=wide 2006.141.08:26:42.69#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.141.08:26:42.69#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.141.08:26:42.69#ibcon#ireg 8 cls_cnt 0 2006.141.08:26:42.69#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:26:42.76#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:26:42.76#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:26:42.79#ibcon#[27=BW32\r\n] 2006.141.08:26:42.82#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:26:42.82#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.141.08:26:42.82#ibcon#about to clear, iclass 11 cls_cnt 0 2006.141.08:26:42.82#ibcon#cleared, iclass 11 cls_cnt 0 2006.141.08:26:42.82$4f8m12a/ifd4f 2006.141.08:26:42.82$ifd4f/lo= 2006.141.08:26:42.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.141.08:26:42.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.141.08:26:42.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.141.08:26:42.82$ifd4f/patch= 2006.141.08:26:42.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.141.08:26:42.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.141.08:26:42.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.141.08:26:42.82$4f8m12a/"form=m,16.000,1:2 2006.141.08:26:42.82$4f8m12a/"tpicd 2006.141.08:26:42.82$4f8m12a/echo=off 2006.141.08:26:42.82$4f8m12a/xlog=off 2006.141.08:26:42.82:!2006.141.08:27:10 2006.141.08:26:49.14#trakl#Source acquired 2006.141.08:26:49.14#flagr#flagr/antenna,acquired 2006.141.08:27:10.00:preob 2006.141.08:27:11.14/onsource/TRACKING 2006.141.08:27:11.14:!2006.141.08:27:20 2006.141.08:27:20.00:data_valid=on 2006.141.08:27:20.00:midob 2006.141.08:27:20.13/onsource/TRACKING 2006.141.08:27:20.13/wx/21.11,1013.1,73 2006.141.08:27:20.29/cable/+6.5240E-03 2006.141.08:27:21.38/va/01,08,usb,yes,32,34 2006.141.08:27:21.38/va/02,07,usb,yes,32,34 2006.141.08:27:21.38/va/03,06,usb,yes,34,34 2006.141.08:27:21.38/va/04,07,usb,yes,33,35 2006.141.08:27:21.38/va/05,07,usb,yes,32,34 2006.141.08:27:21.38/va/06,06,usb,yes,31,31 2006.141.08:27:21.38/va/07,06,usb,yes,32,31 2006.141.08:27:21.38/va/08,06,usb,yes,34,33 2006.141.08:27:21.61/valo/01,532.99,yes,locked 2006.141.08:27:21.61/valo/02,572.99,yes,locked 2006.141.08:27:21.61/valo/03,672.99,yes,locked 2006.141.08:27:21.61/valo/04,832.99,yes,locked 2006.141.08:27:21.61/valo/05,652.99,yes,locked 2006.141.08:27:21.61/valo/06,772.99,yes,locked 2006.141.08:27:21.61/valo/07,832.99,yes,locked 2006.141.08:27:21.61/valo/08,852.99,yes,locked 2006.141.08:27:22.70/vb/01,04,usb,yes,32,30 2006.141.08:27:22.70/vb/02,04,usb,yes,33,35 2006.141.08:27:22.70/vb/03,04,usb,yes,29,33 2006.141.08:27:22.70/vb/04,04,usb,yes,30,31 2006.141.08:27:22.70/vb/05,04,usb,yes,29,33 2006.141.08:27:22.70/vb/06,04,usb,yes,30,33 2006.141.08:27:22.70/vb/07,04,usb,yes,32,32 2006.141.08:27:22.70/vb/08,04,usb,yes,29,33 2006.141.08:27:22.94/vblo/01,632.99,yes,locked 2006.141.08:27:22.94/vblo/02,640.99,yes,locked 2006.141.08:27:22.94/vblo/03,656.99,yes,locked 2006.141.08:27:22.94/vblo/04,712.99,yes,locked 2006.141.08:27:22.94/vblo/05,744.99,yes,locked 2006.141.08:27:22.94/vblo/06,752.99,yes,locked 2006.141.08:27:22.94/vblo/07,734.99,yes,locked 2006.141.08:27:22.94/vblo/08,744.99,yes,locked 2006.141.08:27:23.09/vabw/8 2006.141.08:27:23.24/vbbw/8 2006.141.08:27:23.33/xfe/off,on,15.2 2006.141.08:27:23.72/ifatt/23,28,28,28 2006.141.08:27:24.12/fmout-gps/S +1.05E-07 2006.141.08:27:24.16:!2006.141.08:28:20 2006.141.08:28:20.00:data_valid=off 2006.141.08:28:20.00:postob 2006.141.08:28:20.21/cable/+6.5237E-03 2006.141.08:28:20.21/wx/21.11,1013.1,73 2006.141.08:28:21.12/fmout-gps/S +1.04E-07 2006.141.08:28:21.12:checkk5last 2006.141.08:28:21.12&checkk5last/chk_obsdata=1 2006.141.08:28:21.13&checkk5last/chk_obsdata=2 2006.141.08:28:21.13&checkk5last/chk_obsdata=3 2006.141.08:28:21.14&checkk5last/chk_obsdata=4 2006.141.08:28:21.14&checkk5last/k5log=1 2006.141.08:28:21.14&checkk5last/k5log=2 2006.141.08:28:21.15&checkk5last/k5log=3 2006.141.08:28:21.15&checkk5last/k5log=4 2006.141.08:28:21.20&checkk5last/obsinfo 2006.141.08:28:21.57/chk_obsdata//k5ts1/T1410827??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:28:21.95/chk_obsdata//k5ts2/T1410827??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:28:22.32/chk_obsdata//k5ts3/T1410827??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:28:22.70/chk_obsdata//k5ts4/T1410827??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.141.08:28:23.40/k5log//k5ts1_log_newline 2006.141.08:28:24.09/k5log//k5ts2_log_newline 2006.141.08:28:24.84/k5log//k5ts3_log_newline 2006.141.08:28:25.54/k5log//k5ts4_log_newline 2006.141.08:28:25.56/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.141.08:28:25.56:sched_end 2006.141.08:28:25.56&sched_end/stopcheck 2006.141.08:28:25.56&stopcheck/sy=killall check_fsrun.pl 2006.141.08:28:25.56&stopcheck/" sy=killall chmem.sh 2006.141.08:28:25.66:source=idle 2006.141.08:28:26.13#flagr#flagr/antenna,new-source 2006.141.08:28:26.13:stow 2006.141.08:28:26.13&stow/source=idle 2006.141.08:28:26.14&stow/"this is stow command. 2006.141.08:28:26.14&stow/antenna=m3 2006.141.08:28:30.01:!+10m 2006.141.08:38:30.02:standby 2006.141.08:38:30.02&standby/"this is standby command. 2006.141.08:38:30.02&standby/antenna=m0 2006.141.08:38:31.01:sy=cp /usr2/log/k06141ts.log /usr2/log_backup/ 2006.141.08:38:31.05:*end of schedule 2006.141.17:30:43.87?ERROR st -97 Trouble decoding pressure data 2006.141.17:30:43.87#wxget#04 1.9 3.5 17.10 871015.9