2006.139.21:40:07.04:Log Opened: Mark IV Field System Version 9.7.7 2006.139.21:40:07.04:location,TSUKUB32,-140.09,36.10,61.0 2006.139.21:40:07.04:horizon1,0.,5.,360. 2006.139.21:40:07.09:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.139.21:40:07.09:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.139.21:40:07.10:drivev11,330,270,no 2006.139.21:40:07.10:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.139.21:40:07.10:drivev13,15.000,268,10.000,10.000,10.000 2006.139.21:40:07.11:drivev21,330,270,no 2006.139.21:40:07.11:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.139.21:40:07.11:drivev23,15.000,268,10.000,10.000,10.000 2006.139.21:40:07.12:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.139.21:40:07.12:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.139.21:40:07.12:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.139.21:40:07.17:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.139.21:40:07.18:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.139.21:40:07.18:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.139.21:40:07.18:time,-0.364,101.533,rate 2006.139.21:40:07.19:flagr,200 2006.139.21:40:07.19:proc=k06140ts 2006.139.21:40:07.20:" k06140 2006 tsukub32 t ts 2006.139.21:40:07.20:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.139.21:40:07.20:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.139.21:40:07.21:" 108 tsukub32 14 17400 2006.139.21:40:07.21:" drudg version 050216 compiled under fs 9.7.07 2006.139.21:40:07.26:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.139.21:40:07.26:!2006.140.07:19:50 2006.140.07:19:50.00:unstow 2006.140.07:19:50.00&unstow/antenna=e 2006.140.07:19:50.00&unstow/!+10s 2006.140.07:19:50.00&unstow/antenna=m2 2006.140.07:20:02.01:scan_name=140-0730,k06140,60 2006.140.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.140.07:20:03.13#antcn#PM 1 00019 2005 228 00 22 31 00 2006.140.07:20:03.13#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.140.07:20:03.13#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.140.07:20:03.13#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.140.07:20:03.13#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.140.07:20:03.13#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.140.07:20:04.13:ready_k5 2006.140.07:20:04.13&ready_k5/obsinfo=st 2006.140.07:20:04.13&ready_k5/autoobs=1 2006.140.07:20:04.13&ready_k5/autoobs=2 2006.140.07:20:04.13&ready_k5/autoobs=3 2006.140.07:20:04.13&ready_k5/autoobs=4 2006.140.07:20:04.13&ready_k5/obsinfo 2006.140.07:20:04.13#flagr#flagr/antenna,new-source 2006.140.07:20:04.13/obsinfo=st/error_log.tmp was not found (or not removed). 2006.140.07:20:07.30/autoobs//k5ts1/ autoobs started! 2006.140.07:20:10.41/autoobs//k5ts2/ autoobs started! 2006.140.07:20:13.50/autoobs//k5ts3/ autoobs started! 2006.140.07:20:16.60/autoobs//k5ts4/ autoobs started! 2006.140.07:20:16.63/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:20:16.63:4f8m12a=1 2006.140.07:20:16.63&4f8m12a/xlog=on 2006.140.07:20:16.63&4f8m12a/echo=on 2006.140.07:20:16.63&4f8m12a/pcalon 2006.140.07:20:16.63&4f8m12a/"tpicd=stop 2006.140.07:20:16.63&4f8m12a/vc4f8 2006.140.07:20:16.63&4f8m12a/ifd4f 2006.140.07:20:16.63&4f8m12a/"form=m,16.000,1:2 2006.140.07:20:16.63&4f8m12a/"tpicd 2006.140.07:20:16.63&4f8m12a/echo=off 2006.140.07:20:16.63&4f8m12a/xlog=off 2006.140.07:20:16.63$4f8m12a/echo=on 2006.140.07:20:16.63$4f8m12a/pcalon 2006.140.07:20:16.63&pcalon/"no phase cal control is implemented here 2006.140.07:20:16.63$pcalon/"no phase cal control is implemented here 2006.140.07:20:16.63$4f8m12a/"tpicd=stop 2006.140.07:20:16.63$4f8m12a/vc4f8 2006.140.07:20:16.63&vc4f8/valo=1,532.99 2006.140.07:20:16.63&vc4f8/va=1,8 2006.140.07:20:16.63&vc4f8/valo=2,572.99 2006.140.07:20:16.63&vc4f8/va=2,7 2006.140.07:20:16.63&vc4f8/valo=3,672.99 2006.140.07:20:16.63&vc4f8/va=3,6 2006.140.07:20:16.63&vc4f8/valo=4,832.99 2006.140.07:20:16.63&vc4f8/va=4,7 2006.140.07:20:16.63&vc4f8/valo=5,652.99 2006.140.07:20:16.63&vc4f8/va=5,7 2006.140.07:20:16.63&vc4f8/valo=6,772.99 2006.140.07:20:16.63&vc4f8/va=6,6 2006.140.07:20:16.63&vc4f8/valo=7,832.99 2006.140.07:20:16.63&vc4f8/va=7,6 2006.140.07:20:16.63&vc4f8/valo=8,852.99 2006.140.07:20:16.63&vc4f8/va=8,6 2006.140.07:20:16.63&vc4f8/vblo=1,632.99 2006.140.07:20:16.63&vc4f8/vb=1,4 2006.140.07:20:16.63&vc4f8/vblo=2,640.99 2006.140.07:20:16.63&vc4f8/vb=2,4 2006.140.07:20:16.63&vc4f8/vblo=3,656.99 2006.140.07:20:16.63&vc4f8/vb=3,4 2006.140.07:20:16.63&vc4f8/vblo=4,712.99 2006.140.07:20:16.63&vc4f8/vb=4,4 2006.140.07:20:16.63&vc4f8/vblo=5,744.99 2006.140.07:20:16.63&vc4f8/vb=5,4 2006.140.07:20:16.63&vc4f8/vblo=6,752.99 2006.140.07:20:16.63&vc4f8/vb=6,4 2006.140.07:20:16.63&vc4f8/vabw=wide 2006.140.07:20:16.63&vc4f8/vbbw=wide 2006.140.07:20:16.63$vc4f8/valo=1,532.99 2006.140.07:20:16.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:20:16.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:20:16.64#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:16.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:16.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:16.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:16.68#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:20:16.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:16.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:16.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:20:16.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:20:16.73$vc4f8/va=1,8 2006.140.07:20:16.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:20:16.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:20:16.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:16.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:16.73#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:16.73#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:16.75#ibcon#[25=AT01-08\r\n] 2006.140.07:20:16.79#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:16.79#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:16.79#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:20:16.79#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:16.79#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:16.91#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:16.91#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:16.93#ibcon#[25=USB\r\n] 2006.140.07:20:16.96#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:16.96#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:16.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:20:16.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:20:16.96$vc4f8/valo=2,572.99 2006.140.07:20:16.96#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:20:16.96#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:20:16.96#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:16.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:16.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:16.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:16.99#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:20:17.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:17.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:17.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:20:17.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:20:17.04$vc4f8/va=2,7 2006.140.07:20:17.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:20:17.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:20:17.04#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:17.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:17.08#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:17.08#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:17.10#ibcon#[25=AT02-07\r\n] 2006.140.07:20:17.13#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:17.13#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:17.13#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:20:17.13#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:17.13#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:17.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:17.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:17.28#ibcon#[25=USB\r\n] 2006.140.07:20:17.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:17.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:17.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:20:17.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:20:17.31$vc4f8/valo=3,672.99 2006.140.07:20:17.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:20:17.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:20:17.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:17.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:17.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:17.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:17.34#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:20:17.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:17.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:17.39#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:20:17.39#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:20:17.39$vc4f8/va=3,6 2006.140.07:20:17.39#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:20:17.39#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:20:17.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:17.39#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:17.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:17.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:17.45#ibcon#[25=AT03-06\r\n] 2006.140.07:20:17.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:17.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:17.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:20:17.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:17.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:17.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:17.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:17.62#ibcon#[25=USB\r\n] 2006.140.07:20:17.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:17.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:17.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:20:17.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:20:17.65$vc4f8/valo=4,832.99 2006.140.07:20:17.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:20:17.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:20:17.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:17.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:17.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:17.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:17.67#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:20:17.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:17.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:17.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:20:17.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:20:17.71$vc4f8/va=4,7 2006.140.07:20:17.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:20:17.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:20:17.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:17.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:17.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:17.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:17.79#ibcon#[25=AT04-07\r\n] 2006.140.07:20:17.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:17.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:17.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:20:17.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:17.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:17.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:17.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:17.96#ibcon#[25=USB\r\n] 2006.140.07:20:17.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:17.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:17.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:20:17.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:20:17.99$vc4f8/valo=5,652.99 2006.140.07:20:17.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:20:17.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:20:17.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:17.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:17.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:17.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:18.01#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:20:18.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:18.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:18.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:20:18.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:20:18.05$vc4f8/va=5,7 2006.140.07:20:18.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:20:18.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:20:18.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:18.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:18.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:18.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:18.13#ibcon#[25=AT05-07\r\n] 2006.140.07:20:18.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:18.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:18.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:20:18.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:18.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:18.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:18.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:18.30#ibcon#[25=USB\r\n] 2006.140.07:20:18.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:18.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:18.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:20:18.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:20:18.33$vc4f8/valo=6,772.99 2006.140.07:20:18.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:20:18.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:20:18.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:18.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:18.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:18.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:18.35#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:20:18.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:18.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:18.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:20:18.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:20:18.39$vc4f8/va=6,6 2006.140.07:20:18.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.07:20:18.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.07:20:18.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:18.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:18.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:18.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:18.47#ibcon#[25=AT06-06\r\n] 2006.140.07:20:18.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:18.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:18.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.07:20:18.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:18.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:20:18.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:20:18.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:20:18.64#ibcon#[25=USB\r\n] 2006.140.07:20:18.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:20:18.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:20:18.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:20:18.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:20:18.67$vc4f8/valo=7,832.99 2006.140.07:20:18.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.07:20:18.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.07:20:18.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:18.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:20:18.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:20:18.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:20:18.69#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:20:18.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:20:18.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:20:18.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:20:18.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:20:18.73$vc4f8/va=7,6 2006.140.07:20:18.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.07:20:18.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.07:20:18.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:18.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:20:18.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:20:18.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:20:18.81#ibcon#[25=AT07-06\r\n] 2006.140.07:20:18.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:20:18.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:20:18.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.07:20:18.84#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:18.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:20:18.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:20:18.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:20:18.98#ibcon#[25=USB\r\n] 2006.140.07:20:19.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:20:19.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:20:19.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:20:19.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:20:19.01$vc4f8/valo=8,852.99 2006.140.07:20:19.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:20:19.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:20:19.01#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:19.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:20:19.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:20:19.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:20:19.03#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:20:19.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:20:19.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:20:19.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:20:19.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:20:19.07$vc4f8/va=8,6 2006.140.07:20:19.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.07:20:19.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.07:20:19.07#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:19.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:20:19.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:20:19.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:20:19.15#ibcon#[25=AT08-06\r\n] 2006.140.07:20:19.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:20:19.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:20:19.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.07:20:19.18#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:19.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:20:19.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:20:19.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:20:19.32#ibcon#[25=USB\r\n] 2006.140.07:20:19.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:20:19.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:20:19.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:20:19.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:20:19.35$vc4f8/vblo=1,632.99 2006.140.07:20:19.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:20:19.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:20:19.35#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:19.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:20:19.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:20:19.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:20:19.37#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:20:19.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:20:19.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:20:19.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:20:19.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:20:19.41$vc4f8/vb=1,4 2006.140.07:20:19.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:20:19.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:20:19.41#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:19.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:20:19.41#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:20:19.41#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:20:19.43#ibcon#[27=AT01-04\r\n] 2006.140.07:20:19.46#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:20:19.46#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:20:19.46#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:20:19.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:19.46#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:20:19.58#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:20:19.58#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:20:19.60#ibcon#[27=USB\r\n] 2006.140.07:20:19.63#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:20:19.63#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:20:19.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:20:19.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:20:19.63$vc4f8/vblo=2,640.99 2006.140.07:20:19.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:20:19.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:20:19.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:19.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:19.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:19.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:19.65#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:20:19.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:19.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:20:19.69#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:20:19.69#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:20:19.69$vc4f8/vb=2,4 2006.140.07:20:19.69#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:20:19.69#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:20:19.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:19.69#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:19.75#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:19.75#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:19.77#ibcon#[27=AT02-04\r\n] 2006.140.07:20:19.80#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:19.80#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:20:19.80#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:20:19.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:19.80#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:19.92#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:19.92#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:19.94#ibcon#[27=USB\r\n] 2006.140.07:20:19.97#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:19.97#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:20:19.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:20:19.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:20:19.97$vc4f8/vblo=3,656.99 2006.140.07:20:19.97#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:20:19.97#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:20:19.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:19.97#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:19.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:19.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:19.99#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:20:20.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:20.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:20:20.03#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:20:20.03#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:20:20.03$vc4f8/vb=3,4 2006.140.07:20:20.03#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:20:20.03#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:20:20.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:20.03#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:20.09#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:20.09#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:20.11#ibcon#[27=AT03-04\r\n] 2006.140.07:20:20.14#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:20.14#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:20:20.14#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:20:20.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:20.14#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:20.26#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:20.26#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:20.28#ibcon#[27=USB\r\n] 2006.140.07:20:20.31#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:20.31#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:20:20.31#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:20:20.31#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:20:20.31$vc4f8/vblo=4,712.99 2006.140.07:20:20.31#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:20:20.31#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:20:20.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:20.31#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:20.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:20.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:20.33#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:20:20.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:20.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:20:20.37#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:20:20.37#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:20:20.37$vc4f8/vb=4,4 2006.140.07:20:20.37#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:20:20.37#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:20:20.37#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:20.37#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:20.43#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:20.43#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:20.45#ibcon#[27=AT04-04\r\n] 2006.140.07:20:20.48#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:20.48#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:20:20.48#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:20:20.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:20.48#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:20.60#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:20.60#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:20.62#ibcon#[27=USB\r\n] 2006.140.07:20:20.65#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:20.65#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:20:20.65#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:20:20.65#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:20:20.65$vc4f8/vblo=5,744.99 2006.140.07:20:20.65#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:20:20.65#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:20:20.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:20.65#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:20.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:20.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:20.67#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:20:20.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:20.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:20:20.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:20:20.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:20:20.71$vc4f8/vb=5,4 2006.140.07:20:20.71#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:20:20.71#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:20:20.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:20.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:20.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:20.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:20.79#ibcon#[27=AT05-04\r\n] 2006.140.07:20:20.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:20.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:20:20.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:20:20.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:20.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:20.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:20.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:20.96#ibcon#[27=USB\r\n] 2006.140.07:20:20.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:20.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:20:20.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:20:20.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:20:20.99$vc4f8/vblo=6,752.99 2006.140.07:20:20.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:20:20.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:20:20.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:20:20.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:20.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:20.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:21.01#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:20:21.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:21.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:20:21.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:20:21.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:20:21.05$vc4f8/vb=6,4 2006.140.07:20:21.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:20:21.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:20:21.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:20:21.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:21.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:21.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:21.13#ibcon#[27=AT06-04\r\n] 2006.140.07:20:21.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:21.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:20:21.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:20:21.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:20:21.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:21.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:21.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:21.30#ibcon#[27=USB\r\n] 2006.140.07:20:21.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:21.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:20:21.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:20:21.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:20:21.33$vc4f8/vabw=wide 2006.140.07:20:21.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:20:21.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:20:21.33#ibcon#ireg 8 cls_cnt 0 2006.140.07:20:21.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:21.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:21.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:21.35#ibcon#[25=BW32\r\n] 2006.140.07:20:21.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:21.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:20:21.38#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:20:21.38#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:20:21.38$vc4f8/vbbw=wide 2006.140.07:20:21.38#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:20:21.38#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:20:21.38#ibcon#ireg 8 cls_cnt 0 2006.140.07:20:21.38#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:20:21.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:20:21.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:20:21.47#ibcon#[27=BW32\r\n] 2006.140.07:20:21.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:20:21.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:20:21.50#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:20:21.50#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:20:21.50$4f8m12a/ifd4f 2006.140.07:20:21.50&ifd4f/lo= 2006.140.07:20:21.50&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:20:21.50&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:20:21.50&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:20:21.50&ifd4f/patch= 2006.140.07:20:21.50&ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:20:21.50&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:20:21.50&ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:20:21.50$ifd4f/lo= 2006.140.07:20:21.50$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:20:21.50$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:20:21.50$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:20:21.50$ifd4f/patch= 2006.140.07:20:21.50$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:20:21.50$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:20:21.50$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:20:21.50$4f8m12a/"form=m,16.000,1:2 2006.140.07:20:21.50$4f8m12a/"tpicd 2006.140.07:20:21.50$4f8m12a/echo=off 2006.140.07:20:21.50$4f8m12a/xlog=off 2006.140.07:20:21.50:!2006.140.07:29:50 2006.140.07:20:42.13#trakl#Source acquired 2006.140.07:20:44.13#flagr#flagr/antenna,acquired 2006.140.07:29:13.13#trakl#Off source 2006.140.07:29:13.13?ERROR st -7 Antenna off-source! 2006.140.07:29:13.13#trakl#az 13.165 el 19.564 azerr*cos(el) 0.0190 elerr -0.0007 2006.140.07:29:14.13#flagr#flagr/antenna,off-source 2006.140.07:29:19.13#trakl#Source re-acquired 2006.140.07:29:20.13#flagr#flagr/antenna,re-acquired 2006.140.07:29:50.00:preob 2006.140.07:29:50.00&preob/onsource 2006.140.07:29:51.13/onsource/TRACKING 2006.140.07:29:51.13:!2006.140.07:30:00 2006.140.07:30:00.00:data_valid=on 2006.140.07:30:00.00:midob 2006.140.07:30:00.00&midob/onsource 2006.140.07:30:00.00&midob/wx 2006.140.07:30:00.00&midob/cable 2006.140.07:30:00.00&midob/va 2006.140.07:30:00.00&midob/valo 2006.140.07:30:00.00&midob/vb 2006.140.07:30:00.00&midob/vblo 2006.140.07:30:00.00&midob/vabw 2006.140.07:30:00.00&midob/vbbw 2006.140.07:30:00.00&midob/"form 2006.140.07:30:00.00&midob/xfe 2006.140.07:30:00.00&midob/ifatt 2006.140.07:30:00.00&midob/clockoff 2006.140.07:30:00.00&midob/sy=logmail 2006.140.07:30:00.00&midob/"sy=run setcl adapt & 2006.140.07:30:00.13/onsource/TRACKING 2006.140.07:30:00.13/wx/24.65,993.2,83 2006.140.07:30:00.31/cable/+6.4987E-03 2006.140.07:30:01.40/va/01,08,usb,yes,34,36 2006.140.07:30:01.40/va/02,07,usb,yes,34,36 2006.140.07:30:01.40/va/03,06,usb,yes,36,37 2006.140.07:30:01.40/va/04,07,usb,yes,35,38 2006.140.07:30:01.40/va/05,07,usb,yes,35,37 2006.140.07:30:01.40/va/06,06,usb,yes,34,33 2006.140.07:30:01.40/va/07,06,usb,yes,34,34 2006.140.07:30:01.40/va/08,06,usb,yes,36,36 2006.140.07:30:01.63/valo/01,532.99,yes,locked 2006.140.07:30:01.63/valo/02,572.99,yes,locked 2006.140.07:30:01.63/valo/03,672.99,yes,locked 2006.140.07:30:01.63/valo/04,832.99,yes,locked 2006.140.07:30:01.63/valo/05,652.99,yes,locked 2006.140.07:30:01.63/valo/06,772.99,yes,locked 2006.140.07:30:01.63/valo/07,832.99,yes,locked 2006.140.07:30:01.63/valo/08,852.99,yes,locked 2006.140.07:30:02.72/vb/01,04,usb,yes,30,51 2006.140.07:30:02.72/vb/02,04,usb,yes,31,51 2006.140.07:30:02.72/vb/03,04,usb,yes,28,33 2006.140.07:30:02.72/vb/04,04,usb,yes,29,29 2006.140.07:30:02.72/vb/05,04,usb,yes,28,32 2006.140.07:30:02.72/vb/06,04,usb,yes,29,32 2006.140.07:30:02.72/vb/07,04,usb,yes,30,30 2006.140.07:30:02.72/vb/08,04,usb,yes,28,31 2006.140.07:30:02.95/vblo/01,632.99,yes,locked 2006.140.07:30:02.95/vblo/02,640.99,yes,locked 2006.140.07:30:02.95/vblo/03,656.99,yes,locked 2006.140.07:30:02.95/vblo/04,712.99,yes,locked 2006.140.07:30:02.95/vblo/05,744.99,yes,locked 2006.140.07:30:02.95/vblo/06,752.99,yes,locked 2006.140.07:30:02.95/vblo/07,734.99,yes,locked 2006.140.07:30:02.95/vblo/08,744.99,yes,locked 2006.140.07:30:03.10/vabw/8 2006.140.07:30:03.25/vbbw/8 2006.140.07:30:03.34/xfe/off,on,14.7 2006.140.07:30:03.71/ifatt/23,28,28,28 2006.140.07:30:03.71&clockoff/"gps-fmout=1p 2006.140.07:30:03.71&clockoff/fmout-gps=1p 2006.140.07:30:04.10/fmout-gps/S +1.09E-07 2006.140.07:30:04.18:!2006.140.07:31:00 2006.140.07:31:00.00:data_valid=off 2006.140.07:31:00.00:postob 2006.140.07:31:00.00&postob/cable 2006.140.07:31:00.01&postob/wx 2006.140.07:31:00.01&postob/clockoff 2006.140.07:31:00.20/cable/+6.4972E-03 2006.140.07:31:00.20/wx/24.62,993.1,83 2006.140.07:31:01.10/fmout-gps/S +1.08E-07 2006.140.07:31:01.10:scan_name=140-0733,k06140,60 2006.140.07:31:01.10:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.140.07:31:01.14#flagr#flagr/antenna,new-source 2006.140.07:31:02.14:checkk5 2006.140.07:31:02.14&checkk5/chk_autoobs=1 2006.140.07:31:02.14&checkk5/chk_autoobs=2 2006.140.07:31:02.15&checkk5/chk_autoobs=3 2006.140.07:31:02.15&checkk5/chk_autoobs=4 2006.140.07:31:02.15&checkk5/chk_obsdata=1 2006.140.07:31:02.16&checkk5/chk_obsdata=2 2006.140.07:31:02.16&checkk5/chk_obsdata=3 2006.140.07:31:02.17&checkk5/chk_obsdata=4 2006.140.07:31:02.17&checkk5/k5log=1 2006.140.07:31:02.17&checkk5/k5log=2 2006.140.07:31:02.18&checkk5/k5log=3 2006.140.07:31:02.18&checkk5/k5log=4 2006.140.07:31:02.18&checkk5/obsinfo 2006.140.07:31:02.58/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:31:02.96/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:31:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:31:03.73/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:31:04.10/chk_obsdata//k5ts1/T1400730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:31:04.47/chk_obsdata//k5ts2/T1400730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:31:04.84/chk_obsdata//k5ts3/T1400730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:31:05.21/chk_obsdata//k5ts4/T1400730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:31:05.92/k5log//k5ts1_log_newline 2006.140.07:31:06.60/k5log//k5ts2_log_newline 2006.140.07:31:07.29/k5log//k5ts3_log_newline 2006.140.07:31:07.98/k5log//k5ts4_log_newline 2006.140.07:31:08.00/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:31:08.00:4f8m12a=1 2006.140.07:31:08.00$4f8m12a/echo=on 2006.140.07:31:08.00$4f8m12a/pcalon 2006.140.07:31:08.00$pcalon/"no phase cal control is implemented here 2006.140.07:31:08.00$4f8m12a/"tpicd=stop 2006.140.07:31:08.00$4f8m12a/vc4f8 2006.140.07:31:08.00$vc4f8/valo=1,532.99 2006.140.07:31:08.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:31:08.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:31:08.01#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:08.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:08.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:08.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:08.05#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:31:08.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:08.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:08.11#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:31:08.11#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:31:08.11$vc4f8/va=1,8 2006.140.07:31:08.11#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:31:08.11#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:31:08.11#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:08.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:08.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:08.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:08.14#ibcon#[25=AT01-08\r\n] 2006.140.07:31:08.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:08.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:08.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:31:08.18#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:08.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:08.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:08.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:08.32#ibcon#[25=USB\r\n] 2006.140.07:31:08.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:08.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:08.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:31:08.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:31:08.35$vc4f8/valo=2,572.99 2006.140.07:31:08.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:31:08.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:31:08.35#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:08.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:08.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:08.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:08.38#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:31:08.43#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:08.43#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:08.43#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:31:08.43#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:31:08.43$vc4f8/va=2,7 2006.140.07:31:08.43#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:31:08.43#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:31:08.43#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:08.43#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:08.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:08.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:08.49#ibcon#[25=AT02-07\r\n] 2006.140.07:31:08.52#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:08.52#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:08.52#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:31:08.52#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:08.52#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:08.64#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:08.64#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:08.66#ibcon#[25=USB\r\n] 2006.140.07:31:08.69#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:08.69#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:08.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:31:08.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:31:08.69$vc4f8/valo=3,672.99 2006.140.07:31:08.69#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:31:08.69#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:31:08.69#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:08.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:08.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:08.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:08.72#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:31:08.77#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:08.77#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:08.77#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:31:08.77#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:31:08.77$vc4f8/va=3,6 2006.140.07:31:08.77#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:31:08.77#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:31:08.77#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:08.77#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:08.81#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:08.81#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:08.83#ibcon#[25=AT03-06\r\n] 2006.140.07:31:08.86#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:08.86#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:08.86#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:31:08.86#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:08.86#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:08.98#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:08.98#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:09.00#ibcon#[25=USB\r\n] 2006.140.07:31:09.03#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:09.03#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:09.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:31:09.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:31:09.03$vc4f8/valo=4,832.99 2006.140.07:31:09.03#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:31:09.03#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:31:09.03#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:09.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:09.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:09.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:09.05#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:31:09.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:09.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:09.09#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:31:09.09#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:31:09.09$vc4f8/va=4,7 2006.140.07:31:09.09#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:31:09.09#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:31:09.09#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:09.09#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:09.15#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:09.15#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:09.17#ibcon#[25=AT04-07\r\n] 2006.140.07:31:09.20#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:09.20#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:09.20#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:31:09.20#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:09.20#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:09.32#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:09.32#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:09.34#ibcon#[25=USB\r\n] 2006.140.07:31:09.37#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:09.37#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:09.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:31:09.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:31:09.37$vc4f8/valo=5,652.99 2006.140.07:31:09.37#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:31:09.37#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:31:09.37#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:09.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:09.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:09.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:09.39#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:31:09.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:09.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:09.43#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:31:09.43#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:31:09.43$vc4f8/va=5,7 2006.140.07:31:09.43#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:31:09.43#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:31:09.43#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:09.43#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:09.49#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:09.49#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:09.51#ibcon#[25=AT05-07\r\n] 2006.140.07:31:09.54#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:09.54#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:09.54#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:31:09.54#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:09.54#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:09.66#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:09.66#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:09.68#ibcon#[25=USB\r\n] 2006.140.07:31:09.71#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:09.71#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:09.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:31:09.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:31:09.71$vc4f8/valo=6,772.99 2006.140.07:31:09.71#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:31:09.71#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:31:09.71#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:09.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:09.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:09.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:09.73#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:31:09.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:09.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:09.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:31:09.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:31:09.77$vc4f8/va=6,6 2006.140.07:31:09.77#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:31:09.77#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:31:09.77#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:09.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:09.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:09.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:09.85#ibcon#[25=AT06-06\r\n] 2006.140.07:31:09.88#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:09.88#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:09.88#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:31:09.88#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:09.88#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:31:10.00#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:31:10.00#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:31:10.02#ibcon#[25=USB\r\n] 2006.140.07:31:10.05#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:31:10.05#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:31:10.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:31:10.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:31:10.05$vc4f8/valo=7,832.99 2006.140.07:31:10.05#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:31:10.05#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:31:10.05#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:10.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:31:10.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:31:10.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:31:10.07#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:31:10.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:31:10.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:31:10.11#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:31:10.11#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:31:10.11$vc4f8/va=7,6 2006.140.07:31:10.11#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.07:31:10.11#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.07:31:10.11#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:10.11#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:31:10.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:31:10.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:31:10.19#ibcon#[25=AT07-06\r\n] 2006.140.07:31:10.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:31:10.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:31:10.22#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.07:31:10.22#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:10.22#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:31:10.34#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:31:10.34#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:31:10.36#ibcon#[25=USB\r\n] 2006.140.07:31:10.39#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:31:10.39#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:31:10.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:31:10.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:31:10.39$vc4f8/valo=8,852.99 2006.140.07:31:10.39#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.07:31:10.39#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.07:31:10.39#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:10.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:31:10.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:31:10.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:31:10.41#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:31:10.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:31:10.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:31:10.45#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:31:10.45#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:31:10.45$vc4f8/va=8,6 2006.140.07:31:10.45#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.07:31:10.45#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.07:31:10.45#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:10.45#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:31:10.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:31:10.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:31:10.53#ibcon#[25=AT08-06\r\n] 2006.140.07:31:10.56#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:31:10.56#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:31:10.56#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.07:31:10.56#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:10.56#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:31:10.68#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:31:10.68#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:31:10.70#ibcon#[25=USB\r\n] 2006.140.07:31:10.73#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:31:10.73#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:31:10.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:31:10.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:31:10.73$vc4f8/vblo=1,632.99 2006.140.07:31:10.73#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.07:31:10.73#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.07:31:10.73#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:10.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:31:10.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:31:10.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:31:10.75#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:31:10.79#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:31:10.79#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:31:10.79#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:31:10.79#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:31:10.79$vc4f8/vb=1,4 2006.140.07:31:10.79#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.07:31:10.79#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.07:31:10.79#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:10.79#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:31:10.79#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:31:10.79#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:31:10.81#ibcon#[27=AT01-04\r\n] 2006.140.07:31:10.84#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:31:10.84#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:31:10.84#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.07:31:10.84#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:10.84#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:31:10.96#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:31:10.96#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:31:10.98#ibcon#[27=USB\r\n] 2006.140.07:31:11.01#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:31:11.01#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:31:11.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:31:11.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:31:11.01$vc4f8/vblo=2,640.99 2006.140.07:31:11.01#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:31:11.01#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:31:11.01#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:11.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:11.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:11.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:11.03#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:31:11.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:11.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:31:11.07#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:31:11.07#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:31:11.07$vc4f8/vb=2,4 2006.140.07:31:11.07#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:31:11.07#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:31:11.07#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:11.07#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:11.13#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:11.13#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:11.15#ibcon#[27=AT02-04\r\n] 2006.140.07:31:11.18#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:11.18#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:31:11.18#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:31:11.18#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:11.18#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:11.30#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:11.30#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:11.32#ibcon#[27=USB\r\n] 2006.140.07:31:11.35#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:11.35#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:31:11.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:31:11.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:31:11.35$vc4f8/vblo=3,656.99 2006.140.07:31:11.35#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:31:11.35#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:31:11.35#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:11.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:11.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:11.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:11.37#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:31:11.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:11.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:31:11.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:31:11.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:31:11.41$vc4f8/vb=3,4 2006.140.07:31:11.41#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:31:11.41#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:31:11.41#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:11.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:11.47#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:11.47#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:11.49#ibcon#[27=AT03-04\r\n] 2006.140.07:31:11.53#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:11.53#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:31:11.53#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:31:11.53#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:11.53#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:11.65#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:11.65#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:11.67#ibcon#[27=USB\r\n] 2006.140.07:31:11.70#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:11.70#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:31:11.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:31:11.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:31:11.70$vc4f8/vblo=4,712.99 2006.140.07:31:11.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:31:11.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:31:11.70#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:11.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:11.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:11.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:11.72#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:31:11.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:11.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:31:11.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:31:11.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:31:11.76$vc4f8/vb=4,4 2006.140.07:31:11.76#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:31:11.76#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:31:11.76#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:11.76#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:11.82#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:11.82#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:11.84#ibcon#[27=AT04-04\r\n] 2006.140.07:31:11.87#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:11.87#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:31:11.87#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:31:11.87#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:11.87#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:11.99#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:11.99#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:12.01#ibcon#[27=USB\r\n] 2006.140.07:31:12.04#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:12.04#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:31:12.04#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:31:12.04#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:31:12.04$vc4f8/vblo=5,744.99 2006.140.07:31:12.04#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:31:12.04#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:31:12.04#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:12.04#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:12.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:12.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:12.06#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:31:12.10#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:12.10#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:31:12.10#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:31:12.10#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:31:12.10$vc4f8/vb=5,4 2006.140.07:31:12.10#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:31:12.10#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:31:12.10#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:12.10#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:12.16#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:12.16#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:12.18#ibcon#[27=AT05-04\r\n] 2006.140.07:31:12.21#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:12.21#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:31:12.21#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:31:12.21#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:12.21#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:12.33#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:12.33#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:12.35#ibcon#[27=USB\r\n] 2006.140.07:31:12.38#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:12.38#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:31:12.38#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:31:12.38#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:31:12.38$vc4f8/vblo=6,752.99 2006.140.07:31:12.38#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:31:12.38#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:31:12.38#ibcon#ireg 17 cls_cnt 0 2006.140.07:31:12.38#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:12.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:12.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:12.40#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:31:12.44#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:12.44#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:31:12.44#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:31:12.44#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:31:12.44$vc4f8/vb=6,4 2006.140.07:31:12.44#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:31:12.44#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:31:12.44#ibcon#ireg 11 cls_cnt 2 2006.140.07:31:12.44#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:12.50#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:12.50#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:12.52#ibcon#[27=AT06-04\r\n] 2006.140.07:31:12.55#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:12.55#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:31:12.55#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:31:12.55#ibcon#ireg 7 cls_cnt 0 2006.140.07:31:12.55#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:12.67#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:12.67#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:12.69#ibcon#[27=USB\r\n] 2006.140.07:31:12.72#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:12.72#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:31:12.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:31:12.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:31:12.72$vc4f8/vabw=wide 2006.140.07:31:12.72#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:31:12.72#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:31:12.72#ibcon#ireg 8 cls_cnt 0 2006.140.07:31:12.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:12.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:12.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:12.74#ibcon#[25=BW32\r\n] 2006.140.07:31:12.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:12.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:31:12.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:31:12.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:31:12.77$vc4f8/vbbw=wide 2006.140.07:31:12.77#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.07:31:12.77#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.07:31:12.77#ibcon#ireg 8 cls_cnt 0 2006.140.07:31:12.77#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:31:12.84#abcon#<5=/08 3.310.0 24.62 83 993.2\r\n> 2006.140.07:31:12.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:31:12.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:31:12.86#ibcon#[27=BW32\r\n] 2006.140.07:31:12.86#abcon#{5=INTERFACE CLEAR} 2006.140.07:31:12.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:31:12.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:31:12.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:31:12.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:31:12.89$4f8m12a/ifd4f 2006.140.07:31:12.89$ifd4f/lo= 2006.140.07:31:12.89$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:31:12.89$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:31:12.89$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:31:12.89$ifd4f/patch= 2006.140.07:31:12.89$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:31:12.89$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:31:12.89$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:31:12.89$4f8m12a/"form=m,16.000,1:2 2006.140.07:31:12.89$4f8m12a/"tpicd 2006.140.07:31:12.89$4f8m12a/echo=off 2006.140.07:31:12.89$4f8m12a/xlog=off 2006.140.07:31:12.89:!2006.140.07:33:20 2006.140.07:31:46.14#trakl#Source acquired 2006.140.07:31:46.14#flagr#flagr/antenna,acquired 2006.140.07:32:48.14#trakl#Off source 2006.140.07:32:48.14?ERROR st -7 Antenna off-source! 2006.140.07:32:48.14#trakl#az 260.304 el 10.140 azerr*cos(el) 0.0204 elerr -0.0014 2006.140.07:32:49.14#flagr#flagr/antenna,off-source 2006.140.07:32:55.14#trakl#Source re-acquired 2006.140.07:32:55.14#flagr#flagr/antenna,re-acquired 2006.140.07:33:04.14#trakl#Off source 2006.140.07:33:04.14?ERROR st -7 Antenna off-source! 2006.140.07:33:04.14#trakl#az 260.345 el 10.088 azerr*cos(el) 0.0047 elerr -0.0177 2006.140.07:33:04.14#flagr#flagr/antenna,off-source 2006.140.07:33:10.14#trakl#Source re-acquired 2006.140.07:33:10.14#flagr#flagr/antenna,re-acquired 2006.140.07:33:20.00:preob 2006.140.07:33:20.14/onsource/TRACKING 2006.140.07:33:20.14:!2006.140.07:33:30 2006.140.07:33:28.14#trakl#Off source 2006.140.07:33:28.14?ERROR st -7 Antenna off-source! 2006.140.07:33:28.14#trakl#az 260.407 el 10.009 azerr*cos(el) 0.0002 elerr -0.0186 2006.140.07:33:30.00:data_valid=on 2006.140.07:33:30.00:midob 2006.140.07:33:30.14#flagr#flagr/antenna,off-source 2006.140.07:33:31.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.140.07:33:31.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.140.07:33:31.14/onsource/SLEWING 2006.140.07:33:31.14/wx/24.55,993.3,83 2006.140.07:33:31.21/cable/+6.4990E-03 2006.140.07:33:32.30/va/01,08,usb,yes,53,55 2006.140.07:33:32.30/va/02,07,usb,yes,53,56 2006.140.07:33:32.30/va/03,06,usb,yes,57,57 2006.140.07:33:32.30/va/04,07,usb,yes,55,59 2006.140.07:33:32.30/va/05,07,usb,yes,55,58 2006.140.07:33:32.30/va/06,06,usb,yes,54,54 2006.140.07:33:32.30/va/07,06,usb,yes,55,55 2006.140.07:33:32.30/va/08,06,usb,yes,58,57 2006.140.07:33:32.53/valo/01,532.99,yes,locked 2006.140.07:33:32.53/valo/02,572.99,yes,locked 2006.140.07:33:32.53/valo/03,672.99,yes,locked 2006.140.07:33:32.53/valo/04,832.99,yes,locked 2006.140.07:33:32.53/valo/05,652.99,yes,locked 2006.140.07:33:32.53/valo/06,772.99,yes,locked 2006.140.07:33:32.53/valo/07,832.99,yes,locked 2006.140.07:33:32.53/valo/08,852.99,yes,locked 2006.140.07:33:33.62/vb/01,04,usb,yes,31,30 2006.140.07:33:33.62/vb/02,04,usb,yes,33,35 2006.140.07:33:33.62/vb/03,04,usb,yes,29,33 2006.140.07:33:33.62/vb/04,04,usb,yes,30,30 2006.140.07:33:33.62/vb/05,04,usb,yes,29,33 2006.140.07:33:33.62/vb/06,04,usb,yes,30,33 2006.140.07:33:33.62/vb/07,04,usb,yes,32,32 2006.140.07:33:33.62/vb/08,04,usb,yes,29,33 2006.140.07:33:33.86/vblo/01,632.99,yes,locked 2006.140.07:33:33.86/vblo/02,640.99,yes,locked 2006.140.07:33:33.86/vblo/03,656.99,yes,locked 2006.140.07:33:33.86/vblo/04,712.99,yes,locked 2006.140.07:33:33.86/vblo/05,744.99,yes,locked 2006.140.07:33:33.86/vblo/06,752.99,yes,locked 2006.140.07:33:33.86/vblo/07,734.99,yes,locked 2006.140.07:33:33.86/vblo/08,744.99,yes,locked 2006.140.07:33:34.01/vabw/8 2006.140.07:33:34.14#trakl#Source re-acquired 2006.140.07:33:34.16/vbbw/8 2006.140.07:33:34.33/xfe/off,on,15.5 2006.140.07:33:34.72/ifatt/23,28,28,28 2006.140.07:33:35.10/fmout-gps/S +1.08E-07 2006.140.07:33:35.14#flagr#flagr/antenna,re-acquired 2006.140.07:33:35.18:!2006.140.07:34:30 2006.140.07:34:30.00:data_valid=off 2006.140.07:34:30.00:postob 2006.140.07:34:30.19/cable/+6.5007E-03 2006.140.07:34:30.19/wx/24.52,993.4,84 2006.140.07:34:31.10/fmout-gps/S +1.07E-07 2006.140.07:34:31.10:scan_name=140-0735,k06140,60 2006.140.07:34:31.10:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.140.07:34:31.14#flagr#flagr/antenna,new-source 2006.140.07:34:32.14:checkk5 2006.140.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:34:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:34:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:34:34.01/chk_obsdata//k5ts1/T1400733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:34:34.39/chk_obsdata//k5ts2/T1400733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:34:34.76/chk_obsdata//k5ts3/T1400733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:34:35.12/chk_obsdata//k5ts4/T1400733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:34:35.81/k5log//k5ts1_log_newline 2006.140.07:34:36.49/k5log//k5ts2_log_newline 2006.140.07:34:37.19/k5log//k5ts3_log_newline 2006.140.07:34:37.87/k5log//k5ts4_log_newline 2006.140.07:34:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:34:37.89:4f8m12a=1 2006.140.07:34:37.89$4f8m12a/echo=on 2006.140.07:34:37.89$4f8m12a/pcalon 2006.140.07:34:37.90$pcalon/"no phase cal control is implemented here 2006.140.07:34:37.90$4f8m12a/"tpicd=stop 2006.140.07:34:37.90$4f8m12a/vc4f8 2006.140.07:34:37.90$vc4f8/valo=1,532.99 2006.140.07:34:37.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:34:37.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:34:37.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:37.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:37.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:37.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:34:37.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:37.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:37.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:34:37.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:34:37.99$vc4f8/va=1,8 2006.140.07:34:37.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.07:34:37.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.07:34:37.99#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:37.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:37.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:37.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:38.02#ibcon#[25=AT01-08\r\n] 2006.140.07:34:38.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:38.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:38.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.07:34:38.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:38.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:38.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:38.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:38.19#ibcon#[25=USB\r\n] 2006.140.07:34:38.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:38.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:38.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:34:38.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:34:38.22$vc4f8/valo=2,572.99 2006.140.07:34:38.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.07:34:38.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.07:34:38.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:38.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:38.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:38.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:38.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:34:38.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:38.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:38.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:34:38.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:34:38.28$vc4f8/va=2,7 2006.140.07:34:38.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.07:34:38.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.07:34:38.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:38.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:38.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:38.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:38.36#ibcon#[25=AT02-07\r\n] 2006.140.07:34:38.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:38.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:38.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.07:34:38.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:38.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:38.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:38.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:38.53#ibcon#[25=USB\r\n] 2006.140.07:34:38.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:38.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:38.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:34:38.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:34:38.56$vc4f8/valo=3,672.99 2006.140.07:34:38.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:34:38.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:34:38.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:38.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:38.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:38.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:38.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:34:38.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:38.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:38.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:34:38.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:34:38.64$vc4f8/va=3,6 2006.140.07:34:38.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.07:34:38.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.07:34:38.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:38.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:38.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:38.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:38.70#ibcon#[25=AT03-06\r\n] 2006.140.07:34:38.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:38.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:38.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.07:34:38.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:38.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:38.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:38.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:38.87#ibcon#[25=USB\r\n] 2006.140.07:34:38.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:38.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:38.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:34:38.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:34:38.90$vc4f8/valo=4,832.99 2006.140.07:34:38.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:34:38.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:34:38.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:38.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:38.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:38.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:34:38.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:38.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:38.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:34:38.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:34:38.96$vc4f8/va=4,7 2006.140.07:34:38.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.07:34:38.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.07:34:38.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:38.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:39.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:39.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:39.04#ibcon#[25=AT04-07\r\n] 2006.140.07:34:39.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:39.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:39.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.07:34:39.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:39.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:39.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:39.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:39.21#ibcon#[25=USB\r\n] 2006.140.07:34:39.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:39.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:39.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:34:39.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:34:39.24$vc4f8/valo=5,652.99 2006.140.07:34:39.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:34:39.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:34:39.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:39.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:39.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:39.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:34:39.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:39.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:39.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:34:39.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:34:39.30$vc4f8/va=5,7 2006.140.07:34:39.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:34:39.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:34:39.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:39.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:39.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:39.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:39.38#ibcon#[25=AT05-07\r\n] 2006.140.07:34:39.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:39.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:39.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:34:39.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:39.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:39.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:39.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:39.55#ibcon#[25=USB\r\n] 2006.140.07:34:39.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:39.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:39.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:34:39.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:34:39.58$vc4f8/valo=6,772.99 2006.140.07:34:39.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.07:34:39.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.07:34:39.58#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:39.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:39.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:39.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:34:39.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:39.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:39.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:34:39.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:34:39.64$vc4f8/va=6,6 2006.140.07:34:39.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.07:34:39.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.07:34:39.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:39.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:39.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:39.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:39.72#ibcon#[25=AT06-06\r\n] 2006.140.07:34:39.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:39.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:39.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.07:34:39.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:39.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:34:39.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:34:39.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:34:39.89#ibcon#[25=USB\r\n] 2006.140.07:34:39.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:34:39.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:34:39.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:34:39.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:34:39.92$vc4f8/valo=7,832.99 2006.140.07:34:39.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.07:34:39.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.07:34:39.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:39.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:34:39.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:34:39.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:34:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:34:39.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:34:39.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:34:39.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:34:39.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:34:39.98$vc4f8/va=7,6 2006.140.07:34:39.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.07:34:39.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.07:34:39.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:39.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:34:40.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:34:40.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:34:40.06#ibcon#[25=AT07-06\r\n] 2006.140.07:34:40.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:34:40.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:34:40.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.07:34:40.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:40.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:34:40.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:34:40.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:34:40.23#ibcon#[25=USB\r\n] 2006.140.07:34:40.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:34:40.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:34:40.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:34:40.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:34:40.26$vc4f8/valo=8,852.99 2006.140.07:34:40.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.07:34:40.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.07:34:40.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:40.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:34:40.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:34:40.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:34:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:34:40.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:34:40.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:34:40.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:34:40.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:34:40.32$vc4f8/va=8,6 2006.140.07:34:40.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.07:34:40.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.07:34:40.32#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:40.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:34:40.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:34:40.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:34:40.40#ibcon#[25=AT08-06\r\n] 2006.140.07:34:40.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:34:40.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:34:40.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.07:34:40.43#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:40.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:34:40.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:34:40.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:34:40.57#ibcon#[25=USB\r\n] 2006.140.07:34:40.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:34:40.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:34:40.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:34:40.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:34:40.60$vc4f8/vblo=1,632.99 2006.140.07:34:40.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.07:34:40.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.07:34:40.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:40.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:34:40.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:34:40.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:34:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:34:40.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:34:40.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:34:40.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:34:40.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:34:40.66$vc4f8/vb=1,4 2006.140.07:34:40.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.07:34:40.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.07:34:40.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:40.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:34:40.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:34:40.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:34:40.68#ibcon#[27=AT01-04\r\n] 2006.140.07:34:40.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:34:40.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:34:40.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.07:34:40.71#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:40.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:34:40.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:34:40.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:34:40.85#ibcon#[27=USB\r\n] 2006.140.07:34:40.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:34:40.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:34:40.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:34:40.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:34:40.88$vc4f8/vblo=2,640.99 2006.140.07:34:40.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:34:40.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:34:40.88#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:40.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:40.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:40.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:34:40.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:40.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:34:40.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:34:40.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:34:40.94$vc4f8/vb=2,4 2006.140.07:34:40.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.07:34:40.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.07:34:40.94#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:40.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:41.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:41.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:41.02#ibcon#[27=AT02-04\r\n] 2006.140.07:34:41.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:41.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:34:41.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.07:34:41.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:41.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:41.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:41.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:41.19#ibcon#[27=USB\r\n] 2006.140.07:34:41.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:41.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:34:41.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:34:41.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:34:41.22$vc4f8/vblo=3,656.99 2006.140.07:34:41.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.07:34:41.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.07:34:41.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:41.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:41.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:41.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:34:41.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:41.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:34:41.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:34:41.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:34:41.28$vc4f8/vb=3,4 2006.140.07:34:41.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.07:34:41.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.07:34:41.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:41.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:41.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:41.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:41.36#ibcon#[27=AT03-04\r\n] 2006.140.07:34:41.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:41.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:34:41.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.07:34:41.40#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:41.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:41.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:41.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:41.54#ibcon#[27=USB\r\n] 2006.140.07:34:41.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:41.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:34:41.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:34:41.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:34:41.57$vc4f8/vblo=4,712.99 2006.140.07:34:41.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:34:41.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:34:41.57#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:41.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:41.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:41.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:34:41.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:41.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:34:41.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:34:41.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:34:41.63$vc4f8/vb=4,4 2006.140.07:34:41.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.07:34:41.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.07:34:41.63#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:41.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:41.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:41.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:41.71#ibcon#[27=AT04-04\r\n] 2006.140.07:34:41.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:41.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:34:41.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.07:34:41.74#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:41.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:41.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:41.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:41.88#ibcon#[27=USB\r\n] 2006.140.07:34:41.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:41.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:34:41.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:34:41.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:34:41.91$vc4f8/vblo=5,744.99 2006.140.07:34:41.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:34:41.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:34:41.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:41.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:41.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:41.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:34:41.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:41.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:34:41.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:34:41.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:34:41.97$vc4f8/vb=5,4 2006.140.07:34:41.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.07:34:41.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.07:34:41.97#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:41.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:42.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:42.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:42.05#ibcon#[27=AT05-04\r\n] 2006.140.07:34:42.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:42.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:34:42.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.07:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:42.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:42.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:42.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:42.22#ibcon#[27=USB\r\n] 2006.140.07:34:42.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:42.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:34:42.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:34:42.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:34:42.25$vc4f8/vblo=6,752.99 2006.140.07:34:42.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:34:42.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:34:42.25#ibcon#ireg 17 cls_cnt 0 2006.140.07:34:42.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:42.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:42.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:34:42.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:42.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:34:42.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:34:42.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:34:42.31$vc4f8/vb=6,4 2006.140.07:34:42.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:34:42.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:34:42.31#ibcon#ireg 11 cls_cnt 2 2006.140.07:34:42.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:42.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:42.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:42.39#ibcon#[27=AT06-04\r\n] 2006.140.07:34:42.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:42.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:34:42.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:34:42.42#ibcon#ireg 7 cls_cnt 0 2006.140.07:34:42.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:42.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:42.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:42.56#ibcon#[27=USB\r\n] 2006.140.07:34:42.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:42.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:34:42.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:34:42.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:34:42.59$vc4f8/vabw=wide 2006.140.07:34:42.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.07:34:42.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.07:34:42.59#ibcon#ireg 8 cls_cnt 0 2006.140.07:34:42.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:42.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:42.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:42.61#ibcon#[25=BW32\r\n] 2006.140.07:34:42.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:42.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:34:42.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:34:42.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:34:42.64$vc4f8/vbbw=wide 2006.140.07:34:42.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:34:42.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:34:42.64#ibcon#ireg 8 cls_cnt 0 2006.140.07:34:42.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:34:42.71#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:34:42.71#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:34:42.73#ibcon#[27=BW32\r\n] 2006.140.07:34:42.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:34:42.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:34:42.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:34:42.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:34:42.76$4f8m12a/ifd4f 2006.140.07:34:42.76$ifd4f/lo= 2006.140.07:34:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:34:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:34:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:34:42.76$ifd4f/patch= 2006.140.07:34:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:34:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:34:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:34:42.76$4f8m12a/"form=m,16.000,1:2 2006.140.07:34:42.76$4f8m12a/"tpicd 2006.140.07:34:42.76$4f8m12a/echo=off 2006.140.07:34:42.76$4f8m12a/xlog=off 2006.140.07:34:42.76:!2006.140.07:35:10 2006.140.07:34:53.14#trakl#Source acquired 2006.140.07:34:55.14#flagr#flagr/antenna,acquired 2006.140.07:35:10.00:preob 2006.140.07:35:11.14/onsource/TRACKING 2006.140.07:35:11.14:!2006.140.07:35:20 2006.140.07:35:20.00:data_valid=on 2006.140.07:35:20.00:midob 2006.140.07:35:20.14/onsource/TRACKING 2006.140.07:35:20.14/wx/24.48,993.4,84 2006.140.07:35:20.20/cable/+6.4998E-03 2006.140.07:35:21.29/va/01,08,usb,yes,30,32 2006.140.07:35:21.29/va/02,07,usb,yes,30,32 2006.140.07:35:21.29/va/03,06,usb,yes,32,32 2006.140.07:35:21.29/va/04,07,usb,yes,31,33 2006.140.07:35:21.29/va/05,07,usb,yes,30,32 2006.140.07:35:21.29/va/06,06,usb,yes,29,29 2006.140.07:35:21.29/va/07,06,usb,yes,29,29 2006.140.07:35:21.29/va/08,06,usb,yes,31,31 2006.140.07:35:21.52/valo/01,532.99,yes,locked 2006.140.07:35:21.52/valo/02,572.99,yes,locked 2006.140.07:35:21.52/valo/03,672.99,yes,locked 2006.140.07:35:21.52/valo/04,832.99,yes,locked 2006.140.07:35:21.52/valo/05,652.99,yes,locked 2006.140.07:35:21.52/valo/06,772.99,yes,locked 2006.140.07:35:21.52/valo/07,832.99,yes,locked 2006.140.07:35:21.52/valo/08,852.99,yes,locked 2006.140.07:35:22.61/vb/01,04,usb,yes,29,28 2006.140.07:35:22.61/vb/02,04,usb,yes,31,32 2006.140.07:35:22.61/vb/03,04,usb,yes,27,31 2006.140.07:35:22.61/vb/04,04,usb,yes,28,28 2006.140.07:35:22.61/vb/05,04,usb,yes,27,31 2006.140.07:35:22.61/vb/06,04,usb,yes,28,30 2006.140.07:35:22.61/vb/07,04,usb,yes,30,30 2006.140.07:35:22.61/vb/08,04,usb,yes,27,31 2006.140.07:35:22.85/vblo/01,632.99,yes,locked 2006.140.07:35:22.85/vblo/02,640.99,yes,locked 2006.140.07:35:22.85/vblo/03,656.99,yes,locked 2006.140.07:35:22.85/vblo/04,712.99,yes,locked 2006.140.07:35:22.85/vblo/05,744.99,yes,locked 2006.140.07:35:22.85/vblo/06,752.99,yes,locked 2006.140.07:35:22.85/vblo/07,734.99,yes,locked 2006.140.07:35:22.85/vblo/08,744.99,yes,locked 2006.140.07:35:23.00/vabw/8 2006.140.07:35:23.15/vbbw/8 2006.140.07:35:23.24/xfe/off,on,15.5 2006.140.07:35:23.62/ifatt/23,28,28,28 2006.140.07:35:24.10/fmout-gps/S +1.07E-07 2006.140.07:35:24.17:!2006.140.07:36:20 2006.140.07:36:20.00:data_valid=off 2006.140.07:36:20.00:postob 2006.140.07:36:20.11/cable/+6.4969E-03 2006.140.07:36:20.11/wx/24.44,993.4,85 2006.140.07:36:21.10/fmout-gps/S +1.06E-07 2006.140.07:36:21.10:scan_name=140-0737,k06140,60 2006.140.07:36:21.10:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.140.07:36:21.14#flagr#flagr/antenna,new-source 2006.140.07:36:22.14:checkk5 2006.140.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:36:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:36:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:36:24.00/chk_obsdata//k5ts1/T1400735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:36:24.38/chk_obsdata//k5ts2/T1400735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:36:24.75/chk_obsdata//k5ts3/T1400735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:36:25.12/chk_obsdata//k5ts4/T1400735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:36:25.81/k5log//k5ts1_log_newline 2006.140.07:36:26.50/k5log//k5ts2_log_newline 2006.140.07:36:27.19/k5log//k5ts3_log_newline 2006.140.07:36:27.87/k5log//k5ts4_log_newline 2006.140.07:36:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:36:27.90:4f8m12a=1 2006.140.07:36:27.90$4f8m12a/echo=on 2006.140.07:36:27.90$4f8m12a/pcalon 2006.140.07:36:27.90$pcalon/"no phase cal control is implemented here 2006.140.07:36:27.90$4f8m12a/"tpicd=stop 2006.140.07:36:27.90$4f8m12a/vc4f8 2006.140.07:36:27.90$vc4f8/valo=1,532.99 2006.140.07:36:27.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:36:27.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:36:27.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:27.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:27.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:27.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:36:27.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:27.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:27.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:36:27.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:36:27.99$vc4f8/va=1,8 2006.140.07:36:27.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:36:27.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:36:27.99#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:27.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:27.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:27.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:28.02#ibcon#[25=AT01-08\r\n] 2006.140.07:36:28.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:28.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:28.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:36:28.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:28.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:28.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:28.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:28.19#ibcon#[25=USB\r\n] 2006.140.07:36:28.20#abcon#<5=/08 3.210.0 24.44 85 993.5\r\n> 2006.140.07:36:28.23#abcon#{5=INTERFACE CLEAR} 2006.140.07:36:28.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:28.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:28.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:36:28.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:36:28.23$vc4f8/valo=2,572.99 2006.140.07:36:28.23#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:36:28.23#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:36:28.23#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:28.23#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:36:28.23#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:36:28.23#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:36:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:36:28.29#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:36:28.29#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:36:28.29#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:36:28.29#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:36:28.29#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:36:28.29$vc4f8/va=2,7 2006.140.07:36:28.29#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:36:28.29#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:36:28.29#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:28.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:28.35#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:28.35#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:28.37#ibcon#[25=AT02-07\r\n] 2006.140.07:36:28.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:28.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:28.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:36:28.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:28.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:28.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:28.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:28.55#ibcon#[25=USB\r\n] 2006.140.07:36:28.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:28.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:28.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:36:28.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:36:28.60$vc4f8/valo=3,672.99 2006.140.07:36:28.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:36:28.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:36:28.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:28.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:28.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:28.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:28.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:36:28.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:28.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:28.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:36:28.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:36:28.67$vc4f8/va=3,6 2006.140.07:36:28.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:36:28.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:36:28.67#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:28.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:28.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:28.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:28.74#ibcon#[25=AT03-06\r\n] 2006.140.07:36:28.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:28.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:28.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:36:28.77#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:28.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:28.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:28.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:28.91#ibcon#[25=USB\r\n] 2006.140.07:36:28.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:28.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:28.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:36:28.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:36:28.94$vc4f8/valo=4,832.99 2006.140.07:36:28.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:36:28.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:36:28.94#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:28.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:28.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:28.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:36:29.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:29.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:29.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:36:29.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:36:29.00$vc4f8/va=4,7 2006.140.07:36:29.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:36:29.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:36:29.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:29.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:29.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:29.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:29.08#ibcon#[25=AT04-07\r\n] 2006.140.07:36:29.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:29.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:29.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:36:29.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:29.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:29.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:29.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:29.25#ibcon#[25=USB\r\n] 2006.140.07:36:29.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:29.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:29.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:36:29.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:36:29.28$vc4f8/valo=5,652.99 2006.140.07:36:29.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:36:29.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:36:29.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:29.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:29.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:29.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:36:29.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:29.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:29.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:36:29.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:36:29.34$vc4f8/va=5,7 2006.140.07:36:29.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.07:36:29.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.07:36:29.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:29.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:29.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:29.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:29.42#ibcon#[25=AT05-07\r\n] 2006.140.07:36:29.46#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:29.46#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:29.46#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.07:36:29.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:29.46#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:29.58#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:29.58#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:29.60#ibcon#[25=USB\r\n] 2006.140.07:36:29.63#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:29.63#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:29.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:36:29.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:36:29.63$vc4f8/valo=6,772.99 2006.140.07:36:29.63#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.07:36:29.63#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.07:36:29.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:29.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:29.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:29.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:29.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:36:29.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:29.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:29.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:36:29.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:36:29.69$vc4f8/va=6,6 2006.140.07:36:29.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.07:36:29.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.07:36:29.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:29.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:29.75#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:29.75#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:29.77#ibcon#[25=AT06-06\r\n] 2006.140.07:36:29.80#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:29.80#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:29.80#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.07:36:29.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:29.80#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:36:29.92#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:36:29.92#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:36:29.94#ibcon#[25=USB\r\n] 2006.140.07:36:29.97#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:36:29.97#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:36:29.97#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:36:29.97#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:36:29.97$vc4f8/valo=7,832.99 2006.140.07:36:29.97#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.07:36:29.97#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.07:36:29.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:29.97#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:36:29.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:36:29.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:36:29.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:36:30.03#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:36:30.03#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:36:30.03#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:36:30.03#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:36:30.03$vc4f8/va=7,6 2006.140.07:36:30.03#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.07:36:30.03#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.07:36:30.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:30.03#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:36:30.09#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:36:30.09#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:36:30.11#ibcon#[25=AT07-06\r\n] 2006.140.07:36:30.14#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:36:30.14#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:36:30.14#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.07:36:30.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:30.14#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:36:30.26#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:36:30.26#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:36:30.28#ibcon#[25=USB\r\n] 2006.140.07:36:30.33#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:36:30.33#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:36:30.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:36:30.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:36:30.33$vc4f8/valo=8,852.99 2006.140.07:36:30.33#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:36:30.33#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:36:30.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:30.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:36:30.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:36:30.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:36:30.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:36:30.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:36:30.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:36:30.39#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:36:30.39#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:36:30.39$vc4f8/va=8,6 2006.140.07:36:30.39#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:36:30.39#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:36:30.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:30.39#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:36:30.45#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:36:30.45#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:36:30.47#ibcon#[25=AT08-06\r\n] 2006.140.07:36:30.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:36:30.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:36:30.50#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:36:30.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:30.50#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:36:30.62#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:36:30.62#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:36:30.64#ibcon#[25=USB\r\n] 2006.140.07:36:30.67#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:36:30.67#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:36:30.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:36:30.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:36:30.67$vc4f8/vblo=1,632.99 2006.140.07:36:30.67#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:36:30.67#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:36:30.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:30.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:30.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:30.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:30.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:36:30.73#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:30.73#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:36:30.73#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:36:30.73#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:36:30.73$vc4f8/vb=1,4 2006.140.07:36:30.73#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:36:30.73#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:36:30.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:30.73#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:30.73#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:30.73#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:30.75#ibcon#[27=AT01-04\r\n] 2006.140.07:36:30.78#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:30.78#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:36:30.78#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:36:30.78#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:30.78#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:30.90#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:30.90#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:30.92#ibcon#[27=USB\r\n] 2006.140.07:36:30.95#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:30.95#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:36:30.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:36:30.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:36:30.95$vc4f8/vblo=2,640.99 2006.140.07:36:30.95#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:36:30.95#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:36:30.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:30.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:36:30.95#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:36:30.95#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:36:30.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:36:31.01#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:36:31.01#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:36:31.01#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:36:31.01#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:36:31.01$vc4f8/vb=2,4 2006.140.07:36:31.01#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:36:31.01#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:36:31.01#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:31.01#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:36:31.07#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:36:31.07#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:36:31.09#ibcon#[27=AT02-04\r\n] 2006.140.07:36:31.12#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:36:31.12#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:36:31.12#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:36:31.12#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:31.12#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:36:31.24#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:36:31.24#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:36:31.26#ibcon#[27=USB\r\n] 2006.140.07:36:31.29#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:36:31.29#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:36:31.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:36:31.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:36:31.29$vc4f8/vblo=3,656.99 2006.140.07:36:31.29#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:36:31.29#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:36:31.29#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:31.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:36:31.29#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:36:31.29#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:36:31.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:36:31.35#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:36:31.35#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:36:31.35#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:36:31.35#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:36:31.35$vc4f8/vb=3,4 2006.140.07:36:31.35#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:36:31.35#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:36:31.35#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:31.35#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:31.41#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:31.41#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:31.43#ibcon#[27=AT03-04\r\n] 2006.140.07:36:31.46#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:31.46#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:36:31.46#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:36:31.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:31.46#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:31.58#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:31.58#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:31.60#ibcon#[27=USB\r\n] 2006.140.07:36:31.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:31.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:36:31.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:36:31.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:36:31.65$vc4f8/vblo=4,712.99 2006.140.07:36:31.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:36:31.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:36:31.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:31.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:31.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:31.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:31.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:36:31.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:31.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:36:31.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:36:31.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:36:31.71$vc4f8/vb=4,4 2006.140.07:36:31.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:36:31.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:36:31.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:31.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:31.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:31.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:31.79#ibcon#[27=AT04-04\r\n] 2006.140.07:36:31.82#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:31.82#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:36:31.82#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:36:31.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:31.82#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:31.94#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:31.94#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:31.96#ibcon#[27=USB\r\n] 2006.140.07:36:31.99#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:31.99#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:36:31.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:36:31.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:36:31.99$vc4f8/vblo=5,744.99 2006.140.07:36:31.99#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:36:31.99#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:36:31.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:31.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:31.99#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:31.99#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:32.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:36:32.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:32.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:36:32.05#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:36:32.05#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:36:32.05$vc4f8/vb=5,4 2006.140.07:36:32.05#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:36:32.05#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:36:32.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:32.05#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:32.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:32.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:32.13#ibcon#[27=AT05-04\r\n] 2006.140.07:36:32.16#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:32.16#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:36:32.16#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:36:32.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:32.16#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:32.28#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:32.28#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:32.30#ibcon#[27=USB\r\n] 2006.140.07:36:32.34#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:32.34#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:36:32.34#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:36:32.34#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:36:32.34$vc4f8/vblo=6,752.99 2006.140.07:36:32.34#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:36:32.34#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:36:32.34#ibcon#ireg 17 cls_cnt 0 2006.140.07:36:32.34#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:32.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:32.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:32.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:36:32.40#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:32.40#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:36:32.40#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:36:32.40#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:36:32.40$vc4f8/vb=6,4 2006.140.07:36:32.40#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.07:36:32.40#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.07:36:32.40#ibcon#ireg 11 cls_cnt 2 2006.140.07:36:32.40#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:32.46#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:32.46#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:32.48#ibcon#[27=AT06-04\r\n] 2006.140.07:36:32.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:32.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:36:32.51#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.07:36:32.51#ibcon#ireg 7 cls_cnt 0 2006.140.07:36:32.51#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:32.63#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:32.63#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:32.65#ibcon#[27=USB\r\n] 2006.140.07:36:32.68#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:32.68#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:36:32.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:36:32.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:36:32.68$vc4f8/vabw=wide 2006.140.07:36:32.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.07:36:32.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.07:36:32.68#ibcon#ireg 8 cls_cnt 0 2006.140.07:36:32.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:32.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:32.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:32.70#ibcon#[25=BW32\r\n] 2006.140.07:36:32.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:32.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:36:32.73#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:36:32.73#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:36:32.73$vc4f8/vbbw=wide 2006.140.07:36:32.73#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.07:36:32.73#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.07:36:32.73#ibcon#ireg 8 cls_cnt 0 2006.140.07:36:32.73#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:36:32.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:36:32.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:36:32.82#ibcon#[27=BW32\r\n] 2006.140.07:36:32.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:36:32.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:36:32.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:36:32.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:36:32.85$4f8m12a/ifd4f 2006.140.07:36:32.85$ifd4f/lo= 2006.140.07:36:32.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:36:32.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:36:32.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:36:32.85$ifd4f/patch= 2006.140.07:36:32.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:36:32.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:36:32.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:36:32.85$4f8m12a/"form=m,16.000,1:2 2006.140.07:36:32.85$4f8m12a/"tpicd 2006.140.07:36:32.85$4f8m12a/echo=off 2006.140.07:36:32.85$4f8m12a/xlog=off 2006.140.07:36:32.85:!2006.140.07:37:00 2006.140.07:36:42.13#trakl#Source acquired 2006.140.07:36:42.13#flagr#flagr/antenna,acquired 2006.140.07:37:00.00:preob 2006.140.07:37:01.13/onsource/TRACKING 2006.140.07:37:01.13:!2006.140.07:37:10 2006.140.07:37:10.00:data_valid=on 2006.140.07:37:10.00:midob 2006.140.07:37:10.13/onsource/TRACKING 2006.140.07:37:10.13/wx/24.41,993.5,85 2006.140.07:37:10.24/cable/+6.4982E-03 2006.140.07:37:11.33/va/01,08,usb,yes,31,33 2006.140.07:37:11.33/va/02,07,usb,yes,31,33 2006.140.07:37:11.33/va/03,06,usb,yes,33,33 2006.140.07:37:11.33/va/04,07,usb,yes,32,34 2006.140.07:37:11.33/va/05,07,usb,yes,31,33 2006.140.07:37:11.33/va/06,06,usb,yes,30,30 2006.140.07:37:11.33/va/07,06,usb,yes,31,31 2006.140.07:37:11.33/va/08,06,usb,yes,33,33 2006.140.07:37:11.56/valo/01,532.99,yes,locked 2006.140.07:37:11.56/valo/02,572.99,yes,locked 2006.140.07:37:11.56/valo/03,672.99,yes,locked 2006.140.07:37:11.56/valo/04,832.99,yes,locked 2006.140.07:37:11.56/valo/05,652.99,yes,locked 2006.140.07:37:11.56/valo/06,772.99,yes,locked 2006.140.07:37:11.56/valo/07,832.99,yes,locked 2006.140.07:37:11.56/valo/08,852.99,yes,locked 2006.140.07:37:12.65/vb/01,04,usb,yes,29,28 2006.140.07:37:12.65/vb/02,04,usb,yes,31,32 2006.140.07:37:12.65/vb/03,04,usb,yes,27,31 2006.140.07:37:12.65/vb/04,04,usb,yes,28,28 2006.140.07:37:12.65/vb/05,04,usb,yes,27,30 2006.140.07:37:12.65/vb/06,04,usb,yes,28,30 2006.140.07:37:12.65/vb/07,04,usb,yes,29,29 2006.140.07:37:12.65/vb/08,04,usb,yes,27,30 2006.140.07:37:12.88/vblo/01,632.99,yes,locked 2006.140.07:37:12.88/vblo/02,640.99,yes,locked 2006.140.07:37:12.88/vblo/03,656.99,yes,locked 2006.140.07:37:12.88/vblo/04,712.99,yes,locked 2006.140.07:37:12.88/vblo/05,744.99,yes,locked 2006.140.07:37:12.88/vblo/06,752.99,yes,locked 2006.140.07:37:12.88/vblo/07,734.99,yes,locked 2006.140.07:37:12.88/vblo/08,744.99,yes,locked 2006.140.07:37:13.03/vabw/8 2006.140.07:37:13.18/vbbw/8 2006.140.07:37:13.27/xfe/off,on,14.7 2006.140.07:37:13.64/ifatt/23,28,28,28 2006.140.07:37:14.11/fmout-gps/S +1.06E-07 2006.140.07:37:14.15:!2006.140.07:38:10 2006.140.07:38:10.00:data_valid=off 2006.140.07:38:10.00:postob 2006.140.07:38:10.20/cable/+6.4987E-03 2006.140.07:38:10.20/wx/24.38,993.4,85 2006.140.07:38:11.10/fmout-gps/S +1.05E-07 2006.140.07:38:11.10:scan_name=140-0739,k06140,60 2006.140.07:38:11.10:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.140.07:38:11.13#flagr#flagr/antenna,new-source 2006.140.07:38:12.13:checkk5 2006.140.07:38:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:38:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:38:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:38:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:38:13.99/chk_obsdata//k5ts1/T1400737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:38:14.36/chk_obsdata//k5ts2/T1400737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:38:14.73/chk_obsdata//k5ts3/T1400737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:38:15.09/chk_obsdata//k5ts4/T1400737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:38:15.79/k5log//k5ts1_log_newline 2006.140.07:38:16.48/k5log//k5ts2_log_newline 2006.140.07:38:17.17/k5log//k5ts3_log_newline 2006.140.07:38:17.85/k5log//k5ts4_log_newline 2006.140.07:38:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:38:17.88:4f8m12a=1 2006.140.07:38:17.88$4f8m12a/echo=on 2006.140.07:38:17.88$4f8m12a/pcalon 2006.140.07:38:17.88$pcalon/"no phase cal control is implemented here 2006.140.07:38:17.88$4f8m12a/"tpicd=stop 2006.140.07:38:17.88$4f8m12a/vc4f8 2006.140.07:38:17.88$vc4f8/valo=1,532.99 2006.140.07:38:17.88#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:38:17.88#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:38:17.88#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:17.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:17.88#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:17.88#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:38:17.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:17.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:17.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:38:17.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:38:17.98$vc4f8/va=1,8 2006.140.07:38:17.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:38:17.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:38:17.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:17.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:17.98#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:17.98#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:18.01#ibcon#[25=AT01-08\r\n] 2006.140.07:38:18.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:18.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:18.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:38:18.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:18.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:18.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:18.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:18.19#ibcon#[25=USB\r\n] 2006.140.07:38:18.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:18.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:18.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:38:18.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:38:18.22$vc4f8/valo=2,572.99 2006.140.07:38:18.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:38:18.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:38:18.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:18.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:18.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:18.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:38:18.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:18.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:18.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:38:18.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:38:18.28$vc4f8/va=2,7 2006.140.07:38:18.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:38:18.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:38:18.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:18.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:18.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:18.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:18.36#ibcon#[25=AT02-07\r\n] 2006.140.07:38:18.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:18.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:18.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:38:18.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:18.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:18.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:18.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:18.53#ibcon#[25=USB\r\n] 2006.140.07:38:18.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:18.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:18.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:38:18.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:38:18.56$vc4f8/valo=3,672.99 2006.140.07:38:18.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:38:18.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:38:18.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:18.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:18.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:18.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:38:18.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:18.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:18.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:38:18.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:38:18.64$vc4f8/va=3,6 2006.140.07:38:18.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:38:18.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:38:18.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:18.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:18.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:18.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:18.70#ibcon#[25=AT03-06\r\n] 2006.140.07:38:18.73#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:18.73#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:18.73#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:38:18.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:18.73#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:18.85#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:18.85#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:18.87#ibcon#[25=USB\r\n] 2006.140.07:38:18.90#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:18.90#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:18.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:38:18.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:38:18.90$vc4f8/valo=4,832.99 2006.140.07:38:18.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:38:18.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:38:18.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:18.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:18.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:18.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:38:18.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:18.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:18.96#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:38:18.96#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:38:18.96$vc4f8/va=4,7 2006.140.07:38:18.96#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:38:18.96#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:38:18.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:18.96#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:19.02#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:19.02#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:19.04#ibcon#[25=AT04-07\r\n] 2006.140.07:38:19.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:19.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:19.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:38:19.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:19.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:19.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:19.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:19.21#ibcon#[25=USB\r\n] 2006.140.07:38:19.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:19.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:19.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:38:19.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:38:19.24$vc4f8/valo=5,652.99 2006.140.07:38:19.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:38:19.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:38:19.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:19.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:19.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:19.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:38:19.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:19.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:19.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:38:19.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:38:19.30$vc4f8/va=5,7 2006.140.07:38:19.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:38:19.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:38:19.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:19.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:19.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:19.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:19.38#ibcon#[25=AT05-07\r\n] 2006.140.07:38:19.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:19.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:19.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:38:19.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:19.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:19.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:19.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:19.55#ibcon#[25=USB\r\n] 2006.140.07:38:19.58#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:19.58#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:19.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:38:19.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:38:19.58$vc4f8/valo=6,772.99 2006.140.07:38:19.58#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:38:19.58#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:38:19.58#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:19.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:19.58#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:19.58#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:38:19.64#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:19.64#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:19.64#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:38:19.64#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:38:19.64$vc4f8/va=6,6 2006.140.07:38:19.64#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:38:19.64#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:38:19.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:19.64#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:19.70#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:19.70#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:19.72#ibcon#[25=AT06-06\r\n] 2006.140.07:38:19.75#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:19.75#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:19.75#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:38:19.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:19.75#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:19.87#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:19.87#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:19.89#ibcon#[25=USB\r\n] 2006.140.07:38:19.92#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:19.92#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:19.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:38:19.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:38:19.92$vc4f8/valo=7,832.99 2006.140.07:38:19.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:38:19.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:38:19.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:19.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:19.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:19.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:38:19.98#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:19.98#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:19.98#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:38:19.98#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:38:19.98$vc4f8/va=7,6 2006.140.07:38:19.98#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.07:38:19.98#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.07:38:19.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:19.98#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:20.04#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:20.04#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:20.06#ibcon#[25=AT07-06\r\n] 2006.140.07:38:20.08#abcon#<5=/08 2.9 9.5 24.37 85 993.4\r\n> 2006.140.07:38:20.09#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:20.09#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:20.09#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.07:38:20.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:20.09#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:38:20.10#abcon#{5=INTERFACE CLEAR} 2006.140.07:38:20.16#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:38:20.21#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:38:20.21#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:38:20.23#ibcon#[25=USB\r\n] 2006.140.07:38:20.26#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:38:20.26#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:38:20.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:38:20.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:38:20.26$vc4f8/valo=8,852.99 2006.140.07:38:20.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:38:20.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:38:20.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:20.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:38:20.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:38:20.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:38:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:38:20.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:38:20.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:38:20.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:38:20.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:38:20.34$vc4f8/va=8,6 2006.140.07:38:20.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.07:38:20.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.07:38:20.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:20.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:38:20.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:38:20.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:38:20.40#ibcon#[25=AT08-06\r\n] 2006.140.07:38:20.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:38:20.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:38:20.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.07:38:20.43#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:20.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:38:20.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:38:20.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:38:20.57#ibcon#[25=USB\r\n] 2006.140.07:38:20.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:38:20.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:38:20.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:38:20.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:38:20.60$vc4f8/vblo=1,632.99 2006.140.07:38:20.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:38:20.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:38:20.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:20.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:20.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:20.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:38:20.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:20.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:38:20.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:38:20.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:38:20.66$vc4f8/vb=1,4 2006.140.07:38:20.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:38:20.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:38:20.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:20.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:20.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:20.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:20.68#ibcon#[27=AT01-04\r\n] 2006.140.07:38:20.71#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:20.71#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:38:20.71#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:38:20.71#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:20.71#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:20.83#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:20.83#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:20.85#ibcon#[27=USB\r\n] 2006.140.07:38:20.88#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:20.88#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:38:20.88#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:38:20.88#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:38:20.88$vc4f8/vblo=2,640.99 2006.140.07:38:20.88#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:38:20.88#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:38:20.88#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:20.88#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:20.88#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:20.88#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:38:20.94#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:20.94#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:38:20.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:38:20.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:38:20.94$vc4f8/vb=2,4 2006.140.07:38:20.94#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:38:20.94#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:38:20.94#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:20.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:21.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:21.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:21.02#ibcon#[27=AT02-04\r\n] 2006.140.07:38:21.05#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:21.05#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:38:21.05#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:38:21.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:21.05#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:21.17#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:21.17#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:21.19#ibcon#[27=USB\r\n] 2006.140.07:38:21.22#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:21.22#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:38:21.22#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:38:21.22#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:38:21.22$vc4f8/vblo=3,656.99 2006.140.07:38:21.22#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:38:21.22#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:38:21.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:21.22#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:21.22#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:21.22#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:38:21.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:21.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:38:21.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:38:21.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:38:21.28$vc4f8/vb=3,4 2006.140.07:38:21.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:38:21.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:38:21.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:21.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:21.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:21.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:21.36#ibcon#[27=AT03-04\r\n] 2006.140.07:38:21.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:21.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:38:21.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:38:21.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:21.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:21.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:21.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:21.53#ibcon#[27=USB\r\n] 2006.140.07:38:21.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:21.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:38:21.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:38:21.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:38:21.56$vc4f8/vblo=4,712.99 2006.140.07:38:21.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:38:21.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:38:21.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:21.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:21.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:21.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:38:21.62#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:21.62#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:38:21.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:38:21.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:38:21.62$vc4f8/vb=4,4 2006.140.07:38:21.62#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:38:21.62#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:38:21.62#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:21.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:21.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:21.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:21.70#ibcon#[27=AT04-04\r\n] 2006.140.07:38:21.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:21.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:38:21.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:38:21.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:21.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:21.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:21.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:21.87#ibcon#[27=USB\r\n] 2006.140.07:38:21.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:21.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:38:21.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:38:21.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:38:21.90$vc4f8/vblo=5,744.99 2006.140.07:38:21.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:38:21.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:38:21.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:21.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:21.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:21.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:38:21.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:21.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:38:21.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:38:21.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:38:21.96$vc4f8/vb=5,4 2006.140.07:38:21.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:38:21.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:38:21.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:21.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:22.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:22.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:22.04#ibcon#[27=AT05-04\r\n] 2006.140.07:38:22.07#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:22.07#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:38:22.07#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:38:22.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:22.07#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:22.19#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:22.19#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:22.21#ibcon#[27=USB\r\n] 2006.140.07:38:22.24#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:22.24#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:38:22.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:38:22.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:38:22.24$vc4f8/vblo=6,752.99 2006.140.07:38:22.24#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:38:22.24#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:38:22.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:38:22.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:22.24#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:22.24#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:38:22.30#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:22.30#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:38:22.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:38:22.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:38:22.30$vc4f8/vb=6,4 2006.140.07:38:22.30#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:38:22.30#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:38:22.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:38:22.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:22.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:22.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:22.38#ibcon#[27=AT06-04\r\n] 2006.140.07:38:22.41#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:22.41#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:38:22.41#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:38:22.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:38:22.41#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:22.53#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:22.53#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:22.55#ibcon#[27=USB\r\n] 2006.140.07:38:22.58#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:22.58#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:38:22.58#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:38:22.58#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:38:22.58$vc4f8/vabw=wide 2006.140.07:38:22.58#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:38:22.58#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:38:22.58#ibcon#ireg 8 cls_cnt 0 2006.140.07:38:22.58#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:22.58#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:22.58#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:22.60#ibcon#[25=BW32\r\n] 2006.140.07:38:22.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:22.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:38:22.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:38:22.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:38:22.63$vc4f8/vbbw=wide 2006.140.07:38:22.63#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:38:22.63#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:38:22.63#ibcon#ireg 8 cls_cnt 0 2006.140.07:38:22.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:38:22.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:38:22.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:38:22.72#ibcon#[27=BW32\r\n] 2006.140.07:38:22.75#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:38:22.75#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:38:22.75#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:38:22.75#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:38:22.75$4f8m12a/ifd4f 2006.140.07:38:22.75$ifd4f/lo= 2006.140.07:38:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:38:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:38:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:38:22.75$ifd4f/patch= 2006.140.07:38:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:38:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:38:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:38:22.75$4f8m12a/"form=m,16.000,1:2 2006.140.07:38:22.75$4f8m12a/"tpicd 2006.140.07:38:22.75$4f8m12a/echo=off 2006.140.07:38:22.75$4f8m12a/xlog=off 2006.140.07:38:22.75:!2006.140.07:38:50 2006.140.07:38:29.13#trakl#Source acquired 2006.140.07:38:29.13#flagr#flagr/antenna,acquired 2006.140.07:38:50.00:preob 2006.140.07:38:51.13/onsource/TRACKING 2006.140.07:38:51.13:!2006.140.07:39:00 2006.140.07:39:00.00:data_valid=on 2006.140.07:39:00.00:midob 2006.140.07:39:00.14/onsource/TRACKING 2006.140.07:39:00.14/wx/24.35,993.4,85 2006.140.07:39:00.35/cable/+6.4999E-03 2006.140.07:39:01.44/va/01,08,usb,yes,30,32 2006.140.07:39:01.44/va/02,07,usb,yes,31,32 2006.140.07:39:01.44/va/03,06,usb,yes,32,32 2006.140.07:39:01.44/va/04,07,usb,yes,31,34 2006.140.07:39:01.44/va/05,07,usb,yes,31,33 2006.140.07:39:01.44/va/06,06,usb,yes,30,29 2006.140.07:39:01.44/va/07,06,usb,yes,30,30 2006.140.07:39:01.44/va/08,06,usb,yes,32,32 2006.140.07:39:01.67/valo/01,532.99,yes,locked 2006.140.07:39:01.67/valo/02,572.99,yes,locked 2006.140.07:39:01.67/valo/03,672.99,yes,locked 2006.140.07:39:01.67/valo/04,832.99,yes,locked 2006.140.07:39:01.67/valo/05,652.99,yes,locked 2006.140.07:39:01.67/valo/06,772.99,yes,locked 2006.140.07:39:01.67/valo/07,832.99,yes,locked 2006.140.07:39:01.67/valo/08,852.99,yes,locked 2006.140.07:39:02.76/vb/01,04,usb,yes,29,28 2006.140.07:39:02.76/vb/02,04,usb,yes,31,32 2006.140.07:39:02.76/vb/03,04,usb,yes,27,30 2006.140.07:39:02.76/vb/04,04,usb,yes,28,28 2006.140.07:39:02.76/vb/05,04,usb,yes,26,30 2006.140.07:39:02.76/vb/06,04,usb,yes,27,30 2006.140.07:39:02.76/vb/07,04,usb,yes,29,29 2006.140.07:39:02.76/vb/08,04,usb,yes,27,30 2006.140.07:39:02.99/vblo/01,632.99,yes,locked 2006.140.07:39:02.99/vblo/02,640.99,yes,locked 2006.140.07:39:02.99/vblo/03,656.99,yes,locked 2006.140.07:39:02.99/vblo/04,712.99,yes,locked 2006.140.07:39:02.99/vblo/05,744.99,yes,locked 2006.140.07:39:02.99/vblo/06,752.99,yes,locked 2006.140.07:39:02.99/vblo/07,734.99,yes,locked 2006.140.07:39:02.99/vblo/08,744.99,yes,locked 2006.140.07:39:03.14/vabw/8 2006.140.07:39:03.29/vbbw/8 2006.140.07:39:03.38/xfe/off,on,15.0 2006.140.07:39:03.76/ifatt/23,28,28,28 2006.140.07:39:04.10/fmout-gps/S +1.06E-07 2006.140.07:39:04.17:!2006.140.07:40:00 2006.140.07:40:00.00:data_valid=off 2006.140.07:40:00.00:postob 2006.140.07:40:00.18/cable/+6.5007E-03 2006.140.07:40:00.18/wx/24.31,993.5,86 2006.140.07:40:01.09/fmout-gps/S +1.05E-07 2006.140.07:40:01.09:scan_name=140-0740,k06140,60 2006.140.07:40:01.09:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.140.07:40:01.14#flagr#flagr/antenna,new-source 2006.140.07:40:02.14:checkk5 2006.140.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:40:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:40:04.02/chk_obsdata//k5ts1/T1400739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:40:04.39/chk_obsdata//k5ts2/T1400739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:40:04.76/chk_obsdata//k5ts3/T1400739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:40:05.14/chk_obsdata//k5ts4/T1400739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:40:05.83/k5log//k5ts1_log_newline 2006.140.07:40:06.52/k5log//k5ts2_log_newline 2006.140.07:40:07.21/k5log//k5ts3_log_newline 2006.140.07:40:07.89/k5log//k5ts4_log_newline 2006.140.07:40:07.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:40:07.92:4f8m12a=1 2006.140.07:40:07.92$4f8m12a/echo=on 2006.140.07:40:07.92$4f8m12a/pcalon 2006.140.07:40:07.92$pcalon/"no phase cal control is implemented here 2006.140.07:40:07.92$4f8m12a/"tpicd=stop 2006.140.07:40:07.92$4f8m12a/vc4f8 2006.140.07:40:07.92$vc4f8/valo=1,532.99 2006.140.07:40:07.92#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:40:07.92#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:40:07.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:07.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:07.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:07.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:40:08.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:08.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:08.02#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:40:08.02#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:40:08.02$vc4f8/va=1,8 2006.140.07:40:08.02#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:40:08.02#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:40:08.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:08.02#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:08.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:08.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:08.05#ibcon#[25=AT01-08\r\n] 2006.140.07:40:08.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:08.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:08.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:40:08.08#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:08.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:08.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:08.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:08.23#ibcon#[25=USB\r\n] 2006.140.07:40:08.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:08.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:08.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:40:08.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:40:08.27$vc4f8/valo=2,572.99 2006.140.07:40:08.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:40:08.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:40:08.27#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:08.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:08.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:08.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:40:08.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:08.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:08.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:40:08.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:40:08.35$vc4f8/va=2,7 2006.140.07:40:08.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:40:08.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:40:08.35#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:08.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:08.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:08.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:08.41#ibcon#[25=AT02-07\r\n] 2006.140.07:40:08.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:08.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:08.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:40:08.44#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:08.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:08.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:08.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:08.58#ibcon#[25=USB\r\n] 2006.140.07:40:08.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:08.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:08.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:40:08.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:40:08.63$vc4f8/valo=3,672.99 2006.140.07:40:08.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:40:08.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:40:08.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:08.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:08.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:08.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:08.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:40:08.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:08.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:08.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:40:08.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:40:08.70$vc4f8/va=3,6 2006.140.07:40:08.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:40:08.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:40:08.70#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:08.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:08.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:08.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:08.77#ibcon#[25=AT03-06\r\n] 2006.140.07:40:08.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:08.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:08.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:40:08.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:08.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:08.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:08.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:08.94#ibcon#[25=USB\r\n] 2006.140.07:40:08.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:08.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:08.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:40:08.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:40:08.97$vc4f8/valo=4,832.99 2006.140.07:40:08.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:40:08.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:40:08.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:08.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:08.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:08.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:08.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:40:09.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:09.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:09.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:40:09.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:40:09.03$vc4f8/va=4,7 2006.140.07:40:09.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:40:09.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:40:09.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:09.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:09.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:09.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:09.11#ibcon#[25=AT04-07\r\n] 2006.140.07:40:09.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:09.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:09.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:40:09.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:09.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:09.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:09.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:09.28#ibcon#[25=USB\r\n] 2006.140.07:40:09.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:09.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:09.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:40:09.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:40:09.31$vc4f8/valo=5,652.99 2006.140.07:40:09.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.07:40:09.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.07:40:09.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:09.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:40:09.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:40:09.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:40:09.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:40:09.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:40:09.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:40:09.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:40:09.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:40:09.37$vc4f8/va=5,7 2006.140.07:40:09.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.07:40:09.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.07:40:09.37#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:09.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:40:09.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:40:09.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:40:09.45#ibcon#[25=AT05-07\r\n] 2006.140.07:40:09.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:40:09.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:40:09.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.07:40:09.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:09.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:40:09.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:40:09.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:40:09.62#ibcon#[25=USB\r\n] 2006.140.07:40:09.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:40:09.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:40:09.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:40:09.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:40:09.65$vc4f8/valo=6,772.99 2006.140.07:40:09.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.07:40:09.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.07:40:09.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:09.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:09.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:09.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:09.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:40:09.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:09.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:09.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:40:09.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:40:09.71$vc4f8/va=6,6 2006.140.07:40:09.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.07:40:09.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.07:40:09.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:09.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:09.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:09.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:09.79#ibcon#[25=AT06-06\r\n] 2006.140.07:40:09.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:09.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:09.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.07:40:09.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:09.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:09.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:09.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:09.96#ibcon#[25=USB\r\n] 2006.140.07:40:09.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:09.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:09.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:40:09.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:40:09.99$vc4f8/valo=7,832.99 2006.140.07:40:09.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.07:40:09.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.07:40:09.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:09.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:09.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:09.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:10.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:40:10.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:10.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:10.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:40:10.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:40:10.05$vc4f8/va=7,6 2006.140.07:40:10.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.07:40:10.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.07:40:10.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:10.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:10.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:10.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:10.13#ibcon#[25=AT07-06\r\n] 2006.140.07:40:10.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:10.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:10.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.07:40:10.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:10.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:40:10.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:40:10.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:40:10.30#ibcon#[25=USB\r\n] 2006.140.07:40:10.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:40:10.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:40:10.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:40:10.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:40:10.33$vc4f8/valo=8,852.99 2006.140.07:40:10.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.07:40:10.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.07:40:10.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:10.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:40:10.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:40:10.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:40:10.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:40:10.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:40:10.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:40:10.41#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:40:10.41#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:40:10.41$vc4f8/va=8,6 2006.140.07:40:10.41#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.07:40:10.41#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.07:40:10.41#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:10.41#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:40:10.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:40:10.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:40:10.47#ibcon#[25=AT08-06\r\n] 2006.140.07:40:10.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:40:10.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:40:10.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.07:40:10.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:10.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:40:10.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:40:10.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:40:10.64#ibcon#[25=USB\r\n] 2006.140.07:40:10.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:40:10.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:40:10.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:40:10.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:40:10.67$vc4f8/vblo=1,632.99 2006.140.07:40:10.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.07:40:10.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.07:40:10.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:10.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:40:10.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:40:10.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:40:10.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:40:10.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:40:10.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:40:10.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:40:10.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:40:10.73$vc4f8/vb=1,4 2006.140.07:40:10.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.07:40:10.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.07:40:10.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:10.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:40:10.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:40:10.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:40:10.75#ibcon#[27=AT01-04\r\n] 2006.140.07:40:10.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:40:10.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:40:10.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.07:40:10.78#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:10.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:40:10.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:40:10.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:40:10.92#ibcon#[27=USB\r\n] 2006.140.07:40:10.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:40:10.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:40:10.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:40:10.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:40:10.95$vc4f8/vblo=2,640.99 2006.140.07:40:10.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:40:10.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:40:10.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:10.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:10.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:10.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:10.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:40:11.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:11.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:40:11.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:40:11.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:40:11.01$vc4f8/vb=2,4 2006.140.07:40:11.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:40:11.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:40:11.01#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:11.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:11.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:11.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:11.09#ibcon#[27=AT02-04\r\n] 2006.140.07:40:11.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:11.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:40:11.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:40:11.12#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:11.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:11.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:11.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:11.26#ibcon#[27=USB\r\n] 2006.140.07:40:11.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:11.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:40:11.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:40:11.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:40:11.29$vc4f8/vblo=3,656.99 2006.140.07:40:11.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:40:11.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:40:11.29#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:11.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:11.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:11.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:11.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:40:11.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:11.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:40:11.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:40:11.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:40:11.35$vc4f8/vb=3,4 2006.140.07:40:11.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:40:11.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:40:11.35#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:11.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:11.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:11.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:11.43#ibcon#[27=AT03-04\r\n] 2006.140.07:40:11.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:11.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:40:11.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:40:11.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:11.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:11.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:11.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:11.60#ibcon#[27=USB\r\n] 2006.140.07:40:11.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:11.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:40:11.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:40:11.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:40:11.63$vc4f8/vblo=4,712.99 2006.140.07:40:11.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:40:11.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:40:11.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:11.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:11.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:11.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:11.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:40:11.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:11.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:40:11.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:40:11.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:40:11.69$vc4f8/vb=4,4 2006.140.07:40:11.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:40:11.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:40:11.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:11.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:11.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:11.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:11.77#ibcon#[27=AT04-04\r\n] 2006.140.07:40:11.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:11.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:40:11.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:40:11.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:11.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:11.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:11.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:11.94#ibcon#[27=USB\r\n] 2006.140.07:40:11.99#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:11.99#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:40:11.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:40:11.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:40:11.99$vc4f8/vblo=5,744.99 2006.140.07:40:11.99#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:40:11.99#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:40:11.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:11.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:11.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:11.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:12.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:40:12.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:12.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:40:12.05#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:40:12.05#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:40:12.05$vc4f8/vb=5,4 2006.140.07:40:12.05#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:40:12.05#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:40:12.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:12.05#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:12.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:12.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:12.13#ibcon#[27=AT05-04\r\n] 2006.140.07:40:12.15#abcon#<5=/08 2.6 9.5 24.30 86 993.5\r\n> 2006.140.07:40:12.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:12.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:40:12.16#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:40:12.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:12.16#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:12.17#abcon#{5=INTERFACE CLEAR} 2006.140.07:40:12.23#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:40:12.28#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:12.28#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:12.30#ibcon#[27=USB\r\n] 2006.140.07:40:12.33#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:12.33#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:40:12.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:40:12.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:40:12.33$vc4f8/vblo=6,752.99 2006.140.07:40:12.33#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.07:40:12.33#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.07:40:12.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:40:12.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:12.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:12.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:12.35#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:40:12.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:12.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:40:12.39#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:40:12.39#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:40:12.39$vc4f8/vb=6,4 2006.140.07:40:12.39#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.07:40:12.39#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.07:40:12.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:40:12.39#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:12.45#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:12.45#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:12.47#ibcon#[27=AT06-04\r\n] 2006.140.07:40:12.50#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:12.50#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:40:12.50#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.07:40:12.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:40:12.50#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:12.62#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:12.62#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:12.64#ibcon#[27=USB\r\n] 2006.140.07:40:12.69#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:12.69#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:40:12.69#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:40:12.69#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:40:12.69$vc4f8/vabw=wide 2006.140.07:40:12.69#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.07:40:12.69#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.07:40:12.69#ibcon#ireg 8 cls_cnt 0 2006.140.07:40:12.69#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:12.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:12.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:12.71#ibcon#[25=BW32\r\n] 2006.140.07:40:12.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:12.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:40:12.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:40:12.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:40:12.74$vc4f8/vbbw=wide 2006.140.07:40:12.74#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:40:12.74#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:40:12.74#ibcon#ireg 8 cls_cnt 0 2006.140.07:40:12.74#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:40:12.81#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:40:12.81#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:40:12.83#ibcon#[27=BW32\r\n] 2006.140.07:40:12.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:40:12.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:40:12.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:40:12.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:40:12.86$4f8m12a/ifd4f 2006.140.07:40:12.86$ifd4f/lo= 2006.140.07:40:12.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:40:12.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:40:12.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:40:12.86$ifd4f/patch= 2006.140.07:40:12.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:40:12.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:40:12.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:40:12.86$4f8m12a/"form=m,16.000,1:2 2006.140.07:40:12.86$4f8m12a/"tpicd 2006.140.07:40:12.86$4f8m12a/echo=off 2006.140.07:40:12.86$4f8m12a/xlog=off 2006.140.07:40:12.86:!2006.140.07:40:40 2006.140.07:40:23.14#trakl#Source acquired 2006.140.07:40:25.14#flagr#flagr/antenna,acquired 2006.140.07:40:40.00:preob 2006.140.07:40:41.14/onsource/TRACKING 2006.140.07:40:41.14:!2006.140.07:40:50 2006.140.07:40:45.14#trakl#Off source 2006.140.07:40:45.14?ERROR st -7 Antenna off-source! 2006.140.07:40:45.14#trakl#az 334.646 el 69.486 azerr*cos(el) 0.0002 elerr -0.0164 2006.140.07:40:45.14#flagr#flagr/antenna,off-source 2006.140.07:40:50.00:data_valid=on 2006.140.07:40:50.00:midob 2006.140.07:40:50.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.140.07:40:50.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.140.07:40:50.14/onsource/SLEWING 2006.140.07:40:50.14/wx/24.28,993.5,86 2006.140.07:40:50.27/cable/+6.5027E-03 2006.140.07:40:51.14#trakl#Source re-acquired 2006.140.07:40:51.14#flagr#flagr/antenna,re-acquired 2006.140.07:40:51.36/va/01,08,usb,yes,30,32 2006.140.07:40:51.36/va/02,07,usb,yes,31,32 2006.140.07:40:51.36/va/03,06,usb,yes,32,33 2006.140.07:40:51.36/va/04,07,usb,yes,31,34 2006.140.07:40:51.36/va/05,07,usb,yes,31,32 2006.140.07:40:51.36/va/06,06,usb,yes,30,29 2006.140.07:40:51.36/va/07,06,usb,yes,30,30 2006.140.07:40:51.36/va/08,06,usb,yes,32,32 2006.140.07:40:51.59/valo/01,532.99,yes,locked 2006.140.07:40:51.59/valo/02,572.99,yes,locked 2006.140.07:40:51.59/valo/03,672.99,yes,locked 2006.140.07:40:51.59/valo/04,832.99,yes,locked 2006.140.07:40:51.59/valo/05,652.99,yes,locked 2006.140.07:40:51.59/valo/06,772.99,yes,locked 2006.140.07:40:51.59/valo/07,832.99,yes,locked 2006.140.07:40:51.59/valo/08,852.99,yes,locked 2006.140.07:40:52.68/vb/01,04,usb,yes,29,28 2006.140.07:40:52.68/vb/02,04,usb,yes,31,32 2006.140.07:40:52.68/vb/03,04,usb,yes,27,31 2006.140.07:40:52.68/vb/04,04,usb,yes,28,28 2006.140.07:40:52.68/vb/05,04,usb,yes,26,30 2006.140.07:40:52.68/vb/06,04,usb,yes,27,30 2006.140.07:40:52.68/vb/07,04,usb,yes,29,29 2006.140.07:40:52.68/vb/08,04,usb,yes,27,30 2006.140.07:40:52.91/vblo/01,632.99,yes,locked 2006.140.07:40:52.91/vblo/02,640.99,yes,locked 2006.140.07:40:52.91/vblo/03,656.99,yes,locked 2006.140.07:40:52.91/vblo/04,712.99,yes,locked 2006.140.07:40:52.91/vblo/05,744.99,yes,locked 2006.140.07:40:52.91/vblo/06,752.99,yes,locked 2006.140.07:40:52.91/vblo/07,734.99,yes,locked 2006.140.07:40:52.91/vblo/08,744.99,yes,locked 2006.140.07:40:53.06/vabw/8 2006.140.07:40:53.21/vbbw/8 2006.140.07:40:53.39/xfe/off,on,15.2 2006.140.07:40:53.77/ifatt/23,28,28,28 2006.140.07:40:54.10/fmout-gps/S +1.05E-07 2006.140.07:40:54.17:!2006.140.07:41:50 2006.140.07:41:50.00:data_valid=off 2006.140.07:41:50.00:postob 2006.140.07:41:50.14/cable/+6.5007E-03 2006.140.07:41:50.14/wx/24.25,993.5,86 2006.140.07:41:51.09/fmout-gps/S +1.07E-07 2006.140.07:41:51.09:scan_name=140-0742,k06140,60 2006.140.07:41:51.09:source=1044+719,104827.62,714335.9,2000.0,cw 2006.140.07:41:51.14#flagr#flagr/antenna,new-source 2006.140.07:41:52.14:checkk5 2006.140.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:41:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:41:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:41:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:41:54.02/chk_obsdata//k5ts1/T1400740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:41:54.39/chk_obsdata//k5ts2/T1400740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:41:54.76/chk_obsdata//k5ts3/T1400740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:41:55.14/chk_obsdata//k5ts4/T1400740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:41:55.84/k5log//k5ts1_log_newline 2006.140.07:41:56.53/k5log//k5ts2_log_newline 2006.140.07:41:57.21/k5log//k5ts3_log_newline 2006.140.07:41:57.90/k5log//k5ts4_log_newline 2006.140.07:41:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:41:57.93:4f8m12a=1 2006.140.07:41:57.93$4f8m12a/echo=on 2006.140.07:41:57.93$4f8m12a/pcalon 2006.140.07:41:57.93$pcalon/"no phase cal control is implemented here 2006.140.07:41:57.93$4f8m12a/"tpicd=stop 2006.140.07:41:57.93$4f8m12a/vc4f8 2006.140.07:41:57.93$vc4f8/valo=1,532.99 2006.140.07:41:57.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:41:57.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:41:57.93#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:57.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:41:57.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:41:57.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:41:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:41:58.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:41:58.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:41:58.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:41:58.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:41:58.03$vc4f8/va=1,8 2006.140.07:41:58.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:41:58.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:41:58.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:58.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:41:58.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:41:58.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:41:58.06#ibcon#[25=AT01-08\r\n] 2006.140.07:41:58.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:41:58.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:41:58.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:41:58.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:58.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:41:58.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:41:58.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:41:58.24#ibcon#[25=USB\r\n] 2006.140.07:41:58.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:41:58.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:41:58.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:41:58.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:41:58.28$vc4f8/valo=2,572.99 2006.140.07:41:58.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:41:58.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:41:58.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:58.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:41:58.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:41:58.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:41:58.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:41:58.36#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:41:58.36#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:41:58.36#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:41:58.36#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:41:58.36$vc4f8/va=2,7 2006.140.07:41:58.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:41:58.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:41:58.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:58.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:41:58.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:41:58.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:41:58.42#ibcon#[25=AT02-07\r\n] 2006.140.07:41:58.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:41:58.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:41:58.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:41:58.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:58.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:41:58.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:41:58.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:41:58.59#ibcon#[25=USB\r\n] 2006.140.07:41:58.62#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:41:58.62#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:41:58.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:41:58.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:41:58.62$vc4f8/valo=3,672.99 2006.140.07:41:58.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:41:58.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:41:58.62#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:58.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:41:58.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:41:58.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:41:58.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:41:58.70#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:41:58.70#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:41:58.70#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:41:58.70#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:41:58.70$vc4f8/va=3,6 2006.140.07:41:58.70#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:41:58.70#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:41:58.70#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:58.70#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:41:58.74#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:41:58.74#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:41:58.76#ibcon#[25=AT03-06\r\n] 2006.140.07:41:58.79#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:41:58.79#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:41:58.79#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:41:58.79#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:58.79#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:41:58.91#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:41:58.91#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:41:58.93#ibcon#[25=USB\r\n] 2006.140.07:41:58.96#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:41:58.96#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:41:58.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:41:58.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:41:58.96$vc4f8/valo=4,832.99 2006.140.07:41:58.96#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:41:58.96#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:41:58.96#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:58.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:41:58.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:41:58.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:41:58.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:41:59.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:41:59.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:41:59.02#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:41:59.02#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:41:59.02$vc4f8/va=4,7 2006.140.07:41:59.02#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:41:59.02#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:41:59.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:59.02#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:41:59.08#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:41:59.08#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:41:59.10#ibcon#[25=AT04-07\r\n] 2006.140.07:41:59.13#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:41:59.13#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:41:59.13#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:41:59.13#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:59.13#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:41:59.25#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:41:59.25#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:41:59.27#ibcon#[25=USB\r\n] 2006.140.07:41:59.30#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:41:59.30#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:41:59.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:41:59.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:41:59.30$vc4f8/valo=5,652.99 2006.140.07:41:59.30#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:41:59.30#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:41:59.30#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:59.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:41:59.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:41:59.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:41:59.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:41:59.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:41:59.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:41:59.36#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:41:59.36#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:41:59.36$vc4f8/va=5,7 2006.140.07:41:59.36#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:41:59.36#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:41:59.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:59.36#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:41:59.42#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:41:59.42#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:41:59.44#ibcon#[25=AT05-07\r\n] 2006.140.07:41:59.47#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:41:59.47#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:41:59.47#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:41:59.47#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:59.47#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:41:59.59#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:41:59.59#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:41:59.61#ibcon#[25=USB\r\n] 2006.140.07:41:59.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:41:59.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:41:59.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:41:59.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:41:59.64$vc4f8/valo=6,772.99 2006.140.07:41:59.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:41:59.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:41:59.64#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:59.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:41:59.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:41:59.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:41:59.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:41:59.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:41:59.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:41:59.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:41:59.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:41:59.72$vc4f8/va=6,6 2006.140.07:41:59.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:41:59.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:41:59.72#ibcon#ireg 11 cls_cnt 2 2006.140.07:41:59.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:41:59.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:41:59.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:41:59.78#ibcon#[25=AT06-06\r\n] 2006.140.07:41:59.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:41:59.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:41:59.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:41:59.81#ibcon#ireg 7 cls_cnt 0 2006.140.07:41:59.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:41:59.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:41:59.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:41:59.95#ibcon#[25=USB\r\n] 2006.140.07:41:59.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:41:59.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:41:59.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:41:59.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:41:59.98$vc4f8/valo=7,832.99 2006.140.07:41:59.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:41:59.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:41:59.98#ibcon#ireg 17 cls_cnt 0 2006.140.07:41:59.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:41:59.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:41:59.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:42:00.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:42:00.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:42:00.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:42:00.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:42:00.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:42:00.04$vc4f8/va=7,6 2006.140.07:42:00.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.07:42:00.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.07:42:00.04#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:00.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:42:00.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:42:00.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:42:00.12#ibcon#[25=AT07-06\r\n] 2006.140.07:42:00.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:42:00.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:42:00.15#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.07:42:00.15#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:00.15#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:42:00.27#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:42:00.27#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:42:00.29#ibcon#[25=USB\r\n] 2006.140.07:42:00.32#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:42:00.32#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:42:00.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:42:00.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:42:00.32$vc4f8/valo=8,852.99 2006.140.07:42:00.32#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.07:42:00.32#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.07:42:00.32#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:00.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:42:00.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:42:00.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:42:00.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:42:00.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:42:00.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:42:00.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:42:00.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:42:00.38$vc4f8/va=8,6 2006.140.07:42:00.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.07:42:00.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.07:42:00.38#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:00.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:42:00.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:42:00.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:42:00.46#ibcon#[25=AT08-06\r\n] 2006.140.07:42:00.50#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:42:00.50#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:42:00.50#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.07:42:00.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:00.50#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:42:00.62#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:42:00.62#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:42:00.64#ibcon#[25=USB\r\n] 2006.140.07:42:00.67#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:42:00.67#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:42:00.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:42:00.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:42:00.67$vc4f8/vblo=1,632.99 2006.140.07:42:00.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:42:00.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:42:00.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:00.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:42:00.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:42:00.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:42:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:42:00.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:42:00.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:42:00.73#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:42:00.73#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:42:00.73$vc4f8/vb=1,4 2006.140.07:42:00.73#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.07:42:00.73#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.07:42:00.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:00.73#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:42:00.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:42:00.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:42:00.75#ibcon#[27=AT01-04\r\n] 2006.140.07:42:00.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:42:00.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:42:00.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.07:42:00.78#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:00.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:42:00.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:42:00.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:42:00.92#ibcon#[27=USB\r\n] 2006.140.07:42:00.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:42:00.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:42:00.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:42:00.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:42:00.95$vc4f8/vblo=2,640.99 2006.140.07:42:00.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:42:00.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:42:00.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:00.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:42:00.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:42:00.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:42:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:42:01.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:42:01.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:42:01.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:42:01.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:42:01.01$vc4f8/vb=2,4 2006.140.07:42:01.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:42:01.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:42:01.01#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:01.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:42:01.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:42:01.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:42:01.09#ibcon#[27=AT02-04\r\n] 2006.140.07:42:01.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:42:01.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:42:01.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:42:01.12#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:01.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:42:01.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:42:01.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:42:01.26#ibcon#[27=USB\r\n] 2006.140.07:42:01.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:42:01.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:42:01.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:42:01.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:42:01.29$vc4f8/vblo=3,656.99 2006.140.07:42:01.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:42:01.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:42:01.29#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:01.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:42:01.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:42:01.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:42:01.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:42:01.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:42:01.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:42:01.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:42:01.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:42:01.35$vc4f8/vb=3,4 2006.140.07:42:01.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:42:01.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:42:01.35#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:01.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:42:01.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:42:01.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:42:01.43#ibcon#[27=AT03-04\r\n] 2006.140.07:42:01.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:42:01.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:42:01.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:42:01.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:01.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:42:01.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:42:01.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:42:01.60#ibcon#[27=USB\r\n] 2006.140.07:42:01.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:42:01.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:42:01.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:42:01.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:42:01.63$vc4f8/vblo=4,712.99 2006.140.07:42:01.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:42:01.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:42:01.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:01.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:42:01.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:42:01.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:42:01.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:42:01.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:42:01.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:42:01.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:42:01.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:42:01.69$vc4f8/vb=4,4 2006.140.07:42:01.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:42:01.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:42:01.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:01.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:42:01.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:42:01.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:42:01.77#ibcon#[27=AT04-04\r\n] 2006.140.07:42:01.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:42:01.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:42:01.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:42:01.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:01.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:42:01.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:42:01.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:42:01.94#ibcon#[27=USB\r\n] 2006.140.07:42:01.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:42:01.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:42:01.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:42:01.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:42:01.97$vc4f8/vblo=5,744.99 2006.140.07:42:01.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:42:01.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:42:01.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:01.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:42:01.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:42:01.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:42:01.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:42:02.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:42:02.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:42:02.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:42:02.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:42:02.03$vc4f8/vb=5,4 2006.140.07:42:02.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:42:02.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:42:02.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:02.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:42:02.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:42:02.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:42:02.11#ibcon#[27=AT05-04\r\n] 2006.140.07:42:02.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:42:02.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:42:02.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:42:02.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:02.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:42:02.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:42:02.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:42:02.28#ibcon#[27=USB\r\n] 2006.140.07:42:02.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:42:02.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:42:02.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:42:02.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:42:02.31$vc4f8/vblo=6,752.99 2006.140.07:42:02.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:42:02.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:42:02.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:42:02.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:42:02.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:42:02.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:42:02.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:42:02.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:42:02.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:42:02.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:42:02.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:42:02.37$vc4f8/vb=6,4 2006.140.07:42:02.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:42:02.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:42:02.37#ibcon#ireg 11 cls_cnt 2 2006.140.07:42:02.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:42:02.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:42:02.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:42:02.45#ibcon#[27=AT06-04\r\n] 2006.140.07:42:02.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:42:02.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:42:02.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:42:02.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:42:02.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:42:02.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:42:02.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:42:02.62#ibcon#[27=USB\r\n] 2006.140.07:42:02.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:42:02.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:42:02.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:42:02.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:42:02.65$vc4f8/vabw=wide 2006.140.07:42:02.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:42:02.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:42:02.65#ibcon#ireg 8 cls_cnt 0 2006.140.07:42:02.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:42:02.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:42:02.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:42:02.67#ibcon#[25=BW32\r\n] 2006.140.07:42:02.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:42:02.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:42:02.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:42:02.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:42:02.70$vc4f8/vbbw=wide 2006.140.07:42:02.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:42:02.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:42:02.70#ibcon#ireg 8 cls_cnt 0 2006.140.07:42:02.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:42:02.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:42:02.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:42:02.79#ibcon#[27=BW32\r\n] 2006.140.07:42:02.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:42:02.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:42:02.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:42:02.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:42:02.82$4f8m12a/ifd4f 2006.140.07:42:02.82$ifd4f/lo= 2006.140.07:42:02.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:42:02.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:42:02.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:42:02.82$ifd4f/patch= 2006.140.07:42:02.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:42:02.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:42:02.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:42:02.82$4f8m12a/"form=m,16.000,1:2 2006.140.07:42:02.82$4f8m12a/"tpicd 2006.140.07:42:02.82$4f8m12a/echo=off 2006.140.07:42:02.82$4f8m12a/xlog=off 2006.140.07:42:02.82:!2006.140.07:42:30 2006.140.07:42:14.14#trakl#Source acquired 2006.140.07:42:15.14#flagr#flagr/antenna,acquired 2006.140.07:42:30.00:preob 2006.140.07:42:31.14/onsource/TRACKING 2006.140.07:42:31.14:!2006.140.07:42:40 2006.140.07:42:40.00:data_valid=on 2006.140.07:42:40.00:midob 2006.140.07:42:40.14/onsource/TRACKING 2006.140.07:42:40.14/wx/24.22,993.6,86 2006.140.07:42:40.22/cable/+6.5000E-03 2006.140.07:42:41.31/va/01,08,usb,yes,32,33 2006.140.07:42:41.31/va/02,07,usb,yes,32,33 2006.140.07:42:41.31/va/03,06,usb,yes,34,34 2006.140.07:42:41.31/va/04,07,usb,yes,33,35 2006.140.07:42:41.31/va/05,07,usb,yes,32,34 2006.140.07:42:41.31/va/06,06,usb,yes,31,31 2006.140.07:42:41.31/va/07,06,usb,yes,31,31 2006.140.07:42:41.31/va/08,06,usb,yes,34,33 2006.140.07:42:41.54/valo/01,532.99,yes,locked 2006.140.07:42:41.54/valo/02,572.99,yes,locked 2006.140.07:42:41.54/valo/03,672.99,yes,locked 2006.140.07:42:41.54/valo/04,832.99,yes,locked 2006.140.07:42:41.54/valo/05,652.99,yes,locked 2006.140.07:42:41.54/valo/06,772.99,yes,locked 2006.140.07:42:41.54/valo/07,832.99,yes,locked 2006.140.07:42:41.54/valo/08,852.99,yes,locked 2006.140.07:42:42.63/vb/01,04,usb,yes,29,28 2006.140.07:42:42.63/vb/02,04,usb,yes,31,32 2006.140.07:42:42.63/vb/03,04,usb,yes,27,31 2006.140.07:42:42.63/vb/04,04,usb,yes,28,28 2006.140.07:42:42.63/vb/05,04,usb,yes,27,30 2006.140.07:42:42.63/vb/06,04,usb,yes,27,30 2006.140.07:42:42.63/vb/07,04,usb,yes,29,29 2006.140.07:42:42.63/vb/08,04,usb,yes,27,30 2006.140.07:42:42.86/vblo/01,632.99,yes,locked 2006.140.07:42:42.86/vblo/02,640.99,yes,locked 2006.140.07:42:42.86/vblo/03,656.99,yes,locked 2006.140.07:42:42.86/vblo/04,712.99,yes,locked 2006.140.07:42:42.86/vblo/05,744.99,yes,locked 2006.140.07:42:42.86/vblo/06,752.99,yes,locked 2006.140.07:42:42.86/vblo/07,734.99,yes,locked 2006.140.07:42:42.86/vblo/08,744.99,yes,locked 2006.140.07:42:43.01/vabw/8 2006.140.07:42:43.16/vbbw/8 2006.140.07:42:43.25/xfe/off,on,16.0 2006.140.07:42:43.64/ifatt/23,28,28,28 2006.140.07:42:44.10/fmout-gps/S +1.08E-07 2006.140.07:42:44.17:!2006.140.07:43:40 2006.140.07:43:40.00:data_valid=off 2006.140.07:43:40.00:postob 2006.140.07:43:40.20/cable/+6.4988E-03 2006.140.07:43:40.20/wx/24.20,993.6,86 2006.140.07:43:41.10/fmout-gps/S +1.08E-07 2006.140.07:43:41.10:scan_name=140-0745,k06140,100 2006.140.07:43:41.10:source=0458-020,050112.81,-015914.3,2000.0,ccw 2006.140.07:43:41.14#flagr#flagr/antenna,new-source 2006.140.07:43:42.14:checkk5 2006.140.07:43:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:43:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:43:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:43:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:43:44.02/chk_obsdata//k5ts1/T1400742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:43:44.39/chk_obsdata//k5ts2/T1400742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:43:44.76/chk_obsdata//k5ts3/T1400742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:43:45.14/chk_obsdata//k5ts4/T1400742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:43:45.82/k5log//k5ts1_log_newline 2006.140.07:43:46.51/k5log//k5ts2_log_newline 2006.140.07:43:47.19/k5log//k5ts3_log_newline 2006.140.07:43:47.88/k5log//k5ts4_log_newline 2006.140.07:43:47.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:43:47.91:4f8m12a=1 2006.140.07:43:47.91$4f8m12a/echo=on 2006.140.07:43:47.91$4f8m12a/pcalon 2006.140.07:43:47.91$pcalon/"no phase cal control is implemented here 2006.140.07:43:47.91$4f8m12a/"tpicd=stop 2006.140.07:43:47.91$4f8m12a/vc4f8 2006.140.07:43:47.91$vc4f8/valo=1,532.99 2006.140.07:43:47.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:43:47.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:43:47.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:47.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:47.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:47.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:47.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:43:48.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:48.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:48.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:43:48.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:43:48.01$vc4f8/va=1,8 2006.140.07:43:48.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:43:48.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:43:48.01#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:48.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:48.01#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:48.01#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:48.04#ibcon#[25=AT01-08\r\n] 2006.140.07:43:48.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:48.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:48.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:43:48.08#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:48.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:48.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:48.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:48.22#ibcon#[25=USB\r\n] 2006.140.07:43:48.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:48.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:48.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:43:48.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:43:48.27$vc4f8/valo=2,572.99 2006.140.07:43:48.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:43:48.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:43:48.27#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:48.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:48.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:48.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:48.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:43:48.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:48.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:48.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:43:48.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:43:48.34$vc4f8/va=2,7 2006.140.07:43:48.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:43:48.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:43:48.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:48.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:48.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:48.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:48.41#ibcon#[25=AT02-07\r\n] 2006.140.07:43:48.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:48.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:48.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:43:48.44#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:48.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:48.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:48.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:48.58#ibcon#[25=USB\r\n] 2006.140.07:43:48.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:48.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:48.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:43:48.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:43:48.63$vc4f8/valo=3,672.99 2006.140.07:43:48.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:43:48.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:43:48.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:48.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:48.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:48.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:48.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:43:48.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:48.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:48.70#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:43:48.70#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:43:48.70$vc4f8/va=3,6 2006.140.07:43:48.70#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:43:48.70#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:43:48.70#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:48.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:48.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:48.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:48.77#ibcon#[25=AT03-06\r\n] 2006.140.07:43:48.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:48.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:48.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:43:48.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:48.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:48.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:48.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:48.94#ibcon#[25=USB\r\n] 2006.140.07:43:48.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:48.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:48.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:43:48.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:43:48.97$vc4f8/valo=4,832.99 2006.140.07:43:48.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:43:48.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:43:48.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:48.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:48.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:48.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:48.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:43:49.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:49.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:49.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:43:49.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:43:49.03$vc4f8/va=4,7 2006.140.07:43:49.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:43:49.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:43:49.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:49.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:49.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:49.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:49.11#ibcon#[25=AT04-07\r\n] 2006.140.07:43:49.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:49.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:49.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:43:49.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:49.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:49.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:49.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:49.28#ibcon#[25=USB\r\n] 2006.140.07:43:49.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:49.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:49.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:43:49.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:43:49.31$vc4f8/valo=5,652.99 2006.140.07:43:49.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.07:43:49.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.07:43:49.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:49.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:49.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:49.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:49.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:43:49.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:49.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:49.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:43:49.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:43:49.37$vc4f8/va=5,7 2006.140.07:43:49.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.07:43:49.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.07:43:49.37#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:49.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:49.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:49.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:49.45#ibcon#[25=AT05-07\r\n] 2006.140.07:43:49.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:49.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:49.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.07:43:49.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:49.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:49.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:49.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:49.62#ibcon#[25=USB\r\n] 2006.140.07:43:49.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:49.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:49.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:43:49.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:43:49.65$vc4f8/valo=6,772.99 2006.140.07:43:49.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.07:43:49.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.07:43:49.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:49.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:49.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:49.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:43:49.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:49.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:49.71#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:43:49.71#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:43:49.71$vc4f8/va=6,6 2006.140.07:43:49.71#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.07:43:49.71#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.07:43:49.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:49.71#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:49.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:49.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:49.79#ibcon#[25=AT06-06\r\n] 2006.140.07:43:49.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:49.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:49.82#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.07:43:49.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:49.82#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:43:49.94#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:43:49.94#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:43:49.96#ibcon#[25=USB\r\n] 2006.140.07:43:49.99#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:43:49.99#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:43:49.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:43:49.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:43:49.99$vc4f8/valo=7,832.99 2006.140.07:43:49.99#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.07:43:49.99#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.07:43:49.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:49.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:43:49.99#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:43:49.99#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:43:50.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:43:50.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:43:50.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:43:50.05#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:43:50.05#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:43:50.05$vc4f8/va=7,6 2006.140.07:43:50.05#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.07:43:50.05#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.07:43:50.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:50.05#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:43:50.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:43:50.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:43:50.13#ibcon#[25=AT07-06\r\n] 2006.140.07:43:50.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:43:50.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:43:50.16#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.07:43:50.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:50.16#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:43:50.28#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:43:50.28#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:43:50.30#ibcon#[25=USB\r\n] 2006.140.07:43:50.33#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:43:50.33#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:43:50.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:43:50.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:43:50.33$vc4f8/valo=8,852.99 2006.140.07:43:50.33#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.07:43:50.33#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.07:43:50.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:50.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:43:50.33#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:43:50.33#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:43:50.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:43:50.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:43:50.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:43:50.39#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:43:50.39#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:43:50.39$vc4f8/va=8,6 2006.140.07:43:50.39#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.07:43:50.39#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.07:43:50.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:50.39#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:43:50.45#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:43:50.45#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:43:50.47#ibcon#[25=AT08-06\r\n] 2006.140.07:43:50.50#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:43:50.50#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:43:50.50#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.07:43:50.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:50.50#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:43:50.62#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:43:50.62#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:43:50.64#ibcon#[25=USB\r\n] 2006.140.07:43:50.67#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:43:50.67#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:43:50.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:43:50.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:43:50.67$vc4f8/vblo=1,632.99 2006.140.07:43:50.67#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.07:43:50.67#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.07:43:50.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:50.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:43:50.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:43:50.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:43:50.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:43:50.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:43:50.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:43:50.73#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:43:50.73#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:43:50.73$vc4f8/vb=1,4 2006.140.07:43:50.73#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.07:43:50.73#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.07:43:50.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:50.73#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:43:50.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:43:50.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:43:50.75#ibcon#[27=AT01-04\r\n] 2006.140.07:43:50.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:43:50.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:43:50.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.07:43:50.78#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:50.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:43:50.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:43:50.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:43:50.92#ibcon#[27=USB\r\n] 2006.140.07:43:50.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:43:50.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:43:50.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:43:50.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:43:50.95$vc4f8/vblo=2,640.99 2006.140.07:43:50.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:43:50.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:43:50.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:50.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:50.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:50.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:50.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:43:51.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:51.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:43:51.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:43:51.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:43:51.01$vc4f8/vb=2,4 2006.140.07:43:51.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:43:51.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:43:51.01#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:51.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:51.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:51.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:51.09#ibcon#[27=AT02-04\r\n] 2006.140.07:43:51.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:51.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:43:51.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:43:51.12#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:51.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:51.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:51.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:51.26#ibcon#[27=USB\r\n] 2006.140.07:43:51.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:51.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:43:51.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:43:51.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:43:51.29$vc4f8/vblo=3,656.99 2006.140.07:43:51.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:43:51.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:43:51.29#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:51.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:51.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:51.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:51.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:43:51.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:51.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:43:51.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:43:51.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:43:51.35$vc4f8/vb=3,4 2006.140.07:43:51.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:43:51.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:43:51.35#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:51.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:51.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:51.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:51.43#ibcon#[27=AT03-04\r\n] 2006.140.07:43:51.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:51.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:43:51.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:43:51.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:51.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:51.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:51.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:51.60#ibcon#[27=USB\r\n] 2006.140.07:43:51.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:51.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:43:51.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:43:51.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:43:51.63$vc4f8/vblo=4,712.99 2006.140.07:43:51.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:43:51.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:43:51.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:51.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:51.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:51.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:43:51.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:51.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:43:51.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:43:51.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:43:51.69$vc4f8/vb=4,4 2006.140.07:43:51.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:43:51.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:43:51.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:51.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:51.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:51.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:51.77#ibcon#[27=AT04-04\r\n] 2006.140.07:43:51.80#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:51.80#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:43:51.80#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:43:51.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:51.80#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:51.92#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:51.92#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:51.94#ibcon#[27=USB\r\n] 2006.140.07:43:51.97#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:51.97#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:43:51.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:43:51.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:43:51.97$vc4f8/vblo=5,744.99 2006.140.07:43:51.97#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:43:51.97#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:43:51.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:51.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:51.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:51.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:43:52.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:52.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:43:52.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:43:52.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:43:52.03$vc4f8/vb=5,4 2006.140.07:43:52.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:43:52.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:43:52.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:52.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:52.09#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:52.09#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:52.11#ibcon#[27=AT05-04\r\n] 2006.140.07:43:52.14#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:52.14#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:43:52.14#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:43:52.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:52.14#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:52.26#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:52.26#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:52.28#ibcon#[27=USB\r\n] 2006.140.07:43:52.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:52.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:43:52.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:43:52.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:43:52.31$vc4f8/vblo=6,752.99 2006.140.07:43:52.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.07:43:52.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.07:43:52.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:43:52.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:52.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:52.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:43:52.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:52.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:43:52.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:43:52.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:43:52.37$vc4f8/vb=6,4 2006.140.07:43:52.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.07:43:52.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.07:43:52.37#ibcon#ireg 11 cls_cnt 2 2006.140.07:43:52.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:52.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:52.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:52.45#ibcon#[27=AT06-04\r\n] 2006.140.07:43:52.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:52.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:43:52.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.07:43:52.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:43:52.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:52.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:52.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:52.62#ibcon#[27=USB\r\n] 2006.140.07:43:52.65#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:52.65#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:43:52.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:43:52.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:43:52.65$vc4f8/vabw=wide 2006.140.07:43:52.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.07:43:52.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.07:43:52.65#ibcon#ireg 8 cls_cnt 0 2006.140.07:43:52.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:52.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:52.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:52.67#ibcon#[25=BW32\r\n] 2006.140.07:43:52.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:52.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:43:52.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:43:52.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:43:52.70$vc4f8/vbbw=wide 2006.140.07:43:52.70#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:43:52.70#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:43:52.70#ibcon#ireg 8 cls_cnt 0 2006.140.07:43:52.70#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:43:52.77#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:43:52.77#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:43:52.79#ibcon#[27=BW32\r\n] 2006.140.07:43:52.82#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:43:52.82#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:43:52.82#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:43:52.82#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:43:52.82$4f8m12a/ifd4f 2006.140.07:43:52.82$ifd4f/lo= 2006.140.07:43:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:43:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:43:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:43:52.82$ifd4f/patch= 2006.140.07:43:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:43:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:43:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:43:52.82$4f8m12a/"form=m,16.000,1:2 2006.140.07:43:52.82$4f8m12a/"tpicd 2006.140.07:43:52.82$4f8m12a/echo=off 2006.140.07:43:52.82$4f8m12a/xlog=off 2006.140.07:43:52.82:!2006.140.07:44:50 2006.140.07:44:35.14#trakl#Source acquired 2006.140.07:44:35.14#flagr#flagr/antenna,acquired 2006.140.07:44:50.00:preob 2006.140.07:44:51.14/onsource/TRACKING 2006.140.07:44:51.14:!2006.140.07:45:00 2006.140.07:45:00.00:data_valid=on 2006.140.07:45:00.00:midob 2006.140.07:45:00.14/onsource/TRACKING 2006.140.07:45:00.14/wx/24.18,993.7,86 2006.140.07:45:00.27/cable/+6.4985E-03 2006.140.07:45:01.36/va/01,08,usb,yes,44,46 2006.140.07:45:01.36/va/02,07,usb,yes,45,46 2006.140.07:45:01.36/va/03,06,usb,yes,47,48 2006.140.07:45:01.36/va/04,07,usb,yes,46,49 2006.140.07:45:01.36/va/05,07,usb,yes,46,49 2006.140.07:45:01.36/va/06,06,usb,yes,46,45 2006.140.07:45:01.36/va/07,06,usb,yes,46,46 2006.140.07:45:01.36/va/08,06,usb,yes,49,48 2006.140.07:45:01.59/valo/01,532.99,yes,locked 2006.140.07:45:01.59/valo/02,572.99,yes,locked 2006.140.07:45:01.59/valo/03,672.99,yes,locked 2006.140.07:45:01.59/valo/04,832.99,yes,locked 2006.140.07:45:01.59/valo/05,652.99,yes,locked 2006.140.07:45:01.59/valo/06,772.99,yes,locked 2006.140.07:45:01.59/valo/07,832.99,yes,locked 2006.140.07:45:01.59/valo/08,852.99,yes,locked 2006.140.07:45:02.68/vb/01,04,usb,yes,31,29 2006.140.07:45:02.68/vb/02,04,usb,yes,32,34 2006.140.07:45:02.68/vb/03,04,usb,yes,29,32 2006.140.07:45:02.68/vb/04,04,usb,yes,30,30 2006.140.07:45:02.68/vb/05,04,usb,yes,28,32 2006.140.07:45:02.68/vb/06,04,usb,yes,29,32 2006.140.07:45:02.68/vb/07,04,usb,yes,31,31 2006.140.07:45:02.68/vb/08,04,usb,yes,29,32 2006.140.07:45:02.91/vblo/01,632.99,yes,locked 2006.140.07:45:02.91/vblo/02,640.99,yes,locked 2006.140.07:45:02.91/vblo/03,656.99,yes,locked 2006.140.07:45:02.91/vblo/04,712.99,yes,locked 2006.140.07:45:02.91/vblo/05,744.99,yes,locked 2006.140.07:45:02.91/vblo/06,752.99,yes,locked 2006.140.07:45:02.91/vblo/07,734.99,yes,locked 2006.140.07:45:02.91/vblo/08,744.99,yes,locked 2006.140.07:45:03.06/vabw/8 2006.140.07:45:03.21/vbbw/8 2006.140.07:45:03.30/xfe/off,on,15.0 2006.140.07:45:03.67/ifatt/23,28,28,28 2006.140.07:45:04.09/fmout-gps/S +1.07E-07 2006.140.07:45:04.13:!2006.140.07:46:40 2006.140.07:46:40.00:data_valid=off 2006.140.07:46:40.00:postob 2006.140.07:46:40.16/cable/+6.4995E-03 2006.140.07:46:40.16/wx/24.16,993.7,87 2006.140.07:46:41.09/fmout-gps/S +1.08E-07 2006.140.07:46:41.09:scan_name=140-0748,k06140,60 2006.140.07:46:41.09:source=0955+476,095819.67,472507.8,2000.0,cw 2006.140.07:46:42.13#flagr#flagr/antenna,new-source 2006.140.07:46:42.13:checkk5 2006.140.07:46:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:46:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:46:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:46:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:46:44.00/chk_obsdata//k5ts1/T1400745??a.dat file size is correct (nominal:800MB, actual:800MB). 2006.140.07:46:44.37/chk_obsdata//k5ts2/T1400745??b.dat file size is correct (nominal:800MB, actual:800MB). 2006.140.07:46:44.74/chk_obsdata//k5ts3/T1400745??c.dat file size is correct (nominal:800MB, actual:800MB). 2006.140.07:46:45.12/chk_obsdata//k5ts4/T1400745??d.dat file size is correct (nominal:800MB, actual:800MB). 2006.140.07:46:45.82/k5log//k5ts1_log_newline 2006.140.07:46:46.53/k5log//k5ts2_log_newline 2006.140.07:46:47.23/k5log//k5ts3_log_newline 2006.140.07:46:47.92/k5log//k5ts4_log_newline 2006.140.07:46:47.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:46:47.95:4f8m12a=1 2006.140.07:46:47.95$4f8m12a/echo=on 2006.140.07:46:47.95$4f8m12a/pcalon 2006.140.07:46:47.95$pcalon/"no phase cal control is implemented here 2006.140.07:46:47.95$4f8m12a/"tpicd=stop 2006.140.07:46:47.95$4f8m12a/vc4f8 2006.140.07:46:47.95$vc4f8/valo=1,532.99 2006.140.07:46:47.95#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:46:47.95#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:46:47.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:47.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:47.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:47.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:47.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:46:48.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:48.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:48.05#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:46:48.05#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:46:48.05$vc4f8/va=1,8 2006.140.07:46:48.05#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.07:46:48.05#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.07:46:48.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:48.05#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:48.05#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:48.05#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:48.08#ibcon#[25=AT01-08\r\n] 2006.140.07:46:48.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:48.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:48.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.07:46:48.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:48.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:48.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:48.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:48.25#ibcon#[25=USB\r\n] 2006.140.07:46:48.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:48.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:48.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:46:48.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:46:48.28$vc4f8/valo=2,572.99 2006.140.07:46:48.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:46:48.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:46:48.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:48.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:48.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:48.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:48.31#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:46:48.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:48.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:48.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:46:48.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:46:48.36$vc4f8/va=2,7 2006.140.07:46:48.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.07:46:48.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.07:46:48.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:48.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:48.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:48.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:48.42#ibcon#[25=AT02-07\r\n] 2006.140.07:46:48.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:48.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:48.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.07:46:48.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:48.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:48.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:48.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:48.59#ibcon#[25=USB\r\n] 2006.140.07:46:48.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:48.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:48.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:46:48.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:46:48.62$vc4f8/valo=3,672.99 2006.140.07:46:48.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:46:48.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:46:48.62#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:48.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:48.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:48.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:48.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:46:48.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:48.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:48.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:46:48.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:46:48.70$vc4f8/va=3,6 2006.140.07:46:48.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:46:48.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:46:48.70#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:48.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:48.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:48.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:48.76#ibcon#[25=AT03-06\r\n] 2006.140.07:46:48.78#abcon#<5=/08 2.3 8.0 24.16 87 993.7\r\n> 2006.140.07:46:48.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:48.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:48.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:46:48.79#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:48.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:48.80#abcon#{5=INTERFACE CLEAR} 2006.140.07:46:48.86#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:46:48.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:48.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:48.93#ibcon#[25=USB\r\n] 2006.140.07:46:48.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:48.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:48.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:46:48.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:46:48.96$vc4f8/valo=4,832.99 2006.140.07:46:48.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.07:46:48.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.07:46:48.96#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:48.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:48.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:48.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:48.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:46:49.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:49.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:49.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:46:49.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:46:49.02$vc4f8/va=4,7 2006.140.07:46:49.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.07:46:49.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.07:46:49.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:49.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:49.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:49.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:49.10#ibcon#[25=AT04-07\r\n] 2006.140.07:46:49.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:49.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:49.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.07:46:49.13#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:49.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:49.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:49.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:49.27#ibcon#[25=USB\r\n] 2006.140.07:46:49.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:49.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:49.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:46:49.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:46:49.30$vc4f8/valo=5,652.99 2006.140.07:46:49.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.07:46:49.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.07:46:49.30#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:49.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:49.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:49.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:49.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:46:49.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:49.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:49.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:46:49.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:46:49.36$vc4f8/va=5,7 2006.140.07:46:49.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.07:46:49.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.07:46:49.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:49.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:49.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:49.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:49.44#ibcon#[25=AT05-07\r\n] 2006.140.07:46:49.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:49.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:49.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.07:46:49.47#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:49.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:49.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:49.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:49.61#ibcon#[25=USB\r\n] 2006.140.07:46:49.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:49.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:49.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:46:49.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:46:49.64$vc4f8/valo=6,772.99 2006.140.07:46:49.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.07:46:49.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.07:46:49.64#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:49.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:49.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:49.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:49.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:46:49.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:49.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:49.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:46:49.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:46:49.72$vc4f8/va=6,6 2006.140.07:46:49.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.07:46:49.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.07:46:49.72#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:49.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:49.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:49.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:49.78#ibcon#[25=AT06-06\r\n] 2006.140.07:46:49.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:49.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:49.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.07:46:49.81#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:49.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:46:49.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:46:49.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:46:49.95#ibcon#[25=USB\r\n] 2006.140.07:46:49.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:46:49.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:46:49.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:46:49.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:46:49.98$vc4f8/valo=7,832.99 2006.140.07:46:49.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:46:49.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:46:49.98#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:49.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:46:49.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:46:49.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:46:50.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:46:50.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:46:50.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:46:50.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:46:50.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:46:50.04$vc4f8/va=7,6 2006.140.07:46:50.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.07:46:50.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.07:46:50.04#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:50.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:46:50.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:46:50.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:46:50.12#ibcon#[25=AT07-06\r\n] 2006.140.07:46:50.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:46:50.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:46:50.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.07:46:50.15#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:50.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:46:50.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:46:50.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:46:50.29#ibcon#[25=USB\r\n] 2006.140.07:46:50.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:46:50.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:46:50.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:46:50.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:46:50.32$vc4f8/valo=8,852.99 2006.140.07:46:50.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.07:46:50.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.07:46:50.32#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:50.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:46:50.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:46:50.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:46:50.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:46:50.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:46:50.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:46:50.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:46:50.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:46:50.38$vc4f8/va=8,6 2006.140.07:46:50.38#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.07:46:50.38#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.07:46:50.38#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:50.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:46:50.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:46:50.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:46:50.46#ibcon#[25=AT08-06\r\n] 2006.140.07:46:50.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:46:50.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:46:50.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.07:46:50.49#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:50.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:46:50.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:46:50.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:46:50.63#ibcon#[25=USB\r\n] 2006.140.07:46:50.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:46:50.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:46:50.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:46:50.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:46:50.66$vc4f8/vblo=1,632.99 2006.140.07:46:50.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:46:50.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:46:50.66#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:50.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:50.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:50.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:50.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:46:50.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:50.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:46:50.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:46:50.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:46:50.72$vc4f8/vb=1,4 2006.140.07:46:50.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.07:46:50.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.07:46:50.72#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:50.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:50.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:50.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:50.74#ibcon#[27=AT01-04\r\n] 2006.140.07:46:50.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:50.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:46:50.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.07:46:50.77#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:50.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:50.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:50.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:50.91#ibcon#[27=USB\r\n] 2006.140.07:46:50.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:50.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:46:50.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:46:50.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:46:50.94$vc4f8/vblo=2,640.99 2006.140.07:46:50.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:46:50.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:46:50.94#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:50.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:50.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:50.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:50.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:46:51.00#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:51.00#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:46:51.00#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:46:51.00#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:46:51.00$vc4f8/vb=2,4 2006.140.07:46:51.00#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.07:46:51.00#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.07:46:51.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:51.00#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:51.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:51.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:51.08#ibcon#[27=AT02-04\r\n] 2006.140.07:46:51.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:51.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:46:51.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.07:46:51.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:51.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:51.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:51.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:51.25#ibcon#[27=USB\r\n] 2006.140.07:46:51.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:51.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:46:51.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:46:51.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:46:51.28$vc4f8/vblo=3,656.99 2006.140.07:46:51.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:46:51.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:46:51.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:51.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:51.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:51.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:51.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:46:51.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:51.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:46:51.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:46:51.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:46:51.34$vc4f8/vb=3,4 2006.140.07:46:51.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:46:51.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:46:51.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:51.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:51.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:51.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:51.42#ibcon#[27=AT03-04\r\n] 2006.140.07:46:51.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:51.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:46:51.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:46:51.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:51.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:51.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:51.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:51.59#ibcon#[27=USB\r\n] 2006.140.07:46:51.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:51.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:46:51.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:46:51.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:46:51.62$vc4f8/vblo=4,712.99 2006.140.07:46:51.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.07:46:51.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.07:46:51.62#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:51.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:46:51.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:46:51.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:46:51.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:46:51.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:46:51.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:46:51.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:46:51.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:46:51.68$vc4f8/vb=4,4 2006.140.07:46:51.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.07:46:51.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.07:46:51.68#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:51.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:46:51.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:46:51.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:46:51.76#ibcon#[27=AT04-04\r\n] 2006.140.07:46:51.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:46:51.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:46:51.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.07:46:51.79#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:51.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:46:51.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:46:51.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:46:51.93#ibcon#[27=USB\r\n] 2006.140.07:46:51.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:46:51.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:46:51.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:46:51.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:46:51.96$vc4f8/vblo=5,744.99 2006.140.07:46:51.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.07:46:51.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.07:46:51.96#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:51.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:51.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:51.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:51.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:46:52.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:52.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:46:52.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:46:52.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:46:52.02$vc4f8/vb=5,4 2006.140.07:46:52.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.07:46:52.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.07:46:52.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:52.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:52.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:52.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:52.10#ibcon#[27=AT05-04\r\n] 2006.140.07:46:52.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:52.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:46:52.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.07:46:52.13#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:52.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:52.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:52.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:52.27#ibcon#[27=USB\r\n] 2006.140.07:46:52.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:52.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:46:52.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:46:52.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:46:52.30$vc4f8/vblo=6,752.99 2006.140.07:46:52.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.07:46:52.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.07:46:52.30#ibcon#ireg 17 cls_cnt 0 2006.140.07:46:52.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:52.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:52.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:52.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:46:52.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:52.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:46:52.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:46:52.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:46:52.36$vc4f8/vb=6,4 2006.140.07:46:52.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.07:46:52.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.07:46:52.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:46:52.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:52.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:52.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:52.44#ibcon#[27=AT06-04\r\n] 2006.140.07:46:52.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:52.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:46:52.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.07:46:52.47#ibcon#ireg 7 cls_cnt 0 2006.140.07:46:52.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:52.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:52.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:52.61#ibcon#[27=USB\r\n] 2006.140.07:46:52.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:52.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:46:52.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:46:52.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:46:52.64$vc4f8/vabw=wide 2006.140.07:46:52.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.07:46:52.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.07:46:52.64#ibcon#ireg 8 cls_cnt 0 2006.140.07:46:52.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:52.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:52.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:52.66#ibcon#[25=BW32\r\n] 2006.140.07:46:52.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:52.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:46:52.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:46:52.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:46:52.69$vc4f8/vbbw=wide 2006.140.07:46:52.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:46:52.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:46:52.69#ibcon#ireg 8 cls_cnt 0 2006.140.07:46:52.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:46:52.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:46:52.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:46:52.78#ibcon#[27=BW32\r\n] 2006.140.07:46:52.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:46:52.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:46:52.81#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:46:52.81#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:46:52.81$4f8m12a/ifd4f 2006.140.07:46:52.81$ifd4f/lo= 2006.140.07:46:52.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:46:52.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:46:52.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:46:52.81$ifd4f/patch= 2006.140.07:46:52.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:46:52.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:46:52.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:46:52.81$4f8m12a/"form=m,16.000,1:2 2006.140.07:46:52.81$4f8m12a/"tpicd 2006.140.07:46:52.81$4f8m12a/echo=off 2006.140.07:46:52.81$4f8m12a/xlog=off 2006.140.07:46:52.81:!2006.140.07:48:00 2006.140.07:47:38.14#trakl#Source acquired 2006.140.07:47:40.14#flagr#flagr/antenna,acquired 2006.140.07:48:00.00:preob 2006.140.07:48:00.14/onsource/TRACKING 2006.140.07:48:00.14:!2006.140.07:48:10 2006.140.07:48:10.00:data_valid=on 2006.140.07:48:10.00:midob 2006.140.07:48:10.14/onsource/TRACKING 2006.140.07:48:10.14/wx/24.15,993.8,87 2006.140.07:48:10.32/cable/+6.4997E-03 2006.140.07:48:11.41/va/01,08,usb,yes,38,40 2006.140.07:48:11.41/va/02,07,usb,yes,38,40 2006.140.07:48:11.41/va/03,06,usb,yes,41,41 2006.140.07:48:11.41/va/04,07,usb,yes,40,42 2006.140.07:48:11.41/va/05,07,usb,yes,40,42 2006.140.07:48:11.41/va/06,06,usb,yes,39,39 2006.140.07:48:11.41/va/07,06,usb,yes,40,40 2006.140.07:48:11.41/va/08,06,usb,yes,43,42 2006.140.07:48:11.64/valo/01,532.99,yes,locked 2006.140.07:48:11.64/valo/02,572.99,yes,locked 2006.140.07:48:11.64/valo/03,672.99,yes,locked 2006.140.07:48:11.64/valo/04,832.99,yes,locked 2006.140.07:48:11.64/valo/05,652.99,yes,locked 2006.140.07:48:11.64/valo/06,772.99,yes,locked 2006.140.07:48:11.64/valo/07,832.99,yes,locked 2006.140.07:48:11.64/valo/08,852.99,yes,locked 2006.140.07:48:12.73/vb/01,04,usb,yes,29,28 2006.140.07:48:12.73/vb/02,04,usb,yes,31,32 2006.140.07:48:12.73/vb/03,04,usb,yes,27,31 2006.140.07:48:12.73/vb/04,04,usb,yes,28,28 2006.140.07:48:12.73/vb/05,04,usb,yes,27,31 2006.140.07:48:12.73/vb/06,04,usb,yes,28,31 2006.140.07:48:12.73/vb/07,04,usb,yes,30,30 2006.140.07:48:12.73/vb/08,04,usb,yes,27,31 2006.140.07:48:12.97/vblo/01,632.99,yes,locked 2006.140.07:48:12.97/vblo/02,640.99,yes,locked 2006.140.07:48:12.97/vblo/03,656.99,yes,locked 2006.140.07:48:12.97/vblo/04,712.99,yes,locked 2006.140.07:48:12.97/vblo/05,744.99,yes,locked 2006.140.07:48:12.97/vblo/06,752.99,yes,locked 2006.140.07:48:12.97/vblo/07,734.99,yes,locked 2006.140.07:48:12.97/vblo/08,744.99,yes,locked 2006.140.07:48:13.12/vabw/8 2006.140.07:48:13.27/vbbw/8 2006.140.07:48:13.36/xfe/off,on,16.2 2006.140.07:48:13.73/ifatt/23,28,28,28 2006.140.07:48:14.10/fmout-gps/S +1.08E-07 2006.140.07:48:14.17:!2006.140.07:49:10 2006.140.07:48:36.14#trakl#Off source 2006.140.07:48:36.14?ERROR st -7 Antenna off-source! 2006.140.07:48:36.14#trakl#az 39.275 el 74.344 azerr*cos(el) -0.0000 elerr 0.0213 2006.140.07:48:36.14#flagr#flagr/antenna,off-source 2006.140.07:48:44.14#trakl#Source re-acquired 2006.140.07:48:45.14#flagr#flagr/antenna,re-acquired 2006.140.07:48:46.14#trakl#Off source 2006.140.07:48:46.14?ERROR st -7 Antenna off-source! 2006.140.07:48:46.14#trakl#az 39.206 el 74.365 azerr*cos(el) 0.0012 elerr 0.0169 2006.140.07:48:48.14#flagr#flagr/antenna,off-source 2006.140.07:48:52.14#trakl#Source re-acquired 2006.140.07:48:54.14#flagr#flagr/antenna,re-acquired 2006.140.07:49:10.00:data_valid=off 2006.140.07:49:10.00:postob 2006.140.07:49:10.11/cable/+6.4996E-03 2006.140.07:49:10.11/wx/24.14,993.9,87 2006.140.07:49:11.10/fmout-gps/S +1.07E-07 2006.140.07:49:11.10:scan_name=140-0750,k06140,60 2006.140.07:49:11.10:source=1357+769,135755.37,764321.1,2000.0,cw 2006.140.07:49:11.14#flagr#flagr/antenna,new-source 2006.140.07:49:12.14:checkk5 2006.140.07:49:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:49:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:49:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:49:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:49:14.00/chk_obsdata//k5ts1/T1400748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:49:14.37/chk_obsdata//k5ts2/T1400748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:49:14.75/chk_obsdata//k5ts3/T1400748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:49:15.12/chk_obsdata//k5ts4/T1400748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:49:15.81/k5log//k5ts1_log_newline 2006.140.07:49:16.50/k5log//k5ts2_log_newline 2006.140.07:49:17.19/k5log//k5ts3_log_newline 2006.140.07:49:17.88/k5log//k5ts4_log_newline 2006.140.07:49:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:49:17.90:4f8m12a=1 2006.140.07:49:17.90$4f8m12a/echo=on 2006.140.07:49:17.90$4f8m12a/pcalon 2006.140.07:49:17.90$pcalon/"no phase cal control is implemented here 2006.140.07:49:17.90$4f8m12a/"tpicd=stop 2006.140.07:49:17.90$4f8m12a/vc4f8 2006.140.07:49:17.90$vc4f8/valo=1,532.99 2006.140.07:49:17.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:49:17.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:49:17.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:17.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:17.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:17.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:49:18.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:18.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:18.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:49:18.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:49:18.00$vc4f8/va=1,8 2006.140.07:49:18.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:49:18.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:49:18.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:18.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:18.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:18.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:18.03#ibcon#[25=AT01-08\r\n] 2006.140.07:49:18.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:18.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:18.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:49:18.06#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:18.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:18.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:18.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:18.20#ibcon#[25=USB\r\n] 2006.140.07:49:18.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:18.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:18.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:49:18.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:49:18.23$vc4f8/valo=2,572.99 2006.140.07:49:18.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:49:18.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:49:18.23#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:18.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:18.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:18.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:49:18.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:18.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:18.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:49:18.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:49:18.29$vc4f8/va=2,7 2006.140.07:49:18.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:49:18.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:49:18.29#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:18.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:18.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:18.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:18.37#ibcon#[25=AT02-07\r\n] 2006.140.07:49:18.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:18.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:18.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:49:18.40#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:18.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:18.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:18.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:18.54#ibcon#[25=USB\r\n] 2006.140.07:49:18.59#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:18.59#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:18.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:49:18.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:49:18.59$vc4f8/valo=3,672.99 2006.140.07:49:18.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:49:18.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:49:18.59#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:18.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:49:18.59#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:49:18.59#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:49:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:49:18.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:49:18.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:49:18.66#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:49:18.66#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:49:18.66$vc4f8/va=3,6 2006.140.07:49:18.66#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:49:18.66#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:49:18.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:18.66#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:49:18.71#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:49:18.71#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:49:18.73#ibcon#[25=AT03-06\r\n] 2006.140.07:49:18.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:49:18.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:49:18.76#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:49:18.76#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:18.76#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:49:18.88#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:49:18.88#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:49:18.90#ibcon#[25=USB\r\n] 2006.140.07:49:18.93#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:49:18.93#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:49:18.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:49:18.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:49:18.93$vc4f8/valo=4,832.99 2006.140.07:49:18.93#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:49:18.93#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:49:18.93#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:18.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:18.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:18.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:18.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:49:18.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:18.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:18.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:49:18.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:49:18.99$vc4f8/va=4,7 2006.140.07:49:18.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:49:18.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:49:18.99#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:18.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:19.05#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:19.05#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:19.07#ibcon#[25=AT04-07\r\n] 2006.140.07:49:19.10#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:19.10#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:19.10#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:49:19.10#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:19.10#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:19.22#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:19.22#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:19.24#ibcon#[25=USB\r\n] 2006.140.07:49:19.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:19.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:19.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:49:19.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:49:19.27$vc4f8/valo=5,652.99 2006.140.07:49:19.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:49:19.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:49:19.27#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:19.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:19.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:19.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:19.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:49:19.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:19.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:19.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:49:19.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:49:19.33$vc4f8/va=5,7 2006.140.07:49:19.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:49:19.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:49:19.33#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:19.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:19.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:19.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:19.41#ibcon#[25=AT05-07\r\n] 2006.140.07:49:19.45#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:19.45#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:19.45#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:49:19.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:19.45#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:19.57#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:19.57#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:19.59#ibcon#[25=USB\r\n] 2006.140.07:49:19.62#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:19.62#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:19.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:49:19.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:49:19.62$vc4f8/valo=6,772.99 2006.140.07:49:19.62#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:49:19.62#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:49:19.62#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:19.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:19.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:19.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:19.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:49:19.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:19.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:19.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:49:19.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:49:19.68$vc4f8/va=6,6 2006.140.07:49:19.68#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:49:19.68#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:49:19.68#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:19.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:19.74#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:19.74#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:19.76#ibcon#[25=AT06-06\r\n] 2006.140.07:49:19.79#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:19.79#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:19.79#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:49:19.79#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:19.79#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:19.91#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:19.91#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:19.93#ibcon#[25=USB\r\n] 2006.140.07:49:19.96#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:19.96#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:19.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:49:19.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:49:19.96$vc4f8/valo=7,832.99 2006.140.07:49:19.96#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:49:19.96#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:49:19.96#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:19.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:19.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:19.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:49:20.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:20.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:20.02#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:49:20.02#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:49:20.02$vc4f8/va=7,6 2006.140.07:49:20.02#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.07:49:20.02#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.07:49:20.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:20.02#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:20.08#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:20.08#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:20.10#ibcon#[25=AT07-06\r\n] 2006.140.07:49:20.13#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:20.13#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:20.13#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.07:49:20.13#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:20.13#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:49:20.25#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:49:20.25#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:49:20.27#ibcon#[25=USB\r\n] 2006.140.07:49:20.30#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:49:20.30#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:49:20.30#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:49:20.30#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:49:20.30$vc4f8/valo=8,852.99 2006.140.07:49:20.30#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.07:49:20.30#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.07:49:20.30#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:20.30#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:49:20.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:49:20.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:49:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:49:20.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:49:20.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:49:20.36#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:49:20.36#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:49:20.36$vc4f8/va=8,6 2006.140.07:49:20.36#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.07:49:20.36#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.07:49:20.36#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:20.36#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:49:20.42#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:49:20.42#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:49:20.44#ibcon#[25=AT08-06\r\n] 2006.140.07:49:20.47#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:49:20.47#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:49:20.47#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.07:49:20.47#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:20.47#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:49:20.59#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:49:20.59#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:49:20.61#ibcon#[25=USB\r\n] 2006.140.07:49:20.64#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:49:20.64#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:49:20.64#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:49:20.64#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:49:20.64$vc4f8/vblo=1,632.99 2006.140.07:49:20.64#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.07:49:20.64#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.07:49:20.64#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:20.64#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:49:20.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:49:20.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:49:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:49:20.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:49:20.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:49:20.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:49:20.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:49:20.70$vc4f8/vb=1,4 2006.140.07:49:20.70#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.07:49:20.70#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.07:49:20.70#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:20.70#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:49:20.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:49:20.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:49:20.72#ibcon#[27=AT01-04\r\n] 2006.140.07:49:20.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:49:20.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:49:20.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.07:49:20.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:20.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:49:20.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:49:20.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:49:20.89#ibcon#[27=USB\r\n] 2006.140.07:49:20.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:49:20.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:49:20.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:49:20.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:49:20.92$vc4f8/vblo=2,640.99 2006.140.07:49:20.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:49:20.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:49:20.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:20.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:20.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:20.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:20.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:49:21.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:21.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:49:21.00#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:49:21.00#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:49:21.00$vc4f8/vb=2,4 2006.140.07:49:21.00#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:49:21.00#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:49:21.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:21.00#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:21.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:21.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:21.06#ibcon#[27=AT02-04\r\n] 2006.140.07:49:21.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:21.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:49:21.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:49:21.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:21.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:21.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:21.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:21.23#ibcon#[27=USB\r\n] 2006.140.07:49:21.26#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:21.26#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:49:21.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:49:21.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:49:21.26$vc4f8/vblo=3,656.99 2006.140.07:49:21.26#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:49:21.26#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:49:21.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:21.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:21.26#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:21.26#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:49:21.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:21.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:49:21.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:49:21.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:49:21.32$vc4f8/vb=3,4 2006.140.07:49:21.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:49:21.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:49:21.32#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:21.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:21.38#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:21.38#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:21.40#ibcon#[27=AT03-04\r\n] 2006.140.07:49:21.43#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:21.43#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:49:21.43#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:49:21.43#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:21.43#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:21.47#abcon#<5=/09 2.5 8.0 24.13 87 994.0\r\n> 2006.140.07:49:21.49#abcon#{5=INTERFACE CLEAR} 2006.140.07:49:21.55#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:49:21.55#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:21.55#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:21.57#ibcon#[27=USB\r\n] 2006.140.07:49:21.60#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:21.60#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:49:21.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:49:21.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:49:21.60$vc4f8/vblo=4,712.99 2006.140.07:49:21.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:49:21.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:49:21.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:21.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:21.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:21.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:49:21.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:21.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:49:21.66#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:49:21.66#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:49:21.66$vc4f8/vb=4,4 2006.140.07:49:21.66#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:49:21.66#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:49:21.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:21.66#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:21.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:21.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:21.74#ibcon#[27=AT04-04\r\n] 2006.140.07:49:21.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:21.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:49:21.77#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:49:21.77#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:21.77#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:21.89#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:21.89#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:21.91#ibcon#[27=USB\r\n] 2006.140.07:49:21.94#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:21.94#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:49:21.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:49:21.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:49:21.94$vc4f8/vblo=5,744.99 2006.140.07:49:21.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:49:21.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:49:21.94#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:21.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:21.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:21.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:49:22.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:22.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:49:22.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:49:22.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:49:22.00$vc4f8/vb=5,4 2006.140.07:49:22.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:49:22.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:49:22.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:22.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:22.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:22.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:22.08#ibcon#[27=AT05-04\r\n] 2006.140.07:49:22.11#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:22.11#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:49:22.11#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:49:22.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:22.11#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:22.23#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:22.23#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:22.25#ibcon#[27=USB\r\n] 2006.140.07:49:22.28#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:22.28#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:49:22.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:49:22.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:49:22.28$vc4f8/vblo=6,752.99 2006.140.07:49:22.28#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:49:22.28#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:49:22.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:49:22.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:22.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:22.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:49:22.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:22.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:49:22.34#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:49:22.34#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:49:22.34$vc4f8/vb=6,4 2006.140.07:49:22.34#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:49:22.34#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:49:22.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:49:22.34#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:22.40#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:22.40#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:22.42#ibcon#[27=AT06-04\r\n] 2006.140.07:49:22.45#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:22.45#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:49:22.45#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:49:22.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:49:22.45#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:22.57#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:22.57#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:22.59#ibcon#[27=USB\r\n] 2006.140.07:49:22.62#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:22.62#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:49:22.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:49:22.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:49:22.62$vc4f8/vabw=wide 2006.140.07:49:22.62#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:49:22.62#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:49:22.62#ibcon#ireg 8 cls_cnt 0 2006.140.07:49:22.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:22.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:22.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:22.64#ibcon#[25=BW32\r\n] 2006.140.07:49:22.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:22.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:49:22.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:49:22.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:49:22.67$vc4f8/vbbw=wide 2006.140.07:49:22.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.07:49:22.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.07:49:22.67#ibcon#ireg 8 cls_cnt 0 2006.140.07:49:22.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:49:22.74#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:49:22.74#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:49:22.76#ibcon#[27=BW32\r\n] 2006.140.07:49:22.79#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:49:22.79#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:49:22.79#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:49:22.79#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:49:22.79$4f8m12a/ifd4f 2006.140.07:49:22.79$ifd4f/lo= 2006.140.07:49:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:49:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:49:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:49:22.79$ifd4f/patch= 2006.140.07:49:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:49:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:49:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:49:22.79$4f8m12a/"form=m,16.000,1:2 2006.140.07:49:22.79$4f8m12a/"tpicd 2006.140.07:49:22.79$4f8m12a/echo=off 2006.140.07:49:22.79$4f8m12a/xlog=off 2006.140.07:49:22.79:!2006.140.07:49:50 2006.140.07:49:36.14#trakl#Source acquired 2006.140.07:49:38.14#flagr#flagr/antenna,acquired 2006.140.07:49:50.00:preob 2006.140.07:49:51.14/onsource/TRACKING 2006.140.07:49:51.14:!2006.140.07:50:00 2006.140.07:50:00.00:data_valid=on 2006.140.07:50:00.00:midob 2006.140.07:50:00.14/onsource/TRACKING 2006.140.07:50:00.14/wx/24.12,993.9,88 2006.140.07:50:00.23/cable/+6.4996E-03 2006.140.07:50:01.32/va/01,08,usb,yes,50,53 2006.140.07:50:01.32/va/02,07,usb,yes,51,53 2006.140.07:50:01.32/va/03,06,usb,yes,54,54 2006.140.07:50:01.32/va/04,07,usb,yes,52,56 2006.140.07:50:01.32/va/05,07,usb,yes,53,56 2006.140.07:50:01.32/va/06,06,usb,yes,53,52 2006.140.07:50:01.32/va/07,06,usb,yes,53,53 2006.140.07:50:01.32/va/08,06,usb,yes,56,55 2006.140.07:50:01.55/valo/01,532.99,yes,locked 2006.140.07:50:01.55/valo/02,572.99,yes,locked 2006.140.07:50:01.55/valo/03,672.99,yes,locked 2006.140.07:50:01.55/valo/04,832.99,yes,locked 2006.140.07:50:01.55/valo/05,652.99,yes,locked 2006.140.07:50:01.55/valo/06,772.99,yes,locked 2006.140.07:50:01.55/valo/07,832.99,yes,locked 2006.140.07:50:01.55/valo/08,852.99,yes,locked 2006.140.07:50:02.64/vb/01,04,usb,yes,30,29 2006.140.07:50:02.64/vb/02,04,usb,yes,32,34 2006.140.07:50:02.64/vb/03,04,usb,yes,29,32 2006.140.07:50:02.64/vb/04,04,usb,yes,30,30 2006.140.07:50:02.64/vb/05,04,usb,yes,28,32 2006.140.07:50:02.64/vb/06,04,usb,yes,29,32 2006.140.07:50:02.64/vb/07,04,usb,yes,31,31 2006.140.07:50:02.64/vb/08,04,usb,yes,29,32 2006.140.07:50:02.87/vblo/01,632.99,yes,locked 2006.140.07:50:02.87/vblo/02,640.99,yes,locked 2006.140.07:50:02.87/vblo/03,656.99,yes,locked 2006.140.07:50:02.87/vblo/04,712.99,yes,locked 2006.140.07:50:02.87/vblo/05,744.99,yes,locked 2006.140.07:50:02.87/vblo/06,752.99,yes,locked 2006.140.07:50:02.87/vblo/07,734.99,yes,locked 2006.140.07:50:02.87/vblo/08,744.99,yes,locked 2006.140.07:50:03.02/vabw/8 2006.140.07:50:03.17/vbbw/8 2006.140.07:50:03.26/xfe/off,on,14.7 2006.140.07:50:03.65/ifatt/23,28,28,28 2006.140.07:50:04.10/fmout-gps/S +1.09E-07 2006.140.07:50:04.17:!2006.140.07:51:00 2006.140.07:51:00.00:data_valid=off 2006.140.07:51:00.00:postob 2006.140.07:51:00.15/cable/+6.4998E-03 2006.140.07:51:00.15/wx/24.10,993.8,87 2006.140.07:51:01.10/fmout-gps/S +1.09E-07 2006.140.07:51:01.10:scan_name=140-0751,k06140,60 2006.140.07:51:01.10:source=1739+522,174036.98,521143.4,2000.0,cw 2006.140.07:51:01.14#flagr#flagr/antenna,new-source 2006.140.07:51:02.14:checkk5 2006.140.07:51:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:51:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:51:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:51:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:51:04.00/chk_obsdata//k5ts1/T1400750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:51:04.37/chk_obsdata//k5ts2/T1400750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:51:04.74/chk_obsdata//k5ts3/T1400750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:51:05.11/chk_obsdata//k5ts4/T1400750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:51:05.80/k5log//k5ts1_log_newline 2006.140.07:51:06.48/k5log//k5ts2_log_newline 2006.140.07:51:07.17/k5log//k5ts3_log_newline 2006.140.07:51:07.86/k5log//k5ts4_log_newline 2006.140.07:51:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:51:07.88:4f8m12a=1 2006.140.07:51:07.88$4f8m12a/echo=on 2006.140.07:51:07.88$4f8m12a/pcalon 2006.140.07:51:07.88$pcalon/"no phase cal control is implemented here 2006.140.07:51:07.88$4f8m12a/"tpicd=stop 2006.140.07:51:07.88$4f8m12a/vc4f8 2006.140.07:51:07.88$vc4f8/valo=1,532.99 2006.140.07:51:07.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:51:07.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:51:07.89#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:07.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:07.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:07.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:51:07.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:07.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:07.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:51:07.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:51:07.98$vc4f8/va=1,8 2006.140.07:51:07.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.07:51:07.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.07:51:07.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:07.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:07.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:07.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:08.01#ibcon#[25=AT01-08\r\n] 2006.140.07:51:08.05#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:08.05#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:08.05#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.07:51:08.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:08.05#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:08.17#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:08.17#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:08.19#ibcon#[25=USB\r\n] 2006.140.07:51:08.22#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:08.22#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:08.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:51:08.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:51:08.22$vc4f8/valo=2,572.99 2006.140.07:51:08.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:51:08.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:51:08.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:08.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:08.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:08.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:51:08.28#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:08.28#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:08.28#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:51:08.28#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:51:08.28$vc4f8/va=2,7 2006.140.07:51:08.28#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:51:08.28#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:51:08.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:08.28#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:08.34#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:08.34#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:08.36#ibcon#[25=AT02-07\r\n] 2006.140.07:51:08.39#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:08.39#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:08.39#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:51:08.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:08.39#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:08.51#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:08.51#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:08.53#ibcon#[25=USB\r\n] 2006.140.07:51:08.56#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:08.56#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:08.56#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:51:08.56#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:51:08.56$vc4f8/valo=3,672.99 2006.140.07:51:08.56#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:51:08.56#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:51:08.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:08.56#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:08.56#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:08.56#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:51:08.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:08.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:08.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:51:08.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:51:08.64$vc4f8/va=3,6 2006.140.07:51:08.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:51:08.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:51:08.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:08.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:08.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:08.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:08.70#ibcon#[25=AT03-06\r\n] 2006.140.07:51:08.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:08.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:08.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:51:08.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:08.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:08.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:08.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:08.87#ibcon#[25=USB\r\n] 2006.140.07:51:08.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:08.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:08.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:51:08.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:51:08.90$vc4f8/valo=4,832.99 2006.140.07:51:08.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:51:08.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:51:08.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:08.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:08.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:08.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:51:08.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:08.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:08.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:51:08.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:51:08.96$vc4f8/va=4,7 2006.140.07:51:08.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:51:08.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:51:08.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:08.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:09.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:09.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:09.04#ibcon#[25=AT04-07\r\n] 2006.140.07:51:09.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:09.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:09.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:51:09.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:09.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:09.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:09.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:09.21#ibcon#[25=USB\r\n] 2006.140.07:51:09.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:09.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:09.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:51:09.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:51:09.24$vc4f8/valo=5,652.99 2006.140.07:51:09.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:51:09.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:51:09.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:09.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:09.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:09.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:51:09.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:09.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:09.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:51:09.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:51:09.30$vc4f8/va=5,7 2006.140.07:51:09.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:51:09.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:51:09.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:09.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:09.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:09.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:09.38#ibcon#[25=AT05-07\r\n] 2006.140.07:51:09.41#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:09.41#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:09.41#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:51:09.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:09.41#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:09.53#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:09.53#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:09.55#ibcon#[25=USB\r\n] 2006.140.07:51:09.58#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:09.58#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:09.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:51:09.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:51:09.58$vc4f8/valo=6,772.99 2006.140.07:51:09.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:51:09.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:51:09.58#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:09.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:09.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:09.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:51:09.64#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:09.64#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:09.64#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:51:09.64#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:51:09.64$vc4f8/va=6,6 2006.140.07:51:09.64#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.07:51:09.64#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.07:51:09.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:09.64#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:09.70#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:09.70#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:09.72#ibcon#[25=AT06-06\r\n] 2006.140.07:51:09.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:09.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:09.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.07:51:09.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:09.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:51:09.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:51:09.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:51:09.89#ibcon#[25=USB\r\n] 2006.140.07:51:09.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:51:09.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.07:51:09.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:51:09.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:51:09.92$vc4f8/valo=7,832.99 2006.140.07:51:09.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.07:51:09.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.07:51:09.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:09.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:51:09.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:51:09.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:51:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:51:09.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:51:09.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.07:51:09.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:51:09.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:51:09.98$vc4f8/va=7,6 2006.140.07:51:09.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.07:51:09.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.07:51:09.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:09.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:51:10.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:51:10.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:51:10.06#ibcon#[25=AT07-06\r\n] 2006.140.07:51:10.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:51:10.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.07:51:10.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.07:51:10.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:10.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:51:10.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:51:10.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:51:10.23#ibcon#[25=USB\r\n] 2006.140.07:51:10.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:51:10.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.07:51:10.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:51:10.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:51:10.26$vc4f8/valo=8,852.99 2006.140.07:51:10.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.07:51:10.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.07:51:10.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:10.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:51:10.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:51:10.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:51:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:51:10.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:51:10.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.07:51:10.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:51:10.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:51:10.32$vc4f8/va=8,6 2006.140.07:51:10.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.07:51:10.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.07:51:10.32#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:10.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:51:10.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:51:10.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:51:10.40#ibcon#[25=AT08-06\r\n] 2006.140.07:51:10.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:51:10.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.07:51:10.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.07:51:10.44#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:10.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:51:10.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:51:10.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:51:10.58#ibcon#[25=USB\r\n] 2006.140.07:51:10.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:51:10.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.07:51:10.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:51:10.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:51:10.61$vc4f8/vblo=1,632.99 2006.140.07:51:10.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.07:51:10.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.07:51:10.61#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:10.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:51:10.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:51:10.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:51:10.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:51:10.67#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:51:10.67#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.07:51:10.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:51:10.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:51:10.67$vc4f8/vb=1,4 2006.140.07:51:10.67#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.07:51:10.67#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.07:51:10.67#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:10.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:51:10.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:51:10.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:51:10.69#ibcon#[27=AT01-04\r\n] 2006.140.07:51:10.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:51:10.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.07:51:10.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.07:51:10.72#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:10.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:51:10.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:51:10.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:51:10.86#ibcon#[27=USB\r\n] 2006.140.07:51:10.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:51:10.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.07:51:10.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:51:10.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:51:10.89$vc4f8/vblo=2,640.99 2006.140.07:51:10.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.07:51:10.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.07:51:10.89#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:10.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:10.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:10.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:10.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:51:10.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:10.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.07:51:10.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:51:10.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:51:10.95$vc4f8/vb=2,4 2006.140.07:51:10.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.07:51:10.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.07:51:10.95#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:10.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:11.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:11.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:11.03#ibcon#[27=AT02-04\r\n] 2006.140.07:51:11.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:11.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.07:51:11.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.07:51:11.06#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:11.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:11.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:11.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:11.22#ibcon#[27=USB\r\n] 2006.140.07:51:11.25#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:11.25#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.07:51:11.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:51:11.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:51:11.25$vc4f8/vblo=3,656.99 2006.140.07:51:11.25#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.07:51:11.25#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.07:51:11.25#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:11.25#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:11.25#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:11.25#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:51:11.31#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:11.31#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.07:51:11.31#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:51:11.31#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:51:11.31$vc4f8/vb=3,4 2006.140.07:51:11.31#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.07:51:11.31#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.07:51:11.31#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:11.31#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:11.37#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:11.37#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:11.39#ibcon#[27=AT03-04\r\n] 2006.140.07:51:11.42#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:11.42#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.07:51:11.42#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.07:51:11.42#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:11.42#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:11.54#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:11.54#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:11.56#ibcon#[27=USB\r\n] 2006.140.07:51:11.59#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:11.59#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.07:51:11.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:51:11.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:51:11.59$vc4f8/vblo=4,712.99 2006.140.07:51:11.59#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.07:51:11.59#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.07:51:11.59#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:11.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:11.59#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:11.59#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:51:11.65#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:11.65#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.07:51:11.65#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:51:11.65#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:51:11.65$vc4f8/vb=4,4 2006.140.07:51:11.65#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.07:51:11.65#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.07:51:11.65#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:11.65#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:11.71#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:11.71#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:11.73#ibcon#[27=AT04-04\r\n] 2006.140.07:51:11.76#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:11.76#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.07:51:11.76#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.07:51:11.76#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:11.76#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:11.88#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:11.88#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:11.90#ibcon#[27=USB\r\n] 2006.140.07:51:11.93#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:11.93#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.07:51:11.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:51:11.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:51:11.93$vc4f8/vblo=5,744.99 2006.140.07:51:11.93#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.07:51:11.93#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.07:51:11.93#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:11.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:11.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:11.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:51:11.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:11.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.07:51:11.99#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:51:11.99#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:51:11.99$vc4f8/vb=5,4 2006.140.07:51:11.99#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.07:51:11.99#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.07:51:11.99#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:11.99#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:12.05#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:12.05#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:12.07#ibcon#[27=AT05-04\r\n] 2006.140.07:51:12.10#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:12.10#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.07:51:12.10#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.07:51:12.10#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:12.10#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:12.22#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:12.22#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:12.24#ibcon#[27=USB\r\n] 2006.140.07:51:12.27#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:12.27#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.07:51:12.27#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:51:12.27#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:51:12.27$vc4f8/vblo=6,752.99 2006.140.07:51:12.27#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:51:12.27#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:51:12.27#ibcon#ireg 17 cls_cnt 0 2006.140.07:51:12.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:12.27#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:12.27#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:51:12.33#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:12.33#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:51:12.33#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:51:12.33#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:51:12.33$vc4f8/vb=6,4 2006.140.07:51:12.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.07:51:12.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.07:51:12.33#ibcon#ireg 11 cls_cnt 2 2006.140.07:51:12.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:12.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:12.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:12.41#ibcon#[27=AT06-04\r\n] 2006.140.07:51:12.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:12.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.07:51:12.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.07:51:12.44#ibcon#ireg 7 cls_cnt 0 2006.140.07:51:12.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:12.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:12.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:12.58#ibcon#[27=USB\r\n] 2006.140.07:51:12.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:12.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.07:51:12.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:51:12.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:51:12.61$vc4f8/vabw=wide 2006.140.07:51:12.61#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.07:51:12.61#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.07:51:12.61#ibcon#ireg 8 cls_cnt 0 2006.140.07:51:12.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:12.61#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:12.61#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:12.63#ibcon#[25=BW32\r\n] 2006.140.07:51:12.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:12.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.07:51:12.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:51:12.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:51:12.66$vc4f8/vbbw=wide 2006.140.07:51:12.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:51:12.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:51:12.66#ibcon#ireg 8 cls_cnt 0 2006.140.07:51:12.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:51:12.73#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:51:12.73#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:51:12.75#ibcon#[27=BW32\r\n] 2006.140.07:51:12.78#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:51:12.78#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:51:12.78#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:51:12.78#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:51:12.78$4f8m12a/ifd4f 2006.140.07:51:12.78$ifd4f/lo= 2006.140.07:51:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:51:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:51:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:51:12.78$ifd4f/patch= 2006.140.07:51:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:51:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:51:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:51:12.78$4f8m12a/"form=m,16.000,1:2 2006.140.07:51:12.78$4f8m12a/"tpicd 2006.140.07:51:12.78$4f8m12a/echo=off 2006.140.07:51:12.78$4f8m12a/xlog=off 2006.140.07:51:12.78:!2006.140.07:51:40 2006.140.07:51:24.14#trakl#Source acquired 2006.140.07:51:25.14#flagr#flagr/antenna,acquired 2006.140.07:51:40.00:preob 2006.140.07:51:41.14/onsource/TRACKING 2006.140.07:51:41.14:!2006.140.07:51:50 2006.140.07:51:50.00:data_valid=on 2006.140.07:51:50.00:midob 2006.140.07:51:50.14/onsource/TRACKING 2006.140.07:51:50.14/wx/24.07,993.7,88 2006.140.07:51:50.28/cable/+6.4983E-03 2006.140.07:51:51.37/va/01,08,usb,yes,76,80 2006.140.07:51:51.37/va/02,07,usb,yes,77,80 2006.140.07:51:51.37/va/03,06,usb,yes,81,82 2006.140.07:51:51.37/va/04,07,usb,yes,78,84 2006.140.07:51:51.37/va/05,07,usb,yes,80,85 2006.140.07:51:51.37/va/06,06,usb,yes,80,79 2006.140.07:51:51.37/va/07,06,usb,yes,80,80 2006.140.07:51:51.37/va/08,06,usb,yes,85,83 2006.140.07:51:51.60/valo/01,532.99,yes,locked 2006.140.07:51:51.60/valo/02,572.99,yes,locked 2006.140.07:51:51.60/valo/03,672.99,yes,locked 2006.140.07:51:51.60/valo/04,832.99,yes,locked 2006.140.07:51:51.60/valo/05,652.99,yes,locked 2006.140.07:51:51.60/valo/06,772.99,yes,locked 2006.140.07:51:51.60/valo/07,832.99,yes,locked 2006.140.07:51:51.60/valo/08,852.99,yes,locked 2006.140.07:51:52.69/vb/01,04,usb,yes,37,35 2006.140.07:51:52.69/vb/02,04,usb,yes,39,40 2006.140.07:51:52.69/vb/03,04,usb,yes,34,39 2006.140.07:51:52.69/vb/04,04,usb,yes,37,36 2006.140.07:51:52.69/vb/05,04,usb,yes,34,38 2006.140.07:51:52.69/vb/06,04,usb,yes,35,38 2006.140.07:51:52.69/vb/07,04,usb,yes,38,39 2006.140.07:51:52.69/vb/08,04,usb,yes,35,39 2006.140.07:51:52.92/vblo/01,632.99,yes,locked 2006.140.07:51:52.92/vblo/02,640.99,yes,locked 2006.140.07:51:52.92/vblo/03,656.99,yes,locked 2006.140.07:51:52.92/vblo/04,712.99,yes,locked 2006.140.07:51:52.92/vblo/05,744.99,yes,locked 2006.140.07:51:52.92/vblo/06,752.99,yes,locked 2006.140.07:51:52.92/vblo/07,734.99,yes,locked 2006.140.07:51:52.92/vblo/08,744.99,yes,locked 2006.140.07:51:53.07/vabw/8 2006.140.07:51:53.22/vbbw/8 2006.140.07:51:53.32/xfe/off,on,15.2 2006.140.07:51:53.69/ifatt/23,28,28,28 2006.140.07:51:54.10/fmout-gps/S +1.09E-07 2006.140.07:51:54.17:!2006.140.07:52:50 2006.140.07:52:50.00:data_valid=off 2006.140.07:52:50.00:postob 2006.140.07:52:50.20/cable/+6.4998E-03 2006.140.07:52:50.20/wx/24.02,993.6,89 2006.140.07:52:51.11/fmout-gps/S +1.10E-07 2006.140.07:52:51.11:scan_name=140-0753,k06140,60 2006.140.07:52:51.11:source=1300+580,130252.47,574837.6,2000.0,cw 2006.140.07:52:51.14#flagr#flagr/antenna,new-source 2006.140.07:52:52.14:checkk5 2006.140.07:52:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:52:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:52:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:52:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:52:54.01/chk_obsdata//k5ts1/T1400751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:52:54.38/chk_obsdata//k5ts2/T1400751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:52:54.75/chk_obsdata//k5ts3/T1400751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:52:55.12/chk_obsdata//k5ts4/T1400751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:52:55.82/k5log//k5ts1_log_newline 2006.140.07:52:56.51/k5log//k5ts2_log_newline 2006.140.07:52:57.19/k5log//k5ts3_log_newline 2006.140.07:52:57.88/k5log//k5ts4_log_newline 2006.140.07:52:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:52:57.90:4f8m12a=1 2006.140.07:52:57.90$4f8m12a/echo=on 2006.140.07:52:57.90$4f8m12a/pcalon 2006.140.07:52:57.90$pcalon/"no phase cal control is implemented here 2006.140.07:52:57.90$4f8m12a/"tpicd=stop 2006.140.07:52:57.90$4f8m12a/vc4f8 2006.140.07:52:57.90$vc4f8/valo=1,532.99 2006.140.07:52:57.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.07:52:57.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.07:52:57.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:57.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:52:57.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:52:57.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:52:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:52:58.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:52:58.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:52:58.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:52:58.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:52:58.00$vc4f8/va=1,8 2006.140.07:52:58.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.07:52:58.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.07:52:58.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:58.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:52:58.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:52:58.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:52:58.03#ibcon#[25=AT01-08\r\n] 2006.140.07:52:58.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:52:58.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:52:58.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.07:52:58.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:58.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:52:58.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:52:58.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:52:58.21#ibcon#[25=USB\r\n] 2006.140.07:52:58.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:52:58.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:52:58.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:52:58.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:52:58.24$vc4f8/valo=2,572.99 2006.140.07:52:58.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:52:58.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:52:58.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:58.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:52:58.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:52:58.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:52:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:52:58.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:52:58.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:52:58.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:52:58.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:52:58.30$vc4f8/va=2,7 2006.140.07:52:58.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:52:58.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:52:58.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:58.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:52:58.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:52:58.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:52:58.38#ibcon#[25=AT02-07\r\n] 2006.140.07:52:58.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:52:58.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:52:58.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:52:58.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:58.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:52:58.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:52:58.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:52:58.55#ibcon#[25=USB\r\n] 2006.140.07:52:58.60#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:52:58.60#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:52:58.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:52:58.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:52:58.60$vc4f8/valo=3,672.99 2006.140.07:52:58.60#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:52:58.60#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:52:58.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:58.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:52:58.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:52:58.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:52:58.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:52:58.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:52:58.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:52:58.67#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:52:58.67#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:52:58.67$vc4f8/va=3,6 2006.140.07:52:58.67#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:52:58.67#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:52:58.67#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:58.67#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:52:58.72#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:52:58.72#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:52:58.74#ibcon#[25=AT03-06\r\n] 2006.140.07:52:58.77#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:52:58.77#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:52:58.77#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:52:58.77#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:58.77#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:52:58.89#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:52:58.89#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:52:58.91#ibcon#[25=USB\r\n] 2006.140.07:52:58.94#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:52:58.94#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:52:58.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:52:58.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:52:58.94$vc4f8/valo=4,832.99 2006.140.07:52:58.94#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:52:58.94#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:52:58.94#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:58.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:52:58.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:52:58.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:52:58.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:52:59.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:52:59.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:52:59.00#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:52:59.00#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:52:59.00$vc4f8/va=4,7 2006.140.07:52:59.00#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:52:59.00#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:52:59.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:59.00#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:52:59.06#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:52:59.06#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:52:59.08#ibcon#[25=AT04-07\r\n] 2006.140.07:52:59.11#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:52:59.11#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:52:59.11#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:52:59.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:59.11#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:52:59.23#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:52:59.23#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:52:59.25#ibcon#[25=USB\r\n] 2006.140.07:52:59.28#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:52:59.28#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:52:59.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:52:59.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:52:59.28$vc4f8/valo=5,652.99 2006.140.07:52:59.28#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:52:59.28#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:52:59.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:59.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:52:59.28#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:52:59.28#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:52:59.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:52:59.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:52:59.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:52:59.34#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:52:59.34#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:52:59.34$vc4f8/va=5,7 2006.140.07:52:59.34#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:52:59.34#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:52:59.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:59.34#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:52:59.40#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:52:59.40#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:52:59.42#ibcon#[25=AT05-07\r\n] 2006.140.07:52:59.46#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:52:59.46#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:52:59.46#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:52:59.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:59.46#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:52:59.58#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:52:59.58#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:52:59.60#ibcon#[25=USB\r\n] 2006.140.07:52:59.63#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:52:59.63#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:52:59.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:52:59.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:52:59.63$vc4f8/valo=6,772.99 2006.140.07:52:59.63#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.07:52:59.63#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.07:52:59.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:59.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:52:59.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:52:59.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:52:59.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:52:59.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:52:59.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:52:59.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:52:59.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:52:59.69$vc4f8/va=6,6 2006.140.07:52:59.69#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.07:52:59.69#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.07:52:59.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:52:59.69#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:52:59.75#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:52:59.75#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:52:59.77#ibcon#[25=AT06-06\r\n] 2006.140.07:52:59.80#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:52:59.80#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.07:52:59.80#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.07:52:59.80#ibcon#ireg 7 cls_cnt 0 2006.140.07:52:59.80#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:52:59.92#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:52:59.92#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:52:59.94#ibcon#[25=USB\r\n] 2006.140.07:52:59.97#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:52:59.97#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.07:52:59.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:52:59.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:52:59.97$vc4f8/valo=7,832.99 2006.140.07:52:59.97#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.07:52:59.97#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.07:52:59.97#ibcon#ireg 17 cls_cnt 0 2006.140.07:52:59.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:52:59.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:52:59.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:52:59.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:53:00.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:53:00.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.07:53:00.03#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:53:00.03#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:53:00.03$vc4f8/va=7,6 2006.140.07:53:00.03#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.07:53:00.03#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.07:53:00.03#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:00.03#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:53:00.09#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:53:00.09#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:53:00.11#ibcon#[25=AT07-06\r\n] 2006.140.07:53:00.14#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:53:00.14#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.07:53:00.14#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.07:53:00.14#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:00.14#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:53:00.26#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:53:00.26#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:53:00.28#ibcon#[25=USB\r\n] 2006.140.07:53:00.33#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:53:00.33#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.07:53:00.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:53:00.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:53:00.33$vc4f8/valo=8,852.99 2006.140.07:53:00.33#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.07:53:00.33#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.07:53:00.33#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:00.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:53:00.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:53:00.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:53:00.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:53:00.39#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:53:00.39#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.07:53:00.39#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:53:00.39#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:53:00.39$vc4f8/va=8,6 2006.140.07:53:00.39#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.07:53:00.39#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.07:53:00.39#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:00.39#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:53:00.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:53:00.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:53:00.47#ibcon#[25=AT08-06\r\n] 2006.140.07:53:00.50#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:53:00.50#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.07:53:00.50#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.07:53:00.50#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:00.50#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:53:00.62#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:53:00.62#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:53:00.64#ibcon#[25=USB\r\n] 2006.140.07:53:00.67#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:53:00.67#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.07:53:00.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:53:00.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:53:00.67$vc4f8/vblo=1,632.99 2006.140.07:53:00.67#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.07:53:00.67#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.07:53:00.67#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:00.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:53:00.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:53:00.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:53:00.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:53:00.73#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:53:00.73#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:53:00.73#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:53:00.73#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:53:00.73$vc4f8/vb=1,4 2006.140.07:53:00.73#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.07:53:00.73#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.07:53:00.73#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:00.73#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:53:00.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:53:00.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:53:00.75#ibcon#[27=AT01-04\r\n] 2006.140.07:53:00.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:53:00.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.07:53:00.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.07:53:00.78#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:00.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:53:00.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:53:00.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:53:00.92#ibcon#[27=USB\r\n] 2006.140.07:53:00.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:53:00.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.07:53:00.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:53:00.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:53:00.95$vc4f8/vblo=2,640.99 2006.140.07:53:00.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.07:53:00.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.07:53:00.95#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:00.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:53:00.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:53:00.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:53:00.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:53:01.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:53:01.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.07:53:01.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:53:01.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:53:01.02$vc4f8/vb=2,4 2006.140.07:53:01.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.07:53:01.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.07:53:01.02#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:01.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:53:01.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:53:01.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:53:01.09#ibcon#[27=AT02-04\r\n] 2006.140.07:53:01.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:53:01.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.07:53:01.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.07:53:01.12#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:01.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:53:01.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:53:01.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:53:01.26#ibcon#[27=USB\r\n] 2006.140.07:53:01.31#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:53:01.31#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.07:53:01.31#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:53:01.31#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:53:01.31$vc4f8/vblo=3,656.99 2006.140.07:53:01.31#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.07:53:01.31#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.07:53:01.31#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:01.31#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:53:01.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:53:01.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:53:01.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:53:01.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:53:01.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.07:53:01.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:53:01.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:53:01.38$vc4f8/vb=3,4 2006.140.07:53:01.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.07:53:01.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.07:53:01.38#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:01.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:53:01.43#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:53:01.43#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:53:01.45#ibcon#[27=AT03-04\r\n] 2006.140.07:53:01.48#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:53:01.48#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.07:53:01.48#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.07:53:01.48#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:01.48#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:53:01.60#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:53:01.60#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:53:01.62#ibcon#[27=USB\r\n] 2006.140.07:53:01.65#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:53:01.65#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.07:53:01.65#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:53:01.65#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:53:01.65$vc4f8/vblo=4,712.99 2006.140.07:53:01.65#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.07:53:01.65#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.07:53:01.65#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:01.65#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:53:01.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:53:01.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:53:01.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:53:01.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:53:01.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.07:53:01.71#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:53:01.71#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:53:01.71$vc4f8/vb=4,4 2006.140.07:53:01.71#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.07:53:01.71#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.07:53:01.71#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:01.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:53:01.77#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:53:01.77#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:53:01.79#ibcon#[27=AT04-04\r\n] 2006.140.07:53:01.82#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:53:01.82#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.07:53:01.82#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.07:53:01.82#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:01.82#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:53:01.94#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:53:01.94#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:53:01.96#ibcon#[27=USB\r\n] 2006.140.07:53:01.99#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:53:01.99#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.07:53:01.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:53:01.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:53:01.99$vc4f8/vblo=5,744.99 2006.140.07:53:01.99#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.07:53:01.99#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.07:53:01.99#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:01.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:53:01.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:53:01.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:53:02.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:53:02.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:53:02.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.07:53:02.05#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:53:02.05#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:53:02.05$vc4f8/vb=5,4 2006.140.07:53:02.05#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.07:53:02.05#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.07:53:02.05#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:02.05#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:53:02.11#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:53:02.11#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:53:02.13#ibcon#[27=AT05-04\r\n] 2006.140.07:53:02.16#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:53:02.16#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.07:53:02.16#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.07:53:02.16#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:02.16#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:53:02.28#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:53:02.28#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:53:02.30#ibcon#[27=USB\r\n] 2006.140.07:53:02.35#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:53:02.35#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.07:53:02.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:53:02.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:53:02.35$vc4f8/vblo=6,752.99 2006.140.07:53:02.35#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.07:53:02.35#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.07:53:02.35#ibcon#ireg 17 cls_cnt 0 2006.140.07:53:02.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:53:02.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:53:02.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:53:02.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:53:02.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:53:02.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.07:53:02.41#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:53:02.41#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:53:02.41$vc4f8/vb=6,4 2006.140.07:53:02.41#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.07:53:02.41#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.07:53:02.41#ibcon#ireg 11 cls_cnt 2 2006.140.07:53:02.41#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:53:02.47#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:53:02.47#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:53:02.49#ibcon#[27=AT06-04\r\n] 2006.140.07:53:02.52#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:53:02.52#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.07:53:02.52#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.07:53:02.52#ibcon#ireg 7 cls_cnt 0 2006.140.07:53:02.52#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:53:02.64#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:53:02.64#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:53:02.66#ibcon#[27=USB\r\n] 2006.140.07:53:02.69#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:53:02.69#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.07:53:02.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:53:02.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:53:02.69$vc4f8/vabw=wide 2006.140.07:53:02.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.07:53:02.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.07:53:02.69#ibcon#ireg 8 cls_cnt 0 2006.140.07:53:02.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:53:02.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:53:02.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:53:02.71#ibcon#[25=BW32\r\n] 2006.140.07:53:02.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:53:02.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.07:53:02.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:53:02.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:53:02.74$vc4f8/vbbw=wide 2006.140.07:53:02.74#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:53:02.74#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:53:02.74#ibcon#ireg 8 cls_cnt 0 2006.140.07:53:02.74#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:53:02.81#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:53:02.81#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:53:02.83#ibcon#[27=BW32\r\n] 2006.140.07:53:02.86#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:53:02.86#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:53:02.86#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:53:02.86#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:53:02.86$4f8m12a/ifd4f 2006.140.07:53:02.86$ifd4f/lo= 2006.140.07:53:02.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:53:02.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:53:02.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:53:02.86$ifd4f/patch= 2006.140.07:53:02.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:53:02.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:53:02.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:53:02.86$4f8m12a/"form=m,16.000,1:2 2006.140.07:53:02.86$4f8m12a/"tpicd 2006.140.07:53:02.86$4f8m12a/echo=off 2006.140.07:53:02.86$4f8m12a/xlog=off 2006.140.07:53:02.86:!2006.140.07:53:30 2006.140.07:53:16.14#trakl#Source acquired 2006.140.07:53:18.14#flagr#flagr/antenna,acquired 2006.140.07:53:30.00:preob 2006.140.07:53:31.13/onsource/TRACKING 2006.140.07:53:31.13:!2006.140.07:53:40 2006.140.07:53:40.00:data_valid=on 2006.140.07:53:40.00:midob 2006.140.07:53:40.13/onsource/TRACKING 2006.140.07:53:40.13/wx/23.98,993.6,90 2006.140.07:53:40.19/cable/+6.4985E-03 2006.140.07:53:41.28/va/01,08,usb,yes,47,50 2006.140.07:53:41.28/va/02,07,usb,yes,48,50 2006.140.07:53:41.28/va/03,06,usb,yes,50,51 2006.140.07:53:41.28/va/04,07,usb,yes,49,52 2006.140.07:53:41.28/va/05,07,usb,yes,50,53 2006.140.07:53:41.28/va/06,06,usb,yes,49,49 2006.140.07:53:41.28/va/07,06,usb,yes,50,50 2006.140.07:53:41.28/va/08,06,usb,yes,53,52 2006.140.07:53:41.51/valo/01,532.99,yes,locked 2006.140.07:53:41.51/valo/02,572.99,yes,locked 2006.140.07:53:41.51/valo/03,672.99,yes,locked 2006.140.07:53:41.51/valo/04,832.99,yes,locked 2006.140.07:53:41.51/valo/05,652.99,yes,locked 2006.140.07:53:41.51/valo/06,772.99,yes,locked 2006.140.07:53:41.51/valo/07,832.99,yes,locked 2006.140.07:53:41.51/valo/08,852.99,yes,locked 2006.140.07:53:42.60/vb/01,04,usb,yes,31,29 2006.140.07:53:42.60/vb/02,04,usb,yes,32,34 2006.140.07:53:42.60/vb/03,04,usb,yes,29,32 2006.140.07:53:42.60/vb/04,04,usb,yes,30,30 2006.140.07:53:42.60/vb/05,04,usb,yes,28,32 2006.140.07:53:42.60/vb/06,04,usb,yes,29,32 2006.140.07:53:42.60/vb/07,04,usb,yes,31,31 2006.140.07:53:42.60/vb/08,04,usb,yes,29,32 2006.140.07:53:42.84/vblo/01,632.99,yes,locked 2006.140.07:53:42.84/vblo/02,640.99,yes,locked 2006.140.07:53:42.84/vblo/03,656.99,yes,locked 2006.140.07:53:42.84/vblo/04,712.99,yes,locked 2006.140.07:53:42.84/vblo/05,744.99,yes,locked 2006.140.07:53:42.84/vblo/06,752.99,yes,locked 2006.140.07:53:42.84/vblo/07,734.99,yes,locked 2006.140.07:53:42.84/vblo/08,744.99,yes,locked 2006.140.07:53:42.99/vabw/8 2006.140.07:53:43.14/vbbw/8 2006.140.07:53:43.23/xfe/off,on,15.5 2006.140.07:53:43.61/ifatt/23,28,28,28 2006.140.07:53:44.11/fmout-gps/S +1.11E-07 2006.140.07:53:44.18:!2006.140.07:54:40 2006.140.07:54:40.00:data_valid=off 2006.140.07:54:40.00:postob 2006.140.07:54:40.10/cable/+6.5006E-03 2006.140.07:54:40.10/wx/23.91,993.5,91 2006.140.07:54:41.11/fmout-gps/S +1.11E-07 2006.140.07:54:41.11:scan_name=140-0756,k06140,60 2006.140.07:54:41.11:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.140.07:54:41.13#flagr#flagr/antenna,new-source 2006.140.07:54:42.13:checkk5 2006.140.07:54:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:54:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:54:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:54:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:54:44.02/chk_obsdata//k5ts1/T1400753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:54:44.39/chk_obsdata//k5ts2/T1400753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:54:44.76/chk_obsdata//k5ts3/T1400753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:54:45.13/chk_obsdata//k5ts4/T1400753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.07:54:45.82/k5log//k5ts1_log_newline 2006.140.07:54:46.51/k5log//k5ts2_log_newline 2006.140.07:54:47.19/k5log//k5ts3_log_newline 2006.140.07:54:47.88/k5log//k5ts4_log_newline 2006.140.07:54:47.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:54:47.90:4f8m12a=2 2006.140.07:54:47.90$4f8m12a/echo=on 2006.140.07:54:47.90$4f8m12a/pcalon 2006.140.07:54:47.90$pcalon/"no phase cal control is implemented here 2006.140.07:54:47.90$4f8m12a/"tpicd=stop 2006.140.07:54:47.90$4f8m12a/vc4f8 2006.140.07:54:47.90$vc4f8/valo=1,532.99 2006.140.07:54:47.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:54:47.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:54:47.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:47.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:47.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:47.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:47.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:54:48.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:48.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:48.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:54:48.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:54:48.00$vc4f8/va=1,8 2006.140.07:54:48.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:54:48.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:54:48.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:48.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:48.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:48.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:48.03#ibcon#[25=AT01-08\r\n] 2006.140.07:54:48.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:48.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:48.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:54:48.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:48.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:48.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:48.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:48.21#ibcon#[25=USB\r\n] 2006.140.07:54:48.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:48.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:48.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:54:48.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:54:48.24$vc4f8/valo=2,572.99 2006.140.07:54:48.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.07:54:48.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.07:54:48.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:48.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:48.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:48.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:54:48.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:48.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:48.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:54:48.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:54:48.30$vc4f8/va=2,7 2006.140.07:54:48.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.07:54:48.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.07:54:48.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:48.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:48.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:48.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:48.38#ibcon#[25=AT02-07\r\n] 2006.140.07:54:48.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:48.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:48.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.07:54:48.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:48.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:48.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:48.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:48.55#ibcon#[25=USB\r\n] 2006.140.07:54:48.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:48.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:48.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:54:48.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:54:48.58$vc4f8/valo=3,672.99 2006.140.07:54:48.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.07:54:48.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.07:54:48.58#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:48.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:48.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:48.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:48.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:54:48.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:48.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:48.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:54:48.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:54:48.66$vc4f8/va=3,6 2006.140.07:54:48.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.07:54:48.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.07:54:48.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:48.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:48.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:48.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:48.72#ibcon#[25=AT03-06\r\n] 2006.140.07:54:48.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:48.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:48.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.07:54:48.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:48.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:48.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:48.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:48.89#ibcon#[25=USB\r\n] 2006.140.07:54:48.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:48.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:48.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:54:48.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:54:48.92$vc4f8/valo=4,832.99 2006.140.07:54:48.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.07:54:48.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.07:54:48.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:48.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:48.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:48.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:48.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:54:48.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:48.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:48.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:54:48.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:54:48.98$vc4f8/va=4,7 2006.140.07:54:48.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.07:54:48.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.07:54:48.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:48.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:49.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:49.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:49.06#ibcon#[25=AT04-07\r\n] 2006.140.07:54:49.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:49.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:49.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.07:54:49.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:49.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:49.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:49.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:49.23#ibcon#[25=USB\r\n] 2006.140.07:54:49.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:49.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:49.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:54:49.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:54:49.26$vc4f8/valo=5,652.99 2006.140.07:54:49.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.07:54:49.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.07:54:49.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:49.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:49.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:49.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:49.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:54:49.32#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:49.32#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:49.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:54:49.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:54:49.32$vc4f8/va=5,7 2006.140.07:54:49.32#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.07:54:49.32#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.07:54:49.32#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:49.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:49.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:49.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:49.40#ibcon#[25=AT05-07\r\n] 2006.140.07:54:49.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:49.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:49.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.07:54:49.43#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:49.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:49.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:49.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:49.57#ibcon#[25=USB\r\n] 2006.140.07:54:49.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:49.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:49.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:54:49.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:54:49.60$vc4f8/valo=6,772.99 2006.140.07:54:49.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:54:49.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:54:49.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:49.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:49.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:49.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:49.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:54:49.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:49.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:49.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:54:49.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:54:49.66$vc4f8/va=6,6 2006.140.07:54:49.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.07:54:49.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.07:54:49.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:49.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:49.72#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:49.72#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:49.74#ibcon#[25=AT06-06\r\n] 2006.140.07:54:49.77#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:49.77#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:49.77#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.07:54:49.77#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:49.77#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:54:49.89#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:54:49.89#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:54:49.91#ibcon#[25=USB\r\n] 2006.140.07:54:49.94#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:54:49.94#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.07:54:49.94#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:54:49.94#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:54:49.94$vc4f8/valo=7,832.99 2006.140.07:54:49.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.07:54:49.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.07:54:49.94#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:49.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:54:49.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:54:49.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:54:49.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:54:50.00#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:54:50.00#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.07:54:50.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.07:54:50.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.07:54:50.00$vc4f8/va=7,6 2006.140.07:54:50.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.07:54:50.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.07:54:50.00#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:50.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:54:50.06#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:54:50.06#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:54:50.08#ibcon#[25=AT07-06\r\n] 2006.140.07:54:50.11#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:54:50.11#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.07:54:50.11#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.07:54:50.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:50.11#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:54:50.23#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:54:50.23#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:54:50.25#ibcon#[25=USB\r\n] 2006.140.07:54:50.28#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:54:50.28#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.07:54:50.28#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.07:54:50.28#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.07:54:50.28$vc4f8/valo=8,852.99 2006.140.07:54:50.28#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.07:54:50.28#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.07:54:50.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:50.28#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:54:50.28#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:54:50.28#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:54:50.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:54:50.34#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:54:50.34#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.07:54:50.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.07:54:50.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.07:54:50.34$vc4f8/va=8,6 2006.140.07:54:50.34#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.07:54:50.34#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.07:54:50.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:50.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:54:50.40#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:54:50.40#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:54:50.42#ibcon#[25=AT08-06\r\n] 2006.140.07:54:50.46#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:54:50.46#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.07:54:50.46#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.07:54:50.46#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:50.46#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:54:50.58#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:54:50.58#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:54:50.60#ibcon#[25=USB\r\n] 2006.140.07:54:50.63#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:54:50.63#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.07:54:50.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.07:54:50.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.07:54:50.63$vc4f8/vblo=1,632.99 2006.140.07:54:50.63#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.07:54:50.63#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.07:54:50.63#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:50.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:54:50.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:54:50.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:54:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:54:50.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:54:50.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.07:54:50.69#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.07:54:50.69#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.07:54:50.69$vc4f8/vb=1,4 2006.140.07:54:50.69#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.07:54:50.69#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.07:54:50.69#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:50.69#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:54:50.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:54:50.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:54:50.71#ibcon#[27=AT01-04\r\n] 2006.140.07:54:50.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:54:50.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.07:54:50.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.07:54:50.74#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:50.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:54:50.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:54:50.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:54:50.88#ibcon#[27=USB\r\n] 2006.140.07:54:50.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:54:50.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.07:54:50.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.07:54:50.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.07:54:50.91$vc4f8/vblo=2,640.99 2006.140.07:54:50.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.07:54:50.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.07:54:50.91#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:50.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:50.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:50.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:54:50.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:50.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.07:54:50.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.07:54:50.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.07:54:50.97$vc4f8/vb=2,4 2006.140.07:54:50.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.07:54:50.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.07:54:50.97#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:50.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:51.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:51.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:51.05#ibcon#[27=AT02-04\r\n] 2006.140.07:54:51.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:51.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.07:54:51.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.07:54:51.08#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:51.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:51.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:51.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:51.22#ibcon#[27=USB\r\n] 2006.140.07:54:51.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:51.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.07:54:51.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.07:54:51.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.07:54:51.25$vc4f8/vblo=3,656.99 2006.140.07:54:51.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.07:54:51.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.07:54:51.25#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:51.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:51.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:51.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:54:51.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:51.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.07:54:51.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.07:54:51.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.07:54:51.31$vc4f8/vb=3,4 2006.140.07:54:51.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.07:54:51.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.07:54:51.31#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:51.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:51.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:51.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:51.39#ibcon#[27=AT03-04\r\n] 2006.140.07:54:51.42#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:51.42#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.07:54:51.42#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.07:54:51.42#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:51.42#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:51.54#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:51.54#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:51.56#ibcon#[27=USB\r\n] 2006.140.07:54:51.59#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:51.59#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.07:54:51.59#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.07:54:51.59#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.07:54:51.59$vc4f8/vblo=4,712.99 2006.140.07:54:51.59#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.07:54:51.59#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.07:54:51.59#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:51.59#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:51.59#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:51.59#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:54:51.65#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:51.65#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.07:54:51.65#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.07:54:51.65#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.07:54:51.65$vc4f8/vb=4,4 2006.140.07:54:51.65#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.07:54:51.65#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.07:54:51.65#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:51.65#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:51.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:51.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:51.73#ibcon#[27=AT04-04\r\n] 2006.140.07:54:51.76#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:51.76#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.07:54:51.76#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.07:54:51.76#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:51.76#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:51.88#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:51.88#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:51.90#ibcon#[27=USB\r\n] 2006.140.07:54:51.93#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:51.93#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.07:54:51.93#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.07:54:51.93#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.07:54:51.93$vc4f8/vblo=5,744.99 2006.140.07:54:51.93#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.07:54:51.93#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.07:54:51.93#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:51.93#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:51.93#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:51.93#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:51.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:54:51.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:51.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.07:54:51.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.07:54:51.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.07:54:51.99$vc4f8/vb=5,4 2006.140.07:54:51.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.07:54:51.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.07:54:51.99#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:51.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:52.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:52.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:52.07#ibcon#[27=AT05-04\r\n] 2006.140.07:54:52.11#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:52.11#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.07:54:52.11#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.07:54:52.11#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:52.11#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:52.23#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:52.23#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:52.25#ibcon#[27=USB\r\n] 2006.140.07:54:52.28#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:52.28#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.07:54:52.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.07:54:52.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.07:54:52.28$vc4f8/vblo=6,752.99 2006.140.07:54:52.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.07:54:52.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.07:54:52.28#ibcon#ireg 17 cls_cnt 0 2006.140.07:54:52.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:52.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:52.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:54:52.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:52.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.07:54:52.34#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.07:54:52.34#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.07:54:52.34$vc4f8/vb=6,4 2006.140.07:54:52.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.07:54:52.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.07:54:52.34#ibcon#ireg 11 cls_cnt 2 2006.140.07:54:52.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:52.40#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:52.40#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:52.42#ibcon#[27=AT06-04\r\n] 2006.140.07:54:52.45#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:52.45#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.07:54:52.45#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.07:54:52.45#ibcon#ireg 7 cls_cnt 0 2006.140.07:54:52.45#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:52.57#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:52.57#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:52.59#ibcon#[27=USB\r\n] 2006.140.07:54:52.62#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:52.62#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.07:54:52.62#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.07:54:52.62#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.07:54:52.62$vc4f8/vabw=wide 2006.140.07:54:52.62#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.07:54:52.62#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.07:54:52.62#ibcon#ireg 8 cls_cnt 0 2006.140.07:54:52.62#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:52.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:52.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:52.64#ibcon#[25=BW32\r\n] 2006.140.07:54:52.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:52.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.07:54:52.67#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.07:54:52.67#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.07:54:52.67$vc4f8/vbbw=wide 2006.140.07:54:52.67#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.07:54:52.67#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.07:54:52.67#ibcon#ireg 8 cls_cnt 0 2006.140.07:54:52.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:54:52.74#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:54:52.74#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:54:52.76#ibcon#[27=BW32\r\n] 2006.140.07:54:52.79#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:54:52.79#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.07:54:52.79#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.07:54:52.79#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.07:54:52.79$4f8m12a/ifd4f 2006.140.07:54:52.79$ifd4f/lo= 2006.140.07:54:52.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:54:52.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:54:52.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:54:52.79$ifd4f/patch= 2006.140.07:54:52.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:54:52.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:54:52.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:54:52.79$4f8m12a/"form=m,16.000,1:2 2006.140.07:54:52.79$4f8m12a/"tpicd 2006.140.07:54:52.79$4f8m12a/echo=off 2006.140.07:54:52.79$4f8m12a/xlog=off 2006.140.07:54:52.79:!2006.140.07:56:00 2006.140.07:55:35.13#trakl#Source acquired 2006.140.07:55:35.13#flagr#flagr/antenna,acquired 2006.140.07:56:00.00:preob 2006.140.07:56:00.14/onsource/TRACKING 2006.140.07:56:00.14:!2006.140.07:56:10 2006.140.07:56:10.00:data_valid=on 2006.140.07:56:10.00:midob 2006.140.07:56:11.14/onsource/TRACKING 2006.140.07:56:11.14/wx/23.78,993.5,92 2006.140.07:56:11.32/cable/+6.5007E-03 2006.140.07:56:12.41/va/01,08,usb,yes,54,57 2006.140.07:56:12.41/va/02,07,usb,yes,55,57 2006.140.07:56:12.41/va/03,06,usb,yes,58,59 2006.140.07:56:12.41/va/04,07,usb,yes,57,61 2006.140.07:56:12.41/va/05,07,usb,yes,57,60 2006.140.07:56:12.41/va/06,06,usb,yes,56,56 2006.140.07:56:12.41/va/07,06,usb,yes,57,57 2006.140.07:56:12.41/va/08,06,usb,yes,60,59 2006.140.07:56:12.64/valo/01,532.99,yes,locked 2006.140.07:56:12.64/valo/02,572.99,yes,locked 2006.140.07:56:12.64/valo/03,672.99,yes,locked 2006.140.07:56:12.64/valo/04,832.99,yes,locked 2006.140.07:56:12.64/valo/05,652.99,yes,locked 2006.140.07:56:12.64/valo/06,772.99,yes,locked 2006.140.07:56:12.64/valo/07,832.99,yes,locked 2006.140.07:56:12.64/valo/08,852.99,yes,locked 2006.140.07:56:13.73/vb/01,04,usb,yes,32,30 2006.140.07:56:13.73/vb/02,04,usb,yes,33,35 2006.140.07:56:13.73/vb/03,04,usb,yes,30,34 2006.140.07:56:13.73/vb/04,04,usb,yes,31,31 2006.140.07:56:13.73/vb/05,04,usb,yes,29,33 2006.140.07:56:13.73/vb/06,04,usb,yes,30,33 2006.140.07:56:13.73/vb/07,04,usb,yes,32,32 2006.140.07:56:13.73/vb/08,04,usb,yes,30,33 2006.140.07:56:13.96/vblo/01,632.99,yes,locked 2006.140.07:56:13.96/vblo/02,640.99,yes,locked 2006.140.07:56:13.96/vblo/03,656.99,yes,locked 2006.140.07:56:13.96/vblo/04,712.99,yes,locked 2006.140.07:56:13.96/vblo/05,744.99,yes,locked 2006.140.07:56:13.96/vblo/06,752.99,yes,locked 2006.140.07:56:13.96/vblo/07,734.99,yes,locked 2006.140.07:56:13.96/vblo/08,744.99,yes,locked 2006.140.07:56:14.11/vabw/8 2006.140.07:56:14.26/vbbw/8 2006.140.07:56:14.37/xfe/off,on,14.7 2006.140.07:56:14.76/ifatt/23,28,28,28 2006.140.07:56:15.11/fmout-gps/S +1.11E-07 2006.140.07:56:15.15:!2006.140.07:57:10 2006.140.07:57:10.00:data_valid=off 2006.140.07:57:10.00:postob 2006.140.07:57:10.08/cable/+6.5023E-03 2006.140.07:57:10.08/wx/23.67,993.6,93 2006.140.07:57:11.11/fmout-gps/S +1.11E-07 2006.140.07:57:11.11:scan_name=140-0759,k06140,60 2006.140.07:57:11.11:source=1418+546,141946.60,542314.8,2000.0,cw 2006.140.07:57:11.14#flagr#flagr/antenna,new-source 2006.140.07:57:12.14:checkk5 2006.140.07:57:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.07:57:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.07:57:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.07:57:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.07:57:14.01/chk_obsdata//k5ts1/T1400756??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:57:14.38/chk_obsdata//k5ts2/T1400756??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:57:14.74/chk_obsdata//k5ts3/T1400756??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:57:15.11/chk_obsdata//k5ts4/T1400756??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.07:57:15.80/k5log//k5ts1_log_newline 2006.140.07:57:16.49/k5log//k5ts2_log_newline 2006.140.07:57:17.18/k5log//k5ts3_log_newline 2006.140.07:57:17.86/k5log//k5ts4_log_newline 2006.140.07:57:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.07:57:17.88:4f8m12a=2 2006.140.07:57:17.88$4f8m12a/echo=on 2006.140.07:57:17.88$4f8m12a/pcalon 2006.140.07:57:17.88$pcalon/"no phase cal control is implemented here 2006.140.07:57:17.88$4f8m12a/"tpicd=stop 2006.140.07:57:17.88$4f8m12a/vc4f8 2006.140.07:57:17.88$vc4f8/valo=1,532.99 2006.140.07:57:17.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:57:17.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:57:17.89#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:17.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:17.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:17.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.07:57:17.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:17.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:17.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:57:17.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:57:17.98$vc4f8/va=1,8 2006.140.07:57:17.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:57:17.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:57:17.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:17.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:17.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:17.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:18.01#ibcon#[25=AT01-08\r\n] 2006.140.07:57:18.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:18.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:18.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:57:18.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:18.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:18.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:18.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:18.19#ibcon#[25=USB\r\n] 2006.140.07:57:18.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:18.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:18.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:57:18.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:57:18.22$vc4f8/valo=2,572.99 2006.140.07:57:18.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:57:18.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:57:18.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:18.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:18.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:18.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.07:57:18.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:18.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:18.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:57:18.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:57:18.28$vc4f8/va=2,7 2006.140.07:57:18.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:57:18.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:57:18.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:18.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:18.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:18.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:18.36#ibcon#[25=AT02-07\r\n] 2006.140.07:57:18.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:18.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:18.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:57:18.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:18.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:18.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:18.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:18.53#ibcon#[25=USB\r\n] 2006.140.07:57:18.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:18.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:18.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:57:18.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:57:18.56$vc4f8/valo=3,672.99 2006.140.07:57:18.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:57:18.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:57:18.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:18.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:18.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:18.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.07:57:18.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:18.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:18.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:57:18.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:57:18.64$vc4f8/va=3,6 2006.140.07:57:18.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:57:18.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:57:18.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:18.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:18.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:18.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:18.70#ibcon#[25=AT03-06\r\n] 2006.140.07:57:18.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:18.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:18.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:57:18.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:18.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:18.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:18.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:18.87#ibcon#[25=USB\r\n] 2006.140.07:57:18.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:18.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:18.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:57:18.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:57:18.90$vc4f8/valo=4,832.99 2006.140.07:57:18.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:57:18.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:57:18.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:18.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:18.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:18.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.07:57:18.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:18.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:18.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:57:18.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:57:18.96$vc4f8/va=4,7 2006.140.07:57:18.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:57:18.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:57:18.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:18.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:19.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:19.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:19.04#ibcon#[25=AT04-07\r\n] 2006.140.07:57:19.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:19.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:19.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:57:19.07#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:19.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:19.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:19.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:19.21#ibcon#[25=USB\r\n] 2006.140.07:57:19.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:19.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:19.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:57:19.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:57:19.24$vc4f8/valo=5,652.99 2006.140.07:57:19.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:57:19.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:57:19.24#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:19.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:19.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:19.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.07:57:19.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:19.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:19.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:57:19.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:57:19.30$vc4f8/va=5,7 2006.140.07:57:19.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:57:19.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:57:19.30#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:19.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:19.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:19.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:19.38#ibcon#[25=AT05-07\r\n] 2006.140.07:57:19.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:19.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:19.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:57:19.41#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:19.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:19.47#abcon#<5=/15 1.4 6.1 23.65 93 993.6\r\n> 2006.140.07:57:19.49#abcon#{5=INTERFACE CLEAR} 2006.140.07:57:19.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:19.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:19.55#ibcon#[25=USB\r\n] 2006.140.07:57:19.55#abcon#[5=S1D000X0/0*\r\n] 2006.140.07:57:19.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:19.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:19.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:57:19.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:57:19.58$vc4f8/valo=6,772.99 2006.140.07:57:19.58#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:57:19.58#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:57:19.58#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:19.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:19.58#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:19.58#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.07:57:19.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:19.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:19.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:57:19.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:57:19.64$vc4f8/va=6,6 2006.140.07:57:19.64#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.07:57:19.64#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.07:57:19.64#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:19.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:19.70#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:19.70#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:19.72#ibcon#[25=AT06-06\r\n] 2006.140.07:57:19.75#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:19.75#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:19.75#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.07:57:19.75#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:19.75#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:57:19.87#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:57:19.87#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:57:19.89#ibcon#[25=USB\r\n] 2006.140.07:57:19.92#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:57:19.92#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.07:57:19.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:57:19.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:57:19.92$vc4f8/valo=7,832.99 2006.140.07:57:19.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.07:57:19.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.07:57:19.92#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:19.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:57:19.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:57:19.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:57:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.07:57:19.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:57:19.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.07:57:19.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.07:57:19.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.07:57:19.98$vc4f8/va=7,6 2006.140.07:57:19.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.07:57:19.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.07:57:19.98#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:19.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:57:20.04#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:57:20.04#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:57:20.06#ibcon#[25=AT07-06\r\n] 2006.140.07:57:20.09#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:57:20.09#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.07:57:20.09#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.07:57:20.09#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:20.09#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:57:20.21#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:57:20.21#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:57:20.23#ibcon#[25=USB\r\n] 2006.140.07:57:20.26#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:57:20.26#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.07:57:20.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.07:57:20.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.07:57:20.26$vc4f8/valo=8,852.99 2006.140.07:57:20.26#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.07:57:20.26#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.07:57:20.26#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:20.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:57:20.26#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:57:20.26#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:57:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.07:57:20.32#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:57:20.32#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.07:57:20.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.07:57:20.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.07:57:20.32$vc4f8/va=8,6 2006.140.07:57:20.32#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.07:57:20.32#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.07:57:20.32#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:20.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:57:20.38#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:57:20.38#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:57:20.40#ibcon#[25=AT08-06\r\n] 2006.140.07:57:20.43#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:57:20.43#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.07:57:20.43#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.07:57:20.43#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:20.43#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:57:20.55#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:57:20.55#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:57:20.57#ibcon#[25=USB\r\n] 2006.140.07:57:20.60#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:57:20.60#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.07:57:20.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.07:57:20.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.07:57:20.60$vc4f8/vblo=1,632.99 2006.140.07:57:20.60#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.07:57:20.60#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.07:57:20.60#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:20.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:20.60#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:20.60#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.07:57:20.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:20.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.07:57:20.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.07:57:20.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.07:57:20.66$vc4f8/vb=1,4 2006.140.07:57:20.66#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.07:57:20.66#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.07:57:20.66#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:20.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:20.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:20.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:20.68#ibcon#[27=AT01-04\r\n] 2006.140.07:57:20.71#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:20.71#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.07:57:20.71#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.07:57:20.71#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:20.71#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:20.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:20.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:20.85#ibcon#[27=USB\r\n] 2006.140.07:57:20.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:20.88#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.07:57:20.88#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.07:57:20.88#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.07:57:20.88$vc4f8/vblo=2,640.99 2006.140.07:57:20.88#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.07:57:20.88#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.07:57:20.88#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:20.88#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:20.88#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:20.88#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.07:57:20.94#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:20.94#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.07:57:20.94#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.07:57:20.94#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.07:57:20.94$vc4f8/vb=2,4 2006.140.07:57:20.94#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.07:57:20.94#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.07:57:20.94#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:20.94#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:21.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:21.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:21.02#ibcon#[27=AT02-04\r\n] 2006.140.07:57:21.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:21.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.07:57:21.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.07:57:21.05#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:21.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:21.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:21.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:21.19#ibcon#[27=USB\r\n] 2006.140.07:57:21.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:21.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.07:57:21.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.07:57:21.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.07:57:21.22$vc4f8/vblo=3,656.99 2006.140.07:57:21.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.07:57:21.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.07:57:21.22#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:21.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:21.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:21.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.07:57:21.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:21.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.07:57:21.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.07:57:21.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.07:57:21.28$vc4f8/vb=3,4 2006.140.07:57:21.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.07:57:21.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.07:57:21.28#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:21.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:21.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:21.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:21.36#ibcon#[27=AT03-04\r\n] 2006.140.07:57:21.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:21.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.07:57:21.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.07:57:21.39#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:21.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:21.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:21.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:21.53#ibcon#[27=USB\r\n] 2006.140.07:57:21.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:21.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.07:57:21.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.07:57:21.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.07:57:21.56$vc4f8/vblo=4,712.99 2006.140.07:57:21.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.07:57:21.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.07:57:21.56#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:21.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:21.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:21.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.07:57:21.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:21.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.07:57:21.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.07:57:21.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.07:57:21.62$vc4f8/vb=4,4 2006.140.07:57:21.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.07:57:21.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.07:57:21.62#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:21.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:21.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:21.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:21.70#ibcon#[27=AT04-04\r\n] 2006.140.07:57:21.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:21.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.07:57:21.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.07:57:21.73#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:21.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:21.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:21.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:21.87#ibcon#[27=USB\r\n] 2006.140.07:57:21.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:21.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.07:57:21.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.07:57:21.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.07:57:21.90$vc4f8/vblo=5,744.99 2006.140.07:57:21.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.07:57:21.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.07:57:21.90#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:21.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:21.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:21.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.07:57:21.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:21.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.07:57:21.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.07:57:21.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.07:57:21.96$vc4f8/vb=5,4 2006.140.07:57:21.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.07:57:21.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.07:57:21.96#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:21.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:22.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:22.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:22.04#ibcon#[27=AT05-04\r\n] 2006.140.07:57:22.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:22.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.07:57:22.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.07:57:22.08#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:22.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:22.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:22.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:22.22#ibcon#[27=USB\r\n] 2006.140.07:57:22.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:22.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.07:57:22.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.07:57:22.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.07:57:22.25$vc4f8/vblo=6,752.99 2006.140.07:57:22.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.07:57:22.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.07:57:22.25#ibcon#ireg 17 cls_cnt 0 2006.140.07:57:22.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:57:22.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:57:22.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:57:22.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.07:57:22.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:57:22.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.07:57:22.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.07:57:22.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.07:57:22.31$vc4f8/vb=6,4 2006.140.07:57:22.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.07:57:22.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.07:57:22.31#ibcon#ireg 11 cls_cnt 2 2006.140.07:57:22.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:57:22.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:57:22.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:57:22.39#ibcon#[27=AT06-04\r\n] 2006.140.07:57:22.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:57:22.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.07:57:22.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.07:57:22.42#ibcon#ireg 7 cls_cnt 0 2006.140.07:57:22.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:57:22.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:57:22.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:57:22.56#ibcon#[27=USB\r\n] 2006.140.07:57:22.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:57:22.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.07:57:22.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.07:57:22.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.07:57:22.59$vc4f8/vabw=wide 2006.140.07:57:22.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.07:57:22.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.07:57:22.59#ibcon#ireg 8 cls_cnt 0 2006.140.07:57:22.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:22.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:22.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:22.61#ibcon#[25=BW32\r\n] 2006.140.07:57:22.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:22.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.07:57:22.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.07:57:22.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.07:57:22.64$vc4f8/vbbw=wide 2006.140.07:57:22.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.07:57:22.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.07:57:22.64#ibcon#ireg 8 cls_cnt 0 2006.140.07:57:22.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:57:22.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:57:22.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:57:22.73#ibcon#[27=BW32\r\n] 2006.140.07:57:22.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:57:22.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.07:57:22.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.07:57:22.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.07:57:22.76$4f8m12a/ifd4f 2006.140.07:57:22.76$ifd4f/lo= 2006.140.07:57:22.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.07:57:22.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.07:57:22.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.07:57:22.76$ifd4f/patch= 2006.140.07:57:22.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.07:57:22.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.07:57:22.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.07:57:22.76$4f8m12a/"form=m,16.000,1:2 2006.140.07:57:22.76$4f8m12a/"tpicd 2006.140.07:57:22.76$4f8m12a/echo=off 2006.140.07:57:22.76$4f8m12a/xlog=off 2006.140.07:57:22.76:!2006.140.07:59:30 2006.140.07:58:06.14#trakl#Source acquired 2006.140.07:58:08.14#flagr#flagr/antenna,acquired 2006.140.07:59:30.00:preob 2006.140.07:59:30.14/onsource/TRACKING 2006.140.07:59:30.14:!2006.140.07:59:40 2006.140.07:59:40.00:data_valid=on 2006.140.07:59:40.00:midob 2006.140.07:59:41.14/onsource/TRACKING 2006.140.07:59:41.14/wx/23.37,993.7,95 2006.140.07:59:41.30/cable/+6.5006E-03 2006.140.07:59:42.39/va/01,08,usb,yes,59,62 2006.140.07:59:42.39/va/02,07,usb,yes,60,62 2006.140.07:59:42.39/va/03,06,usb,yes,63,64 2006.140.07:59:42.39/va/04,07,usb,yes,62,66 2006.140.07:59:42.39/va/05,07,usb,yes,63,67 2006.140.07:59:42.39/va/06,06,usb,yes,63,62 2006.140.07:59:42.39/va/07,06,usb,yes,63,63 2006.140.07:59:42.39/va/08,06,usb,yes,67,66 2006.140.07:59:42.62/valo/01,532.99,yes,locked 2006.140.07:59:42.62/valo/02,572.99,yes,locked 2006.140.07:59:42.62/valo/03,672.99,yes,locked 2006.140.07:59:42.62/valo/04,832.99,yes,locked 2006.140.07:59:42.62/valo/05,652.99,yes,locked 2006.140.07:59:42.62/valo/06,772.99,yes,locked 2006.140.07:59:42.62/valo/07,832.99,yes,locked 2006.140.07:59:42.62/valo/08,852.99,yes,locked 2006.140.07:59:43.71/vb/01,04,usb,yes,32,31 2006.140.07:59:43.71/vb/02,04,usb,yes,34,36 2006.140.07:59:43.71/vb/03,04,usb,yes,30,34 2006.140.07:59:43.71/vb/04,04,usb,yes,31,32 2006.140.07:59:43.71/vb/05,04,usb,yes,30,34 2006.140.07:59:43.71/vb/06,04,usb,yes,31,34 2006.140.07:59:43.71/vb/07,04,usb,yes,33,33 2006.140.07:59:43.71/vb/08,04,usb,yes,30,34 2006.140.07:59:43.95/vblo/01,632.99,yes,locked 2006.140.07:59:43.95/vblo/02,640.99,yes,locked 2006.140.07:59:43.95/vblo/03,656.99,yes,locked 2006.140.07:59:43.95/vblo/04,712.99,yes,locked 2006.140.07:59:43.95/vblo/05,744.99,yes,locked 2006.140.07:59:43.95/vblo/06,752.99,yes,locked 2006.140.07:59:43.95/vblo/07,734.99,yes,locked 2006.140.07:59:43.95/vblo/08,744.99,yes,locked 2006.140.07:59:44.10/vabw/8 2006.140.07:59:44.25/vbbw/8 2006.140.07:59:44.34/xfe/off,on,15.2 2006.140.07:59:44.71/ifatt/23,28,28,28 2006.140.07:59:45.10/fmout-gps/S +1.13E-07 2006.140.07:59:45.17:!2006.140.08:00:40 2006.140.08:00:40.00:data_valid=off 2006.140.08:00:40.00:postob 2006.140.08:00:40.12/cable/+6.4989E-03 2006.140.08:00:40.12/wx/23.25,993.8,95 2006.140.08:00:41.10/fmout-gps/S +1.14E-07 2006.140.08:00:41.10:scan_name=140-0801,k06140,60 2006.140.08:00:41.10:source=0955+476,095819.67,472507.8,2000.0,cw 2006.140.08:00:41.14#flagr#flagr/antenna,new-source 2006.140.08:00:42.14:checkk5 2006.140.08:00:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:00:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:00:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:00:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:00:44.02/chk_obsdata//k5ts1/T1400759??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:00:44.39/chk_obsdata//k5ts2/T1400759??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:00:44.76/chk_obsdata//k5ts3/T1400759??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:00:45.12/chk_obsdata//k5ts4/T1400759??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:00:45.81/k5log//k5ts1_log_newline 2006.140.08:00:46.50/k5log//k5ts2_log_newline 2006.140.08:00:47.19/k5log//k5ts3_log_newline 2006.140.08:00:47.87/k5log//k5ts4_log_newline 2006.140.08:00:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:00:47.90:4f8m12a=2 2006.140.08:00:47.90$4f8m12a/echo=on 2006.140.08:00:47.90$4f8m12a/pcalon 2006.140.08:00:47.90$pcalon/"no phase cal control is implemented here 2006.140.08:00:47.90$4f8m12a/"tpicd=stop 2006.140.08:00:47.90$4f8m12a/vc4f8 2006.140.08:00:47.90$vc4f8/valo=1,532.99 2006.140.08:00:47.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:00:47.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:00:47.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:47.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:47.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:47.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:00:47.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:47.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:47.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:00:47.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:00:47.99$vc4f8/va=1,8 2006.140.08:00:47.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:00:47.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:00:47.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:47.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:47.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:47.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:48.01#ibcon#[25=AT01-08\r\n] 2006.140.08:00:48.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:48.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:48.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:00:48.04#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:48.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:48.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:48.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:48.18#ibcon#[25=USB\r\n] 2006.140.08:00:48.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:48.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:48.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:00:48.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:00:48.23$vc4f8/valo=2,572.99 2006.140.08:00:48.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:00:48.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:00:48.23#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:48.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:48.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:48.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:48.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:00:48.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:48.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:48.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:00:48.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:00:48.29$vc4f8/va=2,7 2006.140.08:00:48.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:00:48.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:00:48.29#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:48.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:48.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:48.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:48.37#ibcon#[25=AT02-07\r\n] 2006.140.08:00:48.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:48.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:48.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:00:48.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:48.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:48.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:48.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:48.54#ibcon#[25=USB\r\n] 2006.140.08:00:48.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:48.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:48.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:00:48.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:00:48.59$vc4f8/valo=3,672.99 2006.140.08:00:48.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:00:48.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:00:48.59#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:48.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:48.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:48.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:48.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:00:48.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:48.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:48.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:00:48.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:00:48.66$vc4f8/va=3,6 2006.140.08:00:48.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:00:48.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:00:48.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:48.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:48.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:48.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:48.73#ibcon#[25=AT03-06\r\n] 2006.140.08:00:48.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:48.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:48.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:00:48.76#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:48.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:48.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:48.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:48.90#ibcon#[25=USB\r\n] 2006.140.08:00:48.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:48.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:48.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:00:48.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:00:48.93$vc4f8/valo=4,832.99 2006.140.08:00:48.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:00:48.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:00:48.93#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:48.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:48.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:48.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:48.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:00:48.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:48.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:48.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:00:48.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:00:48.99$vc4f8/va=4,7 2006.140.08:00:48.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:00:48.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:00:48.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:48.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:49.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:49.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:49.07#ibcon#[25=AT04-07\r\n] 2006.140.08:00:49.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:49.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:49.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:00:49.10#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:49.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:49.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:49.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:49.24#ibcon#[25=USB\r\n] 2006.140.08:00:49.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:49.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:49.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:00:49.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:00:49.27$vc4f8/valo=5,652.99 2006.140.08:00:49.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:00:49.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:00:49.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:49.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:49.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:49.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:49.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:00:49.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:49.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:49.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:00:49.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:00:49.33$vc4f8/va=5,7 2006.140.08:00:49.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:00:49.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:00:49.33#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:49.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:49.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:49.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:49.41#ibcon#[25=AT05-07\r\n] 2006.140.08:00:49.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:49.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:49.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:00:49.44#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:49.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:49.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:49.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:49.58#ibcon#[25=USB\r\n] 2006.140.08:00:49.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:49.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:49.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:00:49.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:00:49.61$vc4f8/valo=6,772.99 2006.140.08:00:49.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:00:49.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:00:49.61#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:49.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:49.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:49.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:00:49.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:49.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:49.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:00:49.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:00:49.67$vc4f8/va=6,6 2006.140.08:00:49.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.08:00:49.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.08:00:49.67#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:49.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:49.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:49.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:49.75#ibcon#[25=AT06-06\r\n] 2006.140.08:00:49.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:49.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:49.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.08:00:49.78#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:49.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:00:49.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:00:49.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:00:49.92#ibcon#[25=USB\r\n] 2006.140.08:00:49.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:00:49.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:00:49.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:00:49.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:00:49.95$vc4f8/valo=7,832.99 2006.140.08:00:49.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.08:00:49.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.08:00:49.95#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:49.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:00:49.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:00:49.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:00:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:00:50.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:00:50.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:00:50.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:00:50.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:00:50.01$vc4f8/va=7,6 2006.140.08:00:50.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.08:00:50.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.08:00:50.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:50.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:00:50.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:00:50.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:00:50.09#ibcon#[25=AT07-06\r\n] 2006.140.08:00:50.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:00:50.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:00:50.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.08:00:50.12#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:50.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:00:50.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:00:50.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:00:50.26#ibcon#[25=USB\r\n] 2006.140.08:00:50.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:00:50.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:00:50.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:00:50.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:00:50.29$vc4f8/valo=8,852.99 2006.140.08:00:50.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:00:50.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:00:50.29#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:50.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:00:50.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:00:50.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:00:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:00:50.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:00:50.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:00:50.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:00:50.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:00:50.35$vc4f8/va=8,6 2006.140.08:00:50.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:00:50.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:00:50.35#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:50.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:00:50.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:00:50.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:00:50.43#ibcon#[25=AT08-06\r\n] 2006.140.08:00:50.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:00:50.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:00:50.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:00:50.46#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:50.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:00:50.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:00:50.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:00:50.60#ibcon#[25=USB\r\n] 2006.140.08:00:50.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:00:50.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:00:50.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:00:50.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:00:50.63$vc4f8/vblo=1,632.99 2006.140.08:00:50.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:00:50.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:00:50.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:50.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:00:50.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:00:50.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:00:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:00:50.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:00:50.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:00:50.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:00:50.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:00:50.69$vc4f8/vb=1,4 2006.140.08:00:50.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:00:50.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:00:50.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:50.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:00:50.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:00:50.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:00:50.71#ibcon#[27=AT01-04\r\n] 2006.140.08:00:50.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:00:50.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:00:50.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:00:50.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:50.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:00:50.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:00:50.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:00:50.88#ibcon#[27=USB\r\n] 2006.140.08:00:50.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:00:50.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:00:50.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:00:50.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:00:50.91$vc4f8/vblo=2,640.99 2006.140.08:00:50.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:00:50.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:00:50.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:50.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:50.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:50.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:00:50.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:50.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:00:50.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:00:50.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:00:50.97$vc4f8/vb=2,4 2006.140.08:00:50.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:00:50.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:00:50.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:50.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:51.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:51.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:51.05#ibcon#[27=AT02-04\r\n] 2006.140.08:00:51.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:51.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:00:51.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:00:51.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:51.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:51.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:51.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:51.22#ibcon#[27=USB\r\n] 2006.140.08:00:51.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:51.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:00:51.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:00:51.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:00:51.25$vc4f8/vblo=3,656.99 2006.140.08:00:51.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:00:51.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:00:51.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:51.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:51.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:51.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:00:51.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:51.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:00:51.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:00:51.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:00:51.31$vc4f8/vb=3,4 2006.140.08:00:51.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:00:51.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:00:51.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:51.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:51.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:51.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:51.39#ibcon#[27=AT03-04\r\n] 2006.140.08:00:51.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:51.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:00:51.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:00:51.42#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:51.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:51.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:51.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:51.56#ibcon#[27=USB\r\n] 2006.140.08:00:51.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:51.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:00:51.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:00:51.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:00:51.59$vc4f8/vblo=4,712.99 2006.140.08:00:51.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:00:51.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:00:51.59#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:51.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:51.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:51.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:00:51.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:51.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:00:51.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:00:51.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:00:51.65$vc4f8/vb=4,4 2006.140.08:00:51.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:00:51.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:00:51.65#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:51.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:51.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:51.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:51.73#ibcon#[27=AT04-04\r\n] 2006.140.08:00:51.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:51.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:00:51.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:00:51.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:51.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:51.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:51.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:51.91#ibcon#[27=USB\r\n] 2006.140.08:00:51.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:51.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:00:51.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:00:51.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:00:51.94$vc4f8/vblo=5,744.99 2006.140.08:00:51.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:00:51.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:00:51.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:51.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:51.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:51.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:51.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:00:52.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:52.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:00:52.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:00:52.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:00:52.00$vc4f8/vb=5,4 2006.140.08:00:52.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:00:52.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:00:52.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:52.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:52.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:52.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:52.08#ibcon#[27=AT05-04\r\n] 2006.140.08:00:52.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:52.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:00:52.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:00:52.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:52.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:52.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:52.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:52.25#ibcon#[27=USB\r\n] 2006.140.08:00:52.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:52.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:00:52.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:00:52.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:00:52.28$vc4f8/vblo=6,752.99 2006.140.08:00:52.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:00:52.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:00:52.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:00:52.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:52.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:52.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:52.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:00:52.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:52.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:00:52.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:00:52.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:00:52.34$vc4f8/vb=6,4 2006.140.08:00:52.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:00:52.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:00:52.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:00:52.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:52.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:52.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:52.42#ibcon#[27=AT06-04\r\n] 2006.140.08:00:52.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:52.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:00:52.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:00:52.46#ibcon#ireg 7 cls_cnt 0 2006.140.08:00:52.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:52.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:52.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:52.60#ibcon#[27=USB\r\n] 2006.140.08:00:52.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:52.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:00:52.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:00:52.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:00:52.63$vc4f8/vabw=wide 2006.140.08:00:52.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:00:52.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:00:52.63#ibcon#ireg 8 cls_cnt 0 2006.140.08:00:52.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:52.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:52.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:52.65#ibcon#[25=BW32\r\n] 2006.140.08:00:52.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:52.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:00:52.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:00:52.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:00:52.68$vc4f8/vbbw=wide 2006.140.08:00:52.68#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:00:52.68#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:00:52.68#ibcon#ireg 8 cls_cnt 0 2006.140.08:00:52.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:00:52.75#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:00:52.75#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:00:52.77#ibcon#[27=BW32\r\n] 2006.140.08:00:52.80#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:00:52.80#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:00:52.80#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:00:52.80#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:00:52.80$4f8m12a/ifd4f 2006.140.08:00:52.80$ifd4f/lo= 2006.140.08:00:52.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:00:52.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:00:52.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:00:52.80$ifd4f/patch= 2006.140.08:00:52.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:00:52.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:00:52.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:00:52.80$4f8m12a/"form=m,16.000,1:2 2006.140.08:00:52.80$4f8m12a/"tpicd 2006.140.08:00:52.80$4f8m12a/echo=off 2006.140.08:00:52.80$4f8m12a/xlog=off 2006.140.08:00:52.80:!2006.140.08:01:20 2006.140.08:01:08.14#trakl#Source acquired 2006.140.08:01:08.14#flagr#flagr/antenna,acquired 2006.140.08:01:20.00:preob 2006.140.08:01:21.14/onsource/TRACKING 2006.140.08:01:21.14:!2006.140.08:01:30 2006.140.08:01:30.00:data_valid=on 2006.140.08:01:30.00:midob 2006.140.08:01:30.14/onsource/TRACKING 2006.140.08:01:30.14/wx/23.16,993.8,96 2006.140.08:01:30.19/cable/+6.4991E-03 2006.140.08:01:31.28/va/01,08,usb,yes,64,67 2006.140.08:01:31.28/va/02,07,usb,yes,65,67 2006.140.08:01:31.28/va/03,06,usb,yes,68,69 2006.140.08:01:31.28/va/04,07,usb,yes,66,71 2006.140.08:01:31.28/va/05,07,usb,yes,68,72 2006.140.08:01:31.28/va/06,06,usb,yes,67,67 2006.140.08:01:31.28/va/07,06,usb,yes,68,67 2006.140.08:01:31.28/va/08,06,usb,yes,72,71 2006.140.08:01:31.51/valo/01,532.99,yes,locked 2006.140.08:01:31.51/valo/02,572.99,yes,locked 2006.140.08:01:31.51/valo/03,672.99,yes,locked 2006.140.08:01:31.51/valo/04,832.99,yes,locked 2006.140.08:01:31.51/valo/05,652.99,yes,locked 2006.140.08:01:31.51/valo/06,772.99,yes,locked 2006.140.08:01:31.51/valo/07,832.99,yes,locked 2006.140.08:01:31.51/valo/08,852.99,yes,locked 2006.140.08:01:32.60/vb/01,04,usb,yes,33,32 2006.140.08:01:32.60/vb/02,04,usb,yes,35,37 2006.140.08:01:32.60/vb/03,04,usb,yes,31,35 2006.140.08:01:32.60/vb/04,04,usb,yes,33,33 2006.140.08:01:32.60/vb/05,04,usb,yes,31,35 2006.140.08:01:32.60/vb/06,04,usb,yes,32,35 2006.140.08:01:32.60/vb/07,04,usb,yes,34,34 2006.140.08:01:32.60/vb/08,04,usb,yes,32,35 2006.140.08:01:32.83/vblo/01,632.99,yes,locked 2006.140.08:01:32.83/vblo/02,640.99,yes,locked 2006.140.08:01:32.83/vblo/03,656.99,yes,locked 2006.140.08:01:32.83/vblo/04,712.99,yes,locked 2006.140.08:01:32.83/vblo/05,744.99,yes,locked 2006.140.08:01:32.83/vblo/06,752.99,yes,locked 2006.140.08:01:32.83/vblo/07,734.99,yes,locked 2006.140.08:01:32.83/vblo/08,744.99,yes,locked 2006.140.08:01:32.98/vabw/8 2006.140.08:01:33.13/vbbw/8 2006.140.08:01:33.22/xfe/off,on,16.0 2006.140.08:01:33.61/ifatt/23,28,28,28 2006.140.08:01:34.09/fmout-gps/S +1.15E-07 2006.140.08:01:34.13:!2006.140.08:02:30 2006.140.08:02:30.00:data_valid=off 2006.140.08:02:30.00:postob 2006.140.08:02:30.08/cable/+6.5015E-03 2006.140.08:02:30.09/wx/23.06,993.7,97 2006.140.08:02:31.10/fmout-gps/S +1.15E-07 2006.140.08:02:31.10:scan_name=140-0803,k06140,60 2006.140.08:02:31.10:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.140.08:02:31.13#flagr#flagr/antenna,new-source 2006.140.08:02:32.13:checkk5 2006.140.08:02:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:02:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:02:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:02:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:02:34.01/chk_obsdata//k5ts1/T1400801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:02:34.38/chk_obsdata//k5ts2/T1400801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:02:34.75/chk_obsdata//k5ts3/T1400801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:02:35.13/chk_obsdata//k5ts4/T1400801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:02:35.81/k5log//k5ts1_log_newline 2006.140.08:02:36.50/k5log//k5ts2_log_newline 2006.140.08:02:37.19/k5log//k5ts3_log_newline 2006.140.08:02:37.88/k5log//k5ts4_log_newline 2006.140.08:02:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:02:37.91:4f8m12a=2 2006.140.08:02:37.91$4f8m12a/echo=on 2006.140.08:02:37.91$4f8m12a/pcalon 2006.140.08:02:37.91$pcalon/"no phase cal control is implemented here 2006.140.08:02:37.91$4f8m12a/"tpicd=stop 2006.140.08:02:37.91$4f8m12a/vc4f8 2006.140.08:02:37.91$vc4f8/valo=1,532.99 2006.140.08:02:37.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:02:37.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:02:37.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:37.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:37.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:37.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:37.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:02:37.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:37.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:37.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:02:37.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:02:37.98$vc4f8/va=1,8 2006.140.08:02:37.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.08:02:37.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.08:02:37.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:37.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:37.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:37.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:38.00#ibcon#[25=AT01-08\r\n] 2006.140.08:02:38.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:38.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:38.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.08:02:38.04#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:38.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:38.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:38.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:38.18#ibcon#[25=USB\r\n] 2006.140.08:02:38.23#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:38.23#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:38.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:02:38.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:02:38.23$vc4f8/valo=2,572.99 2006.140.08:02:38.23#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:02:38.23#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:02:38.23#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:38.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:38.23#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:38.23#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:38.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:02:38.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:38.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:38.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:02:38.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:02:38.29$vc4f8/va=2,7 2006.140.08:02:38.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.08:02:38.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.08:02:38.29#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:38.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:38.35#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:38.35#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:38.37#ibcon#[25=AT02-07\r\n] 2006.140.08:02:38.40#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:38.40#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:38.40#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.08:02:38.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:38.40#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:38.52#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:38.52#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:38.54#ibcon#[25=USB\r\n] 2006.140.08:02:38.57#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:38.57#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:38.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:02:38.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:02:38.57$vc4f8/valo=3,672.99 2006.140.08:02:38.57#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.08:02:38.57#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.08:02:38.57#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:38.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:38.57#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:38.57#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:38.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:02:38.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:38.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:38.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:02:38.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:02:38.65$vc4f8/va=3,6 2006.140.08:02:38.65#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.08:02:38.65#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.08:02:38.65#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:38.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:38.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:38.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:38.71#ibcon#[25=AT03-06\r\n] 2006.140.08:02:38.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:38.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:38.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.08:02:38.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:38.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:38.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:38.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:38.88#ibcon#[25=USB\r\n] 2006.140.08:02:38.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:38.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:38.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:02:38.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:02:38.91$vc4f8/valo=4,832.99 2006.140.08:02:38.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:02:38.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:02:38.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:38.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:38.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:38.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:38.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:02:38.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:38.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:38.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:02:38.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:02:38.97$vc4f8/va=4,7 2006.140.08:02:38.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.08:02:38.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.08:02:38.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:38.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:39.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:39.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:39.05#ibcon#[25=AT04-07\r\n] 2006.140.08:02:39.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:39.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:39.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.08:02:39.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:39.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:39.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:39.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:39.22#ibcon#[25=USB\r\n] 2006.140.08:02:39.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:39.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:39.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:02:39.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:02:39.25$vc4f8/valo=5,652.99 2006.140.08:02:39.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:02:39.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:02:39.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:39.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:39.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:39.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:39.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:02:39.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:39.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:39.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:02:39.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:02:39.31$vc4f8/va=5,7 2006.140.08:02:39.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.08:02:39.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.08:02:39.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:39.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:39.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:39.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:39.39#ibcon#[25=AT05-07\r\n] 2006.140.08:02:39.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:39.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:39.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.08:02:39.42#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:39.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:39.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:39.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:39.56#ibcon#[25=USB\r\n] 2006.140.08:02:39.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:39.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:39.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:02:39.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:02:39.59$vc4f8/valo=6,772.99 2006.140.08:02:39.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:02:39.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:02:39.59#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:39.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:39.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:39.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:02:39.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:39.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:39.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:02:39.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:02:39.65$vc4f8/va=6,6 2006.140.08:02:39.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.08:02:39.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.08:02:39.65#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:39.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:39.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:39.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:39.73#ibcon#[25=AT06-06\r\n] 2006.140.08:02:39.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:39.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:39.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.08:02:39.76#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:39.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:02:39.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:02:39.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:02:39.90#ibcon#[25=USB\r\n] 2006.140.08:02:39.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:02:39.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:02:39.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:02:39.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:02:39.93$vc4f8/valo=7,832.99 2006.140.08:02:39.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.08:02:39.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.08:02:39.93#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:39.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:02:39.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:02:39.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:02:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:02:39.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:02:39.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:02:39.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:02:39.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:02:39.99$vc4f8/va=7,6 2006.140.08:02:39.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.08:02:39.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.08:02:39.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:39.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:02:40.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:02:40.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:02:40.07#ibcon#[25=AT07-06\r\n] 2006.140.08:02:40.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:02:40.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:02:40.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.08:02:40.10#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:40.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:02:40.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:02:40.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:02:40.24#ibcon#[25=USB\r\n] 2006.140.08:02:40.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:02:40.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:02:40.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:02:40.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:02:40.27$vc4f8/valo=8,852.99 2006.140.08:02:40.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.08:02:40.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.08:02:40.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:40.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:02:40.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:02:40.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:02:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:02:40.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:02:40.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:02:40.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:02:40.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:02:40.33$vc4f8/va=8,6 2006.140.08:02:40.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.08:02:40.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.08:02:40.33#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:40.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:02:40.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:02:40.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:02:40.41#ibcon#[25=AT08-06\r\n] 2006.140.08:02:40.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:02:40.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:02:40.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.08:02:40.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:40.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:02:40.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:02:40.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:02:40.59#ibcon#[25=USB\r\n] 2006.140.08:02:40.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:02:40.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:02:40.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:02:40.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:02:40.62$vc4f8/vblo=1,632.99 2006.140.08:02:40.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.08:02:40.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.08:02:40.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:40.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:02:40.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:02:40.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:02:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:02:40.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:02:40.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:02:40.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:02:40.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:02:40.68$vc4f8/vb=1,4 2006.140.08:02:40.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.08:02:40.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.08:02:40.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:40.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:02:40.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:02:40.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:02:40.70#ibcon#[27=AT01-04\r\n] 2006.140.08:02:40.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:02:40.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:02:40.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.08:02:40.73#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:40.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:02:40.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:02:40.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:02:40.87#ibcon#[27=USB\r\n] 2006.140.08:02:40.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:02:40.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:02:40.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:02:40.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:02:40.90$vc4f8/vblo=2,640.99 2006.140.08:02:40.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:02:40.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:02:40.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:40.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:40.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:40.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:02:40.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:40.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:02:40.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:02:40.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:02:40.96$vc4f8/vb=2,4 2006.140.08:02:40.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.08:02:40.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.08:02:40.96#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:40.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:41.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:41.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:41.04#ibcon#[27=AT02-04\r\n] 2006.140.08:02:41.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:41.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:02:41.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.08:02:41.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:41.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:41.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:41.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:41.21#ibcon#[27=USB\r\n] 2006.140.08:02:41.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:41.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:02:41.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:02:41.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:02:41.24$vc4f8/vblo=3,656.99 2006.140.08:02:41.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:02:41.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:02:41.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:41.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:41.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:41.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:41.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:02:41.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:41.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:02:41.32#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:02:41.32#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:02:41.32$vc4f8/vb=3,4 2006.140.08:02:41.32#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.08:02:41.32#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.08:02:41.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:41.32#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:41.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:41.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:41.38#ibcon#[27=AT03-04\r\n] 2006.140.08:02:41.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:41.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:02:41.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.08:02:41.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:41.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:41.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:41.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:41.55#ibcon#[27=USB\r\n] 2006.140.08:02:41.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:41.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:02:41.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:02:41.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:02:41.58$vc4f8/vblo=4,712.99 2006.140.08:02:41.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.08:02:41.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.08:02:41.58#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:41.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:41.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:41.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:02:41.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:41.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:02:41.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:02:41.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:02:41.64$vc4f8/vb=4,4 2006.140.08:02:41.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.08:02:41.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.08:02:41.64#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:41.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:41.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:41.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:41.72#ibcon#[27=AT04-04\r\n] 2006.140.08:02:41.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:41.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:02:41.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.08:02:41.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:41.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:41.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:41.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:41.89#ibcon#[27=USB\r\n] 2006.140.08:02:41.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:41.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:02:41.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:02:41.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:02:41.92$vc4f8/vblo=5,744.99 2006.140.08:02:41.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:02:41.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:02:41.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:41.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:41.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:41.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:41.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:02:42.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:42.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:02:42.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:02:42.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:02:42.00$vc4f8/vb=5,4 2006.140.08:02:42.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.08:02:42.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.08:02:42.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:42.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:42.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:42.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:42.06#ibcon#[27=AT05-04\r\n] 2006.140.08:02:42.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:42.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:02:42.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.08:02:42.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:42.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:42.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:42.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:42.23#ibcon#[27=USB\r\n] 2006.140.08:02:42.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:42.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:02:42.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:02:42.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:02:42.26$vc4f8/vblo=6,752.99 2006.140.08:02:42.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:02:42.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:02:42.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:02:42.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:42.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:42.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:02:42.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:42.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:02:42.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:02:42.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:02:42.32$vc4f8/vb=6,4 2006.140.08:02:42.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.08:02:42.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.08:02:42.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:02:42.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:42.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:42.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:42.40#ibcon#[27=AT06-04\r\n] 2006.140.08:02:42.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:42.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:02:42.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.08:02:42.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:02:42.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:42.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:42.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:42.57#ibcon#[27=USB\r\n] 2006.140.08:02:42.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:42.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:02:42.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:02:42.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:02:42.60$vc4f8/vabw=wide 2006.140.08:02:42.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:02:42.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:02:42.60#ibcon#ireg 8 cls_cnt 0 2006.140.08:02:42.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:42.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:42.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:42.62#ibcon#[25=BW32\r\n] 2006.140.08:02:42.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:42.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:02:42.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:02:42.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:02:42.65$vc4f8/vbbw=wide 2006.140.08:02:42.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.08:02:42.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.08:02:42.65#ibcon#ireg 8 cls_cnt 0 2006.140.08:02:42.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:02:42.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:02:42.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:02:42.74#ibcon#[27=BW32\r\n] 2006.140.08:02:42.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:02:42.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:02:42.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:02:42.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:02:42.77$4f8m12a/ifd4f 2006.140.08:02:42.77$ifd4f/lo= 2006.140.08:02:42.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:02:42.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:02:42.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:02:42.77$ifd4f/patch= 2006.140.08:02:42.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:02:42.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:02:42.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:02:42.77$4f8m12a/"form=m,16.000,1:2 2006.140.08:02:42.77$4f8m12a/"tpicd 2006.140.08:02:42.77$4f8m12a/echo=off 2006.140.08:02:42.77$4f8m12a/xlog=off 2006.140.08:02:42.77:!2006.140.08:03:20 2006.140.08:03:01.13#trakl#Source acquired 2006.140.08:03:01.13#flagr#flagr/antenna,acquired 2006.140.08:03:20.00:preob 2006.140.08:03:20.13/onsource/TRACKING 2006.140.08:03:20.13:!2006.140.08:03:30 2006.140.08:03:30.00:data_valid=on 2006.140.08:03:30.00:midob 2006.140.08:03:31.13/onsource/TRACKING 2006.140.08:03:31.13/wx/22.96,993.6,97 2006.140.08:03:31.35/cable/+6.4989E-03 2006.140.08:03:32.44/va/01,08,usb,yes,69,72 2006.140.08:03:32.44/va/02,07,usb,yes,70,72 2006.140.08:03:32.44/va/03,06,usb,yes,74,74 2006.140.08:03:32.44/va/04,07,usb,yes,71,77 2006.140.08:03:32.44/va/05,07,usb,yes,73,77 2006.140.08:03:32.44/va/06,06,usb,yes,73,72 2006.140.08:03:32.44/va/07,06,usb,yes,73,73 2006.140.08:03:32.44/va/08,06,usb,yes,77,76 2006.140.08:03:32.67/valo/01,532.99,yes,locked 2006.140.08:03:32.67/valo/02,572.99,yes,locked 2006.140.08:03:32.67/valo/03,672.99,yes,locked 2006.140.08:03:32.67/valo/04,832.99,yes,locked 2006.140.08:03:32.67/valo/05,652.99,yes,locked 2006.140.08:03:32.67/valo/06,772.99,yes,locked 2006.140.08:03:32.67/valo/07,832.99,yes,locked 2006.140.08:03:32.67/valo/08,852.99,yes,locked 2006.140.08:03:33.76/vb/01,04,usb,yes,34,32 2006.140.08:03:33.76/vb/02,04,usb,yes,36,38 2006.140.08:03:33.76/vb/03,04,usb,yes,32,36 2006.140.08:03:33.76/vb/04,04,usb,yes,34,34 2006.140.08:03:33.76/vb/05,04,usb,yes,32,36 2006.140.08:03:33.76/vb/06,04,usb,yes,33,36 2006.140.08:03:33.76/vb/07,04,usb,yes,35,35 2006.140.08:03:33.76/vb/08,04,usb,yes,32,36 2006.140.08:03:33.99/vblo/01,632.99,yes,locked 2006.140.08:03:33.99/vblo/02,640.99,yes,locked 2006.140.08:03:33.99/vblo/03,656.99,yes,locked 2006.140.08:03:33.99/vblo/04,712.99,yes,locked 2006.140.08:03:33.99/vblo/05,744.99,yes,locked 2006.140.08:03:33.99/vblo/06,752.99,yes,locked 2006.140.08:03:33.99/vblo/07,734.99,yes,locked 2006.140.08:03:33.99/vblo/08,744.99,yes,locked 2006.140.08:03:34.14/vabw/8 2006.140.08:03:34.29/vbbw/8 2006.140.08:03:34.38/xfe/off,on,14.7 2006.140.08:03:34.75/ifatt/23,28,28,28 2006.140.08:03:35.11/fmout-gps/S +1.15E-07 2006.140.08:03:35.15:!2006.140.08:04:30 2006.140.08:04:30.00:data_valid=off 2006.140.08:04:30.00:postob 2006.140.08:04:30.12/cable/+6.5038E-03 2006.140.08:04:30.12/wx/22.87,993.5,97 2006.140.08:04:31.11/fmout-gps/S +1.15E-07 2006.140.08:04:31.11:scan_name=140-0805,k06140,60 2006.140.08:04:31.11:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.140.08:04:31.14#flagr#flagr/antenna,new-source 2006.140.08:04:32.14:checkk5 2006.140.08:04:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:04:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:04:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:04:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:04:34.02/chk_obsdata//k5ts1/T1400803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:04:34.39/chk_obsdata//k5ts2/T1400803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:04:34.76/chk_obsdata//k5ts3/T1400803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:04:35.14/chk_obsdata//k5ts4/T1400803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:04:35.83/k5log//k5ts1_log_newline 2006.140.08:04:36.52/k5log//k5ts2_log_newline 2006.140.08:04:37.21/k5log//k5ts3_log_newline 2006.140.08:04:37.90/k5log//k5ts4_log_newline 2006.140.08:04:37.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:04:37.93:4f8m12a=2 2006.140.08:04:37.93$4f8m12a/echo=on 2006.140.08:04:37.93$4f8m12a/pcalon 2006.140.08:04:37.93$pcalon/"no phase cal control is implemented here 2006.140.08:04:37.93$4f8m12a/"tpicd=stop 2006.140.08:04:37.93$4f8m12a/vc4f8 2006.140.08:04:37.93$vc4f8/valo=1,532.99 2006.140.08:04:37.93#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.08:04:37.93#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.08:04:37.93#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:37.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:37.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:37.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:37.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:04:38.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:38.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:38.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:04:38.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:04:38.02$vc4f8/va=1,8 2006.140.08:04:38.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.08:04:38.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.08:04:38.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:38.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:38.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:38.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:38.05#ibcon#[25=AT01-08\r\n] 2006.140.08:04:38.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:38.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:38.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.08:04:38.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:38.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:38.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:38.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:38.23#ibcon#[25=USB\r\n] 2006.140.08:04:38.27#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:38.27#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:38.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:04:38.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:04:38.27$vc4f8/valo=2,572.99 2006.140.08:04:38.27#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:04:38.27#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:04:38.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:38.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:38.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:38.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:38.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:04:38.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:38.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:38.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:04:38.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:04:38.35$vc4f8/va=2,7 2006.140.08:04:38.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.08:04:38.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.08:04:38.35#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:38.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:38.39#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:38.39#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:38.41#ibcon#[25=AT02-07\r\n] 2006.140.08:04:38.44#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:38.44#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:38.44#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.08:04:38.44#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:38.44#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:38.56#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:38.56#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:38.58#ibcon#[25=USB\r\n] 2006.140.08:04:38.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:38.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:38.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:04:38.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:04:38.63$vc4f8/valo=3,672.99 2006.140.08:04:38.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:04:38.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:04:38.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:38.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:38.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:38.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:38.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:04:38.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:38.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:38.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:04:38.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:04:38.70$vc4f8/va=3,6 2006.140.08:04:38.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.08:04:38.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.08:04:38.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:38.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:38.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:38.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:38.77#ibcon#[25=AT03-06\r\n] 2006.140.08:04:38.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:38.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:38.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.08:04:38.80#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:38.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:38.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:38.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:38.94#ibcon#[25=USB\r\n] 2006.140.08:04:38.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:38.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:38.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:04:38.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:04:38.97$vc4f8/valo=4,832.99 2006.140.08:04:38.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.08:04:38.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.08:04:38.97#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:38.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:38.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:38.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:38.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:04:39.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:39.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:39.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:04:39.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:04:39.03$vc4f8/va=4,7 2006.140.08:04:39.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.08:04:39.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.08:04:39.03#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:39.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:39.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:39.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:39.11#ibcon#[25=AT04-07\r\n] 2006.140.08:04:39.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:39.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:39.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.08:04:39.14#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:39.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:39.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:39.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:39.28#ibcon#[25=USB\r\n] 2006.140.08:04:39.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:39.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:39.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:04:39.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:04:39.31$vc4f8/valo=5,652.99 2006.140.08:04:39.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:04:39.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:04:39.31#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:39.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:39.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:39.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:39.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:04:39.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:39.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:39.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:04:39.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:04:39.37$vc4f8/va=5,7 2006.140.08:04:39.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.08:04:39.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.08:04:39.37#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:39.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:39.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:39.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:39.45#ibcon#[25=AT05-07\r\n] 2006.140.08:04:39.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:39.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:39.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.08:04:39.48#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:39.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:39.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:39.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:39.62#ibcon#[25=USB\r\n] 2006.140.08:04:39.65#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:39.65#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:39.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:04:39.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:04:39.65$vc4f8/valo=6,772.99 2006.140.08:04:39.65#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:04:39.65#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:04:39.65#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:39.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:39.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:39.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:39.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:04:39.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:39.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:39.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:04:39.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:04:39.71$vc4f8/va=6,6 2006.140.08:04:39.71#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.08:04:39.71#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.08:04:39.71#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:39.71#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:39.77#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:39.77#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:39.79#ibcon#[25=AT06-06\r\n] 2006.140.08:04:39.82#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:39.82#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:39.82#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.08:04:39.82#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:39.82#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:04:39.94#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:04:39.94#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:04:39.96#ibcon#[25=USB\r\n] 2006.140.08:04:39.99#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:04:39.99#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:04:39.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:04:39.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:04:39.99$vc4f8/valo=7,832.99 2006.140.08:04:39.99#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:04:39.99#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:04:39.99#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:39.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:04:39.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:04:39.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:04:40.01#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:04:40.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:04:40.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:04:40.05#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:04:40.05#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:04:40.05$vc4f8/va=7,6 2006.140.08:04:40.05#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.08:04:40.05#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.08:04:40.05#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:40.05#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:04:40.11#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:04:40.11#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:04:40.13#ibcon#[25=AT07-06\r\n] 2006.140.08:04:40.16#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:04:40.16#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:04:40.16#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.08:04:40.16#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:40.16#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:04:40.28#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:04:40.28#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:04:40.30#ibcon#[25=USB\r\n] 2006.140.08:04:40.33#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:04:40.33#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:04:40.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:04:40.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:04:40.33$vc4f8/valo=8,852.99 2006.140.08:04:40.33#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.08:04:40.33#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.08:04:40.33#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:40.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:04:40.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:04:40.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:04:40.35#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:04:40.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:04:40.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:04:40.39#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:04:40.39#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:04:40.39$vc4f8/va=8,6 2006.140.08:04:40.39#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.08:04:40.39#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.08:04:40.39#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:40.39#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:04:40.45#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:04:40.45#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:04:40.47#ibcon#[25=AT08-06\r\n] 2006.140.08:04:40.50#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:04:40.50#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:04:40.50#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.08:04:40.50#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:40.50#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:04:40.62#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:04:40.62#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:04:40.64#ibcon#[25=USB\r\n] 2006.140.08:04:40.67#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:04:40.67#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:04:40.67#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:04:40.67#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:04:40.67$vc4f8/vblo=1,632.99 2006.140.08:04:40.67#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.08:04:40.67#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.08:04:40.67#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:40.67#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:04:40.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:04:40.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:04:40.69#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:04:40.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:04:40.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:04:40.73#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:04:40.73#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:04:40.73$vc4f8/vb=1,4 2006.140.08:04:40.73#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.08:04:40.73#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.08:04:40.73#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:40.73#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:04:40.73#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:04:40.73#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:04:40.75#ibcon#[27=AT01-04\r\n] 2006.140.08:04:40.78#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:04:40.78#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:04:40.78#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.08:04:40.78#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:40.78#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:04:40.90#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:04:40.90#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:04:40.92#ibcon#[27=USB\r\n] 2006.140.08:04:40.95#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:04:40.95#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:04:40.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:04:40.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:04:40.95$vc4f8/vblo=2,640.99 2006.140.08:04:40.95#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.08:04:40.95#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.08:04:40.95#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:40.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:40.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:40.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:40.97#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:04:41.01#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:41.01#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:04:41.01#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:04:41.01#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:04:41.01$vc4f8/vb=2,4 2006.140.08:04:41.01#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.08:04:41.01#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.08:04:41.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:41.01#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:41.07#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:41.07#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:41.09#ibcon#[27=AT02-04\r\n] 2006.140.08:04:41.12#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:41.12#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:04:41.12#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.08:04:41.12#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:41.12#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:41.24#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:41.24#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:41.26#ibcon#[27=USB\r\n] 2006.140.08:04:41.29#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:41.29#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:04:41.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:04:41.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:04:41.29$vc4f8/vblo=3,656.99 2006.140.08:04:41.29#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:04:41.29#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:04:41.29#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:41.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:41.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:41.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:41.31#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:04:41.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:41.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:04:41.35#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:04:41.35#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:04:41.35$vc4f8/vb=3,4 2006.140.08:04:41.35#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.08:04:41.35#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.08:04:41.35#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:41.35#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:41.41#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:41.41#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:41.43#ibcon#[27=AT03-04\r\n] 2006.140.08:04:41.46#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:41.46#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:04:41.46#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.08:04:41.46#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:41.46#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:41.58#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:41.58#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:41.60#ibcon#[27=USB\r\n] 2006.140.08:04:41.63#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:41.63#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:04:41.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:04:41.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:04:41.63$vc4f8/vblo=4,712.99 2006.140.08:04:41.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:04:41.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:04:41.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:41.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:41.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:41.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:41.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:04:41.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:41.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:04:41.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:04:41.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:04:41.69$vc4f8/vb=4,4 2006.140.08:04:41.69#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.08:04:41.69#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.08:04:41.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:41.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:41.75#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:41.75#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:41.77#ibcon#[27=AT04-04\r\n] 2006.140.08:04:41.80#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:41.80#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:04:41.80#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.08:04:41.80#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:41.80#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:41.92#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:41.92#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:41.94#ibcon#[27=USB\r\n] 2006.140.08:04:41.97#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:41.97#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:04:41.97#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:04:41.97#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:04:41.97$vc4f8/vblo=5,744.99 2006.140.08:04:41.97#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.08:04:41.97#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.08:04:41.97#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:41.97#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:41.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:41.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:41.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:04:42.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:42.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:04:42.03#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:04:42.03#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:04:42.03$vc4f8/vb=5,4 2006.140.08:04:42.03#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.08:04:42.03#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.08:04:42.03#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:42.03#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:42.09#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:42.09#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:42.11#ibcon#[27=AT05-04\r\n] 2006.140.08:04:42.14#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:42.14#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:04:42.14#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.08:04:42.14#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:42.14#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:42.26#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:42.26#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:42.28#ibcon#[27=USB\r\n] 2006.140.08:04:42.31#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:42.31#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:04:42.31#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:04:42.31#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:04:42.31$vc4f8/vblo=6,752.99 2006.140.08:04:42.31#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:04:42.31#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:04:42.31#ibcon#ireg 17 cls_cnt 0 2006.140.08:04:42.31#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:42.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:42.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:42.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:04:42.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:42.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:04:42.37#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:04:42.37#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:04:42.37$vc4f8/vb=6,4 2006.140.08:04:42.37#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.08:04:42.37#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.08:04:42.37#ibcon#ireg 11 cls_cnt 2 2006.140.08:04:42.37#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:42.43#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:42.43#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:42.45#ibcon#[27=AT06-04\r\n] 2006.140.08:04:42.48#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:42.48#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:04:42.48#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.08:04:42.48#ibcon#ireg 7 cls_cnt 0 2006.140.08:04:42.48#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:42.60#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:42.60#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:42.62#ibcon#[27=USB\r\n] 2006.140.08:04:42.67#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:42.67#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:04:42.67#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:04:42.67#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:04:42.67$vc4f8/vabw=wide 2006.140.08:04:42.67#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:04:42.67#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:04:42.67#ibcon#ireg 8 cls_cnt 0 2006.140.08:04:42.67#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:42.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:42.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:42.69#ibcon#[25=BW32\r\n] 2006.140.08:04:42.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:42.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:04:42.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:04:42.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:04:42.72$vc4f8/vbbw=wide 2006.140.08:04:42.72#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:04:42.72#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:04:42.72#ibcon#ireg 8 cls_cnt 0 2006.140.08:04:42.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:04:42.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:04:42.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:04:42.81#ibcon#[27=BW32\r\n] 2006.140.08:04:42.84#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:04:42.84#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:04:42.84#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:04:42.84#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:04:42.84$4f8m12a/ifd4f 2006.140.08:04:42.84$ifd4f/lo= 2006.140.08:04:42.84$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:04:42.84$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:04:42.84$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:04:42.84$ifd4f/patch= 2006.140.08:04:42.84$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:04:42.84$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:04:42.84$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:04:42.84$4f8m12a/"form=m,16.000,1:2 2006.140.08:04:42.84$4f8m12a/"tpicd 2006.140.08:04:42.84$4f8m12a/echo=off 2006.140.08:04:42.84$4f8m12a/xlog=off 2006.140.08:04:42.84:!2006.140.08:05:10 2006.140.08:04:53.14#trakl#Source acquired 2006.140.08:04:55.14#flagr#flagr/antenna,acquired 2006.140.08:05:10.00:preob 2006.140.08:05:11.14/onsource/TRACKING 2006.140.08:05:11.14:!2006.140.08:05:20 2006.140.08:05:20.00:data_valid=on 2006.140.08:05:20.00:midob 2006.140.08:05:20.14/onsource/TRACKING 2006.140.08:05:20.14/wx/22.79,993.4,98 2006.140.08:05:20.22/cable/+6.5008E-03 2006.140.08:05:21.31/va/01,08,usb,yes,67,71 2006.140.08:05:21.31/va/02,07,usb,yes,68,71 2006.140.08:05:21.31/va/03,06,usb,yes,72,73 2006.140.08:05:21.31/va/04,07,usb,yes,70,75 2006.140.08:05:21.31/va/05,07,usb,yes,72,76 2006.140.08:05:21.31/va/06,06,usb,yes,71,71 2006.140.08:05:21.31/va/07,06,usb,yes,72,71 2006.140.08:05:21.31/va/08,06,usb,yes,76,75 2006.140.08:05:21.54/valo/01,532.99,yes,locked 2006.140.08:05:21.54/valo/02,572.99,yes,locked 2006.140.08:05:21.54/valo/03,672.99,yes,locked 2006.140.08:05:21.54/valo/04,832.99,yes,locked 2006.140.08:05:21.54/valo/05,652.99,yes,locked 2006.140.08:05:21.54/valo/06,772.99,yes,locked 2006.140.08:05:21.54/valo/07,832.99,yes,locked 2006.140.08:05:21.54/valo/08,852.99,yes,locked 2006.140.08:05:22.63/vb/01,04,usb,yes,35,33 2006.140.08:05:22.63/vb/02,04,usb,yes,37,38 2006.140.08:05:22.63/vb/03,04,usb,yes,33,37 2006.140.08:05:22.63/vb/04,04,usb,yes,34,34 2006.140.08:05:22.63/vb/05,04,usb,yes,32,37 2006.140.08:05:22.63/vb/06,04,usb,yes,33,36 2006.140.08:05:22.63/vb/07,04,usb,yes,35,35 2006.140.08:05:22.63/vb/08,04,usb,yes,33,37 2006.140.08:05:22.87/vblo/01,632.99,yes,locked 2006.140.08:05:22.87/vblo/02,640.99,yes,locked 2006.140.08:05:22.87/vblo/03,656.99,yes,locked 2006.140.08:05:22.87/vblo/04,712.99,yes,locked 2006.140.08:05:22.87/vblo/05,744.99,yes,locked 2006.140.08:05:22.87/vblo/06,752.99,yes,locked 2006.140.08:05:22.87/vblo/07,734.99,yes,locked 2006.140.08:05:22.87/vblo/08,744.99,yes,locked 2006.140.08:05:23.02/vabw/8 2006.140.08:05:23.17/vbbw/8 2006.140.08:05:23.26/xfe/off,on,14.2 2006.140.08:05:23.65/ifatt/23,28,28,28 2006.140.08:05:24.10/fmout-gps/S +1.16E-07 2006.140.08:05:24.17:!2006.140.08:06:20 2006.140.08:06:20.00:data_valid=off 2006.140.08:06:20.00:postob 2006.140.08:06:20.15/cable/+6.5005E-03 2006.140.08:06:20.15/wx/22.71,993.2,98 2006.140.08:06:21.11/fmout-gps/S +1.15E-07 2006.140.08:06:21.11:scan_name=140-0807,k06140,70 2006.140.08:06:21.11:source=0536+145,053942.37,143345.6,2000.0,ccw 2006.140.08:06:21.14#flagr#flagr/antenna,new-source 2006.140.08:06:22.14:checkk5 2006.140.08:06:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:06:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:06:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:06:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:06:23.99/chk_obsdata//k5ts1/T1400805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:06:24.36/chk_obsdata//k5ts2/T1400805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:06:24.73/chk_obsdata//k5ts3/T1400805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:06:25.11/chk_obsdata//k5ts4/T1400805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:06:25.80/k5log//k5ts1_log_newline 2006.140.08:06:26.49/k5log//k5ts2_log_newline 2006.140.08:06:27.18/k5log//k5ts3_log_newline 2006.140.08:06:27.87/k5log//k5ts4_log_newline 2006.140.08:06:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:06:27.90:4f8m12a=2 2006.140.08:06:27.90$4f8m12a/echo=on 2006.140.08:06:27.90$4f8m12a/pcalon 2006.140.08:06:27.90$pcalon/"no phase cal control is implemented here 2006.140.08:06:27.90$4f8m12a/"tpicd=stop 2006.140.08:06:27.90$4f8m12a/vc4f8 2006.140.08:06:27.90$vc4f8/valo=1,532.99 2006.140.08:06:27.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:06:27.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:06:27.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:27.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:27.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:27.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:27.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:06:27.97#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:27.97#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:27.97#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:06:27.97#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:06:27.97$vc4f8/va=1,8 2006.140.08:06:27.97#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:06:27.97#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:06:27.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:27.97#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:27.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:27.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:27.99#ibcon#[25=AT01-08\r\n] 2006.140.08:06:28.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:28.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:28.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:06:28.02#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:28.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:28.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:28.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:28.17#ibcon#[25=USB\r\n] 2006.140.08:06:28.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:28.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:28.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:06:28.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:06:28.22$vc4f8/valo=2,572.99 2006.140.08:06:28.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:06:28.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:06:28.22#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:28.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:28.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:28.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:06:28.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:28.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:28.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:06:28.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:06:28.28$vc4f8/va=2,7 2006.140.08:06:28.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:06:28.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:06:28.28#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:28.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:28.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:28.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:28.36#ibcon#[25=AT02-07\r\n] 2006.140.08:06:28.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:28.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:28.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:06:28.39#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:28.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:28.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:28.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:28.53#ibcon#[25=USB\r\n] 2006.140.08:06:28.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:28.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:28.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:06:28.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:06:28.56$vc4f8/valo=3,672.99 2006.140.08:06:28.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:06:28.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:06:28.56#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:28.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:28.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:28.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:06:28.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:28.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:28.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:06:28.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:06:28.64$vc4f8/va=3,6 2006.140.08:06:28.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:06:28.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:06:28.64#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:28.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:28.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:28.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:28.70#ibcon#[25=AT03-06\r\n] 2006.140.08:06:28.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:28.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:28.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:06:28.73#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:28.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:28.79#abcon#<5=/15 1.3 4.0 22.70 98 993.1\r\n> 2006.140.08:06:28.81#abcon#{5=INTERFACE CLEAR} 2006.140.08:06:28.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:28.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:28.87#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:06:28.87#ibcon#[25=USB\r\n] 2006.140.08:06:28.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:28.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:28.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:06:28.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:06:28.90$vc4f8/valo=4,832.99 2006.140.08:06:28.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.08:06:28.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.08:06:28.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:28.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:28.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:28.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:06:28.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:28.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:28.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:06:28.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:06:28.96$vc4f8/va=4,7 2006.140.08:06:28.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.08:06:28.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.08:06:28.96#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:28.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:29.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:29.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:29.04#ibcon#[25=AT04-07\r\n] 2006.140.08:06:29.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:29.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:29.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.08:06:29.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:29.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:29.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:29.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:29.21#ibcon#[25=USB\r\n] 2006.140.08:06:29.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:29.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:29.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:06:29.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:06:29.24$vc4f8/valo=5,652.99 2006.140.08:06:29.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:06:29.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:06:29.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:29.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:29.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:29.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:06:29.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:29.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:29.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:06:29.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:06:29.30$vc4f8/va=5,7 2006.140.08:06:29.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.08:06:29.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.08:06:29.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:29.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:29.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:29.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:29.38#ibcon#[25=AT05-07\r\n] 2006.140.08:06:29.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:29.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:29.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.08:06:29.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:29.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:29.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:29.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:29.55#ibcon#[25=USB\r\n] 2006.140.08:06:29.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:29.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:29.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:06:29.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:06:29.58$vc4f8/valo=6,772.99 2006.140.08:06:29.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.08:06:29.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.08:06:29.58#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:29.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:29.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:29.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:06:29.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:29.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:29.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:06:29.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:06:29.64$vc4f8/va=6,6 2006.140.08:06:29.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.08:06:29.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.08:06:29.64#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:29.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:29.70#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:29.70#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:29.72#ibcon#[25=AT06-06\r\n] 2006.140.08:06:29.75#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:29.75#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:29.75#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.08:06:29.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:29.75#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:06:29.87#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:06:29.87#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:06:29.89#ibcon#[25=USB\r\n] 2006.140.08:06:29.92#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:06:29.92#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:06:29.92#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:06:29.92#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:06:29.92$vc4f8/valo=7,832.99 2006.140.08:06:29.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.08:06:29.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.08:06:29.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:29.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:06:29.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:06:29.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:06:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:06:29.98#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:06:29.98#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:06:29.98#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:06:29.98#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:06:29.98$vc4f8/va=7,6 2006.140.08:06:29.98#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.08:06:29.98#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.08:06:29.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:29.98#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:06:30.04#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:06:30.04#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:06:30.06#ibcon#[25=AT07-06\r\n] 2006.140.08:06:30.09#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:06:30.09#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:06:30.09#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.08:06:30.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:30.09#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:06:30.21#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:06:30.21#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:06:30.23#ibcon#[25=USB\r\n] 2006.140.08:06:30.26#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:06:30.26#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:06:30.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:06:30.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:06:30.26$vc4f8/valo=8,852.99 2006.140.08:06:30.26#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.08:06:30.26#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.08:06:30.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:30.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:06:30.26#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:06:30.26#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:06:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:06:30.32#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:06:30.32#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:06:30.32#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:06:30.32#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:06:30.32$vc4f8/va=8,6 2006.140.08:06:30.32#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.08:06:30.32#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.08:06:30.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:30.32#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:06:30.38#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:06:30.38#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:06:30.40#ibcon#[25=AT08-06\r\n] 2006.140.08:06:30.43#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:06:30.43#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:06:30.43#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.08:06:30.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:30.43#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:06:30.55#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:06:30.55#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:06:30.57#ibcon#[25=USB\r\n] 2006.140.08:06:30.60#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:06:30.60#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:06:30.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:06:30.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:06:30.60$vc4f8/vblo=1,632.99 2006.140.08:06:30.60#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:06:30.60#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:06:30.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:30.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:30.60#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:30.60#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:06:30.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:30.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:06:30.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:06:30.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:06:30.66$vc4f8/vb=1,4 2006.140.08:06:30.66#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:06:30.66#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:06:30.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:30.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:30.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:30.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:30.68#ibcon#[27=AT01-04\r\n] 2006.140.08:06:30.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:30.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:06:30.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:06:30.71#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:30.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:30.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:30.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:30.85#ibcon#[27=USB\r\n] 2006.140.08:06:30.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:30.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:06:30.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:06:30.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:06:30.88$vc4f8/vblo=2,640.99 2006.140.08:06:30.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:06:30.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:06:30.88#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:30.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:30.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:30.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:06:30.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:30.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:06:30.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:06:30.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:06:30.94$vc4f8/vb=2,4 2006.140.08:06:30.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:06:30.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:06:30.94#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:30.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:31.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:31.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:31.02#ibcon#[27=AT02-04\r\n] 2006.140.08:06:31.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:31.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:06:31.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:06:31.05#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:31.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:31.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:31.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:31.19#ibcon#[27=USB\r\n] 2006.140.08:06:31.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:31.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:06:31.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:06:31.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:06:31.22$vc4f8/vblo=3,656.99 2006.140.08:06:31.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:06:31.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:06:31.22#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:31.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:31.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:31.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:06:31.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:31.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:06:31.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:06:31.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:06:31.28$vc4f8/vb=3,4 2006.140.08:06:31.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:06:31.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:06:31.28#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:31.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:31.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:31.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:31.36#ibcon#[27=AT03-04\r\n] 2006.140.08:06:31.40#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:31.40#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:06:31.40#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:06:31.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:31.40#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:31.52#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:31.52#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:31.54#ibcon#[27=USB\r\n] 2006.140.08:06:31.57#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:31.57#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:06:31.57#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:06:31.57#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:06:31.57$vc4f8/vblo=4,712.99 2006.140.08:06:31.57#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.08:06:31.57#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.08:06:31.57#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:31.57#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:06:31.57#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:06:31.57#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:06:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:06:31.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:06:31.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:06:31.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:06:31.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:06:31.63$vc4f8/vb=4,4 2006.140.08:06:31.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.08:06:31.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.08:06:31.63#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:31.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:06:31.69#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:06:31.69#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:06:31.71#ibcon#[27=AT04-04\r\n] 2006.140.08:06:31.74#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:06:31.74#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:06:31.74#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.08:06:31.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:31.74#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:06:31.86#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:06:31.86#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:06:31.88#ibcon#[27=USB\r\n] 2006.140.08:06:31.91#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:06:31.91#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:06:31.91#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:06:31.91#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:06:31.91$vc4f8/vblo=5,744.99 2006.140.08:06:31.91#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.08:06:31.91#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.08:06:31.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:31.91#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:31.91#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:31.91#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:06:31.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:31.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:06:31.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:06:31.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:06:31.97$vc4f8/vb=5,4 2006.140.08:06:31.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.08:06:31.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.08:06:31.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:31.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:32.03#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:32.03#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:32.05#ibcon#[27=AT05-04\r\n] 2006.140.08:06:32.08#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:32.08#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:06:32.08#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.08:06:32.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:32.08#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:32.20#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:32.20#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:32.22#ibcon#[27=USB\r\n] 2006.140.08:06:32.25#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:32.25#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:06:32.25#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:06:32.25#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:06:32.25$vc4f8/vblo=6,752.99 2006.140.08:06:32.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:06:32.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:06:32.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:06:32.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:32.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:32.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:06:32.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:32.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:06:32.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:06:32.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:06:32.31$vc4f8/vb=6,4 2006.140.08:06:32.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.08:06:32.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.08:06:32.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:06:32.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:32.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:32.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:32.39#ibcon#[27=AT06-04\r\n] 2006.140.08:06:32.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:32.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:06:32.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.08:06:32.42#ibcon#ireg 7 cls_cnt 0 2006.140.08:06:32.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:32.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:32.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:32.56#ibcon#[27=USB\r\n] 2006.140.08:06:32.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:32.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:06:32.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:06:32.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:06:32.59$vc4f8/vabw=wide 2006.140.08:06:32.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.08:06:32.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.08:06:32.59#ibcon#ireg 8 cls_cnt 0 2006.140.08:06:32.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:32.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:32.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:32.61#ibcon#[25=BW32\r\n] 2006.140.08:06:32.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:32.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:06:32.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:06:32.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:06:32.64$vc4f8/vbbw=wide 2006.140.08:06:32.64#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:06:32.64#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:06:32.64#ibcon#ireg 8 cls_cnt 0 2006.140.08:06:32.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:06:32.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:06:32.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:06:32.73#ibcon#[27=BW32\r\n] 2006.140.08:06:32.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:06:32.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:06:32.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:06:32.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:06:32.76$4f8m12a/ifd4f 2006.140.08:06:32.76$ifd4f/lo= 2006.140.08:06:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:06:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:06:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:06:32.76$ifd4f/patch= 2006.140.08:06:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:06:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:06:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:06:32.76$4f8m12a/"form=m,16.000,1:2 2006.140.08:06:32.76$4f8m12a/"tpicd 2006.140.08:06:32.76$4f8m12a/echo=off 2006.140.08:06:32.76$4f8m12a/xlog=off 2006.140.08:06:32.76:!2006.140.08:07:00 2006.140.08:06:44.14#trakl#Source acquired 2006.140.08:06:45.14#flagr#flagr/antenna,acquired 2006.140.08:07:00.00:preob 2006.140.08:07:01.14/onsource/TRACKING 2006.140.08:07:01.14:!2006.140.08:07:10 2006.140.08:07:10.00:data_valid=on 2006.140.08:07:10.00:midob 2006.140.08:07:10.14/onsource/TRACKING 2006.140.08:07:10.14/wx/22.66,993.0,98 2006.140.08:07:10.20/cable/+6.5036E-03 2006.140.08:07:11.29/va/01,08,usb,yes,63,67 2006.140.08:07:11.29/va/02,07,usb,yes,64,67 2006.140.08:07:11.29/va/03,06,usb,yes,68,68 2006.140.08:07:11.29/va/04,07,usb,yes,66,70 2006.140.08:07:11.29/va/05,07,usb,yes,67,71 2006.140.08:07:11.29/va/06,06,usb,yes,66,66 2006.140.08:07:11.29/va/07,06,usb,yes,67,66 2006.140.08:07:11.29/va/08,06,usb,yes,71,69 2006.140.08:07:11.52/valo/01,532.99,yes,locked 2006.140.08:07:11.52/valo/02,572.99,yes,locked 2006.140.08:07:11.52/valo/03,672.99,yes,locked 2006.140.08:07:11.52/valo/04,832.99,yes,locked 2006.140.08:07:11.52/valo/05,652.99,yes,locked 2006.140.08:07:11.52/valo/06,772.99,yes,locked 2006.140.08:07:11.52/valo/07,832.99,yes,locked 2006.140.08:07:11.52/valo/08,852.99,yes,locked 2006.140.08:07:12.61/vb/01,04,usb,yes,34,32 2006.140.08:07:12.61/vb/02,04,usb,yes,35,37 2006.140.08:07:12.61/vb/03,04,usb,yes,32,36 2006.140.08:07:12.61/vb/04,04,usb,yes,33,33 2006.140.08:07:12.61/vb/05,04,usb,yes,31,35 2006.140.08:07:12.61/vb/06,04,usb,yes,32,35 2006.140.08:07:12.61/vb/07,04,usb,yes,34,34 2006.140.08:07:12.61/vb/08,04,usb,yes,32,35 2006.140.08:07:12.84/vblo/01,632.99,yes,locked 2006.140.08:07:12.84/vblo/02,640.99,yes,locked 2006.140.08:07:12.84/vblo/03,656.99,yes,locked 2006.140.08:07:12.84/vblo/04,712.99,yes,locked 2006.140.08:07:12.84/vblo/05,744.99,yes,locked 2006.140.08:07:12.84/vblo/06,752.99,yes,locked 2006.140.08:07:12.84/vblo/07,734.99,yes,locked 2006.140.08:07:12.84/vblo/08,744.99,yes,locked 2006.140.08:07:12.99/vabw/8 2006.140.08:07:13.14/vbbw/8 2006.140.08:07:13.23/xfe/off,on,15.2 2006.140.08:07:13.62/ifatt/23,28,28,28 2006.140.08:07:14.11/fmout-gps/S +1.15E-07 2006.140.08:07:14.15:!2006.140.08:08:20 2006.140.08:08:20.00:data_valid=off 2006.140.08:08:20.00:postob 2006.140.08:08:20.20/cable/+6.5045E-03 2006.140.08:08:20.20/wx/22.61,992.8,99 2006.140.08:08:21.11/fmout-gps/S +1.15E-07 2006.140.08:08:21.11:scan_name=140-0809,k06140,60 2006.140.08:08:21.11:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.140.08:08:22.14#flagr#flagr/antenna,new-source 2006.140.08:08:22.14:checkk5 2006.140.08:08:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:08:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:08:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:08:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:08:24.01/chk_obsdata//k5ts1/T1400807??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.140.08:08:24.38/chk_obsdata//k5ts2/T1400807??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.140.08:08:24.75/chk_obsdata//k5ts3/T1400807??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.140.08:08:25.13/chk_obsdata//k5ts4/T1400807??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.140.08:08:25.82/k5log//k5ts1_log_newline 2006.140.08:08:26.51/k5log//k5ts2_log_newline 2006.140.08:08:27.19/k5log//k5ts3_log_newline 2006.140.08:08:27.89/k5log//k5ts4_log_newline 2006.140.08:08:27.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:08:27.91:4f8m12a=2 2006.140.08:08:27.91$4f8m12a/echo=on 2006.140.08:08:27.91$4f8m12a/pcalon 2006.140.08:08:27.91$pcalon/"no phase cal control is implemented here 2006.140.08:08:27.91$4f8m12a/"tpicd=stop 2006.140.08:08:27.91$4f8m12a/vc4f8 2006.140.08:08:27.91$vc4f8/valo=1,532.99 2006.140.08:08:27.92#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:08:27.92#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:08:27.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:27.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:08:27.92#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:08:27.92#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:08:27.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:08:28.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:08:28.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:08:28.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:08:28.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:08:28.01$vc4f8/va=1,8 2006.140.08:08:28.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:08:28.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:08:28.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:28.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:08:28.01#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:08:28.01#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:08:28.04#ibcon#[25=AT01-08\r\n] 2006.140.08:08:28.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:08:28.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:08:28.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:08:28.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:28.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:08:28.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:08:28.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:08:28.22#ibcon#[25=USB\r\n] 2006.140.08:08:28.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:08:28.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:08:28.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:08:28.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:08:28.27$vc4f8/valo=2,572.99 2006.140.08:08:28.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:08:28.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:08:28.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:28.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:08:28.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:08:28.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:08:28.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:08:28.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:08:28.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:08:28.34#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:08:28.34#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:08:28.34$vc4f8/va=2,7 2006.140.08:08:28.34#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:08:28.34#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:08:28.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:28.34#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:08:28.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:08:28.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:08:28.41#ibcon#[25=AT02-07\r\n] 2006.140.08:08:28.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:08:28.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:08:28.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:08:28.44#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:28.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:08:28.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:08:28.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:08:28.58#ibcon#[25=USB\r\n] 2006.140.08:08:28.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:08:28.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:08:28.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:08:28.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:08:28.63$vc4f8/valo=3,672.99 2006.140.08:08:28.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:08:28.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:08:28.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:28.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:28.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:28.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:28.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:08:28.70#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:28.70#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:28.70#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:08:28.70#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:08:28.70$vc4f8/va=3,6 2006.140.08:08:28.70#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:08:28.70#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:08:28.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:28.70#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:28.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:28.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:28.77#ibcon#[25=AT03-06\r\n] 2006.140.08:08:28.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:28.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:28.80#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:08:28.80#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:28.80#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:28.92#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:28.92#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:28.94#ibcon#[25=USB\r\n] 2006.140.08:08:28.97#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:28.97#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:28.97#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:08:28.97#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:08:28.97$vc4f8/valo=4,832.99 2006.140.08:08:28.97#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:08:28.97#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:08:28.97#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:28.97#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:28.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:28.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:28.99#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:08:29.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:29.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:29.03#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:08:29.03#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:08:29.03$vc4f8/va=4,7 2006.140.08:08:29.03#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:08:29.03#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:08:29.03#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:29.03#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:29.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:29.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:29.11#ibcon#[25=AT04-07\r\n] 2006.140.08:08:29.14#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:29.14#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:29.14#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:08:29.14#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:29.14#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:29.26#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:29.26#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:29.28#ibcon#[25=USB\r\n] 2006.140.08:08:29.31#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:29.31#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:29.31#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:08:29.31#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:08:29.31$vc4f8/valo=5,652.99 2006.140.08:08:29.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:08:29.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:08:29.31#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:29.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:29.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:29.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:29.33#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:08:29.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:29.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:29.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:08:29.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:08:29.37$vc4f8/va=5,7 2006.140.08:08:29.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:08:29.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:08:29.37#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:29.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:29.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:29.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:29.45#ibcon#[25=AT05-07\r\n] 2006.140.08:08:29.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:29.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:29.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:08:29.49#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:29.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:29.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:29.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:29.63#ibcon#[25=USB\r\n] 2006.140.08:08:29.66#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:29.66#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:29.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:08:29.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:08:29.66$vc4f8/valo=6,772.99 2006.140.08:08:29.66#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:08:29.66#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:08:29.66#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:29.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:29.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:29.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:29.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:08:29.72#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:29.72#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:29.72#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:08:29.72#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:08:29.72$vc4f8/va=6,6 2006.140.08:08:29.72#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:08:29.72#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:08:29.72#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:29.72#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:29.78#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:29.78#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:29.80#ibcon#[25=AT06-06\r\n] 2006.140.08:08:29.83#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:29.83#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:29.83#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:08:29.83#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:29.83#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:29.95#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:29.95#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:29.97#ibcon#[25=USB\r\n] 2006.140.08:08:30.00#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:30.00#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:30.00#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:08:30.00#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:08:30.00$vc4f8/valo=7,832.99 2006.140.08:08:30.00#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:08:30.00#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:08:30.00#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:30.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:30.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:30.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:30.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:08:30.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:30.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:30.06#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:08:30.06#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:08:30.06$vc4f8/va=7,6 2006.140.08:08:30.06#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:08:30.06#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:08:30.06#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:30.06#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:30.12#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:30.12#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:30.14#ibcon#[25=AT07-06\r\n] 2006.140.08:08:30.17#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:30.17#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:30.17#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:08:30.17#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:30.17#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:08:30.29#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:08:30.29#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:08:30.31#ibcon#[25=USB\r\n] 2006.140.08:08:30.34#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:08:30.34#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:08:30.34#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:08:30.34#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:08:30.34$vc4f8/valo=8,852.99 2006.140.08:08:30.34#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:08:30.34#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:08:30.34#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:30.34#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:08:30.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:08:30.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:08:30.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:08:30.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:08:30.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:08:30.40#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:08:30.40#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:08:30.40$vc4f8/va=8,6 2006.140.08:08:30.40#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.08:08:30.40#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.08:08:30.40#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:30.40#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:08:30.46#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:08:30.46#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:08:30.48#ibcon#[25=AT08-06\r\n] 2006.140.08:08:30.51#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:08:30.51#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:08:30.51#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.08:08:30.51#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:30.51#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:08:30.63#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:08:30.63#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:08:30.65#ibcon#[25=USB\r\n] 2006.140.08:08:30.68#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:08:30.68#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:08:30.68#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:08:30.68#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:08:30.68$vc4f8/vblo=1,632.99 2006.140.08:08:30.68#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.08:08:30.68#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.08:08:30.68#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:30.68#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:08:30.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:08:30.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:08:30.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:08:30.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:08:30.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:08:30.74#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:08:30.74#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:08:30.74$vc4f8/vb=1,4 2006.140.08:08:30.74#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.08:08:30.74#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.08:08:30.74#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:30.74#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:08:30.74#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:08:30.74#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:08:30.76#ibcon#[27=AT01-04\r\n] 2006.140.08:08:30.79#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:08:30.79#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:08:30.79#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.08:08:30.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:30.79#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:08:30.91#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:08:30.91#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:08:30.93#ibcon#[27=USB\r\n] 2006.140.08:08:30.96#abcon#<5=/16 1.5 4.1 22.59 99 992.8\r\n> 2006.140.08:08:30.96#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:08:30.96#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:08:30.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:08:30.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:08:30.96$vc4f8/vblo=2,640.99 2006.140.08:08:30.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:08:30.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:08:30.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:30.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:08:30.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:08:30.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:08:30.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:08:30.98#abcon#{5=INTERFACE CLEAR} 2006.140.08:08:31.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:08:31.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:08:31.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:08:31.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:08:31.02$vc4f8/vb=2,4 2006.140.08:08:31.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:08:31.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:08:31.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:31.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:08:31.04#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:08:31.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:08:31.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:08:31.10#ibcon#[27=AT02-04\r\n] 2006.140.08:08:31.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:08:31.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:08:31.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:08:31.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:31.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:08:31.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:08:31.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:08:31.27#ibcon#[27=USB\r\n] 2006.140.08:08:31.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:08:31.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:08:31.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:08:31.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:08:31.30$vc4f8/vblo=3,656.99 2006.140.08:08:31.30#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:08:31.30#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:08:31.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:31.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:31.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:31.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:31.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:08:31.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:31.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:08:31.36#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:08:31.36#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:08:31.36$vc4f8/vb=3,4 2006.140.08:08:31.36#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:08:31.36#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:08:31.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:31.36#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:31.42#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:31.42#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:31.44#ibcon#[27=AT03-04\r\n] 2006.140.08:08:31.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:31.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:08:31.47#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:08:31.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:31.47#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:31.59#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:31.59#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:31.61#ibcon#[27=USB\r\n] 2006.140.08:08:31.64#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:31.64#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:08:31.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:08:31.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:08:31.64$vc4f8/vblo=4,712.99 2006.140.08:08:31.64#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:08:31.64#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:08:31.64#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:31.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:31.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:31.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:31.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:08:31.70#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:31.70#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:08:31.70#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:08:31.70#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:08:31.70$vc4f8/vb=4,4 2006.140.08:08:31.70#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:08:31.70#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:08:31.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:31.70#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:31.76#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:31.76#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:31.78#ibcon#[27=AT04-04\r\n] 2006.140.08:08:31.81#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:31.81#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:08:31.81#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:08:31.81#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:31.81#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:31.93#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:31.93#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:31.95#ibcon#[27=USB\r\n] 2006.140.08:08:31.98#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:31.98#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:08:31.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:08:31.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:08:31.98$vc4f8/vblo=5,744.99 2006.140.08:08:31.98#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:08:31.98#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:08:31.98#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:31.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:31.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:31.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:32.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:08:32.04#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:32.04#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:08:32.04#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:08:32.04#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:08:32.04$vc4f8/vb=5,4 2006.140.08:08:32.04#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:08:32.04#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:08:32.04#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:32.04#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:32.10#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:32.10#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:32.12#ibcon#[27=AT05-04\r\n] 2006.140.08:08:32.15#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:32.15#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:08:32.15#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:08:32.15#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:32.15#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:32.27#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:32.27#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:32.29#ibcon#[27=USB\r\n] 2006.140.08:08:32.32#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:32.32#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:08:32.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:08:32.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:08:32.32$vc4f8/vblo=6,752.99 2006.140.08:08:32.32#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:08:32.32#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:08:32.32#ibcon#ireg 17 cls_cnt 0 2006.140.08:08:32.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:32.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:32.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:32.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:08:32.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:32.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:08:32.38#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:08:32.38#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:08:32.38$vc4f8/vb=6,4 2006.140.08:08:32.38#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:08:32.38#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:08:32.38#ibcon#ireg 11 cls_cnt 2 2006.140.08:08:32.38#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:32.44#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:32.44#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:32.46#ibcon#[27=AT06-04\r\n] 2006.140.08:08:32.49#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:32.49#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:08:32.49#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:08:32.49#ibcon#ireg 7 cls_cnt 0 2006.140.08:08:32.49#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:32.61#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:32.61#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:32.63#ibcon#[27=USB\r\n] 2006.140.08:08:32.66#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:32.66#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:08:32.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:08:32.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:08:32.66$vc4f8/vabw=wide 2006.140.08:08:32.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:08:32.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:08:32.66#ibcon#ireg 8 cls_cnt 0 2006.140.08:08:32.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:32.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:32.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:32.68#ibcon#[25=BW32\r\n] 2006.140.08:08:32.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:32.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:08:32.71#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:08:32.71#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:08:32.71$vc4f8/vbbw=wide 2006.140.08:08:32.71#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:08:32.71#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:08:32.71#ibcon#ireg 8 cls_cnt 0 2006.140.08:08:32.71#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:08:32.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:08:32.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:08:32.80#ibcon#[27=BW32\r\n] 2006.140.08:08:32.83#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:08:32.83#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:08:32.83#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:08:32.83#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:08:32.83$4f8m12a/ifd4f 2006.140.08:08:32.83$ifd4f/lo= 2006.140.08:08:32.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:08:32.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:08:32.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:08:32.83$ifd4f/patch= 2006.140.08:08:32.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:08:32.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:08:32.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:08:32.83$4f8m12a/"form=m,16.000,1:2 2006.140.08:08:32.83$4f8m12a/"tpicd 2006.140.08:08:32.83$4f8m12a/echo=off 2006.140.08:08:32.83$4f8m12a/xlog=off 2006.140.08:08:32.83:!2006.140.08:09:00 2006.140.08:08:43.14#trakl#Source acquired 2006.140.08:08:44.14#flagr#flagr/antenna,acquired 2006.140.08:09:00.00:preob 2006.140.08:09:00.14/onsource/TRACKING 2006.140.08:09:00.14:!2006.140.08:09:10 2006.140.08:09:10.00:data_valid=on 2006.140.08:09:10.00:midob 2006.140.08:09:11.14/onsource/TRACKING 2006.140.08:09:11.14/wx/22.57,992.8,99 2006.140.08:09:11.19/cable/+6.5041E-03 2006.140.08:09:12.28/va/01,08,usb,yes,59,63 2006.140.08:09:12.28/va/02,07,usb,yes,60,63 2006.140.08:09:12.28/va/03,06,usb,yes,64,64 2006.140.08:09:12.28/va/04,07,usb,yes,62,66 2006.140.08:09:12.28/va/05,07,usb,yes,63,67 2006.140.08:09:12.28/va/06,06,usb,yes,62,62 2006.140.08:09:12.28/va/07,06,usb,yes,63,63 2006.140.08:09:12.28/va/08,06,usb,yes,67,66 2006.140.08:09:12.51/valo/01,532.99,yes,locked 2006.140.08:09:12.51/valo/02,572.99,yes,locked 2006.140.08:09:12.51/valo/03,672.99,yes,locked 2006.140.08:09:12.51/valo/04,832.99,yes,locked 2006.140.08:09:12.51/valo/05,652.99,yes,locked 2006.140.08:09:12.51/valo/06,772.99,yes,locked 2006.140.08:09:12.51/valo/07,832.99,yes,locked 2006.140.08:09:12.51/valo/08,852.99,yes,locked 2006.140.08:09:13.60/vb/01,04,usb,yes,33,31 2006.140.08:09:13.60/vb/02,04,usb,yes,35,36 2006.140.08:09:13.60/vb/03,04,usb,yes,31,35 2006.140.08:09:13.60/vb/04,04,usb,yes,32,32 2006.140.08:09:13.60/vb/05,04,usb,yes,30,34 2006.140.08:09:13.60/vb/06,04,usb,yes,31,34 2006.140.08:09:13.60/vb/07,04,usb,yes,33,33 2006.140.08:09:13.60/vb/08,04,usb,yes,31,34 2006.140.08:09:13.84/vblo/01,632.99,yes,locked 2006.140.08:09:13.84/vblo/02,640.99,yes,locked 2006.140.08:09:13.84/vblo/03,656.99,yes,locked 2006.140.08:09:13.84/vblo/04,712.99,yes,locked 2006.140.08:09:13.84/vblo/05,744.99,yes,locked 2006.140.08:09:13.84/vblo/06,752.99,yes,locked 2006.140.08:09:13.84/vblo/07,734.99,yes,locked 2006.140.08:09:13.84/vblo/08,744.99,yes,locked 2006.140.08:09:13.99/vabw/8 2006.140.08:09:14.14/vbbw/8 2006.140.08:09:14.23/xfe/off,on,15.5 2006.140.08:09:14.62/ifatt/23,28,28,28 2006.140.08:09:15.11/fmout-gps/S +1.15E-07 2006.140.08:09:15.18:!2006.140.08:10:10 2006.140.08:10:10.00:data_valid=off 2006.140.08:10:10.00:postob 2006.140.08:10:10.08/cable/+6.5044E-03 2006.140.08:10:10.09/wx/22.53,992.8,99 2006.140.08:10:11.10/fmout-gps/S +1.15E-07 2006.140.08:10:11.10:scan_name=140-0811,k06140,60 2006.140.08:10:11.10:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.140.08:10:11.14#flagr#flagr/antenna,new-source 2006.140.08:10:12.14:checkk5 2006.140.08:10:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:10:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:10:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:10:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:10:14.00/chk_obsdata//k5ts1/T1400809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:10:14.38/chk_obsdata//k5ts2/T1400809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:10:14.75/chk_obsdata//k5ts3/T1400809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:10:15.12/chk_obsdata//k5ts4/T1400809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:10:15.81/k5log//k5ts1_log_newline 2006.140.08:10:16.49/k5log//k5ts2_log_newline 2006.140.08:10:17.18/k5log//k5ts3_log_newline 2006.140.08:10:17.88/k5log//k5ts4_log_newline 2006.140.08:10:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:10:17.90:4f8m12a=2 2006.140.08:10:17.90$4f8m12a/echo=on 2006.140.08:10:17.90$4f8m12a/pcalon 2006.140.08:10:17.90$pcalon/"no phase cal control is implemented here 2006.140.08:10:17.90$4f8m12a/"tpicd=stop 2006.140.08:10:17.90$4f8m12a/vc4f8 2006.140.08:10:17.90$vc4f8/valo=1,532.99 2006.140.08:10:17.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.08:10:17.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.08:10:17.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:17.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:17.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:17.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:10:18.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:18.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:18.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:10:18.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:10:18.00$vc4f8/va=1,8 2006.140.08:10:18.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.08:10:18.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.08:10:18.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:18.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:18.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:18.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:18.03#ibcon#[25=AT01-08\r\n] 2006.140.08:10:18.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:18.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:18.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.08:10:18.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:18.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:18.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:18.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:18.21#ibcon#[25=USB\r\n] 2006.140.08:10:18.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:18.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:18.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:10:18.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:10:18.24$vc4f8/valo=2,572.99 2006.140.08:10:18.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.08:10:18.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.08:10:18.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:18.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:18.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:18.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:10:18.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:18.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:18.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:10:18.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:10:18.30$vc4f8/va=2,7 2006.140.08:10:18.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.08:10:18.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.08:10:18.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:18.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:18.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:18.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:18.38#ibcon#[25=AT02-07\r\n] 2006.140.08:10:18.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:18.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:18.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.08:10:18.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:18.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:18.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:18.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:18.55#ibcon#[25=USB\r\n] 2006.140.08:10:18.58#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:18.58#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:18.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:10:18.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:10:18.58$vc4f8/valo=3,672.99 2006.140.08:10:18.58#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:10:18.58#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:10:18.58#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:18.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:18.58#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:18.58#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:10:18.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:18.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:18.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:10:18.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:10:18.66$vc4f8/va=3,6 2006.140.08:10:18.66#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.08:10:18.66#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.08:10:18.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:18.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:18.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:18.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:18.72#ibcon#[25=AT03-06\r\n] 2006.140.08:10:18.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:18.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:18.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.08:10:18.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:18.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:18.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:18.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:18.89#ibcon#[25=USB\r\n] 2006.140.08:10:18.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:18.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:18.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:10:18.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:10:18.92$vc4f8/valo=4,832.99 2006.140.08:10:18.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:10:18.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:10:18.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:18.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:18.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:18.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:10:18.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:18.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:18.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:10:18.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:10:18.98$vc4f8/va=4,7 2006.140.08:10:18.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.08:10:18.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.08:10:18.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:18.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:19.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:19.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:19.06#ibcon#[25=AT04-07\r\n] 2006.140.08:10:19.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:19.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:19.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.08:10:19.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:19.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:19.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:19.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:19.23#ibcon#[25=USB\r\n] 2006.140.08:10:19.26#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:19.26#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:19.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:10:19.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:10:19.26$vc4f8/valo=5,652.99 2006.140.08:10:19.26#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.08:10:19.26#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.08:10:19.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:19.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:19.26#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:19.26#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:10:19.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:19.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:19.32#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:10:19.32#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:10:19.32$vc4f8/va=5,7 2006.140.08:10:19.32#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.08:10:19.32#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.08:10:19.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:19.32#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:19.38#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:19.38#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:19.40#ibcon#[25=AT05-07\r\n] 2006.140.08:10:19.43#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:19.43#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:19.43#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.08:10:19.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:19.43#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:19.55#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:19.55#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:19.57#ibcon#[25=USB\r\n] 2006.140.08:10:19.60#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:19.60#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:19.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:10:19.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:10:19.60$vc4f8/valo=6,772.99 2006.140.08:10:19.60#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:10:19.60#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:10:19.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:19.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:19.60#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:19.60#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:10:19.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:19.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:19.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:10:19.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:10:19.66$vc4f8/va=6,6 2006.140.08:10:19.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.08:10:19.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.08:10:19.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:19.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:19.72#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:19.72#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:19.74#ibcon#[25=AT06-06\r\n] 2006.140.08:10:19.77#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:19.77#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:19.77#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.08:10:19.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:19.77#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:10:19.89#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:10:19.89#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:10:19.91#ibcon#[25=USB\r\n] 2006.140.08:10:19.94#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:10:19.94#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:10:19.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:10:19.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:10:19.94$vc4f8/valo=7,832.99 2006.140.08:10:19.94#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:10:19.94#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:10:19.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:19.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:10:19.94#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:10:19.94#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:10:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:10:20.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:10:20.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:10:20.00#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:10:20.00#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:10:20.00$vc4f8/va=7,6 2006.140.08:10:20.00#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.08:10:20.00#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.08:10:20.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:20.00#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:10:20.06#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:10:20.06#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:10:20.08#ibcon#[25=AT07-06\r\n] 2006.140.08:10:20.11#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:10:20.11#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:10:20.11#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.08:10:20.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:20.11#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:10:20.23#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:10:20.23#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:10:20.25#ibcon#[25=USB\r\n] 2006.140.08:10:20.28#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:10:20.28#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:10:20.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:10:20.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:10:20.28$vc4f8/valo=8,852.99 2006.140.08:10:20.28#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:10:20.28#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:10:20.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:20.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:10:20.28#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:10:20.28#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:10:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:10:20.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:10:20.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:10:20.34#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:10:20.34#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:10:20.34$vc4f8/va=8,6 2006.140.08:10:20.34#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.08:10:20.34#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.08:10:20.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:20.34#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:10:20.40#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:10:20.40#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:10:20.42#ibcon#[25=AT08-06\r\n] 2006.140.08:10:20.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:10:20.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:10:20.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.08:10:20.46#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:20.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:10:20.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:10:20.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:10:20.60#ibcon#[25=USB\r\n] 2006.140.08:10:20.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:10:20.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:10:20.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:10:20.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:10:20.63$vc4f8/vblo=1,632.99 2006.140.08:10:20.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.08:10:20.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.08:10:20.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:20.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:10:20.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:10:20.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:10:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:10:20.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:10:20.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:10:20.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:10:20.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:10:20.69$vc4f8/vb=1,4 2006.140.08:10:20.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.08:10:20.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.08:10:20.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:20.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:10:20.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:10:20.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:10:20.71#ibcon#[27=AT01-04\r\n] 2006.140.08:10:20.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:10:20.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:10:20.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.08:10:20.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:20.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:10:20.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:10:20.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:10:20.88#ibcon#[27=USB\r\n] 2006.140.08:10:20.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:10:20.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:10:20.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:10:20.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:10:20.91$vc4f8/vblo=2,640.99 2006.140.08:10:20.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.08:10:20.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.08:10:20.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:20.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:20.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:20.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:10:20.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:20.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:10:20.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:10:20.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:10:20.97$vc4f8/vb=2,4 2006.140.08:10:20.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.08:10:20.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.08:10:20.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:20.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:21.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:21.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:21.05#ibcon#[27=AT02-04\r\n] 2006.140.08:10:21.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:21.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:10:21.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.08:10:21.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:21.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:21.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:21.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:21.22#ibcon#[27=USB\r\n] 2006.140.08:10:21.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:21.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:10:21.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:10:21.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:10:21.25$vc4f8/vblo=3,656.99 2006.140.08:10:21.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.08:10:21.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.08:10:21.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:21.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:21.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:21.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:10:21.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:21.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:10:21.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:10:21.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:10:21.33$vc4f8/vb=3,4 2006.140.08:10:21.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.08:10:21.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.08:10:21.33#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:21.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:21.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:21.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:21.39#ibcon#[27=AT03-04\r\n] 2006.140.08:10:21.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:21.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:10:21.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.08:10:21.42#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:21.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:21.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:21.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:21.56#ibcon#[27=USB\r\n] 2006.140.08:10:21.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:21.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:10:21.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:10:21.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:10:21.59$vc4f8/vblo=4,712.99 2006.140.08:10:21.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:10:21.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:10:21.59#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:21.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:21.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:21.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:10:21.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:21.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:10:21.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:10:21.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:10:21.65$vc4f8/vb=4,4 2006.140.08:10:21.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.08:10:21.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.08:10:21.65#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:21.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:21.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:21.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:21.73#ibcon#[27=AT04-04\r\n] 2006.140.08:10:21.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:21.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:10:21.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.08:10:21.76#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:21.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:21.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:21.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:21.90#ibcon#[27=USB\r\n] 2006.140.08:10:21.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:21.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:10:21.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:10:21.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:10:21.93$vc4f8/vblo=5,744.99 2006.140.08:10:21.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:10:21.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:10:21.93#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:21.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:21.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:21.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:10:21.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:21.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:10:21.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:10:21.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:10:21.99$vc4f8/vb=5,4 2006.140.08:10:21.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.08:10:21.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.08:10:21.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:21.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:22.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:22.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:22.07#ibcon#[27=AT05-04\r\n] 2006.140.08:10:22.11#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:22.11#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:10:22.11#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.08:10:22.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:22.11#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:22.23#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:22.23#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:22.25#ibcon#[27=USB\r\n] 2006.140.08:10:22.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:22.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:10:22.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:10:22.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:10:22.28$vc4f8/vblo=6,752.99 2006.140.08:10:22.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.08:10:22.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.08:10:22.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:10:22.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:22.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:22.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:10:22.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:22.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:10:22.34#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:10:22.34#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:10:22.34$vc4f8/vb=6,4 2006.140.08:10:22.34#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.140.08:10:22.34#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.140.08:10:22.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:10:22.34#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:22.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:22.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:22.42#ibcon#[27=AT06-04\r\n] 2006.140.08:10:22.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:22.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.140.08:10:22.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.140.08:10:22.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:10:22.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:22.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:22.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:22.59#ibcon#[27=USB\r\n] 2006.140.08:10:22.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:22.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.140.08:10:22.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:10:22.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:10:22.62$vc4f8/vabw=wide 2006.140.08:10:22.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:10:22.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:10:22.62#ibcon#ireg 8 cls_cnt 0 2006.140.08:10:22.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:22.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:22.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:22.64#ibcon#[25=BW32\r\n] 2006.140.08:10:22.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:22.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:10:22.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:10:22.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:10:22.67$vc4f8/vbbw=wide 2006.140.08:10:22.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:10:22.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:10:22.67#ibcon#ireg 8 cls_cnt 0 2006.140.08:10:22.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:10:22.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:10:22.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:10:22.76#ibcon#[27=BW32\r\n] 2006.140.08:10:22.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:10:22.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:10:22.79#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:10:22.79#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:10:22.79$4f8m12a/ifd4f 2006.140.08:10:22.79$ifd4f/lo= 2006.140.08:10:22.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:10:22.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:10:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:10:22.79$ifd4f/patch= 2006.140.08:10:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:10:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:10:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:10:22.79$4f8m12a/"form=m,16.000,1:2 2006.140.08:10:22.79$4f8m12a/"tpicd 2006.140.08:10:22.79$4f8m12a/echo=off 2006.140.08:10:22.79$4f8m12a/xlog=off 2006.140.08:10:22.79:!2006.140.08:10:50 2006.140.08:10:22.83#abcon#<5=/02 1.7 4.1 22.51 99 992.8\r\n> 2006.140.08:10:33.13#trakl#Source acquired 2006.140.08:10:35.13#flagr#flagr/antenna,acquired 2006.140.08:10:50.00:preob 2006.140.08:10:51.13/onsource/TRACKING 2006.140.08:10:51.13:!2006.140.08:11:00 2006.140.08:11:00.00:data_valid=on 2006.140.08:11:00.00:midob 2006.140.08:11:00.13/onsource/TRACKING 2006.140.08:11:00.13/wx/22.49,992.9,99 2006.140.08:11:00.27/cable/+6.5012E-03 2006.140.08:11:01.36/va/01,08,usb,yes,56,59 2006.140.08:11:01.36/va/02,07,usb,yes,57,59 2006.140.08:11:01.36/va/03,06,usb,yes,60,60 2006.140.08:11:01.36/va/04,07,usb,yes,58,62 2006.140.08:11:01.36/va/05,07,usb,yes,59,63 2006.140.08:11:01.36/va/06,06,usb,yes,59,58 2006.140.08:11:01.36/va/07,06,usb,yes,59,59 2006.140.08:11:01.36/va/08,06,usb,yes,63,62 2006.140.08:11:01.59/valo/01,532.99,yes,locked 2006.140.08:11:01.59/valo/02,572.99,yes,locked 2006.140.08:11:01.59/valo/03,672.99,yes,locked 2006.140.08:11:01.59/valo/04,832.99,yes,locked 2006.140.08:11:01.59/valo/05,652.99,yes,locked 2006.140.08:11:01.59/valo/06,772.99,yes,locked 2006.140.08:11:01.59/valo/07,832.99,yes,locked 2006.140.08:11:01.59/valo/08,852.99,yes,locked 2006.140.08:11:02.68/vb/01,04,usb,yes,32,30 2006.140.08:11:02.68/vb/02,04,usb,yes,34,35 2006.140.08:11:02.68/vb/03,04,usb,yes,30,34 2006.140.08:11:02.68/vb/04,04,usb,yes,31,31 2006.140.08:11:02.68/vb/05,04,usb,yes,30,34 2006.140.08:11:02.68/vb/06,04,usb,yes,31,34 2006.140.08:11:02.68/vb/07,04,usb,yes,33,33 2006.140.08:11:02.68/vb/08,04,usb,yes,30,34 2006.140.08:11:02.91/vblo/01,632.99,yes,locked 2006.140.08:11:02.91/vblo/02,640.99,yes,locked 2006.140.08:11:02.91/vblo/03,656.99,yes,locked 2006.140.08:11:02.91/vblo/04,712.99,yes,locked 2006.140.08:11:02.91/vblo/05,744.99,yes,locked 2006.140.08:11:02.91/vblo/06,752.99,yes,locked 2006.140.08:11:02.91/vblo/07,734.99,yes,locked 2006.140.08:11:02.91/vblo/08,744.99,yes,locked 2006.140.08:11:03.06/vabw/8 2006.140.08:11:03.21/vbbw/8 2006.140.08:11:03.30/xfe/off,on,14.5 2006.140.08:11:03.68/ifatt/23,28,28,28 2006.140.08:11:04.10/fmout-gps/S +1.17E-07 2006.140.08:11:04.14:!2006.140.08:12:00 2006.140.08:12:00.00:data_valid=off 2006.140.08:12:00.00:postob 2006.140.08:12:00.08/cable/+6.5026E-03 2006.140.08:12:00.08/wx/22.45,992.9,99 2006.140.08:12:01.11/fmout-gps/S +1.16E-07 2006.140.08:12:01.11:scan_name=140-0812,k06140,60 2006.140.08:12:01.11:source=1803+784,180045.68,782804.0,2000.0,cw 2006.140.08:12:01.13#flagr#flagr/antenna,new-source 2006.140.08:12:02.13:checkk5 2006.140.08:12:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:12:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:12:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:12:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:12:04.00/chk_obsdata//k5ts1/T1400811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:12:04.37/chk_obsdata//k5ts2/T1400811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:12:04.73/chk_obsdata//k5ts3/T1400811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:12:05.11/chk_obsdata//k5ts4/T1400811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:12:05.80/k5log//k5ts1_log_newline 2006.140.08:12:06.48/k5log//k5ts2_log_newline 2006.140.08:12:07.18/k5log//k5ts3_log_newline 2006.140.08:12:07.87/k5log//k5ts4_log_newline 2006.140.08:12:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:12:07.89:4f8m12a=2 2006.140.08:12:07.89$4f8m12a/echo=on 2006.140.08:12:07.89$4f8m12a/pcalon 2006.140.08:12:07.89$pcalon/"no phase cal control is implemented here 2006.140.08:12:07.89$4f8m12a/"tpicd=stop 2006.140.08:12:07.89$4f8m12a/vc4f8 2006.140.08:12:07.89$vc4f8/valo=1,532.99 2006.140.08:12:07.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:12:07.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:12:07.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:07.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:07.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:07.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:12:07.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:07.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:07.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:12:07.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:12:07.99$vc4f8/va=1,8 2006.140.08:12:07.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.08:12:07.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.08:12:07.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:07.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:07.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:07.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:08.02#ibcon#[25=AT01-08\r\n] 2006.140.08:12:08.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:08.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:08.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.08:12:08.06#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:08.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:08.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:08.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:08.22#ibcon#[25=USB\r\n] 2006.140.08:12:08.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:08.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:08.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:12:08.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:12:08.25$vc4f8/valo=2,572.99 2006.140.08:12:08.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.08:12:08.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.08:12:08.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:08.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:08.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:08.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:08.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:12:08.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:08.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:08.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:12:08.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:12:08.31$vc4f8/va=2,7 2006.140.08:12:08.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.08:12:08.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.08:12:08.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:08.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:08.38#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:08.38#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:08.40#ibcon#[25=AT02-07\r\n] 2006.140.08:12:08.43#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:08.43#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:08.43#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.08:12:08.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:08.43#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:08.55#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:08.55#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:08.57#ibcon#[25=USB\r\n] 2006.140.08:12:08.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:08.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:08.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:12:08.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:12:08.62$vc4f8/valo=3,672.99 2006.140.08:12:08.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.08:12:08.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.08:12:08.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:08.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:08.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:08.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:08.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:12:08.69#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:08.69#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:08.69#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:12:08.69#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:12:08.69$vc4f8/va=3,6 2006.140.08:12:08.69#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.08:12:08.69#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.08:12:08.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:08.69#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:08.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:08.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:08.76#ibcon#[25=AT03-06\r\n] 2006.140.08:12:08.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:08.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:08.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.08:12:08.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:08.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:08.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:08.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:08.93#ibcon#[25=USB\r\n] 2006.140.08:12:08.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:08.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:08.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:12:08.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:12:08.96$vc4f8/valo=4,832.99 2006.140.08:12:08.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.08:12:08.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.08:12:08.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:08.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:08.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:08.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:08.98#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:12:09.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:09.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:09.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:12:09.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:12:09.02$vc4f8/va=4,7 2006.140.08:12:09.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.08:12:09.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.08:12:09.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:09.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:09.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:09.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:09.10#ibcon#[25=AT04-07\r\n] 2006.140.08:12:09.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:09.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:09.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.08:12:09.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:09.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:09.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:09.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:09.27#ibcon#[25=USB\r\n] 2006.140.08:12:09.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:09.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:09.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:12:09.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:12:09.30$vc4f8/valo=5,652.99 2006.140.08:12:09.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:12:09.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:12:09.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:09.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:09.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:09.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:09.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:12:09.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:09.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:09.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:12:09.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:12:09.36$vc4f8/va=5,7 2006.140.08:12:09.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.08:12:09.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.08:12:09.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:09.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:09.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:09.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:09.44#ibcon#[25=AT05-07\r\n] 2006.140.08:12:09.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:09.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:09.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.08:12:09.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:09.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:09.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:09.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:09.61#ibcon#[25=USB\r\n] 2006.140.08:12:09.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:09.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:09.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:12:09.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:12:09.64$vc4f8/valo=6,772.99 2006.140.08:12:09.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:12:09.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:12:09.64#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:09.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:09.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:09.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:09.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:12:09.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:09.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:09.70#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:12:09.70#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:12:09.70$vc4f8/va=6,6 2006.140.08:12:09.70#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.08:12:09.70#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.08:12:09.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:09.70#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:09.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:09.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:09.78#ibcon#[25=AT06-06\r\n] 2006.140.08:12:09.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:09.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:09.81#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.08:12:09.81#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:09.81#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:12:09.93#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:12:09.93#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:12:09.95#ibcon#[25=USB\r\n] 2006.140.08:12:09.98#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:12:09.98#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:12:09.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:12:09.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:12:09.98$vc4f8/valo=7,832.99 2006.140.08:12:09.98#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.08:12:09.98#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.08:12:09.98#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:09.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:12:09.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:12:09.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:12:10.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:12:10.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:12:10.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:12:10.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:12:10.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:12:10.04$vc4f8/va=7,6 2006.140.08:12:10.04#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.08:12:10.04#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.08:12:10.04#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:10.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:12:10.10#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:12:10.10#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:12:10.12#ibcon#[25=AT07-06\r\n] 2006.140.08:12:10.15#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:12:10.15#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:12:10.15#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.08:12:10.15#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:10.15#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:12:10.27#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:12:10.27#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:12:10.29#ibcon#[25=USB\r\n] 2006.140.08:12:10.32#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:12:10.32#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:12:10.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:12:10.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:12:10.32$vc4f8/valo=8,852.99 2006.140.08:12:10.32#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:12:10.32#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:12:10.32#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:10.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:12:10.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:12:10.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:12:10.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:12:10.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:12:10.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:12:10.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:12:10.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:12:10.40$vc4f8/va=8,6 2006.140.08:12:10.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.08:12:10.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.08:12:10.40#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:10.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:12:10.44#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:12:10.44#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:12:10.46#ibcon#[25=AT08-06\r\n] 2006.140.08:12:10.49#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:12:10.49#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:12:10.49#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.08:12:10.49#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:10.49#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:12:10.61#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:12:10.61#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:12:10.63#ibcon#[25=USB\r\n] 2006.140.08:12:10.66#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:12:10.66#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:12:10.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:12:10.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:12:10.66$vc4f8/vblo=1,632.99 2006.140.08:12:10.66#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:12:10.66#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:12:10.66#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:10.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:12:10.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:12:10.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:12:10.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:12:10.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:12:10.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:12:10.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:12:10.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:12:10.72$vc4f8/vb=1,4 2006.140.08:12:10.72#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.08:12:10.72#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.08:12:10.72#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:10.72#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:12:10.72#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:12:10.72#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:12:10.74#ibcon#[27=AT01-04\r\n] 2006.140.08:12:10.77#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:12:10.77#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:12:10.77#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.08:12:10.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:10.77#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:12:10.89#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:12:10.89#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:12:10.91#ibcon#[27=USB\r\n] 2006.140.08:12:10.94#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:12:10.94#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:12:10.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:12:10.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:12:10.94$vc4f8/vblo=2,640.99 2006.140.08:12:10.94#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:12:10.94#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:12:10.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:10.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:10.94#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:10.94#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:10.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:12:11.01#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:11.01#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:12:11.01#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:12:11.01#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:12:11.01$vc4f8/vb=2,4 2006.140.08:12:11.01#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.08:12:11.01#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.08:12:11.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:11.01#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:11.06#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:11.06#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:11.08#ibcon#[27=AT02-04\r\n] 2006.140.08:12:11.11#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:11.11#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:12:11.11#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.08:12:11.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:11.11#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:11.23#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:11.23#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:11.25#ibcon#[27=USB\r\n] 2006.140.08:12:11.28#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:11.28#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:12:11.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:12:11.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:12:11.28$vc4f8/vblo=3,656.99 2006.140.08:12:11.28#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.08:12:11.28#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.08:12:11.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:11.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:11.28#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:11.28#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:11.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:12:11.34#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:11.34#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:12:11.34#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:12:11.34#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:12:11.34$vc4f8/vb=3,4 2006.140.08:12:11.34#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.08:12:11.34#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.08:12:11.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:11.34#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:11.40#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:11.40#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:11.42#ibcon#[27=AT03-04\r\n] 2006.140.08:12:11.45#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:11.45#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:12:11.45#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.08:12:11.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:11.45#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:11.57#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:11.57#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:11.59#ibcon#[27=USB\r\n] 2006.140.08:12:11.62#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:11.62#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:12:11.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:12:11.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:12:11.62$vc4f8/vblo=4,712.99 2006.140.08:12:11.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.08:12:11.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.08:12:11.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:11.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:11.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:11.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:11.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:12:11.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:11.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:12:11.68#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:12:11.68#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:12:11.68$vc4f8/vb=4,4 2006.140.08:12:11.68#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.08:12:11.68#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.08:12:11.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:11.68#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:11.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:11.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:11.76#ibcon#[27=AT04-04\r\n] 2006.140.08:12:11.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:11.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:12:11.79#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.08:12:11.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:11.79#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:11.91#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:11.91#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:11.93#ibcon#[27=USB\r\n] 2006.140.08:12:11.96#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:11.96#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:12:11.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:12:11.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:12:11.96$vc4f8/vblo=5,744.99 2006.140.08:12:11.96#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.08:12:11.96#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.08:12:11.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:11.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:11.96#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:11.96#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:11.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:12:12.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:12.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:12:12.02#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:12:12.02#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:12:12.02$vc4f8/vb=5,4 2006.140.08:12:12.02#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.08:12:12.02#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.08:12:12.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:12.02#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:12.08#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:12.08#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:12.10#ibcon#[27=AT05-04\r\n] 2006.140.08:12:12.13#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:12.13#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:12:12.13#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.08:12:12.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:12.13#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:12.25#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:12.25#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:12.27#ibcon#[27=USB\r\n] 2006.140.08:12:12.30#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:12.30#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:12:12.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:12:12.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:12:12.30$vc4f8/vblo=6,752.99 2006.140.08:12:12.30#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:12:12.30#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:12:12.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:12:12.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:12.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:12.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:12:12.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:12.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:12:12.36#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:12:12.36#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:12:12.36$vc4f8/vb=6,4 2006.140.08:12:12.36#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.08:12:12.36#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.08:12:12.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:12:12.36#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:12.42#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:12.42#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:12.44#ibcon#[27=AT06-04\r\n] 2006.140.08:12:12.47#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:12.47#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:12:12.47#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.08:12:12.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:12:12.47#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:12.59#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:12.59#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:12.61#ibcon#[27=USB\r\n] 2006.140.08:12:12.64#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:12.64#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:12:12.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:12:12.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:12:12.64$vc4f8/vabw=wide 2006.140.08:12:12.64#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:12:12.64#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:12:12.64#ibcon#ireg 8 cls_cnt 0 2006.140.08:12:12.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:12.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:12.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:12.66#ibcon#[25=BW32\r\n] 2006.140.08:12:12.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:12.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:12:12.69#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:12:12.69#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:12:12.69$vc4f8/vbbw=wide 2006.140.08:12:12.69#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:12:12.69#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:12:12.69#ibcon#ireg 8 cls_cnt 0 2006.140.08:12:12.69#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:12:12.76#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:12:12.76#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:12:12.78#ibcon#[27=BW32\r\n] 2006.140.08:12:12.81#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:12:12.81#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:12:12.81#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:12:12.81#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:12:12.81$4f8m12a/ifd4f 2006.140.08:12:12.81$ifd4f/lo= 2006.140.08:12:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:12:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:12:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:12:12.81$ifd4f/patch= 2006.140.08:12:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:12:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:12:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:12:12.81$4f8m12a/"form=m,16.000,1:2 2006.140.08:12:12.81$4f8m12a/"tpicd 2006.140.08:12:12.81$4f8m12a/echo=off 2006.140.08:12:12.81$4f8m12a/xlog=off 2006.140.08:12:12.81:!2006.140.08:12:40 2006.140.08:12:24.14#trakl#Source acquired 2006.140.08:12:25.14#flagr#flagr/antenna,acquired 2006.140.08:12:40.00:preob 2006.140.08:12:41.14/onsource/TRACKING 2006.140.08:12:41.14:!2006.140.08:12:50 2006.140.08:12:50.00:data_valid=on 2006.140.08:12:50.00:midob 2006.140.08:12:50.14/onsource/TRACKING 2006.140.08:12:50.14/wx/22.43,992.9,100 2006.140.08:12:50.33/cable/+6.5054E-03 2006.140.08:12:51.42/va/01,08,usb,yes,51,54 2006.140.08:12:51.42/va/02,07,usb,yes,52,54 2006.140.08:12:51.42/va/03,06,usb,yes,55,56 2006.140.08:12:51.42/va/04,07,usb,yes,54,57 2006.140.08:12:51.42/va/05,07,usb,yes,54,58 2006.140.08:12:51.42/va/06,06,usb,yes,54,53 2006.140.08:12:51.42/va/07,06,usb,yes,54,54 2006.140.08:12:51.42/va/08,06,usb,yes,58,57 2006.140.08:12:51.65/valo/01,532.99,yes,locked 2006.140.08:12:51.65/valo/02,572.99,yes,locked 2006.140.08:12:51.65/valo/03,672.99,yes,locked 2006.140.08:12:51.65/valo/04,832.99,yes,locked 2006.140.08:12:51.65/valo/05,652.99,yes,locked 2006.140.08:12:51.65/valo/06,772.99,yes,locked 2006.140.08:12:51.65/valo/07,832.99,yes,locked 2006.140.08:12:51.65/valo/08,852.99,yes,locked 2006.140.08:12:52.74/vb/01,04,usb,yes,31,32 2006.140.08:12:52.74/vb/02,04,usb,yes,33,36 2006.140.08:12:52.74/vb/03,04,usb,yes,29,33 2006.140.08:12:52.74/vb/04,04,usb,yes,30,30 2006.140.08:12:52.74/vb/05,04,usb,yes,29,33 2006.140.08:12:52.74/vb/06,04,usb,yes,30,33 2006.140.08:12:52.74/vb/07,04,usb,yes,32,32 2006.140.08:12:52.74/vb/08,04,usb,yes,29,33 2006.140.08:12:52.97/vblo/01,632.99,yes,locked 2006.140.08:12:52.97/vblo/02,640.99,yes,locked 2006.140.08:12:52.97/vblo/03,656.99,yes,locked 2006.140.08:12:52.97/vblo/04,712.99,yes,locked 2006.140.08:12:52.97/vblo/05,744.99,yes,locked 2006.140.08:12:52.97/vblo/06,752.99,yes,locked 2006.140.08:12:52.97/vblo/07,734.99,yes,locked 2006.140.08:12:52.97/vblo/08,744.99,yes,locked 2006.140.08:12:53.12/vabw/8 2006.140.08:12:53.27/vbbw/8 2006.140.08:12:53.38/xfe/off,on,14.2 2006.140.08:12:53.77/ifatt/23,28,28,28 2006.140.08:12:54.11/fmout-gps/S +1.16E-07 2006.140.08:12:54.18:!2006.140.08:13:50 2006.140.08:13:50.00:data_valid=off 2006.140.08:13:50.00:postob 2006.140.08:13:50.11/cable/+6.5025E-03 2006.140.08:13:50.11/wx/22.40,992.9,100 2006.140.08:13:51.11/fmout-gps/S +1.17E-07 2006.140.08:13:51.11:scan_name=140-0814,k06140,60 2006.140.08:13:51.11:source=1418+546,141946.60,542314.8,2000.0,cw 2006.140.08:13:51.14#flagr#flagr/antenna,new-source 2006.140.08:13:52.14:checkk5 2006.140.08:13:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:13:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:13:56.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:13:56.63/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:13:57.01/chk_obsdata//k5ts1/T1400812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:13:57.38/chk_obsdata//k5ts2/T1400812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:13:57.75/chk_obsdata//k5ts3/T1400812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:13:58.12/chk_obsdata//k5ts4/T1400812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:13:58.82/k5log//k5ts1_log_newline 2006.140.08:13:59.50/k5log//k5ts2_log_newline 2006.140.08:14:00.20/k5log//k5ts3_log_newline 2006.140.08:14:00.89/k5log//k5ts4_log_newline 2006.140.08:14:00.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:14:00.91:4f8m12a=2 2006.140.08:14:00.91$4f8m12a/echo=on 2006.140.08:14:00.91$4f8m12a/pcalon 2006.140.08:14:00.91$pcalon/"no phase cal control is implemented here 2006.140.08:14:00.91$4f8m12a/"tpicd=stop 2006.140.08:14:00.91$4f8m12a/vc4f8 2006.140.08:14:00.91$vc4f8/valo=1,532.99 2006.140.08:14:00.92#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.08:14:00.92#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.08:14:00.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:00.92#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:00.92#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:00.92#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:00.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:14:01.01#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:01.01#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:01.01#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:14:01.01#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:14:01.01$vc4f8/va=1,8 2006.140.08:14:01.01#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.08:14:01.01#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.08:14:01.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:01.01#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:01.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:01.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:01.04#ibcon#[25=AT01-08\r\n] 2006.140.08:14:01.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:01.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:01.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.08:14:01.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:01.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:01.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:01.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:01.23#ibcon#[25=USB\r\n] 2006.140.08:14:01.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:01.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:01.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:14:01.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:14:01.27$vc4f8/valo=2,572.99 2006.140.08:14:01.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.08:14:01.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.08:14:01.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:01.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:01.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:01.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:01.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:14:01.35#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:01.35#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:01.35#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:14:01.35#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:14:01.35$vc4f8/va=2,7 2006.140.08:14:01.35#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.08:14:01.35#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.08:14:01.35#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:01.35#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:01.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:01.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:01.41#ibcon#[25=AT02-07\r\n] 2006.140.08:14:01.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:01.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:01.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.08:14:01.44#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:01.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:01.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:01.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:01.58#ibcon#[25=USB\r\n] 2006.140.08:14:01.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:01.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:01.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:14:01.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:14:01.61$vc4f8/valo=3,672.99 2006.140.08:14:01.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:14:01.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:14:01.61#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:01.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:01.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:01.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:01.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:14:01.69#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:01.69#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:01.69#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:14:01.69#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:14:01.69$vc4f8/va=3,6 2006.140.08:14:01.69#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:14:01.69#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:14:01.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:01.69#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:01.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:01.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:01.75#ibcon#[25=AT03-06\r\n] 2006.140.08:14:01.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:01.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:01.78#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:14:01.78#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:01.78#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:01.90#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:01.90#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:01.92#ibcon#[25=USB\r\n] 2006.140.08:14:01.95#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:01.95#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:01.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:14:01.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:14:01.95$vc4f8/valo=4,832.99 2006.140.08:14:01.95#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:14:01.95#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:14:01.95#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:01.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:01.95#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:01.95#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:01.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:14:02.01#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:02.01#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:02.01#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:14:02.01#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:14:02.01$vc4f8/va=4,7 2006.140.08:14:02.01#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:14:02.01#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:14:02.01#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:02.01#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:02.07#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:02.07#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:02.09#ibcon#[25=AT04-07\r\n] 2006.140.08:14:02.12#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:02.12#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:02.12#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:14:02.12#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:02.12#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:02.24#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:02.24#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:02.26#ibcon#[25=USB\r\n] 2006.140.08:14:02.29#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:02.29#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:02.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:14:02.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:14:02.29$vc4f8/valo=5,652.99 2006.140.08:14:02.29#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:14:02.29#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:14:02.29#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:02.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:02.29#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:02.29#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:02.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:14:02.35#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:02.35#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:02.35#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:14:02.35#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:14:02.35$vc4f8/va=5,7 2006.140.08:14:02.35#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:14:02.35#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:14:02.35#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:02.35#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:02.41#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:02.41#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:02.43#ibcon#[25=AT05-07\r\n] 2006.140.08:14:02.46#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:02.46#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:02.46#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:14:02.46#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:02.46#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:02.58#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:02.58#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:02.60#ibcon#[25=USB\r\n] 2006.140.08:14:02.63#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:02.63#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:02.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:14:02.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:14:02.63$vc4f8/valo=6,772.99 2006.140.08:14:02.63#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.08:14:02.63#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.08:14:02.63#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:02.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:02.63#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:02.63#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:02.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:14:02.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:02.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:02.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:14:02.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:14:02.69$vc4f8/va=6,6 2006.140.08:14:02.69#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.08:14:02.69#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.08:14:02.69#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:02.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:02.75#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:02.75#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:02.77#ibcon#[25=AT06-06\r\n] 2006.140.08:14:02.80#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:02.80#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:02.80#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.08:14:02.80#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:02.80#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:14:02.92#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:14:02.92#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:14:02.94#ibcon#[25=USB\r\n] 2006.140.08:14:02.97#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:14:02.97#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:14:02.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:14:02.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:14:02.97$vc4f8/valo=7,832.99 2006.140.08:14:02.97#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.08:14:02.97#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.08:14:02.97#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:02.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:14:02.97#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:14:02.97#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:14:02.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:14:03.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:14:03.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:14:03.03#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:14:03.03#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:14:03.03$vc4f8/va=7,6 2006.140.08:14:03.03#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.08:14:03.03#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.08:14:03.03#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:03.03#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:14:03.09#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:14:03.09#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:14:03.11#ibcon#[25=AT07-06\r\n] 2006.140.08:14:03.14#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:14:03.14#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:14:03.14#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.08:14:03.14#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:03.14#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:14:03.26#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:14:03.26#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:14:03.28#ibcon#[25=USB\r\n] 2006.140.08:14:03.31#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:14:03.31#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:14:03.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:14:03.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:14:03.31$vc4f8/valo=8,852.99 2006.140.08:14:03.31#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:14:03.31#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:14:03.31#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:03.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:14:03.31#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:14:03.31#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:14:03.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:14:03.37#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:14:03.37#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:14:03.37#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:14:03.37#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:14:03.37$vc4f8/va=8,6 2006.140.08:14:03.37#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.08:14:03.37#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.08:14:03.37#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:03.37#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:14:03.43#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:14:03.43#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:14:03.45#ibcon#[25=AT08-06\r\n] 2006.140.08:14:03.48#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:14:03.48#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:14:03.48#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.08:14:03.48#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:03.48#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:14:03.60#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:14:03.60#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:14:03.62#ibcon#[25=USB\r\n] 2006.140.08:14:03.65#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:14:03.65#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:14:03.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:14:03.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:14:03.65$vc4f8/vblo=1,632.99 2006.140.08:14:03.65#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.08:14:03.65#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.08:14:03.65#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:03.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:14:03.65#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:14:03.65#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:14:03.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:14:03.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:14:03.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:14:03.71#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:14:03.71#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:14:03.71$vc4f8/vb=1,4 2006.140.08:14:03.71#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.08:14:03.71#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.08:14:03.71#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:03.71#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:14:03.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:14:03.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:14:03.73#ibcon#[27=AT01-04\r\n] 2006.140.08:14:03.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:14:03.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:14:03.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.08:14:03.76#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:03.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:14:03.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:14:03.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:14:03.90#ibcon#[27=USB\r\n] 2006.140.08:14:03.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:14:03.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:14:03.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:14:03.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:14:03.93$vc4f8/vblo=2,640.99 2006.140.08:14:03.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.08:14:03.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.08:14:03.93#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:03.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:03.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:03.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:03.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:14:03.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:03.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:14:03.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:14:03.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:14:03.99$vc4f8/vb=2,4 2006.140.08:14:03.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.08:14:03.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.08:14:03.99#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:03.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:04.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:04.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:04.07#ibcon#[27=AT02-04\r\n] 2006.140.08:14:04.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:04.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:14:04.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.08:14:04.10#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:04.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:04.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:04.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:04.24#ibcon#[27=USB\r\n] 2006.140.08:14:04.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:04.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:14:04.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:14:04.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:14:04.27$vc4f8/vblo=3,656.99 2006.140.08:14:04.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.08:14:04.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.08:14:04.27#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:04.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:04.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:04.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:04.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:14:04.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:04.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:14:04.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:14:04.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:14:04.33$vc4f8/vb=3,4 2006.140.08:14:04.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.08:14:04.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.08:14:04.33#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:04.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:04.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:04.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:04.41#ibcon#[27=AT03-04\r\n] 2006.140.08:14:04.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:04.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:14:04.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.08:14:04.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:04.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:04.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:04.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:04.59#ibcon#[27=USB\r\n] 2006.140.08:14:04.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:04.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:14:04.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:14:04.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:14:04.62$vc4f8/vblo=4,712.99 2006.140.08:14:04.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:14:04.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:14:04.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:04.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:04.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:04.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:04.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:14:04.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:04.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:14:04.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:14:04.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:14:04.68$vc4f8/vb=4,4 2006.140.08:14:04.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:14:04.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:14:04.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:04.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:04.74#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:04.74#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:04.76#ibcon#[27=AT04-04\r\n] 2006.140.08:14:04.79#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:04.79#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:14:04.79#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:14:04.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:04.79#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:04.91#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:04.91#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:04.93#ibcon#[27=USB\r\n] 2006.140.08:14:04.96#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:04.96#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:14:04.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:14:04.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:14:04.96$vc4f8/vblo=5,744.99 2006.140.08:14:04.96#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:14:04.96#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:14:04.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:04.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:04.96#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:04.96#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:04.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:14:05.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:05.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:14:05.02#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:14:05.02#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:14:05.02$vc4f8/vb=5,4 2006.140.08:14:05.02#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:14:05.02#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:14:05.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:05.02#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:05.08#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:05.08#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:05.10#ibcon#[27=AT05-04\r\n] 2006.140.08:14:05.13#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:05.13#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:14:05.13#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:14:05.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:05.13#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:05.25#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:05.25#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:05.27#ibcon#[27=USB\r\n] 2006.140.08:14:05.30#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:05.30#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:14:05.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:14:05.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:14:05.30$vc4f8/vblo=6,752.99 2006.140.08:14:05.30#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:14:05.30#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:14:05.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:14:05.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:05.30#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:05.30#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:05.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:14:05.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:05.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:14:05.36#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:14:05.36#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:14:05.36$vc4f8/vb=6,4 2006.140.08:14:05.36#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:14:05.36#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:14:05.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:14:05.36#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:05.42#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:05.42#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:05.44#ibcon#[27=AT06-04\r\n] 2006.140.08:14:05.47#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:05.47#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:14:05.47#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:14:05.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:14:05.47#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:05.59#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:05.59#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:05.61#ibcon#[27=USB\r\n] 2006.140.08:14:05.64#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:05.64#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:14:05.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:14:05.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:14:05.64$vc4f8/vabw=wide 2006.140.08:14:05.64#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.08:14:05.64#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.08:14:05.64#ibcon#ireg 8 cls_cnt 0 2006.140.08:14:05.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:05.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:05.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:05.66#ibcon#[25=BW32\r\n] 2006.140.08:14:05.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:05.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:14:05.69#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:14:05.69#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:14:05.69$vc4f8/vbbw=wide 2006.140.08:14:05.69#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.140.08:14:05.69#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.140.08:14:05.69#ibcon#ireg 8 cls_cnt 0 2006.140.08:14:05.69#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:14:05.76#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:14:05.76#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:14:05.78#ibcon#[27=BW32\r\n] 2006.140.08:14:05.81#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:14:05.81#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.140.08:14:05.81#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:14:05.81#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:14:05.81$4f8m12a/ifd4f 2006.140.08:14:05.81$ifd4f/lo= 2006.140.08:14:05.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:14:05.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:14:05.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:14:05.81$ifd4f/patch= 2006.140.08:14:05.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:14:05.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:14:05.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:14:05.81$4f8m12a/"form=m,16.000,1:2 2006.140.08:14:05.81$4f8m12a/"tpicd 2006.140.08:14:05.81$4f8m12a/echo=off 2006.140.08:14:05.81$4f8m12a/xlog=off 2006.140.08:14:05.81:!2006.140.08:14:30 2006.140.08:14:12.14#trakl#Source acquired 2006.140.08:14:12.14#flagr#flagr/antenna,acquired 2006.140.08:14:30.00:preob 2006.140.08:14:31.14/onsource/TRACKING 2006.140.08:14:31.14:!2006.140.08:14:40 2006.140.08:14:40.00:data_valid=on 2006.140.08:14:40.00:midob 2006.140.08:14:40.14/onsource/TRACKING 2006.140.08:14:40.14/wx/22.38,992.9,100 2006.140.08:14:40.24/cable/+6.5017E-03 2006.140.08:14:41.33/va/01,08,usb,yes,49,52 2006.140.08:14:41.33/va/02,07,usb,yes,50,52 2006.140.08:14:41.33/va/03,06,usb,yes,53,53 2006.140.08:14:41.33/va/04,07,usb,yes,52,55 2006.140.08:14:41.33/va/05,07,usb,yes,53,56 2006.140.08:14:41.33/va/06,06,usb,yes,52,52 2006.140.08:14:41.33/va/07,06,usb,yes,53,53 2006.140.08:14:41.33/va/08,06,usb,yes,56,55 2006.140.08:14:41.56/valo/01,532.99,yes,locked 2006.140.08:14:41.56/valo/02,572.99,yes,locked 2006.140.08:14:41.56/valo/03,672.99,yes,locked 2006.140.08:14:41.56/valo/04,832.99,yes,locked 2006.140.08:14:41.56/valo/05,652.99,yes,locked 2006.140.08:14:41.56/valo/06,772.99,yes,locked 2006.140.08:14:41.56/valo/07,832.99,yes,locked 2006.140.08:14:41.56/valo/08,852.99,yes,locked 2006.140.08:14:42.65/vb/01,04,usb,yes,31,29 2006.140.08:14:42.65/vb/02,04,usb,yes,34,34 2006.140.08:14:42.65/vb/03,04,usb,yes,29,34 2006.140.08:14:42.65/vb/04,04,usb,yes,30,30 2006.140.08:14:42.65/vb/05,04,usb,yes,28,32 2006.140.08:14:42.65/vb/06,04,usb,yes,29,32 2006.140.08:14:42.65/vb/07,04,usb,yes,31,31 2006.140.08:14:42.65/vb/08,04,usb,yes,29,32 2006.140.08:14:42.89/vblo/01,632.99,yes,locked 2006.140.08:14:42.89/vblo/02,640.99,yes,locked 2006.140.08:14:42.89/vblo/03,656.99,yes,locked 2006.140.08:14:42.89/vblo/04,712.99,yes,locked 2006.140.08:14:42.89/vblo/05,744.99,yes,locked 2006.140.08:14:42.89/vblo/06,752.99,yes,locked 2006.140.08:14:42.89/vblo/07,734.99,yes,locked 2006.140.08:14:42.89/vblo/08,744.99,yes,locked 2006.140.08:14:43.04/vabw/8 2006.140.08:14:43.19/vbbw/8 2006.140.08:14:43.28/xfe/off,on,15.0 2006.140.08:14:43.67/ifatt/23,28,28,28 2006.140.08:14:44.11/fmout-gps/S +1.17E-07 2006.140.08:14:44.15:!2006.140.08:15:40 2006.140.08:15:40.00:data_valid=off 2006.140.08:15:40.00:postob 2006.140.08:15:40.07/cable/+6.5034E-03 2006.140.08:15:40.08/wx/22.37,993.0,100 2006.140.08:15:41.11/fmout-gps/S +1.18E-07 2006.140.08:15:41.11:scan_name=140-0816,k06140,60 2006.140.08:15:41.11:source=3c371,180650.68,694928.1,2000.0,cw 2006.140.08:15:41.14#flagr#flagr/antenna,new-source 2006.140.08:15:42.14:checkk5 2006.140.08:15:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:15:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:15:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:15:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:15:44.00/chk_obsdata//k5ts1/T1400814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:15:44.38/chk_obsdata//k5ts2/T1400814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:15:44.75/chk_obsdata//k5ts3/T1400814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:15:45.13/chk_obsdata//k5ts4/T1400814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:15:45.81/k5log//k5ts1_log_newline 2006.140.08:15:46.50/k5log//k5ts2_log_newline 2006.140.08:15:47.19/k5log//k5ts3_log_newline 2006.140.08:15:47.88/k5log//k5ts4_log_newline 2006.140.08:15:47.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:15:47.90:4f8m12a=2 2006.140.08:15:47.90$4f8m12a/echo=on 2006.140.08:15:47.90$4f8m12a/pcalon 2006.140.08:15:47.90$pcalon/"no phase cal control is implemented here 2006.140.08:15:47.90$4f8m12a/"tpicd=stop 2006.140.08:15:47.90$4f8m12a/vc4f8 2006.140.08:15:47.90$vc4f8/valo=1,532.99 2006.140.08:15:47.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:15:47.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:15:47.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:47.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:47.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:47.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:47.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:15:48.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:48.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:48.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:15:48.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:15:48.00$vc4f8/va=1,8 2006.140.08:15:48.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:15:48.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:15:48.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:48.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:48.00#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:48.00#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:48.03#ibcon#[25=AT01-08\r\n] 2006.140.08:15:48.07#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:48.07#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:48.07#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:15:48.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:48.07#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:48.19#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:48.19#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:48.21#ibcon#[25=USB\r\n] 2006.140.08:15:48.24#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:48.24#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:48.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:15:48.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:15:48.24$vc4f8/valo=2,572.99 2006.140.08:15:48.24#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:15:48.24#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:15:48.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:48.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:48.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:48.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:15:48.30#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:48.30#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:48.30#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:15:48.30#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:15:48.30$vc4f8/va=2,7 2006.140.08:15:48.30#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:15:48.30#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:15:48.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:48.30#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:48.36#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:48.36#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:48.38#ibcon#[25=AT02-07\r\n] 2006.140.08:15:48.41#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:48.41#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:48.41#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:15:48.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:48.41#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:48.53#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:48.53#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:48.55#ibcon#[25=USB\r\n] 2006.140.08:15:48.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:48.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:48.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:15:48.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:15:48.60$vc4f8/valo=3,672.99 2006.140.08:15:48.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.08:15:48.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.08:15:48.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:48.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:15:48.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:15:48.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:15:48.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:15:48.63#abcon#<5=/04 1.8 4.1 22.36100 993.0\r\n> 2006.140.08:15:48.65#abcon#{5=INTERFACE CLEAR} 2006.140.08:15:48.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:15:48.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:15:48.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:15:48.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:15:48.67$vc4f8/va=3,6 2006.140.08:15:48.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.08:15:48.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.08:15:48.67#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:48.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:15:48.71#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:15:48.72#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:15:48.72#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:15:48.74#ibcon#[25=AT03-06\r\n] 2006.140.08:15:48.77#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:15:48.77#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:15:48.77#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.08:15:48.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:48.77#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:15:48.89#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:15:48.89#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:15:48.91#ibcon#[25=USB\r\n] 2006.140.08:15:48.94#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:15:48.94#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:15:48.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:15:48.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:15:48.94$vc4f8/valo=4,832.99 2006.140.08:15:48.94#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:15:48.94#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:15:48.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:48.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:48.94#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:48.94#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:48.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:15:49.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:49.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:49.00#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:15:49.00#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:15:49.00$vc4f8/va=4,7 2006.140.08:15:49.00#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:15:49.00#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:15:49.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:49.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:49.06#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:49.06#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:49.08#ibcon#[25=AT04-07\r\n] 2006.140.08:15:49.11#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:49.11#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:49.11#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:15:49.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:49.11#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:49.23#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:49.23#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:49.25#ibcon#[25=USB\r\n] 2006.140.08:15:49.28#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:49.28#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:49.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:15:49.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:15:49.28$vc4f8/valo=5,652.99 2006.140.08:15:49.28#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:15:49.28#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:15:49.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:49.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:49.28#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:49.28#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:49.32#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:15:49.36#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:49.36#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:49.36#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:15:49.36#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:15:49.36$vc4f8/va=5,7 2006.140.08:15:49.36#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:15:49.36#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:15:49.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:49.36#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:49.40#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:49.40#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:49.42#ibcon#[25=AT05-07\r\n] 2006.140.08:15:49.45#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:49.45#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:49.45#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:15:49.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:49.45#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:49.57#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:49.57#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:49.59#ibcon#[25=USB\r\n] 2006.140.08:15:49.62#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:49.62#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:49.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:15:49.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:15:49.62$vc4f8/valo=6,772.99 2006.140.08:15:49.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:15:49.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:15:49.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:49.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:49.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:49.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:49.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:15:49.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:49.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:49.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:15:49.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:15:49.68$vc4f8/va=6,6 2006.140.08:15:49.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:15:49.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:15:49.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:49.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:49.74#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:49.74#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:49.76#ibcon#[25=AT06-06\r\n] 2006.140.08:15:49.79#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:49.79#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:49.79#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:15:49.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:49.79#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:15:49.91#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:15:49.91#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:15:49.93#ibcon#[25=USB\r\n] 2006.140.08:15:49.98#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:15:49.98#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:15:49.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:15:49.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:15:49.98$vc4f8/valo=7,832.99 2006.140.08:15:49.98#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:15:49.98#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:15:49.98#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:49.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:15:49.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:15:49.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:15:50.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:15:50.04#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:15:50.04#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:15:50.04#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:15:50.04#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:15:50.04$vc4f8/va=7,6 2006.140.08:15:50.04#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:15:50.04#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:15:50.04#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:50.04#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:15:50.10#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:15:50.10#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:15:50.12#ibcon#[25=AT07-06\r\n] 2006.140.08:15:50.15#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:15:50.15#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:15:50.15#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:15:50.15#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:50.15#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:15:50.27#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:15:50.27#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:15:50.29#ibcon#[25=USB\r\n] 2006.140.08:15:50.32#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:15:50.32#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:15:50.32#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:15:50.32#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:15:50.32$vc4f8/valo=8,852.99 2006.140.08:15:50.32#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:15:50.32#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:15:50.32#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:50.32#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:15:50.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:15:50.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:15:50.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:15:50.38#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:15:50.38#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:15:50.38#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:15:50.38#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:15:50.38$vc4f8/va=8,6 2006.140.08:15:50.38#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:15:50.38#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:15:50.38#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:50.38#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:15:50.44#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:15:50.44#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:15:50.46#ibcon#[25=AT08-06\r\n] 2006.140.08:15:50.49#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:15:50.49#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:15:50.49#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:15:50.49#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:50.49#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:15:50.61#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:15:50.61#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:15:50.63#ibcon#[25=USB\r\n] 2006.140.08:15:50.68#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:15:50.68#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:15:50.68#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:15:50.68#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:15:50.68$vc4f8/vblo=1,632.99 2006.140.08:15:50.68#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:15:50.68#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:15:50.68#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:50.68#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:50.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:50.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:50.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:15:50.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:50.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:15:50.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:15:50.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:15:50.74$vc4f8/vb=1,4 2006.140.08:15:50.74#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:15:50.74#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:15:50.74#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:50.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:50.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:50.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:50.76#ibcon#[27=AT01-04\r\n] 2006.140.08:15:50.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:50.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:15:50.79#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:15:50.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:50.79#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:50.91#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:50.91#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:50.93#ibcon#[27=USB\r\n] 2006.140.08:15:50.96#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:50.96#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:15:50.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:15:50.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:15:50.96$vc4f8/vblo=2,640.99 2006.140.08:15:50.96#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:15:50.96#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:15:50.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:50.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:50.96#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:50.96#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:50.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:15:51.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:51.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:15:51.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:15:51.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:15:51.02$vc4f8/vb=2,4 2006.140.08:15:51.02#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:15:51.02#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:15:51.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:51.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:51.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:51.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:51.10#ibcon#[27=AT02-04\r\n] 2006.140.08:15:51.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:51.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:15:51.13#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:15:51.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:51.13#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:51.25#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:51.25#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:51.27#ibcon#[27=USB\r\n] 2006.140.08:15:51.30#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:51.30#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:15:51.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:15:51.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:15:51.30$vc4f8/vblo=3,656.99 2006.140.08:15:51.30#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:15:51.30#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:15:51.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:51.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:15:51.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:15:51.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:15:51.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:15:51.36#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:15:51.36#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:15:51.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:15:51.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:15:51.36$vc4f8/vb=3,4 2006.140.08:15:51.36#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.08:15:51.36#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.08:15:51.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:51.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:15:51.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:15:51.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:15:51.44#ibcon#[27=AT03-04\r\n] 2006.140.08:15:51.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:15:51.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:15:51.47#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.08:15:51.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:51.47#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:15:51.59#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:15:51.59#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:15:51.61#ibcon#[27=USB\r\n] 2006.140.08:15:51.64#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:15:51.64#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:15:51.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:15:51.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:15:51.64$vc4f8/vblo=4,712.99 2006.140.08:15:51.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.08:15:51.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.08:15:51.64#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:51.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:15:51.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:15:51.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:15:51.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:15:51.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:15:51.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:15:51.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:15:51.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:15:51.70$vc4f8/vb=4,4 2006.140.08:15:51.70#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.08:15:51.70#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.08:15:51.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:51.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:15:51.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:15:51.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:15:51.78#ibcon#[27=AT04-04\r\n] 2006.140.08:15:51.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:15:51.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:15:51.81#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.08:15:51.81#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:51.81#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:15:51.93#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:15:51.93#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:15:51.95#ibcon#[27=USB\r\n] 2006.140.08:15:51.98#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:15:51.98#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:15:51.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:15:51.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:15:51.98$vc4f8/vblo=5,744.99 2006.140.08:15:51.98#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:15:51.98#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:15:51.98#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:51.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:51.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:51.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:52.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:15:52.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:52.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:15:52.04#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:15:52.04#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:15:52.04$vc4f8/vb=5,4 2006.140.08:15:52.04#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:15:52.04#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:15:52.04#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:52.04#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:52.10#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:52.10#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:52.12#ibcon#[27=AT05-04\r\n] 2006.140.08:15:52.15#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:52.15#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:15:52.15#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:15:52.15#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:52.15#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:52.27#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:52.27#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:52.29#ibcon#[27=USB\r\n] 2006.140.08:15:52.32#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:52.32#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:15:52.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:15:52.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:15:52.32$vc4f8/vblo=6,752.99 2006.140.08:15:52.32#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:15:52.32#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:15:52.32#ibcon#ireg 17 cls_cnt 0 2006.140.08:15:52.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:52.32#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:52.32#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:52.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:15:52.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:52.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:15:52.38#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:15:52.38#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:15:52.38$vc4f8/vb=6,4 2006.140.08:15:52.38#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:15:52.38#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:15:52.38#ibcon#ireg 11 cls_cnt 2 2006.140.08:15:52.38#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:52.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:52.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:52.46#ibcon#[27=AT06-04\r\n] 2006.140.08:15:52.49#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:52.49#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:15:52.49#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:15:52.49#ibcon#ireg 7 cls_cnt 0 2006.140.08:15:52.49#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:52.61#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:52.61#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:52.63#ibcon#[27=USB\r\n] 2006.140.08:15:52.66#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:52.66#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:15:52.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:15:52.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:15:52.66$vc4f8/vabw=wide 2006.140.08:15:52.66#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:15:52.66#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:15:52.66#ibcon#ireg 8 cls_cnt 0 2006.140.08:15:52.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:52.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:52.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:52.68#ibcon#[25=BW32\r\n] 2006.140.08:15:52.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:52.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:15:52.71#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:15:52.71#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:15:52.71$vc4f8/vbbw=wide 2006.140.08:15:52.71#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:15:52.71#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:15:52.71#ibcon#ireg 8 cls_cnt 0 2006.140.08:15:52.71#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:15:52.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:15:52.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:15:52.80#ibcon#[27=BW32\r\n] 2006.140.08:15:52.83#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:15:52.83#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:15:52.83#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:15:52.83#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:15:52.83$4f8m12a/ifd4f 2006.140.08:15:52.83$ifd4f/lo= 2006.140.08:15:52.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:15:52.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:15:52.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:15:52.83$ifd4f/patch= 2006.140.08:15:52.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:15:52.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:15:52.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:15:52.83$4f8m12a/"form=m,16.000,1:2 2006.140.08:15:52.83$4f8m12a/"tpicd 2006.140.08:15:52.83$4f8m12a/echo=off 2006.140.08:15:52.83$4f8m12a/xlog=off 2006.140.08:15:52.83:!2006.140.08:16:20 2006.140.08:16:02.14#trakl#Source acquired 2006.140.08:16:02.14#flagr#flagr/antenna,acquired 2006.140.08:16:20.00:preob 2006.140.08:16:21.14/onsource/TRACKING 2006.140.08:16:21.14:!2006.140.08:16:30 2006.140.08:16:30.00:data_valid=on 2006.140.08:16:30.00:midob 2006.140.08:16:30.14/onsource/TRACKING 2006.140.08:16:30.14/wx/22.35,993.0,100 2006.140.08:16:30.19/cable/+6.5038E-03 2006.140.08:16:31.28/va/01,08,usb,yes,51,54 2006.140.08:16:31.28/va/02,07,usb,yes,52,54 2006.140.08:16:31.28/va/03,06,usb,yes,55,55 2006.140.08:16:31.28/va/04,07,usb,yes,53,57 2006.140.08:16:31.28/va/05,07,usb,yes,54,57 2006.140.08:16:31.28/va/06,06,usb,yes,54,53 2006.140.08:16:31.28/va/07,06,usb,yes,54,54 2006.140.08:16:31.28/va/08,06,usb,yes,57,56 2006.140.08:16:31.51/valo/01,532.99,yes,locked 2006.140.08:16:31.51/valo/02,572.99,yes,locked 2006.140.08:16:31.51/valo/03,672.99,yes,locked 2006.140.08:16:31.51/valo/04,832.99,yes,locked 2006.140.08:16:31.51/valo/05,652.99,yes,locked 2006.140.08:16:31.51/valo/06,772.99,yes,locked 2006.140.08:16:31.51/valo/07,832.99,yes,locked 2006.140.08:16:31.51/valo/08,852.99,yes,locked 2006.140.08:16:32.60/vb/01,04,usb,yes,32,30 2006.140.08:16:32.60/vb/02,04,usb,yes,35,35 2006.140.08:16:32.60/vb/03,04,usb,yes,30,35 2006.140.08:16:32.60/vb/04,04,usb,yes,31,31 2006.140.08:16:32.60/vb/05,04,usb,yes,29,33 2006.140.08:16:32.60/vb/06,04,usb,yes,31,33 2006.140.08:16:32.60/vb/07,04,usb,yes,32,32 2006.140.08:16:32.60/vb/08,04,usb,yes,30,33 2006.140.08:16:32.83/vblo/01,632.99,yes,locked 2006.140.08:16:32.83/vblo/02,640.99,yes,locked 2006.140.08:16:32.83/vblo/03,656.99,yes,locked 2006.140.08:16:32.83/vblo/04,712.99,yes,locked 2006.140.08:16:32.83/vblo/05,744.99,yes,locked 2006.140.08:16:32.83/vblo/06,752.99,yes,locked 2006.140.08:16:32.83/vblo/07,734.99,yes,locked 2006.140.08:16:32.83/vblo/08,744.99,yes,locked 2006.140.08:16:32.98/vabw/8 2006.140.08:16:33.13/vbbw/8 2006.140.08:16:33.22/xfe/off,on,15.0 2006.140.08:16:33.59/ifatt/23,28,28,28 2006.140.08:16:34.11/fmout-gps/S +1.18E-07 2006.140.08:16:34.18:!2006.140.08:17:30 2006.140.08:17:30.00:data_valid=off 2006.140.08:17:30.00:postob 2006.140.08:17:30.07/cable/+6.5012E-03 2006.140.08:17:30.07/wx/22.34,993.0,100 2006.140.08:17:31.11/fmout-gps/S +1.17E-07 2006.140.08:17:31.11:scan_name=140-0818,k06140,60 2006.140.08:17:31.11:source=1739+522,174036.98,521143.4,2000.0,cw 2006.140.08:17:31.14#flagr#flagr/antenna,new-source 2006.140.08:17:32.14:checkk5 2006.140.08:17:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:17:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:17:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:17:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:17:34.00/chk_obsdata//k5ts1/T1400816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:17:34.38/chk_obsdata//k5ts2/T1400816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:17:34.75/chk_obsdata//k5ts3/T1400816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:17:35.12/chk_obsdata//k5ts4/T1400816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:17:35.81/k5log//k5ts1_log_newline 2006.140.08:17:36.50/k5log//k5ts2_log_newline 2006.140.08:17:37.19/k5log//k5ts3_log_newline 2006.140.08:17:37.88/k5log//k5ts4_log_newline 2006.140.08:17:37.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:17:37.90:4f8m12a=2 2006.140.08:17:37.90$4f8m12a/echo=on 2006.140.08:17:37.90$4f8m12a/pcalon 2006.140.08:17:37.90$pcalon/"no phase cal control is implemented here 2006.140.08:17:37.90$4f8m12a/"tpicd=stop 2006.140.08:17:37.90$4f8m12a/vc4f8 2006.140.08:17:37.90$vc4f8/valo=1,532.99 2006.140.08:17:37.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:17:37.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:17:37.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:37.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:37.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:37.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:37.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:17:38.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:38.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:38.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:17:38.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:17:38.00$vc4f8/va=1,8 2006.140.08:17:38.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.08:17:38.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.08:17:38.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:38.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:38.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:38.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:38.03#ibcon#[25=AT01-08\r\n] 2006.140.08:17:38.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:38.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:38.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.08:17:38.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:38.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:38.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:38.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:38.21#ibcon#[25=USB\r\n] 2006.140.08:17:38.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:38.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:38.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:17:38.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:17:38.24$vc4f8/valo=2,572.99 2006.140.08:17:38.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:17:38.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:17:38.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:38.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:38.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:38.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:17:38.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:38.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:38.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:17:38.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:17:38.30$vc4f8/va=2,7 2006.140.08:17:38.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.08:17:38.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.08:17:38.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:38.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:38.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:38.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:38.38#ibcon#[25=AT02-07\r\n] 2006.140.08:17:38.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:38.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:38.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.08:17:38.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:38.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:38.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:38.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:38.55#ibcon#[25=USB\r\n] 2006.140.08:17:38.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:38.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:38.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:17:38.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:17:38.58$vc4f8/valo=3,672.99 2006.140.08:17:38.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:17:38.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:17:38.58#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:38.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:38.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:38.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:38.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:17:38.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:38.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:38.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:17:38.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:17:38.66$vc4f8/va=3,6 2006.140.08:17:38.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.08:17:38.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.08:17:38.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:38.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:38.70#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:38.70#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:38.72#ibcon#[25=AT03-06\r\n] 2006.140.08:17:38.75#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:38.75#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:38.75#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.08:17:38.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:38.75#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:38.87#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:38.87#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:38.89#ibcon#[25=USB\r\n] 2006.140.08:17:38.92#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:38.92#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:38.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:17:38.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:17:38.92$vc4f8/valo=4,832.99 2006.140.08:17:38.92#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.08:17:38.92#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.08:17:38.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:38.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:38.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:38.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:38.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:17:38.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:38.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:38.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:17:38.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:17:38.98$vc4f8/va=4,7 2006.140.08:17:38.98#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.08:17:38.98#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.08:17:38.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:38.98#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:39.04#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:39.04#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:39.06#ibcon#[25=AT04-07\r\n] 2006.140.08:17:39.09#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:39.09#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:39.09#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.08:17:39.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:39.09#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:39.21#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:39.21#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:39.23#ibcon#[25=USB\r\n] 2006.140.08:17:39.26#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:39.26#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:39.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:17:39.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:17:39.26$vc4f8/valo=5,652.99 2006.140.08:17:39.26#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.08:17:39.26#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.08:17:39.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:39.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:39.26#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:39.26#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:39.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:17:39.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:39.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:39.32#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:17:39.32#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:17:39.32$vc4f8/va=5,7 2006.140.08:17:39.32#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.08:17:39.32#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.08:17:39.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:39.32#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:39.38#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:39.38#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:39.40#ibcon#[25=AT05-07\r\n] 2006.140.08:17:39.43#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:39.43#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:39.43#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.08:17:39.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:39.43#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:39.55#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:39.55#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:39.57#ibcon#[25=USB\r\n] 2006.140.08:17:39.60#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:39.60#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:39.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:17:39.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:17:39.60$vc4f8/valo=6,772.99 2006.140.08:17:39.60#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.08:17:39.60#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.08:17:39.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:39.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:39.60#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:39.60#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:39.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:17:39.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:39.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:39.66#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:17:39.66#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:17:39.66$vc4f8/va=6,6 2006.140.08:17:39.66#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.08:17:39.66#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.08:17:39.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:39.66#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:39.72#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:39.72#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:39.74#ibcon#[25=AT06-06\r\n] 2006.140.08:17:39.77#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:39.77#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:39.77#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.08:17:39.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:39.77#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:39.89#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:39.89#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:39.91#ibcon#[25=USB\r\n] 2006.140.08:17:39.94#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:39.94#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:39.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:17:39.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:17:39.94$vc4f8/valo=7,832.99 2006.140.08:17:39.94#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:17:39.94#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:17:39.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:39.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:39.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:39.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:39.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:17:40.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:40.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:40.00#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:17:40.00#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:17:40.00$vc4f8/va=7,6 2006.140.08:17:40.00#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.140.08:17:40.00#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.140.08:17:40.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:40.00#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:40.06#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:40.06#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:40.08#ibcon#[25=AT07-06\r\n] 2006.140.08:17:40.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:40.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:40.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.140.08:17:40.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:40.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:17:40.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:17:40.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:17:40.25#ibcon#[25=USB\r\n] 2006.140.08:17:40.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:17:40.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.140.08:17:40.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:17:40.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:17:40.28$vc4f8/valo=8,852.99 2006.140.08:17:40.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:17:40.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:17:40.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:40.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:17:40.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:17:40.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:17:40.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:17:40.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:17:40.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:17:40.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:17:40.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:17:40.34$vc4f8/va=8,6 2006.140.08:17:40.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.140.08:17:40.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.140.08:17:40.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:40.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:17:40.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:17:40.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:17:40.42#ibcon#[25=AT08-06\r\n] 2006.140.08:17:40.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:17:40.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.140.08:17:40.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.140.08:17:40.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:40.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:17:40.51#abcon#<5=/03 1.8 3.3 22.33100 993.0\r\n> 2006.140.08:17:40.53#abcon#{5=INTERFACE CLEAR} 2006.140.08:17:40.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:17:40.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:17:40.59#ibcon#[25=USB\r\n] 2006.140.08:17:40.59#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:17:40.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:17:40.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.140.08:17:40.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:17:40.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:17:40.62$vc4f8/vblo=1,632.99 2006.140.08:17:40.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.140.08:17:40.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.140.08:17:40.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:40.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:40.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:40.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:40.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:17:40.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:40.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.140.08:17:40.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:17:40.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:17:40.68$vc4f8/vb=1,4 2006.140.08:17:40.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.140.08:17:40.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.140.08:17:40.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:40.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:40.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:40.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:40.70#ibcon#[27=AT01-04\r\n] 2006.140.08:17:40.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:40.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.140.08:17:40.73#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.140.08:17:40.73#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:40.73#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:40.85#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:40.85#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:40.87#ibcon#[27=USB\r\n] 2006.140.08:17:40.90#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:40.90#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.140.08:17:40.90#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:17:40.90#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:17:40.90$vc4f8/vblo=2,640.99 2006.140.08:17:40.90#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:17:40.90#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:17:40.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:40.90#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:40.90#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:40.90#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:40.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:17:40.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:40.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:17:40.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:17:40.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:17:40.96$vc4f8/vb=2,4 2006.140.08:17:40.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.140.08:17:40.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.140.08:17:40.96#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:40.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:41.02#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:41.02#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:41.04#ibcon#[27=AT02-04\r\n] 2006.140.08:17:41.07#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:41.07#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.140.08:17:41.07#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.140.08:17:41.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:41.07#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:41.19#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:41.19#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:41.21#ibcon#[27=USB\r\n] 2006.140.08:17:41.24#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:41.24#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.140.08:17:41.24#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:17:41.24#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:17:41.24$vc4f8/vblo=3,656.99 2006.140.08:17:41.24#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.140.08:17:41.24#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.140.08:17:41.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:41.24#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:41.24#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:41.24#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:41.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:17:41.30#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:41.30#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.140.08:17:41.30#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:17:41.30#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:17:41.30$vc4f8/vb=3,4 2006.140.08:17:41.30#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.140.08:17:41.30#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.140.08:17:41.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:41.30#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:41.36#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:41.36#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:41.38#ibcon#[27=AT03-04\r\n] 2006.140.08:17:41.41#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:41.41#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.140.08:17:41.41#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.140.08:17:41.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:41.41#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:41.53#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:41.53#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:41.55#ibcon#[27=USB\r\n] 2006.140.08:17:41.58#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:41.58#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.140.08:17:41.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:17:41.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:17:41.58$vc4f8/vblo=4,712.99 2006.140.08:17:41.58#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.140.08:17:41.58#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.140.08:17:41.58#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:41.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:41.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:41.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:41.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:17:41.64#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:41.64#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.140.08:17:41.64#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:17:41.64#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:17:41.64$vc4f8/vb=4,4 2006.140.08:17:41.64#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.140.08:17:41.64#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.140.08:17:41.64#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:41.64#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:41.70#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:41.70#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:41.72#ibcon#[27=AT04-04\r\n] 2006.140.08:17:41.75#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:41.75#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.140.08:17:41.75#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.140.08:17:41.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:41.75#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:41.87#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:41.87#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:41.89#ibcon#[27=USB\r\n] 2006.140.08:17:41.92#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:41.92#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.140.08:17:41.92#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:17:41.92#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:17:41.92$vc4f8/vblo=5,744.99 2006.140.08:17:41.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.140.08:17:41.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.140.08:17:41.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:41.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:41.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:41.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:41.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:17:41.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:41.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.140.08:17:41.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:17:41.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:17:41.98$vc4f8/vb=5,4 2006.140.08:17:41.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.140.08:17:41.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.140.08:17:41.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:41.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:42.04#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:42.04#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:42.06#ibcon#[27=AT05-04\r\n] 2006.140.08:17:42.09#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:42.09#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.140.08:17:42.09#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.140.08:17:42.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:42.09#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:42.21#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:42.21#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:42.23#ibcon#[27=USB\r\n] 2006.140.08:17:42.26#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:42.26#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.140.08:17:42.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:17:42.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:17:42.26$vc4f8/vblo=6,752.99 2006.140.08:17:42.26#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.140.08:17:42.26#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.140.08:17:42.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:17:42.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:42.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:42.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:42.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:17:42.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:42.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.140.08:17:42.32#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:17:42.32#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:17:42.32$vc4f8/vb=6,4 2006.140.08:17:42.32#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.140.08:17:42.32#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.140.08:17:42.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:17:42.32#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:42.38#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:42.38#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:42.40#ibcon#[27=AT06-04\r\n] 2006.140.08:17:42.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:42.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.140.08:17:42.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.140.08:17:42.44#ibcon#ireg 7 cls_cnt 0 2006.140.08:17:42.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:42.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:42.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:42.58#ibcon#[27=USB\r\n] 2006.140.08:17:42.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:42.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.140.08:17:42.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:17:42.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:17:42.61$vc4f8/vabw=wide 2006.140.08:17:42.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.140.08:17:42.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.140.08:17:42.61#ibcon#ireg 8 cls_cnt 0 2006.140.08:17:42.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:42.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:42.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:42.63#ibcon#[25=BW32\r\n] 2006.140.08:17:42.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:42.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.140.08:17:42.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:17:42.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:17:42.66$vc4f8/vbbw=wide 2006.140.08:17:42.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:17:42.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:17:42.66#ibcon#ireg 8 cls_cnt 0 2006.140.08:17:42.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:17:42.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:17:42.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:17:42.75#ibcon#[27=BW32\r\n] 2006.140.08:17:42.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:17:42.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:17:42.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:17:42.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:17:42.78$4f8m12a/ifd4f 2006.140.08:17:42.78$ifd4f/lo= 2006.140.08:17:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:17:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:17:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:17:42.78$ifd4f/patch= 2006.140.08:17:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:17:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:17:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:17:42.78$4f8m12a/"form=m,16.000,1:2 2006.140.08:17:42.78$4f8m12a/"tpicd 2006.140.08:17:42.78$4f8m12a/echo=off 2006.140.08:17:42.78$4f8m12a/xlog=off 2006.140.08:17:42.78:!2006.140.08:18:10 2006.140.08:17:48.14#trakl#Source acquired 2006.140.08:17:49.14#flagr#flagr/antenna,acquired 2006.140.08:18:10.00:preob 2006.140.08:18:11.14/onsource/TRACKING 2006.140.08:18:11.14:!2006.140.08:18:20 2006.140.08:18:20.01:data_valid=on 2006.140.08:18:20.01:midob 2006.140.08:18:21.14/onsource/TRACKING 2006.140.08:18:21.14/wx/22.32,993.1,100 2006.140.08:18:21.26/cable/+6.5050E-03 2006.140.08:18:22.35/va/01,08,usb,yes,64,67 2006.140.08:18:22.35/va/02,07,usb,yes,65,67 2006.140.08:18:22.35/va/03,06,usb,yes,68,69 2006.140.08:18:22.35/va/04,07,usb,yes,66,71 2006.140.08:18:22.35/va/05,07,usb,yes,68,73 2006.140.08:18:22.35/va/06,06,usb,yes,68,68 2006.140.08:18:22.35/va/07,06,usb,yes,69,68 2006.140.08:18:22.35/va/08,06,usb,yes,73,71 2006.140.08:18:22.58/valo/01,532.99,yes,locked 2006.140.08:18:22.58/valo/02,572.99,yes,locked 2006.140.08:18:22.58/valo/03,672.99,yes,locked 2006.140.08:18:22.58/valo/04,832.99,yes,locked 2006.140.08:18:22.58/valo/05,652.99,yes,locked 2006.140.08:18:22.58/valo/06,772.99,yes,locked 2006.140.08:18:22.58/valo/07,832.99,yes,locked 2006.140.08:18:22.58/valo/08,852.99,yes,locked 2006.140.08:18:23.67/vb/01,04,usb,yes,35,33 2006.140.08:18:23.67/vb/02,04,usb,yes,37,38 2006.140.08:18:23.67/vb/03,04,usb,yes,33,37 2006.140.08:18:23.67/vb/04,04,usb,yes,34,34 2006.140.08:18:23.67/vb/05,04,usb,yes,32,37 2006.140.08:18:23.67/vb/06,04,usb,yes,33,37 2006.140.08:18:23.67/vb/07,04,usb,yes,36,35 2006.140.08:18:23.67/vb/08,04,usb,yes,33,37 2006.140.08:18:23.91/vblo/01,632.99,yes,locked 2006.140.08:18:23.91/vblo/02,640.99,yes,locked 2006.140.08:18:23.91/vblo/03,656.99,yes,locked 2006.140.08:18:23.91/vblo/04,712.99,yes,locked 2006.140.08:18:23.91/vblo/05,744.99,yes,locked 2006.140.08:18:23.91/vblo/06,752.99,yes,locked 2006.140.08:18:23.91/vblo/07,734.99,yes,locked 2006.140.08:18:23.91/vblo/08,744.99,yes,locked 2006.140.08:18:24.06/vabw/8 2006.140.08:18:24.21/vbbw/8 2006.140.08:18:24.32/xfe/off,on,15.5 2006.140.08:18:24.72/ifatt/23,28,28,28 2006.140.08:18:25.10/fmout-gps/S +1.17E-07 2006.140.08:18:25.17:!2006.140.08:19:20 2006.140.08:19:20.00:data_valid=off 2006.140.08:19:20.00:postob 2006.140.08:19:20.11/cable/+6.5064E-03 2006.140.08:19:20.11/wx/22.30,993.0,100 2006.140.08:19:21.10/fmout-gps/S +1.17E-07 2006.140.08:19:21.10:scan_name=140-0821,k06140,60 2006.140.08:19:21.10:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.140.08:19:22.13#flagr#flagr/antenna,new-source 2006.140.08:19:22.13:checkk5 2006.140.08:19:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:19:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:19:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:19:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:19:24.01/chk_obsdata//k5ts1/T1400818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:19:24.38/chk_obsdata//k5ts2/T1400818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:19:24.75/chk_obsdata//k5ts3/T1400818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:19:25.12/chk_obsdata//k5ts4/T1400818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:19:25.81/k5log//k5ts1_log_newline 2006.140.08:19:26.50/k5log//k5ts2_log_newline 2006.140.08:19:27.19/k5log//k5ts3_log_newline 2006.140.08:19:27.88/k5log//k5ts4_log_newline 2006.140.08:19:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:19:27.90:4f8m12a=3 2006.140.08:19:27.90$4f8m12a/echo=on 2006.140.08:19:27.90$4f8m12a/pcalon 2006.140.08:19:27.90$pcalon/"no phase cal control is implemented here 2006.140.08:19:27.90$4f8m12a/"tpicd=stop 2006.140.08:19:27.90$4f8m12a/vc4f8 2006.140.08:19:27.90$vc4f8/valo=1,532.99 2006.140.08:19:27.91#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:19:27.91#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:19:27.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:27.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:27.91#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:27.91#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:19:28.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:28.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:28.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:19:28.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:19:28.00$vc4f8/va=1,8 2006.140.08:19:28.00#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.08:19:28.00#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.08:19:28.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:28.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:28.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:28.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:28.03#ibcon#[25=AT01-08\r\n] 2006.140.08:19:28.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:28.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:28.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.08:19:28.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:28.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:28.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:28.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:28.21#ibcon#[25=USB\r\n] 2006.140.08:19:28.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:28.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:28.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:19:28.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:19:28.24$vc4f8/valo=2,572.99 2006.140.08:19:28.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.08:19:28.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.08:19:28.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:28.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:28.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:28.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:28.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:19:28.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:28.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:28.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:19:28.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:19:28.30$vc4f8/va=2,7 2006.140.08:19:28.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.08:19:28.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.08:19:28.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:28.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:28.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:28.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:28.38#ibcon#[25=AT02-07\r\n] 2006.140.08:19:28.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:28.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:28.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.08:19:28.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:28.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:28.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:28.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:28.55#ibcon#[25=USB\r\n] 2006.140.08:19:28.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:28.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:28.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:19:28.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:19:28.60$vc4f8/valo=3,672.99 2006.140.08:19:28.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:19:28.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:19:28.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:28.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:28.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:28.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:28.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:19:28.67#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:28.67#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:28.67#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:19:28.67#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:19:28.67$vc4f8/va=3,6 2006.140.08:19:28.67#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.08:19:28.67#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.08:19:28.67#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:28.67#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:28.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:28.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:28.74#ibcon#[25=AT03-06\r\n] 2006.140.08:19:28.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:28.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:28.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.08:19:28.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:28.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:28.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:28.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:28.91#ibcon#[25=USB\r\n] 2006.140.08:19:28.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:28.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:28.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:19:28.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:19:28.94$vc4f8/valo=4,832.99 2006.140.08:19:28.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:19:28.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:19:28.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:28.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:28.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:28.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:19:29.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:29.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:29.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:19:29.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:19:29.00$vc4f8/va=4,7 2006.140.08:19:29.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.08:19:29.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.08:19:29.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:29.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:29.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:29.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:29.08#ibcon#[25=AT04-07\r\n] 2006.140.08:19:29.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:29.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:29.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.08:19:29.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:29.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:29.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:29.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:29.25#ibcon#[25=USB\r\n] 2006.140.08:19:29.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:29.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:29.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:19:29.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:19:29.28$vc4f8/valo=5,652.99 2006.140.08:19:29.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:19:29.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:19:29.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:29.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:29.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:29.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:19:29.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:29.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:29.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:19:29.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:19:29.34$vc4f8/va=5,7 2006.140.08:19:29.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.08:19:29.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.08:19:29.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:29.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:29.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:29.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:29.42#ibcon#[25=AT05-07\r\n] 2006.140.08:19:29.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:29.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:29.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.08:19:29.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:29.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:29.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:29.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:29.59#ibcon#[25=USB\r\n] 2006.140.08:19:29.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:29.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:29.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:19:29.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:19:29.62$vc4f8/valo=6,772.99 2006.140.08:19:29.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.140.08:19:29.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.140.08:19:29.62#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:29.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:19:29.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:19:29.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:19:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:19:29.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:19:29.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.140.08:19:29.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:19:29.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:19:29.68$vc4f8/va=6,6 2006.140.08:19:29.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.140.08:19:29.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.140.08:19:29.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:29.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:19:29.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:19:29.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:19:29.76#ibcon#[25=AT06-06\r\n] 2006.140.08:19:29.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:19:29.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.140.08:19:29.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.140.08:19:29.79#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:29.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:19:29.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:19:29.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:19:29.93#ibcon#[25=USB\r\n] 2006.140.08:19:29.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:19:29.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.140.08:19:29.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:19:29.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:19:29.96$vc4f8/valo=7,832.99 2006.140.08:19:29.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.08:19:29.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.08:19:29.96#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:29.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:29.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:29.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:19:30.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:30.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:30.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:19:30.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:19:30.02$vc4f8/va=7,6 2006.140.08:19:30.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.140.08:19:30.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.140.08:19:30.02#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:30.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:30.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:30.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:30.10#ibcon#[25=AT07-06\r\n] 2006.140.08:19:30.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:30.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:30.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.140.08:19:30.13#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:30.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:19:30.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:19:30.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:19:30.27#ibcon#[25=USB\r\n] 2006.140.08:19:30.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:19:30.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.140.08:19:30.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:19:30.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:19:30.30$vc4f8/valo=8,852.99 2006.140.08:19:30.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.140.08:19:30.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.140.08:19:30.30#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:30.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:19:30.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:19:30.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:19:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:19:30.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:19:30.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.140.08:19:30.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:19:30.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:19:30.36$vc4f8/va=8,6 2006.140.08:19:30.36#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.140.08:19:30.36#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.140.08:19:30.36#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:30.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:19:30.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:19:30.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:19:30.44#ibcon#[25=AT08-06\r\n] 2006.140.08:19:30.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:19:30.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.140.08:19:30.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.140.08:19:30.47#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:30.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:19:30.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:19:30.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:19:30.61#ibcon#[25=USB\r\n] 2006.140.08:19:30.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:19:30.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.140.08:19:30.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:19:30.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:19:30.64$vc4f8/vblo=1,632.99 2006.140.08:19:30.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.140.08:19:30.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.140.08:19:30.64#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:30.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:19:30.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:19:30.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:19:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:19:30.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:19:30.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.140.08:19:30.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:19:30.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:19:30.70$vc4f8/vb=1,4 2006.140.08:19:30.70#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.140.08:19:30.70#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.140.08:19:30.70#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:30.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:19:30.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:19:30.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:19:30.72#ibcon#[27=AT01-04\r\n] 2006.140.08:19:30.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:19:30.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.140.08:19:30.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.140.08:19:30.75#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:30.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:19:30.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:19:30.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:19:30.89#ibcon#[27=USB\r\n] 2006.140.08:19:30.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:19:30.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.140.08:19:30.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:19:30.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:19:30.92$vc4f8/vblo=2,640.99 2006.140.08:19:30.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.140.08:19:30.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.140.08:19:30.92#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:30.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:30.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:30.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:19:30.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:30.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.140.08:19:30.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:19:30.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:19:30.98$vc4f8/vb=2,4 2006.140.08:19:30.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.140.08:19:30.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.140.08:19:30.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:30.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:31.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:31.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:31.06#ibcon#[27=AT02-04\r\n] 2006.140.08:19:31.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:31.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.140.08:19:31.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.140.08:19:31.09#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:31.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:31.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:31.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:31.23#ibcon#[27=USB\r\n] 2006.140.08:19:31.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:31.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.140.08:19:31.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:19:31.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:19:31.26$vc4f8/vblo=3,656.99 2006.140.08:19:31.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.140.08:19:31.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.140.08:19:31.26#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:31.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:31.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:31.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:19:31.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:31.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.140.08:19:31.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:19:31.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:19:31.32$vc4f8/vb=3,4 2006.140.08:19:31.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.140.08:19:31.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.140.08:19:31.32#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:31.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:31.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:31.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:31.40#ibcon#[27=AT03-04\r\n] 2006.140.08:19:31.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:31.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.140.08:19:31.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.140.08:19:31.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:31.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:31.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:31.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:31.57#ibcon#[27=USB\r\n] 2006.140.08:19:31.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:31.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.140.08:19:31.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:19:31.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:19:31.60$vc4f8/vblo=4,712.99 2006.140.08:19:31.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:19:31.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:19:31.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:31.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:31.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:31.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:31.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:19:31.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:31.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:19:31.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:19:31.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:19:31.68$vc4f8/vb=4,4 2006.140.08:19:31.68#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.140.08:19:31.68#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.140.08:19:31.68#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:31.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:31.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:31.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:31.74#ibcon#[27=AT04-04\r\n] 2006.140.08:19:31.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:31.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.140.08:19:31.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.140.08:19:31.77#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:31.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:31.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:31.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:31.91#ibcon#[27=USB\r\n] 2006.140.08:19:31.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:31.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.140.08:19:31.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:19:31.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:19:31.94$vc4f8/vblo=5,744.99 2006.140.08:19:31.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.140.08:19:31.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.140.08:19:31.94#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:31.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:31.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:31.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:19:32.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:32.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.140.08:19:32.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:19:32.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:19:32.00$vc4f8/vb=5,4 2006.140.08:19:32.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.140.08:19:32.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.140.08:19:32.00#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:32.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:32.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:32.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:32.08#ibcon#[27=AT05-04\r\n] 2006.140.08:19:32.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:32.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.140.08:19:32.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.140.08:19:32.11#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:32.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:32.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:32.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:32.25#ibcon#[27=USB\r\n] 2006.140.08:19:32.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:32.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.140.08:19:32.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:19:32.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:19:32.28$vc4f8/vblo=6,752.99 2006.140.08:19:32.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.140.08:19:32.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.140.08:19:32.28#ibcon#ireg 17 cls_cnt 0 2006.140.08:19:32.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:32.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:32.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:19:32.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:32.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.140.08:19:32.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:19:32.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:19:32.34$vc4f8/vb=6,4 2006.140.08:19:32.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.140.08:19:32.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.140.08:19:32.34#ibcon#ireg 11 cls_cnt 2 2006.140.08:19:32.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:32.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:32.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:32.42#ibcon#[27=AT06-04\r\n] 2006.140.08:19:32.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:32.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.140.08:19:32.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.140.08:19:32.45#ibcon#ireg 7 cls_cnt 0 2006.140.08:19:32.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:32.50#abcon#<5=/03 1.6 3.1 22.30100 993.1\r\n> 2006.140.08:19:32.52#abcon#{5=INTERFACE CLEAR} 2006.140.08:19:32.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:32.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:32.58#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:19:32.59#ibcon#[27=USB\r\n] 2006.140.08:19:32.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:32.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.140.08:19:32.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:19:32.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:19:32.62$vc4f8/vabw=wide 2006.140.08:19:32.62#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.140.08:19:32.62#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.140.08:19:32.62#ibcon#ireg 8 cls_cnt 0 2006.140.08:19:32.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:32.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:32.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:32.64#ibcon#[25=BW32\r\n] 2006.140.08:19:32.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:32.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.140.08:19:32.67#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:19:32.67#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:19:32.67$vc4f8/vbbw=wide 2006.140.08:19:32.67#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:19:32.67#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:19:32.67#ibcon#ireg 8 cls_cnt 0 2006.140.08:19:32.67#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:19:32.74#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:19:32.74#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:19:32.76#ibcon#[27=BW32\r\n] 2006.140.08:19:32.79#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:19:32.79#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:19:32.79#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:19:32.79#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:19:32.79$4f8m12a/ifd4f 2006.140.08:19:32.79$ifd4f/lo= 2006.140.08:19:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:19:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:19:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:19:32.79$ifd4f/patch= 2006.140.08:19:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:19:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:19:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:19:32.79$4f8m12a/"form=m,16.000,1:2 2006.140.08:19:32.79$4f8m12a/"tpicd 2006.140.08:19:32.79$4f8m12a/echo=off 2006.140.08:19:32.79$4f8m12a/xlog=off 2006.140.08:19:32.79:!2006.140.08:21:00 2006.140.08:20:11.13#trakl#Source acquired 2006.140.08:20:12.13#flagr#flagr/antenna,acquired 2006.140.08:21:00.00:preob 2006.140.08:21:01.14/onsource/TRACKING 2006.140.08:21:01.14:!2006.140.08:21:10 2006.140.08:21:10.00:data_valid=on 2006.140.08:21:10.00:midob 2006.140.08:21:10.14/onsource/TRACKING 2006.140.08:21:10.14/wx/22.27,993.1,100 2006.140.08:21:10.36/cable/+6.5054E-03 2006.140.08:21:11.45/va/01,08,usb,yes,45,48 2006.140.08:21:11.45/va/02,07,usb,yes,46,48 2006.140.08:21:11.45/va/03,06,usb,yes,49,49 2006.140.08:21:11.45/va/04,07,usb,yes,47,50 2006.140.08:21:11.45/va/05,07,usb,yes,48,51 2006.140.08:21:11.45/va/06,06,usb,yes,47,47 2006.140.08:21:11.45/va/07,06,usb,yes,47,47 2006.140.08:21:11.45/va/08,06,usb,yes,51,50 2006.140.08:21:11.68/valo/01,532.99,yes,locked 2006.140.08:21:11.68/valo/02,572.99,yes,locked 2006.140.08:21:11.68/valo/03,672.99,yes,locked 2006.140.08:21:11.68/valo/04,832.99,yes,locked 2006.140.08:21:11.68/valo/05,652.99,yes,locked 2006.140.08:21:11.68/valo/06,772.99,yes,locked 2006.140.08:21:11.68/valo/07,832.99,yes,locked 2006.140.08:21:11.68/valo/08,852.99,yes,locked 2006.140.08:21:12.77/vb/01,04,usb,yes,31,29 2006.140.08:21:12.77/vb/02,04,usb,yes,32,34 2006.140.08:21:12.77/vb/03,04,usb,yes,29,32 2006.140.08:21:12.77/vb/04,04,usb,yes,30,30 2006.140.08:21:12.77/vb/05,04,usb,yes,28,32 2006.140.08:21:12.77/vb/06,04,usb,yes,29,32 2006.140.08:21:12.77/vb/07,04,usb,yes,31,31 2006.140.08:21:12.77/vb/08,04,usb,yes,29,32 2006.140.08:21:13.00/vblo/01,632.99,yes,locked 2006.140.08:21:13.00/vblo/02,640.99,yes,locked 2006.140.08:21:13.00/vblo/03,656.99,yes,locked 2006.140.08:21:13.00/vblo/04,712.99,yes,locked 2006.140.08:21:13.00/vblo/05,744.99,yes,locked 2006.140.08:21:13.00/vblo/06,752.99,yes,locked 2006.140.08:21:13.00/vblo/07,734.99,yes,locked 2006.140.08:21:13.00/vblo/08,744.99,yes,locked 2006.140.08:21:13.15/vabw/8 2006.140.08:21:13.30/vbbw/8 2006.140.08:21:13.39/xfe/off,on,14.5 2006.140.08:21:13.76/ifatt/23,28,28,28 2006.140.08:21:14.10/fmout-gps/S +1.16E-07 2006.140.08:21:14.17:!2006.140.08:22:10 2006.140.08:22:10.00:data_valid=off 2006.140.08:22:10.00:postob 2006.140.08:22:10.10/cable/+6.5053E-03 2006.140.08:22:10.10/wx/22.25,993.0,100 2006.140.08:22:11.10/fmout-gps/S +1.17E-07 2006.140.08:22:11.10:scan_name=140-0824,k06140,60 2006.140.08:22:11.10:source=1357+769,135755.37,764321.1,2000.0,cw 2006.140.08:22:11.14#flagr#flagr/antenna,new-source 2006.140.08:22:12.14:checkk5 2006.140.08:22:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:22:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:22:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:22:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:22:14.00/chk_obsdata//k5ts1/T1400821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:22:14.37/chk_obsdata//k5ts2/T1400821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:22:14.73/chk_obsdata//k5ts3/T1400821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:22:15.10/chk_obsdata//k5ts4/T1400821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:22:15.80/k5log//k5ts1_log_newline 2006.140.08:22:16.49/k5log//k5ts2_log_newline 2006.140.08:22:17.18/k5log//k5ts3_log_newline 2006.140.08:22:17.86/k5log//k5ts4_log_newline 2006.140.08:22:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:22:17.88:4f8m12a=3 2006.140.08:22:17.88$4f8m12a/echo=on 2006.140.08:22:17.88$4f8m12a/pcalon 2006.140.08:22:17.88$pcalon/"no phase cal control is implemented here 2006.140.08:22:17.89$4f8m12a/"tpicd=stop 2006.140.08:22:17.89$4f8m12a/vc4f8 2006.140.08:22:17.89$vc4f8/valo=1,532.99 2006.140.08:22:17.89#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:22:17.89#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:22:17.89#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:17.89#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:17.89#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:17.89#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:22:17.98#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:17.98#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:17.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:22:17.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:22:17.98$vc4f8/va=1,8 2006.140.08:22:17.98#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:22:17.98#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:22:17.98#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:17.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:17.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:17.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:18.01#ibcon#[25=AT01-08\r\n] 2006.140.08:22:18.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:18.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:18.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:22:18.04#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:18.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:18.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:18.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:18.18#ibcon#[25=USB\r\n] 2006.140.08:22:18.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:18.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:18.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:22:18.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:22:18.21$vc4f8/valo=2,572.99 2006.140.08:22:18.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:22:18.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:22:18.21#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:18.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:18.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:18.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:22:18.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:18.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:18.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:22:18.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:22:18.27$vc4f8/va=2,7 2006.140.08:22:18.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:22:18.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:22:18.27#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:18.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:18.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:18.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:18.35#ibcon#[25=AT02-07\r\n] 2006.140.08:22:18.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:18.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:18.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:22:18.38#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:18.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:18.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:18.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:18.52#ibcon#[25=USB\r\n] 2006.140.08:22:18.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:18.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:18.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:22:18.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:22:18.55$vc4f8/valo=3,672.99 2006.140.08:22:18.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:22:18.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:22:18.55#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:18.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:18.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:18.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:22:18.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:18.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:18.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:22:18.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:22:18.63$vc4f8/va=3,6 2006.140.08:22:18.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:22:18.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:22:18.63#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:18.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:18.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:18.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:18.69#ibcon#[25=AT03-06\r\n] 2006.140.08:22:18.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:18.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:18.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:22:18.72#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:18.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:18.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:18.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:18.86#ibcon#[25=USB\r\n] 2006.140.08:22:18.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:18.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:18.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:22:18.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:22:18.89$vc4f8/valo=4,832.99 2006.140.08:22:18.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.08:22:18.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.08:22:18.89#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:18.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:18.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:18.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:22:18.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:18.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:18.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:22:18.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:22:18.95$vc4f8/va=4,7 2006.140.08:22:18.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.08:22:18.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.08:22:18.95#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:18.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:19.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:19.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:19.03#ibcon#[25=AT04-07\r\n] 2006.140.08:22:19.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:19.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:19.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.08:22:19.06#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:19.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:19.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:19.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:19.20#ibcon#[25=USB\r\n] 2006.140.08:22:19.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:19.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:19.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:22:19.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:22:19.23$vc4f8/valo=5,652.99 2006.140.08:22:19.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.08:22:19.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.08:22:19.23#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:19.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:19.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:19.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:22:19.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:19.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:19.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:22:19.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:22:19.29$vc4f8/va=5,7 2006.140.08:22:19.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.08:22:19.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.08:22:19.29#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:19.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:19.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:19.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:19.37#ibcon#[25=AT05-07\r\n] 2006.140.08:22:19.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:19.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:19.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.08:22:19.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:19.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:19.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:19.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:19.54#ibcon#[25=USB\r\n] 2006.140.08:22:19.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:19.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:19.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:22:19.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:22:19.57$vc4f8/valo=6,772.99 2006.140.08:22:19.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:22:19.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:22:19.57#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:19.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:19.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:19.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:22:19.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:19.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:19.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:22:19.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:22:19.63$vc4f8/va=6,6 2006.140.08:22:19.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.140.08:22:19.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.140.08:22:19.63#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:19.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:19.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:19.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:19.71#ibcon#[25=AT06-06\r\n] 2006.140.08:22:19.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:19.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:19.74#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.140.08:22:19.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:19.74#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:22:19.86#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:22:19.86#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:22:19.88#ibcon#[25=USB\r\n] 2006.140.08:22:19.91#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:22:19.91#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.140.08:22:19.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:22:19.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:22:19.91$vc4f8/valo=7,832.99 2006.140.08:22:19.91#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.140.08:22:19.91#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.140.08:22:19.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:19.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:22:19.91#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:22:19.91#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:22:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:22:19.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:22:19.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.140.08:22:19.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.140.08:22:19.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.140.08:22:19.97$vc4f8/va=7,6 2006.140.08:22:19.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.140.08:22:19.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.140.08:22:19.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:19.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:22:20.03#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:22:20.03#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:22:20.05#ibcon#[25=AT07-06\r\n] 2006.140.08:22:20.08#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:22:20.08#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.140.08:22:20.08#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.140.08:22:20.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:20.08#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:22:20.20#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:22:20.20#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:22:20.22#ibcon#[25=USB\r\n] 2006.140.08:22:20.25#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:22:20.25#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.140.08:22:20.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.140.08:22:20.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.140.08:22:20.25$vc4f8/valo=8,852.99 2006.140.08:22:20.25#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.140.08:22:20.25#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.140.08:22:20.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:20.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:22:20.25#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:22:20.25#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:22:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:22:20.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:22:20.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.140.08:22:20.31#ibcon#about to clear, iclass 16 cls_cnt 0 2006.140.08:22:20.31#ibcon#cleared, iclass 16 cls_cnt 0 2006.140.08:22:20.31$vc4f8/va=8,6 2006.140.08:22:20.31#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.140.08:22:20.31#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.140.08:22:20.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:20.31#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:22:20.37#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:22:20.37#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:22:20.39#ibcon#[25=AT08-06\r\n] 2006.140.08:22:20.42#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:22:20.42#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.140.08:22:20.42#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.140.08:22:20.42#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:20.42#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:22:20.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:22:20.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:22:20.56#ibcon#[25=USB\r\n] 2006.140.08:22:20.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:22:20.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.140.08:22:20.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.140.08:22:20.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.140.08:22:20.59$vc4f8/vblo=1,632.99 2006.140.08:22:20.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.140.08:22:20.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.140.08:22:20.59#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:20.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:22:20.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:22:20.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:22:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:22:20.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:22:20.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.140.08:22:20.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.140.08:22:20.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.140.08:22:20.65$vc4f8/vb=1,4 2006.140.08:22:20.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.140.08:22:20.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.140.08:22:20.65#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:20.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:22:20.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:22:20.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:22:20.67#ibcon#[27=AT01-04\r\n] 2006.140.08:22:20.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:22:20.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.140.08:22:20.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.140.08:22:20.70#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:20.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:22:20.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:22:20.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:22:20.84#ibcon#[27=USB\r\n] 2006.140.08:22:20.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:22:20.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.140.08:22:20.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.140.08:22:20.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.140.08:22:20.87$vc4f8/vblo=2,640.99 2006.140.08:22:20.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.140.08:22:20.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.140.08:22:20.87#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:20.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:20.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:20.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:20.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:22:20.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:20.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.140.08:22:20.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.140.08:22:20.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.140.08:22:20.93$vc4f8/vb=2,4 2006.140.08:22:20.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.140.08:22:20.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.140.08:22:20.93#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:20.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:20.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:20.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:21.01#ibcon#[27=AT02-04\r\n] 2006.140.08:22:21.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:21.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.140.08:22:21.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.140.08:22:21.04#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:21.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:21.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:21.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:21.18#ibcon#[27=USB\r\n] 2006.140.08:22:21.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:21.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.140.08:22:21.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.140.08:22:21.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.140.08:22:21.21$vc4f8/vblo=3,656.99 2006.140.08:22:21.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.140.08:22:21.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.140.08:22:21.21#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:21.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:21.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:21.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:21.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:22:21.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:21.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.140.08:22:21.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.140.08:22:21.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.140.08:22:21.27$vc4f8/vb=3,4 2006.140.08:22:21.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.140.08:22:21.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.140.08:22:21.27#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:21.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:21.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:21.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:21.35#ibcon#[27=AT03-04\r\n] 2006.140.08:22:21.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:21.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.140.08:22:21.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.140.08:22:21.38#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:21.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:21.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:21.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:21.52#ibcon#[27=USB\r\n] 2006.140.08:22:21.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:21.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.140.08:22:21.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.140.08:22:21.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.140.08:22:21.55$vc4f8/vblo=4,712.99 2006.140.08:22:21.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.140.08:22:21.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.140.08:22:21.55#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:21.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:21.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:21.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:22:21.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:21.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.140.08:22:21.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.140.08:22:21.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.140.08:22:21.61$vc4f8/vb=4,4 2006.140.08:22:21.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.140.08:22:21.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.140.08:22:21.61#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:21.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:21.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:21.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:21.69#ibcon#[27=AT04-04\r\n] 2006.140.08:22:21.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:21.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.140.08:22:21.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.140.08:22:21.72#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:21.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:21.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:21.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:21.86#ibcon#[27=USB\r\n] 2006.140.08:22:21.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:21.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.140.08:22:21.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:22:21.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:22:21.89$vc4f8/vblo=5,744.99 2006.140.08:22:21.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.140.08:22:21.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.140.08:22:21.89#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:21.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:21.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:21.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:22:21.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:21.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.140.08:22:21.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.140.08:22:21.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.140.08:22:21.95$vc4f8/vb=5,4 2006.140.08:22:21.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.08:22:21.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.08:22:21.95#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:21.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:22.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:22.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:22.03#ibcon#[27=AT05-04\r\n] 2006.140.08:22:22.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:22.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:22:22.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.08:22:22.06#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:22.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:22.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:22.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:22.20#ibcon#[27=USB\r\n] 2006.140.08:22:22.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:22.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:22:22.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:22:22.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:22:22.23$vc4f8/vblo=6,752.99 2006.140.08:22:22.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.140.08:22:22.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.140.08:22:22.23#ibcon#ireg 17 cls_cnt 0 2006.140.08:22:22.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:22.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:22.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:22.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:22:22.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:22.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.140.08:22:22.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.140.08:22:22.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.140.08:22:22.29$vc4f8/vb=6,4 2006.140.08:22:22.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.140.08:22:22.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.140.08:22:22.29#ibcon#ireg 11 cls_cnt 2 2006.140.08:22:22.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:22.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:22.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:22.37#ibcon#[27=AT06-04\r\n] 2006.140.08:22:22.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:22.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.140.08:22:22.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.140.08:22:22.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:22:22.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:22.52#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:22.52#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:22.54#ibcon#[27=USB\r\n] 2006.140.08:22:22.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:22.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.140.08:22:22.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.140.08:22:22.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.140.08:22:22.57$vc4f8/vabw=wide 2006.140.08:22:22.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.140.08:22:22.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.140.08:22:22.57#ibcon#ireg 8 cls_cnt 0 2006.140.08:22:22.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:22.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:22.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:22.59#ibcon#[25=BW32\r\n] 2006.140.08:22:22.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:22.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.140.08:22:22.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.140.08:22:22.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.140.08:22:22.62$vc4f8/vbbw=wide 2006.140.08:22:22.62#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.140.08:22:22.62#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.140.08:22:22.62#ibcon#ireg 8 cls_cnt 0 2006.140.08:22:22.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:22:22.69#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:22:22.69#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:22:22.71#ibcon#[27=BW32\r\n] 2006.140.08:22:22.74#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:22:22.74#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.140.08:22:22.74#ibcon#about to clear, iclass 10 cls_cnt 0 2006.140.08:22:22.74#ibcon#cleared, iclass 10 cls_cnt 0 2006.140.08:22:22.74$4f8m12a/ifd4f 2006.140.08:22:22.74$ifd4f/lo= 2006.140.08:22:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:22:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:22:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:22:22.74$ifd4f/patch= 2006.140.08:22:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:22:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:22:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:22:22.74$4f8m12a/"form=m,16.000,1:2 2006.140.08:22:22.74$4f8m12a/"tpicd 2006.140.08:22:22.74$4f8m12a/echo=off 2006.140.08:22:22.74$4f8m12a/xlog=off 2006.140.08:22:22.74:!2006.140.08:24:30 2006.140.08:22:56.14#trakl#Source acquired 2006.140.08:22:56.14#flagr#flagr/antenna,acquired 2006.140.08:24:30.00:preob 2006.140.08:24:30.14/onsource/TRACKING 2006.140.08:24:30.14:!2006.140.08:24:40 2006.140.08:24:40.00:data_valid=on 2006.140.08:24:40.00:midob 2006.140.08:24:41.14/onsource/TRACKING 2006.140.08:24:41.14/wx/22.20,992.9,100 2006.140.08:24:41.35/cable/+6.5059E-03 2006.140.08:24:42.44/va/01,08,usb,yes,45,48 2006.140.08:24:42.44/va/02,07,usb,yes,46,48 2006.140.08:24:42.44/va/03,06,usb,yes,48,49 2006.140.08:24:42.44/va/04,07,usb,yes,47,50 2006.140.08:24:42.44/va/05,07,usb,yes,48,51 2006.140.08:24:42.44/va/06,06,usb,yes,47,47 2006.140.08:24:42.44/va/07,06,usb,yes,48,48 2006.140.08:24:42.44/va/08,06,usb,yes,51,50 2006.140.08:24:42.67/valo/01,532.99,yes,locked 2006.140.08:24:42.67/valo/02,572.99,yes,locked 2006.140.08:24:42.67/valo/03,672.99,yes,locked 2006.140.08:24:42.67/valo/04,832.99,yes,locked 2006.140.08:24:42.67/valo/05,652.99,yes,locked 2006.140.08:24:42.67/valo/06,772.99,yes,locked 2006.140.08:24:42.67/valo/07,832.99,yes,locked 2006.140.08:24:42.67/valo/08,852.99,yes,locked 2006.140.08:24:43.76/vb/01,04,usb,yes,30,29 2006.140.08:24:43.76/vb/02,04,usb,yes,32,33 2006.140.08:24:43.76/vb/03,04,usb,yes,28,32 2006.140.08:24:43.76/vb/04,04,usb,yes,29,29 2006.140.08:24:43.76/vb/05,04,usb,yes,28,32 2006.140.08:24:43.76/vb/06,04,usb,yes,29,32 2006.140.08:24:43.76/vb/07,04,usb,yes,31,31 2006.140.08:24:43.76/vb/08,04,usb,yes,28,32 2006.140.08:24:43.99/vblo/01,632.99,yes,locked 2006.140.08:24:43.99/vblo/02,640.99,yes,locked 2006.140.08:24:43.99/vblo/03,656.99,yes,locked 2006.140.08:24:43.99/vblo/04,712.99,yes,locked 2006.140.08:24:43.99/vblo/05,744.99,yes,locked 2006.140.08:24:43.99/vblo/06,752.99,yes,locked 2006.140.08:24:43.99/vblo/07,734.99,yes,locked 2006.140.08:24:43.99/vblo/08,744.99,yes,locked 2006.140.08:24:44.14/vabw/8 2006.140.08:24:44.29/vbbw/8 2006.140.08:24:44.47/xfe/off,on,14.7 2006.140.08:24:44.84/ifatt/23,28,28,28 2006.140.08:24:45.10/fmout-gps/S +1.18E-07 2006.140.08:24:45.16:!2006.140.08:25:40 2006.140.08:25:40.00:data_valid=off 2006.140.08:25:40.00:postob 2006.140.08:25:40.14/cable/+6.5059E-03 2006.140.08:25:40.14/wx/22.19,992.9,100 2006.140.08:25:41.10/fmout-gps/S +1.16E-07 2006.140.08:25:41.10:scan_name=140-0826,k06140,60 2006.140.08:25:41.10:source=1418+546,141946.60,542314.8,2000.0,cw 2006.140.08:25:41.14#flagr#flagr/antenna,new-source 2006.140.08:25:42.14:checkk5 2006.140.08:25:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.140.08:25:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.140.08:25:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.140.08:25:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.140.08:25:44.01/chk_obsdata//k5ts1/T1400824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.08:25:44.37/chk_obsdata//k5ts2/T1400824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.08:25:44.74/chk_obsdata//k5ts3/T1400824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.08:25:45.11/chk_obsdata//k5ts4/T1400824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.140.08:25:45.80/k5log//k5ts1_log_newline 2006.140.08:25:46.48/k5log//k5ts2_log_newline 2006.140.08:25:47.17/k5log//k5ts3_log_newline 2006.140.08:25:47.85/k5log//k5ts4_log_newline 2006.140.08:25:47.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:25:47.88:4f8m12a=3 2006.140.08:25:47.88$4f8m12a/echo=on 2006.140.08:25:47.88$4f8m12a/pcalon 2006.140.08:25:47.88$pcalon/"no phase cal control is implemented here 2006.140.08:25:47.88$4f8m12a/"tpicd=stop 2006.140.08:25:47.88$4f8m12a/vc4f8 2006.140.08:25:47.88$vc4f8/valo=1,532.99 2006.140.08:25:47.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.08:25:47.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.08:25:47.88#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:47.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:47.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:47.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:47.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.140.08:25:47.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:47.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:47.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:25:47.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:25:47.97$vc4f8/va=1,8 2006.140.08:25:47.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.08:25:47.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.08:25:47.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:47.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:47.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:47.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:48.01#ibcon#[25=AT01-08\r\n] 2006.140.08:25:48.04#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:48.04#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:48.04#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.08:25:48.04#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:48.04#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:48.16#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:48.16#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:48.18#ibcon#[25=USB\r\n] 2006.140.08:25:48.21#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:48.21#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:48.21#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:25:48.21#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:25:48.21$vc4f8/valo=2,572.99 2006.140.08:25:48.21#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:25:48.21#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:25:48.21#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:48.21#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:48.21#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:48.21#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:48.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.140.08:25:48.27#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:48.27#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:48.27#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:25:48.27#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:25:48.27$vc4f8/va=2,7 2006.140.08:25:48.27#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:25:48.27#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:25:48.27#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:48.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:48.33#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:48.33#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:48.35#ibcon#[25=AT02-07\r\n] 2006.140.08:25:48.38#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:48.38#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:48.38#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:25:48.38#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:48.38#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:48.50#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:48.50#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:48.52#ibcon#[25=USB\r\n] 2006.140.08:25:48.55#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:48.55#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:48.55#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:25:48.55#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:25:48.55$vc4f8/valo=3,672.99 2006.140.08:25:48.55#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:25:48.55#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:25:48.55#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:48.55#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:48.55#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:48.55#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:48.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.140.08:25:48.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:48.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:48.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:25:48.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:25:48.63$vc4f8/va=3,6 2006.140.08:25:48.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:25:48.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:25:48.63#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:48.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:48.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:48.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:48.69#ibcon#[25=AT03-06\r\n] 2006.140.08:25:48.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:48.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:48.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:25:48.72#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:48.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:48.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:48.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:48.86#ibcon#[25=USB\r\n] 2006.140.08:25:48.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:48.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:48.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:25:48.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:25:48.89$vc4f8/valo=4,832.99 2006.140.08:25:48.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.140.08:25:48.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.140.08:25:48.89#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:48.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:25:48.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:25:48.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:25:48.90#abcon#<5=/03 1.9 4.3 22.19100 992.9\r\n> 2006.140.08:25:48.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.140.08:25:48.92#abcon#{5=INTERFACE CLEAR} 2006.140.08:25:48.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:25:48.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.140.08:25:48.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.140.08:25:48.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.140.08:25:48.95$vc4f8/va=4,7 2006.140.08:25:48.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.140.08:25:48.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.140.08:25:48.95#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:48.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:25:48.98#abcon#[5=S1D000X0/0*\r\n] 2006.140.08:25:49.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:25:49.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:25:49.03#ibcon#[25=AT04-07\r\n] 2006.140.08:25:49.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:25:49.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.140.08:25:49.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.140.08:25:49.06#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:49.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:25:49.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:25:49.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:25:49.20#ibcon#[25=USB\r\n] 2006.140.08:25:49.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:25:49.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.140.08:25:49.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.140.08:25:49.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.140.08:25:49.23$vc4f8/valo=5,652.99 2006.140.08:25:49.23#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:25:49.23#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:25:49.23#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:49.23#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:49.23#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:49.23#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.140.08:25:49.29#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:49.29#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:49.29#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:25:49.29#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:25:49.29$vc4f8/va=5,7 2006.140.08:25:49.29#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:25:49.29#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:25:49.29#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:49.29#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:49.35#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:49.35#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:49.37#ibcon#[25=AT05-07\r\n] 2006.140.08:25:49.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:49.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:49.40#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:25:49.40#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:49.40#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:49.52#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:49.52#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:49.54#ibcon#[25=USB\r\n] 2006.140.08:25:49.57#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:49.57#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:49.57#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:25:49.57#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:25:49.57$vc4f8/valo=6,772.99 2006.140.08:25:49.57#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:25:49.57#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:25:49.57#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:49.57#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:49.57#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:49.57#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:49.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.140.08:25:49.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:49.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:49.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:25:49.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:25:49.63$vc4f8/va=6,6 2006.140.08:25:49.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.140.08:25:49.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.140.08:25:49.63#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:49.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:49.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:49.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:49.71#ibcon#[25=AT06-06\r\n] 2006.140.08:25:49.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:49.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:49.74#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.140.08:25:49.74#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:49.74#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:25:49.86#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:25:49.86#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:25:49.88#ibcon#[25=USB\r\n] 2006.140.08:25:49.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:25:49.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.140.08:25:49.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:25:49.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:25:49.91$vc4f8/valo=7,832.99 2006.140.08:25:49.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.140.08:25:49.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.140.08:25:49.91#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:49.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:25:49.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:25:49.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:25:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.140.08:25:49.97#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:25:49.97#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.140.08:25:49.97#ibcon#about to clear, iclass 13 cls_cnt 0 2006.140.08:25:49.97#ibcon#cleared, iclass 13 cls_cnt 0 2006.140.08:25:49.97$vc4f8/va=7,6 2006.140.08:25:49.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.140.08:25:49.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.140.08:25:49.97#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:49.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:25:50.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:25:50.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:25:50.05#ibcon#[25=AT07-06\r\n] 2006.140.08:25:50.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:25:50.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.140.08:25:50.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.140.08:25:50.08#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:50.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:25:50.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:25:50.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:25:50.22#ibcon#[25=USB\r\n] 2006.140.08:25:50.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:25:50.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.140.08:25:50.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.140.08:25:50.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.140.08:25:50.25$vc4f8/valo=8,852.99 2006.140.08:25:50.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.140.08:25:50.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.140.08:25:50.25#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:50.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:25:50.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:25:50.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:25:50.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.140.08:25:50.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:25:50.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.140.08:25:50.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.140.08:25:50.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.140.08:25:50.31$vc4f8/va=8,6 2006.140.08:25:50.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.140.08:25:50.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.140.08:25:50.31#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:50.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:25:50.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:25:50.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:25:50.39#ibcon#[25=AT08-06\r\n] 2006.140.08:25:50.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:25:50.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.140.08:25:50.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.140.08:25:50.43#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:50.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:25:50.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:25:50.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:25:50.57#ibcon#[25=USB\r\n] 2006.140.08:25:50.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:25:50.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.140.08:25:50.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.140.08:25:50.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.140.08:25:50.60$vc4f8/vblo=1,632.99 2006.140.08:25:50.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.140.08:25:50.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.140.08:25:50.60#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:50.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:50.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:50.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.140.08:25:50.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:50.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.140.08:25:50.66#ibcon#about to clear, iclass 21 cls_cnt 0 2006.140.08:25:50.66#ibcon#cleared, iclass 21 cls_cnt 0 2006.140.08:25:50.66$vc4f8/vb=1,4 2006.140.08:25:50.66#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.140.08:25:50.66#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.140.08:25:50.66#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:50.66#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:50.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:50.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:50.68#ibcon#[27=AT01-04\r\n] 2006.140.08:25:50.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:50.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.140.08:25:50.71#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.140.08:25:50.71#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:50.71#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:50.83#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:50.83#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:50.85#ibcon#[27=USB\r\n] 2006.140.08:25:50.88#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:50.88#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.140.08:25:50.88#ibcon#about to clear, iclass 23 cls_cnt 0 2006.140.08:25:50.88#ibcon#cleared, iclass 23 cls_cnt 0 2006.140.08:25:50.88$vc4f8/vblo=2,640.99 2006.140.08:25:50.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.140.08:25:50.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.140.08:25:50.88#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:50.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:50.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:50.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.140.08:25:50.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:50.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.140.08:25:50.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.140.08:25:50.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.140.08:25:50.94$vc4f8/vb=2,4 2006.140.08:25:50.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.140.08:25:50.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.140.08:25:50.94#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:50.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:51.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:51.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:51.02#ibcon#[27=AT02-04\r\n] 2006.140.08:25:51.05#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:51.05#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.140.08:25:51.05#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.140.08:25:51.05#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:51.05#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:51.17#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:51.17#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:51.19#ibcon#[27=USB\r\n] 2006.140.08:25:51.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:51.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.140.08:25:51.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.140.08:25:51.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.140.08:25:51.22$vc4f8/vblo=3,656.99 2006.140.08:25:51.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.140.08:25:51.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.140.08:25:51.22#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:51.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:51.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:51.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.140.08:25:51.28#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:51.28#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.140.08:25:51.28#ibcon#about to clear, iclass 29 cls_cnt 0 2006.140.08:25:51.28#ibcon#cleared, iclass 29 cls_cnt 0 2006.140.08:25:51.28$vc4f8/vb=3,4 2006.140.08:25:51.28#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.140.08:25:51.28#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.140.08:25:51.28#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:51.28#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:51.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:51.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:51.36#ibcon#[27=AT03-04\r\n] 2006.140.08:25:51.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:51.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.140.08:25:51.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.140.08:25:51.39#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:51.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:51.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:51.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:51.53#ibcon#[27=USB\r\n] 2006.140.08:25:51.56#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:51.56#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.140.08:25:51.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.140.08:25:51.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.140.08:25:51.56$vc4f8/vblo=4,712.99 2006.140.08:25:51.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.140.08:25:51.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.140.08:25:51.56#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:51.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:25:51.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:25:51.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:25:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.140.08:25:51.62#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:25:51.62#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.140.08:25:51.62#ibcon#about to clear, iclass 33 cls_cnt 0 2006.140.08:25:51.62#ibcon#cleared, iclass 33 cls_cnt 0 2006.140.08:25:51.62$vc4f8/vb=4,4 2006.140.08:25:51.62#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.140.08:25:51.62#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.140.08:25:51.62#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:51.62#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:25:51.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:25:51.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:25:51.70#ibcon#[27=AT04-04\r\n] 2006.140.08:25:51.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:25:51.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.140.08:25:51.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.140.08:25:51.73#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:51.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:25:51.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:25:51.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:25:51.87#ibcon#[27=USB\r\n] 2006.140.08:25:51.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:25:51.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.140.08:25:51.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.140.08:25:51.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.140.08:25:51.90$vc4f8/vblo=5,744.99 2006.140.08:25:51.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.140.08:25:51.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.140.08:25:51.90#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:51.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:25:51.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:25:51.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:25:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.140.08:25:51.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:25:51.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.140.08:25:51.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.140.08:25:51.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.140.08:25:51.96$vc4f8/vb=5,4 2006.140.08:25:51.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.140.08:25:51.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.140.08:25:51.96#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:51.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:25:52.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:25:52.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:25:52.04#ibcon#[27=AT05-04\r\n] 2006.140.08:25:52.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:25:52.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.140.08:25:52.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.140.08:25:52.07#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:52.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:25:52.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:25:52.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:25:52.21#ibcon#[27=USB\r\n] 2006.140.08:25:52.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:25:52.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.140.08:25:52.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.140.08:25:52.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.140.08:25:52.24$vc4f8/vblo=6,752.99 2006.140.08:25:52.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.140.08:25:52.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.140.08:25:52.24#ibcon#ireg 17 cls_cnt 0 2006.140.08:25:52.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:52.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:52.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.140.08:25:52.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:52.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.140.08:25:52.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.140.08:25:52.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.140.08:25:52.30$vc4f8/vb=6,4 2006.140.08:25:52.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.140.08:25:52.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.140.08:25:52.30#ibcon#ireg 11 cls_cnt 2 2006.140.08:25:52.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:52.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:52.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:52.38#ibcon#[27=AT06-04\r\n] 2006.140.08:25:52.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:52.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.140.08:25:52.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.140.08:25:52.41#ibcon#ireg 7 cls_cnt 0 2006.140.08:25:52.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:52.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:52.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:52.55#ibcon#[27=USB\r\n] 2006.140.08:25:52.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:52.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.140.08:25:52.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.140.08:25:52.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.140.08:25:52.58$vc4f8/vabw=wide 2006.140.08:25:52.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.140.08:25:52.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.140.08:25:52.58#ibcon#ireg 8 cls_cnt 0 2006.140.08:25:52.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:52.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:52.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:52.60#ibcon#[25=BW32\r\n] 2006.140.08:25:52.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:52.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.140.08:25:52.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.140.08:25:52.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.140.08:25:52.63$vc4f8/vbbw=wide 2006.140.08:25:52.63#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.140.08:25:52.63#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.140.08:25:52.63#ibcon#ireg 8 cls_cnt 0 2006.140.08:25:52.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:25:52.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:25:52.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:25:52.72#ibcon#[27=BW32\r\n] 2006.140.08:25:52.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:25:52.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.140.08:25:52.75#ibcon#about to clear, iclass 11 cls_cnt 0 2006.140.08:25:52.75#ibcon#cleared, iclass 11 cls_cnt 0 2006.140.08:25:52.75$4f8m12a/ifd4f 2006.140.08:25:52.75$ifd4f/lo= 2006.140.08:25:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.140.08:25:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.140.08:25:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.140.08:25:52.75$ifd4f/patch= 2006.140.08:25:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.140.08:25:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.140.08:25:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.140.08:25:52.75$4f8m12a/"form=m,16.000,1:2 2006.140.08:25:52.75$4f8m12a/"tpicd 2006.140.08:25:52.75$4f8m12a/echo=off 2006.140.08:25:52.75$4f8m12a/xlog=off 2006.140.08:25:52.75:!2006.140.08:26:20 2006.140.08:26:01.14#trakl#Source acquired 2006.140.08:26:02.14#flagr#flagr/antenna,acquired 2006.140.08:26:20.00:preob 2006.140.08:26:21.14/onsource/TRACKING 2006.140.08:26:21.14:!2006.140.08:26:30 2006.140.08:26:30.00:data_valid=on 2006.140.08:26:30.00:midob 2006.140.08:26:30.14/onsource/TRACKING 2006.140.08:26:30.14/wx/22.18,993.0,100 2006.140.08:26:30.23/cable/+6.5049E-03 2006.140.08:26:31.32/va/01,08,usb,yes,44,46 2006.140.08:26:31.32/va/02,07,usb,yes,44,46 2006.140.08:26:31.32/va/03,06,usb,yes,47,47 2006.140.08:26:31.32/va/04,07,usb,yes,45,49 2006.140.08:26:31.32/va/05,07,usb,yes,47,50 2006.140.08:26:31.32/va/06,06,usb,yes,46,46 2006.140.08:26:31.32/va/07,06,usb,yes,47,46 2006.140.08:26:31.32/va/08,06,usb,yes,50,49 2006.140.08:26:31.55/valo/01,532.99,yes,locked 2006.140.08:26:31.55/valo/02,572.99,yes,locked 2006.140.08:26:31.55/valo/03,672.99,yes,locked 2006.140.08:26:31.55/valo/04,832.99,yes,locked 2006.140.08:26:31.55/valo/05,652.99,yes,locked 2006.140.08:26:31.55/valo/06,772.99,yes,locked 2006.140.08:26:31.55/valo/07,832.99,yes,locked 2006.140.08:26:31.55/valo/08,852.99,yes,locked 2006.140.08:26:32.64/vb/01,04,usb,yes,30,29 2006.140.08:26:32.64/vb/02,04,usb,yes,32,34 2006.140.08:26:32.64/vb/03,04,usb,yes,28,32 2006.140.08:26:32.64/vb/04,04,usb,yes,29,30 2006.140.08:26:32.64/vb/05,04,usb,yes,28,32 2006.140.08:26:32.64/vb/06,04,usb,yes,29,32 2006.140.08:26:32.64/vb/07,04,usb,yes,31,31 2006.140.08:26:32.64/vb/08,04,usb,yes,29,32 2006.140.08:26:32.87/vblo/01,632.99,yes,locked 2006.140.08:26:32.87/vblo/02,640.99,yes,locked 2006.140.08:26:32.87/vblo/03,656.99,yes,locked 2006.140.08:26:32.87/vblo/04,712.99,yes,locked 2006.140.08:26:32.87/vblo/05,744.99,yes,locked 2006.140.08:26:32.87/vblo/06,752.99,yes,locked 2006.140.08:26:32.87/vblo/07,734.99,yes,locked 2006.140.08:26:32.87/vblo/08,744.99,yes,locked 2006.140.08:26:33.02/vabw/8 2006.140.08:26:33.17/vbbw/8 2006.140.08:26:33.26/xfe/off,on,15.2 2006.140.08:26:33.63/ifatt/23,28,28,28 2006.140.08:26:34.10/fmout-gps/S +1.15E-07 2006.140.08:26:34.17:!2006.140.08:27:30 2006.140.08:27:30.00:data_valid=off 2006.140.08:27:30.00:postob 2006.140.08:27:30.08/cable/+6.5060E-03 2006.140.08:27:30.08/wx/22.17,993.1,100 2006.140.08:27:31.10/fmout-gps/S +1.14E-07 2006.140.08:27:31.10:checkk5last 2006.140.08:27:31.10&checkk5last/chk_obsdata=1 2006.140.08:27:31.11&checkk5last/chk_obsdata=2 2006.140.08:27:31.11&checkk5last/chk_obsdata=3 2006.140.08:27:31.11&checkk5last/chk_obsdata=4 2006.140.08:27:31.12&checkk5last/k5log=1 2006.140.08:27:31.12&checkk5last/k5log=2 2006.140.08:27:31.12&checkk5last/k5log=3 2006.140.08:27:31.13&checkk5last/k5log=4 2006.140.08:27:31.13&checkk5last/obsinfo 2006.140.08:27:31.51/chk_obsdata//k5ts1/T1400826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:27:31.89/chk_obsdata//k5ts2/T1400826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:27:32.26/chk_obsdata//k5ts3/T1400826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:27:32.63/chk_obsdata//k5ts4/T1400826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.140.08:27:33.38/k5log//k5ts1_log_newline 2006.140.08:27:34.07/k5log//k5ts2_log_newline 2006.140.08:27:34.76/k5log//k5ts3_log_newline 2006.140.08:27:35.45/k5log//k5ts4_log_newline 2006.140.08:27:35.48/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.140.08:27:35.48:"sched_end 2006.140.08:27:35.48:source=idle 2006.140.08:27:36.13:stow 2006.140.08:27:36.13&stow/source=idle 2006.140.08:27:36.13&stow/"this is stow command. 2006.140.08:27:36.13&stow/antenna=m3 2006.140.08:27:36.13#flagr#flagr/antenna,new-source 2006.140.08:27:39.01:!+10m 2006.140.08:37:39.02:standby 2006.140.08:37:39.02&standby/"this is standby command. 2006.140.08:37:39.02&standby/antenna=m0 2006.140.08:37:40.01:sy=cp /usr2/log/k06140ts.log /usr2/log_backup/ 2006.140.08:37:40.04:log=u06140ts