2006.133.08:37:20.09:Log Opened: Mark IV Field System Version 9.7.7 2006.133.08:37:20.09:location,TSUKUB32,-140.09,36.10,61.0 2006.133.08:37:20.09:horizon1,0.,5.,360. 2006.133.08:37:20.10:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.133.08:37:20.10:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.133.08:37:20.10:drivev11,330,270,no 2006.133.08:37:20.11:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.133.08:37:20.11:drivev13,15.000,268,10.000,10.000,10.000 2006.133.08:37:20.11:drivev21,330,270,no 2006.133.08:37:20.12:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.133.08:37:20.12:drivev23,15.000,268,10.000,10.000,10.000 2006.133.08:37:20.12:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.133.08:37:20.17:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.133.08:37:20.17:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.133.08:37:20.17:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.133.08:37:20.18:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.133.08:37:20.18:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.133.08:37:20.18:time,-0.364,101.533,rate 2006.133.08:37:20.19:flagr,200 2006.133.08:37:20.19:proc=k06134ts 2006.133.08:37:20.20:" k06134 2006 tsukub32 t ts 2006.133.08:37:20.20:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.133.08:37:20.20:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.133.08:37:20.21:" 108 tsukub32 14 17400 2006.133.08:37:20.25:" drudg version 050216 compiled under fs 9.7.07 2006.133.08:37:20.25:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.133.08:37:20.26:!2006.134.07:19:50 2006.134.07:19:50.00:unstow 2006.134.07:19:50.00&unstow/antenna=e 2006.134.07:19:50.00&unstow/!+10s 2006.134.07:19:50.00&unstow/antenna=m2 2006.134.07:20:02.01:scan_name=134-0730,k06134,60 2006.134.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.134.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.134.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.134.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.134.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.134.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.134.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.134.07:20:03.14:ready_k5 2006.134.07:20:03.14&ready_k5/obsinfo=st 2006.134.07:20:03.14&ready_k5/autoobs=1 2006.134.07:20:03.14&ready_k5/autoobs=2 2006.134.07:20:03.14&ready_k5/autoobs=3 2006.134.07:20:03.14&ready_k5/autoobs=4 2006.134.07:20:03.14&ready_k5/obsinfo 2006.134.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.134.07:20:03.14#flagr#flagr/antenna,new-source 2006.134.07:20:06.31/autoobs//k5ts1/ autoobs started! 2006.134.07:20:09.40/autoobs//k5ts2/ autoobs started! 2006.134.07:20:12.51/autoobs//k5ts3/ autoobs started! 2006.134.07:20:15.62/autoobs//k5ts4/ autoobs started! 2006.134.07:20:15.65/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:20:15.65:4f8m12a=1 2006.134.07:20:15.65&4f8m12a/xlog=on 2006.134.07:20:15.65&4f8m12a/echo=on 2006.134.07:20:15.65&4f8m12a/pcalon 2006.134.07:20:15.65&4f8m12a/"tpicd=stop 2006.134.07:20:15.65&4f8m12a/vc4f8 2006.134.07:20:15.65&4f8m12a/ifd4f 2006.134.07:20:15.65&4f8m12a/"form=m,16.000,1:2 2006.134.07:20:15.65&4f8m12a/"tpicd 2006.134.07:20:15.65&4f8m12a/echo=off 2006.134.07:20:15.65&4f8m12a/xlog=off 2006.134.07:20:15.65$4f8m12a/echo=on 2006.134.07:20:15.65$4f8m12a/pcalon 2006.134.07:20:15.65&pcalon/"no phase cal control is implemented here 2006.134.07:20:15.65$pcalon/"no phase cal control is implemented here 2006.134.07:20:15.65$4f8m12a/"tpicd=stop 2006.134.07:20:15.65$4f8m12a/vc4f8 2006.134.07:20:15.65&vc4f8/valo=1,532.99 2006.134.07:20:15.65&vc4f8/va=1,8 2006.134.07:20:15.65&vc4f8/valo=2,572.99 2006.134.07:20:15.65&vc4f8/va=2,7 2006.134.07:20:15.65&vc4f8/valo=3,672.99 2006.134.07:20:15.65&vc4f8/va=3,6 2006.134.07:20:15.65&vc4f8/valo=4,832.99 2006.134.07:20:15.65&vc4f8/va=4,7 2006.134.07:20:15.65&vc4f8/valo=5,652.99 2006.134.07:20:15.65&vc4f8/va=5,6 2006.134.07:20:15.65&vc4f8/valo=6,772.99 2006.134.07:20:15.65&vc4f8/va=6,5 2006.134.07:20:15.65&vc4f8/valo=7,832.99 2006.134.07:20:15.65&vc4f8/va=7,5 2006.134.07:20:15.65&vc4f8/valo=8,852.99 2006.134.07:20:15.65&vc4f8/va=8,6 2006.134.07:20:15.65&vc4f8/vblo=1,632.99 2006.134.07:20:15.65&vc4f8/vb=1,4 2006.134.07:20:15.65&vc4f8/vblo=2,640.99 2006.134.07:20:15.65&vc4f8/vb=2,4 2006.134.07:20:15.65&vc4f8/vblo=3,656.99 2006.134.07:20:15.65&vc4f8/vb=3,4 2006.134.07:20:15.65&vc4f8/vblo=4,712.99 2006.134.07:20:15.65&vc4f8/vb=4,4 2006.134.07:20:15.65&vc4f8/vblo=5,744.99 2006.134.07:20:15.65&vc4f8/vb=5,4 2006.134.07:20:15.65&vc4f8/vblo=6,752.99 2006.134.07:20:15.65&vc4f8/vb=6,4 2006.134.07:20:15.65&vc4f8/vabw=wide 2006.134.07:20:15.65&vc4f8/vbbw=wide 2006.134.07:20:15.65$vc4f8/valo=1,532.99 2006.134.07:20:15.66#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:20:15.66#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:20:15.66#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:15.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:15.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:15.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:15.69#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:20:15.74#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:15.74#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:15.74#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:20:15.74#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:20:15.74$vc4f8/va=1,8 2006.134.07:20:15.74#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:20:15.74#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:20:15.74#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:15.74#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:15.74#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:15.74#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:15.76#ibcon#[25=AT01-08\r\n] 2006.134.07:20:15.79#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:15.79#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:15.79#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:20:15.79#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:15.79#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:15.91#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:15.91#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:15.93#ibcon#[25=USB\r\n] 2006.134.07:20:15.98#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:15.98#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:15.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:20:15.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:20:15.98$vc4f8/valo=2,572.99 2006.134.07:20:15.98#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:20:15.98#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:20:15.98#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:15.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:15.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:15.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:15.99#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:20:16.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:16.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:16.03#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:20:16.03#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:20:16.03$vc4f8/va=2,7 2006.134.07:20:16.03#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:20:16.03#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:20:16.03#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:16.03#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:16.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:16.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:16.12#ibcon#[25=AT02-07\r\n] 2006.134.07:20:16.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:16.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:16.15#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:20:16.15#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:16.15#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:16.27#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:16.27#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:16.29#ibcon#[25=USB\r\n] 2006.134.07:20:16.34#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:16.34#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:16.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:20:16.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:20:16.34$vc4f8/valo=3,672.99 2006.134.07:20:16.34#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:20:16.34#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:20:16.34#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:16.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:16.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:16.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:16.35#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:20:16.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:16.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:16.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:20:16.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:20:16.39$vc4f8/va=3,6 2006.134.07:20:16.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:20:16.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:20:16.39#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:16.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:16.46#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:16.46#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:16.48#ibcon#[25=AT03-06\r\n] 2006.134.07:20:16.51#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:16.51#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:16.51#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:20:16.51#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:16.51#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:16.63#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:16.63#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:16.65#ibcon#[25=USB\r\n] 2006.134.07:20:16.68#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:16.68#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:16.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:20:16.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:20:16.68$vc4f8/valo=4,832.99 2006.134.07:20:16.68#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:20:16.68#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:20:16.68#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:16.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:16.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:16.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:16.70#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:20:16.74#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:16.74#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:16.74#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:20:16.74#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:20:16.74$vc4f8/va=4,7 2006.134.07:20:16.74#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:20:16.74#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:20:16.74#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:16.74#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:16.80#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:16.80#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:16.82#ibcon#[25=AT04-07\r\n] 2006.134.07:20:16.85#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:16.85#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:16.85#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:20:16.85#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:16.85#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:16.97#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:16.97#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:16.99#ibcon#[25=USB\r\n] 2006.134.07:20:17.02#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:17.02#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:17.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:20:17.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:20:17.02$vc4f8/valo=5,652.99 2006.134.07:20:17.02#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:20:17.02#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:20:17.02#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:17.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:17.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:17.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:17.04#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:20:17.08#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:17.08#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:17.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:20:17.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:20:17.08$vc4f8/va=5,6 2006.134.07:20:17.08#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:20:17.08#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:20:17.08#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:17.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:17.14#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:17.14#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:17.16#ibcon#[25=AT05-06\r\n] 2006.134.07:20:17.19#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:17.19#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:17.19#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:20:17.19#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:17.19#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:17.31#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:17.31#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:17.33#ibcon#[25=USB\r\n] 2006.134.07:20:17.36#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:17.36#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:17.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:20:17.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:20:17.36$vc4f8/valo=6,772.99 2006.134.07:20:17.36#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:20:17.36#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:20:17.36#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:17.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:17.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:17.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:17.40#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:20:17.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:17.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:17.44#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:20:17.44#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:20:17.44$vc4f8/va=6,5 2006.134.07:20:17.44#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:20:17.44#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:20:17.44#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:17.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:17.48#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:17.48#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:17.50#ibcon#[25=AT06-05\r\n] 2006.134.07:20:17.53#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:17.53#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:17.53#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:20:17.53#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:17.53#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:17.65#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:17.65#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:17.67#ibcon#[25=USB\r\n] 2006.134.07:20:17.68#abcon#<5=/04 4.1 6.4 19.39 741006.0\r\n> 2006.134.07:20:17.70#abcon#{5=INTERFACE CLEAR} 2006.134.07:20:17.70#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:17.70#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:17.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:20:17.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:20:17.70$vc4f8/valo=7,832.99 2006.134.07:20:17.70#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:20:17.70#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:20:17.70#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:17.70#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:20:17.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:20:17.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:20:17.72#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:20:17.76#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:20:17.76#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:20:17.76#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:20:17.76#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:20:17.76#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:20:17.76$vc4f8/va=7,5 2006.134.07:20:17.76#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.07:20:17.76#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.07:20:17.76#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:17.76#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:20:17.82#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:20:17.82#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:20:17.84#ibcon#[25=AT07-05\r\n] 2006.134.07:20:17.87#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:20:17.87#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:20:17.87#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.07:20:17.87#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:17.87#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:20:17.99#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:20:17.99#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:20:18.01#ibcon#[25=USB\r\n] 2006.134.07:20:18.04#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:20:18.04#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:20:18.04#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:20:18.04#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:20:18.04$vc4f8/valo=8,852.99 2006.134.07:20:18.04#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.07:20:18.04#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.07:20:18.04#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:18.04#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:20:18.04#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:20:18.04#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:20:18.06#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:20:18.10#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:20:18.10#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:20:18.10#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:20:18.10#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:20:18.10$vc4f8/va=8,6 2006.134.07:20:18.10#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.07:20:18.10#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.07:20:18.10#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:18.10#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:20:18.16#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:20:18.16#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:20:18.18#ibcon#[25=AT08-06\r\n] 2006.134.07:20:18.21#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:20:18.21#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:20:18.21#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.07:20:18.21#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:18.21#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:20:18.33#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:20:18.33#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:20:18.35#ibcon#[25=USB\r\n] 2006.134.07:20:18.38#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:20:18.38#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:20:18.38#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:20:18.38#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:20:18.38$vc4f8/vblo=1,632.99 2006.134.07:20:18.38#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:20:18.38#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:20:18.38#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:18.38#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:18.38#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:18.38#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:18.40#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:20:18.44#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:18.44#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:20:18.44#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:20:18.44#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:20:18.44$vc4f8/vb=1,4 2006.134.07:20:18.44#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:20:18.44#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:20:18.44#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:18.44#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:18.44#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:18.44#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:18.46#ibcon#[27=AT01-04\r\n] 2006.134.07:20:18.49#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:18.49#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:20:18.49#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:20:18.49#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:18.49#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:18.61#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:18.61#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:18.63#ibcon#[27=USB\r\n] 2006.134.07:20:18.66#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:18.66#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:20:18.66#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:20:18.66#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:20:18.66$vc4f8/vblo=2,640.99 2006.134.07:20:18.66#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:20:18.66#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:20:18.66#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:18.66#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:18.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:18.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:18.68#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:20:18.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:18.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:20:18.72#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:20:18.72#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:20:18.72$vc4f8/vb=2,4 2006.134.07:20:18.72#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:20:18.72#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:20:18.72#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:18.72#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:18.78#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:18.78#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:18.80#ibcon#[27=AT02-04\r\n] 2006.134.07:20:18.83#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:18.83#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:20:18.83#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:20:18.83#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:18.83#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:18.95#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:18.95#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:18.97#ibcon#[27=USB\r\n] 2006.134.07:20:19.02#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:19.02#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:20:19.02#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:20:19.02#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:20:19.02$vc4f8/vblo=3,656.99 2006.134.07:20:19.02#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:20:19.02#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:20:19.02#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:19.02#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:19.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:19.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:19.03#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:20:19.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:19.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:20:19.07#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:20:19.07#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:20:19.07$vc4f8/vb=3,4 2006.134.07:20:19.07#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:20:19.07#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:20:19.07#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:19.07#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:19.14#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:19.14#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:19.16#ibcon#[27=AT03-04\r\n] 2006.134.07:20:19.19#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:19.19#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:20:19.19#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:20:19.19#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:19.19#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:19.31#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:19.31#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:19.33#ibcon#[27=USB\r\n] 2006.134.07:20:19.36#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:19.36#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:20:19.36#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:20:19.36#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:20:19.36$vc4f8/vblo=4,712.99 2006.134.07:20:19.36#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:20:19.36#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:20:19.36#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:19.36#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:19.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:19.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:19.38#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:20:19.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:19.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:20:19.42#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:20:19.42#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:20:19.42$vc4f8/vb=4,4 2006.134.07:20:19.42#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:20:19.42#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:20:19.42#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:19.42#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:19.48#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:19.48#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:19.50#ibcon#[27=AT04-04\r\n] 2006.134.07:20:19.53#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:19.53#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:20:19.53#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:20:19.53#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:19.53#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:19.65#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:19.65#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:19.67#ibcon#[27=USB\r\n] 2006.134.07:20:19.70#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:19.70#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:20:19.70#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:20:19.70#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:20:19.70$vc4f8/vblo=5,744.99 2006.134.07:20:19.70#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:20:19.70#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:20:19.70#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:19.70#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:19.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:19.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:19.72#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:20:19.76#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:19.76#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:20:19.76#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:20:19.76#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:20:19.76$vc4f8/vb=5,4 2006.134.07:20:19.76#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:20:19.76#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:20:19.76#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:19.76#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:19.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:19.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:19.84#ibcon#[27=AT05-04\r\n] 2006.134.07:20:19.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:19.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:20:19.87#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:20:19.87#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:19.87#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:19.99#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:19.99#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:20.01#ibcon#[27=USB\r\n] 2006.134.07:20:20.04#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:20.04#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:20:20.04#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:20:20.04#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:20:20.04$vc4f8/vblo=6,752.99 2006.134.07:20:20.04#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:20:20.04#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:20:20.04#ibcon#ireg 17 cls_cnt 0 2006.134.07:20:20.04#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:20.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:20.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:20.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:20:20.10#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:20.10#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:20:20.10#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:20:20.10#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:20:20.10$vc4f8/vb=6,4 2006.134.07:20:20.10#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:20:20.10#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:20:20.10#ibcon#ireg 11 cls_cnt 2 2006.134.07:20:20.10#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:20.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:20.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:20.18#ibcon#[27=AT06-04\r\n] 2006.134.07:20:20.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:20.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:20:20.21#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:20:20.21#ibcon#ireg 7 cls_cnt 0 2006.134.07:20:20.21#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:20.33#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:20.33#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:20.35#ibcon#[27=USB\r\n] 2006.134.07:20:20.38#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:20.38#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:20:20.38#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:20:20.38#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:20:20.38$vc4f8/vabw=wide 2006.134.07:20:20.38#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:20:20.38#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:20:20.38#ibcon#ireg 8 cls_cnt 0 2006.134.07:20:20.38#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:20:20.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:20:20.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:20:20.40#ibcon#[25=BW32\r\n] 2006.134.07:20:20.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:20:20.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:20:20.43#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:20:20.43#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:20:20.43$vc4f8/vbbw=wide 2006.134.07:20:20.43#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:20:20.43#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:20:20.43#ibcon#ireg 8 cls_cnt 0 2006.134.07:20:20.43#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:20:20.50#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:20:20.50#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:20:20.52#ibcon#[27=BW32\r\n] 2006.134.07:20:20.55#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:20:20.55#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:20:20.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:20:20.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:20:20.55$4f8m12a/ifd4f 2006.134.07:20:20.55&ifd4f/lo= 2006.134.07:20:20.55&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:20:20.55&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:20:20.55&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:20:20.55&ifd4f/patch= 2006.134.07:20:20.55&ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:20:20.55&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:20:20.55&ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:20:20.55$ifd4f/lo= 2006.134.07:20:20.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:20:20.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:20:20.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:20:20.55$ifd4f/patch= 2006.134.07:20:20.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:20:20.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:20:20.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:20:20.55$4f8m12a/"form=m,16.000,1:2 2006.134.07:20:20.55$4f8m12a/"tpicd 2006.134.07:20:20.55$4f8m12a/echo=off 2006.134.07:20:20.55$4f8m12a/xlog=off 2006.134.07:20:20.55:!2006.134.07:29:50 2006.134.07:20:41.14#trakl#Source acquired 2006.134.07:20:41.14#flagr#flagr/antenna,acquired 2006.134.07:29:50.00:preob 2006.134.07:29:50.00&preob/onsource 2006.134.07:29:51.14/onsource/TRACKING 2006.134.07:29:51.14:!2006.134.07:30:00 2006.134.07:30:00.00:data_valid=on 2006.134.07:30:00.00:midob 2006.134.07:30:00.00&midob/onsource 2006.134.07:30:00.00&midob/wx 2006.134.07:30:00.00&midob/cable 2006.134.07:30:00.00&midob/va 2006.134.07:30:00.00&midob/valo 2006.134.07:30:00.00&midob/vb 2006.134.07:30:00.00&midob/vblo 2006.134.07:30:00.00&midob/vabw 2006.134.07:30:00.00&midob/vbbw 2006.134.07:30:00.00&midob/"form 2006.134.07:30:00.00&midob/xfe 2006.134.07:30:00.00&midob/ifatt 2006.134.07:30:00.00&midob/clockoff 2006.134.07:30:00.00&midob/sy=logmail 2006.134.07:30:00.00&midob/"sy=run setcl adapt & 2006.134.07:30:00.14/onsource/TRACKING 2006.134.07:30:00.14/wx/19.40,1006.2,74 2006.134.07:30:00.22/cable/+6.5455E-03 2006.134.07:30:01.31/va/01,08,usb,yes,31,33 2006.134.07:30:01.31/va/02,07,usb,yes,31,32 2006.134.07:30:01.31/va/03,06,usb,yes,33,33 2006.134.07:30:01.31/va/04,07,usb,yes,32,34 2006.134.07:30:01.31/va/05,06,usb,yes,33,35 2006.134.07:30:01.31/va/06,05,usb,yes,33,33 2006.134.07:30:01.31/va/07,05,usb,yes,33,33 2006.134.07:30:01.31/va/08,06,usb,yes,31,30 2006.134.07:30:01.54/valo/01,532.99,yes,locked 2006.134.07:30:01.54/valo/02,572.99,yes,locked 2006.134.07:30:01.54/valo/03,672.99,yes,locked 2006.134.07:30:01.54/valo/04,832.99,yes,locked 2006.134.07:30:01.54/valo/05,652.99,yes,locked 2006.134.07:30:01.54/valo/06,772.99,yes,locked 2006.134.07:30:01.54/valo/07,832.99,yes,locked 2006.134.07:30:01.54/valo/08,852.99,yes,locked 2006.134.07:30:02.63/vb/01,04,usb,yes,29,37 2006.134.07:30:02.63/vb/02,04,usb,yes,31,41 2006.134.07:30:02.63/vb/03,04,usb,yes,28,32 2006.134.07:30:02.63/vb/04,04,usb,yes,28,29 2006.134.07:30:02.63/vb/05,04,usb,yes,27,31 2006.134.07:30:02.63/vb/06,04,usb,yes,28,31 2006.134.07:30:02.63/vb/07,04,usb,yes,30,30 2006.134.07:30:02.63/vb/08,04,usb,yes,28,31 2006.134.07:30:02.86/vblo/01,632.99,yes,locked 2006.134.07:30:02.86/vblo/02,640.99,yes,locked 2006.134.07:30:02.86/vblo/03,656.99,yes,locked 2006.134.07:30:02.86/vblo/04,712.99,yes,locked 2006.134.07:30:02.86/vblo/05,744.99,yes,locked 2006.134.07:30:02.86/vblo/06,752.99,yes,locked 2006.134.07:30:02.86/vblo/07,734.99,yes,locked 2006.134.07:30:02.86/vblo/08,744.99,yes,locked 2006.134.07:30:03.01/vabw/8 2006.134.07:30:03.16/vbbw/8 2006.134.07:30:03.25/xfe/off,on,15.0 2006.134.07:30:03.64/ifatt/23,28,28,28 2006.134.07:30:03.64&clockoff/"gps-fmout=1p 2006.134.07:30:03.64&clockoff/fmout-gps=1p 2006.134.07:30:04.07/fmout-gps/S +1.79E-07 2006.134.07:30:04.15:!2006.134.07:31:00 2006.134.07:31:00.00:data_valid=off 2006.134.07:31:00.00:postob 2006.134.07:31:00.00&postob/cable 2006.134.07:31:00.01&postob/wx 2006.134.07:31:00.01&postob/clockoff 2006.134.07:31:00.21/cable/+6.5460E-03 2006.134.07:31:00.21/wx/19.42,1006.2,75 2006.134.07:31:01.07/fmout-gps/S +1.79E-07 2006.134.07:31:01.07:scan_name=134-0733,k06134,60 2006.134.07:31:01.07:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.134.07:31:01.14#flagr#flagr/antenna,new-source 2006.134.07:31:02.14:checkk5 2006.134.07:31:02.14&checkk5/chk_autoobs=1 2006.134.07:31:02.14&checkk5/chk_autoobs=2 2006.134.07:31:02.15&checkk5/chk_autoobs=3 2006.134.07:31:02.15&checkk5/chk_autoobs=4 2006.134.07:31:02.15&checkk5/chk_obsdata=1 2006.134.07:31:02.16&checkk5/chk_obsdata=2 2006.134.07:31:02.16&checkk5/chk_obsdata=3 2006.134.07:31:02.16&checkk5/chk_obsdata=4 2006.134.07:31:02.17&checkk5/k5log=1 2006.134.07:31:02.17&checkk5/k5log=2 2006.134.07:31:02.17&checkk5/k5log=3 2006.134.07:31:02.18&checkk5/k5log=4 2006.134.07:31:02.18&checkk5/obsinfo 2006.134.07:31:02.59/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:31:02.97/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:31:03.34/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:31:03.72/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:31:04.09/chk_obsdata//k5ts1/T1340730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:31:04.46/chk_obsdata//k5ts2/T1340730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:31:04.82/chk_obsdata//k5ts3/T1340730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:31:05.19/chk_obsdata//k5ts4/T1340730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:31:05.90/k5log//k5ts1_log_newline 2006.134.07:31:06.58/k5log//k5ts2_log_newline 2006.134.07:31:07.26/k5log//k5ts3_log_newline 2006.134.07:31:07.95/k5log//k5ts4_log_newline 2006.134.07:31:07.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:31:07.97:4f8m12a=1 2006.134.07:31:07.97$4f8m12a/echo=on 2006.134.07:31:07.97$4f8m12a/pcalon 2006.134.07:31:07.97$pcalon/"no phase cal control is implemented here 2006.134.07:31:07.97$4f8m12a/"tpicd=stop 2006.134.07:31:07.97$4f8m12a/vc4f8 2006.134.07:31:07.97$vc4f8/valo=1,532.99 2006.134.07:31:07.98#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:31:07.98#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:31:07.98#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:07.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:07.98#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:07.98#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:08.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:31:08.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:08.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:08.07#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:31:08.07#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:31:08.07$vc4f8/va=1,8 2006.134.07:31:08.07#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:31:08.07#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:31:08.07#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:08.07#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:08.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:08.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:08.10#ibcon#[25=AT01-08\r\n] 2006.134.07:31:08.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:08.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:08.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:31:08.13#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:08.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:08.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:08.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:08.27#ibcon#[25=USB\r\n] 2006.134.07:31:08.31#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:08.31#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:08.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:31:08.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:31:08.31$vc4f8/valo=2,572.99 2006.134.07:31:08.31#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:31:08.31#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:31:08.31#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:08.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:08.31#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:08.31#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:08.33#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:31:08.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:08.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:08.37#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:31:08.37#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:31:08.37$vc4f8/va=2,7 2006.134.07:31:08.37#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:31:08.37#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:31:08.37#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:08.37#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:08.43#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:08.43#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:08.45#ibcon#[25=AT02-07\r\n] 2006.134.07:31:08.48#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:08.48#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:08.48#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:31:08.48#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:08.48#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:08.60#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:08.60#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:08.62#ibcon#[25=USB\r\n] 2006.134.07:31:08.66#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:08.66#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:08.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:31:08.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:31:08.66$vc4f8/valo=3,672.99 2006.134.07:31:08.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:31:08.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:31:08.66#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:08.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:08.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:08.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:08.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:31:08.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:08.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:08.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:31:08.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:31:08.72$vc4f8/va=3,6 2006.134.07:31:08.72#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:31:08.72#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:31:08.72#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:08.72#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:08.77#abcon#<5=/05 3.3 6.5 19.42 751006.2\r\n> 2006.134.07:31:08.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:08.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:08.79#abcon#{5=INTERFACE CLEAR} 2006.134.07:31:08.80#ibcon#[25=AT03-06\r\n] 2006.134.07:31:08.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:08.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:08.83#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:31:08.83#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:08.83#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:08.85#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:31:08.95#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:08.95#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:08.97#ibcon#[25=USB\r\n] 2006.134.07:31:09.00#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:09.00#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:09.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:31:09.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:31:09.00$vc4f8/valo=4,832.99 2006.134.07:31:09.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:31:09.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:31:09.00#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:09.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:09.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:09.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:09.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:31:09.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:09.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:09.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:31:09.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:31:09.06$vc4f8/va=4,7 2006.134.07:31:09.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:31:09.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:31:09.06#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:09.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:09.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:09.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:09.14#ibcon#[25=AT04-07\r\n] 2006.134.07:31:09.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:09.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:09.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:31:09.17#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:09.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:09.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:09.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:09.31#ibcon#[25=USB\r\n] 2006.134.07:31:09.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:09.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:09.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:31:09.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:31:09.34$vc4f8/valo=5,652.99 2006.134.07:31:09.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:31:09.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:31:09.34#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:09.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:09.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:09.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:09.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:31:09.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:09.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:09.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:31:09.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:31:09.40$vc4f8/va=5,6 2006.134.07:31:09.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:31:09.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:31:09.40#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:09.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:09.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:09.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:09.48#ibcon#[25=AT05-06\r\n] 2006.134.07:31:09.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:09.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:09.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:31:09.51#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:09.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:09.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:09.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:09.65#ibcon#[25=USB\r\n] 2006.134.07:31:09.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:09.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:09.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:31:09.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:31:09.68$vc4f8/valo=6,772.99 2006.134.07:31:09.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:31:09.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:31:09.68#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:09.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:09.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:09.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:09.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:31:09.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:09.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:09.74#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:31:09.74#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:31:09.74$vc4f8/va=6,5 2006.134.07:31:09.74#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:31:09.74#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:31:09.74#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:09.74#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:09.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:09.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:09.82#ibcon#[25=AT06-05\r\n] 2006.134.07:31:09.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:09.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:09.85#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:31:09.85#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:09.85#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:31:09.97#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:31:09.97#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:31:09.99#ibcon#[25=USB\r\n] 2006.134.07:31:10.02#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:31:10.02#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:31:10.02#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:31:10.02#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:31:10.02$vc4f8/valo=7,832.99 2006.134.07:31:10.02#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:31:10.02#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:31:10.02#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:10.02#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:31:10.02#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:31:10.02#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:31:10.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:31:10.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:31:10.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:31:10.08#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:31:10.08#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:31:10.08$vc4f8/va=7,5 2006.134.07:31:10.08#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:31:10.08#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:31:10.08#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:10.08#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:31:10.14#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:31:10.14#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:31:10.16#ibcon#[25=AT07-05\r\n] 2006.134.07:31:10.19#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:31:10.19#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:31:10.19#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:31:10.19#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:10.19#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:31:10.31#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:31:10.31#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:31:10.33#ibcon#[25=USB\r\n] 2006.134.07:31:10.36#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:31:10.36#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:31:10.36#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:31:10.36#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:31:10.36$vc4f8/valo=8,852.99 2006.134.07:31:10.36#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:31:10.36#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:31:10.36#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:10.36#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:31:10.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:31:10.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:31:10.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:31:10.42#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:31:10.42#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:31:10.42#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:31:10.42#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:31:10.42$vc4f8/va=8,6 2006.134.07:31:10.42#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:31:10.42#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:31:10.42#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:10.42#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:31:10.48#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:31:10.48#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:31:10.50#ibcon#[25=AT08-06\r\n] 2006.134.07:31:10.53#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:31:10.53#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:31:10.53#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:31:10.53#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:10.53#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:31:10.65#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:31:10.65#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:31:10.67#ibcon#[25=USB\r\n] 2006.134.07:31:10.70#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:31:10.70#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:31:10.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:31:10.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:31:10.70$vc4f8/vblo=1,632.99 2006.134.07:31:10.70#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:31:10.70#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:31:10.70#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:10.70#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:10.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:10.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:10.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:31:10.76#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:10.76#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:31:10.76#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:31:10.76#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:31:10.76$vc4f8/vb=1,4 2006.134.07:31:10.76#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:31:10.76#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:31:10.76#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:10.76#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:10.76#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:10.76#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:10.78#ibcon#[27=AT01-04\r\n] 2006.134.07:31:10.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:10.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:31:10.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:31:10.81#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:10.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:10.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:10.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:10.95#ibcon#[27=USB\r\n] 2006.134.07:31:10.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:10.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:31:10.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:31:10.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:31:10.98$vc4f8/vblo=2,640.99 2006.134.07:31:10.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:31:10.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:31:10.98#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:10.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:10.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:10.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:11.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:31:11.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:11.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:31:11.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:31:11.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:31:11.04$vc4f8/vb=2,4 2006.134.07:31:11.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:31:11.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:31:11.04#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:11.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:11.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:11.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:11.12#ibcon#[27=AT02-04\r\n] 2006.134.07:31:11.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:11.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:31:11.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:31:11.15#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:11.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:11.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:11.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:11.29#ibcon#[27=USB\r\n] 2006.134.07:31:11.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:11.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:31:11.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:31:11.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:31:11.32$vc4f8/vblo=3,656.99 2006.134.07:31:11.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:31:11.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:31:11.32#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:11.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:11.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:11.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:11.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:31:11.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:11.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:31:11.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:31:11.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:31:11.38$vc4f8/vb=3,4 2006.134.07:31:11.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:31:11.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:31:11.38#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:11.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:11.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:11.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:11.46#ibcon#[27=AT03-04\r\n] 2006.134.07:31:11.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:11.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:31:11.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:31:11.49#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:11.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:11.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:11.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:11.63#ibcon#[27=USB\r\n] 2006.134.07:31:11.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:11.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:31:11.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:31:11.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:31:11.66$vc4f8/vblo=4,712.99 2006.134.07:31:11.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:31:11.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:31:11.66#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:11.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:31:11.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:31:11.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:31:11.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:31:11.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:31:11.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:31:11.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:31:11.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:31:11.72$vc4f8/vb=4,4 2006.134.07:31:11.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.07:31:11.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.07:31:11.72#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:11.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:31:11.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:31:11.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:31:11.80#ibcon#[27=AT04-04\r\n] 2006.134.07:31:11.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:31:11.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:31:11.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.07:31:11.83#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:11.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:31:11.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:31:11.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:31:11.97#ibcon#[27=USB\r\n] 2006.134.07:31:12.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:31:12.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:31:12.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:31:12.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:31:12.00$vc4f8/vblo=5,744.99 2006.134.07:31:12.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:31:12.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:31:12.00#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:12.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:12.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:12.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:12.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:31:12.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:12.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:31:12.08#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:31:12.08#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:31:12.08$vc4f8/vb=5,4 2006.134.07:31:12.08#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:31:12.08#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:31:12.08#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:12.08#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:12.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:12.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:12.14#ibcon#[27=AT05-04\r\n] 2006.134.07:31:12.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:12.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:31:12.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:31:12.17#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:12.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:12.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:12.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:12.31#ibcon#[27=USB\r\n] 2006.134.07:31:12.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:12.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:31:12.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:31:12.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:31:12.34$vc4f8/vblo=6,752.99 2006.134.07:31:12.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:31:12.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:31:12.34#ibcon#ireg 17 cls_cnt 0 2006.134.07:31:12.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:12.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:12.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:12.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:31:12.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:12.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:31:12.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:31:12.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:31:12.40$vc4f8/vb=6,4 2006.134.07:31:12.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:31:12.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:31:12.40#ibcon#ireg 11 cls_cnt 2 2006.134.07:31:12.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:12.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:12.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:12.48#ibcon#[27=AT06-04\r\n] 2006.134.07:31:12.51#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:12.51#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:31:12.51#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:31:12.51#ibcon#ireg 7 cls_cnt 0 2006.134.07:31:12.51#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:12.63#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:12.63#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:12.65#ibcon#[27=USB\r\n] 2006.134.07:31:12.68#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:12.68#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:31:12.68#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:31:12.68#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:31:12.68$vc4f8/vabw=wide 2006.134.07:31:12.68#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:31:12.68#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:31:12.68#ibcon#ireg 8 cls_cnt 0 2006.134.07:31:12.68#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:12.68#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:12.68#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:12.70#ibcon#[25=BW32\r\n] 2006.134.07:31:12.73#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:12.73#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:31:12.73#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:31:12.73#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:31:12.73$vc4f8/vbbw=wide 2006.134.07:31:12.73#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:31:12.73#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:31:12.73#ibcon#ireg 8 cls_cnt 0 2006.134.07:31:12.73#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:31:12.80#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:31:12.80#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:31:12.82#ibcon#[27=BW32\r\n] 2006.134.07:31:12.85#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:31:12.85#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:31:12.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:31:12.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:31:12.85$4f8m12a/ifd4f 2006.134.07:31:12.85$ifd4f/lo= 2006.134.07:31:12.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:31:12.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:31:12.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:31:12.85$ifd4f/patch= 2006.134.07:31:12.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:31:12.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:31:12.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:31:12.85$4f8m12a/"form=m,16.000,1:2 2006.134.07:31:12.85$4f8m12a/"tpicd 2006.134.07:31:12.85$4f8m12a/echo=off 2006.134.07:31:12.85$4f8m12a/xlog=off 2006.134.07:31:12.85:!2006.134.07:33:20 2006.134.07:31:48.14#trakl#Source acquired 2006.134.07:31:49.14#flagr#flagr/antenna,acquired 2006.134.07:33:20.00:preob 2006.134.07:33:20.13/onsource/TRACKING 2006.134.07:33:20.13:!2006.134.07:33:30 2006.134.07:33:30.00:data_valid=on 2006.134.07:33:30.00:midob 2006.134.07:33:31.13/onsource/TRACKING 2006.134.07:33:31.13/wx/19.46,1006.3,77 2006.134.07:33:31.29/cable/+6.5458E-03 2006.134.07:33:32.38/va/01,08,usb,yes,32,34 2006.134.07:33:32.38/va/02,07,usb,yes,32,34 2006.134.07:33:32.38/va/03,06,usb,yes,34,34 2006.134.07:33:32.38/va/04,07,usb,yes,33,35 2006.134.07:33:32.38/va/05,06,usb,yes,34,36 2006.134.07:33:32.38/va/06,05,usb,yes,35,34 2006.134.07:33:32.38/va/07,05,usb,yes,35,34 2006.134.07:33:32.38/va/08,06,usb,yes,32,32 2006.134.07:33:32.61/valo/01,532.99,yes,locked 2006.134.07:33:32.61/valo/02,572.99,yes,locked 2006.134.07:33:32.61/valo/03,672.99,yes,locked 2006.134.07:33:32.61/valo/04,832.99,yes,locked 2006.134.07:33:32.61/valo/05,652.99,yes,locked 2006.134.07:33:32.61/valo/06,772.99,yes,locked 2006.134.07:33:32.61/valo/07,832.99,yes,locked 2006.134.07:33:32.61/valo/08,852.99,yes,locked 2006.134.07:33:33.70/vb/01,04,usb,yes,29,28 2006.134.07:33:33.70/vb/02,04,usb,yes,31,32 2006.134.07:33:33.70/vb/03,04,usb,yes,27,31 2006.134.07:33:33.70/vb/04,04,usb,yes,28,28 2006.134.07:33:33.70/vb/05,04,usb,yes,27,31 2006.134.07:33:33.70/vb/06,04,usb,yes,28,30 2006.134.07:33:33.70/vb/07,04,usb,yes,30,30 2006.134.07:33:33.70/vb/08,04,usb,yes,27,31 2006.134.07:33:33.93/vblo/01,632.99,yes,locked 2006.134.07:33:33.93/vblo/02,640.99,yes,locked 2006.134.07:33:33.93/vblo/03,656.99,yes,locked 2006.134.07:33:33.93/vblo/04,712.99,yes,locked 2006.134.07:33:33.93/vblo/05,744.99,yes,locked 2006.134.07:33:33.93/vblo/06,752.99,yes,locked 2006.134.07:33:33.93/vblo/07,734.99,yes,locked 2006.134.07:33:33.93/vblo/08,744.99,yes,locked 2006.134.07:33:34.08/vabw/8 2006.134.07:33:34.23/vbbw/8 2006.134.07:33:34.32/xfe/off,on,16.0 2006.134.07:33:34.69/ifatt/23,28,28,28 2006.134.07:33:35.08/fmout-gps/S +1.79E-07 2006.134.07:33:35.12:!2006.134.07:34:30 2006.134.07:34:30.00:data_valid=off 2006.134.07:34:30.00:postob 2006.134.07:34:30.22/cable/+6.5479E-03 2006.134.07:34:30.22/wx/19.48,1006.3,76 2006.134.07:34:31.08/fmout-gps/S +1.80E-07 2006.134.07:34:31.08:scan_name=134-0735,k06134,60 2006.134.07:34:31.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.134.07:34:31.14#flagr#flagr/antenna,new-source 2006.134.07:34:32.14:checkk5 2006.134.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:34:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:34:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:34:34.00/chk_obsdata//k5ts1/T1340733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:34:34.36/chk_obsdata//k5ts2/T1340733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:34:34.72/chk_obsdata//k5ts3/T1340733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:34:35.09/chk_obsdata//k5ts4/T1340733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:34:35.78/k5log//k5ts1_log_newline 2006.134.07:34:36.47/k5log//k5ts2_log_newline 2006.134.07:34:37.15/k5log//k5ts3_log_newline 2006.134.07:34:37.84/k5log//k5ts4_log_newline 2006.134.07:34:37.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:34:37.86:4f8m12a=1 2006.134.07:34:37.86$4f8m12a/echo=on 2006.134.07:34:37.86$4f8m12a/pcalon 2006.134.07:34:37.86$pcalon/"no phase cal control is implemented here 2006.134.07:34:37.86$4f8m12a/"tpicd=stop 2006.134.07:34:37.86$4f8m12a/vc4f8 2006.134.07:34:37.86$vc4f8/valo=1,532.99 2006.134.07:34:37.87#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:34:37.87#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:34:37.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:37.87#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:37.87#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:37.87#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:34:37.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:37.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:37.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:34:37.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:34:37.96$vc4f8/va=1,8 2006.134.07:34:37.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.07:34:37.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.07:34:37.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:37.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:37.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:37.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:37.99#ibcon#[25=AT01-08\r\n] 2006.134.07:34:38.02#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:38.02#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:38.02#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.07:34:38.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:38.02#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:38.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:38.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:38.16#ibcon#[25=USB\r\n] 2006.134.07:34:38.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:38.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:38.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:34:38.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:34:38.19$vc4f8/valo=2,572.99 2006.134.07:34:38.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.07:34:38.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.07:34:38.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:38.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:38.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:38.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:34:38.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:38.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:38.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:34:38.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:34:38.26$vc4f8/va=2,7 2006.134.07:34:38.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.07:34:38.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.07:34:38.26#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:38.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:38.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:38.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:38.33#ibcon#[25=AT02-07\r\n] 2006.134.07:34:38.36#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:38.36#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:38.36#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.07:34:38.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:38.36#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:38.48#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:38.48#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:38.50#ibcon#[25=USB\r\n] 2006.134.07:34:38.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:38.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:38.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:34:38.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:34:38.54$vc4f8/valo=3,672.99 2006.134.07:34:38.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.07:34:38.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.07:34:38.54#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:38.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:38.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:38.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:34:38.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:38.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:38.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:34:38.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:34:38.60$vc4f8/va=3,6 2006.134.07:34:38.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.07:34:38.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.07:34:38.60#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:38.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:38.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:38.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:38.68#ibcon#[25=AT03-06\r\n] 2006.134.07:34:38.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:38.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:38.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.07:34:38.71#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:38.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:38.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:38.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:38.85#ibcon#[25=USB\r\n] 2006.134.07:34:38.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:38.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:38.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:34:38.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:34:38.88$vc4f8/valo=4,832.99 2006.134.07:34:38.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.07:34:38.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.07:34:38.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:38.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:38.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:38.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:34:38.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:38.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:38.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:34:38.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:34:38.94$vc4f8/va=4,7 2006.134.07:34:38.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.07:34:38.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.07:34:38.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:38.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:39.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:39.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:39.02#ibcon#[25=AT04-07\r\n] 2006.134.07:34:39.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:39.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:39.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.07:34:39.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:39.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:39.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:39.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:39.19#ibcon#[25=USB\r\n] 2006.134.07:34:39.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:39.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:39.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:34:39.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:34:39.22$vc4f8/valo=5,652.99 2006.134.07:34:39.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:34:39.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:34:39.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:39.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:39.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:39.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:34:39.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:39.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:39.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:34:39.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:34:39.28$vc4f8/va=5,6 2006.134.07:34:39.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.07:34:39.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.07:34:39.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:39.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:39.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:39.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:39.36#ibcon#[25=AT05-06\r\n] 2006.134.07:34:39.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:39.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:39.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.07:34:39.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:39.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:39.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:39.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:39.53#ibcon#[25=USB\r\n] 2006.134.07:34:39.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:39.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:39.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:34:39.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:34:39.56$vc4f8/valo=6,772.99 2006.134.07:34:39.56#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.07:34:39.56#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.07:34:39.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:39.56#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:34:39.56#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:34:39.56#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:34:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:34:39.62#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:34:39.62#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:34:39.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:34:39.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:34:39.62$vc4f8/va=6,5 2006.134.07:34:39.62#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.07:34:39.62#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.07:34:39.62#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:39.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:34:39.68#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:34:39.68#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:34:39.70#ibcon#[25=AT06-05\r\n] 2006.134.07:34:39.73#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:34:39.73#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:34:39.73#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.07:34:39.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:39.73#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:34:39.85#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:34:39.85#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:34:39.87#ibcon#[25=USB\r\n] 2006.134.07:34:39.90#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:34:39.90#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:34:39.90#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:34:39.90#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:34:39.90$vc4f8/valo=7,832.99 2006.134.07:34:39.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:34:39.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:34:39.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:39.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:39.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:39.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:34:39.96#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:39.96#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:39.96#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:34:39.96#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:34:39.96$vc4f8/va=7,5 2006.134.07:34:39.96#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.07:34:39.96#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.07:34:39.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:39.96#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:40.02#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:40.02#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:40.04#ibcon#[25=AT07-05\r\n] 2006.134.07:34:40.07#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:40.07#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:40.07#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.07:34:40.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:40.07#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:34:40.19#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:34:40.19#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:34:40.21#ibcon#[25=USB\r\n] 2006.134.07:34:40.24#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:34:40.24#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:34:40.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:34:40.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:34:40.24$vc4f8/valo=8,852.99 2006.134.07:34:40.24#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.07:34:40.24#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.07:34:40.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:40.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:34:40.24#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:34:40.24#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:34:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:34:40.30#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:34:40.30#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:34:40.30#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:34:40.30#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:34:40.30$vc4f8/va=8,6 2006.134.07:34:40.30#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.07:34:40.30#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.07:34:40.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:40.30#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:34:40.36#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:34:40.36#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:34:40.38#ibcon#[25=AT08-06\r\n] 2006.134.07:34:40.41#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:34:40.41#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:34:40.41#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.07:34:40.41#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:40.41#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:34:40.53#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:34:40.53#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:34:40.55#ibcon#[25=USB\r\n] 2006.134.07:34:40.58#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:34:40.58#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:34:40.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:34:40.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:34:40.58$vc4f8/vblo=1,632.99 2006.134.07:34:40.58#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:34:40.58#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:34:40.58#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:40.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:34:40.58#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:34:40.58#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:34:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:34:40.64#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:34:40.64#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:34:40.64#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:34:40.64#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:34:40.64$vc4f8/vb=1,4 2006.134.07:34:40.64#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.07:34:40.64#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.07:34:40.64#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:40.64#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:34:40.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:34:40.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:34:40.66#ibcon#[27=AT01-04\r\n] 2006.134.07:34:40.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:34:40.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:34:40.69#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.07:34:40.69#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:40.69#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:34:40.81#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:34:40.81#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:34:40.83#ibcon#[27=USB\r\n] 2006.134.07:34:40.86#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:34:40.86#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:34:40.86#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:34:40.86#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:34:40.86$vc4f8/vblo=2,640.99 2006.134.07:34:40.86#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:34:40.86#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:34:40.86#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:40.86#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:40.86#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:40.86#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:34:40.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:40.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:34:40.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:34:40.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:34:40.92$vc4f8/vb=2,4 2006.134.07:34:40.92#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.07:34:40.92#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.07:34:40.92#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:40.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:40.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:40.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:41.00#ibcon#[27=AT02-04\r\n] 2006.134.07:34:41.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:41.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:34:41.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.07:34:41.03#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:41.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:41.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:41.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:41.17#ibcon#[27=USB\r\n] 2006.134.07:34:41.20#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:41.20#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:34:41.20#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:34:41.20#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:34:41.20$vc4f8/vblo=3,656.99 2006.134.07:34:41.20#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.07:34:41.20#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.07:34:41.20#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:41.20#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:41.20#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:41.20#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:41.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:34:41.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:41.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:34:41.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:34:41.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:34:41.28$vc4f8/vb=3,4 2006.134.07:34:41.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.07:34:41.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.07:34:41.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:41.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:41.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:41.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:41.34#ibcon#[27=AT03-04\r\n] 2006.134.07:34:41.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:41.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:34:41.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.07:34:41.37#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:41.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:41.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:41.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:41.51#ibcon#[27=USB\r\n] 2006.134.07:34:41.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:41.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:34:41.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:34:41.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:34:41.54$vc4f8/vblo=4,712.99 2006.134.07:34:41.54#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.07:34:41.54#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.07:34:41.54#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:41.54#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:41.54#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:41.54#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:34:41.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:41.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:34:41.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:34:41.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:34:41.60$vc4f8/vb=4,4 2006.134.07:34:41.60#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.07:34:41.60#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.07:34:41.60#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:41.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:41.66#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:41.66#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.134.07:34:41.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:41.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:34:41.71#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:41.71#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:41.83#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:41.83#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:41.85#ibcon#[27=USB\r\n] 2006.134.07:34:41.88#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:41.88#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:34:41.88#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:34:41.88#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:34:41.88$vc4f8/vblo=5,744.99 2006.134.07:34:41.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.07:34:41.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.07:34:41.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:41.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:41.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:41.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:34:41.94#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:41.94#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:34:41.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:34:41.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:34:41.94$vc4f8/vb=5,4 2006.134.07:34:41.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.07:34:41.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.07:34:41.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:41.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:42.00#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:42.00#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:42.02#ibcon#[27=AT05-04\r\n] 2006.134.07:34:42.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:42.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:34:42.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.07:34:42.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:42.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:42.17#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:42.17#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:42.19#ibcon#[27=USB\r\n] 2006.134.07:34:42.22#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:42.22#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:34:42.22#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:34:42.22#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:34:42.22$vc4f8/vblo=6,752.99 2006.134.07:34:42.22#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:34:42.22#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:34:42.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:34:42.22#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:42.22#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:42.22#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:34:42.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:42.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:34:42.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:34:42.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:34:42.28$vc4f8/vb=6,4 2006.134.07:34:42.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.07:34:42.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.07:34:42.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:34:42.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:42.34#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:42.34#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:42.36#ibcon#[27=AT06-04\r\n] 2006.134.07:34:42.39#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:42.39#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:34:42.39#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.07:34:42.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:34:42.39#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:42.48#abcon#<5=/04 3.0 4.9 19.48 761006.3\r\n> 2006.134.07:34:42.50#abcon#{5=INTERFACE CLEAR} 2006.134.07:34:42.51#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:42.51#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:42.53#ibcon#[27=USB\r\n] 2006.134.07:34:42.56#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:34:42.56#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:42.56#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:34:42.56#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:34:42.56#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:34:42.56$vc4f8/vabw=wide 2006.134.07:34:42.56#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:34:42.56#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:34:42.56#ibcon#ireg 8 cls_cnt 0 2006.134.07:34:42.56#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:42.56#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:42.56#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:42.58#ibcon#[25=BW32\r\n] 2006.134.07:34:42.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:42.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:34:42.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:34:42.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:34:42.61$vc4f8/vbbw=wide 2006.134.07:34:42.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:34:42.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:34:42.61#ibcon#ireg 8 cls_cnt 0 2006.134.07:34:42.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:34:42.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:34:42.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:34:42.70#ibcon#[27=BW32\r\n] 2006.134.07:34:42.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:34:42.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:34:42.73#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:34:42.73#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:34:42.73$4f8m12a/ifd4f 2006.134.07:34:42.73$ifd4f/lo= 2006.134.07:34:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:34:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:34:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:34:42.73$ifd4f/patch= 2006.134.07:34:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:34:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:34:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:34:42.73$4f8m12a/"form=m,16.000,1:2 2006.134.07:34:42.73$4f8m12a/"tpicd 2006.134.07:34:42.73$4f8m12a/echo=off 2006.134.07:34:42.73$4f8m12a/xlog=off 2006.134.07:34:42.73:!2006.134.07:35:10 2006.134.07:34:53.14#trakl#Source acquired 2006.134.07:34:55.14#flagr#flagr/antenna,acquired 2006.134.07:35:10.00:preob 2006.134.07:35:11.14/onsource/TRACKING 2006.134.07:35:11.14:!2006.134.07:35:20 2006.134.07:35:20.00:data_valid=on 2006.134.07:35:20.00:midob 2006.134.07:35:20.14/onsource/TRACKING 2006.134.07:35:20.14/wx/19.48,1006.3,76 2006.134.07:35:20.33/cable/+6.5503E-03 2006.134.07:35:21.42/va/01,08,usb,yes,29,31 2006.134.07:35:21.42/va/02,07,usb,yes,29,30 2006.134.07:35:21.42/va/03,06,usb,yes,30,31 2006.134.07:35:21.42/va/04,07,usb,yes,30,32 2006.134.07:35:21.42/va/05,06,usb,yes,31,33 2006.134.07:35:21.42/va/06,05,usb,yes,31,31 2006.134.07:35:21.42/va/07,05,usb,yes,31,31 2006.134.07:35:21.42/va/08,06,usb,yes,29,28 2006.134.07:35:21.65/valo/01,532.99,yes,locked 2006.134.07:35:21.65/valo/02,572.99,yes,locked 2006.134.07:35:21.65/valo/03,672.99,yes,locked 2006.134.07:35:21.65/valo/04,832.99,yes,locked 2006.134.07:35:21.65/valo/05,652.99,yes,locked 2006.134.07:35:21.65/valo/06,772.99,yes,locked 2006.134.07:35:21.65/valo/07,832.99,yes,locked 2006.134.07:35:21.65/valo/08,852.99,yes,locked 2006.134.07:35:22.74/vb/01,04,usb,yes,28,27 2006.134.07:35:22.74/vb/02,04,usb,yes,30,32 2006.134.07:35:22.74/vb/03,04,usb,yes,27,30 2006.134.07:35:22.74/vb/04,04,usb,yes,28,28 2006.134.07:35:22.74/vb/05,04,usb,yes,26,30 2006.134.07:35:22.74/vb/06,04,usb,yes,27,30 2006.134.07:35:22.74/vb/07,04,usb,yes,29,29 2006.134.07:35:22.74/vb/08,04,usb,yes,27,30 2006.134.07:35:22.97/vblo/01,632.99,yes,locked 2006.134.07:35:22.97/vblo/02,640.99,yes,locked 2006.134.07:35:22.97/vblo/03,656.99,yes,locked 2006.134.07:35:22.97/vblo/04,712.99,yes,locked 2006.134.07:35:22.97/vblo/05,744.99,yes,locked 2006.134.07:35:22.97/vblo/06,752.99,yes,locked 2006.134.07:35:22.97/vblo/07,734.99,yes,locked 2006.134.07:35:22.97/vblo/08,744.99,yes,locked 2006.134.07:35:23.12/vabw/8 2006.134.07:35:23.27/vbbw/8 2006.134.07:35:23.36/xfe/off,on,14.7 2006.134.07:35:23.73/ifatt/23,28,28,28 2006.134.07:35:24.08/fmout-gps/S +1.79E-07 2006.134.07:35:24.12:!2006.134.07:36:20 2006.134.07:36:20.02:data_valid=off 2006.134.07:36:20.02:postob 2006.134.07:36:20.09/cable/+6.5464E-03 2006.134.07:36:20.09/wx/19.48,1006.3,76 2006.134.07:36:20.15/fmout-gps/S +1.79E-07 2006.134.07:36:20.15:scan_name=134-0737,k06134,60 2006.134.07:36:20.15:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.134.07:36:21.13#flagr#flagr/antenna,new-source 2006.134.07:36:21.15:checkk5 2006.134.07:36:21.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:36:21.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:36:22.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:36:22.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:36:23.00/chk_obsdata//k5ts1/T1340735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:36:23.37/chk_obsdata//k5ts2/T1340735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:36:23.73/chk_obsdata//k5ts3/T1340735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:36:24.10/chk_obsdata//k5ts4/T1340735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:36:24.79/k5log//k5ts1_log_newline 2006.134.07:36:25.48/k5log//k5ts2_log_newline 2006.134.07:36:26.16/k5log//k5ts3_log_newline 2006.134.07:36:26.85/k5log//k5ts4_log_newline 2006.134.07:36:26.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:36:26.87:4f8m12a=1 2006.134.07:36:26.87$4f8m12a/echo=on 2006.134.07:36:26.87$4f8m12a/pcalon 2006.134.07:36:26.87$pcalon/"no phase cal control is implemented here 2006.134.07:36:26.87$4f8m12a/"tpicd=stop 2006.134.07:36:26.87$4f8m12a/vc4f8 2006.134.07:36:26.87$vc4f8/valo=1,532.99 2006.134.07:36:26.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:36:26.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:36:26.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:26.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:26.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:26.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:26.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:36:26.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:26.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:26.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:36:26.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:36:26.97$vc4f8/va=1,8 2006.134.07:36:26.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.07:36:26.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.07:36:26.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:26.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:26.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:26.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:27.00#ibcon#[25=AT01-08\r\n] 2006.134.07:36:27.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:27.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:27.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.07:36:27.03#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:27.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:27.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:27.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:27.15#ibcon#[25=USB\r\n] 2006.134.07:36:27.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:27.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:27.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:36:27.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:36:27.19$vc4f8/valo=2,572.99 2006.134.07:36:27.19#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:36:27.19#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:36:27.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:27.19#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:27.19#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:27.19#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:27.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:36:27.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:27.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:27.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:36:27.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:36:27.26$vc4f8/va=2,7 2006.134.07:36:27.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.07:36:27.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.07:36:27.26#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:27.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:27.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:27.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:27.31#ibcon#[25=AT02-07\r\n] 2006.134.07:36:27.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:27.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:27.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.07:36:27.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:27.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:27.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:27.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:27.48#ibcon#[25=USB\r\n] 2006.134.07:36:27.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:27.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:27.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:36:27.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:36:27.52$vc4f8/valo=3,672.99 2006.134.07:36:27.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.07:36:27.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.07:36:27.52#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:27.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:27.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:27.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:27.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:36:27.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:27.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:27.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:36:27.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:36:27.59$vc4f8/va=3,6 2006.134.07:36:27.59#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.07:36:27.59#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.07:36:27.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:27.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:27.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:27.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:27.64#ibcon#[25=AT03-06\r\n] 2006.134.07:36:27.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:27.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:27.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.07:36:27.67#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:27.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:27.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:27.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:27.81#ibcon#[25=USB\r\n] 2006.134.07:36:27.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:27.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:27.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:36:27.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:36:27.85$vc4f8/valo=4,832.99 2006.134.07:36:27.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.07:36:27.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.07:36:27.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:27.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:27.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:27.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:27.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:36:27.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:27.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:27.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:36:27.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:36:27.91$vc4f8/va=4,7 2006.134.07:36:27.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.07:36:27.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.07:36:27.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:27.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:27.95#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:27.95#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:27.97#ibcon#[25=AT04-07\r\n] 2006.134.07:36:28.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:28.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:28.00#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.07:36:28.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:28.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:28.12#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:28.12#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:28.14#ibcon#[25=USB\r\n] 2006.134.07:36:28.17#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:28.17#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:28.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:36:28.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:36:28.18$vc4f8/valo=5,652.99 2006.134.07:36:28.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:36:28.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:36:28.18#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:28.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:28.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:28.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:28.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:36:28.23#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:28.23#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:28.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:36:28.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:36:28.24$vc4f8/va=5,6 2006.134.07:36:28.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.07:36:28.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.07:36:28.24#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:28.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:28.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:28.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:28.30#ibcon#[25=AT05-06\r\n] 2006.134.07:36:28.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:28.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:28.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.07:36:28.33#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:28.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:28.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:28.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:28.47#ibcon#[25=USB\r\n] 2006.134.07:36:28.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:28.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:28.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:36:28.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:36:28.51$vc4f8/valo=6,772.99 2006.134.07:36:28.51#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:36:28.51#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:36:28.51#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:28.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:28.51#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:28.51#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:28.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:36:28.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:28.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:28.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:36:28.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:36:28.57$vc4f8/va=6,5 2006.134.07:36:28.57#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.07:36:28.57#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.07:36:28.57#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:28.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:28.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:28.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:28.63#ibcon#[25=AT06-05\r\n] 2006.134.07:36:28.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:28.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:28.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.07:36:28.66#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:28.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:36:28.78#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:36:28.78#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:36:28.80#ibcon#[25=USB\r\n] 2006.134.07:36:28.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:36:28.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:36:28.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:36:28.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:36:28.84$vc4f8/valo=7,832.99 2006.134.07:36:28.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.07:36:28.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.07:36:28.84#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:28.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:36:28.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:36:28.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:36:28.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:36:28.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:36:28.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:36:28.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:36:28.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:36:28.90$vc4f8/va=7,5 2006.134.07:36:28.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.07:36:28.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.07:36:28.90#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:28.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:36:28.94#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:36:28.94#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:36:28.96#ibcon#[25=AT07-05\r\n] 2006.134.07:36:28.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:36:28.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:36:28.99#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.07:36:28.99#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:28.99#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:36:29.11#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:36:29.11#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:36:29.13#ibcon#[25=USB\r\n] 2006.134.07:36:29.16#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:36:29.16#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:36:29.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:36:29.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:36:29.17$vc4f8/valo=8,852.99 2006.134.07:36:29.17#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:36:29.17#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:36:29.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:29.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:36:29.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:36:29.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:36:29.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:36:29.22#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:36:29.22#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:36:29.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:36:29.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:36:29.23$vc4f8/va=8,6 2006.134.07:36:29.23#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.07:36:29.23#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.07:36:29.23#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:29.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:36:29.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:36:29.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:36:29.29#ibcon#[25=AT08-06\r\n] 2006.134.07:36:29.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:36:29.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:36:29.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.07:36:29.32#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:29.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:36:29.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:36:29.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:36:29.46#ibcon#[25=USB\r\n] 2006.134.07:36:29.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:36:29.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:36:29.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:36:29.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:36:29.50$vc4f8/vblo=1,632.99 2006.134.07:36:29.50#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.07:36:29.50#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.07:36:29.50#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:29.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:36:29.50#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:36:29.50#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:36:29.51#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:36:29.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:36:29.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:36:29.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:36:29.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:36:29.56$vc4f8/vb=1,4 2006.134.07:36:29.56#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.07:36:29.56#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.07:36:29.56#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:29.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:36:29.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:36:29.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:36:29.57#ibcon#[27=AT01-04\r\n] 2006.134.07:36:29.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:36:29.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:36:29.60#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.07:36:29.60#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:29.60#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:36:29.72#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:36:29.72#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:36:29.74#ibcon#[27=USB\r\n] 2006.134.07:36:29.77#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:36:29.77#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:36:29.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:36:29.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:36:29.78$vc4f8/vblo=2,640.99 2006.134.07:36:29.78#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:36:29.78#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:36:29.78#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:29.78#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:29.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:29.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:29.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:36:29.84#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:29.84#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:36:29.84#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:36:29.84#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:36:29.85$vc4f8/vb=2,4 2006.134.07:36:29.85#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.07:36:29.85#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.07:36:29.85#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:29.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:29.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:29.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:29.90#ibcon#[27=AT02-04\r\n] 2006.134.07:36:29.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:29.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:36:29.93#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.07:36:29.93#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:29.93#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:30.05#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:30.05#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:30.07#ibcon#[27=USB\r\n] 2006.134.07:36:30.10#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:30.10#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:36:30.10#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:36:30.10#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:36:30.11$vc4f8/vblo=3,656.99 2006.134.07:36:30.11#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:36:30.11#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:36:30.11#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:30.11#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:30.11#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:30.11#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:30.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:36:30.16#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:30.16#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:36:30.16#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:36:30.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:36:30.17$vc4f8/vb=3,4 2006.134.07:36:30.17#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.07:36:30.17#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.07:36:30.17#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:30.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:30.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:30.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:30.23#ibcon#[27=AT03-04\r\n] 2006.134.07:36:30.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:30.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:36:30.26#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.07:36:30.26#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:30.26#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:30.38#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:30.38#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:30.40#ibcon#[27=USB\r\n] 2006.134.07:36:30.43#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:30.43#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:36:30.43#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:36:30.43#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:36:30.44$vc4f8/vblo=4,712.99 2006.134.07:36:30.44#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.07:36:30.44#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.07:36:30.44#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:30.44#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:30.44#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:30.44#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:30.45#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:36:30.49#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:30.49#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:36:30.49#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:36:30.49#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:36:30.50$vc4f8/vb=4,4 2006.134.07:36:30.50#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.07:36:30.50#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.07:36:30.50#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:30.50#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:30.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:30.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:30.56#ibcon#[27=AT04-04\r\n] 2006.134.07:36:30.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:30.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:36:30.61#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.07:36:30.61#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:30.61#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:30.72#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:30.72#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:30.74#ibcon#[27=USB\r\n] 2006.134.07:36:30.77#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:30.77#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:36:30.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:36:30.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:36:30.78$vc4f8/vblo=5,744.99 2006.134.07:36:30.78#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.07:36:30.78#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.07:36:30.78#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:30.78#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:30.78#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:30.78#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:30.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:36:30.83#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:30.83#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:36:30.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:36:30.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:36:30.84$vc4f8/vb=5,4 2006.134.07:36:30.84#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.07:36:30.84#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.07:36:30.84#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:30.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:30.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:30.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:30.90#ibcon#[27=AT05-04\r\n] 2006.134.07:36:30.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:30.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:36:30.93#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.07:36:30.93#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:30.93#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:31.05#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:31.05#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:31.07#ibcon#[27=USB\r\n] 2006.134.07:36:31.10#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:31.10#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:36:31.10#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:36:31.11#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:36:31.11$vc4f8/vblo=6,752.99 2006.134.07:36:31.11#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:36:31.11#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:36:31.11#ibcon#ireg 17 cls_cnt 0 2006.134.07:36:31.11#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:31.11#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:31.11#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:31.12#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:36:31.16#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:31.16#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:36:31.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:36:31.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:36:31.17$vc4f8/vb=6,4 2006.134.07:36:31.17#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.07:36:31.17#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.07:36:31.17#ibcon#ireg 11 cls_cnt 2 2006.134.07:36:31.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:31.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:31.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:31.23#ibcon#[27=AT06-04\r\n] 2006.134.07:36:31.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:31.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:36:31.26#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.07:36:31.26#ibcon#ireg 7 cls_cnt 0 2006.134.07:36:31.26#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:31.38#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:31.38#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:31.40#ibcon#[27=USB\r\n] 2006.134.07:36:31.43#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:31.43#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:36:31.43#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:36:31.43#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:36:31.44$vc4f8/vabw=wide 2006.134.07:36:31.44#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:36:31.44#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:36:31.44#ibcon#ireg 8 cls_cnt 0 2006.134.07:36:31.44#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:31.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:31.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:31.45#ibcon#[25=BW32\r\n] 2006.134.07:36:31.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:31.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:36:31.48#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:36:31.48#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:36:31.49$vc4f8/vbbw=wide 2006.134.07:36:31.49#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:36:31.49#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:36:31.49#ibcon#ireg 8 cls_cnt 0 2006.134.07:36:31.49#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:36:31.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:36:31.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:36:31.56#ibcon#[27=BW32\r\n] 2006.134.07:36:31.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:36:31.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:36:31.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:36:31.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:36:31.60$4f8m12a/ifd4f 2006.134.07:36:31.60$ifd4f/lo= 2006.134.07:36:31.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:36:31.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:36:31.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:36:31.60$ifd4f/patch= 2006.134.07:36:31.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:36:31.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:36:31.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:36:31.60$4f8m12a/"form=m,16.000,1:2 2006.134.07:36:31.60$4f8m12a/"tpicd 2006.134.07:36:31.60$4f8m12a/echo=off 2006.134.07:36:31.60$4f8m12a/xlog=off 2006.134.07:36:31.60:!2006.134.07:37:00 2006.134.07:36:42.14#trakl#Source acquired 2006.134.07:36:44.15#flagr#flagr/antenna,acquired 2006.134.07:37:00.02:preob 2006.134.07:37:01.15/onsource/TRACKING 2006.134.07:37:01.15:!2006.134.07:37:10 2006.134.07:37:10.02:data_valid=on 2006.134.07:37:10.02:midob 2006.134.07:37:11.15/onsource/TRACKING 2006.134.07:37:11.15/wx/19.47,1006.4,76 2006.134.07:37:11.36/cable/+6.5485E-03 2006.134.07:37:12.45/va/01,08,usb,yes,29,30 2006.134.07:37:12.45/va/02,07,usb,yes,29,30 2006.134.07:37:12.45/va/03,06,usb,yes,30,30 2006.134.07:37:12.45/va/04,07,usb,yes,29,31 2006.134.07:37:12.45/va/05,06,usb,yes,31,33 2006.134.07:37:12.45/va/06,05,usb,yes,31,31 2006.134.07:37:12.45/va/07,05,usb,yes,31,31 2006.134.07:37:12.45/va/08,06,usb,yes,29,28 2006.134.07:37:12.68/valo/01,532.99,yes,locked 2006.134.07:37:12.68/valo/02,572.99,yes,locked 2006.134.07:37:12.68/valo/03,672.99,yes,locked 2006.134.07:37:12.68/valo/04,832.99,yes,locked 2006.134.07:37:12.68/valo/05,652.99,yes,locked 2006.134.07:37:12.68/valo/06,772.99,yes,locked 2006.134.07:37:12.69/valo/07,832.99,yes,locked 2006.134.07:37:12.69/valo/08,852.99,yes,locked 2006.134.07:37:13.77/vb/01,04,usb,yes,28,27 2006.134.07:37:13.77/vb/02,04,usb,yes,30,31 2006.134.07:37:13.77/vb/03,04,usb,yes,26,30 2006.134.07:37:13.77/vb/04,04,usb,yes,27,27 2006.134.07:37:13.77/vb/05,04,usb,yes,26,29 2006.134.07:37:13.77/vb/06,04,usb,yes,27,29 2006.134.07:37:13.77/vb/07,04,usb,yes,29,28 2006.134.07:37:13.77/vb/08,04,usb,yes,26,29 2006.134.07:37:14.00/vblo/01,632.99,yes,locked 2006.134.07:37:14.00/vblo/02,640.99,yes,locked 2006.134.07:37:14.00/vblo/03,656.99,yes,locked 2006.134.07:37:14.00/vblo/04,712.99,yes,locked 2006.134.07:37:14.00/vblo/05,744.99,yes,locked 2006.134.07:37:14.00/vblo/06,752.99,yes,locked 2006.134.07:37:14.01/vblo/07,734.99,yes,locked 2006.134.07:37:14.01/vblo/08,744.99,yes,locked 2006.134.07:37:14.15/vabw/8 2006.134.07:37:14.30/vbbw/8 2006.134.07:37:14.44/xfe/off,on,14.2 2006.134.07:37:14.82/ifatt/23,28,28,28 2006.134.07:37:15.07/fmout-gps/S +1.79E-07 2006.134.07:37:15.12:!2006.134.07:38:10 2006.134.07:38:10.02:data_valid=off 2006.134.07:38:10.02:postob 2006.134.07:38:10.13/cable/+6.5496E-03 2006.134.07:38:10.14/wx/19.46,1006.4,76 2006.134.07:38:11.07/fmout-gps/S +1.79E-07 2006.134.07:38:11.07:scan_name=134-0739,k06134,60 2006.134.07:38:11.07:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.134.07:38:12.15#flagr#flagr/antenna,new-source 2006.134.07:38:12.15:checkk5 2006.134.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:38:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:38:14.00/chk_obsdata//k5ts1/T1340737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:38:14.37/chk_obsdata//k5ts2/T1340737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:38:14.74/chk_obsdata//k5ts3/T1340737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:38:15.10/chk_obsdata//k5ts4/T1340737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:38:15.79/k5log//k5ts1_log_newline 2006.134.07:38:16.47/k5log//k5ts2_log_newline 2006.134.07:38:17.16/k5log//k5ts3_log_newline 2006.134.07:38:17.84/k5log//k5ts4_log_newline 2006.134.07:38:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:38:17.86:4f8m12a=1 2006.134.07:38:17.86$4f8m12a/echo=on 2006.134.07:38:17.86$4f8m12a/pcalon 2006.134.07:38:17.86$pcalon/"no phase cal control is implemented here 2006.134.07:38:17.86$4f8m12a/"tpicd=stop 2006.134.07:38:17.86$4f8m12a/vc4f8 2006.134.07:38:17.86$vc4f8/valo=1,532.99 2006.134.07:38:17.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:38:17.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:38:17.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:17.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:17.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:17.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:17.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:38:17.95#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:17.95#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:17.95#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:38:17.95#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:38:17.95$vc4f8/va=1,8 2006.134.07:38:17.95#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:38:17.95#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:38:17.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:17.95#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:17.95#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:17.95#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:17.99#ibcon#[25=AT01-08\r\n] 2006.134.07:38:18.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:18.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:18.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:38:18.01#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:18.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:18.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:18.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:18.15#ibcon#[25=USB\r\n] 2006.134.07:38:18.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:18.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:18.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:38:18.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:38:18.20$vc4f8/valo=2,572.99 2006.134.07:38:18.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.07:38:18.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.07:38:18.20#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:18.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:18.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:18.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:38:18.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:18.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:18.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:38:18.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:38:18.25$vc4f8/va=2,7 2006.134.07:38:18.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.07:38:18.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.07:38:18.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:18.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:18.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:18.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:18.34#ibcon#[25=AT02-07\r\n] 2006.134.07:38:18.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:18.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:18.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.07:38:18.37#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:18.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:18.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:18.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:18.51#ibcon#[25=USB\r\n] 2006.134.07:38:18.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:18.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:18.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:38:18.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:38:18.56$vc4f8/valo=3,672.99 2006.134.07:38:18.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.07:38:18.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.07:38:18.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:18.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:18.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:18.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:18.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:38:18.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:18.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:18.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:38:18.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:38:18.61$vc4f8/va=3,6 2006.134.07:38:18.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.07:38:18.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.07:38:18.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:18.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:18.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:18.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:18.70#ibcon#[25=AT03-06\r\n] 2006.134.07:38:18.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:18.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:18.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.07:38:18.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:18.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:18.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:18.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:18.87#ibcon#[25=USB\r\n] 2006.134.07:38:18.90#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:18.90#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:18.90#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:38:18.90#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:38:18.90$vc4f8/valo=4,832.99 2006.134.07:38:18.90#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:38:18.90#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:38:18.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:18.90#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:18.90#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:18.90#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:38:18.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:18.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:18.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:38:18.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:38:18.97$vc4f8/va=4,7 2006.134.07:38:18.97#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:38:18.97#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:38:18.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:18.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:19.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:19.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:19.03#ibcon#[25=AT04-07\r\n] 2006.134.07:38:19.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:19.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:19.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:38:19.06#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:19.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:19.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:19.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:19.20#ibcon#[25=USB\r\n] 2006.134.07:38:19.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:19.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:19.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:38:19.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:38:19.23$vc4f8/valo=5,652.99 2006.134.07:38:19.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:38:19.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:38:19.23#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:19.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:19.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:19.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:38:19.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:19.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:19.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:38:19.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:38:19.29$vc4f8/va=5,6 2006.134.07:38:19.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:38:19.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:38:19.29#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:19.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:19.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:19.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:19.37#ibcon#[25=AT05-06\r\n] 2006.134.07:38:19.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:19.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:19.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:38:19.40#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:19.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:19.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:19.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:19.54#ibcon#[25=USB\r\n] 2006.134.07:38:19.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:19.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:19.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:38:19.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:38:19.57$vc4f8/valo=6,772.99 2006.134.07:38:19.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:38:19.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:38:19.57#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:19.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:19.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:19.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:38:19.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:19.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:19.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:38:19.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:38:19.63$vc4f8/va=6,5 2006.134.07:38:19.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:38:19.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:38:19.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:19.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:19.69#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:19.69#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:19.71#ibcon#[25=AT06-05\r\n] 2006.134.07:38:19.74#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:19.74#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:19.74#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:38:19.74#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:19.74#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:38:19.86#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:38:19.86#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:38:19.88#ibcon#[25=USB\r\n] 2006.134.07:38:19.91#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:38:19.91#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:38:19.91#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:38:19.91#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:38:19.91$vc4f8/valo=7,832.99 2006.134.07:38:19.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:38:19.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:38:19.91#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:19.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:38:19.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:38:19.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:38:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:38:19.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:38:19.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:38:19.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:38:19.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:38:19.97$vc4f8/va=7,5 2006.134.07:38:19.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:38:19.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:38:19.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:19.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:38:20.03#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:38:20.03#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:38:20.05#ibcon#[25=AT07-05\r\n] 2006.134.07:38:20.08#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:38:20.08#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:38:20.08#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:38:20.08#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:20.08#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:38:20.20#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:38:20.20#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:38:20.22#ibcon#[25=USB\r\n] 2006.134.07:38:20.25#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:38:20.25#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:38:20.25#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:38:20.25#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:38:20.25$vc4f8/valo=8,852.99 2006.134.07:38:20.25#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:38:20.25#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:38:20.25#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:20.25#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:38:20.25#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:38:20.25#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:38:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:38:20.31#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:38:20.31#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:38:20.31#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:38:20.31#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:38:20.31$vc4f8/va=8,6 2006.134.07:38:20.31#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:38:20.31#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:38:20.31#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:20.31#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:38:20.37#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:38:20.37#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:38:20.39#ibcon#[25=AT08-06\r\n] 2006.134.07:38:20.42#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:38:20.42#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:38:20.42#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:38:20.42#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:20.42#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:38:20.54#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:38:20.54#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:38:20.56#ibcon#[25=USB\r\n] 2006.134.07:38:20.59#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:38:20.59#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:38:20.59#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:38:20.59#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:38:20.59$vc4f8/vblo=1,632.99 2006.134.07:38:20.59#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:38:20.59#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:38:20.59#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:20.59#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:38:20.59#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:38:20.59#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:38:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:38:20.65#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:38:20.65#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:38:20.65#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:38:20.65#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:38:20.65$vc4f8/vb=1,4 2006.134.07:38:20.65#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:38:20.65#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:38:20.65#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:20.65#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:38:20.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:38:20.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:38:20.67#ibcon#[27=AT01-04\r\n] 2006.134.07:38:20.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:38:20.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:38:20.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:38:20.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:20.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:38:20.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:38:20.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:38:20.84#ibcon#[27=USB\r\n] 2006.134.07:38:20.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:38:20.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:38:20.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:38:20.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:38:20.87$vc4f8/vblo=2,640.99 2006.134.07:38:20.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:38:20.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:38:20.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:20.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:20.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:20.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:20.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:38:20.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:20.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:38:20.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:38:20.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:38:20.93$vc4f8/vb=2,4 2006.134.07:38:20.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:38:20.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:38:20.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:20.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:20.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:20.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:21.01#ibcon#[27=AT02-04\r\n] 2006.134.07:38:21.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:21.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:38:21.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:38:21.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:21.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:21.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:21.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:21.18#ibcon#[27=USB\r\n] 2006.134.07:38:21.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:21.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:38:21.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:38:21.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:38:21.21$vc4f8/vblo=3,656.99 2006.134.07:38:21.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.07:38:21.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.07:38:21.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:21.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:21.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:21.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:21.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:38:21.28#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:21.28#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:38:21.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:38:21.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:38:21.28$vc4f8/vb=3,4 2006.134.07:38:21.28#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.07:38:21.28#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.07:38:21.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:21.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:21.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:21.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:21.35#ibcon#[27=AT03-04\r\n] 2006.134.07:38:21.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:21.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:38:21.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.07:38:21.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:21.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:21.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:21.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:21.52#ibcon#[27=USB\r\n] 2006.134.07:38:21.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:21.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:38:21.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:38:21.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:38:21.55$vc4f8/vblo=4,712.99 2006.134.07:38:21.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.07:38:21.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.07:38:21.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:21.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:21.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:21.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:38:21.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:21.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:38:21.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:38:21.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:38:21.61$vc4f8/vb=4,4 2006.134.07:38:21.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.07:38:21.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.07:38:21.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:21.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:21.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:21.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:21.69#ibcon#[27=AT04-04\r\n] 2006.134.07:38:21.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:21.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:38:21.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.07:38:21.72#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:21.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:21.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:21.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:21.86#ibcon#[27=USB\r\n] 2006.134.07:38:21.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:21.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:38:21.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:38:21.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:38:21.89$vc4f8/vblo=5,744.99 2006.134.07:38:21.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:38:21.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:38:21.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:21.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:21.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:21.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:38:21.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:21.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:38:21.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:38:21.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:38:21.96$vc4f8/vb=5,4 2006.134.07:38:21.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:38:21.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:38:21.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:21.97#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:22.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:22.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:22.02#ibcon#[27=AT05-04\r\n] 2006.134.07:38:22.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:22.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:38:22.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:38:22.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:22.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:22.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:22.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:22.19#ibcon#[27=USB\r\n] 2006.134.07:38:22.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:22.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:38:22.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:38:22.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:38:22.22$vc4f8/vblo=6,752.99 2006.134.07:38:22.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:38:22.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:38:22.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:38:22.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:22.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:22.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:22.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:38:22.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:22.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:38:22.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:38:22.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:38:22.28$vc4f8/vb=6,4 2006.134.07:38:22.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:38:22.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:38:22.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:38:22.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:22.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:22.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:22.36#ibcon#[27=AT06-04\r\n] 2006.134.07:38:22.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:22.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:38:22.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:38:22.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:38:22.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:22.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:22.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:22.53#ibcon#[27=USB\r\n] 2006.134.07:38:22.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:22.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:38:22.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:38:22.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:38:22.56$vc4f8/vabw=wide 2006.134.07:38:22.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:38:22.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:38:22.56#ibcon#ireg 8 cls_cnt 0 2006.134.07:38:22.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:22.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:22.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:22.58#ibcon#[25=BW32\r\n] 2006.134.07:38:22.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:22.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:38:22.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:38:22.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:38:22.61$vc4f8/vbbw=wide 2006.134.07:38:22.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:38:22.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:38:22.61#ibcon#ireg 8 cls_cnt 0 2006.134.07:38:22.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:38:22.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:38:22.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:38:22.70#ibcon#[27=BW32\r\n] 2006.134.07:38:22.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:38:22.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:38:22.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:38:22.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:38:22.73$4f8m12a/ifd4f 2006.134.07:38:22.73$ifd4f/lo= 2006.134.07:38:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:38:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:38:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:38:22.74$ifd4f/patch= 2006.134.07:38:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:38:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:38:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:38:22.74$4f8m12a/"form=m,16.000,1:2 2006.134.07:38:22.74$4f8m12a/"tpicd 2006.134.07:38:22.74$4f8m12a/echo=off 2006.134.07:38:22.74$4f8m12a/xlog=off 2006.134.07:38:22.74:!2006.134.07:38:50 2006.134.07:38:28.14#trakl#Source acquired 2006.134.07:38:29.15#flagr#flagr/antenna,acquired 2006.134.07:38:50.01:preob 2006.134.07:38:51.14/onsource/TRACKING 2006.134.07:38:51.15:!2006.134.07:39:00 2006.134.07:39:00.01:data_valid=on 2006.134.07:39:00.02:midob 2006.134.07:39:01.14/onsource/TRACKING 2006.134.07:39:01.15/wx/19.44,1006.3,75 2006.134.07:39:01.29/cable/+6.5467E-03 2006.134.07:39:02.38/va/01,08,usb,yes,29,30 2006.134.07:39:02.38/va/02,07,usb,yes,29,30 2006.134.07:39:02.38/va/03,06,usb,yes,30,30 2006.134.07:39:02.38/va/04,07,usb,yes,29,32 2006.134.07:39:02.38/va/05,06,usb,yes,31,33 2006.134.07:39:02.38/va/06,05,usb,yes,31,31 2006.134.07:39:02.38/va/07,05,usb,yes,31,31 2006.134.07:39:02.38/va/08,06,usb,yes,29,28 2006.134.07:39:02.61/valo/01,532.99,yes,locked 2006.134.07:39:02.61/valo/02,572.99,yes,locked 2006.134.07:39:02.61/valo/03,672.99,yes,locked 2006.134.07:39:02.61/valo/04,832.99,yes,locked 2006.134.07:39:02.61/valo/05,652.99,yes,locked 2006.134.07:39:02.61/valo/06,772.99,yes,locked 2006.134.07:39:02.61/valo/07,832.99,yes,locked 2006.134.07:39:02.61/valo/08,852.99,yes,locked 2006.134.07:39:03.70/vb/01,04,usb,yes,29,27 2006.134.07:39:03.70/vb/02,04,usb,yes,30,32 2006.134.07:39:03.70/vb/03,04,usb,yes,27,30 2006.134.07:39:03.70/vb/04,04,usb,yes,28,28 2006.134.07:39:03.70/vb/05,04,usb,yes,26,30 2006.134.07:39:03.70/vb/06,04,usb,yes,27,30 2006.134.07:39:03.70/vb/07,04,usb,yes,29,29 2006.134.07:39:03.70/vb/08,04,usb,yes,27,30 2006.134.07:39:03.94/vblo/01,632.99,yes,locked 2006.134.07:39:03.94/vblo/02,640.99,yes,locked 2006.134.07:39:03.94/vblo/03,656.99,yes,locked 2006.134.07:39:03.94/vblo/04,712.99,yes,locked 2006.134.07:39:03.94/vblo/05,744.99,yes,locked 2006.134.07:39:03.94/vblo/06,752.99,yes,locked 2006.134.07:39:03.94/vblo/07,734.99,yes,locked 2006.134.07:39:03.94/vblo/08,744.99,yes,locked 2006.134.07:39:04.09/vabw/8 2006.134.07:39:04.24/vbbw/8 2006.134.07:39:04.33/xfe/off,on,14.7 2006.134.07:39:04.72/ifatt/23,28,28,28 2006.134.07:39:05.07/fmout-gps/S +1.79E-07 2006.134.07:39:05.12:!2006.134.07:40:00 2006.134.07:40:00.00:data_valid=off 2006.134.07:40:00.01:postob 2006.134.07:40:00.24/cable/+6.5464E-03 2006.134.07:40:00.25/wx/19.42,1006.4,77 2006.134.07:40:01.07/fmout-gps/S +1.79E-07 2006.134.07:40:01.08:scan_name=134-0740,k06134,60 2006.134.07:40:01.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.134.07:40:02.14#flagr#flagr/antenna,new-source 2006.134.07:40:02.15:checkk5 2006.134.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:40:04.00/chk_obsdata//k5ts1/T1340739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:40:04.36/chk_obsdata//k5ts2/T1340739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:40:04.73/chk_obsdata//k5ts3/T1340739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:40:05.09/chk_obsdata//k5ts4/T1340739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:40:05.78/k5log//k5ts1_log_newline 2006.134.07:40:06.46/k5log//k5ts2_log_newline 2006.134.07:40:07.15/k5log//k5ts3_log_newline 2006.134.07:40:07.83/k5log//k5ts4_log_newline 2006.134.07:40:07.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:40:07.85:4f8m12a=1 2006.134.07:40:07.85$4f8m12a/echo=on 2006.134.07:40:07.85$4f8m12a/pcalon 2006.134.07:40:07.85$pcalon/"no phase cal control is implemented here 2006.134.07:40:07.85$4f8m12a/"tpicd=stop 2006.134.07:40:07.85$4f8m12a/vc4f8 2006.134.07:40:07.85$vc4f8/valo=1,532.99 2006.134.07:40:07.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:40:07.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:40:07.86#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:07.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:07.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:07.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:07.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:40:07.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:07.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:07.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:40:07.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:40:07.94$vc4f8/va=1,8 2006.134.07:40:07.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:40:07.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:40:07.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:07.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:07.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:07.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:07.98#ibcon#[25=AT01-08\r\n] 2006.134.07:40:08.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:08.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:08.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:40:08.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:08.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:08.02#abcon#<5=/04 3.2 6.0 19.42 761006.4\r\n> 2006.134.07:40:08.05#abcon#{5=INTERFACE CLEAR} 2006.134.07:40:08.10#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:40:08.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:08.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:08.16#ibcon#[25=USB\r\n] 2006.134.07:40:08.18#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:08.18#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:08.18#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:40:08.18#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:40:08.18$vc4f8/valo=2,572.99 2006.134.07:40:08.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:40:08.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:40:08.18#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:08.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:08.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:08.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:08.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:40:08.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:08.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:08.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:40:08.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:40:08.24$vc4f8/va=2,7 2006.134.07:40:08.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:40:08.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:40:08.24#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:08.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:08.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:08.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:08.33#ibcon#[25=AT02-07\r\n] 2006.134.07:40:08.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:08.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:08.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:40:08.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:08.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:08.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:08.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:08.50#ibcon#[25=USB\r\n] 2006.134.07:40:08.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:08.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:08.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:40:08.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:40:08.53$vc4f8/valo=3,672.99 2006.134.07:40:08.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:40:08.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:40:08.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:08.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:08.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:08.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:40:08.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:08.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:08.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:40:08.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:40:08.60$vc4f8/va=3,6 2006.134.07:40:08.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:40:08.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:40:08.60#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:08.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:08.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:08.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:08.67#ibcon#[25=AT03-06\r\n] 2006.134.07:40:08.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:08.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:08.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:40:08.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:08.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:08.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:08.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:08.84#ibcon#[25=USB\r\n] 2006.134.07:40:08.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:08.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:08.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:40:08.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:40:08.87$vc4f8/valo=4,832.99 2006.134.07:40:08.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:40:08.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:40:08.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:08.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:08.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:08.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:08.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:40:08.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:08.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:08.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:40:08.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:40:08.93$vc4f8/va=4,7 2006.134.07:40:08.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:40:08.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:40:08.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:08.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:08.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:08.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:09.01#ibcon#[25=AT04-07\r\n] 2006.134.07:40:09.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:09.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:09.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:40:09.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:09.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:09.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:09.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:09.18#ibcon#[25=USB\r\n] 2006.134.07:40:09.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:09.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:09.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:40:09.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:40:09.21$vc4f8/valo=5,652.99 2006.134.07:40:09.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:40:09.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:40:09.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:09.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:09.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:09.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:09.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:40:09.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:09.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:09.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:40:09.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:40:09.27$vc4f8/va=5,6 2006.134.07:40:09.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:40:09.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:40:09.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:09.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:09.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:09.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:09.35#ibcon#[25=AT05-06\r\n] 2006.134.07:40:09.39#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:09.39#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:09.39#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:40:09.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:09.39#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:09.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:09.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:09.52#ibcon#[25=USB\r\n] 2006.134.07:40:09.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:09.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:09.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:40:09.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:40:09.55$vc4f8/valo=6,772.99 2006.134.07:40:09.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:40:09.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:40:09.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:09.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:09.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:09.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:09.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:40:09.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:09.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:09.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:40:09.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:40:09.61$vc4f8/va=6,5 2006.134.07:40:09.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.07:40:09.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.07:40:09.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:09.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:09.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:09.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:09.69#ibcon#[25=AT06-05\r\n] 2006.134.07:40:09.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:09.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:09.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.07:40:09.72#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:09.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:40:09.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:40:09.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:40:09.86#ibcon#[25=USB\r\n] 2006.134.07:40:09.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:40:09.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:40:09.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:40:09.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:40:09.89$vc4f8/valo=7,832.99 2006.134.07:40:09.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:40:09.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:40:09.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:09.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:40:09.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:40:09.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:40:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:40:09.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:40:09.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:40:09.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:40:09.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:40:09.95$vc4f8/va=7,5 2006.134.07:40:09.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:40:09.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:40:09.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:09.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:40:10.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:40:10.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:40:10.03#ibcon#[25=AT07-05\r\n] 2006.134.07:40:10.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:40:10.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:40:10.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:40:10.06#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:10.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:40:10.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:40:10.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:40:10.20#ibcon#[25=USB\r\n] 2006.134.07:40:10.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:40:10.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:40:10.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:40:10.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:40:10.23$vc4f8/valo=8,852.99 2006.134.07:40:10.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:40:10.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:40:10.23#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:10.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:40:10.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:40:10.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:40:10.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:40:10.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:40:10.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:40:10.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:40:10.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:40:10.29$vc4f8/va=8,6 2006.134.07:40:10.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:40:10.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:40:10.29#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:10.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:40:10.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:40:10.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:40:10.37#ibcon#[25=AT08-06\r\n] 2006.134.07:40:10.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:40:10.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:40:10.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:40:10.40#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:10.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:40:10.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:40:10.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:40:10.54#ibcon#[25=USB\r\n] 2006.134.07:40:10.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:40:10.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:40:10.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:40:10.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:40:10.57$vc4f8/vblo=1,632.99 2006.134.07:40:10.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:40:10.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:40:10.57#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:10.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:10.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:10.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:40:10.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:10.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:40:10.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:40:10.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:40:10.63$vc4f8/vb=1,4 2006.134.07:40:10.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:40:10.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:40:10.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:10.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:10.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:10.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:10.65#ibcon#[27=AT01-04\r\n] 2006.134.07:40:10.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:10.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:40:10.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:40:10.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:10.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:10.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:10.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:10.82#ibcon#[27=USB\r\n] 2006.134.07:40:10.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:10.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:40:10.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:40:10.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:40:10.85$vc4f8/vblo=2,640.99 2006.134.07:40:10.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:40:10.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:40:10.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:10.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:40:10.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:40:10.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:40:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:40:10.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:40:10.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:40:10.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:40:10.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:40:10.91$vc4f8/vb=2,4 2006.134.07:40:10.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:40:10.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:40:10.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:10.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:40:10.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:40:10.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:40:10.99#ibcon#[27=AT02-04\r\n] 2006.134.07:40:11.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:40:11.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:40:11.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:40:11.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:11.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:40:11.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:40:11.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:40:11.16#ibcon#[27=USB\r\n] 2006.134.07:40:11.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:40:11.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:40:11.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:40:11.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:40:11.19$vc4f8/vblo=3,656.99 2006.134.07:40:11.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:40:11.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:40:11.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:11.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:11.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:11.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:40:11.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:11.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:40:11.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:40:11.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:40:11.25$vc4f8/vb=3,4 2006.134.07:40:11.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:40:11.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:40:11.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:11.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:11.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:11.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:11.33#ibcon#[27=AT03-04\r\n] 2006.134.07:40:11.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:11.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:40:11.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:40:11.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:11.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:11.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:11.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:11.50#ibcon#[27=USB\r\n] 2006.134.07:40:11.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:11.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:40:11.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:40:11.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:40:11.53$vc4f8/vblo=4,712.99 2006.134.07:40:11.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:40:11.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:40:11.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:11.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:11.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:11.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:11.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:40:11.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:11.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:40:11.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:40:11.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:40:11.59$vc4f8/vb=4,4 2006.134.07:40:11.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:40:11.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:40:11.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:11.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:11.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:11.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:11.67#ibcon#[27=AT04-04\r\n] 2006.134.07:40:11.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:11.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:40:11.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:40:11.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:11.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:11.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:11.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:11.84#ibcon#[27=USB\r\n] 2006.134.07:40:11.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:11.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:40:11.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:40:11.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:40:11.87$vc4f8/vblo=5,744.99 2006.134.07:40:11.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:40:11.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:40:11.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:11.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:11.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:11.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:40:11.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:11.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:40:11.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:40:11.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:40:11.93$vc4f8/vb=5,4 2006.134.07:40:11.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:40:11.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:40:11.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:11.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:11.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:11.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:12.01#ibcon#[27=AT05-04\r\n] 2006.134.07:40:12.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:12.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:40:12.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:40:12.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:12.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:12.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:12.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:12.18#ibcon#[27=USB\r\n] 2006.134.07:40:12.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:12.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:40:12.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:40:12.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:40:12.21$vc4f8/vblo=6,752.99 2006.134.07:40:12.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:40:12.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:40:12.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:40:12.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:12.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:12.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:12.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:40:12.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:12.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:40:12.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:40:12.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:40:12.27$vc4f8/vb=6,4 2006.134.07:40:12.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:40:12.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:40:12.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:40:12.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:12.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:12.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:12.35#ibcon#[27=AT06-04\r\n] 2006.134.07:40:12.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:12.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:40:12.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:40:12.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:40:12.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:12.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:12.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:12.52#ibcon#[27=USB\r\n] 2006.134.07:40:12.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:12.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:40:12.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:40:12.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:40:12.55$vc4f8/vabw=wide 2006.134.07:40:12.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:40:12.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:40:12.55#ibcon#ireg 8 cls_cnt 0 2006.134.07:40:12.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:12.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:12.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:12.57#ibcon#[25=BW32\r\n] 2006.134.07:40:12.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:12.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:40:12.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:40:12.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:40:12.60$vc4f8/vbbw=wide 2006.134.07:40:12.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:40:12.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:40:12.60#ibcon#ireg 8 cls_cnt 0 2006.134.07:40:12.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:40:12.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:40:12.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:40:12.69#ibcon#[27=BW32\r\n] 2006.134.07:40:12.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:40:12.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:40:12.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:40:12.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:40:12.72$4f8m12a/ifd4f 2006.134.07:40:12.72$ifd4f/lo= 2006.134.07:40:12.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:40:12.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:40:12.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:40:12.73$ifd4f/patch= 2006.134.07:40:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:40:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:40:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:40:12.73$4f8m12a/"form=m,16.000,1:2 2006.134.07:40:12.73$4f8m12a/"tpicd 2006.134.07:40:12.73$4f8m12a/echo=off 2006.134.07:40:12.73$4f8m12a/xlog=off 2006.134.07:40:12.73:!2006.134.07:40:40 2006.134.07:40:24.14#trakl#Source acquired 2006.134.07:40:25.14#flagr#flagr/antenna,acquired 2006.134.07:40:40.01:preob 2006.134.07:40:41.13/onsource/TRACKING 2006.134.07:40:41.13:!2006.134.07:40:50 2006.134.07:40:50.00:data_valid=on 2006.134.07:40:50.00:midob 2006.134.07:40:50.13/onsource/TRACKING 2006.134.07:40:50.13/wx/19.41,1006.4,77 2006.134.07:40:50.22/cable/+6.5461E-03 2006.134.07:40:51.30/va/01,08,usb,yes,28,30 2006.134.07:40:51.30/va/02,07,usb,yes,28,30 2006.134.07:40:51.30/va/03,06,usb,yes,30,30 2006.134.07:40:51.30/va/04,07,usb,yes,29,31 2006.134.07:40:51.30/va/05,06,usb,yes,30,32 2006.134.07:40:51.30/va/06,05,usb,yes,31,30 2006.134.07:40:51.30/va/07,05,usb,yes,31,30 2006.134.07:40:51.30/va/08,06,usb,yes,28,28 2006.134.07:40:51.53/valo/01,532.99,yes,locked 2006.134.07:40:51.53/valo/02,572.99,yes,locked 2006.134.07:40:51.53/valo/03,672.99,yes,locked 2006.134.07:40:51.53/valo/04,832.99,yes,locked 2006.134.07:40:51.53/valo/05,652.99,yes,locked 2006.134.07:40:51.53/valo/06,772.99,yes,locked 2006.134.07:40:51.53/valo/07,832.99,yes,locked 2006.134.07:40:51.53/valo/08,852.99,yes,locked 2006.134.07:40:52.62/vb/01,04,usb,yes,28,27 2006.134.07:40:52.62/vb/02,04,usb,yes,30,31 2006.134.07:40:52.62/vb/03,04,usb,yes,26,30 2006.134.07:40:52.62/vb/04,04,usb,yes,28,27 2006.134.07:40:52.62/vb/05,04,usb,yes,26,30 2006.134.07:40:52.62/vb/06,04,usb,yes,27,29 2006.134.07:40:52.62/vb/07,04,usb,yes,29,29 2006.134.07:40:52.62/vb/08,04,usb,yes,26,30 2006.134.07:40:52.85/vblo/01,632.99,yes,locked 2006.134.07:40:52.85/vblo/02,640.99,yes,locked 2006.134.07:40:52.85/vblo/03,656.99,yes,locked 2006.134.07:40:52.85/vblo/04,712.99,yes,locked 2006.134.07:40:52.85/vblo/05,744.99,yes,locked 2006.134.07:40:52.85/vblo/06,752.99,yes,locked 2006.134.07:40:52.85/vblo/07,734.99,yes,locked 2006.134.07:40:52.85/vblo/08,744.99,yes,locked 2006.134.07:40:53.00/vabw/8 2006.134.07:40:53.15/vbbw/8 2006.134.07:40:53.30/xfe/off,on,15.2 2006.134.07:40:53.67/ifatt/23,28,28,28 2006.134.07:40:54.07/fmout-gps/S +1.79E-07 2006.134.07:40:54.12:!2006.134.07:41:50 2006.134.07:41:50.01:data_valid=off 2006.134.07:41:50.02:postob 2006.134.07:41:50.17/cable/+6.5466E-03 2006.134.07:41:50.21/wx/19.39,1006.4,78 2006.134.07:41:51.07/fmout-gps/S +1.79E-07 2006.134.07:41:51.08:scan_name=134-0742,k06134,60 2006.134.07:41:51.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.134.07:41:51.13#flagr#flagr/antenna,new-source 2006.134.07:41:52.13:checkk5 2006.134.07:41:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:41:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:41:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:41:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:41:53.98/chk_obsdata//k5ts1/T1340740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:41:54.35/chk_obsdata//k5ts2/T1340740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:41:54.72/chk_obsdata//k5ts3/T1340740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:41:55.08/chk_obsdata//k5ts4/T1340740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:41:55.77/k5log//k5ts1_log_newline 2006.134.07:41:56.45/k5log//k5ts2_log_newline 2006.134.07:41:57.14/k5log//k5ts3_log_newline 2006.134.07:41:57.82/k5log//k5ts4_log_newline 2006.134.07:41:57.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:41:57.84:4f8m12a=1 2006.134.07:41:57.84$4f8m12a/echo=on 2006.134.07:41:57.84$4f8m12a/pcalon 2006.134.07:41:57.84$pcalon/"no phase cal control is implemented here 2006.134.07:41:57.84$4f8m12a/"tpicd=stop 2006.134.07:41:57.84$4f8m12a/vc4f8 2006.134.07:41:57.84$vc4f8/valo=1,532.99 2006.134.07:41:57.85#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.07:41:57.85#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.07:41:57.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:57.85#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:41:57.85#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:41:57.85#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:41:57.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:41:57.93#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:41:57.93#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:41:57.93#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:41:57.93#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:41:57.93$vc4f8/va=1,8 2006.134.07:41:57.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.07:41:57.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.07:41:57.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:57.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:41:57.93#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:41:57.93#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:41:57.96#ibcon#[25=AT01-08\r\n] 2006.134.07:41:57.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:41:57.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:41:57.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.07:41:57.99#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:57.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:41:58.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:41:58.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:41:58.13#ibcon#[25=USB\r\n] 2006.134.07:41:58.18#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:41:58.18#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:41:58.18#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:41:58.18#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:41:58.18$vc4f8/valo=2,572.99 2006.134.07:41:58.18#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:41:58.18#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:41:58.18#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:58.18#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:41:58.18#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:41:58.18#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:41:58.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:41:58.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:41:58.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:41:58.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:41:58.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:41:58.23$vc4f8/va=2,7 2006.134.07:41:58.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.07:41:58.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.07:41:58.23#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:58.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:41:58.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:41:58.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:41:58.32#ibcon#[25=AT02-07\r\n] 2006.134.07:41:58.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:41:58.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:41:58.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.07:41:58.35#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:58.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:41:58.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:41:58.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:41:58.49#ibcon#[25=USB\r\n] 2006.134.07:41:58.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:41:58.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:41:58.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:41:58.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:41:58.54$vc4f8/valo=3,672.99 2006.134.07:41:58.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.07:41:58.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.07:41:58.54#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:58.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:41:58.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:41:58.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:41:58.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:41:58.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:41:58.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:41:58.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:41:58.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:41:58.59$vc4f8/va=3,6 2006.134.07:41:58.59#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.07:41:58.59#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.07:41:58.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:58.59#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:41:58.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:41:58.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:41:58.68#ibcon#[25=AT03-06\r\n] 2006.134.07:41:58.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:41:58.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:41:58.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.07:41:58.71#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:58.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:41:58.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:41:58.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:41:58.85#ibcon#[25=USB\r\n] 2006.134.07:41:58.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:41:58.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:41:58.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:41:58.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:41:58.88$vc4f8/valo=4,832.99 2006.134.07:41:58.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:41:58.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:41:58.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:58.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:41:58.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:41:58.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:41:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:41:58.94#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:41:58.94#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:41:58.94#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:41:58.94#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:41:58.94$vc4f8/va=4,7 2006.134.07:41:58.94#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.07:41:58.94#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.07:41:58.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:58.94#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:41:59.00#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:41:59.00#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:41:59.02#ibcon#[25=AT04-07\r\n] 2006.134.07:41:59.05#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:41:59.05#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:41:59.05#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.07:41:59.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:59.05#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:41:59.17#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:41:59.17#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:41:59.19#ibcon#[25=USB\r\n] 2006.134.07:41:59.22#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:41:59.22#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:41:59.22#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:41:59.22#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:41:59.22$vc4f8/valo=5,652.99 2006.134.07:41:59.22#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:41:59.22#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:41:59.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:59.22#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:41:59.22#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:41:59.22#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:41:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:41:59.28#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:41:59.28#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:41:59.28#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:41:59.28#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:41:59.28$vc4f8/va=5,6 2006.134.07:41:59.28#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.07:41:59.28#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.07:41:59.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:59.28#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:41:59.34#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:41:59.34#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:41:59.36#ibcon#[25=AT05-06\r\n] 2006.134.07:41:59.39#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:41:59.39#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:41:59.39#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.07:41:59.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:59.39#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:41:59.51#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:41:59.51#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:41:59.53#ibcon#[25=USB\r\n] 2006.134.07:41:59.56#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:41:59.56#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:41:59.56#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:41:59.56#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:41:59.56$vc4f8/valo=6,772.99 2006.134.07:41:59.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.07:41:59.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.07:41:59.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:59.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:41:59.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:41:59.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:41:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:41:59.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:41:59.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:41:59.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:41:59.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:41:59.64$vc4f8/va=6,5 2006.134.07:41:59.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.07:41:59.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.07:41:59.64#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:59.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:41:59.68#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:41:59.68#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:41:59.70#ibcon#[25=AT06-05\r\n] 2006.134.07:41:59.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:41:59.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:41:59.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.07:41:59.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:41:59.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:41:59.85#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:41:59.85#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:41:59.87#ibcon#[25=USB\r\n] 2006.134.07:41:59.89#abcon#<5=/04 3.4 5.9 19.38 781006.4\r\n> 2006.134.07:41:59.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:41:59.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:41:59.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:41:59.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:41:59.90$vc4f8/valo=7,832.99 2006.134.07:41:59.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:41:59.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:41:59.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:41:59.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:41:59.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:41:59.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:41:59.91#abcon#{5=INTERFACE CLEAR} 2006.134.07:41:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:41:59.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:41:59.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:41:59.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:41:59.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:41:59.96$vc4f8/va=7,5 2006.134.07:41:59.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.07:41:59.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.07:41:59.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:41:59.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:41:59.97#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:42:00.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:42:00.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:42:00.04#ibcon#[25=AT07-05\r\n] 2006.134.07:42:00.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:42:00.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:42:00.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.07:42:00.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:00.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:42:00.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:42:00.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:42:00.21#ibcon#[25=USB\r\n] 2006.134.07:42:00.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:42:00.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:42:00.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:42:00.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:42:00.24$vc4f8/valo=8,852.99 2006.134.07:42:00.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:42:00.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:42:00.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:00.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:42:00.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:42:00.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:42:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:42:00.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:42:00.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:42:00.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:42:00.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:42:00.31$vc4f8/va=8,6 2006.134.07:42:00.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.07:42:00.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.07:42:00.31#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:00.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:42:00.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:42:00.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:42:00.37#ibcon#[25=AT08-06\r\n] 2006.134.07:42:00.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:42:00.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:42:00.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.07:42:00.40#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:00.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:42:00.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:42:00.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:42:00.54#ibcon#[25=USB\r\n] 2006.134.07:42:00.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:42:00.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:42:00.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:42:00.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:42:00.57$vc4f8/vblo=1,632.99 2006.134.07:42:00.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.07:42:00.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.07:42:00.57#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:00.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:42:00.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:42:00.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:42:00.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:42:00.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:42:00.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:42:00.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:42:00.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:42:00.63$vc4f8/vb=1,4 2006.134.07:42:00.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.07:42:00.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.07:42:00.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:00.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:42:00.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:42:00.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:42:00.65#ibcon#[27=AT01-04\r\n] 2006.134.07:42:00.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:42:00.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:42:00.68#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.07:42:00.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:00.68#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:42:00.80#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:42:00.80#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:42:00.82#ibcon#[27=USB\r\n] 2006.134.07:42:00.85#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:42:00.85#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:42:00.85#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:42:00.85#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:42:00.85$vc4f8/vblo=2,640.99 2006.134.07:42:00.85#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:42:00.85#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:42:00.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:00.85#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:42:00.85#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:42:00.85#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:42:00.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:42:00.91#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:42:00.91#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:42:00.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:42:00.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:42:00.91$vc4f8/vb=2,4 2006.134.07:42:00.91#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.07:42:00.91#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.07:42:00.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:00.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:42:00.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:42:00.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:42:00.99#ibcon#[27=AT02-04\r\n] 2006.134.07:42:01.02#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:42:01.02#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:42:01.02#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.07:42:01.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:01.02#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:42:01.14#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:42:01.14#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:42:01.16#ibcon#[27=USB\r\n] 2006.134.07:42:01.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:42:01.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:42:01.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:42:01.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:42:01.21$vc4f8/vblo=3,656.99 2006.134.07:42:01.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.07:42:01.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.07:42:01.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:01.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:42:01.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:42:01.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:42:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:42:01.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:42:01.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:42:01.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:42:01.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:42:01.26$vc4f8/vb=3,4 2006.134.07:42:01.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.07:42:01.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.07:42:01.26#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:01.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:42:01.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:42:01.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:42:01.35#ibcon#[27=AT03-04\r\n] 2006.134.07:42:01.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:42:01.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:42:01.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.07:42:01.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:01.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:42:01.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:42:01.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:42:01.52#ibcon#[27=USB\r\n] 2006.134.07:42:01.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:42:01.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:42:01.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:42:01.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:42:01.55$vc4f8/vblo=4,712.99 2006.134.07:42:01.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:42:01.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:42:01.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:01.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:42:01.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:42:01.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:42:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:42:01.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:42:01.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:42:01.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:42:01.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:42:01.61$vc4f8/vb=4,4 2006.134.07:42:01.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.07:42:01.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.07:42:01.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:01.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:42:01.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:42:01.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:42:01.69#ibcon#[27=AT04-04\r\n] 2006.134.07:42:01.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:42:01.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:42:01.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.07:42:01.72#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:01.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:42:01.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:42:01.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:42:01.86#ibcon#[27=USB\r\n] 2006.134.07:42:01.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:42:01.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:42:01.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:42:01.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:42:01.89$vc4f8/vblo=5,744.99 2006.134.07:42:01.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:42:01.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:42:01.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:01.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:42:01.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:42:01.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:42:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:42:01.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:42:01.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:42:01.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:42:01.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:42:01.97$vc4f8/vb=5,4 2006.134.07:42:01.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.07:42:01.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.07:42:01.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:01.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:42:02.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:42:02.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:42:02.02#ibcon#[27=AT05-04\r\n] 2006.134.07:42:02.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:42:02.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:42:02.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.07:42:02.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:02.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:42:02.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:42:02.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:42:02.19#ibcon#[27=USB\r\n] 2006.134.07:42:02.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:42:02.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:42:02.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:42:02.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:42:02.22$vc4f8/vblo=6,752.99 2006.134.07:42:02.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.07:42:02.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.07:42:02.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:42:02.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:42:02.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:42:02.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:42:02.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:42:02.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:42:02.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:42:02.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:42:02.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:42:02.28$vc4f8/vb=6,4 2006.134.07:42:02.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.07:42:02.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.07:42:02.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:42:02.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:42:02.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:42:02.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:42:02.36#ibcon#[27=AT06-04\r\n] 2006.134.07:42:02.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:42:02.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:42:02.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.07:42:02.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:42:02.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:42:02.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:42:02.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:42:02.53#ibcon#[27=USB\r\n] 2006.134.07:42:02.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:42:02.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:42:02.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:42:02.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:42:02.56$vc4f8/vabw=wide 2006.134.07:42:02.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.07:42:02.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.07:42:02.56#ibcon#ireg 8 cls_cnt 0 2006.134.07:42:02.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:42:02.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:42:02.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:42:02.58#ibcon#[25=BW32\r\n] 2006.134.07:42:02.61#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:42:02.61#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:42:02.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:42:02.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:42:02.61$vc4f8/vbbw=wide 2006.134.07:42:02.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:42:02.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:42:02.61#ibcon#ireg 8 cls_cnt 0 2006.134.07:42:02.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:42:02.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:42:02.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:42:02.70#ibcon#[27=BW32\r\n] 2006.134.07:42:02.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:42:02.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:42:02.73#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:42:02.73#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:42:02.73$4f8m12a/ifd4f 2006.134.07:42:02.73$ifd4f/lo= 2006.134.07:42:02.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:42:02.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:42:02.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:42:02.73$ifd4f/patch= 2006.134.07:42:02.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:42:02.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:42:02.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:42:02.74$4f8m12a/"form=m,16.000,1:2 2006.134.07:42:02.74$4f8m12a/"tpicd 2006.134.07:42:02.74$4f8m12a/echo=off 2006.134.07:42:02.74$4f8m12a/xlog=off 2006.134.07:42:02.74:!2006.134.07:42:30 2006.134.07:42:12.13#trakl#Source acquired 2006.134.07:42:12.13#flagr#flagr/antenna,acquired 2006.134.07:42:30.01:preob 2006.134.07:42:31.13/onsource/TRACKING 2006.134.07:42:31.13:!2006.134.07:42:40 2006.134.07:42:40.00:data_valid=on 2006.134.07:42:40.00:midob 2006.134.07:42:40.13/onsource/TRACKING 2006.134.07:42:40.13/wx/19.37,1006.4,79 2006.134.07:42:40.29/cable/+6.5454E-03 2006.134.07:42:41.38/va/01,08,usb,yes,29,30 2006.134.07:42:41.38/va/02,07,usb,yes,29,30 2006.134.07:42:41.38/va/03,06,usb,yes,30,30 2006.134.07:42:41.38/va/04,07,usb,yes,29,32 2006.134.07:42:41.38/va/05,06,usb,yes,31,33 2006.134.07:42:41.38/va/06,05,usb,yes,31,31 2006.134.07:42:41.38/va/07,05,usb,yes,31,31 2006.134.07:42:41.38/va/08,06,usb,yes,29,28 2006.134.07:42:41.61/valo/01,532.99,yes,locked 2006.134.07:42:41.61/valo/02,572.99,yes,locked 2006.134.07:42:41.61/valo/03,672.99,yes,locked 2006.134.07:42:41.61/valo/04,832.99,yes,locked 2006.134.07:42:41.61/valo/05,652.99,yes,locked 2006.134.07:42:41.61/valo/06,772.99,yes,locked 2006.134.07:42:41.61/valo/07,832.99,yes,locked 2006.134.07:42:41.61/valo/08,852.99,yes,locked 2006.134.07:42:42.70/vb/01,04,usb,yes,28,27 2006.134.07:42:42.70/vb/02,04,usb,yes,30,31 2006.134.07:42:42.70/vb/03,04,usb,yes,27,30 2006.134.07:42:42.70/vb/04,04,usb,yes,27,27 2006.134.07:42:42.70/vb/05,04,usb,yes,26,30 2006.134.07:42:42.70/vb/06,04,usb,yes,27,30 2006.134.07:42:42.70/vb/07,04,usb,yes,29,29 2006.134.07:42:42.70/vb/08,04,usb,yes,27,30 2006.134.07:42:42.94/vblo/01,632.99,yes,locked 2006.134.07:42:42.94/vblo/02,640.99,yes,locked 2006.134.07:42:42.94/vblo/03,656.99,yes,locked 2006.134.07:42:42.94/vblo/04,712.99,yes,locked 2006.134.07:42:42.94/vblo/05,744.99,yes,locked 2006.134.07:42:42.94/vblo/06,752.99,yes,locked 2006.134.07:42:42.94/vblo/07,734.99,yes,locked 2006.134.07:42:42.94/vblo/08,744.99,yes,locked 2006.134.07:42:43.09/vabw/8 2006.134.07:42:43.24/vbbw/8 2006.134.07:42:43.33/xfe/off,on,15.5 2006.134.07:42:43.72/ifatt/23,28,28,28 2006.134.07:42:44.07/fmout-gps/S +1.79E-07 2006.134.07:42:44.11:!2006.134.07:43:40 2006.134.07:43:40.01:data_valid=off 2006.134.07:43:40.02:postob 2006.134.07:43:40.10/cable/+6.5466E-03 2006.134.07:43:40.10/wx/19.35,1006.4,80 2006.134.07:43:41.07/fmout-gps/S +1.79E-07 2006.134.07:43:41.08:scan_name=134-0744,k06134,60 2006.134.07:43:41.08:source=0955+476,095819.67,472507.8,2000.0,cw 2006.134.07:43:41.14#flagr#flagr/antenna,new-source 2006.134.07:43:42.14:checkk5 2006.134.07:43:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:43:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:43:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:43:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:43:44.00/chk_obsdata//k5ts1/T1340742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:43:44.38/chk_obsdata//k5ts2/T1340742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:43:44.74/chk_obsdata//k5ts3/T1340742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:43:45.10/chk_obsdata//k5ts4/T1340742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:43:45.79/k5log//k5ts1_log_newline 2006.134.07:43:46.48/k5log//k5ts2_log_newline 2006.134.07:43:47.17/k5log//k5ts3_log_newline 2006.134.07:43:47.85/k5log//k5ts4_log_newline 2006.134.07:43:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:43:47.87:4f8m12a=1 2006.134.07:43:47.87$4f8m12a/echo=on 2006.134.07:43:47.87$4f8m12a/pcalon 2006.134.07:43:47.87$pcalon/"no phase cal control is implemented here 2006.134.07:43:47.87$4f8m12a/"tpicd=stop 2006.134.07:43:47.87$4f8m12a/vc4f8 2006.134.07:43:47.87$vc4f8/valo=1,532.99 2006.134.07:43:47.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:43:47.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:43:47.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:47.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:47.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:47.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:47.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:43:47.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:47.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:47.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:43:47.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:43:47.96$vc4f8/va=1,8 2006.134.07:43:47.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.07:43:47.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.07:43:47.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:47.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:47.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:47.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:48.00#ibcon#[25=AT01-08\r\n] 2006.134.07:43:48.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:48.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:48.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.07:43:48.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:48.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:48.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:48.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:48.16#ibcon#[25=USB\r\n] 2006.134.07:43:48.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:48.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:48.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:43:48.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:43:48.19$vc4f8/valo=2,572.99 2006.134.07:43:48.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.07:43:48.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.07:43:48.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:48.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:48.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:48.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:48.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:43:48.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:48.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:48.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:43:48.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:43:48.26$vc4f8/va=2,7 2006.134.07:43:48.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.07:43:48.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.07:43:48.26#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:48.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:48.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:48.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:48.33#ibcon#[25=AT02-07\r\n] 2006.134.07:43:48.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:48.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:48.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.07:43:48.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:48.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:48.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:48.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:48.50#ibcon#[25=USB\r\n] 2006.134.07:43:48.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:48.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:48.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:43:48.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:43:48.53$vc4f8/valo=3,672.99 2006.134.07:43:48.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:43:48.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:43:48.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:48.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:48.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:48.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:48.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:43:48.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:48.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:48.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:43:48.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:43:48.60$vc4f8/va=3,6 2006.134.07:43:48.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.07:43:48.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.07:43:48.60#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:48.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:48.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:48.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:48.67#ibcon#[25=AT03-06\r\n] 2006.134.07:43:48.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:48.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:48.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.07:43:48.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:48.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:48.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:48.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:48.84#ibcon#[25=USB\r\n] 2006.134.07:43:48.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:48.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:48.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:43:48.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:43:48.87$vc4f8/valo=4,832.99 2006.134.07:43:48.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.07:43:48.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.07:43:48.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:48.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:48.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:48.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:48.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:43:48.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:48.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:48.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:43:48.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:43:48.93$vc4f8/va=4,7 2006.134.07:43:48.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.07:43:48.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.07:43:48.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:48.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:43:48.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:43:48.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:43:49.01#ibcon#[25=AT04-07\r\n] 2006.134.07:43:49.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:43:49.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:43:49.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.07:43:49.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:49.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:43:49.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:43:49.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:43:49.18#ibcon#[25=USB\r\n] 2006.134.07:43:49.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:43:49.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:43:49.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:43:49.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:43:49.21$vc4f8/valo=5,652.99 2006.134.07:43:49.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:43:49.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:43:49.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:49.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:43:49.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:43:49.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:43:49.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:43:49.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:43:49.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:43:49.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:43:49.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:43:49.27$vc4f8/va=5,6 2006.134.07:43:49.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.07:43:49.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.07:43:49.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:49.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:43:49.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:43:49.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:43:49.35#ibcon#[25=AT05-06\r\n] 2006.134.07:43:49.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:43:49.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:43:49.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.07:43:49.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:49.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:43:49.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:43:49.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:43:49.52#ibcon#[25=USB\r\n] 2006.134.07:43:49.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:43:49.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:43:49.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:43:49.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:43:49.55$vc4f8/valo=6,772.99 2006.134.07:43:49.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:43:49.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:43:49.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:49.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:49.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:49.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:49.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:43:49.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:49.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:49.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:43:49.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:43:49.61$vc4f8/va=6,5 2006.134.07:43:49.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.07:43:49.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.07:43:49.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:49.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:49.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:49.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:49.69#ibcon#[25=AT06-05\r\n] 2006.134.07:43:49.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:49.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:49.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.07:43:49.72#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:49.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:49.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:49.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:49.86#ibcon#[25=USB\r\n] 2006.134.07:43:49.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:49.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:49.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:43:49.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:43:49.89$vc4f8/valo=7,832.99 2006.134.07:43:49.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.07:43:49.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.07:43:49.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:49.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:49.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:49.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:49.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:43:49.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:49.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:49.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:43:49.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:43:49.95$vc4f8/va=7,5 2006.134.07:43:49.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.07:43:49.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.07:43:49.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:49.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:50.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:50.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:50.03#ibcon#[25=AT07-05\r\n] 2006.134.07:43:50.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:50.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:50.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.07:43:50.06#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:50.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:43:50.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:43:50.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:43:50.20#ibcon#[25=USB\r\n] 2006.134.07:43:50.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:43:50.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:43:50.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:43:50.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:43:50.23$vc4f8/valo=8,852.99 2006.134.07:43:50.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.07:43:50.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.07:43:50.23#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:50.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:43:50.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:43:50.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:43:50.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:43:50.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:43:50.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:43:50.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:43:50.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:43:50.30$vc4f8/va=8,6 2006.134.07:43:50.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.07:43:50.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.07:43:50.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:50.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:43:50.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:43:50.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:43:50.37#ibcon#[25=AT08-06\r\n] 2006.134.07:43:50.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:43:50.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:43:50.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.07:43:50.40#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:50.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:43:50.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:43:50.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:43:50.54#ibcon#[25=USB\r\n] 2006.134.07:43:50.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:43:50.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:43:50.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:43:50.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:43:50.57$vc4f8/vblo=1,632.99 2006.134.07:43:50.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:43:50.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:43:50.57#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:50.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:43:50.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:43:50.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:43:50.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:43:50.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:43:50.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:43:50.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:43:50.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:43:50.63$vc4f8/vb=1,4 2006.134.07:43:50.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.07:43:50.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.07:43:50.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:50.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:43:50.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:43:50.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:43:50.65#ibcon#[27=AT01-04\r\n] 2006.134.07:43:50.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:43:50.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:43:50.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.07:43:50.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:50.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:43:50.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:43:50.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:43:50.82#ibcon#[27=USB\r\n] 2006.134.07:43:50.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:43:50.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:43:50.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:43:50.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:43:50.85$vc4f8/vblo=2,640.99 2006.134.07:43:50.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:43:50.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:43:50.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:50.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:50.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:50.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:50.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:43:50.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:50.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:43:50.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:43:50.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:43:50.91$vc4f8/vb=2,4 2006.134.07:43:50.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.07:43:50.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.07:43:50.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:50.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:50.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:50.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:50.99#ibcon#[27=AT02-04\r\n] 2006.134.07:43:51.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:51.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:43:51.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.07:43:51.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:51.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:51.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:51.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:51.16#ibcon#[27=USB\r\n] 2006.134.07:43:51.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:51.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:43:51.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:43:51.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:43:51.19$vc4f8/vblo=3,656.99 2006.134.07:43:51.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.07:43:51.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.07:43:51.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:51.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:51.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:51.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:51.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:43:51.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:51.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:43:51.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:43:51.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:43:51.25$vc4f8/vb=3,4 2006.134.07:43:51.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.07:43:51.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.07:43:51.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:51.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:51.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:51.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:51.33#ibcon#[27=AT03-04\r\n] 2006.134.07:43:51.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:51.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:43:51.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.07:43:51.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:51.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:51.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:51.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:51.50#ibcon#[27=USB\r\n] 2006.134.07:43:51.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:51.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:43:51.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:43:51.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:43:51.53$vc4f8/vblo=4,712.99 2006.134.07:43:51.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:43:51.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:43:51.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:51.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:51.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:51.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:51.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:43:51.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:51.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:43:51.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:43:51.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:43:51.59$vc4f8/vb=4,4 2006.134.07:43:51.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.07:43:51.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.07:43:51.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:51.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:51.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:51.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:51.67#ibcon#[27=AT04-04\r\n] 2006.134.07:43:51.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:51.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:43:51.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.07:43:51.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:51.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:51.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:51.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:51.84#ibcon#[27=USB\r\n] 2006.134.07:43:51.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:51.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:43:51.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:43:51.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:43:51.87$vc4f8/vblo=5,744.99 2006.134.07:43:51.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.07:43:51.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.07:43:51.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:51.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:51.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:51.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:51.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:43:51.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:51.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:43:51.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:43:51.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:43:51.93$vc4f8/vb=5,4 2006.134.07:43:51.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:43:51.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:43:51.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:51.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:43:51.97#abcon#<5=/05 3.7 6.0 19.34 791006.5\r\n> 2006.134.07:43:51.99#abcon#{5=INTERFACE CLEAR} 2006.134.07:43:51.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:43:51.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:43:52.01#ibcon#[27=AT05-04\r\n] 2006.134.07:43:52.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:43:52.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:43:52.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:43:52.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:52.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:43:52.05#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:43:52.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:43:52.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:43:52.18#ibcon#[27=USB\r\n] 2006.134.07:43:52.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:43:52.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:43:52.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:43:52.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:43:52.21$vc4f8/vblo=6,752.99 2006.134.07:43:52.21#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:43:52.21#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:43:52.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:43:52.21#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:52.21#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:52.21#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:52.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:43:52.27#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:52.27#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:43:52.27#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:43:52.27#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:43:52.27$vc4f8/vb=6,4 2006.134.07:43:52.27#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.07:43:52.27#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.07:43:52.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:43:52.27#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:52.33#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:52.33#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:52.35#ibcon#[27=AT06-04\r\n] 2006.134.07:43:52.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:52.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:43:52.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.07:43:52.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:43:52.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:52.50#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:52.50#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:52.52#ibcon#[27=USB\r\n] 2006.134.07:43:52.55#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:52.55#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:43:52.55#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:43:52.55#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:43:52.55$vc4f8/vabw=wide 2006.134.07:43:52.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.07:43:52.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.07:43:52.55#ibcon#ireg 8 cls_cnt 0 2006.134.07:43:52.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:52.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:52.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:52.57#ibcon#[25=BW32\r\n] 2006.134.07:43:52.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:52.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:43:52.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:43:52.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:43:52.60$vc4f8/vbbw=wide 2006.134.07:43:52.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:43:52.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:43:52.60#ibcon#ireg 8 cls_cnt 0 2006.134.07:43:52.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:43:52.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:43:52.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:43:52.69#ibcon#[27=BW32\r\n] 2006.134.07:43:52.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:43:52.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:43:52.72#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:43:52.72#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:43:52.72$4f8m12a/ifd4f 2006.134.07:43:52.72$ifd4f/lo= 2006.134.07:43:52.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:43:52.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:43:52.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:43:52.72$ifd4f/patch= 2006.134.07:43:52.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:43:52.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:43:52.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:43:52.72$4f8m12a/"form=m,16.000,1:2 2006.134.07:43:52.72$4f8m12a/"tpicd 2006.134.07:43:52.73$4f8m12a/echo=off 2006.134.07:43:52.73$4f8m12a/xlog=off 2006.134.07:43:52.73:!2006.134.07:44:20 2006.134.07:44:01.14#trakl#Source acquired 2006.134.07:44:02.14#flagr#flagr/antenna,acquired 2006.134.07:44:20.01:preob 2006.134.07:44:21.14/onsource/TRACKING 2006.134.07:44:21.14:!2006.134.07:44:30 2006.134.07:44:30.00:data_valid=on 2006.134.07:44:30.00:midob 2006.134.07:44:30.14/onsource/TRACKING 2006.134.07:44:30.14/wx/19.34,1006.5,80 2006.134.07:44:30.28/cable/+6.5469E-03 2006.134.07:44:31.37/va/01,08,usb,yes,28,30 2006.134.07:44:31.37/va/02,07,usb,yes,28,30 2006.134.07:44:31.37/va/03,06,usb,yes,30,30 2006.134.07:44:31.37/va/04,07,usb,yes,29,31 2006.134.07:44:31.37/va/05,06,usb,yes,31,33 2006.134.07:44:31.37/va/06,05,usb,yes,31,31 2006.134.07:44:31.37/va/07,05,usb,yes,31,31 2006.134.07:44:31.37/va/08,06,usb,yes,29,28 2006.134.07:44:31.60/valo/01,532.99,yes,locked 2006.134.07:44:31.60/valo/02,572.99,yes,locked 2006.134.07:44:31.60/valo/03,672.99,yes,locked 2006.134.07:44:31.60/valo/04,832.99,yes,locked 2006.134.07:44:31.60/valo/05,652.99,yes,locked 2006.134.07:44:31.60/valo/06,772.99,yes,locked 2006.134.07:44:31.60/valo/07,832.99,yes,locked 2006.134.07:44:31.60/valo/08,852.99,yes,locked 2006.134.07:44:32.69/vb/01,04,usb,yes,28,27 2006.134.07:44:32.69/vb/02,04,usb,yes,30,31 2006.134.07:44:32.69/vb/03,04,usb,yes,26,30 2006.134.07:44:32.69/vb/04,04,usb,yes,27,27 2006.134.07:44:32.69/vb/05,04,usb,yes,26,30 2006.134.07:44:32.69/vb/06,04,usb,yes,27,29 2006.134.07:44:32.69/vb/07,04,usb,yes,29,29 2006.134.07:44:32.69/vb/08,04,usb,yes,26,30 2006.134.07:44:32.92/vblo/01,632.99,yes,locked 2006.134.07:44:32.92/vblo/02,640.99,yes,locked 2006.134.07:44:32.92/vblo/03,656.99,yes,locked 2006.134.07:44:32.92/vblo/04,712.99,yes,locked 2006.134.07:44:32.92/vblo/05,744.99,yes,locked 2006.134.07:44:32.92/vblo/06,752.99,yes,locked 2006.134.07:44:32.92/vblo/07,734.99,yes,locked 2006.134.07:44:32.92/vblo/08,744.99,yes,locked 2006.134.07:44:33.07/vabw/8 2006.134.07:44:33.22/vbbw/8 2006.134.07:44:33.31/xfe/off,on,14.5 2006.134.07:44:33.69/ifatt/23,28,28,28 2006.134.07:44:34.07/fmout-gps/S +1.79E-07 2006.134.07:44:34.11:!2006.134.07:45:30 2006.134.07:45:30.00:data_valid=off 2006.134.07:45:30.01:postob 2006.134.07:45:30.13/cable/+6.5457E-03 2006.134.07:45:30.14/wx/19.32,1006.5,81 2006.134.07:45:31.07/fmout-gps/S +1.79E-07 2006.134.07:45:31.08:scan_name=134-0747,k06134,110 2006.134.07:45:31.08:source=0508+138,051138.32,135719.2,2000.0,ccw 2006.134.07:45:31.14#flagr#flagr/antenna,new-source 2006.134.07:45:32.14:checkk5 2006.134.07:45:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:45:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:45:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:45:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:45:34.00/chk_obsdata//k5ts1/T1340744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:45:34.37/chk_obsdata//k5ts2/T1340744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:45:34.74/chk_obsdata//k5ts3/T1340744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:45:35.10/chk_obsdata//k5ts4/T1340744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:45:35.80/k5log//k5ts1_log_newline 2006.134.07:45:36.50/k5log//k5ts2_log_newline 2006.134.07:45:37.20/k5log//k5ts3_log_newline 2006.134.07:45:37.89/k5log//k5ts4_log_newline 2006.134.07:45:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:45:37.91:4f8m12a=1 2006.134.07:45:37.91$4f8m12a/echo=on 2006.134.07:45:37.91$4f8m12a/pcalon 2006.134.07:45:37.91$pcalon/"no phase cal control is implemented here 2006.134.07:45:37.91$4f8m12a/"tpicd=stop 2006.134.07:45:37.91$4f8m12a/vc4f8 2006.134.07:45:37.91$vc4f8/valo=1,532.99 2006.134.07:45:37.92#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:45:37.92#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:45:37.92#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:37.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:37.92#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:37.92#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:37.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:45:38.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:38.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:38.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:45:38.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:45:38.00$vc4f8/va=1,8 2006.134.07:45:38.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:45:38.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:45:38.00#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:38.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:38.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:38.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:38.03#ibcon#[25=AT01-08\r\n] 2006.134.07:45:38.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:38.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:38.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:45:38.06#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:38.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:38.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:38.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:38.22#ibcon#[25=USB\r\n] 2006.134.07:45:38.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:38.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:38.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:45:38.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:45:38.24$vc4f8/valo=2,572.99 2006.134.07:45:38.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:45:38.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:45:38.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:38.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:38.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:38.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:38.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:45:38.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:38.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:38.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:45:38.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:45:38.30$vc4f8/va=2,7 2006.134.07:45:38.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:45:38.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:45:38.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:38.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:38.38#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:38.38#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:38.39#ibcon#[25=AT02-07\r\n] 2006.134.07:45:38.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:38.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:38.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:45:38.42#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:38.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:38.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:38.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:38.56#ibcon#[25=USB\r\n] 2006.134.07:45:38.61#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:38.61#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:38.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:45:38.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:45:38.61$vc4f8/valo=3,672.99 2006.134.07:45:38.61#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:45:38.61#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:45:38.61#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:38.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:38.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:38.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:38.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:45:38.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:38.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:38.66#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:45:38.66#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:45:38.66$vc4f8/va=3,6 2006.134.07:45:38.66#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:45:38.66#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:45:38.66#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:38.66#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:38.73#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:38.73#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:38.75#ibcon#[25=AT03-06\r\n] 2006.134.07:45:38.78#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:38.78#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:38.78#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:45:38.78#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:38.78#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:38.90#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:38.90#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:38.92#ibcon#[25=USB\r\n] 2006.134.07:45:38.95#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:38.95#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:38.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:45:38.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:45:38.95$vc4f8/valo=4,832.99 2006.134.07:45:38.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:45:38.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:45:38.95#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:38.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:38.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:38.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:38.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:45:39.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:39.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:39.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:45:39.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:45:39.01$vc4f8/va=4,7 2006.134.07:45:39.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:45:39.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:45:39.01#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:39.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:39.07#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:39.07#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:39.09#ibcon#[25=AT04-07\r\n] 2006.134.07:45:39.12#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:39.12#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:39.12#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:45:39.12#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:39.12#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:39.24#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:39.24#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:39.26#ibcon#[25=USB\r\n] 2006.134.07:45:39.29#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:39.29#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:39.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:45:39.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:45:39.29$vc4f8/valo=5,652.99 2006.134.07:45:39.29#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:45:39.29#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:45:39.29#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:39.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:39.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:39.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:39.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:45:39.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:39.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:39.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:45:39.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:45:39.35$vc4f8/va=5,6 2006.134.07:45:39.35#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:45:39.35#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:45:39.35#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:39.35#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:39.41#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:39.41#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:39.43#ibcon#[25=AT05-06\r\n] 2006.134.07:45:39.46#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:39.46#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:39.46#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:45:39.46#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:39.46#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:39.58#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:39.58#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:39.60#ibcon#[25=USB\r\n] 2006.134.07:45:39.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:39.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:39.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:45:39.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:45:39.63$vc4f8/valo=6,772.99 2006.134.07:45:39.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.07:45:39.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.07:45:39.63#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:39.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:39.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:39.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:39.67#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:45:39.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:39.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:39.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:45:39.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:45:39.71$vc4f8/va=6,5 2006.134.07:45:39.71#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.07:45:39.71#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.07:45:39.71#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:39.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:39.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:39.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:39.77#ibcon#[25=AT06-05\r\n] 2006.134.07:45:39.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:39.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:39.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.07:45:39.80#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:39.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:45:39.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:45:39.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:45:39.94#ibcon#[25=USB\r\n] 2006.134.07:45:39.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:45:39.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:45:39.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:45:39.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:45:39.97$vc4f8/valo=7,832.99 2006.134.07:45:39.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.07:45:39.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.07:45:39.97#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:39.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:45:39.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:45:39.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:45:39.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:45:40.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:45:40.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:45:40.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:45:40.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:45:40.03$vc4f8/va=7,5 2006.134.07:45:40.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.07:45:40.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.07:45:40.03#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:40.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:45:40.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:45:40.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:45:40.11#ibcon#[25=AT07-05\r\n] 2006.134.07:45:40.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:45:40.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:45:40.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.07:45:40.14#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:40.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:45:40.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:45:40.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:45:40.28#ibcon#[25=USB\r\n] 2006.134.07:45:40.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:45:40.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:45:40.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:45:40.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:45:40.31$vc4f8/valo=8,852.99 2006.134.07:45:40.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:45:40.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:45:40.31#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:40.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:45:40.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:45:40.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:45:40.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:45:40.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:45:40.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:45:40.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:45:40.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:45:40.37$vc4f8/va=8,6 2006.134.07:45:40.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:45:40.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:45:40.37#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:40.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:45:40.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:45:40.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:45:40.45#ibcon#[25=AT08-06\r\n] 2006.134.07:45:40.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:45:40.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:45:40.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:45:40.48#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:40.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:45:40.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:45:40.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:45:40.62#ibcon#[25=USB\r\n] 2006.134.07:45:40.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:45:40.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:45:40.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:45:40.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:45:40.65$vc4f8/vblo=1,632.99 2006.134.07:45:40.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:45:40.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:45:40.65#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:40.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:45:40.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:45:40.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:45:40.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:45:40.71#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:45:40.71#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:45:40.71#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:45:40.71#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:45:40.71$vc4f8/vb=1,4 2006.134.07:45:40.71#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:45:40.71#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:45:40.71#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:40.71#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:45:40.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:45:40.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:45:40.73#ibcon#[27=AT01-04\r\n] 2006.134.07:45:40.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:45:40.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:45:40.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:45:40.76#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:40.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:45:40.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:45:40.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:45:40.90#ibcon#[27=USB\r\n] 2006.134.07:45:40.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:45:40.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:45:40.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:45:40.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:45:40.93$vc4f8/vblo=2,640.99 2006.134.07:45:40.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:45:40.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:45:40.93#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:40.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:40.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:40.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:40.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:45:40.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:40.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:45:40.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:45:40.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:45:40.99$vc4f8/vb=2,4 2006.134.07:45:40.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:45:40.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:45:40.99#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:40.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:41.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:41.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:41.07#ibcon#[27=AT02-04\r\n] 2006.134.07:45:41.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:41.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:45:41.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:45:41.10#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:41.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:41.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:41.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:41.24#ibcon#[27=USB\r\n] 2006.134.07:45:41.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:41.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:45:41.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:45:41.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:45:41.29$vc4f8/vblo=3,656.99 2006.134.07:45:41.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:45:41.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:45:41.29#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:41.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:41.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:41.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:41.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:45:41.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:41.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:45:41.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:45:41.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:45:41.34$vc4f8/vb=3,4 2006.134.07:45:41.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:45:41.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:45:41.34#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:41.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:41.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:41.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:41.43#ibcon#[27=AT03-04\r\n] 2006.134.07:45:41.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:41.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:45:41.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:45:41.46#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:41.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:41.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:41.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:41.60#ibcon#[27=USB\r\n] 2006.134.07:45:41.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:41.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:45:41.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:45:41.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:45:41.63$vc4f8/vblo=4,712.99 2006.134.07:45:41.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:45:41.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:45:41.63#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:41.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:41.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:41.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:41.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:45:41.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:41.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:45:41.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:45:41.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:45:41.69$vc4f8/vb=4,4 2006.134.07:45:41.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:45:41.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:45:41.69#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:41.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:41.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:41.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:41.77#ibcon#[27=AT04-04\r\n] 2006.134.07:45:41.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:41.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:45:41.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:45:41.80#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:41.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:41.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:41.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:41.94#ibcon#[27=USB\r\n] 2006.134.07:45:41.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:41.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:45:41.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:45:41.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:45:41.97$vc4f8/vblo=5,744.99 2006.134.07:45:41.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:45:41.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:45:41.97#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:41.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:41.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:41.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:41.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:45:42.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:42.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:45:42.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:45:42.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:45:42.03$vc4f8/vb=5,4 2006.134.07:45:42.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:45:42.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:45:42.03#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:42.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:42.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:42.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:42.12#ibcon#[27=AT05-04\r\n] 2006.134.07:45:42.15#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:42.15#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:45:42.15#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:45:42.15#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:42.15#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:42.27#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:42.27#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:42.29#ibcon#[27=USB\r\n] 2006.134.07:45:42.32#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:42.32#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:45:42.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:45:42.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:45:42.32$vc4f8/vblo=6,752.99 2006.134.07:45:42.32#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:45:42.32#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:45:42.32#ibcon#ireg 17 cls_cnt 0 2006.134.07:45:42.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:42.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:42.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:42.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:45:42.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:42.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:45:42.38#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:45:42.38#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:45:42.38$vc4f8/vb=6,4 2006.134.07:45:42.38#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:45:42.38#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:45:42.38#ibcon#ireg 11 cls_cnt 2 2006.134.07:45:42.38#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:42.44#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:42.44#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:42.46#ibcon#[27=AT06-04\r\n] 2006.134.07:45:42.49#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:42.49#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:45:42.49#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:45:42.49#ibcon#ireg 7 cls_cnt 0 2006.134.07:45:42.49#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:42.61#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:42.61#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:42.63#ibcon#[27=USB\r\n] 2006.134.07:45:42.66#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:42.66#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:45:42.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:45:42.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:45:42.66$vc4f8/vabw=wide 2006.134.07:45:42.66#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.07:45:42.66#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.07:45:42.66#ibcon#ireg 8 cls_cnt 0 2006.134.07:45:42.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:42.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:42.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:42.68#ibcon#[25=BW32\r\n] 2006.134.07:45:42.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:42.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:45:42.71#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:45:42.71#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:45:42.71$vc4f8/vbbw=wide 2006.134.07:45:42.71#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:45:42.71#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:45:42.71#ibcon#ireg 8 cls_cnt 0 2006.134.07:45:42.71#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:45:42.78#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:45:42.78#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:45:42.80#ibcon#[27=BW32\r\n] 2006.134.07:45:42.83#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:45:42.83#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:45:42.83#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:45:42.83#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:45:42.83$4f8m12a/ifd4f 2006.134.07:45:42.83$ifd4f/lo= 2006.134.07:45:42.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:45:42.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:45:42.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:45:42.83$ifd4f/patch= 2006.134.07:45:42.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:45:42.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:45:42.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:45:42.83$4f8m12a/"form=m,16.000,1:2 2006.134.07:45:42.83$4f8m12a/"tpicd 2006.134.07:45:42.83$4f8m12a/echo=off 2006.134.07:45:42.83$4f8m12a/xlog=off 2006.134.07:45:42.83:!2006.134.07:46:50 2006.134.07:46:28.14#trakl#Source acquired 2006.134.07:46:28.14#flagr#flagr/antenna,acquired 2006.134.07:46:50.00:preob 2006.134.07:46:50.14/onsource/TRACKING 2006.134.07:46:50.14:!2006.134.07:47:00 2006.134.07:47:00.00:data_valid=on 2006.134.07:47:00.00:midob 2006.134.07:47:01.14/onsource/TRACKING 2006.134.07:47:01.14/wx/19.30,1006.5,82 2006.134.07:47:01.21/cable/+6.5494E-03 2006.134.07:47:02.30/va/01,08,usb,yes,29,31 2006.134.07:47:02.30/va/02,07,usb,yes,29,30 2006.134.07:47:02.30/va/03,06,usb,yes,30,31 2006.134.07:47:02.30/va/04,07,usb,yes,30,32 2006.134.07:47:02.30/va/05,06,usb,yes,31,33 2006.134.07:47:02.30/va/06,05,usb,yes,31,31 2006.134.07:47:02.30/va/07,05,usb,yes,31,31 2006.134.07:47:02.30/va/08,06,usb,yes,29,28 2006.134.07:47:02.53/valo/01,532.99,yes,locked 2006.134.07:47:02.53/valo/02,572.99,yes,locked 2006.134.07:47:02.53/valo/03,672.99,yes,locked 2006.134.07:47:02.53/valo/04,832.99,yes,locked 2006.134.07:47:02.53/valo/05,652.99,yes,locked 2006.134.07:47:02.53/valo/06,772.99,yes,locked 2006.134.07:47:02.53/valo/07,832.99,yes,locked 2006.134.07:47:02.53/valo/08,852.99,yes,locked 2006.134.07:47:03.62/vb/01,04,usb,yes,28,27 2006.134.07:47:03.62/vb/02,04,usb,yes,30,32 2006.134.07:47:03.62/vb/03,04,usb,yes,27,30 2006.134.07:47:03.62/vb/04,04,usb,yes,27,28 2006.134.07:47:03.62/vb/05,04,usb,yes,26,30 2006.134.07:47:03.62/vb/06,04,usb,yes,27,30 2006.134.07:47:03.62/vb/07,04,usb,yes,29,29 2006.134.07:47:03.62/vb/08,04,usb,yes,27,30 2006.134.07:47:03.86/vblo/01,632.99,yes,locked 2006.134.07:47:03.86/vblo/02,640.99,yes,locked 2006.134.07:47:03.86/vblo/03,656.99,yes,locked 2006.134.07:47:03.86/vblo/04,712.99,yes,locked 2006.134.07:47:03.86/vblo/05,744.99,yes,locked 2006.134.07:47:03.86/vblo/06,752.99,yes,locked 2006.134.07:47:03.86/vblo/07,734.99,yes,locked 2006.134.07:47:03.86/vblo/08,744.99,yes,locked 2006.134.07:47:04.01/vabw/8 2006.134.07:47:04.16/vbbw/8 2006.134.07:47:04.25/xfe/off,on,15.0 2006.134.07:47:04.65/ifatt/23,28,28,28 2006.134.07:47:05.07/fmout-gps/S +1.79E-07 2006.134.07:47:05.11:!2006.134.07:48:50 2006.134.07:48:50.01:data_valid=off 2006.134.07:48:50.02:postob 2006.134.07:48:50.21/cable/+6.5495E-03 2006.134.07:48:50.22/wx/19.26,1006.6,82 2006.134.07:48:51.07/fmout-gps/S +1.79E-07 2006.134.07:48:51.08:scan_name=134-0750,k06134,60 2006.134.07:48:51.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.134.07:48:52.14#flagr#flagr/antenna,new-source 2006.134.07:48:52.15:checkk5 2006.134.07:48:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:48:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:48:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:48:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:48:54.01/chk_obsdata//k5ts1/T1340747??a.dat file size is correct (nominal:880MB, actual:872MB). 2006.134.07:48:54.37/chk_obsdata//k5ts2/T1340747??b.dat file size is correct (nominal:880MB, actual:872MB). 2006.134.07:48:54.74/chk_obsdata//k5ts3/T1340747??c.dat file size is correct (nominal:880MB, actual:872MB). 2006.134.07:48:55.11/chk_obsdata//k5ts4/T1340747??d.dat file size is correct (nominal:880MB, actual:872MB). 2006.134.07:48:55.80/k5log//k5ts1_log_newline 2006.134.07:48:56.48/k5log//k5ts2_log_newline 2006.134.07:48:57.17/k5log//k5ts3_log_newline 2006.134.07:48:57.86/k5log//k5ts4_log_newline 2006.134.07:48:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:48:57.88:4f8m12a=1 2006.134.07:48:57.88$4f8m12a/echo=on 2006.134.07:48:57.88$4f8m12a/pcalon 2006.134.07:48:57.88$pcalon/"no phase cal control is implemented here 2006.134.07:48:57.88$4f8m12a/"tpicd=stop 2006.134.07:48:57.88$4f8m12a/vc4f8 2006.134.07:48:57.89$vc4f8/valo=1,532.99 2006.134.07:48:57.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:48:57.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:48:57.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:57.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:48:57.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:48:57.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:48:57.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:48:57.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:48:57.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:48:57.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:48:57.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:48:57.95$vc4f8/va=1,8 2006.134.07:48:57.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.07:48:57.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.07:48:57.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:57.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:48:57.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:48:57.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:48:57.97#ibcon#[25=AT01-08\r\n] 2006.134.07:48:58.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:48:58.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:48:58.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.07:48:58.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:58.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:48:58.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:48:58.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:48:58.14#ibcon#[25=USB\r\n] 2006.134.07:48:58.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:48:58.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:48:58.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:48:58.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:48:58.17$vc4f8/valo=2,572.99 2006.134.07:48:58.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:48:58.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:48:58.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:58.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:48:58.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:48:58.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:48:58.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:48:58.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:48:58.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:48:58.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:48:58.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:48:58.24$vc4f8/va=2,7 2006.134.07:48:58.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:48:58.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:48:58.24#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:58.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:48:58.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:48:58.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:48:58.31#ibcon#[25=AT02-07\r\n] 2006.134.07:48:58.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:48:58.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:48:58.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:48:58.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:58.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:48:58.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:48:58.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:48:58.48#ibcon#[25=USB\r\n] 2006.134.07:48:58.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:48:58.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:48:58.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:48:58.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:48:58.51$vc4f8/valo=3,672.99 2006.134.07:48:58.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:48:58.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:48:58.51#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:58.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:48:58.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:48:58.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:48:58.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:48:58.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:48:58.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:48:58.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:48:58.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:48:58.58$vc4f8/va=3,6 2006.134.07:48:58.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:48:58.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:48:58.58#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:58.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:48:58.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:48:58.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:48:58.65#ibcon#[25=AT03-06\r\n] 2006.134.07:48:58.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:48:58.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:48:58.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:48:58.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:58.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:48:58.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:48:58.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:48:58.82#ibcon#[25=USB\r\n] 2006.134.07:48:58.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:48:58.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:48:58.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:48:58.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:48:58.85$vc4f8/valo=4,832.99 2006.134.07:48:58.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:48:58.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:48:58.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:58.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:48:58.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:48:58.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:48:58.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:48:58.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:48:58.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:48:58.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:48:58.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:48:58.91$vc4f8/va=4,7 2006.134.07:48:58.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:48:58.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:48:58.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:58.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:48:58.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:48:58.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:48:58.99#ibcon#[25=AT04-07\r\n] 2006.134.07:48:59.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:48:59.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:48:59.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:48:59.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:59.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:48:59.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:48:59.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:48:59.16#ibcon#[25=USB\r\n] 2006.134.07:48:59.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:48:59.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:48:59.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:48:59.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:48:59.19$vc4f8/valo=5,652.99 2006.134.07:48:59.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:48:59.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:48:59.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:59.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:48:59.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:48:59.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:48:59.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:48:59.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:48:59.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:48:59.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:48:59.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:48:59.25$vc4f8/va=5,6 2006.134.07:48:59.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:48:59.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:48:59.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:59.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:48:59.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:48:59.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:48:59.33#ibcon#[25=AT05-06\r\n] 2006.134.07:48:59.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:48:59.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:48:59.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:48:59.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:59.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:48:59.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:48:59.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:48:59.50#ibcon#[25=USB\r\n] 2006.134.07:48:59.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:48:59.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:48:59.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:48:59.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:48:59.53$vc4f8/valo=6,772.99 2006.134.07:48:59.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:48:59.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:48:59.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:59.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:48:59.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:48:59.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:48:59.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:48:59.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:48:59.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:48:59.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:48:59.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:48:59.59$vc4f8/va=6,5 2006.134.07:48:59.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:48:59.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:48:59.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:59.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:48:59.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:48:59.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:48:59.67#ibcon#[25=AT06-05\r\n] 2006.134.07:48:59.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:48:59.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:48:59.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:48:59.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:48:59.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:48:59.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:48:59.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:48:59.84#ibcon#[25=USB\r\n] 2006.134.07:48:59.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:48:59.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:48:59.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:48:59.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:48:59.87$vc4f8/valo=7,832.99 2006.134.07:48:59.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:48:59.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:48:59.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:48:59.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:48:59.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:48:59.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:48:59.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:48:59.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:48:59.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:48:59.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:48:59.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:48:59.93$vc4f8/va=7,5 2006.134.07:48:59.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:48:59.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:48:59.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:48:59.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:48:59.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:48:59.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:49:00.01#ibcon#[25=AT07-05\r\n] 2006.134.07:49:00.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:49:00.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:49:00.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:49:00.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:00.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:49:00.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:49:00.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:49:00.18#ibcon#[25=USB\r\n] 2006.134.07:49:00.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:49:00.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:49:00.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:49:00.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:49:00.21$vc4f8/valo=8,852.99 2006.134.07:49:00.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:49:00.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:49:00.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:00.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:49:00.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:49:00.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:49:00.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:49:00.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:49:00.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:49:00.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:49:00.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:49:00.27$vc4f8/va=8,6 2006.134.07:49:00.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:49:00.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:49:00.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:00.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:49:00.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:49:00.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:49:00.35#ibcon#[25=AT08-06\r\n] 2006.134.07:49:00.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:49:00.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:49:00.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:49:00.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:00.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:49:00.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:49:00.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:49:00.52#ibcon#[25=USB\r\n] 2006.134.07:49:00.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:49:00.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:49:00.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:49:00.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:49:00.55$vc4f8/vblo=1,632.99 2006.134.07:49:00.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:49:00.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:49:00.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:00.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:49:00.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:49:00.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:49:00.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:49:00.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:49:00.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:49:00.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:49:00.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:49:00.61$vc4f8/vb=1,4 2006.134.07:49:00.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:49:00.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:49:00.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:00.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:49:00.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:49:00.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:49:00.63#ibcon#[27=AT01-04\r\n] 2006.134.07:49:00.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:49:00.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:49:00.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:49:00.66#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:00.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:49:00.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:49:00.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:49:00.80#ibcon#[27=USB\r\n] 2006.134.07:49:00.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:49:00.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:49:00.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:49:00.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:49:00.83$vc4f8/vblo=2,640.99 2006.134.07:49:00.83#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:49:00.83#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:49:00.83#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:00.83#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:49:00.83#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:49:00.83#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:49:00.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:49:00.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:49:00.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:49:00.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:49:00.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:49:00.89$vc4f8/vb=2,4 2006.134.07:49:00.89#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.07:49:00.89#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.07:49:00.89#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:00.89#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:49:00.95#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:49:00.95#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:49:00.97#ibcon#[27=AT02-04\r\n] 2006.134.07:49:01.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:49:01.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:49:01.00#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.07:49:01.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:01.00#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:49:01.12#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:49:01.12#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:49:01.14#ibcon#[27=USB\r\n] 2006.134.07:49:01.17#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:49:01.17#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:49:01.17#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:49:01.17#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:49:01.17$vc4f8/vblo=3,656.99 2006.134.07:49:01.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:49:01.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:49:01.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:01.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:49:01.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:49:01.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:49:01.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:49:01.23#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:49:01.23#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:49:01.23#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:49:01.23#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:49:01.23$vc4f8/vb=3,4 2006.134.07:49:01.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:49:01.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:49:01.23#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:01.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:49:01.29#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:49:01.29#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:49:01.31#ibcon#[27=AT03-04\r\n] 2006.134.07:49:01.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:49:01.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:49:01.34#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:49:01.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:01.34#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:49:01.46#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:49:01.46#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:49:01.48#ibcon#[27=USB\r\n] 2006.134.07:49:01.51#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:49:01.51#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:49:01.51#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:49:01.51#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:49:01.51$vc4f8/vblo=4,712.99 2006.134.07:49:01.51#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:49:01.51#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:49:01.51#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:01.51#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:49:01.51#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:49:01.51#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:49:01.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:49:01.57#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:49:01.57#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:49:01.57#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:49:01.57#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:49:01.57$vc4f8/vb=4,4 2006.134.07:49:01.57#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:49:01.57#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:49:01.57#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:01.57#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:49:01.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:49:01.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:49:01.65#ibcon#[27=AT04-04\r\n] 2006.134.07:49:01.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:49:01.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:49:01.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:49:01.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:01.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:49:01.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:49:01.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:49:01.82#ibcon#[27=USB\r\n] 2006.134.07:49:01.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:49:01.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:49:01.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:49:01.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:49:01.85$vc4f8/vblo=5,744.99 2006.134.07:49:01.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:49:01.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:49:01.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:01.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:49:01.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:49:01.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:49:01.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:49:01.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:49:01.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:49:01.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:49:01.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:49:01.91$vc4f8/vb=5,4 2006.134.07:49:01.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:49:01.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:49:01.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:01.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:49:01.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:49:01.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:49:01.99#ibcon#[27=AT05-04\r\n] 2006.134.07:49:02.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:49:02.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:49:02.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:49:02.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:02.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:49:02.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:49:02.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:49:02.16#ibcon#[27=USB\r\n] 2006.134.07:49:02.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:49:02.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:49:02.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:49:02.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:49:02.19$vc4f8/vblo=6,752.99 2006.134.07:49:02.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:49:02.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:49:02.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:49:02.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:49:02.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:49:02.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:49:02.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:49:02.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:49:02.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:49:02.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:49:02.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:49:02.25$vc4f8/vb=6,4 2006.134.07:49:02.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:49:02.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:49:02.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:49:02.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:49:02.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:49:02.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:49:02.33#ibcon#[27=AT06-04\r\n] 2006.134.07:49:02.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:49:02.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:49:02.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:49:02.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:49:02.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:49:02.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:49:02.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:49:02.50#ibcon#[27=USB\r\n] 2006.134.07:49:02.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:49:02.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:49:02.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:49:02.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:49:02.53$vc4f8/vabw=wide 2006.134.07:49:02.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:49:02.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:49:02.53#ibcon#ireg 8 cls_cnt 0 2006.134.07:49:02.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:49:02.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:49:02.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:49:02.55#ibcon#[25=BW32\r\n] 2006.134.07:49:02.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:49:02.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:49:02.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:49:02.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:49:02.58$vc4f8/vbbw=wide 2006.134.07:49:02.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:49:02.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:49:02.58#ibcon#ireg 8 cls_cnt 0 2006.134.07:49:02.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:49:02.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:49:02.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:49:02.67#ibcon#[27=BW32\r\n] 2006.134.07:49:02.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:49:02.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:49:02.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:49:02.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:49:02.70$4f8m12a/ifd4f 2006.134.07:49:02.70$ifd4f/lo= 2006.134.07:49:02.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:49:02.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:49:02.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:49:02.70$ifd4f/patch= 2006.134.07:49:02.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:49:02.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:49:02.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:49:02.70$4f8m12a/"form=m,16.000,1:2 2006.134.07:49:02.70$4f8m12a/"tpicd 2006.134.07:49:02.70$4f8m12a/echo=off 2006.134.07:49:02.70$4f8m12a/xlog=off 2006.134.07:49:02.70:!2006.134.07:50:00 2006.134.07:49:38.13#trakl#Source acquired 2006.134.07:49:39.13#flagr#flagr/antenna,acquired 2006.134.07:50:00.00:preob 2006.134.07:50:01.13/onsource/TRACKING 2006.134.07:50:01.13:!2006.134.07:50:10 2006.134.07:50:10.00:data_valid=on 2006.134.07:50:10.00:midob 2006.134.07:50:10.13/onsource/TRACKING 2006.134.07:50:10.13/wx/19.23,1006.6,82 2006.134.07:50:10.20/cable/+6.5464E-03 2006.134.07:50:11.29/va/01,08,usb,yes,30,31 2006.134.07:50:11.29/va/02,07,usb,yes,30,31 2006.134.07:50:11.29/va/03,06,usb,yes,31,32 2006.134.07:50:11.29/va/04,07,usb,yes,30,33 2006.134.07:50:11.29/va/05,06,usb,yes,32,34 2006.134.07:50:11.29/va/06,05,usb,yes,32,32 2006.134.07:50:11.29/va/07,05,usb,yes,32,32 2006.134.07:50:11.29/va/08,06,usb,yes,30,29 2006.134.07:50:11.52/valo/01,532.99,yes,locked 2006.134.07:50:11.52/valo/02,572.99,yes,locked 2006.134.07:50:11.52/valo/03,672.99,yes,locked 2006.134.07:50:11.52/valo/04,832.99,yes,locked 2006.134.07:50:11.52/valo/05,652.99,yes,locked 2006.134.07:50:11.52/valo/06,772.99,yes,locked 2006.134.07:50:11.52/valo/07,832.99,yes,locked 2006.134.07:50:11.52/valo/08,852.99,yes,locked 2006.134.07:50:12.61/vb/01,04,usb,yes,28,27 2006.134.07:50:12.61/vb/02,04,usb,yes,30,32 2006.134.07:50:12.61/vb/03,04,usb,yes,27,30 2006.134.07:50:12.61/vb/04,04,usb,yes,28,28 2006.134.07:50:12.61/vb/05,04,usb,yes,26,30 2006.134.07:50:12.61/vb/06,04,usb,yes,27,30 2006.134.07:50:12.61/vb/07,04,usb,yes,29,29 2006.134.07:50:12.61/vb/08,04,usb,yes,27,30 2006.134.07:50:12.84/vblo/01,632.99,yes,locked 2006.134.07:50:12.84/vblo/02,640.99,yes,locked 2006.134.07:50:12.84/vblo/03,656.99,yes,locked 2006.134.07:50:12.84/vblo/04,712.99,yes,locked 2006.134.07:50:12.84/vblo/05,744.99,yes,locked 2006.134.07:50:12.84/vblo/06,752.99,yes,locked 2006.134.07:50:12.84/vblo/07,734.99,yes,locked 2006.134.07:50:12.84/vblo/08,744.99,yes,locked 2006.134.07:50:12.99/vabw/8 2006.134.07:50:13.14/vbbw/8 2006.134.07:50:13.23/xfe/off,on,15.2 2006.134.07:50:13.60/ifatt/23,28,28,28 2006.134.07:50:14.07/fmout-gps/S +1.78E-07 2006.134.07:50:14.11:!2006.134.07:51:10 2006.134.07:51:10.01:data_valid=off 2006.134.07:51:10.02:postob 2006.134.07:51:10.13/cable/+6.5428E-03 2006.134.07:51:10.14/wx/19.21,1006.7,82 2006.134.07:51:11.07/fmout-gps/S +1.78E-07 2006.134.07:51:11.07:scan_name=134-0752,k06134,60 2006.134.07:51:11.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.134.07:51:11.13#flagr#flagr/antenna,new-source 2006.134.07:51:12.14:checkk5 2006.134.07:51:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:51:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:51:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:51:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:51:14.01/chk_obsdata//k5ts1/T1340750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:51:14.38/chk_obsdata//k5ts2/T1340750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:51:14.74/chk_obsdata//k5ts3/T1340750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:51:15.11/chk_obsdata//k5ts4/T1340750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:51:15.80/k5log//k5ts1_log_newline 2006.134.07:51:16.48/k5log//k5ts2_log_newline 2006.134.07:51:17.17/k5log//k5ts3_log_newline 2006.134.07:51:17.86/k5log//k5ts4_log_newline 2006.134.07:51:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:51:17.88:4f8m12a=1 2006.134.07:51:17.88$4f8m12a/echo=on 2006.134.07:51:17.89$4f8m12a/pcalon 2006.134.07:51:17.89$pcalon/"no phase cal control is implemented here 2006.134.07:51:17.89$4f8m12a/"tpicd=stop 2006.134.07:51:17.89$4f8m12a/vc4f8 2006.134.07:51:17.89$vc4f8/valo=1,532.99 2006.134.07:51:17.89#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:51:17.89#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:51:17.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:17.89#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:17.89#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:17.89#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:51:17.95#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:17.95#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:17.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:51:17.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:51:17.95$vc4f8/va=1,8 2006.134.07:51:17.95#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.07:51:17.95#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.07:51:17.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:17.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:17.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:17.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:17.97#ibcon#[25=AT01-08\r\n] 2006.134.07:51:18.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:18.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:18.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.07:51:18.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:18.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:18.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:18.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:18.14#ibcon#[25=USB\r\n] 2006.134.07:51:18.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:18.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:18.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:51:18.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:51:18.17$vc4f8/valo=2,572.99 2006.134.07:51:18.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.07:51:18.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.07:51:18.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:18.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:18.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:18.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:18.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:51:18.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:18.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:18.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:51:18.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:51:18.24$vc4f8/va=2,7 2006.134.07:51:18.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.07:51:18.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.07:51:18.24#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:18.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:18.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:18.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:18.31#ibcon#[25=AT02-07\r\n] 2006.134.07:51:18.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:18.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:18.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.07:51:18.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:18.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:18.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:18.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:18.48#ibcon#[25=USB\r\n] 2006.134.07:51:18.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:18.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:18.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:51:18.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:51:18.51$vc4f8/valo=3,672.99 2006.134.07:51:18.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:51:18.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:51:18.51#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:18.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:18.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:18.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:18.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:51:18.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:18.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:18.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:51:18.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:51:18.58$vc4f8/va=3,6 2006.134.07:51:18.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.07:51:18.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.07:51:18.58#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:18.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:18.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:18.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:18.65#ibcon#[25=AT03-06\r\n] 2006.134.07:51:18.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:18.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:18.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.07:51:18.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:18.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:18.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:18.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:18.82#ibcon#[25=USB\r\n] 2006.134.07:51:18.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:18.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:18.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:51:18.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:51:18.85$vc4f8/valo=4,832.99 2006.134.07:51:18.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.07:51:18.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.07:51:18.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:18.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:18.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:18.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:51:18.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:18.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:18.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:51:18.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:51:18.91$vc4f8/va=4,7 2006.134.07:51:18.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.07:51:18.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.07:51:18.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:18.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:18.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:18.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:18.99#ibcon#[25=AT04-07\r\n] 2006.134.07:51:19.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:19.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:19.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.07:51:19.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:19.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:19.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:19.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:19.16#ibcon#[25=USB\r\n] 2006.134.07:51:19.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:19.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:19.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:51:19.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:51:19.19$vc4f8/valo=5,652.99 2006.134.07:51:19.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:51:19.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:51:19.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:19.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:19.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:19.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:19.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:51:19.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:19.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:19.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:51:19.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:51:19.25$vc4f8/va=5,6 2006.134.07:51:19.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.07:51:19.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.07:51:19.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:19.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:19.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:19.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:19.33#ibcon#[25=AT05-06\r\n] 2006.134.07:51:19.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:19.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:19.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.07:51:19.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:19.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:19.47#abcon#<5=/04 3.5 5.5 19.20 821006.7\r\n> 2006.134.07:51:19.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:19.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:19.49#abcon#{5=INTERFACE CLEAR} 2006.134.07:51:19.50#ibcon#[25=USB\r\n] 2006.134.07:51:19.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:19.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:19.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:51:19.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:51:19.53$vc4f8/valo=6,772.99 2006.134.07:51:19.53#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:51:19.53#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:51:19.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:19.53#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:51:19.53#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:51:19.53#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:51:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:51:19.55#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:51:19.59#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:51:19.59#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:51:19.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:51:19.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:51:19.59$vc4f8/va=6,5 2006.134.07:51:19.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.07:51:19.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.07:51:19.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:19.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:19.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:19.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:19.67#ibcon#[25=AT06-05\r\n] 2006.134.07:51:19.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:19.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:19.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.07:51:19.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:19.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:51:19.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:51:19.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:51:19.84#ibcon#[25=USB\r\n] 2006.134.07:51:19.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:51:19.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.07:51:19.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:51:19.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:51:19.87$vc4f8/valo=7,832.99 2006.134.07:51:19.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.07:51:19.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.07:51:19.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:19.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:51:19.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:51:19.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:51:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:51:19.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:51:19.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.07:51:19.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:51:19.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:51:19.93$vc4f8/va=7,5 2006.134.07:51:19.93#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.07:51:19.93#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.07:51:19.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:19.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:51:19.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:51:19.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:51:20.01#ibcon#[25=AT07-05\r\n] 2006.134.07:51:20.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:51:20.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.07:51:20.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.07:51:20.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:20.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:51:20.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:51:20.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:51:20.18#ibcon#[25=USB\r\n] 2006.134.07:51:20.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:51:20.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.07:51:20.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:51:20.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:51:20.21$vc4f8/valo=8,852.99 2006.134.07:51:20.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.07:51:20.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.07:51:20.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:20.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:51:20.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:51:20.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:51:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:51:20.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:51:20.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.07:51:20.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:51:20.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:51:20.27$vc4f8/va=8,6 2006.134.07:51:20.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.07:51:20.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.07:51:20.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:20.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:51:20.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:51:20.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:51:20.35#ibcon#[25=AT08-06\r\n] 2006.134.07:51:20.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:51:20.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.07:51:20.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.07:51:20.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:20.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:51:20.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:51:20.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:51:20.52#ibcon#[25=USB\r\n] 2006.134.07:51:20.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:51:20.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.07:51:20.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:51:20.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:51:20.55$vc4f8/vblo=1,632.99 2006.134.07:51:20.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.07:51:20.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.07:51:20.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:20.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:20.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:20.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:51:20.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:20.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.07:51:20.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:51:20.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:51:20.61$vc4f8/vb=1,4 2006.134.07:51:20.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.07:51:20.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.07:51:20.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:20.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:20.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:20.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:20.63#ibcon#[27=AT01-04\r\n] 2006.134.07:51:20.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:20.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.07:51:20.66#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.07:51:20.66#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:20.66#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:20.78#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:20.78#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:20.80#ibcon#[27=USB\r\n] 2006.134.07:51:20.83#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:20.83#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.07:51:20.83#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:51:20.83#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:51:20.83$vc4f8/vblo=2,640.99 2006.134.07:51:20.83#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.07:51:20.83#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.07:51:20.83#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:20.83#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:20.83#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:20.83#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:51:20.89#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:20.89#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.07:51:20.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:51:20.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:51:20.89$vc4f8/vb=2,4 2006.134.07:51:20.89#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.07:51:20.89#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.07:51:20.89#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:20.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:20.95#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:20.95#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:20.97#ibcon#[27=AT02-04\r\n] 2006.134.07:51:21.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:21.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.07:51:21.00#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.07:51:21.00#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:21.00#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:21.12#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:21.12#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:21.14#ibcon#[27=USB\r\n] 2006.134.07:51:21.17#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:21.17#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.07:51:21.17#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:51:21.17#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:51:21.17$vc4f8/vblo=3,656.99 2006.134.07:51:21.17#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.07:51:21.17#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.07:51:21.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:21.17#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:21.17#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:21.17#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:51:21.23#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:21.23#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.07:51:21.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:51:21.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:51:21.23$vc4f8/vb=3,4 2006.134.07:51:21.23#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.07:51:21.23#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.07:51:21.23#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:21.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:21.29#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:21.29#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:21.31#ibcon#[27=AT03-04\r\n] 2006.134.07:51:21.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:21.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.07:51:21.34#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.07:51:21.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:21.34#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:21.46#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:21.46#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:21.48#ibcon#[27=USB\r\n] 2006.134.07:51:21.51#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:21.51#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.07:51:21.51#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:51:21.51#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:51:21.51$vc4f8/vblo=4,712.99 2006.134.07:51:21.51#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.07:51:21.51#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.07:51:21.51#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:21.51#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:21.51#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:21.51#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:51:21.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:21.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.07:51:21.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:51:21.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:51:21.57$vc4f8/vb=4,4 2006.134.07:51:21.57#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.07:51:21.57#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.07:51:21.57#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:21.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:21.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:21.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:21.65#ibcon#[27=AT04-04\r\n] 2006.134.07:51:21.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:21.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.07:51:21.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.07:51:21.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:21.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:21.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:21.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:21.82#ibcon#[27=USB\r\n] 2006.134.07:51:21.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:21.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.07:51:21.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:51:21.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:51:21.85$vc4f8/vblo=5,744.99 2006.134.07:51:21.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:51:21.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:51:21.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:21.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:21.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:21.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:51:21.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:21.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:51:21.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:51:21.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:51:21.91$vc4f8/vb=5,4 2006.134.07:51:21.91#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.07:51:21.91#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.07:51:21.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:21.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:21.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:21.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:21.99#ibcon#[27=AT05-04\r\n] 2006.134.07:51:22.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:22.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.07:51:22.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.07:51:22.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:22.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:22.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:22.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:22.16#ibcon#[27=USB\r\n] 2006.134.07:51:22.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:22.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.07:51:22.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:51:22.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:51:22.19$vc4f8/vblo=6,752.99 2006.134.07:51:22.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.07:51:22.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.07:51:22.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:51:22.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:51:22.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:51:22.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:51:22.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:51:22.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:51:22.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.07:51:22.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:51:22.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:51:22.25$vc4f8/vb=6,4 2006.134.07:51:22.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.07:51:22.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.07:51:22.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:51:22.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:51:22.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:51:22.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:51:22.33#ibcon#[27=AT06-04\r\n] 2006.134.07:51:22.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:51:22.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.07:51:22.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.07:51:22.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:51:22.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:51:22.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:51:22.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:51:22.50#ibcon#[27=USB\r\n] 2006.134.07:51:22.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:51:22.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.07:51:22.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:51:22.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:51:22.53$vc4f8/vabw=wide 2006.134.07:51:22.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.07:51:22.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.07:51:22.53#ibcon#ireg 8 cls_cnt 0 2006.134.07:51:22.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:51:22.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:51:22.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:51:22.56#ibcon#[25=BW32\r\n] 2006.134.07:51:22.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:51:22.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.07:51:22.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:51:22.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:51:22.59$vc4f8/vbbw=wide 2006.134.07:51:22.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:51:22.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:51:22.59#ibcon#ireg 8 cls_cnt 0 2006.134.07:51:22.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:51:22.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:51:22.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:51:22.67#ibcon#[27=BW32\r\n] 2006.134.07:51:22.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:51:22.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:51:22.70#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:51:22.70#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:51:22.70$4f8m12a/ifd4f 2006.134.07:51:22.70$ifd4f/lo= 2006.134.07:51:22.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:51:22.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:51:22.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:51:22.70$ifd4f/patch= 2006.134.07:51:22.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:51:22.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:51:22.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:51:22.70$4f8m12a/"form=m,16.000,1:2 2006.134.07:51:22.70$4f8m12a/"tpicd 2006.134.07:51:22.70$4f8m12a/echo=off 2006.134.07:51:22.70$4f8m12a/xlog=off 2006.134.07:51:22.70:!2006.134.07:51:50 2006.134.07:51:28.14#trakl#Source acquired 2006.134.07:51:29.14#flagr#flagr/antenna,acquired 2006.134.07:51:50.00:preob 2006.134.07:51:51.14/onsource/TRACKING 2006.134.07:51:51.14:!2006.134.07:52:00 2006.134.07:52:00.00:data_valid=on 2006.134.07:52:00.00:midob 2006.134.07:52:00.14/onsource/TRACKING 2006.134.07:52:00.14/wx/19.19,1006.7,81 2006.134.07:52:00.28/cable/+6.5461E-03 2006.134.07:52:01.37/va/01,08,usb,yes,30,32 2006.134.07:52:01.37/va/02,07,usb,yes,30,32 2006.134.07:52:01.37/va/03,06,usb,yes,32,32 2006.134.07:52:01.37/va/04,07,usb,yes,31,33 2006.134.07:52:01.37/va/05,06,usb,yes,33,35 2006.134.07:52:01.37/va/06,05,usb,yes,33,33 2006.134.07:52:01.37/va/07,05,usb,yes,33,33 2006.134.07:52:01.37/va/08,06,usb,yes,31,30 2006.134.07:52:01.60/valo/01,532.99,yes,locked 2006.134.07:52:01.60/valo/02,572.99,yes,locked 2006.134.07:52:01.60/valo/03,672.99,yes,locked 2006.134.07:52:01.60/valo/04,832.99,yes,locked 2006.134.07:52:01.60/valo/05,652.99,yes,locked 2006.134.07:52:01.60/valo/06,772.99,yes,locked 2006.134.07:52:01.60/valo/07,832.99,yes,locked 2006.134.07:52:01.60/valo/08,852.99,yes,locked 2006.134.07:52:02.69/vb/01,04,usb,yes,29,28 2006.134.07:52:02.69/vb/02,04,usb,yes,31,32 2006.134.07:52:02.69/vb/03,04,usb,yes,27,31 2006.134.07:52:02.69/vb/04,04,usb,yes,28,28 2006.134.07:52:02.69/vb/05,04,usb,yes,26,30 2006.134.07:52:02.69/vb/06,04,usb,yes,28,30 2006.134.07:52:02.69/vb/07,04,usb,yes,29,29 2006.134.07:52:02.69/vb/08,04,usb,yes,27,30 2006.134.07:52:02.92/vblo/01,632.99,yes,locked 2006.134.07:52:02.92/vblo/02,640.99,yes,locked 2006.134.07:52:02.92/vblo/03,656.99,yes,locked 2006.134.07:52:02.92/vblo/04,712.99,yes,locked 2006.134.07:52:02.92/vblo/05,744.99,yes,locked 2006.134.07:52:02.92/vblo/06,752.99,yes,locked 2006.134.07:52:02.92/vblo/07,734.99,yes,locked 2006.134.07:52:02.92/vblo/08,744.99,yes,locked 2006.134.07:52:03.07/vabw/8 2006.134.07:52:03.22/vbbw/8 2006.134.07:52:03.31/xfe/off,on,15.0 2006.134.07:52:03.71/ifatt/23,28,28,28 2006.134.07:52:04.07/fmout-gps/S +1.79E-07 2006.134.07:52:04.11:!2006.134.07:53:00 2006.134.07:53:00.01:data_valid=off 2006.134.07:53:00.02:postob 2006.134.07:53:00.21/cable/+6.5458E-03 2006.134.07:53:00.21/wx/19.16,1006.7,81 2006.134.07:53:01.07/fmout-gps/S +1.78E-07 2006.134.07:53:01.07:scan_name=134-0753,k06134,60 2006.134.07:53:01.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.134.07:53:01.15#flagr#flagr/antenna,new-source 2006.134.07:53:02.13:checkk5 2006.134.07:53:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:53:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:53:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:53:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:53:03.99/chk_obsdata//k5ts1/T1340752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:53:04.35/chk_obsdata//k5ts2/T1340752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:53:04.72/chk_obsdata//k5ts3/T1340752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:53:05.09/chk_obsdata//k5ts4/T1340752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:53:05.77/k5log//k5ts1_log_newline 2006.134.07:53:06.46/k5log//k5ts2_log_newline 2006.134.07:53:07.15/k5log//k5ts3_log_newline 2006.134.07:53:07.84/k5log//k5ts4_log_newline 2006.134.07:53:07.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:53:07.86:4f8m12a=1 2006.134.07:53:07.86$4f8m12a/echo=on 2006.134.07:53:07.86$4f8m12a/pcalon 2006.134.07:53:07.86$pcalon/"no phase cal control is implemented here 2006.134.07:53:07.86$4f8m12a/"tpicd=stop 2006.134.07:53:07.86$4f8m12a/vc4f8 2006.134.07:53:07.86$vc4f8/valo=1,532.99 2006.134.07:53:07.87#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:53:07.87#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:53:07.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:07.87#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:07.87#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:07.87#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:07.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:53:07.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:07.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:07.93#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:53:07.93#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:53:07.93$vc4f8/va=1,8 2006.134.07:53:07.93#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.07:53:07.93#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.07:53:07.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:07.93#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:07.93#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:07.93#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:07.95#ibcon#[25=AT01-08\r\n] 2006.134.07:53:07.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:07.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:07.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.07:53:07.99#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:07.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:08.10#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:08.10#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:08.12#ibcon#[25=USB\r\n] 2006.134.07:53:08.17#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:08.17#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:08.17#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:53:08.17#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:53:08.17$vc4f8/valo=2,572.99 2006.134.07:53:08.17#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:53:08.17#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:53:08.17#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:08.17#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:08.17#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:08.17#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:08.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:53:08.22#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:08.22#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:08.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:53:08.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:53:08.22$vc4f8/va=2,7 2006.134.07:53:08.22#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.07:53:08.22#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.07:53:08.22#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:08.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:08.29#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:08.29#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:08.31#ibcon#[25=AT02-07\r\n] 2006.134.07:53:08.34#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:08.34#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:08.34#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.07:53:08.34#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:08.34#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:08.46#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:08.46#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:08.48#ibcon#[25=USB\r\n] 2006.134.07:53:08.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:08.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:08.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:53:08.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:53:08.53$vc4f8/valo=3,672.99 2006.134.07:53:08.53#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.07:53:08.53#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.07:53:08.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:08.53#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:53:08.53#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:53:08.53#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:53:08.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:53:08.58#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:53:08.58#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.07:53:08.58#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:53:08.58#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:53:08.58$vc4f8/va=3,6 2006.134.07:53:08.58#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.07:53:08.58#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.07:53:08.58#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:08.58#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:53:08.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:53:08.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:53:08.67#ibcon#[25=AT03-06\r\n] 2006.134.07:53:08.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:53:08.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.07:53:08.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.07:53:08.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:08.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:53:08.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:53:08.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:53:08.84#ibcon#[25=USB\r\n] 2006.134.07:53:08.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:53:08.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.07:53:08.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:53:08.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:53:08.87$vc4f8/valo=4,832.99 2006.134.07:53:08.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:53:08.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:53:08.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:08.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:08.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:08.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:08.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:53:08.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:08.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:08.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:53:08.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:53:08.93$vc4f8/va=4,7 2006.134.07:53:08.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.07:53:08.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.07:53:08.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:08.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:08.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:08.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:09.01#ibcon#[25=AT04-07\r\n] 2006.134.07:53:09.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:09.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:09.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.07:53:09.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:09.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:09.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:09.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:09.18#ibcon#[25=USB\r\n] 2006.134.07:53:09.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:09.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:09.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:53:09.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:53:09.21$vc4f8/valo=5,652.99 2006.134.07:53:09.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.07:53:09.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.07:53:09.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:09.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:09.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:09.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:09.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:53:09.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:09.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:09.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:53:09.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:53:09.27$vc4f8/va=5,6 2006.134.07:53:09.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.07:53:09.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.07:53:09.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:09.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:09.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:09.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:09.35#ibcon#[25=AT05-06\r\n] 2006.134.07:53:09.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:09.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:09.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.07:53:09.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:09.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:09.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:09.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:09.52#ibcon#[25=USB\r\n] 2006.134.07:53:09.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:09.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:09.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:53:09.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:53:09.55$vc4f8/valo=6,772.99 2006.134.07:53:09.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:53:09.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:53:09.55#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:09.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:09.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:09.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:09.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:53:09.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:09.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:09.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:53:09.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:53:09.61$vc4f8/va=6,5 2006.134.07:53:09.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.07:53:09.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.07:53:09.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:09.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:09.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:09.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:09.69#ibcon#[25=AT06-05\r\n] 2006.134.07:53:09.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:09.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:09.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.07:53:09.72#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:09.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:09.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:09.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:09.86#ibcon#[25=USB\r\n] 2006.134.07:53:09.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:09.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:09.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:53:09.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:53:09.89$vc4f8/valo=7,832.99 2006.134.07:53:09.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:53:09.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:53:09.89#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:09.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:09.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:09.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:53:09.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:09.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:09.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:53:09.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:53:09.95$vc4f8/va=7,5 2006.134.07:53:09.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.07:53:09.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.07:53:09.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:09.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:10.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:10.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:10.03#ibcon#[25=AT07-05\r\n] 2006.134.07:53:10.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:10.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:10.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.07:53:10.06#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:10.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:53:10.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:53:10.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:53:10.20#ibcon#[25=USB\r\n] 2006.134.07:53:10.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:53:10.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.07:53:10.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:53:10.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:53:10.23$vc4f8/valo=8,852.99 2006.134.07:53:10.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.07:53:10.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.07:53:10.23#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:10.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:53:10.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:53:10.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:53:10.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:53:10.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:53:10.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.07:53:10.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:53:10.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:53:10.29$vc4f8/va=8,6 2006.134.07:53:10.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.07:53:10.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.07:53:10.29#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:10.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:53:10.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:53:10.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:53:10.37#ibcon#[25=AT08-06\r\n] 2006.134.07:53:10.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:53:10.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.07:53:10.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.07:53:10.40#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:10.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:53:10.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:53:10.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:53:10.54#ibcon#[25=USB\r\n] 2006.134.07:53:10.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:53:10.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.07:53:10.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:53:10.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:53:10.57$vc4f8/vblo=1,632.99 2006.134.07:53:10.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.07:53:10.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.07:53:10.57#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:10.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:53:10.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:53:10.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:53:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:53:10.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:53:10.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.07:53:10.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:53:10.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:53:10.63$vc4f8/vb=1,4 2006.134.07:53:10.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.07:53:10.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.07:53:10.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:10.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:53:10.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:53:10.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:53:10.65#ibcon#[27=AT01-04\r\n] 2006.134.07:53:10.68#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:53:10.68#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.07:53:10.68#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.07:53:10.68#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:10.68#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:53:10.80#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:53:10.80#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:53:10.82#ibcon#[27=USB\r\n] 2006.134.07:53:10.85#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:53:10.85#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.07:53:10.85#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:53:10.85#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:53:10.85$vc4f8/vblo=2,640.99 2006.134.07:53:10.85#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.07:53:10.85#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.07:53:10.85#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:10.85#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:10.85#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:10.85#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:53:10.91#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:10.91#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.07:53:10.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:53:10.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:53:10.91$vc4f8/vb=2,4 2006.134.07:53:10.91#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.07:53:10.91#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.07:53:10.91#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:10.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:10.97#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:10.97#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:10.99#ibcon#[27=AT02-04\r\n] 2006.134.07:53:11.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:11.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.07:53:11.02#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.07:53:11.02#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:11.02#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:11.14#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:11.14#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:11.16#ibcon#[27=USB\r\n] 2006.134.07:53:11.19#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:11.19#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.07:53:11.19#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:53:11.19#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:53:11.19$vc4f8/vblo=3,656.99 2006.134.07:53:11.19#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.07:53:11.19#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.07:53:11.19#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:11.19#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:11.19#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:11.19#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:53:11.25#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:11.25#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.07:53:11.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:53:11.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:53:11.25$vc4f8/vb=3,4 2006.134.07:53:11.25#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.07:53:11.25#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.07:53:11.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:11.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:11.31#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:11.31#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:11.33#ibcon#[27=AT03-04\r\n] 2006.134.07:53:11.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:11.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.07:53:11.36#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.07:53:11.36#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:11.36#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:11.46#abcon#<5=/04 3.2 5.5 19.15 821006.7\r\n> 2006.134.07:53:11.48#abcon#{5=INTERFACE CLEAR} 2006.134.07:53:11.48#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:11.48#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:11.50#ibcon#[27=USB\r\n] 2006.134.07:53:11.53#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:11.53#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.07:53:11.53#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:53:11.53#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:53:11.53$vc4f8/vblo=4,712.99 2006.134.07:53:11.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.07:53:11.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.07:53:11.53#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:11.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:11.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:11.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:11.54#abcon#[5=S1D000X0/0*\r\n] 2006.134.07:53:11.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:53:11.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:11.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.07:53:11.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:53:11.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:53:11.59$vc4f8/vb=4,4 2006.134.07:53:11.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.07:53:11.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.07:53:11.59#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:11.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:11.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:11.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:11.67#ibcon#[27=AT04-04\r\n] 2006.134.07:53:11.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:11.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.07:53:11.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.07:53:11.70#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:11.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:11.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:11.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:11.84#ibcon#[27=USB\r\n] 2006.134.07:53:11.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:11.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.07:53:11.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:53:11.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:53:11.87$vc4f8/vblo=5,744.99 2006.134.07:53:11.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.07:53:11.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.07:53:11.87#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:11.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:11.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:11.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:53:11.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:11.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.07:53:11.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:53:11.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:53:11.93$vc4f8/vb=5,4 2006.134.07:53:11.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.07:53:11.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.07:53:11.93#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:11.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:11.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:11.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:12.01#ibcon#[27=AT05-04\r\n] 2006.134.07:53:12.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:12.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.07:53:12.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.07:53:12.04#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:12.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:12.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:12.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:12.18#ibcon#[27=USB\r\n] 2006.134.07:53:12.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:12.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.07:53:12.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:53:12.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:53:12.21$vc4f8/vblo=6,752.99 2006.134.07:53:12.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.07:53:12.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.07:53:12.21#ibcon#ireg 17 cls_cnt 0 2006.134.07:53:12.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:12.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:12.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:12.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:53:12.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:12.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.07:53:12.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:53:12.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:53:12.27$vc4f8/vb=6,4 2006.134.07:53:12.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.07:53:12.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.07:53:12.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:53:12.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:12.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:12.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:12.35#ibcon#[27=AT06-04\r\n] 2006.134.07:53:12.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:12.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.07:53:12.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.07:53:12.38#ibcon#ireg 7 cls_cnt 0 2006.134.07:53:12.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:12.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:12.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:12.52#ibcon#[27=USB\r\n] 2006.134.07:53:12.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:12.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.07:53:12.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:53:12.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:53:12.55$vc4f8/vabw=wide 2006.134.07:53:12.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:53:12.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:53:12.55#ibcon#ireg 8 cls_cnt 0 2006.134.07:53:12.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:12.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:12.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:12.57#ibcon#[25=BW32\r\n] 2006.134.07:53:12.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:12.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:53:12.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:53:12.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:53:12.60$vc4f8/vbbw=wide 2006.134.07:53:12.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:53:12.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:53:12.60#ibcon#ireg 8 cls_cnt 0 2006.134.07:53:12.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:53:12.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:53:12.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:53:12.69#ibcon#[27=BW32\r\n] 2006.134.07:53:12.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:53:12.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:53:12.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:53:12.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:53:12.72$4f8m12a/ifd4f 2006.134.07:53:12.72$ifd4f/lo= 2006.134.07:53:12.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:53:12.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:53:12.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:53:12.72$ifd4f/patch= 2006.134.07:53:12.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:53:12.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:53:12.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:53:12.72$4f8m12a/"form=m,16.000,1:2 2006.134.07:53:12.72$4f8m12a/"tpicd 2006.134.07:53:12.72$4f8m12a/echo=off 2006.134.07:53:12.72$4f8m12a/xlog=off 2006.134.07:53:12.72:!2006.134.07:53:40 2006.134.07:53:24.14#trakl#Source acquired 2006.134.07:53:25.14#flagr#flagr/antenna,acquired 2006.134.07:53:40.00:preob 2006.134.07:53:41.14/onsource/TRACKING 2006.134.07:53:41.14:!2006.134.07:53:50 2006.134.07:53:50.00:data_valid=on 2006.134.07:53:50.00:midob 2006.134.07:53:50.14/onsource/TRACKING 2006.134.07:53:50.14/wx/19.14,1006.7,82 2006.134.07:53:50.29/cable/+6.5448E-03 2006.134.07:53:51.38/va/01,08,usb,yes,31,33 2006.134.07:53:51.38/va/02,07,usb,yes,31,33 2006.134.07:53:51.38/va/03,06,usb,yes,33,33 2006.134.07:53:51.38/va/04,07,usb,yes,32,34 2006.134.07:53:51.38/va/05,06,usb,yes,34,36 2006.134.07:53:51.38/va/06,05,usb,yes,34,34 2006.134.07:53:51.38/va/07,05,usb,yes,34,34 2006.134.07:53:51.38/va/08,06,usb,yes,32,31 2006.134.07:53:51.61/valo/01,532.99,yes,locked 2006.134.07:53:51.61/valo/02,572.99,yes,locked 2006.134.07:53:51.61/valo/03,672.99,yes,locked 2006.134.07:53:51.61/valo/04,832.99,yes,locked 2006.134.07:53:51.61/valo/05,652.99,yes,locked 2006.134.07:53:51.61/valo/06,772.99,yes,locked 2006.134.07:53:51.61/valo/07,832.99,yes,locked 2006.134.07:53:51.61/valo/08,852.99,yes,locked 2006.134.07:53:52.70/vb/01,04,usb,yes,30,29 2006.134.07:53:52.70/vb/02,04,usb,yes,32,34 2006.134.07:53:52.70/vb/03,04,usb,yes,28,32 2006.134.07:53:52.70/vb/04,04,usb,yes,29,30 2006.134.07:53:52.70/vb/05,04,usb,yes,28,32 2006.134.07:53:52.70/vb/06,04,usb,yes,29,32 2006.134.07:53:52.70/vb/07,04,usb,yes,31,31 2006.134.07:53:52.70/vb/08,04,usb,yes,29,32 2006.134.07:53:52.93/vblo/01,632.99,yes,locked 2006.134.07:53:52.93/vblo/02,640.99,yes,locked 2006.134.07:53:52.93/vblo/03,656.99,yes,locked 2006.134.07:53:52.93/vblo/04,712.99,yes,locked 2006.134.07:53:52.93/vblo/05,744.99,yes,locked 2006.134.07:53:52.93/vblo/06,752.99,yes,locked 2006.134.07:53:52.93/vblo/07,734.99,yes,locked 2006.134.07:53:52.93/vblo/08,744.99,yes,locked 2006.134.07:53:53.08/vabw/8 2006.134.07:53:53.23/vbbw/8 2006.134.07:53:53.34/xfe/off,on,14.5 2006.134.07:53:53.71/ifatt/23,28,28,28 2006.134.07:53:54.07/fmout-gps/S +1.78E-07 2006.134.07:53:54.11:!2006.134.07:54:50 2006.134.07:54:50.01:data_valid=off 2006.134.07:54:50.01:postob 2006.134.07:54:50.12/cable/+6.5462E-03 2006.134.07:54:50.12/wx/19.11,1006.7,82 2006.134.07:54:51.07/fmout-gps/S +1.78E-07 2006.134.07:54:51.07:scan_name=134-0756,k06134,60 2006.134.07:54:51.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.134.07:54:51.14#flagr#flagr/antenna,new-source 2006.134.07:54:52.14:checkk5 2006.134.07:54:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:54:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:54:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:54:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:54:54.01/chk_obsdata//k5ts1/T1340753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.07:54:54.37/chk_obsdata//k5ts2/T1340753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.07:54:54.75/chk_obsdata//k5ts3/T1340753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.07:54:55.11/chk_obsdata//k5ts4/T1340753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.07:54:55.80/k5log//k5ts1_log_newline 2006.134.07:54:56.48/k5log//k5ts2_log_newline 2006.134.07:54:57.16/k5log//k5ts3_log_newline 2006.134.07:54:57.85/k5log//k5ts4_log_newline 2006.134.07:54:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:54:57.88:4f8m12a=2 2006.134.07:54:57.88$4f8m12a/echo=on 2006.134.07:54:57.88$4f8m12a/pcalon 2006.134.07:54:57.88$pcalon/"no phase cal control is implemented here 2006.134.07:54:57.88$4f8m12a/"tpicd=stop 2006.134.07:54:57.88$4f8m12a/vc4f8 2006.134.07:54:57.88$vc4f8/valo=1,532.99 2006.134.07:54:57.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:54:57.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:54:57.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:57.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:54:57.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:54:57.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:54:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:54:57.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:54:57.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:54:57.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:54:57.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:54:57.97$vc4f8/va=1,8 2006.134.07:54:57.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:54:57.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:54:57.97#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:57.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:54:57.97#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:54:57.97#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:54:58.00#ibcon#[25=AT01-08\r\n] 2006.134.07:54:58.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:54:58.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:54:58.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:54:58.03#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:58.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:54:58.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:54:58.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:54:58.17#ibcon#[25=USB\r\n] 2006.134.07:54:58.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:54:58.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:54:58.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:54:58.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:54:58.22$vc4f8/valo=2,572.99 2006.134.07:54:58.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:54:58.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:54:58.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:58.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:54:58.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:54:58.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:54:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:54:58.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:54:58.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:54:58.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:54:58.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:54:58.27$vc4f8/va=2,7 2006.134.07:54:58.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:54:58.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:54:58.27#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:58.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:54:58.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:54:58.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:54:58.36#ibcon#[25=AT02-07\r\n] 2006.134.07:54:58.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:54:58.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:54:58.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:54:58.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:58.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:54:58.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:54:58.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:54:58.53#ibcon#[25=USB\r\n] 2006.134.07:54:58.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:54:58.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:54:58.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:54:58.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:54:58.56$vc4f8/valo=3,672.99 2006.134.07:54:58.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:54:58.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:54:58.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:58.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:54:58.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:54:58.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:54:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:54:58.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:54:58.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:54:58.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:54:58.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:54:58.63$vc4f8/va=3,6 2006.134.07:54:58.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:54:58.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:54:58.63#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:58.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:54:58.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:54:58.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:54:58.70#ibcon#[25=AT03-06\r\n] 2006.134.07:54:58.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:54:58.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:54:58.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:54:58.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:58.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:54:58.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:54:58.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:54:58.87#ibcon#[25=USB\r\n] 2006.134.07:54:58.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:54:58.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:54:58.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:54:58.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:54:58.90$vc4f8/valo=4,832.99 2006.134.07:54:58.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:54:58.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:54:58.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:58.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:54:58.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:54:58.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:54:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:54:58.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:54:58.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:54:58.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:54:58.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:54:58.96$vc4f8/va=4,7 2006.134.07:54:58.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:54:58.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:54:58.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:58.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:54:59.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:54:59.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:54:59.04#ibcon#[25=AT04-07\r\n] 2006.134.07:54:59.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:54:59.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:54:59.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:54:59.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:59.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:54:59.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:54:59.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:54:59.21#ibcon#[25=USB\r\n] 2006.134.07:54:59.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:54:59.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:54:59.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:54:59.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:54:59.24$vc4f8/valo=5,652.99 2006.134.07:54:59.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:54:59.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:54:59.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:59.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:54:59.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:54:59.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:54:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:54:59.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:54:59.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:54:59.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:54:59.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:54:59.30$vc4f8/va=5,6 2006.134.07:54:59.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:54:59.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:54:59.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:59.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:54:59.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:54:59.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:54:59.38#ibcon#[25=AT05-06\r\n] 2006.134.07:54:59.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:54:59.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:54:59.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:54:59.41#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:59.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:54:59.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:54:59.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:54:59.55#ibcon#[25=USB\r\n] 2006.134.07:54:59.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:54:59.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:54:59.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:54:59.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:54:59.58$vc4f8/valo=6,772.99 2006.134.07:54:59.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:54:59.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:54:59.58#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:59.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:54:59.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:54:59.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:54:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:54:59.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:54:59.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:54:59.64#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:54:59.64#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:54:59.64$vc4f8/va=6,5 2006.134.07:54:59.64#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.07:54:59.64#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.07:54:59.64#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:59.64#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:54:59.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:54:59.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:54:59.72#ibcon#[25=AT06-05\r\n] 2006.134.07:54:59.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:54:59.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.07:54:59.75#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.07:54:59.75#ibcon#ireg 7 cls_cnt 0 2006.134.07:54:59.75#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:54:59.87#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:54:59.87#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:54:59.89#ibcon#[25=USB\r\n] 2006.134.07:54:59.92#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:54:59.92#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.07:54:59.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:54:59.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:54:59.92$vc4f8/valo=7,832.99 2006.134.07:54:59.92#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.07:54:59.92#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.07:54:59.92#ibcon#ireg 17 cls_cnt 0 2006.134.07:54:59.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:54:59.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:54:59.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:54:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:54:59.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:54:59.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.07:54:59.98#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.07:54:59.98#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.07:54:59.98$vc4f8/va=7,5 2006.134.07:54:59.98#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.07:54:59.98#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.07:54:59.98#ibcon#ireg 11 cls_cnt 2 2006.134.07:54:59.98#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:55:00.04#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:55:00.04#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:55:00.06#ibcon#[25=AT07-05\r\n] 2006.134.07:55:00.09#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:55:00.09#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.07:55:00.09#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.07:55:00.09#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:00.09#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:55:00.21#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:55:00.21#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:55:00.23#ibcon#[25=USB\r\n] 2006.134.07:55:00.26#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:55:00.26#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.07:55:00.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.07:55:00.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.07:55:00.26$vc4f8/valo=8,852.99 2006.134.07:55:00.26#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.07:55:00.26#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.07:55:00.26#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:00.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:55:00.26#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:55:00.26#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:55:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:55:00.32#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:55:00.32#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.07:55:00.32#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.07:55:00.32#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.07:55:00.32$vc4f8/va=8,6 2006.134.07:55:00.32#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.07:55:00.32#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.07:55:00.32#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:00.32#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:55:00.38#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:55:00.38#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:55:00.40#ibcon#[25=AT08-06\r\n] 2006.134.07:55:00.43#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:55:00.43#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.07:55:00.43#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.07:55:00.43#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:00.43#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:55:00.55#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:55:00.55#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:55:00.57#ibcon#[25=USB\r\n] 2006.134.07:55:00.60#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:55:00.60#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.07:55:00.60#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.07:55:00.60#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.07:55:00.60$vc4f8/vblo=1,632.99 2006.134.07:55:00.60#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.07:55:00.60#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.07:55:00.60#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:00.60#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:55:00.60#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:55:00.60#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:55:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:55:00.66#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:55:00.66#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.07:55:00.66#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.07:55:00.66#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.07:55:00.66$vc4f8/vb=1,4 2006.134.07:55:00.66#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.07:55:00.66#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.07:55:00.66#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:00.66#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:55:00.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:55:00.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:55:00.68#ibcon#[27=AT01-04\r\n] 2006.134.07:55:00.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:55:00.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.07:55:00.71#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.07:55:00.71#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:00.71#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:55:00.83#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:55:00.83#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:55:00.85#ibcon#[27=USB\r\n] 2006.134.07:55:00.88#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:55:00.88#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.07:55:00.88#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.07:55:00.88#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.07:55:00.88$vc4f8/vblo=2,640.99 2006.134.07:55:00.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.07:55:00.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.07:55:00.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:00.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:55:00.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:55:00.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:55:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:55:00.94#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:55:00.94#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.07:55:00.94#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.07:55:00.94#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.07:55:00.94$vc4f8/vb=2,4 2006.134.07:55:00.94#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.07:55:00.94#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.07:55:00.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:00.94#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:55:01.00#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:55:01.00#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:55:01.02#ibcon#[27=AT02-04\r\n] 2006.134.07:55:01.05#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:55:01.05#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.07:55:01.05#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.07:55:01.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:01.05#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:55:01.17#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:55:01.17#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:55:01.19#ibcon#[27=USB\r\n] 2006.134.07:55:01.22#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:55:01.22#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.07:55:01.22#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.07:55:01.22#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.07:55:01.22$vc4f8/vblo=3,656.99 2006.134.07:55:01.22#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.07:55:01.22#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.07:55:01.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:01.22#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:55:01.22#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:55:01.22#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:55:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:55:01.28#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:55:01.28#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.07:55:01.28#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.07:55:01.28#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.07:55:01.28$vc4f8/vb=3,4 2006.134.07:55:01.28#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.07:55:01.28#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.07:55:01.28#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:01.28#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:55:01.34#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:55:01.34#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:55:01.36#ibcon#[27=AT03-04\r\n] 2006.134.07:55:01.39#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:55:01.39#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.07:55:01.39#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.07:55:01.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:01.39#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:55:01.51#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:55:01.51#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:55:01.53#ibcon#[27=USB\r\n] 2006.134.07:55:01.56#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:55:01.56#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.07:55:01.56#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.07:55:01.56#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.07:55:01.56$vc4f8/vblo=4,712.99 2006.134.07:55:01.56#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.07:55:01.56#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.07:55:01.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:01.56#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:55:01.56#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:55:01.56#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:55:01.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:55:01.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:55:01.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.07:55:01.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.07:55:01.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.07:55:01.62$vc4f8/vb=4,4 2006.134.07:55:01.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.07:55:01.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.07:55:01.62#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:01.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:55:01.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:55:01.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:55:01.70#ibcon#[27=AT04-04\r\n] 2006.134.07:55:01.73#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:55:01.73#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.07:55:01.73#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.07:55:01.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:01.73#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:55:01.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:55:01.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:55:01.87#ibcon#[27=USB\r\n] 2006.134.07:55:01.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:55:01.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.07:55:01.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.07:55:01.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.07:55:01.90$vc4f8/vblo=5,744.99 2006.134.07:55:01.90#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.07:55:01.90#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.07:55:01.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:01.90#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:55:01.90#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:55:01.90#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:55:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:55:01.96#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:55:01.96#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.07:55:01.96#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.07:55:01.96#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.07:55:01.96$vc4f8/vb=5,4 2006.134.07:55:01.96#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.07:55:01.96#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.07:55:01.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:01.96#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:55:02.02#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:55:02.02#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:55:02.04#ibcon#[27=AT05-04\r\n] 2006.134.07:55:02.07#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:55:02.07#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.07:55:02.07#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.07:55:02.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:02.07#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:55:02.19#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:55:02.19#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:55:02.21#ibcon#[27=USB\r\n] 2006.134.07:55:02.24#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:55:02.24#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.07:55:02.24#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.07:55:02.24#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.07:55:02.24$vc4f8/vblo=6,752.99 2006.134.07:55:02.24#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.07:55:02.24#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.07:55:02.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:55:02.24#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:55:02.24#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:55:02.24#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:55:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:55:02.30#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:55:02.30#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.07:55:02.30#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.07:55:02.30#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.07:55:02.30$vc4f8/vb=6,4 2006.134.07:55:02.30#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.07:55:02.30#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.07:55:02.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:55:02.30#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:55:02.36#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:55:02.36#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:55:02.38#ibcon#[27=AT06-04\r\n] 2006.134.07:55:02.41#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:55:02.41#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.07:55:02.41#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.07:55:02.41#ibcon#ireg 7 cls_cnt 0 2006.134.07:55:02.41#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:55:02.53#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:55:02.53#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:55:02.55#ibcon#[27=USB\r\n] 2006.134.07:55:02.58#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:55:02.58#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.07:55:02.58#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.07:55:02.58#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.07:55:02.58$vc4f8/vabw=wide 2006.134.07:55:02.58#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.07:55:02.58#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.07:55:02.58#ibcon#ireg 8 cls_cnt 0 2006.134.07:55:02.58#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:55:02.58#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:55:02.58#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:55:02.60#ibcon#[25=BW32\r\n] 2006.134.07:55:02.63#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:55:02.63#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.07:55:02.63#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.07:55:02.63#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.07:55:02.63$vc4f8/vbbw=wide 2006.134.07:55:02.63#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.07:55:02.63#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.07:55:02.63#ibcon#ireg 8 cls_cnt 0 2006.134.07:55:02.63#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:55:02.70#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:55:02.70#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:55:02.72#ibcon#[27=BW32\r\n] 2006.134.07:55:02.75#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:55:02.75#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.07:55:02.75#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.07:55:02.75#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.07:55:02.75$4f8m12a/ifd4f 2006.134.07:55:02.75$ifd4f/lo= 2006.134.07:55:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:55:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:55:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:55:02.75$ifd4f/patch= 2006.134.07:55:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:55:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:55:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:55:02.75$4f8m12a/"form=m,16.000,1:2 2006.134.07:55:02.75$4f8m12a/"tpicd 2006.134.07:55:02.75$4f8m12a/echo=off 2006.134.07:55:02.75$4f8m12a/xlog=off 2006.134.07:55:02.75:!2006.134.07:55:50 2006.134.07:55:08.14#trakl#Source acquired 2006.134.07:55:09.14#flagr#flagr/antenna,acquired 2006.134.07:55:50.00:preob 2006.134.07:55:50.14/onsource/TRACKING 2006.134.07:55:50.14:!2006.134.07:56:00 2006.134.07:56:00.00:data_valid=on 2006.134.07:56:00.00:midob 2006.134.07:56:00.14/onsource/TRACKING 2006.134.07:56:00.14/wx/19.09,1006.8,82 2006.134.07:56:00.24/cable/+6.5461E-03 2006.134.07:56:01.33/va/01,08,usb,yes,32,34 2006.134.07:56:01.33/va/02,07,usb,yes,32,34 2006.134.07:56:01.33/va/03,06,usb,yes,34,34 2006.134.07:56:01.33/va/04,07,usb,yes,33,35 2006.134.07:56:01.33/va/05,06,usb,yes,35,37 2006.134.07:56:01.33/va/06,05,usb,yes,36,35 2006.134.07:56:01.33/va/07,05,usb,yes,36,35 2006.134.07:56:01.33/va/08,06,usb,yes,33,32 2006.134.07:56:01.56/valo/01,532.99,yes,locked 2006.134.07:56:01.56/valo/02,572.99,yes,locked 2006.134.07:56:01.56/valo/03,672.99,yes,locked 2006.134.07:56:01.56/valo/04,832.99,yes,locked 2006.134.07:56:01.56/valo/05,652.99,yes,locked 2006.134.07:56:01.56/valo/06,772.99,yes,locked 2006.134.07:56:01.56/valo/07,832.99,yes,locked 2006.134.07:56:01.56/valo/08,852.99,yes,locked 2006.134.07:56:02.65/vb/01,04,usb,yes,31,29 2006.134.07:56:02.65/vb/02,04,usb,yes,33,34 2006.134.07:56:02.65/vb/03,04,usb,yes,29,33 2006.134.07:56:02.65/vb/04,04,usb,yes,30,30 2006.134.07:56:02.65/vb/05,04,usb,yes,28,32 2006.134.07:56:02.65/vb/06,04,usb,yes,30,32 2006.134.07:56:02.65/vb/07,04,usb,yes,32,31 2006.134.07:56:02.65/vb/08,04,usb,yes,29,32 2006.134.07:56:02.88/vblo/01,632.99,yes,locked 2006.134.07:56:02.88/vblo/02,640.99,yes,locked 2006.134.07:56:02.88/vblo/03,656.99,yes,locked 2006.134.07:56:02.88/vblo/04,712.99,yes,locked 2006.134.07:56:02.88/vblo/05,744.99,yes,locked 2006.134.07:56:02.88/vblo/06,752.99,yes,locked 2006.134.07:56:02.88/vblo/07,734.99,yes,locked 2006.134.07:56:02.88/vblo/08,744.99,yes,locked 2006.134.07:56:03.03/vabw/8 2006.134.07:56:03.18/vbbw/8 2006.134.07:56:03.27/xfe/off,on,14.7 2006.134.07:56:03.66/ifatt/23,28,28,28 2006.134.07:56:04.07/fmout-gps/S +1.78E-07 2006.134.07:56:04.11:!2006.134.07:57:00 2006.134.07:57:00.01:data_valid=off 2006.134.07:57:00.01:postob 2006.134.07:57:00.21/cable/+6.5479E-03 2006.134.07:57:00.21/wx/19.07,1006.8,83 2006.134.07:57:01.07/fmout-gps/S +1.77E-07 2006.134.07:57:01.07:scan_name=134-0759,k06134,60 2006.134.07:57:01.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.134.07:57:01.14#flagr#flagr/antenna,new-source 2006.134.07:57:02.14:checkk5 2006.134.07:57:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.07:57:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.07:57:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.07:57:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.134.07:57:03.99/chk_obsdata//k5ts1/T1340756??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:57:04.36/chk_obsdata//k5ts2/T1340756??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:57:04.73/chk_obsdata//k5ts3/T1340756??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:57:05.09/chk_obsdata//k5ts4/T1340756??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.07:57:05.78/k5log//k5ts1_log_newline 2006.134.07:57:06.46/k5log//k5ts2_log_newline 2006.134.07:57:07.14/k5log//k5ts3_log_newline 2006.134.07:57:07.83/k5log//k5ts4_log_newline 2006.134.07:57:07.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.07:57:07.86:4f8m12a=2 2006.134.07:57:07.86$4f8m12a/echo=on 2006.134.07:57:07.86$4f8m12a/pcalon 2006.134.07:57:07.86$pcalon/"no phase cal control is implemented here 2006.134.07:57:07.86$4f8m12a/"tpicd=stop 2006.134.07:57:07.86$4f8m12a/vc4f8 2006.134.07:57:07.86$vc4f8/valo=1,532.99 2006.134.07:57:07.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:57:07.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:57:07.86#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:07.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:07.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:07.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:07.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.07:57:07.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:07.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:07.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:57:07.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:57:07.95$vc4f8/va=1,8 2006.134.07:57:07.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:57:07.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:57:07.95#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:07.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:07.95#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:07.95#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:07.98#ibcon#[25=AT01-08\r\n] 2006.134.07:57:08.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:08.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:08.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:57:08.01#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:08.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:08.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:08.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:08.15#ibcon#[25=USB\r\n] 2006.134.07:57:08.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:08.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:08.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:57:08.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:57:08.20$vc4f8/valo=2,572.99 2006.134.07:57:08.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:57:08.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:57:08.20#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:08.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:08.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:08.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:08.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.07:57:08.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:08.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:08.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:57:08.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:57:08.25$vc4f8/va=2,7 2006.134.07:57:08.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:57:08.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:57:08.25#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:08.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:08.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:08.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:08.34#ibcon#[25=AT02-07\r\n] 2006.134.07:57:08.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:08.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:08.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:57:08.37#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:08.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:08.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:08.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:08.51#ibcon#[25=USB\r\n] 2006.134.07:57:08.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:08.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:08.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:57:08.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:57:08.56$vc4f8/valo=3,672.99 2006.134.07:57:08.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:57:08.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:57:08.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:08.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:08.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:08.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.07:57:08.61#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:08.61#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:08.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:57:08.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:57:08.61$vc4f8/va=3,6 2006.134.07:57:08.61#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:57:08.61#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:57:08.61#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:08.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:08.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:08.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:08.70#ibcon#[25=AT03-06\r\n] 2006.134.07:57:08.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:08.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:08.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:57:08.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:08.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:08.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:08.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:08.87#ibcon#[25=USB\r\n] 2006.134.07:57:08.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:08.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:08.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:57:08.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:57:08.90$vc4f8/valo=4,832.99 2006.134.07:57:08.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:57:08.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:57:08.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:08.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:08.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:08.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.07:57:08.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:08.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:08.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:57:08.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:57:08.96$vc4f8/va=4,7 2006.134.07:57:08.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:57:08.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:57:08.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:08.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:09.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:09.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:09.04#ibcon#[25=AT04-07\r\n] 2006.134.07:57:09.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:09.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:09.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:57:09.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:09.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:09.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:09.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:09.21#ibcon#[25=USB\r\n] 2006.134.07:57:09.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:09.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:09.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:57:09.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:57:09.24$vc4f8/valo=5,652.99 2006.134.07:57:09.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:57:09.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:57:09.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:09.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:09.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:09.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.07:57:09.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:09.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:09.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:57:09.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:57:09.30$vc4f8/va=5,6 2006.134.07:57:09.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:57:09.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:57:09.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:09.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:09.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:09.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:09.38#ibcon#[25=AT05-06\r\n] 2006.134.07:57:09.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:09.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:09.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:57:09.41#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:09.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:09.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:09.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:09.55#ibcon#[25=USB\r\n] 2006.134.07:57:09.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:09.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:09.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:57:09.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:57:09.58$vc4f8/valo=6,772.99 2006.134.07:57:09.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:57:09.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:57:09.58#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:09.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:09.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:09.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.07:57:09.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:09.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:09.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:57:09.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:57:09.64$vc4f8/va=6,5 2006.134.07:57:09.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.07:57:09.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.07:57:09.64#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:09.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:09.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:09.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:09.72#ibcon#[25=AT06-05\r\n] 2006.134.07:57:09.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:09.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:09.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.07:57:09.75#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:09.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:57:09.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:57:09.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:57:09.89#ibcon#[25=USB\r\n] 2006.134.07:57:09.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:57:09.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.07:57:09.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:57:09.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:57:09.92$vc4f8/valo=7,832.99 2006.134.07:57:09.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.07:57:09.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.07:57:09.92#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:09.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:57:09.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:57:09.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:57:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.07:57:09.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:57:09.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.07:57:09.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.07:57:09.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.07:57:09.98$vc4f8/va=7,5 2006.134.07:57:09.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.07:57:09.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.07:57:09.98#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:09.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:57:10.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:57:10.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:57:10.06#ibcon#[25=AT07-05\r\n] 2006.134.07:57:10.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:57:10.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.07:57:10.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.07:57:10.09#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:10.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:57:10.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:57:10.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:57:10.23#ibcon#[25=USB\r\n] 2006.134.07:57:10.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:57:10.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.07:57:10.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.07:57:10.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.07:57:10.26$vc4f8/valo=8,852.99 2006.134.07:57:10.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.07:57:10.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.07:57:10.26#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:10.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:57:10.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:57:10.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:57:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.07:57:10.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:57:10.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.07:57:10.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.07:57:10.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.07:57:10.32$vc4f8/va=8,6 2006.134.07:57:10.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.07:57:10.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.07:57:10.32#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:10.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:57:10.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:57:10.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:57:10.40#ibcon#[25=AT08-06\r\n] 2006.134.07:57:10.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:57:10.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.07:57:10.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.07:57:10.43#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:10.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:57:10.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:57:10.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:57:10.57#ibcon#[25=USB\r\n] 2006.134.07:57:10.60#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:57:10.60#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.07:57:10.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.07:57:10.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.07:57:10.60$vc4f8/vblo=1,632.99 2006.134.07:57:10.60#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.07:57:10.60#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.07:57:10.60#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:10.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:57:10.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:57:10.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:57:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.07:57:10.66#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:57:10.66#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.07:57:10.66#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.07:57:10.66#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.07:57:10.66$vc4f8/vb=1,4 2006.134.07:57:10.66#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.07:57:10.66#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.07:57:10.66#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:10.66#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:57:10.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:57:10.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:57:10.68#ibcon#[27=AT01-04\r\n] 2006.134.07:57:10.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:57:10.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.07:57:10.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.07:57:10.71#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:10.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:57:10.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:57:10.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:57:10.85#ibcon#[27=USB\r\n] 2006.134.07:57:10.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:57:10.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.07:57:10.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.07:57:10.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.07:57:10.88$vc4f8/vblo=2,640.99 2006.134.07:57:10.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.07:57:10.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.07:57:10.88#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:10.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:10.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:10.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.07:57:10.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:10.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.07:57:10.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.07:57:10.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.07:57:10.94$vc4f8/vb=2,4 2006.134.07:57:10.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.07:57:10.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.07:57:10.94#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:10.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:11.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:11.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:11.02#ibcon#[27=AT02-04\r\n] 2006.134.07:57:11.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:11.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.07:57:11.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.07:57:11.05#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:11.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:11.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:11.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:11.19#ibcon#[27=USB\r\n] 2006.134.07:57:11.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:11.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.07:57:11.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.07:57:11.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.07:57:11.22$vc4f8/vblo=3,656.99 2006.134.07:57:11.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.07:57:11.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.07:57:11.22#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:11.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:11.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:11.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.07:57:11.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:11.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.07:57:11.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.07:57:11.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.07:57:11.30$vc4f8/vb=3,4 2006.134.07:57:11.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.07:57:11.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.07:57:11.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:11.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:11.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:11.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:11.36#ibcon#[27=AT03-04\r\n] 2006.134.07:57:11.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:11.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.07:57:11.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.07:57:11.39#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:11.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:11.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:11.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:11.53#ibcon#[27=USB\r\n] 2006.134.07:57:11.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:11.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.07:57:11.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.07:57:11.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.07:57:11.56$vc4f8/vblo=4,712.99 2006.134.07:57:11.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.07:57:11.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.07:57:11.56#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:11.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:11.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:11.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.07:57:11.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:11.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.07:57:11.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.07:57:11.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.07:57:11.62$vc4f8/vb=4,4 2006.134.07:57:11.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.07:57:11.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.07:57:11.62#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:11.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:11.68#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:11.68#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:11.70#ibcon#[27=AT04-04\r\n] 2006.134.07:57:11.73#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:11.73#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.07:57:11.73#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.07:57:11.73#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:11.73#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:11.85#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:11.85#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:11.87#ibcon#[27=USB\r\n] 2006.134.07:57:11.90#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:11.90#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.07:57:11.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.07:57:11.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.07:57:11.90$vc4f8/vblo=5,744.99 2006.134.07:57:11.90#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.07:57:11.90#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.07:57:11.90#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:11.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:11.90#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:11.90#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.07:57:11.96#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:11.96#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.07:57:11.96#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.07:57:11.96#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.07:57:11.96$vc4f8/vb=5,4 2006.134.07:57:11.96#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.07:57:11.96#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.07:57:11.96#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:11.96#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:12.02#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:12.02#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:12.04#ibcon#[27=AT05-04\r\n] 2006.134.07:57:12.07#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:12.07#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.07:57:12.07#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.07:57:12.07#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:12.07#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:12.19#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:12.19#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:12.21#ibcon#[27=USB\r\n] 2006.134.07:57:12.24#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:12.24#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.07:57:12.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.07:57:12.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.07:57:12.24$vc4f8/vblo=6,752.99 2006.134.07:57:12.24#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.07:57:12.24#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.07:57:12.24#ibcon#ireg 17 cls_cnt 0 2006.134.07:57:12.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:12.24#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:12.24#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.07:57:12.30#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:12.30#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.07:57:12.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.07:57:12.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.07:57:12.30$vc4f8/vb=6,4 2006.134.07:57:12.30#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.07:57:12.30#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.07:57:12.30#ibcon#ireg 11 cls_cnt 2 2006.134.07:57:12.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:12.36#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:12.36#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:12.38#ibcon#[27=AT06-04\r\n] 2006.134.07:57:12.41#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:12.41#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.07:57:12.41#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.07:57:12.41#ibcon#ireg 7 cls_cnt 0 2006.134.07:57:12.41#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:12.53#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:12.53#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:12.55#ibcon#[27=USB\r\n] 2006.134.07:57:12.58#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:12.58#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.07:57:12.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.07:57:12.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.07:57:12.58$vc4f8/vabw=wide 2006.134.07:57:12.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.07:57:12.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.07:57:12.58#ibcon#ireg 8 cls_cnt 0 2006.134.07:57:12.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:12.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:12.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:12.60#ibcon#[25=BW32\r\n] 2006.134.07:57:12.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:12.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.07:57:12.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.07:57:12.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.07:57:12.63$vc4f8/vbbw=wide 2006.134.07:57:12.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.07:57:12.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.07:57:12.63#ibcon#ireg 8 cls_cnt 0 2006.134.07:57:12.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:57:12.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:57:12.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:57:12.72#ibcon#[27=BW32\r\n] 2006.134.07:57:12.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:57:12.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.07:57:12.75#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.07:57:12.75#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.07:57:12.75$4f8m12a/ifd4f 2006.134.07:57:12.75$ifd4f/lo= 2006.134.07:57:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.07:57:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.07:57:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.07:57:12.75$ifd4f/patch= 2006.134.07:57:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.07:57:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.07:57:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.07:57:12.75$4f8m12a/"form=m,16.000,1:2 2006.134.07:57:12.75$4f8m12a/"tpicd 2006.134.07:57:12.75$4f8m12a/echo=off 2006.134.07:57:12.75$4f8m12a/xlog=off 2006.134.07:57:12.75:!2006.134.07:59:20 2006.134.07:57:31.13#trakl#Source acquired 2006.134.07:57:31.13#flagr#flagr/antenna,acquired 2006.134.07:59:20.00:preob 2006.134.07:59:20.13/onsource/TRACKING 2006.134.07:59:20.13:!2006.134.07:59:30 2006.134.07:59:30.00:data_valid=on 2006.134.07:59:30.00:midob 2006.134.07:59:31.13/onsource/TRACKING 2006.134.07:59:31.13/wx/19.01,1006.8,84 2006.134.07:59:31.28/cable/+6.5493E-03 2006.134.07:59:32.37/va/01,08,usb,yes,29,31 2006.134.07:59:32.37/va/02,07,usb,yes,29,31 2006.134.07:59:32.37/va/03,06,usb,yes,31,31 2006.134.07:59:32.37/va/04,07,usb,yes,30,32 2006.134.07:59:32.37/va/05,06,usb,yes,31,33 2006.134.07:59:32.37/va/06,05,usb,yes,32,31 2006.134.07:59:32.37/va/07,05,usb,yes,32,31 2006.134.07:59:32.37/va/08,06,usb,yes,29,29 2006.134.07:59:32.60/valo/01,532.99,yes,locked 2006.134.07:59:32.60/valo/02,572.99,yes,locked 2006.134.07:59:32.60/valo/03,672.99,yes,locked 2006.134.07:59:32.60/valo/04,832.99,yes,locked 2006.134.07:59:32.60/valo/05,652.99,yes,locked 2006.134.07:59:32.60/valo/06,772.99,yes,locked 2006.134.07:59:32.60/valo/07,832.99,yes,locked 2006.134.07:59:32.60/valo/08,852.99,yes,locked 2006.134.07:59:33.69/vb/01,04,usb,yes,29,28 2006.134.07:59:33.69/vb/02,04,usb,yes,31,32 2006.134.07:59:33.69/vb/03,04,usb,yes,27,31 2006.134.07:59:33.69/vb/04,04,usb,yes,28,28 2006.134.07:59:33.69/vb/05,04,usb,yes,27,30 2006.134.07:59:33.69/vb/06,04,usb,yes,28,30 2006.134.07:59:33.69/vb/07,04,usb,yes,30,29 2006.134.07:59:33.69/vb/08,04,usb,yes,27,30 2006.134.07:59:33.92/vblo/01,632.99,yes,locked 2006.134.07:59:33.92/vblo/02,640.99,yes,locked 2006.134.07:59:33.92/vblo/03,656.99,yes,locked 2006.134.07:59:33.92/vblo/04,712.99,yes,locked 2006.134.07:59:33.92/vblo/05,744.99,yes,locked 2006.134.07:59:33.92/vblo/06,752.99,yes,locked 2006.134.07:59:33.92/vblo/07,734.99,yes,locked 2006.134.07:59:33.92/vblo/08,744.99,yes,locked 2006.134.07:59:34.07/vabw/8 2006.134.07:59:34.22/vbbw/8 2006.134.07:59:34.38/xfe/off,on,15.2 2006.134.07:59:34.77/ifatt/23,28,28,28 2006.134.07:59:35.07/fmout-gps/S +1.78E-07 2006.134.07:59:35.11:!2006.134.08:00:30 2006.134.08:00:30.01:data_valid=off 2006.134.08:00:30.01:postob 2006.134.08:00:30.12/cable/+6.5474E-03 2006.134.08:00:30.12/wx/18.98,1006.9,84 2006.134.08:00:31.07/fmout-gps/S +1.78E-07 2006.134.08:00:31.07:scan_name=134-0801,k06134,60 2006.134.08:00:31.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.134.08:00:31.14#flagr#flagr/antenna,new-source 2006.134.08:00:32.14:checkk5 2006.134.08:00:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:00:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:00:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:00:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:00:34.00/chk_obsdata//k5ts1/T1340759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:00:34.36/chk_obsdata//k5ts2/T1340759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:00:34.73/chk_obsdata//k5ts3/T1340759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:00:35.09/chk_obsdata//k5ts4/T1340759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:00:35.78/k5log//k5ts1_log_newline 2006.134.08:00:36.46/k5log//k5ts2_log_newline 2006.134.08:00:37.15/k5log//k5ts3_log_newline 2006.134.08:00:37.83/k5log//k5ts4_log_newline 2006.134.08:00:37.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:00:37.86:4f8m12a=2 2006.134.08:00:37.86$4f8m12a/echo=on 2006.134.08:00:37.86$4f8m12a/pcalon 2006.134.08:00:37.86$pcalon/"no phase cal control is implemented here 2006.134.08:00:37.86$4f8m12a/"tpicd=stop 2006.134.08:00:37.86$4f8m12a/vc4f8 2006.134.08:00:37.86$vc4f8/valo=1,532.99 2006.134.08:00:37.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:00:37.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:00:37.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:37.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:37.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:37.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:37.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:00:37.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:37.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:37.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:00:37.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:00:37.95$vc4f8/va=1,8 2006.134.08:00:37.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:00:37.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:00:37.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:37.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:37.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:37.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:37.98#ibcon#[25=AT01-08\r\n] 2006.134.08:00:38.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:38.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:38.01#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:00:38.01#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:38.01#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:38.13#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:38.13#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:38.15#ibcon#[25=USB\r\n] 2006.134.08:00:38.18#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:38.18#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:38.18#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:00:38.18#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:00:38.18$vc4f8/valo=2,572.99 2006.134.08:00:38.18#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:00:38.18#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:00:38.18#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:38.18#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:38.18#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:38.18#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:38.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:00:38.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:38.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:38.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:00:38.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:00:38.25$vc4f8/va=2,7 2006.134.08:00:38.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:00:38.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:00:38.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:38.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:38.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:38.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:38.32#ibcon#[25=AT02-07\r\n] 2006.134.08:00:38.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:38.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:38.35#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:00:38.35#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:38.35#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:38.47#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:38.47#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:38.49#ibcon#[25=USB\r\n] 2006.134.08:00:38.52#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:38.52#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:38.52#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:00:38.52#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:00:38.52$vc4f8/valo=3,672.99 2006.134.08:00:38.52#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:00:38.52#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:00:38.52#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:38.52#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:38.52#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:38.52#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:38.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:00:38.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:38.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:38.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:00:38.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:00:38.59$vc4f8/va=3,6 2006.134.08:00:38.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:00:38.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:00:38.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:38.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:38.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:38.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:38.66#ibcon#[25=AT03-06\r\n] 2006.134.08:00:38.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:38.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:38.69#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:00:38.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:38.69#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:38.81#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:38.81#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:38.83#ibcon#[25=USB\r\n] 2006.134.08:00:38.86#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:38.86#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:38.86#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:00:38.86#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:00:38.86$vc4f8/valo=4,832.99 2006.134.08:00:38.86#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:00:38.86#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:00:38.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:38.86#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:38.86#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:38.86#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:38.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:00:38.92#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:38.92#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:38.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:00:38.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:00:38.92$vc4f8/va=4,7 2006.134.08:00:38.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:00:38.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:00:38.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:38.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:00:38.94#abcon#<5=/05 3.4 5.5 18.98 841006.9\r\n> 2006.134.08:00:38.96#abcon#{5=INTERFACE CLEAR} 2006.134.08:00:38.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:00:38.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:00:39.00#ibcon#[25=AT04-07\r\n] 2006.134.08:00:39.02#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:00:39.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:00:39.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:00:39.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:00:39.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:39.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:00:39.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:00:39.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:00:39.17#ibcon#[25=USB\r\n] 2006.134.08:00:39.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:00:39.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:00:39.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:00:39.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:00:39.20$vc4f8/valo=5,652.99 2006.134.08:00:39.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:00:39.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:00:39.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:39.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:39.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:39.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:39.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:00:39.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:39.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:39.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:00:39.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:00:39.26$vc4f8/va=5,6 2006.134.08:00:39.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:00:39.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:00:39.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:39.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:39.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:39.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:39.34#ibcon#[25=AT05-06\r\n] 2006.134.08:00:39.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:39.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:39.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:00:39.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:39.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:39.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:39.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:39.51#ibcon#[25=USB\r\n] 2006.134.08:00:39.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:39.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:39.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:00:39.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:00:39.54$vc4f8/valo=6,772.99 2006.134.08:00:39.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:00:39.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:00:39.54#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:39.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:39.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:39.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:39.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:00:39.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:39.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:39.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:00:39.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:00:39.60$vc4f8/va=6,5 2006.134.08:00:39.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:00:39.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:00:39.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:39.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:39.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:39.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:39.68#ibcon#[25=AT06-05\r\n] 2006.134.08:00:39.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:39.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:39.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:00:39.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:39.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:00:39.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:00:39.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:00:39.85#ibcon#[25=USB\r\n] 2006.134.08:00:39.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:00:39.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:00:39.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:00:39.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:00:39.88$vc4f8/valo=7,832.99 2006.134.08:00:39.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:00:39.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:00:39.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:39.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:00:39.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:00:39.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:00:39.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:00:39.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:00:39.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:00:39.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:00:39.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:00:39.94$vc4f8/va=7,5 2006.134.08:00:39.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:00:39.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:00:39.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:39.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:00:40.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:00:40.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:00:40.02#ibcon#[25=AT07-05\r\n] 2006.134.08:00:40.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:00:40.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:00:40.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:00:40.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:40.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:00:40.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:00:40.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:00:40.19#ibcon#[25=USB\r\n] 2006.134.08:00:40.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:00:40.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:00:40.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:00:40.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:00:40.22$vc4f8/valo=8,852.99 2006.134.08:00:40.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:00:40.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:00:40.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:40.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:00:40.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:00:40.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:00:40.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:00:40.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:00:40.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:00:40.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:00:40.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:00:40.28$vc4f8/va=8,6 2006.134.08:00:40.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:00:40.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:00:40.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:40.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:00:40.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:00:40.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:00:40.36#ibcon#[25=AT08-06\r\n] 2006.134.08:00:40.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:00:40.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:00:40.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:00:40.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:40.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:00:40.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:00:40.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:00:40.53#ibcon#[25=USB\r\n] 2006.134.08:00:40.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:00:40.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:00:40.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:00:40.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:00:40.56$vc4f8/vblo=1,632.99 2006.134.08:00:40.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:00:40.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:00:40.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:40.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:40.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:40.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:40.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:00:40.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:40.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:00:40.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:00:40.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:00:40.62$vc4f8/vb=1,4 2006.134.08:00:40.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:00:40.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:00:40.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:40.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:40.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:40.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:40.64#ibcon#[27=AT01-04\r\n] 2006.134.08:00:40.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:40.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:00:40.67#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:00:40.67#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:40.67#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:40.79#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:40.79#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:40.81#ibcon#[27=USB\r\n] 2006.134.08:00:40.84#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:40.84#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:00:40.84#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:00:40.84#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:00:40.84$vc4f8/vblo=2,640.99 2006.134.08:00:40.84#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:00:40.84#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:00:40.84#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:40.84#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:40.84#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:40.84#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:00:40.92#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:40.92#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:00:40.92#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:00:40.92#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:00:40.92$vc4f8/vb=2,4 2006.134.08:00:40.92#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:00:40.92#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:00:40.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:40.92#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:40.96#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:40.96#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:40.98#ibcon#[27=AT02-04\r\n] 2006.134.08:00:41.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:41.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:00:41.01#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:00:41.01#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:41.01#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:41.13#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:41.13#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:41.15#ibcon#[27=USB\r\n] 2006.134.08:00:41.18#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:41.18#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:00:41.18#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:00:41.18#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:00:41.18$vc4f8/vblo=3,656.99 2006.134.08:00:41.18#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:00:41.18#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:00:41.18#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:41.18#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:41.18#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:41.18#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:00:41.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:41.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:00:41.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:00:41.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:00:41.24$vc4f8/vb=3,4 2006.134.08:00:41.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:00:41.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:00:41.24#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:41.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:41.30#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:41.30#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:41.32#ibcon#[27=AT03-04\r\n] 2006.134.08:00:41.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:41.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:00:41.35#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:00:41.35#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:41.35#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:41.47#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:41.47#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:41.49#ibcon#[27=USB\r\n] 2006.134.08:00:41.52#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:41.52#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:00:41.52#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:00:41.52#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:00:41.52$vc4f8/vblo=4,712.99 2006.134.08:00:41.52#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:00:41.52#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:00:41.52#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:41.52#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:41.52#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:41.52#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:41.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:00:41.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:41.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:00:41.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:00:41.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:00:41.58$vc4f8/vb=4,4 2006.134.08:00:41.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:00:41.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:00:41.58#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:41.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:00:41.64#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:00:41.64#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:00:41.66#ibcon#[27=AT04-04\r\n] 2006.134.08:00:41.69#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:00:41.69#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:00:41.69#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:00:41.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:41.69#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:00:41.81#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:00:41.81#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:00:41.83#ibcon#[27=USB\r\n] 2006.134.08:00:41.86#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:00:41.86#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:00:41.86#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:00:41.86#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:00:41.86$vc4f8/vblo=5,744.99 2006.134.08:00:41.86#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:00:41.86#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:00:41.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:41.86#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:00:41.86#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:00:41.86#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:00:41.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:00:41.92#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:00:41.92#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:00:41.92#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:00:41.92#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:00:41.92$vc4f8/vb=5,4 2006.134.08:00:41.92#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.08:00:41.92#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.08:00:41.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:41.92#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:00:41.98#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:00:41.98#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:00:42.00#ibcon#[27=AT05-04\r\n] 2006.134.08:00:42.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:00:42.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:00:42.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.08:00:42.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:42.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:00:42.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:00:42.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:00:42.17#ibcon#[27=USB\r\n] 2006.134.08:00:42.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:00:42.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:00:42.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:00:42.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:00:42.20$vc4f8/vblo=6,752.99 2006.134.08:00:42.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:00:42.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:00:42.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:00:42.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:42.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:42.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:00:42.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:42.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:00:42.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:00:42.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:00:42.26$vc4f8/vb=6,4 2006.134.08:00:42.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:00:42.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:00:42.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:00:42.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:42.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:42.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:42.34#ibcon#[27=AT06-04\r\n] 2006.134.08:00:42.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:42.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:00:42.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:00:42.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:00:42.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:42.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:42.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:42.51#ibcon#[27=USB\r\n] 2006.134.08:00:42.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:42.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:00:42.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:00:42.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:00:42.56$vc4f8/vabw=wide 2006.134.08:00:42.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:00:42.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:00:42.56#ibcon#ireg 8 cls_cnt 0 2006.134.08:00:42.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:42.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:42.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:42.57#ibcon#[25=BW32\r\n] 2006.134.08:00:42.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:42.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:00:42.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:00:42.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:00:42.60$vc4f8/vbbw=wide 2006.134.08:00:42.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:00:42.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:00:42.60#ibcon#ireg 8 cls_cnt 0 2006.134.08:00:42.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:00:42.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:00:42.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:00:42.70#ibcon#[27=BW32\r\n] 2006.134.08:00:42.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:00:42.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:00:42.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:00:42.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:00:42.73$4f8m12a/ifd4f 2006.134.08:00:42.73$ifd4f/lo= 2006.134.08:00:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:00:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:00:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:00:42.73$ifd4f/patch= 2006.134.08:00:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:00:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:00:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:00:42.73$4f8m12a/"form=m,16.000,1:2 2006.134.08:00:42.73$4f8m12a/"tpicd 2006.134.08:00:42.73$4f8m12a/echo=off 2006.134.08:00:42.73$4f8m12a/xlog=off 2006.134.08:00:42.73:!2006.134.08:01:10 2006.134.08:00:52.14#trakl#Source acquired 2006.134.08:00:52.14#flagr#flagr/antenna,acquired 2006.134.08:01:10.00:preob 2006.134.08:01:11.14/onsource/TRACKING 2006.134.08:01:11.14:!2006.134.08:01:20 2006.134.08:01:20.00:data_valid=on 2006.134.08:01:20.00:midob 2006.134.08:01:20.14/onsource/TRACKING 2006.134.08:01:20.14/wx/18.96,1006.9,84 2006.134.08:01:20.22/cable/+6.5471E-03 2006.134.08:01:21.31/va/01,08,usb,yes,29,31 2006.134.08:01:21.31/va/02,07,usb,yes,29,30 2006.134.08:01:21.31/va/03,06,usb,yes,31,31 2006.134.08:01:21.31/va/04,07,usb,yes,30,32 2006.134.08:01:21.31/va/05,06,usb,yes,32,33 2006.134.08:01:21.31/va/06,05,usb,yes,32,31 2006.134.08:01:21.31/va/07,05,usb,yes,32,31 2006.134.08:01:21.31/va/08,06,usb,yes,29,29 2006.134.08:01:21.54/valo/01,532.99,yes,locked 2006.134.08:01:21.54/valo/02,572.99,yes,locked 2006.134.08:01:21.54/valo/03,672.99,yes,locked 2006.134.08:01:21.54/valo/04,832.99,yes,locked 2006.134.08:01:21.54/valo/05,652.99,yes,locked 2006.134.08:01:21.54/valo/06,772.99,yes,locked 2006.134.08:01:21.54/valo/07,832.99,yes,locked 2006.134.08:01:21.54/valo/08,852.99,yes,locked 2006.134.08:01:22.63/vb/01,04,usb,yes,29,28 2006.134.08:01:22.63/vb/02,04,usb,yes,31,32 2006.134.08:01:22.63/vb/03,04,usb,yes,27,31 2006.134.08:01:22.63/vb/04,04,usb,yes,28,28 2006.134.08:01:22.63/vb/05,04,usb,yes,26,30 2006.134.08:01:22.63/vb/06,04,usb,yes,27,30 2006.134.08:01:22.63/vb/07,04,usb,yes,29,29 2006.134.08:01:22.63/vb/08,04,usb,yes,27,30 2006.134.08:01:22.86/vblo/01,632.99,yes,locked 2006.134.08:01:22.86/vblo/02,640.99,yes,locked 2006.134.08:01:22.86/vblo/03,656.99,yes,locked 2006.134.08:01:22.86/vblo/04,712.99,yes,locked 2006.134.08:01:22.86/vblo/05,744.99,yes,locked 2006.134.08:01:22.86/vblo/06,752.99,yes,locked 2006.134.08:01:22.86/vblo/07,734.99,yes,locked 2006.134.08:01:22.86/vblo/08,744.99,yes,locked 2006.134.08:01:23.01/vabw/8 2006.134.08:01:23.16/vbbw/8 2006.134.08:01:23.25/xfe/off,on,14.7 2006.134.08:01:23.64/ifatt/23,28,28,28 2006.134.08:01:24.07/fmout-gps/S +1.77E-07 2006.134.08:01:24.11:!2006.134.08:02:20 2006.134.08:02:20.00:data_valid=off 2006.134.08:02:20.00:postob 2006.134.08:02:20.20/cable/+6.5450E-03 2006.134.08:02:20.20/wx/18.94,1006.9,84 2006.134.08:02:21.07/fmout-gps/S +1.78E-07 2006.134.08:02:21.07:scan_name=134-0803,k06134,60 2006.134.08:02:21.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.134.08:02:21.14#flagr#flagr/antenna,new-source 2006.134.08:02:22.14:checkk5 2006.134.08:02:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:02:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:02:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:02:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:02:24.00/chk_obsdata//k5ts1/T1340801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:02:24.37/chk_obsdata//k5ts2/T1340801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:02:24.73/chk_obsdata//k5ts3/T1340801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:02:25.09/chk_obsdata//k5ts4/T1340801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:02:25.79/k5log//k5ts1_log_newline 2006.134.08:02:26.47/k5log//k5ts2_log_newline 2006.134.08:02:27.16/k5log//k5ts3_log_newline 2006.134.08:02:27.84/k5log//k5ts4_log_newline 2006.134.08:02:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:02:27.87:4f8m12a=2 2006.134.08:02:27.87$4f8m12a/echo=on 2006.134.08:02:27.87$4f8m12a/pcalon 2006.134.08:02:27.87$pcalon/"no phase cal control is implemented here 2006.134.08:02:27.87$4f8m12a/"tpicd=stop 2006.134.08:02:27.87$4f8m12a/vc4f8 2006.134.08:02:27.87$vc4f8/valo=1,532.99 2006.134.08:02:27.87#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.08:02:27.87#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.08:02:27.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:27.87#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:02:27.87#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:02:27.87#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:02:27.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:02:27.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:02:27.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:02:27.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:02:27.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:02:27.96$vc4f8/va=1,8 2006.134.08:02:27.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.08:02:27.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.08:02:27.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:27.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:02:27.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:02:27.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:02:27.99#ibcon#[25=AT01-08\r\n] 2006.134.08:02:28.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:02:28.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:02:28.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.08:02:28.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:28.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:02:28.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:02:28.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:02:28.16#ibcon#[25=USB\r\n] 2006.134.08:02:28.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:02:28.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:02:28.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:02:28.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:02:28.19$vc4f8/valo=2,572.99 2006.134.08:02:28.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.08:02:28.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.08:02:28.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:28.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:02:28.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:02:28.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:02:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:02:28.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:02:28.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:02:28.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:02:28.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:02:28.26$vc4f8/va=2,7 2006.134.08:02:28.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.08:02:28.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.08:02:28.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:28.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:28.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:28.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:28.33#ibcon#[25=AT02-07\r\n] 2006.134.08:02:28.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:28.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:28.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.08:02:28.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:28.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:28.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:28.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:28.50#ibcon#[25=USB\r\n] 2006.134.08:02:28.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:28.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:28.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:02:28.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:02:28.53$vc4f8/valo=3,672.99 2006.134.08:02:28.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.08:02:28.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.08:02:28.53#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:28.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:28.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:28.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:02:28.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:28.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:28.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:02:28.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:02:28.60$vc4f8/va=3,6 2006.134.08:02:28.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.08:02:28.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.08:02:28.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:28.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:28.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:28.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:28.67#ibcon#[25=AT03-06\r\n] 2006.134.08:02:28.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:28.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:28.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.08:02:28.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:28.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:28.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:28.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:28.84#ibcon#[25=USB\r\n] 2006.134.08:02:28.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:28.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:28.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:02:28.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:02:28.87$vc4f8/valo=4,832.99 2006.134.08:02:28.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.08:02:28.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.08:02:28.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:28.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:28.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:28.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:28.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:02:28.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:28.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:28.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:02:28.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:02:28.93$vc4f8/va=4,7 2006.134.08:02:28.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.08:02:28.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.08:02:28.93#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:28.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:28.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:28.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:29.01#ibcon#[25=AT04-07\r\n] 2006.134.08:02:29.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:29.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:29.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.08:02:29.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:29.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:29.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:29.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:29.18#ibcon#[25=USB\r\n] 2006.134.08:02:29.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:29.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:29.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:02:29.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:02:29.21$vc4f8/valo=5,652.99 2006.134.08:02:29.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:02:29.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:02:29.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:29.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:29.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:29.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:29.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:02:29.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:29.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:29.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:02:29.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:02:29.27$vc4f8/va=5,6 2006.134.08:02:29.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:02:29.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:02:29.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:29.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:29.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:29.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:29.35#ibcon#[25=AT05-06\r\n] 2006.134.08:02:29.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:29.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:29.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:02:29.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:29.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:29.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:29.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:29.53#ibcon#[25=USB\r\n] 2006.134.08:02:29.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:29.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:29.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:02:29.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:02:29.56$vc4f8/valo=6,772.99 2006.134.08:02:29.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:02:29.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:02:29.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:29.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:29.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:29.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:29.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:02:29.62#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:29.62#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:29.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:02:29.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:02:29.62$vc4f8/va=6,5 2006.134.08:02:29.62#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:02:29.62#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:02:29.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:29.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:29.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:29.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:29.70#ibcon#[25=AT06-05\r\n] 2006.134.08:02:29.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:29.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:29.73#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:02:29.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:29.73#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:29.85#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:29.85#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:29.87#ibcon#[25=USB\r\n] 2006.134.08:02:29.90#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:29.90#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:29.90#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:02:29.90#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:02:29.90$vc4f8/valo=7,832.99 2006.134.08:02:29.90#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:02:29.90#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:02:29.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:29.90#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:29.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:29.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:02:29.96#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:29.96#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:29.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:02:29.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:02:29.96$vc4f8/va=7,5 2006.134.08:02:29.96#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.08:02:29.96#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.08:02:29.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:29.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:30.02#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:30.02#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:30.04#ibcon#[25=AT07-05\r\n] 2006.134.08:02:30.07#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:30.07#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:30.07#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.08:02:30.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:30.07#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:02:30.19#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:02:30.19#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:02:30.21#ibcon#[25=USB\r\n] 2006.134.08:02:30.24#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:02:30.24#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:02:30.24#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:02:30.24#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:02:30.24$vc4f8/valo=8,852.99 2006.134.08:02:30.24#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.08:02:30.24#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.08:02:30.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:30.24#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:02:30.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:02:30.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:02:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:02:30.30#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:02:30.30#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:02:30.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:02:30.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:02:30.30$vc4f8/va=8,6 2006.134.08:02:30.30#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.08:02:30.30#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.08:02:30.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:30.30#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:02:30.36#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:02:30.36#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:02:30.38#ibcon#[25=AT08-06\r\n] 2006.134.08:02:30.41#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:02:30.41#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:02:30.41#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.08:02:30.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:30.41#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:02:30.53#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:02:30.53#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:02:30.55#ibcon#[25=USB\r\n] 2006.134.08:02:30.58#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:02:30.58#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:02:30.58#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:02:30.58#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:02:30.58$vc4f8/vblo=1,632.99 2006.134.08:02:30.58#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.08:02:30.58#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.08:02:30.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:30.58#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:02:30.58#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:02:30.58#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:02:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:02:30.64#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:02:30.64#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:02:30.64#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:02:30.64#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:02:30.64$vc4f8/vb=1,4 2006.134.08:02:30.64#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.08:02:30.64#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.08:02:30.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:30.64#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:02:30.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:02:30.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:02:30.66#ibcon#[27=AT01-04\r\n] 2006.134.08:02:30.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:02:30.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:02:30.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.08:02:30.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:30.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:02:30.81#abcon#<5=/05 3.4 5.5 18.93 841006.9\r\n> 2006.134.08:02:30.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:02:30.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:02:30.83#ibcon#[27=USB\r\n] 2006.134.08:02:30.83#abcon#{5=INTERFACE CLEAR} 2006.134.08:02:30.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:02:30.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:02:30.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:02:30.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:02:30.86$vc4f8/vblo=2,640.99 2006.134.08:02:30.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:02:30.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:02:30.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:30.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:02:30.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:02:30.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:02:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:02:30.89#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:02:30.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:02:30.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:02:30.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:02:30.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:02:30.92$vc4f8/vb=2,4 2006.134.08:02:30.92#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.08:02:30.92#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.08:02:30.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:30.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:30.98#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:30.98#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:31.00#ibcon#[27=AT02-04\r\n] 2006.134.08:02:31.03#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:31.03#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:02:31.03#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.08:02:31.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:31.03#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:31.15#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:31.15#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:31.17#ibcon#[27=USB\r\n] 2006.134.08:02:31.20#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:31.20#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:02:31.20#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:02:31.20#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:02:31.20$vc4f8/vblo=3,656.99 2006.134.08:02:31.20#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.08:02:31.20#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.08:02:31.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:31.20#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:31.20#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:31.20#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:02:31.26#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:31.26#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:02:31.26#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:02:31.26#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:02:31.26$vc4f8/vb=3,4 2006.134.08:02:31.26#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.08:02:31.26#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.08:02:31.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:31.26#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:31.32#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:31.32#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:31.34#ibcon#[27=AT03-04\r\n] 2006.134.08:02:31.37#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:31.37#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:02:31.37#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.08:02:31.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:31.37#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:31.49#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:31.49#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:31.51#ibcon#[27=USB\r\n] 2006.134.08:02:31.54#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:31.54#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:02:31.54#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:02:31.54#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:02:31.54$vc4f8/vblo=4,712.99 2006.134.08:02:31.54#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.08:02:31.54#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.08:02:31.54#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:31.54#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:31.54#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:31.54#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:31.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:02:31.60#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:31.60#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:02:31.60#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:02:31.60#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:02:31.60$vc4f8/vb=4,4 2006.134.08:02:31.60#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.08:02:31.60#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.08:02:31.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:31.60#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:31.66#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:31.66#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:31.68#ibcon#[27=AT04-04\r\n] 2006.134.08:02:31.71#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:31.71#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:02:31.71#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.08:02:31.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:31.71#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:31.83#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:31.83#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:31.85#ibcon#[27=USB\r\n] 2006.134.08:02:31.88#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:31.88#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:02:31.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:02:31.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:02:31.88$vc4f8/vblo=5,744.99 2006.134.08:02:31.88#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:02:31.88#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:02:31.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:31.88#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:31.88#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:31.88#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:31.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:02:31.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:31.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:02:31.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:02:31.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:02:31.94$vc4f8/vb=5,4 2006.134.08:02:31.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:02:31.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:02:31.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:31.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:32.00#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:32.00#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:32.02#ibcon#[27=AT05-04\r\n] 2006.134.08:02:32.05#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:32.05#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:02:32.05#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:02:32.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:32.05#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:32.17#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:32.17#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:32.19#ibcon#[27=USB\r\n] 2006.134.08:02:32.22#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:32.22#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:02:32.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:02:32.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:02:32.22$vc4f8/vblo=6,752.99 2006.134.08:02:32.22#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:02:32.22#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:02:32.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:02:32.22#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:32.22#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:32.22#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:32.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:02:32.28#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:32.28#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:02:32.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:02:32.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:02:32.28$vc4f8/vb=6,4 2006.134.08:02:32.28#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:02:32.28#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:02:32.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:02:32.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:32.34#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:32.34#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:32.36#ibcon#[27=AT06-04\r\n] 2006.134.08:02:32.39#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:32.39#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:02:32.39#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:02:32.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:02:32.39#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:32.51#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:32.51#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:32.53#ibcon#[27=USB\r\n] 2006.134.08:02:32.56#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:32.56#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:02:32.56#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:02:32.56#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:02:32.56$vc4f8/vabw=wide 2006.134.08:02:32.56#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:02:32.56#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:02:32.56#ibcon#ireg 8 cls_cnt 0 2006.134.08:02:32.56#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:32.56#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:32.56#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:32.59#ibcon#[25=BW32\r\n] 2006.134.08:02:32.62#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:32.62#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:02:32.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:02:32.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:02:32.62$vc4f8/vbbw=wide 2006.134.08:02:32.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.08:02:32.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.08:02:32.62#ibcon#ireg 8 cls_cnt 0 2006.134.08:02:32.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:02:32.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:02:32.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:02:32.70#ibcon#[27=BW32\r\n] 2006.134.08:02:32.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:02:32.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:02:32.73#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:02:32.73#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:02:32.73$4f8m12a/ifd4f 2006.134.08:02:32.73$ifd4f/lo= 2006.134.08:02:32.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:02:32.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:02:32.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:02:32.73$ifd4f/patch= 2006.134.08:02:32.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:02:32.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:02:32.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:02:32.73$4f8m12a/"form=m,16.000,1:2 2006.134.08:02:32.73$4f8m12a/"tpicd 2006.134.08:02:32.73$4f8m12a/echo=off 2006.134.08:02:32.73$4f8m12a/xlog=off 2006.134.08:02:32.73:!2006.134.08:03:00 2006.134.08:02:36.14#trakl#Source acquired 2006.134.08:02:36.14#flagr#flagr/antenna,acquired 2006.134.08:03:00.00:preob 2006.134.08:03:01.14/onsource/TRACKING 2006.134.08:03:01.14:!2006.134.08:03:10 2006.134.08:03:10.00:data_valid=on 2006.134.08:03:10.00:midob 2006.134.08:03:10.14/onsource/TRACKING 2006.134.08:03:10.14/wx/18.91,1006.9,84 2006.134.08:03:10.20/cable/+6.5465E-03 2006.134.08:03:11.29/va/01,08,usb,yes,29,30 2006.134.08:03:11.29/va/02,07,usb,yes,29,30 2006.134.08:03:11.29/va/03,06,usb,yes,30,31 2006.134.08:03:11.29/va/04,07,usb,yes,29,32 2006.134.08:03:11.29/va/05,06,usb,yes,31,33 2006.134.08:03:11.29/va/06,05,usb,yes,32,31 2006.134.08:03:11.29/va/07,05,usb,yes,32,31 2006.134.08:03:11.29/va/08,06,usb,yes,29,29 2006.134.08:03:11.52/valo/01,532.99,yes,locked 2006.134.08:03:11.52/valo/02,572.99,yes,locked 2006.134.08:03:11.52/valo/03,672.99,yes,locked 2006.134.08:03:11.52/valo/04,832.99,yes,locked 2006.134.08:03:11.52/valo/05,652.99,yes,locked 2006.134.08:03:11.52/valo/06,772.99,yes,locked 2006.134.08:03:11.52/valo/07,832.99,yes,locked 2006.134.08:03:11.52/valo/08,852.99,yes,locked 2006.134.08:03:12.61/vb/01,04,usb,yes,28,27 2006.134.08:03:12.61/vb/02,04,usb,yes,30,32 2006.134.08:03:12.61/vb/03,04,usb,yes,27,30 2006.134.08:03:12.61/vb/04,04,usb,yes,27,28 2006.134.08:03:12.61/vb/05,04,usb,yes,26,30 2006.134.08:03:12.61/vb/06,04,usb,yes,27,30 2006.134.08:03:12.61/vb/07,04,usb,yes,29,29 2006.134.08:03:12.61/vb/08,04,usb,yes,27,30 2006.134.08:03:12.85/vblo/01,632.99,yes,locked 2006.134.08:03:12.85/vblo/02,640.99,yes,locked 2006.134.08:03:12.85/vblo/03,656.99,yes,locked 2006.134.08:03:12.85/vblo/04,712.99,yes,locked 2006.134.08:03:12.85/vblo/05,744.99,yes,locked 2006.134.08:03:12.85/vblo/06,752.99,yes,locked 2006.134.08:03:12.85/vblo/07,734.99,yes,locked 2006.134.08:03:12.85/vblo/08,744.99,yes,locked 2006.134.08:03:13.00/vabw/8 2006.134.08:03:13.15/vbbw/8 2006.134.08:03:13.24/xfe/off,on,14.7 2006.134.08:03:13.61/ifatt/23,28,28,28 2006.134.08:03:14.07/fmout-gps/S +1.76E-07 2006.134.08:03:14.11:!2006.134.08:04:10 2006.134.08:04:10.00:data_valid=off 2006.134.08:04:10.00:postob 2006.134.08:04:10.08/cable/+6.5494E-03 2006.134.08:04:10.08/wx/18.88,1006.9,84 2006.134.08:04:11.07/fmout-gps/S +1.76E-07 2006.134.08:04:11.07:scan_name=134-0805,k06134,60 2006.134.08:04:11.07:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.134.08:04:11.14#flagr#flagr/antenna,new-source 2006.134.08:04:12.14:checkk5 2006.134.08:04:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:04:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:04:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:04:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:04:14.00/chk_obsdata//k5ts1/T1340803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:04:14.37/chk_obsdata//k5ts2/T1340803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:04:14.73/chk_obsdata//k5ts3/T1340803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:04:15.09/chk_obsdata//k5ts4/T1340803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:04:15.78/k5log//k5ts1_log_newline 2006.134.08:04:16.47/k5log//k5ts2_log_newline 2006.134.08:04:17.15/k5log//k5ts3_log_newline 2006.134.08:04:17.83/k5log//k5ts4_log_newline 2006.134.08:04:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:04:17.86:4f8m12a=2 2006.134.08:04:17.86$4f8m12a/echo=on 2006.134.08:04:17.86$4f8m12a/pcalon 2006.134.08:04:17.86$pcalon/"no phase cal control is implemented here 2006.134.08:04:17.86$4f8m12a/"tpicd=stop 2006.134.08:04:17.86$4f8m12a/vc4f8 2006.134.08:04:17.86$vc4f8/valo=1,532.99 2006.134.08:04:17.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:04:17.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:04:17.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:17.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:17.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:17.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:04:17.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:17.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:17.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:04:17.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:04:17.95$vc4f8/va=1,8 2006.134.08:04:17.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.08:04:17.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.08:04:17.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:17.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:17.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:17.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:17.98#ibcon#[25=AT01-08\r\n] 2006.134.08:04:18.01#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:18.01#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:18.01#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.08:04:18.01#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:18.01#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:18.13#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:18.13#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:18.15#ibcon#[25=USB\r\n] 2006.134.08:04:18.18#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:18.18#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:18.18#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:04:18.18#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:04:18.18$vc4f8/valo=2,572.99 2006.134.08:04:18.18#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:04:18.18#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:04:18.18#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:18.18#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:18.18#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:18.18#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:04:18.25#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:18.25#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:18.25#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:04:18.25#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:04:18.25$vc4f8/va=2,7 2006.134.08:04:18.25#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.08:04:18.25#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.08:04:18.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:18.25#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:18.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:18.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:18.32#ibcon#[25=AT02-07\r\n] 2006.134.08:04:18.35#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:18.35#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:18.35#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.08:04:18.35#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:18.35#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:18.47#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:18.47#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:18.49#ibcon#[25=USB\r\n] 2006.134.08:04:18.52#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:18.52#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:18.52#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:04:18.52#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:04:18.52$vc4f8/valo=3,672.99 2006.134.08:04:18.52#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.08:04:18.52#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.08:04:18.52#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:18.52#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:18.52#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:18.52#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:18.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:04:18.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:18.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:18.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:04:18.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:04:18.59$vc4f8/va=3,6 2006.134.08:04:18.59#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.08:04:18.59#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.08:04:18.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:18.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:18.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:18.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:18.66#ibcon#[25=AT03-06\r\n] 2006.134.08:04:18.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:18.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:18.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.08:04:18.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:18.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:18.81#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:18.81#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:18.83#ibcon#[25=USB\r\n] 2006.134.08:04:18.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:18.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:18.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:04:18.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:04:18.86$vc4f8/valo=4,832.99 2006.134.08:04:18.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.08:04:18.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.08:04:18.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:18.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:18.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:18.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:18.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:04:18.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:18.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:18.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:04:18.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:04:18.92$vc4f8/va=4,7 2006.134.08:04:18.92#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:04:18.92#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:04:18.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:18.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:18.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:18.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:19.00#ibcon#[25=AT04-07\r\n] 2006.134.08:04:19.03#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:19.03#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:19.03#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:04:19.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:19.03#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:19.15#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:19.15#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:19.17#ibcon#[25=USB\r\n] 2006.134.08:04:19.20#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:19.20#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:19.20#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:04:19.20#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:04:19.20$vc4f8/valo=5,652.99 2006.134.08:04:19.20#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.08:04:19.20#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.08:04:19.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:19.20#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:19.20#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:19.20#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:19.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:04:19.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:19.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:19.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:04:19.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:04:19.27$vc4f8/va=5,6 2006.134.08:04:19.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.08:04:19.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.08:04:19.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:19.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:19.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:19.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:19.33#ibcon#[25=AT05-06\r\n] 2006.134.08:04:19.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:19.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:19.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.08:04:19.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:19.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:19.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:19.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:19.50#ibcon#[25=USB\r\n] 2006.134.08:04:19.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:19.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:19.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:04:19.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:04:19.53$vc4f8/valo=6,772.99 2006.134.08:04:19.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.08:04:19.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.08:04:19.53#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:19.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:19.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:19.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:04:19.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:19.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:19.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:04:19.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:04:19.59$vc4f8/va=6,5 2006.134.08:04:19.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.08:04:19.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.08:04:19.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:19.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:19.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:19.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:19.67#ibcon#[25=AT06-05\r\n] 2006.134.08:04:19.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:19.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:19.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.08:04:19.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:19.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:04:19.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:04:19.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:04:19.84#ibcon#[25=USB\r\n] 2006.134.08:04:19.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:04:19.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:04:19.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:04:19.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:04:19.87$vc4f8/valo=7,832.99 2006.134.08:04:19.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.08:04:19.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.08:04:19.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:19.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:04:19.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:04:19.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:04:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:04:19.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:04:19.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:04:19.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:04:19.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:04:19.93$vc4f8/va=7,5 2006.134.08:04:19.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.08:04:19.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.08:04:19.93#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:19.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:04:19.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:04:19.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:04:20.01#ibcon#[25=AT07-05\r\n] 2006.134.08:04:20.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:04:20.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:04:20.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.08:04:20.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:20.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:04:20.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:04:20.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:04:20.18#ibcon#[25=USB\r\n] 2006.134.08:04:20.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:04:20.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:04:20.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:04:20.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:04:20.21$vc4f8/valo=8,852.99 2006.134.08:04:20.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.08:04:20.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.08:04:20.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:20.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:04:20.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:04:20.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:04:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:04:20.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:04:20.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:04:20.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:04:20.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:04:20.27$vc4f8/va=8,6 2006.134.08:04:20.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.08:04:20.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.08:04:20.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:20.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:04:20.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:04:20.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:04:20.35#ibcon#[25=AT08-06\r\n] 2006.134.08:04:20.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:04:20.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:04:20.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.08:04:20.38#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:20.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:04:20.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:04:20.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:04:20.52#ibcon#[25=USB\r\n] 2006.134.08:04:20.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:04:20.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:04:20.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:04:20.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:04:20.55$vc4f8/vblo=1,632.99 2006.134.08:04:20.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:04:20.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:04:20.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:20.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:04:20.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:04:20.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:04:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:04:20.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:04:20.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:04:20.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:04:20.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:04:20.61$vc4f8/vb=1,4 2006.134.08:04:20.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.08:04:20.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.08:04:20.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:20.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:04:20.61#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:04:20.61#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:04:20.63#ibcon#[27=AT01-04\r\n] 2006.134.08:04:20.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:04:20.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:04:20.66#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.08:04:20.66#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:20.66#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:04:20.78#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:04:20.78#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:04:20.80#ibcon#[27=USB\r\n] 2006.134.08:04:20.83#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:04:20.83#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:04:20.83#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:04:20.83#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:04:20.83$vc4f8/vblo=2,640.99 2006.134.08:04:20.83#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:04:20.83#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:04:20.83#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:20.83#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:20.83#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:20.83#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:04:20.89#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:20.89#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:04:20.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:04:20.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:04:20.89$vc4f8/vb=2,4 2006.134.08:04:20.89#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.08:04:20.89#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.08:04:20.89#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:20.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:20.95#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:20.95#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:20.97#ibcon#[27=AT02-04\r\n] 2006.134.08:04:21.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:21.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:04:21.00#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.08:04:21.00#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:21.00#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:21.12#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:21.12#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:21.14#ibcon#[27=USB\r\n] 2006.134.08:04:21.17#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:21.17#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:04:21.17#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:04:21.17#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:04:21.17$vc4f8/vblo=3,656.99 2006.134.08:04:21.17#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:04:21.17#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:04:21.17#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:21.17#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:21.17#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:21.17#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:04:21.23#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:21.23#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:04:21.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:04:21.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:04:21.23$vc4f8/vb=3,4 2006.134.08:04:21.23#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.08:04:21.23#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.08:04:21.23#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:21.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:21.29#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:21.29#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:21.31#ibcon#[27=AT03-04\r\n] 2006.134.08:04:21.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:21.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:04:21.34#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.08:04:21.34#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:21.34#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:21.46#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:21.46#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:21.48#ibcon#[27=USB\r\n] 2006.134.08:04:21.51#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:21.51#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:04:21.51#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:04:21.51#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:04:21.51$vc4f8/vblo=4,712.99 2006.134.08:04:21.51#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.08:04:21.51#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.08:04:21.51#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:21.51#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:21.51#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:21.51#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:04:21.57#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:21.57#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:04:21.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:04:21.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:04:21.57$vc4f8/vb=4,4 2006.134.08:04:21.57#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.08:04:21.57#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.08:04:21.57#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:21.57#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:21.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:21.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:21.65#ibcon#[27=AT04-04\r\n] 2006.134.08:04:21.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:21.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:04:21.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.08:04:21.68#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:21.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:21.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:21.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:21.82#ibcon#[27=USB\r\n] 2006.134.08:04:21.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:21.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:04:21.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:04:21.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:04:21.85$vc4f8/vblo=5,744.99 2006.134.08:04:21.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.08:04:21.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.08:04:21.85#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:21.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:21.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:21.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:04:21.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:21.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:04:21.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:04:21.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:04:21.91$vc4f8/vb=5,4 2006.134.08:04:21.91#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:04:21.91#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:04:21.91#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:21.91#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:21.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:21.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:21.99#ibcon#[27=AT05-04\r\n] 2006.134.08:04:22.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:22.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:04:22.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:04:22.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:22.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:22.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:22.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:22.16#ibcon#[27=USB\r\n] 2006.134.08:04:22.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:22.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:04:22.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:04:22.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:04:22.19$vc4f8/vblo=6,752.99 2006.134.08:04:22.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.08:04:22.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.08:04:22.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:04:22.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:22.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:22.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:22.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:04:22.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:22.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:04:22.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:04:22.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:04:22.25$vc4f8/vb=6,4 2006.134.08:04:22.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.08:04:22.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.08:04:22.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:04:22.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:22.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:22.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:22.33#ibcon#[27=AT06-04\r\n] 2006.134.08:04:22.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:22.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:04:22.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.08:04:22.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:04:22.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:22.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:22.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:22.50#ibcon#[27=USB\r\n] 2006.134.08:04:22.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:22.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:04:22.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:04:22.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:04:22.53$vc4f8/vabw=wide 2006.134.08:04:22.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.08:04:22.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.08:04:22.53#ibcon#ireg 8 cls_cnt 0 2006.134.08:04:22.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:22.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:22.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:22.55#ibcon#[25=BW32\r\n] 2006.134.08:04:22.58#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:22.58#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:04:22.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:04:22.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:04:22.58$vc4f8/vbbw=wide 2006.134.08:04:22.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:04:22.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:04:22.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:04:22.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:04:22.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:04:22.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:04:22.67#ibcon#[27=BW32\r\n] 2006.134.08:04:22.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:04:22.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:04:22.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:04:22.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:04:22.70$4f8m12a/ifd4f 2006.134.08:04:22.70$ifd4f/lo= 2006.134.08:04:22.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:04:22.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:04:22.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:04:22.70$ifd4f/patch= 2006.134.08:04:22.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:04:22.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:04:22.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:04:22.70$4f8m12a/"form=m,16.000,1:2 2006.134.08:04:22.70$4f8m12a/"tpicd 2006.134.08:04:22.70$4f8m12a/echo=off 2006.134.08:04:22.70$4f8m12a/xlog=off 2006.134.08:04:22.70:!2006.134.08:04:50 2006.134.08:04:33.14#trakl#Source acquired 2006.134.08:04:35.14#flagr#flagr/antenna,acquired 2006.134.08:04:50.00:preob 2006.134.08:04:51.14/onsource/TRACKING 2006.134.08:04:51.14:!2006.134.08:05:00 2006.134.08:05:00.00:data_valid=on 2006.134.08:05:00.00:midob 2006.134.08:05:00.14/onsource/TRACKING 2006.134.08:05:00.14/wx/18.85,1006.9,84 2006.134.08:05:00.29/cable/+6.5456E-03 2006.134.08:05:01.38/va/01,08,usb,yes,29,30 2006.134.08:05:01.38/va/02,07,usb,yes,29,30 2006.134.08:05:01.38/va/03,06,usb,yes,30,30 2006.134.08:05:01.38/va/04,07,usb,yes,29,31 2006.134.08:05:01.38/va/05,06,usb,yes,31,33 2006.134.08:05:01.38/va/06,05,usb,yes,31,31 2006.134.08:05:01.38/va/07,05,usb,yes,31,31 2006.134.08:05:01.38/va/08,06,usb,yes,29,28 2006.134.08:05:01.61/valo/01,532.99,yes,locked 2006.134.08:05:01.61/valo/02,572.99,yes,locked 2006.134.08:05:01.61/valo/03,672.99,yes,locked 2006.134.08:05:01.61/valo/04,832.99,yes,locked 2006.134.08:05:01.61/valo/05,652.99,yes,locked 2006.134.08:05:01.61/valo/06,772.99,yes,locked 2006.134.08:05:01.61/valo/07,832.99,yes,locked 2006.134.08:05:01.61/valo/08,852.99,yes,locked 2006.134.08:05:02.70/vb/01,04,usb,yes,28,27 2006.134.08:05:02.70/vb/02,04,usb,yes,30,32 2006.134.08:05:02.70/vb/03,04,usb,yes,27,30 2006.134.08:05:02.70/vb/04,04,usb,yes,28,28 2006.134.08:05:02.70/vb/05,04,usb,yes,26,30 2006.134.08:05:02.70/vb/06,04,usb,yes,27,30 2006.134.08:05:02.70/vb/07,04,usb,yes,29,29 2006.134.08:05:02.70/vb/08,04,usb,yes,27,30 2006.134.08:05:02.94/vblo/01,632.99,yes,locked 2006.134.08:05:02.94/vblo/02,640.99,yes,locked 2006.134.08:05:02.94/vblo/03,656.99,yes,locked 2006.134.08:05:02.94/vblo/04,712.99,yes,locked 2006.134.08:05:02.94/vblo/05,744.99,yes,locked 2006.134.08:05:02.94/vblo/06,752.99,yes,locked 2006.134.08:05:02.94/vblo/07,734.99,yes,locked 2006.134.08:05:02.94/vblo/08,744.99,yes,locked 2006.134.08:05:03.09/vabw/8 2006.134.08:05:03.24/vbbw/8 2006.134.08:05:03.33/xfe/off,on,15.2 2006.134.08:05:03.71/ifatt/23,28,28,28 2006.134.08:05:04.08/fmout-gps/S +1.76E-07 2006.134.08:05:04.12:!2006.134.08:06:00 2006.134.08:06:00.00:data_valid=off 2006.134.08:06:00.00:postob 2006.134.08:06:00.09/cable/+6.5442E-03 2006.134.08:06:00.09/wx/18.82,1006.9,84 2006.134.08:06:01.08/fmout-gps/S +1.76E-07 2006.134.08:06:01.08:scan_name=134-0806,k06134,60 2006.134.08:06:01.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.134.08:06:01.13#flagr#flagr/antenna,new-source 2006.134.08:06:02.13:checkk5 2006.134.08:06:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:06:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:06:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:06:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:06:04.00/chk_obsdata//k5ts1/T1340805??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:06:04.37/chk_obsdata//k5ts2/T1340805??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:06:04.73/chk_obsdata//k5ts3/T1340805??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:06:05.10/chk_obsdata//k5ts4/T1340805??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:06:05.79/k5log//k5ts1_log_newline 2006.134.08:06:06.48/k5log//k5ts2_log_newline 2006.134.08:06:07.16/k5log//k5ts3_log_newline 2006.134.08:06:07.84/k5log//k5ts4_log_newline 2006.134.08:06:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:06:07.87:4f8m12a=2 2006.134.08:06:07.87$4f8m12a/echo=on 2006.134.08:06:07.87$4f8m12a/pcalon 2006.134.08:06:07.87$pcalon/"no phase cal control is implemented here 2006.134.08:06:07.87$4f8m12a/"tpicd=stop 2006.134.08:06:07.87$4f8m12a/vc4f8 2006.134.08:06:07.87$vc4f8/valo=1,532.99 2006.134.08:06:07.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.08:06:07.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.08:06:07.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:07.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:07.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:07.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:07.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:06:07.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:07.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:07.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:06:07.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:06:07.96$vc4f8/va=1,8 2006.134.08:06:07.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.08:06:07.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.08:06:07.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:07.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:07.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:07.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:07.98#ibcon#[25=AT01-08\r\n] 2006.134.08:06:08.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:08.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:08.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.08:06:08.01#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:08.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:08.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:08.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:08.15#ibcon#[25=USB\r\n] 2006.134.08:06:08.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:08.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:08.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:06:08.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:06:08.18$vc4f8/valo=2,572.99 2006.134.08:06:08.18#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:06:08.18#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:06:08.18#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:08.18#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:08.18#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:08.18#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:08.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:06:08.25#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:08.25#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:08.25#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:06:08.25#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:06:08.25$vc4f8/va=2,7 2006.134.08:06:08.25#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.08:06:08.25#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.08:06:08.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:08.25#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:08.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:08.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:08.32#ibcon#[25=AT02-07\r\n] 2006.134.08:06:08.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:08.35#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:08.35#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.08:06:08.35#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:08.35#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:08.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:08.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:08.49#ibcon#[25=USB\r\n] 2006.134.08:06:08.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:08.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:08.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:06:08.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:06:08.52$vc4f8/valo=3,672.99 2006.134.08:06:08.52#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.08:06:08.52#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.08:06:08.52#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:08.52#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:08.52#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:08.52#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:08.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:06:08.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:08.59#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:08.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:06:08.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:06:08.59$vc4f8/va=3,6 2006.134.08:06:08.59#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.08:06:08.59#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.08:06:08.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:08.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:08.64#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:08.64#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:08.66#ibcon#[25=AT03-06\r\n] 2006.134.08:06:08.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:08.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:08.69#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.08:06:08.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:08.69#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:08.81#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:08.81#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:08.83#ibcon#[25=USB\r\n] 2006.134.08:06:08.86#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:08.86#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:08.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:06:08.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:06:08.86$vc4f8/valo=4,832.99 2006.134.08:06:08.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.08:06:08.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.08:06:08.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:08.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:08.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:08.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:06:08.92#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:08.92#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:08.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:06:08.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:06:08.92$vc4f8/va=4,7 2006.134.08:06:08.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.08:06:08.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.08:06:08.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:08.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:08.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:08.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:09.00#ibcon#[25=AT04-07\r\n] 2006.134.08:06:09.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:09.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:09.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.08:06:09.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:09.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:09.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:09.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:09.17#ibcon#[25=USB\r\n] 2006.134.08:06:09.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:09.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:09.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:06:09.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:06:09.20$vc4f8/valo=5,652.99 2006.134.08:06:09.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.08:06:09.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.08:06:09.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:09.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:09.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:09.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:09.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:06:09.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:09.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:09.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:06:09.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:06:09.26$vc4f8/va=5,6 2006.134.08:06:09.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.08:06:09.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.08:06:09.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:09.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:09.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:09.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:09.34#ibcon#[25=AT05-06\r\n] 2006.134.08:06:09.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:09.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:09.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.08:06:09.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:09.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:09.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:09.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:09.51#ibcon#[25=USB\r\n] 2006.134.08:06:09.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:09.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:09.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:06:09.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:06:09.54$vc4f8/valo=6,772.99 2006.134.08:06:09.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:06:09.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:06:09.54#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:09.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:09.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:09.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:06:09.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:09.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:09.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:06:09.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:06:09.60$vc4f8/va=6,5 2006.134.08:06:09.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.08:06:09.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.08:06:09.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:09.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:09.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:09.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:09.68#ibcon#[25=AT06-05\r\n] 2006.134.08:06:09.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:09.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:09.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.08:06:09.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:09.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:06:09.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:06:09.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:06:09.85#ibcon#[25=USB\r\n] 2006.134.08:06:09.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:06:09.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:06:09.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:06:09.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:06:09.88$vc4f8/valo=7,832.99 2006.134.08:06:09.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.08:06:09.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.08:06:09.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:09.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:06:09.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:06:09.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:06:09.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:06:09.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:06:09.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:06:09.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:06:09.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:06:09.94$vc4f8/va=7,5 2006.134.08:06:09.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.08:06:09.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.08:06:09.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:09.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:06:10.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:06:10.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:06:10.02#ibcon#[25=AT07-05\r\n] 2006.134.08:06:10.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:06:10.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:06:10.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.08:06:10.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:10.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:06:10.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:06:10.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:06:10.19#ibcon#[25=USB\r\n] 2006.134.08:06:10.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:06:10.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:06:10.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:06:10.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:06:10.22$vc4f8/valo=8,852.99 2006.134.08:06:10.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.08:06:10.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.08:06:10.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:10.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:06:10.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:06:10.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:06:10.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:06:10.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:06:10.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:06:10.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:06:10.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:06:10.28$vc4f8/va=8,6 2006.134.08:06:10.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.08:06:10.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.08:06:10.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:10.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:06:10.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:06:10.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:06:10.36#ibcon#[25=AT08-06\r\n] 2006.134.08:06:10.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:06:10.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:06:10.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.08:06:10.40#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:10.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:06:10.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:06:10.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:06:10.54#ibcon#[25=USB\r\n] 2006.134.08:06:10.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:06:10.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:06:10.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:06:10.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:06:10.57$vc4f8/vblo=1,632.99 2006.134.08:06:10.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.08:06:10.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.08:06:10.57#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:10.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:06:10.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:06:10.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:06:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:06:10.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:06:10.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:06:10.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:06:10.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:06:10.63$vc4f8/vb=1,4 2006.134.08:06:10.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.08:06:10.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.08:06:10.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:10.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:06:10.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:06:10.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:06:10.65#ibcon#[27=AT01-04\r\n] 2006.134.08:06:10.68#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:06:10.68#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:06:10.68#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.08:06:10.68#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:10.68#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:06:10.80#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:06:10.80#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:06:10.82#ibcon#[27=USB\r\n] 2006.134.08:06:10.85#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:06:10.85#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:06:10.85#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:06:10.85#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:06:10.85$vc4f8/vblo=2,640.99 2006.134.08:06:10.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.08:06:10.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.08:06:10.85#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:10.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:10.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:10.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:06:10.91#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:10.91#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:06:10.91#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:06:10.91#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:06:10.91$vc4f8/vb=2,4 2006.134.08:06:10.91#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.08:06:10.91#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.08:06:10.91#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:10.91#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:10.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:10.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:10.99#ibcon#[27=AT02-04\r\n] 2006.134.08:06:11.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:11.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:06:11.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.08:06:11.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:11.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:11.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:11.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:11.16#ibcon#[27=USB\r\n] 2006.134.08:06:11.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:11.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:06:11.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:06:11.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:06:11.21$vc4f8/vblo=3,656.99 2006.134.08:06:11.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:06:11.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:06:11.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:11.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:11.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:11.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:11.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:06:11.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:11.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:06:11.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:06:11.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:06:11.26$vc4f8/vb=3,4 2006.134.08:06:11.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.08:06:11.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.08:06:11.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:11.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:11.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:11.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:11.35#ibcon#[27=AT03-04\r\n] 2006.134.08:06:11.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:11.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:06:11.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.08:06:11.38#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:11.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:11.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:11.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:11.52#ibcon#[27=USB\r\n] 2006.134.08:06:11.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:11.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:06:11.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:06:11.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:06:11.55$vc4f8/vblo=4,712.99 2006.134.08:06:11.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.08:06:11.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.08:06:11.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:11.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:11.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:11.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:11.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:06:11.61#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:11.61#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:06:11.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:06:11.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:06:11.61$vc4f8/vb=4,4 2006.134.08:06:11.61#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.08:06:11.61#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.08:06:11.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:11.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:11.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:11.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:11.69#ibcon#[27=AT04-04\r\n] 2006.134.08:06:11.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:11.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:06:11.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.08:06:11.72#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:11.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:11.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:11.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:11.86#ibcon#[27=USB\r\n] 2006.134.08:06:11.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:11.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:06:11.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:06:11.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:06:11.89$vc4f8/vblo=5,744.99 2006.134.08:06:11.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.08:06:11.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.08:06:11.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:11.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:11.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:11.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:11.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:06:11.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:11.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:06:11.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:06:11.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:06:11.95$vc4f8/vb=5,4 2006.134.08:06:11.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.08:06:11.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.08:06:11.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:11.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:12.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:12.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:12.03#ibcon#[27=AT05-04\r\n] 2006.134.08:06:12.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:12.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:06:12.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.08:06:12.06#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:12.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:12.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:12.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:12.20#ibcon#[27=USB\r\n] 2006.134.08:06:12.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:12.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:06:12.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:06:12.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:06:12.23$vc4f8/vblo=6,752.99 2006.134.08:06:12.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.08:06:12.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.08:06:12.23#ibcon#ireg 17 cls_cnt 0 2006.134.08:06:12.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:12.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:12.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:12.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:06:12.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:12.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:06:12.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:06:12.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:06:12.29$vc4f8/vb=6,4 2006.134.08:06:12.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.08:06:12.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.08:06:12.29#ibcon#ireg 11 cls_cnt 2 2006.134.08:06:12.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:12.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:12.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:12.37#ibcon#[27=AT06-04\r\n] 2006.134.08:06:12.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:12.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:06:12.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.08:06:12.40#ibcon#ireg 7 cls_cnt 0 2006.134.08:06:12.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:12.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:12.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:12.54#ibcon#[27=USB\r\n] 2006.134.08:06:12.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:12.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:06:12.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:06:12.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:06:12.57$vc4f8/vabw=wide 2006.134.08:06:12.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:06:12.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:06:12.57#ibcon#ireg 8 cls_cnt 0 2006.134.08:06:12.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:12.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:12.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:12.59#ibcon#[25=BW32\r\n] 2006.134.08:06:12.62#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:12.62#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:06:12.62#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:06:12.62#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:06:12.62$vc4f8/vbbw=wide 2006.134.08:06:12.62#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:06:12.62#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:06:12.62#ibcon#ireg 8 cls_cnt 0 2006.134.08:06:12.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:06:12.69#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:06:12.69#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:06:12.71#ibcon#[27=BW32\r\n] 2006.134.08:06:12.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:06:12.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:06:12.74#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:06:12.74#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:06:12.74$4f8m12a/ifd4f 2006.134.08:06:12.74$ifd4f/lo= 2006.134.08:06:12.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:06:12.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:06:12.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:06:12.74$ifd4f/patch= 2006.134.08:06:12.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:06:12.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:06:12.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:06:12.74$4f8m12a/"form=m,16.000,1:2 2006.134.08:06:12.74$4f8m12a/"tpicd 2006.134.08:06:12.74$4f8m12a/echo=off 2006.134.08:06:12.74$4f8m12a/xlog=off 2006.134.08:06:12.74:!2006.134.08:06:40 2006.134.08:06:24.13#trakl#Source acquired 2006.134.08:06:25.13#flagr#flagr/antenna,acquired 2006.134.08:06:40.00:preob 2006.134.08:06:41.13/onsource/TRACKING 2006.134.08:06:41.13:!2006.134.08:06:50 2006.134.08:06:50.00:data_valid=on 2006.134.08:06:50.00:midob 2006.134.08:06:50.13/onsource/TRACKING 2006.134.08:06:50.13/wx/18.79,1006.9,85 2006.134.08:06:50.34/cable/+6.5462E-03 2006.134.08:06:51.43/va/01,08,usb,yes,29,30 2006.134.08:06:51.43/va/02,07,usb,yes,29,30 2006.134.08:06:51.43/va/03,06,usb,yes,30,31 2006.134.08:06:51.43/va/04,07,usb,yes,29,32 2006.134.08:06:51.43/va/05,06,usb,yes,31,33 2006.134.08:06:51.43/va/06,05,usb,yes,31,31 2006.134.08:06:51.43/va/07,05,usb,yes,32,31 2006.134.08:06:51.43/va/08,06,usb,yes,29,29 2006.134.08:06:51.66/valo/01,532.99,yes,locked 2006.134.08:06:51.66/valo/02,572.99,yes,locked 2006.134.08:06:51.66/valo/03,672.99,yes,locked 2006.134.08:06:51.66/valo/04,832.99,yes,locked 2006.134.08:06:51.66/valo/05,652.99,yes,locked 2006.134.08:06:51.66/valo/06,772.99,yes,locked 2006.134.08:06:51.66/valo/07,832.99,yes,locked 2006.134.08:06:51.66/valo/08,852.99,yes,locked 2006.134.08:06:52.75/vb/01,04,usb,yes,28,27 2006.134.08:06:52.75/vb/02,04,usb,yes,30,31 2006.134.08:06:52.75/vb/03,04,usb,yes,27,30 2006.134.08:06:52.75/vb/04,04,usb,yes,27,28 2006.134.08:06:52.75/vb/05,04,usb,yes,26,30 2006.134.08:06:52.75/vb/06,04,usb,yes,27,30 2006.134.08:06:52.75/vb/07,04,usb,yes,29,29 2006.134.08:06:52.75/vb/08,04,usb,yes,27,30 2006.134.08:06:52.98/vblo/01,632.99,yes,locked 2006.134.08:06:52.98/vblo/02,640.99,yes,locked 2006.134.08:06:52.98/vblo/03,656.99,yes,locked 2006.134.08:06:52.98/vblo/04,712.99,yes,locked 2006.134.08:06:52.98/vblo/05,744.99,yes,locked 2006.134.08:06:52.98/vblo/06,752.99,yes,locked 2006.134.08:06:52.98/vblo/07,734.99,yes,locked 2006.134.08:06:52.98/vblo/08,744.99,yes,locked 2006.134.08:06:53.13/vabw/8 2006.134.08:06:53.28/vbbw/8 2006.134.08:06:53.44/xfe/off,on,15.2 2006.134.08:06:53.82/ifatt/23,28,28,28 2006.134.08:06:54.08/fmout-gps/S +1.76E-07 2006.134.08:06:54.12:!2006.134.08:07:50 2006.134.08:07:50.00:data_valid=off 2006.134.08:07:50.00:postob 2006.134.08:07:50.13/cable/+6.5448E-03 2006.134.08:07:50.13/wx/18.76,1007.0,85 2006.134.08:07:51.08/fmout-gps/S +1.75E-07 2006.134.08:07:51.08:scan_name=134-0808,k06134,60 2006.134.08:07:51.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.134.08:07:51.13#flagr#flagr/antenna,new-source 2006.134.08:07:52.14:checkk5 2006.134.08:07:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:07:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:07:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:07:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:07:54.00/chk_obsdata//k5ts1/T1340806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:07:54.37/chk_obsdata//k5ts2/T1340806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:07:54.74/chk_obsdata//k5ts3/T1340806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:07:55.11/chk_obsdata//k5ts4/T1340806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:07:55.80/k5log//k5ts1_log_newline 2006.134.08:07:56.49/k5log//k5ts2_log_newline 2006.134.08:07:57.17/k5log//k5ts3_log_newline 2006.134.08:07:57.86/k5log//k5ts4_log_newline 2006.134.08:07:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:07:57.89:4f8m12a=2 2006.134.08:07:57.89$4f8m12a/echo=on 2006.134.08:07:57.89$4f8m12a/pcalon 2006.134.08:07:57.89$pcalon/"no phase cal control is implemented here 2006.134.08:07:57.89$4f8m12a/"tpicd=stop 2006.134.08:07:57.89$4f8m12a/vc4f8 2006.134.08:07:57.89$vc4f8/valo=1,532.99 2006.134.08:07:57.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:07:57.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:07:57.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:57.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:07:57.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:07:57.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:07:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:07:57.98#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:07:57.98#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:07:57.98#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:07:57.98#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:07:57.98$vc4f8/va=1,8 2006.134.08:07:57.98#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:07:57.98#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:07:57.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:57.98#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:07:57.98#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:07:57.98#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:07:58.01#ibcon#[25=AT01-08\r\n] 2006.134.08:07:58.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:07:58.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:07:58.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:07:58.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:58.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:07:58.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:07:58.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:07:58.18#ibcon#[25=USB\r\n] 2006.134.08:07:58.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:07:58.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:07:58.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:07:58.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:07:58.21$vc4f8/valo=2,572.99 2006.134.08:07:58.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:07:58.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:07:58.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:58.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:07:58.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:07:58.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:07:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:07:58.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:07:58.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:07:58.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:07:58.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:07:58.27$vc4f8/va=2,7 2006.134.08:07:58.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:07:58.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:07:58.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:58.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:07:58.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:07:58.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:07:58.35#ibcon#[25=AT02-07\r\n] 2006.134.08:07:58.38#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:07:58.38#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:07:58.38#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:07:58.38#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:58.38#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:07:58.50#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:07:58.50#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:07:58.52#ibcon#[25=USB\r\n] 2006.134.08:07:58.55#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:07:58.55#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:07:58.55#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:07:58.55#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:07:58.55$vc4f8/valo=3,672.99 2006.134.08:07:58.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:07:58.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:07:58.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:58.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:07:58.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:07:58.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:07:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:07:58.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:07:58.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:07:58.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:07:58.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:07:58.62$vc4f8/va=3,6 2006.134.08:07:58.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:07:58.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:07:58.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:58.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:07:58.67#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:07:58.67#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:07:58.69#ibcon#[25=AT03-06\r\n] 2006.134.08:07:58.72#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:07:58.72#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:07:58.72#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:07:58.72#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:58.72#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:07:58.84#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:07:58.84#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:07:58.86#ibcon#[25=USB\r\n] 2006.134.08:07:58.89#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:07:58.89#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:07:58.89#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:07:58.89#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:07:58.89$vc4f8/valo=4,832.99 2006.134.08:07:58.89#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:07:58.89#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:07:58.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:58.89#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:07:58.89#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:07:58.89#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:07:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:07:58.95#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:07:58.95#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:07:58.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:07:58.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:07:58.95$vc4f8/va=4,7 2006.134.08:07:58.95#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:07:58.95#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:07:58.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:58.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:07:59.01#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:07:59.01#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:07:59.03#ibcon#[25=AT04-07\r\n] 2006.134.08:07:59.06#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:07:59.06#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:07:59.06#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:07:59.06#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:59.06#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:07:59.18#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:07:59.18#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:07:59.20#ibcon#[25=USB\r\n] 2006.134.08:07:59.23#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:07:59.23#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:07:59.23#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:07:59.23#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:07:59.23$vc4f8/valo=5,652.99 2006.134.08:07:59.23#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:07:59.23#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:07:59.23#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:59.23#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:07:59.23#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:07:59.23#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:07:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:07:59.29#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:07:59.29#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:07:59.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:07:59.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:07:59.29$vc4f8/va=5,6 2006.134.08:07:59.29#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:07:59.29#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:07:59.29#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:59.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:07:59.35#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:07:59.35#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:07:59.37#ibcon#[25=AT05-06\r\n] 2006.134.08:07:59.40#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:07:59.40#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:07:59.40#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:07:59.40#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:59.40#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:07:59.52#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:07:59.52#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:07:59.54#ibcon#[25=USB\r\n] 2006.134.08:07:59.57#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:07:59.57#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:07:59.57#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:07:59.57#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:07:59.57$vc4f8/valo=6,772.99 2006.134.08:07:59.57#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:07:59.57#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:07:59.57#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:59.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:07:59.57#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:07:59.57#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:07:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:07:59.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:07:59.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:07:59.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:07:59.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:07:59.63$vc4f8/va=6,5 2006.134.08:07:59.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:07:59.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:07:59.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:59.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:07:59.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:07:59.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:07:59.71#ibcon#[25=AT06-05\r\n] 2006.134.08:07:59.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:07:59.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:07:59.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:07:59.74#ibcon#ireg 7 cls_cnt 0 2006.134.08:07:59.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:07:59.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:07:59.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:07:59.88#ibcon#[25=USB\r\n] 2006.134.08:07:59.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:07:59.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:07:59.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:07:59.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:07:59.91$vc4f8/valo=7,832.99 2006.134.08:07:59.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:07:59.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:07:59.91#ibcon#ireg 17 cls_cnt 0 2006.134.08:07:59.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:07:59.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:07:59.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:07:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:07:59.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:07:59.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:07:59.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:07:59.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:07:59.97$vc4f8/va=7,5 2006.134.08:07:59.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:07:59.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:07:59.97#ibcon#ireg 11 cls_cnt 2 2006.134.08:07:59.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:08:00.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:08:00.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:08:00.05#ibcon#[25=AT07-05\r\n] 2006.134.08:08:00.08#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:08:00.08#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:08:00.08#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:08:00.08#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:00.08#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:08:00.20#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:08:00.20#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:08:00.22#ibcon#[25=USB\r\n] 2006.134.08:08:00.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:08:00.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:08:00.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:08:00.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:08:00.26$vc4f8/valo=8,852.99 2006.134.08:08:00.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:08:00.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:08:00.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:00.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:08:00.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:08:00.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:08:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:08:00.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:08:00.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:08:00.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:08:00.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:08:00.32$vc4f8/va=8,6 2006.134.08:08:00.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.08:08:00.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.08:08:00.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:00.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:08:00.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:08:00.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:08:00.40#ibcon#[25=AT08-06\r\n] 2006.134.08:08:00.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:08:00.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:08:00.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.08:08:00.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:00.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:08:00.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:08:00.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:08:00.57#ibcon#[25=USB\r\n] 2006.134.08:08:00.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:08:00.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:08:00.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:08:00.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:08:00.60$vc4f8/vblo=1,632.99 2006.134.08:08:00.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:08:00.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:08:00.60#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:00.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:08:00.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:08:00.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:08:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:08:00.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:08:00.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:08:00.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:08:00.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:08:00.66$vc4f8/vb=1,4 2006.134.08:08:00.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:08:00.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:08:00.66#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:00.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:08:00.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:08:00.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:08:00.68#ibcon#[27=AT01-04\r\n] 2006.134.08:08:00.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:08:00.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:08:00.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:08:00.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:00.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:08:00.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:08:00.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:08:00.85#ibcon#[27=USB\r\n] 2006.134.08:08:00.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:08:00.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:08:00.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:08:00.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:08:00.88$vc4f8/vblo=2,640.99 2006.134.08:08:00.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:08:00.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:08:00.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:00.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:08:00.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:08:00.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:08:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:08:00.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:08:00.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:08:00.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:08:00.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:08:00.94$vc4f8/vb=2,4 2006.134.08:08:00.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:08:00.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:08:00.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:00.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:08:01.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:08:01.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:08:01.02#ibcon#[27=AT02-04\r\n] 2006.134.08:08:01.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:08:01.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:08:01.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:08:01.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:01.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:08:01.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:08:01.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:08:01.19#ibcon#[27=USB\r\n] 2006.134.08:08:01.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:08:01.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:08:01.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:08:01.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:08:01.22$vc4f8/vblo=3,656.99 2006.134.08:08:01.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:08:01.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:08:01.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:01.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:08:01.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:08:01.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:08:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:08:01.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:08:01.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:08:01.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:08:01.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:08:01.28$vc4f8/vb=3,4 2006.134.08:08:01.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:08:01.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:08:01.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:01.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:08:01.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:08:01.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:08:01.36#ibcon#[27=AT03-04\r\n] 2006.134.08:08:01.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:08:01.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:08:01.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:08:01.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:01.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:08:01.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:08:01.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:08:01.53#ibcon#[27=USB\r\n] 2006.134.08:08:01.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:08:01.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:08:01.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:08:01.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:08:01.56$vc4f8/vblo=4,712.99 2006.134.08:08:01.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:08:01.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:08:01.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:01.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:08:01.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:08:01.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:08:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:08:01.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:08:01.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:08:01.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:08:01.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:08:01.63$vc4f8/vb=4,4 2006.134.08:08:01.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:08:01.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:08:01.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:01.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:08:01.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:08:01.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:08:01.70#ibcon#[27=AT04-04\r\n] 2006.134.08:08:01.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:08:01.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:08:01.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:08:01.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:01.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:08:01.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:08:01.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:08:01.87#ibcon#[27=USB\r\n] 2006.134.08:08:01.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:08:01.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:08:01.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:08:01.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:08:01.90$vc4f8/vblo=5,744.99 2006.134.08:08:01.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:08:01.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:08:01.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:01.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:08:01.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:08:01.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:08:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:08:01.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:08:01.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:08:01.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:08:01.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:08:01.96$vc4f8/vb=5,4 2006.134.08:08:01.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:08:01.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:08:01.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:01.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:08:02.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:08:02.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:08:02.04#ibcon#[27=AT05-04\r\n] 2006.134.08:08:02.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:08:02.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:08:02.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:08:02.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:02.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:08:02.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:08:02.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:08:02.21#ibcon#[27=USB\r\n] 2006.134.08:08:02.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:08:02.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:08:02.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:08:02.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:08:02.24$vc4f8/vblo=6,752.99 2006.134.08:08:02.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:08:02.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:08:02.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:08:02.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:08:02.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:08:02.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:08:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:08:02.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:08:02.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:08:02.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:08:02.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:08:02.30$vc4f8/vb=6,4 2006.134.08:08:02.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:08:02.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:08:02.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:08:02.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:08:02.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:08:02.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:08:02.38#ibcon#[27=AT06-04\r\n] 2006.134.08:08:02.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:08:02.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:08:02.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:08:02.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:08:02.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:08:02.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:08:02.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:08:02.55#ibcon#[27=USB\r\n] 2006.134.08:08:02.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:08:02.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:08:02.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:08:02.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:08:02.58$vc4f8/vabw=wide 2006.134.08:08:02.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:08:02.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:08:02.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:08:02.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:08:02.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:08:02.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:08:02.60#ibcon#[25=BW32\r\n] 2006.134.08:08:02.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:08:02.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:08:02.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:08:02.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:08:02.63$vc4f8/vbbw=wide 2006.134.08:08:02.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.08:08:02.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.08:08:02.63#ibcon#ireg 8 cls_cnt 0 2006.134.08:08:02.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:08:02.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:08:02.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:08:02.72#ibcon#[27=BW32\r\n] 2006.134.08:08:02.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:08:02.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:08:02.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:08:02.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:08:02.75$4f8m12a/ifd4f 2006.134.08:08:02.75$ifd4f/lo= 2006.134.08:08:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:08:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:08:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:08:02.75$ifd4f/patch= 2006.134.08:08:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:08:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:08:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:08:02.75$4f8m12a/"form=m,16.000,1:2 2006.134.08:08:02.75$4f8m12a/"tpicd 2006.134.08:08:02.75$4f8m12a/echo=off 2006.134.08:08:02.75$4f8m12a/xlog=off 2006.134.08:08:02.75:!2006.134.08:08:30 2006.134.08:08:10.14#trakl#Source acquired 2006.134.08:08:12.14#flagr#flagr/antenna,acquired 2006.134.08:08:30.00:preob 2006.134.08:08:31.14/onsource/TRACKING 2006.134.08:08:31.14:!2006.134.08:08:40 2006.134.08:08:40.00:data_valid=on 2006.134.08:08:40.00:midob 2006.134.08:08:40.14/onsource/TRACKING 2006.134.08:08:40.14/wx/18.73,1007.0,85 2006.134.08:08:40.32/cable/+6.5460E-03 2006.134.08:08:41.41/va/01,08,usb,yes,29,31 2006.134.08:08:41.41/va/02,07,usb,yes,29,30 2006.134.08:08:41.41/va/03,06,usb,yes,31,31 2006.134.08:08:41.41/va/04,07,usb,yes,30,32 2006.134.08:08:41.41/va/05,06,usb,yes,32,34 2006.134.08:08:41.41/va/06,05,usb,yes,32,32 2006.134.08:08:41.41/va/07,05,usb,yes,32,32 2006.134.08:08:41.41/va/08,06,usb,yes,30,29 2006.134.08:08:41.64/valo/01,532.99,yes,locked 2006.134.08:08:41.64/valo/02,572.99,yes,locked 2006.134.08:08:41.64/valo/03,672.99,yes,locked 2006.134.08:08:41.64/valo/04,832.99,yes,locked 2006.134.08:08:41.64/valo/05,652.99,yes,locked 2006.134.08:08:41.64/valo/06,772.99,yes,locked 2006.134.08:08:41.64/valo/07,832.99,yes,locked 2006.134.08:08:41.64/valo/08,852.99,yes,locked 2006.134.08:08:42.73/vb/01,04,usb,yes,29,27 2006.134.08:08:42.73/vb/02,04,usb,yes,31,32 2006.134.08:08:42.73/vb/03,04,usb,yes,27,30 2006.134.08:08:42.73/vb/04,04,usb,yes,28,28 2006.134.08:08:42.73/vb/05,04,usb,yes,26,30 2006.134.08:08:42.73/vb/06,04,usb,yes,27,30 2006.134.08:08:42.73/vb/07,04,usb,yes,29,29 2006.134.08:08:42.73/vb/08,04,usb,yes,27,30 2006.134.08:08:42.96/vblo/01,632.99,yes,locked 2006.134.08:08:42.96/vblo/02,640.99,yes,locked 2006.134.08:08:42.96/vblo/03,656.99,yes,locked 2006.134.08:08:42.96/vblo/04,712.99,yes,locked 2006.134.08:08:42.96/vblo/05,744.99,yes,locked 2006.134.08:08:42.96/vblo/06,752.99,yes,locked 2006.134.08:08:42.96/vblo/07,734.99,yes,locked 2006.134.08:08:42.96/vblo/08,744.99,yes,locked 2006.134.08:08:43.11/vabw/8 2006.134.08:08:43.26/vbbw/8 2006.134.08:08:43.35/xfe/off,on,15.2 2006.134.08:08:43.72/ifatt/23,28,28,28 2006.134.08:08:44.07/fmout-gps/S +1.75E-07 2006.134.08:08:44.11:!2006.134.08:09:40 2006.134.08:09:40.00:data_valid=off 2006.134.08:09:40.00:postob 2006.134.08:09:40.13/cable/+6.5496E-03 2006.134.08:09:40.13/wx/18.70,1007.0,86 2006.134.08:09:41.08/fmout-gps/S +1.75E-07 2006.134.08:09:41.08:scan_name=134-0810,k06134,60 2006.134.08:09:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.134.08:09:41.14#flagr#flagr/antenna,new-source 2006.134.08:09:42.14:checkk5 2006.134.08:09:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:09:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:09:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:09:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:09:44.01/chk_obsdata//k5ts1/T1340808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:09:44.38/chk_obsdata//k5ts2/T1340808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:09:44.74/chk_obsdata//k5ts3/T1340808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:09:45.11/chk_obsdata//k5ts4/T1340808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:09:45.81/k5log//k5ts1_log_newline 2006.134.08:09:46.50/k5log//k5ts2_log_newline 2006.134.08:09:47.19/k5log//k5ts3_log_newline 2006.134.08:09:47.88/k5log//k5ts4_log_newline 2006.134.08:09:47.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:09:47.91:4f8m12a=2 2006.134.08:09:47.91$4f8m12a/echo=on 2006.134.08:09:47.91$4f8m12a/pcalon 2006.134.08:09:47.91$pcalon/"no phase cal control is implemented here 2006.134.08:09:47.91$4f8m12a/"tpicd=stop 2006.134.08:09:47.91$4f8m12a/vc4f8 2006.134.08:09:47.91$vc4f8/valo=1,532.99 2006.134.08:09:47.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:09:47.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:09:47.91#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:47.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:47.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:47.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:47.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:09:47.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:47.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:47.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:09:47.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:09:47.98$vc4f8/va=1,8 2006.134.08:09:47.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:09:47.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:09:47.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:47.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:47.98#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:47.98#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:48.00#ibcon#[25=AT01-08\r\n] 2006.134.08:09:48.03#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:48.03#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:48.03#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:09:48.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:48.03#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:48.15#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:48.15#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:48.17#ibcon#[25=USB\r\n] 2006.134.08:09:48.20#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:48.20#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:48.20#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:09:48.20#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:09:48.20$vc4f8/valo=2,572.99 2006.134.08:09:48.20#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:09:48.20#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:09:48.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:48.20#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:48.20#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:48.20#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:48.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:09:48.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:48.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:48.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:09:48.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:09:48.26$vc4f8/va=2,7 2006.134.08:09:48.26#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.08:09:48.26#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.08:09:48.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:48.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:48.32#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:48.32#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:48.34#ibcon#[25=AT02-07\r\n] 2006.134.08:09:48.37#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:48.37#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:48.37#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.08:09:48.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:48.37#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:48.49#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:48.49#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:48.51#ibcon#[25=USB\r\n] 2006.134.08:09:48.55#abcon#<5=/05 3.8 6.4 18.70 861007.0\r\n> 2006.134.08:09:48.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:48.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:48.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:09:48.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:09:48.55$vc4f8/valo=3,672.99 2006.134.08:09:48.56#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:09:48.56#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:09:48.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:48.56#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:09:48.56#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:09:48.56#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:09:48.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:09:48.57#abcon#{5=INTERFACE CLEAR} 2006.134.08:09:48.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:09:48.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:09:48.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:09:48.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:09:48.61$vc4f8/va=3,6 2006.134.08:09:48.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:09:48.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:09:48.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:48.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:09:48.63#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:09:48.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:09:48.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:09:48.69#ibcon#[25=AT03-06\r\n] 2006.134.08:09:48.72#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:09:48.72#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:09:48.72#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:09:48.72#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:48.72#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:09:48.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:09:48.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:09:48.86#ibcon#[25=USB\r\n] 2006.134.08:09:48.90#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:09:48.90#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:09:48.90#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:09:48.90#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:09:48.90$vc4f8/valo=4,832.99 2006.134.08:09:48.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.08:09:48.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.08:09:48.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:48.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:48.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:48.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:09:48.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:48.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:48.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:09:48.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:09:48.96$vc4f8/va=4,7 2006.134.08:09:48.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.08:09:48.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.08:09:48.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:48.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:49.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:49.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:49.04#ibcon#[25=AT04-07\r\n] 2006.134.08:09:49.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:49.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:49.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.08:09:49.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:49.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:49.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:49.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:49.21#ibcon#[25=USB\r\n] 2006.134.08:09:49.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:49.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:49.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:09:49.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:09:49.24$vc4f8/valo=5,652.99 2006.134.08:09:49.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.08:09:49.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.08:09:49.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:49.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:49.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:49.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:09:49.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:49.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:49.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:09:49.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:09:49.30$vc4f8/va=5,6 2006.134.08:09:49.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.08:09:49.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.08:09:49.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:49.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:49.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:49.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:49.38#ibcon#[25=AT05-06\r\n] 2006.134.08:09:49.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:49.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:49.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.08:09:49.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:49.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:49.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:49.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:49.55#ibcon#[25=USB\r\n] 2006.134.08:09:49.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:49.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:49.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:09:49.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:09:49.58$vc4f8/valo=6,772.99 2006.134.08:09:49.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.08:09:49.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.08:09:49.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:49.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:49.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:49.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:09:49.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:49.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:49.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:09:49.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:09:49.64$vc4f8/va=6,5 2006.134.08:09:49.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.08:09:49.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.08:09:49.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:49.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:49.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:49.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:49.72#ibcon#[25=AT06-05\r\n] 2006.134.08:09:49.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:49.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:49.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.08:09:49.75#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:49.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:09:49.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:09:49.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:09:49.89#ibcon#[25=USB\r\n] 2006.134.08:09:49.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:09:49.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:09:49.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:09:49.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:09:49.92$vc4f8/valo=7,832.99 2006.134.08:09:49.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.08:09:49.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.08:09:49.92#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:49.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:09:49.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:09:49.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:09:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:09:49.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:09:49.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:09:49.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:09:49.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:09:49.98$vc4f8/va=7,5 2006.134.08:09:49.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.08:09:49.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.08:09:49.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:49.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:09:50.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:09:50.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:09:50.06#ibcon#[25=AT07-05\r\n] 2006.134.08:09:50.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:09:50.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:09:50.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.08:09:50.09#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:50.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:09:50.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:09:50.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:09:50.23#ibcon#[25=USB\r\n] 2006.134.08:09:50.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:09:50.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:09:50.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:09:50.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:09:50.26$vc4f8/valo=8,852.99 2006.134.08:09:50.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:09:50.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:09:50.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:50.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:09:50.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:09:50.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:09:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:09:50.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:09:50.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:09:50.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:09:50.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:09:50.32$vc4f8/va=8,6 2006.134.08:09:50.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:09:50.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:09:50.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:50.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:09:50.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:09:50.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:09:50.40#ibcon#[25=AT08-06\r\n] 2006.134.08:09:50.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:09:50.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:09:50.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:09:50.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:50.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:09:50.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:09:50.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:09:50.57#ibcon#[25=USB\r\n] 2006.134.08:09:50.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:09:50.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:09:50.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:09:50.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:09:50.60$vc4f8/vblo=1,632.99 2006.134.08:09:50.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:09:50.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:09:50.60#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:50.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:50.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:50.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:09:50.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:50.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:09:50.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:09:50.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:09:50.66$vc4f8/vb=1,4 2006.134.08:09:50.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:09:50.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:09:50.66#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:50.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:50.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:50.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:50.68#ibcon#[27=AT01-04\r\n] 2006.134.08:09:50.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:50.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:09:50.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:09:50.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:50.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:50.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:50.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:50.85#ibcon#[27=USB\r\n] 2006.134.08:09:50.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:50.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:09:50.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:09:50.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:09:50.88$vc4f8/vblo=2,640.99 2006.134.08:09:50.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:09:50.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:09:50.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:50.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:50.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:50.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:09:50.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:50.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:09:50.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:09:50.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:09:50.94$vc4f8/vb=2,4 2006.134.08:09:50.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.08:09:50.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.08:09:50.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:50.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:51.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:51.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:51.02#ibcon#[27=AT02-04\r\n] 2006.134.08:09:51.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:51.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:09:51.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.08:09:51.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:51.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:51.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:51.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:51.19#ibcon#[27=USB\r\n] 2006.134.08:09:51.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:51.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:09:51.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:09:51.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:09:51.22$vc4f8/vblo=3,656.99 2006.134.08:09:51.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.08:09:51.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.08:09:51.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:51.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:09:51.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:09:51.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:09:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:09:51.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:09:51.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:09:51.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:09:51.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:09:51.28$vc4f8/vb=3,4 2006.134.08:09:51.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.08:09:51.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.08:09:51.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:51.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:09:51.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:09:51.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:09:51.36#ibcon#[27=AT03-04\r\n] 2006.134.08:09:51.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:09:51.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:09:51.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.08:09:51.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:51.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:09:51.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:09:51.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:09:51.53#ibcon#[27=USB\r\n] 2006.134.08:09:51.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:09:51.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:09:51.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:09:51.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:09:51.56$vc4f8/vblo=4,712.99 2006.134.08:09:51.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.08:09:51.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.08:09:51.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:51.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:09:51.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:09:51.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:09:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:09:51.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:09:51.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:09:51.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:09:51.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:09:51.62$vc4f8/vb=4,4 2006.134.08:09:51.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.08:09:51.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.08:09:51.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:51.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:09:51.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:09:51.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:09:51.70#ibcon#[27=AT04-04\r\n] 2006.134.08:09:51.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:09:51.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:09:51.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.08:09:51.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:51.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:09:51.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:09:51.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:09:51.87#ibcon#[27=USB\r\n] 2006.134.08:09:51.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:09:51.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:09:51.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:09:51.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:09:51.90$vc4f8/vblo=5,744.99 2006.134.08:09:51.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.08:09:51.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.08:09:51.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:51.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:51.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:51.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:09:51.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:51.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:09:51.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:09:51.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:09:51.96$vc4f8/vb=5,4 2006.134.08:09:51.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.08:09:51.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.08:09:51.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:51.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:52.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:52.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:52.04#ibcon#[27=AT05-04\r\n] 2006.134.08:09:52.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:52.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:09:52.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.08:09:52.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:52.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:52.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:52.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:52.21#ibcon#[27=USB\r\n] 2006.134.08:09:52.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:52.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:09:52.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:09:52.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:09:52.24$vc4f8/vblo=6,752.99 2006.134.08:09:52.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.08:09:52.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.08:09:52.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:09:52.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:52.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:52.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:09:52.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:52.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:09:52.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:09:52.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:09:52.30$vc4f8/vb=6,4 2006.134.08:09:52.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.08:09:52.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.08:09:52.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:09:52.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:52.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:52.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:52.38#ibcon#[27=AT06-04\r\n] 2006.134.08:09:52.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:52.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:09:52.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.08:09:52.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:09:52.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:52.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:52.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:52.55#ibcon#[27=USB\r\n] 2006.134.08:09:52.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:52.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:09:52.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:09:52.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:09:52.58$vc4f8/vabw=wide 2006.134.08:09:52.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.08:09:52.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.08:09:52.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:09:52.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:52.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:52.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:52.60#ibcon#[25=BW32\r\n] 2006.134.08:09:52.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:52.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:09:52.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:09:52.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:09:52.63$vc4f8/vbbw=wide 2006.134.08:09:52.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.08:09:52.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.08:09:52.63#ibcon#ireg 8 cls_cnt 0 2006.134.08:09:52.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:09:52.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:09:52.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:09:52.72#ibcon#[27=BW32\r\n] 2006.134.08:09:52.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:09:52.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:09:52.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:09:52.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:09:52.75$4f8m12a/ifd4f 2006.134.08:09:52.75$ifd4f/lo= 2006.134.08:09:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:09:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:09:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:09:52.75$ifd4f/patch= 2006.134.08:09:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:09:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:09:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:09:52.75$4f8m12a/"form=m,16.000,1:2 2006.134.08:09:52.75$4f8m12a/"tpicd 2006.134.08:09:52.75$4f8m12a/echo=off 2006.134.08:09:52.75$4f8m12a/xlog=off 2006.134.08:09:52.75:!2006.134.08:10:20 2006.134.08:10:02.14#trakl#Source acquired 2006.134.08:10:02.14#flagr#flagr/antenna,acquired 2006.134.08:10:20.00:preob 2006.134.08:10:21.14/onsource/TRACKING 2006.134.08:10:21.14:!2006.134.08:10:30 2006.134.08:10:30.00:data_valid=on 2006.134.08:10:30.00:midob 2006.134.08:10:30.14/onsource/TRACKING 2006.134.08:10:30.14/wx/18.68,1007.0,85 2006.134.08:10:30.21/cable/+6.5468E-03 2006.134.08:10:31.30/va/01,08,usb,yes,31,32 2006.134.08:10:31.30/va/02,07,usb,yes,31,32 2006.134.08:10:31.30/va/03,06,usb,yes,32,33 2006.134.08:10:31.30/va/04,07,usb,yes,31,34 2006.134.08:10:31.30/va/05,06,usb,yes,33,35 2006.134.08:10:31.30/va/06,05,usb,yes,34,33 2006.134.08:10:31.30/va/07,05,usb,yes,34,33 2006.134.08:10:31.30/va/08,06,usb,yes,31,31 2006.134.08:10:31.53/valo/01,532.99,yes,locked 2006.134.08:10:31.53/valo/02,572.99,yes,locked 2006.134.08:10:31.53/valo/03,672.99,yes,locked 2006.134.08:10:31.53/valo/04,832.99,yes,locked 2006.134.08:10:31.53/valo/05,652.99,yes,locked 2006.134.08:10:31.53/valo/06,772.99,yes,locked 2006.134.08:10:31.53/valo/07,832.99,yes,locked 2006.134.08:10:31.53/valo/08,852.99,yes,locked 2006.134.08:10:32.62/vb/01,04,usb,yes,30,28 2006.134.08:10:32.62/vb/02,04,usb,yes,32,33 2006.134.08:10:32.62/vb/03,04,usb,yes,28,32 2006.134.08:10:32.62/vb/04,04,usb,yes,29,29 2006.134.08:10:32.62/vb/05,04,usb,yes,27,31 2006.134.08:10:32.62/vb/06,04,usb,yes,28,31 2006.134.08:10:32.62/vb/07,04,usb,yes,30,30 2006.134.08:10:32.62/vb/08,04,usb,yes,28,31 2006.134.08:10:32.86/vblo/01,632.99,yes,locked 2006.134.08:10:32.86/vblo/02,640.99,yes,locked 2006.134.08:10:32.86/vblo/03,656.99,yes,locked 2006.134.08:10:32.86/vblo/04,712.99,yes,locked 2006.134.08:10:32.86/vblo/05,744.99,yes,locked 2006.134.08:10:32.86/vblo/06,752.99,yes,locked 2006.134.08:10:32.86/vblo/07,734.99,yes,locked 2006.134.08:10:32.86/vblo/08,744.99,yes,locked 2006.134.08:10:33.01/vabw/8 2006.134.08:10:33.16/vbbw/8 2006.134.08:10:33.27/xfe/off,on,14.7 2006.134.08:10:33.65/ifatt/23,28,28,28 2006.134.08:10:34.08/fmout-gps/S +1.76E-07 2006.134.08:10:34.12:!2006.134.08:11:30 2006.134.08:11:30.01:data_valid=off 2006.134.08:11:30.01:postob 2006.134.08:11:30.09/cable/+6.5446E-03 2006.134.08:11:30.09/wx/18.66,1007.0,86 2006.134.08:11:31.08/fmout-gps/S +1.77E-07 2006.134.08:11:31.08:scan_name=134-0812,k06134,60 2006.134.08:11:31.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.134.08:11:31.14#flagr#flagr/antenna,new-source 2006.134.08:11:32.14:checkk5 2006.134.08:11:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:11:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:11:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:11:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:11:33.99/chk_obsdata//k5ts1/T1340810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:11:34.36/chk_obsdata//k5ts2/T1340810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:11:34.72/chk_obsdata//k5ts3/T1340810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:11:35.09/chk_obsdata//k5ts4/T1340810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:11:35.78/k5log//k5ts1_log_newline 2006.134.08:11:36.47/k5log//k5ts2_log_newline 2006.134.08:11:37.15/k5log//k5ts3_log_newline 2006.134.08:11:37.84/k5log//k5ts4_log_newline 2006.134.08:11:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:11:37.87:4f8m12a=2 2006.134.08:11:37.87$4f8m12a/echo=on 2006.134.08:11:37.87$4f8m12a/pcalon 2006.134.08:11:37.87$pcalon/"no phase cal control is implemented here 2006.134.08:11:37.87$4f8m12a/"tpicd=stop 2006.134.08:11:37.87$4f8m12a/vc4f8 2006.134.08:11:37.87$vc4f8/valo=1,532.99 2006.134.08:11:37.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.08:11:37.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.08:11:37.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:37.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:37.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:37.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:11:37.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:37.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:37.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:11:37.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:11:37.96$vc4f8/va=1,8 2006.134.08:11:37.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.08:11:37.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.08:11:37.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:37.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:37.96#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:37.96#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:37.99#ibcon#[25=AT01-08\r\n] 2006.134.08:11:38.02#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:38.02#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:38.02#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.08:11:38.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:38.02#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:38.14#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:38.14#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:38.16#ibcon#[25=USB\r\n] 2006.134.08:11:38.19#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:38.19#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:38.19#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:11:38.19#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:11:38.19$vc4f8/valo=2,572.99 2006.134.08:11:38.19#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.08:11:38.19#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.08:11:38.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:38.19#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:38.19#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:38.19#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:11:38.26#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:38.26#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:38.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:11:38.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:11:38.26$vc4f8/va=2,7 2006.134.08:11:38.26#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.08:11:38.26#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.08:11:38.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:38.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:38.31#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:38.31#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:38.33#ibcon#[25=AT02-07\r\n] 2006.134.08:11:38.36#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:38.36#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:38.36#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.08:11:38.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:38.36#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:38.48#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:38.48#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:38.50#ibcon#[25=USB\r\n] 2006.134.08:11:38.53#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:38.53#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:38.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:11:38.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:11:38.53$vc4f8/valo=3,672.99 2006.134.08:11:38.53#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.08:11:38.53#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.08:11:38.53#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:38.53#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:38.53#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:38.53#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:11:38.60#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:38.60#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:38.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:11:38.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:11:38.60$vc4f8/va=3,6 2006.134.08:11:38.60#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.08:11:38.60#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.08:11:38.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:38.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:38.65#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:38.65#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:38.67#ibcon#[25=AT03-06\r\n] 2006.134.08:11:38.70#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:38.70#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:38.70#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.08:11:38.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:38.70#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:38.82#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:38.82#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:38.84#ibcon#[25=USB\r\n] 2006.134.08:11:38.87#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:38.87#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:38.87#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:11:38.87#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:11:38.87$vc4f8/valo=4,832.99 2006.134.08:11:38.87#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:11:38.87#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:11:38.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:38.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:38.87#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:38.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:38.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:11:38.93#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:38.93#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:38.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:11:38.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:11:38.93$vc4f8/va=4,7 2006.134.08:11:38.93#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.08:11:38.93#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.08:11:38.93#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:38.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:38.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:38.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:39.01#ibcon#[25=AT04-07\r\n] 2006.134.08:11:39.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:39.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:39.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.08:11:39.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:39.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:39.16#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:39.16#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:39.18#ibcon#[25=USB\r\n] 2006.134.08:11:39.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:39.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:39.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:11:39.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:11:39.21$vc4f8/valo=5,652.99 2006.134.08:11:39.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:11:39.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:11:39.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:39.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:39.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:39.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:39.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:11:39.27#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:39.27#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:39.27#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:11:39.27#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:11:39.27$vc4f8/va=5,6 2006.134.08:11:39.27#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.08:11:39.27#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.08:11:39.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:39.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:39.34#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:39.34#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:39.36#ibcon#[25=AT05-06\r\n] 2006.134.08:11:39.39#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:39.39#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:39.39#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.08:11:39.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:39.39#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:39.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:39.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:39.53#ibcon#[25=USB\r\n] 2006.134.08:11:39.56#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:39.56#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:39.56#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:11:39.56#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:11:39.56$vc4f8/valo=6,772.99 2006.134.08:11:39.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:11:39.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:11:39.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:39.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:39.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:39.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:11:39.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:39.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:39.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:11:39.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:11:39.62$vc4f8/va=6,5 2006.134.08:11:39.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.08:11:39.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.08:11:39.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:39.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:39.68#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:39.68#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:39.70#ibcon#[25=AT06-05\r\n] 2006.134.08:11:39.73#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:39.73#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:39.73#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.08:11:39.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:39.73#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:39.85#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:39.85#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:39.87#ibcon#[25=USB\r\n] 2006.134.08:11:39.90#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:39.90#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:39.90#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:11:39.90#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:11:39.90$vc4f8/valo=7,832.99 2006.134.08:11:39.90#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.08:11:39.90#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.08:11:39.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:39.90#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:39.90#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:39.90#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:11:39.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:39.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:39.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:11:39.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:11:39.96$vc4f8/va=7,5 2006.134.08:11:39.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.08:11:39.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.08:11:39.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:39.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:40.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:40.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:40.04#ibcon#[25=AT07-05\r\n] 2006.134.08:11:40.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:40.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:40.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.08:11:40.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:40.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:11:40.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:11:40.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:11:40.21#ibcon#[25=USB\r\n] 2006.134.08:11:40.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:11:40.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:11:40.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:11:40.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:11:40.24$vc4f8/valo=8,852.99 2006.134.08:11:40.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.08:11:40.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.08:11:40.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:40.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:11:40.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:11:40.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:11:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:11:40.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:11:40.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:11:40.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:11:40.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:11:40.30$vc4f8/va=8,6 2006.134.08:11:40.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:11:40.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:11:40.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:40.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:11:40.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:11:40.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:11:40.38#ibcon#[25=AT08-06\r\n] 2006.134.08:11:40.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:11:40.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:11:40.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:11:40.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:40.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:11:40.42#abcon#<5=/05 3.7 6.4 18.66 861007.0\r\n> 2006.134.08:11:40.44#abcon#{5=INTERFACE CLEAR} 2006.134.08:11:40.50#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:11:40.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:11:40.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:11:40.55#ibcon#[25=USB\r\n] 2006.134.08:11:40.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:11:40.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:11:40.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:11:40.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:11:40.58$vc4f8/vblo=1,632.99 2006.134.08:11:40.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.08:11:40.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.08:11:40.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:40.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:40.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:40.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:11:40.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:40.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:11:40.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:11:40.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:11:40.64$vc4f8/vb=1,4 2006.134.08:11:40.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.08:11:40.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.08:11:40.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:40.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:40.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:40.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:40.66#ibcon#[27=AT01-04\r\n] 2006.134.08:11:40.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:40.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:11:40.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.08:11:40.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:40.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:40.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:40.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:40.83#ibcon#[27=USB\r\n] 2006.134.08:11:40.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:40.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:11:40.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:11:40.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:11:40.86$vc4f8/vblo=2,640.99 2006.134.08:11:40.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.08:11:40.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.08:11:40.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:40.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:40.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:40.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:11:40.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:40.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:11:40.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:11:40.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:11:40.92$vc4f8/vb=2,4 2006.134.08:11:40.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.08:11:40.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.08:11:40.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:40.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:40.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:40.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:41.00#ibcon#[27=AT02-04\r\n] 2006.134.08:11:41.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:41.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:11:41.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.08:11:41.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:41.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:41.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:41.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:41.17#ibcon#[27=USB\r\n] 2006.134.08:11:41.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:41.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:11:41.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:11:41.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:11:41.20$vc4f8/vblo=3,656.99 2006.134.08:11:41.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.08:11:41.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.08:11:41.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:41.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:41.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:41.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:11:41.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:41.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:11:41.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:11:41.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:11:41.26$vc4f8/vb=3,4 2006.134.08:11:41.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.08:11:41.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.08:11:41.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:41.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:41.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:41.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:41.34#ibcon#[27=AT03-04\r\n] 2006.134.08:11:41.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:41.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:11:41.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.08:11:41.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:41.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:41.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:41.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:41.51#ibcon#[27=USB\r\n] 2006.134.08:11:41.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:41.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:11:41.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:11:41.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:11:41.54$vc4f8/vblo=4,712.99 2006.134.08:11:41.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:11:41.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:11:41.54#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:41.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:41.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:41.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:11:41.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:41.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:11:41.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:11:41.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:11:41.60$vc4f8/vb=4,4 2006.134.08:11:41.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.08:11:41.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.08:11:41.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:41.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:41.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:41.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:41.68#ibcon#[27=AT04-04\r\n] 2006.134.08:11:41.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:41.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:11:41.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.08:11:41.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:41.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:41.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:41.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:41.85#ibcon#[27=USB\r\n] 2006.134.08:11:41.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:41.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:11:41.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:11:41.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:11:41.88$vc4f8/vblo=5,744.99 2006.134.08:11:41.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:11:41.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:11:41.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:41.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:41.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:41.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:11:41.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:41.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:11:41.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:11:41.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:11:41.94$vc4f8/vb=5,4 2006.134.08:11:41.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.08:11:41.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.08:11:41.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:41.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:42.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:42.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:42.02#ibcon#[27=AT05-04\r\n] 2006.134.08:11:42.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:42.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:11:42.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.08:11:42.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:42.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:42.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:42.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:42.19#ibcon#[27=USB\r\n] 2006.134.08:11:42.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:42.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:11:42.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:11:42.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:11:42.22$vc4f8/vblo=6,752.99 2006.134.08:11:42.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:11:42.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:11:42.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:11:42.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:42.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:42.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:11:42.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:42.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:11:42.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:11:42.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:11:42.28$vc4f8/vb=6,4 2006.134.08:11:42.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.08:11:42.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.08:11:42.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:11:42.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:42.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:42.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:42.36#ibcon#[27=AT06-04\r\n] 2006.134.08:11:42.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:42.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:11:42.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.08:11:42.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:11:42.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:42.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:42.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:42.53#ibcon#[27=USB\r\n] 2006.134.08:11:42.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:42.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:11:42.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:11:42.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:11:42.56$vc4f8/vabw=wide 2006.134.08:11:42.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.08:11:42.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.08:11:42.56#ibcon#ireg 8 cls_cnt 0 2006.134.08:11:42.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:42.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:42.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:42.58#ibcon#[25=BW32\r\n] 2006.134.08:11:42.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:42.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:11:42.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:11:42.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:11:42.61$vc4f8/vbbw=wide 2006.134.08:11:42.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:11:42.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:11:42.61#ibcon#ireg 8 cls_cnt 0 2006.134.08:11:42.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:11:42.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:11:42.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:11:42.70#ibcon#[27=BW32\r\n] 2006.134.08:11:42.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:11:42.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:11:42.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:11:42.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:11:42.73$4f8m12a/ifd4f 2006.134.08:11:42.73$ifd4f/lo= 2006.134.08:11:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:11:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:11:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:11:42.73$ifd4f/patch= 2006.134.08:11:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:11:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:11:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:11:42.73$4f8m12a/"form=m,16.000,1:2 2006.134.08:11:42.73$4f8m12a/"tpicd 2006.134.08:11:42.73$4f8m12a/echo=off 2006.134.08:11:42.73$4f8m12a/xlog=off 2006.134.08:11:42.73:!2006.134.08:12:10 2006.134.08:11:48.14#trakl#Source acquired 2006.134.08:11:49.14#flagr#flagr/antenna,acquired 2006.134.08:12:10.00:preob 2006.134.08:12:11.14/onsource/TRACKING 2006.134.08:12:11.14:!2006.134.08:12:20 2006.134.08:12:20.00:data_valid=on 2006.134.08:12:20.00:midob 2006.134.08:12:20.14/onsource/TRACKING 2006.134.08:12:20.14/wx/18.65,1007.0,86 2006.134.08:12:20.33/cable/+6.5453E-03 2006.134.08:12:21.42/va/01,08,usb,yes,35,37 2006.134.08:12:21.42/va/02,07,usb,yes,35,37 2006.134.08:12:21.42/va/03,06,usb,yes,37,38 2006.134.08:12:21.42/va/04,07,usb,yes,36,39 2006.134.08:12:21.42/va/05,06,usb,yes,39,41 2006.134.08:12:21.42/va/06,05,usb,yes,39,39 2006.134.08:12:21.42/va/07,05,usb,yes,39,39 2006.134.08:12:21.42/va/08,06,usb,yes,37,36 2006.134.08:12:21.65/valo/01,532.99,yes,locked 2006.134.08:12:21.65/valo/02,572.99,yes,locked 2006.134.08:12:21.65/valo/03,672.99,yes,locked 2006.134.08:12:21.65/valo/04,832.99,yes,locked 2006.134.08:12:21.65/valo/05,652.99,yes,locked 2006.134.08:12:21.65/valo/06,772.99,yes,locked 2006.134.08:12:21.65/valo/07,832.99,yes,locked 2006.134.08:12:21.65/valo/08,852.99,yes,locked 2006.134.08:12:22.74/vb/01,04,usb,yes,32,31 2006.134.08:12:22.74/vb/02,04,usb,yes,34,36 2006.134.08:12:22.74/vb/03,04,usb,yes,31,34 2006.134.08:12:22.74/vb/04,04,usb,yes,32,32 2006.134.08:12:22.74/vb/05,04,usb,yes,30,34 2006.134.08:12:22.74/vb/06,04,usb,yes,31,34 2006.134.08:12:22.74/vb/07,04,usb,yes,33,33 2006.134.08:12:22.74/vb/08,04,usb,yes,31,34 2006.134.08:12:22.98/vblo/01,632.99,yes,locked 2006.134.08:12:22.98/vblo/02,640.99,yes,locked 2006.134.08:12:22.98/vblo/03,656.99,yes,locked 2006.134.08:12:22.98/vblo/04,712.99,yes,locked 2006.134.08:12:22.98/vblo/05,744.99,yes,locked 2006.134.08:12:22.98/vblo/06,752.99,yes,locked 2006.134.08:12:22.98/vblo/07,734.99,yes,locked 2006.134.08:12:22.98/vblo/08,744.99,yes,locked 2006.134.08:12:23.13/vabw/8 2006.134.08:12:23.28/vbbw/8 2006.134.08:12:23.41/xfe/off,on,14.7 2006.134.08:12:23.79/ifatt/23,28,28,28 2006.134.08:12:24.08/fmout-gps/S +1.77E-07 2006.134.08:12:24.12:!2006.134.08:13:20 2006.134.08:13:20.00:data_valid=off 2006.134.08:13:20.00:postob 2006.134.08:13:20.16/cable/+6.5449E-03 2006.134.08:13:20.16/wx/18.62,1007.0,87 2006.134.08:13:21.08/fmout-gps/S +1.76E-07 2006.134.08:13:21.08:scan_name=134-0814,k06134,60 2006.134.08:13:21.08:source=0059+581,010245.76,582411.1,2000.0,ccw 2006.134.08:13:21.14#flagr#flagr/antenna,new-source 2006.134.08:13:22.14:checkk5 2006.134.08:13:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:13:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:13:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:13:23.62/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:13:23.99/chk_obsdata//k5ts1/T1340812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:13:24.36/chk_obsdata//k5ts2/T1340812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:13:24.73/chk_obsdata//k5ts3/T1340812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:13:25.10/chk_obsdata//k5ts4/T1340812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:13:25.79/k5log//k5ts1_log_newline 2006.134.08:13:26.47/k5log//k5ts2_log_newline 2006.134.08:13:27.15/k5log//k5ts3_log_newline 2006.134.08:13:27.84/k5log//k5ts4_log_newline 2006.134.08:13:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:13:27.87:4f8m12a=2 2006.134.08:13:27.87$4f8m12a/echo=on 2006.134.08:13:27.87$4f8m12a/pcalon 2006.134.08:13:27.87$pcalon/"no phase cal control is implemented here 2006.134.08:13:27.87$4f8m12a/"tpicd=stop 2006.134.08:13:27.87$4f8m12a/vc4f8 2006.134.08:13:27.87$vc4f8/valo=1,532.99 2006.134.08:13:27.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:13:27.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:13:27.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:27.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:27.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:27.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:27.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:13:27.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:27.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:27.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:13:27.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:13:27.94$vc4f8/va=1,8 2006.134.08:13:27.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.08:13:27.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.08:13:27.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:27.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:27.94#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:27.94#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:27.96#ibcon#[25=AT01-08\r\n] 2006.134.08:13:27.99#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:27.99#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:27.99#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.08:13:27.99#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:27.99#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:28.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:28.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:28.13#ibcon#[25=USB\r\n] 2006.134.08:13:28.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:28.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:28.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:13:28.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:13:28.18$vc4f8/valo=2,572.99 2006.134.08:13:28.18#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.08:13:28.18#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.08:13:28.18#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:28.18#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:28.18#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:28.18#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:13:28.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:28.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:28.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:13:28.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:13:28.25$vc4f8/va=2,7 2006.134.08:13:28.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.08:13:28.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.08:13:28.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:28.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:28.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:28.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:28.31#ibcon#[25=AT02-07\r\n] 2006.134.08:13:28.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:28.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:28.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.08:13:28.34#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:28.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:28.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:28.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:28.48#ibcon#[25=USB\r\n] 2006.134.08:13:28.52#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:28.52#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:28.52#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:13:28.52#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:13:28.52$vc4f8/valo=3,672.99 2006.134.08:13:28.52#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.08:13:28.52#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.08:13:28.52#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:28.52#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:28.52#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:28.52#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:13:28.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:28.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:28.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:13:28.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:13:28.58$vc4f8/va=3,6 2006.134.08:13:28.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.08:13:28.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.08:13:28.58#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:28.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:28.64#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:28.64#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:28.66#ibcon#[25=AT03-06\r\n] 2006.134.08:13:28.69#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:28.69#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:28.69#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.08:13:28.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:28.69#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:28.81#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:28.81#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:28.83#ibcon#[25=USB\r\n] 2006.134.08:13:28.86#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:28.86#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:28.86#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:13:28.86#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:13:28.86$vc4f8/valo=4,832.99 2006.134.08:13:28.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.08:13:28.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.08:13:28.86#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:28.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:28.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:28.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:28.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:13:28.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:28.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:28.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:13:28.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:13:28.92$vc4f8/va=4,7 2006.134.08:13:28.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.08:13:28.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.08:13:28.92#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:28.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:28.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:28.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:29.00#ibcon#[25=AT04-07\r\n] 2006.134.08:13:29.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:29.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:29.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.08:13:29.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:29.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:29.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:29.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:29.17#ibcon#[25=USB\r\n] 2006.134.08:13:29.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:29.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:29.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:13:29.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:13:29.20$vc4f8/valo=5,652.99 2006.134.08:13:29.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.08:13:29.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.08:13:29.20#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:29.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:29.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:29.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:29.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:13:29.26#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:29.26#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:29.26#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:13:29.26#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:13:29.26$vc4f8/va=5,6 2006.134.08:13:29.26#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.08:13:29.26#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.08:13:29.26#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:29.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:29.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:29.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:29.34#ibcon#[25=AT05-06\r\n] 2006.134.08:13:29.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:29.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:29.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.08:13:29.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:29.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:29.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:29.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:29.51#ibcon#[25=USB\r\n] 2006.134.08:13:29.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:29.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:29.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:13:29.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:13:29.55$vc4f8/valo=6,772.99 2006.134.08:13:29.55#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:13:29.55#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:13:29.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:29.55#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:13:29.55#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:13:29.55#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:13:29.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:13:29.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:13:29.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:13:29.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:13:29.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:13:29.61$vc4f8/va=6,5 2006.134.08:13:29.61#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.08:13:29.61#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.08:13:29.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:29.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:13:29.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:13:29.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:13:29.69#ibcon#[25=AT06-05\r\n] 2006.134.08:13:29.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:13:29.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:13:29.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.08:13:29.72#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:29.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:13:29.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:13:29.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:13:29.86#ibcon#[25=USB\r\n] 2006.134.08:13:29.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:13:29.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:13:29.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:13:29.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:13:29.89$vc4f8/valo=7,832.99 2006.134.08:13:29.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.08:13:29.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.08:13:29.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:29.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:13:29.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:13:29.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:13:29.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:13:29.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:13:29.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:13:29.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:13:29.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:13:29.95$vc4f8/va=7,5 2006.134.08:13:29.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.08:13:29.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.08:13:29.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:29.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:13:30.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:13:30.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:13:30.03#ibcon#[25=AT07-05\r\n] 2006.134.08:13:30.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:13:30.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:13:30.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.08:13:30.06#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:30.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:13:30.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:13:30.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:13:30.20#ibcon#[25=USB\r\n] 2006.134.08:13:30.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:13:30.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:13:30.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:13:30.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:13:30.23$vc4f8/valo=8,852.99 2006.134.08:13:30.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.08:13:30.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.08:13:30.23#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:30.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:13:30.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:13:30.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:13:30.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:13:30.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:13:30.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:13:30.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:13:30.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:13:30.29$vc4f8/va=8,6 2006.134.08:13:30.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.08:13:30.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.08:13:30.29#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:30.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:13:30.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:13:30.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:13:30.37#ibcon#[25=AT08-06\r\n] 2006.134.08:13:30.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:13:30.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:13:30.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.08:13:30.40#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:30.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:13:30.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:13:30.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:13:30.54#ibcon#[25=USB\r\n] 2006.134.08:13:30.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:13:30.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:13:30.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:13:30.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:13:30.57$vc4f8/vblo=1,632.99 2006.134.08:13:30.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.08:13:30.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.08:13:30.57#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:30.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:13:30.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:13:30.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:13:30.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:13:30.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:13:30.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:13:30.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:13:30.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:13:30.63$vc4f8/vb=1,4 2006.134.08:13:30.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.08:13:30.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.08:13:30.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:30.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:13:30.63#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:13:30.63#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:13:30.65#ibcon#[27=AT01-04\r\n] 2006.134.08:13:30.68#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:13:30.68#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:13:30.68#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.08:13:30.68#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:30.68#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:13:30.80#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:13:30.80#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:13:30.82#ibcon#[27=USB\r\n] 2006.134.08:13:30.85#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:13:30.85#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:13:30.85#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:13:30.85#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:13:30.85$vc4f8/vblo=2,640.99 2006.134.08:13:30.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:13:30.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:13:30.85#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:30.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:30.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:30.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:30.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:13:30.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:30.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:13:30.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:13:30.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:13:30.91$vc4f8/vb=2,4 2006.134.08:13:30.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.08:13:30.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.08:13:30.91#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:30.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:30.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:30.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:30.99#ibcon#[27=AT02-04\r\n] 2006.134.08:13:31.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:31.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:13:31.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.08:13:31.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:31.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:31.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:31.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:31.16#ibcon#[27=USB\r\n] 2006.134.08:13:31.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:31.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:13:31.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:13:31.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:13:31.19$vc4f8/vblo=3,656.99 2006.134.08:13:31.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.08:13:31.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.08:13:31.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:31.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:31.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:31.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:31.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:13:31.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:31.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:13:31.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:13:31.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:13:31.25$vc4f8/vb=3,4 2006.134.08:13:31.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.08:13:31.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.08:13:31.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:31.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:31.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:31.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:31.33#ibcon#[27=AT03-04\r\n] 2006.134.08:13:31.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:31.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:13:31.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.08:13:31.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:31.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:31.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:31.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:31.50#ibcon#[27=USB\r\n] 2006.134.08:13:31.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:31.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:13:31.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:13:31.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:13:31.53$vc4f8/vblo=4,712.99 2006.134.08:13:31.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.08:13:31.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.08:13:31.53#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:31.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:31.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:31.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:31.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:13:31.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:31.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:13:31.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:13:31.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:13:31.59$vc4f8/vb=4,4 2006.134.08:13:31.59#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.08:13:31.59#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.08:13:31.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:31.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:31.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:31.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:31.67#ibcon#[27=AT04-04\r\n] 2006.134.08:13:31.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:31.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:13:31.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.08:13:31.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:31.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:31.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:31.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:31.84#ibcon#[27=USB\r\n] 2006.134.08:13:31.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:31.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:13:31.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:13:31.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:13:31.87$vc4f8/vblo=5,744.99 2006.134.08:13:31.87#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.08:13:31.87#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.08:13:31.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:31.87#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:31.87#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:31.87#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:31.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:13:31.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:31.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:13:31.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:13:31.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:13:31.93$vc4f8/vb=5,4 2006.134.08:13:31.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.08:13:31.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.08:13:31.93#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:31.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:31.99#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:31.99#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:32.01#ibcon#[27=AT05-04\r\n] 2006.134.08:13:32.04#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:32.04#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:13:32.04#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.08:13:32.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:32.04#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:32.16#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:32.16#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:32.18#ibcon#[27=USB\r\n] 2006.134.08:13:32.21#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:32.21#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:13:32.21#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:13:32.21#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:13:32.21$vc4f8/vblo=6,752.99 2006.134.08:13:32.21#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.08:13:32.21#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.08:13:32.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:13:32.21#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:32.21#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:32.21#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:32.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:13:32.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:32.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:13:32.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:13:32.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:13:32.27$vc4f8/vb=6,4 2006.134.08:13:32.27#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.08:13:32.27#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.08:13:32.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:13:32.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:32.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:32.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:32.35#ibcon#[27=AT06-04\r\n] 2006.134.08:13:32.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:32.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:13:32.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.08:13:32.38#ibcon#ireg 7 cls_cnt 0 2006.134.08:13:32.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:32.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:32.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:32.52#ibcon#[27=USB\r\n] 2006.134.08:13:32.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:32.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:13:32.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:13:32.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:13:32.55$vc4f8/vabw=wide 2006.134.08:13:32.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:13:32.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:13:32.55#ibcon#ireg 8 cls_cnt 0 2006.134.08:13:32.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:13:32.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:13:32.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:13:32.57#ibcon#[25=BW32\r\n] 2006.134.08:13:32.58#abcon#<5=/05 3.8 6.4 18.61 871007.0\r\n> 2006.134.08:13:32.60#abcon#{5=INTERFACE CLEAR} 2006.134.08:13:32.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:13:32.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:13:32.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:13:32.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:13:32.60$vc4f8/vbbw=wide 2006.134.08:13:32.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:13:32.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:13:32.60#ibcon#ireg 8 cls_cnt 0 2006.134.08:13:32.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:13:32.66#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:13:32.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:13:32.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:13:32.69#ibcon#[27=BW32\r\n] 2006.134.08:13:32.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:13:32.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:13:32.72#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:13:32.72#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:13:32.72$4f8m12a/ifd4f 2006.134.08:13:32.72$ifd4f/lo= 2006.134.08:13:32.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:13:32.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:13:32.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:13:32.72$ifd4f/patch= 2006.134.08:13:32.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:13:32.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:13:32.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:13:32.72$4f8m12a/"form=m,16.000,1:2 2006.134.08:13:32.72$4f8m12a/"tpicd 2006.134.08:13:32.72$4f8m12a/echo=off 2006.134.08:13:32.72$4f8m12a/xlog=off 2006.134.08:13:32.72:!2006.134.08:14:10 2006.134.08:13:51.13#trakl#Source acquired 2006.134.08:13:51.14#flagr#flagr/antenna,acquired 2006.134.08:14:10.02:preob 2006.134.08:14:11.14/onsource/TRACKING 2006.134.08:14:11.14:!2006.134.08:14:20 2006.134.08:14:20.02:data_valid=on 2006.134.08:14:20.02:midob 2006.134.08:14:21.13/onsource/TRACKING 2006.134.08:14:21.13/wx/18.60,1007.0,87 2006.134.08:14:21.37/cable/+6.5457E-03 2006.134.08:14:22.46/va/01,08,usb,yes,32,34 2006.134.08:14:22.46/va/02,07,usb,yes,32,34 2006.134.08:14:22.46/va/03,06,usb,yes,34,34 2006.134.08:14:22.46/va/04,07,usb,yes,33,35 2006.134.08:14:22.46/va/05,06,usb,yes,35,37 2006.134.08:14:22.46/va/06,05,usb,yes,36,35 2006.134.08:14:22.46/va/07,05,usb,yes,36,35 2006.134.08:14:22.46/va/08,06,usb,yes,33,32 2006.134.08:14:22.69/valo/01,532.99,yes,locked 2006.134.08:14:22.69/valo/02,572.99,yes,locked 2006.134.08:14:22.69/valo/03,672.99,yes,locked 2006.134.08:14:22.69/valo/04,832.99,yes,locked 2006.134.08:14:22.69/valo/05,652.99,yes,locked 2006.134.08:14:22.69/valo/06,772.99,yes,locked 2006.134.08:14:22.69/valo/07,832.99,yes,locked 2006.134.08:14:22.69/valo/08,852.99,yes,locked 2006.134.08:14:23.77/vb/01,04,usb,yes,30,29 2006.134.08:14:23.78/vb/02,04,usb,yes,32,34 2006.134.08:14:23.78/vb/03,04,usb,yes,28,32 2006.134.08:14:23.78/vb/04,04,usb,yes,29,30 2006.134.08:14:23.78/vb/05,04,usb,yes,28,32 2006.134.08:14:23.78/vb/06,04,usb,yes,29,32 2006.134.08:14:23.78/vb/07,04,usb,yes,31,31 2006.134.08:14:23.78/vb/08,04,usb,yes,29,32 2006.134.08:14:24.01/vblo/01,632.99,yes,locked 2006.134.08:14:24.01/vblo/02,640.99,yes,locked 2006.134.08:14:24.01/vblo/03,656.99,yes,locked 2006.134.08:14:24.01/vblo/04,712.99,yes,locked 2006.134.08:14:24.01/vblo/05,744.99,yes,locked 2006.134.08:14:24.01/vblo/06,752.99,yes,locked 2006.134.08:14:24.01/vblo/07,734.99,yes,locked 2006.134.08:14:24.01/vblo/08,744.99,yes,locked 2006.134.08:14:24.15/vabw/8 2006.134.08:14:24.30/vbbw/8 2006.134.08:14:24.40/xfe/off,on,15.2 2006.134.08:14:24.78/ifatt/23,28,28,28 2006.134.08:14:25.07/fmout-gps/S +1.78E-07 2006.134.08:14:25.12:!2006.134.08:15:20 2006.134.08:15:20.01:data_valid=off 2006.134.08:15:20.02:postob 2006.134.08:15:20.08/cable/+6.5495E-03 2006.134.08:15:20.09/wx/18.57,1007.0,87 2006.134.08:15:21.07/fmout-gps/S +1.78E-07 2006.134.08:15:21.08:scan_name=134-0816,k06134,60 2006.134.08:15:21.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.134.08:15:21.14#flagr#flagr/antenna,new-source 2006.134.08:15:22.14:checkk5 2006.134.08:15:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:15:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:15:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:15:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:15:23.99/chk_obsdata//k5ts1/T1340814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:15:24.36/chk_obsdata//k5ts2/T1340814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:15:24.73/chk_obsdata//k5ts3/T1340814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:15:25.10/chk_obsdata//k5ts4/T1340814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:15:25.79/k5log//k5ts1_log_newline 2006.134.08:15:26.49/k5log//k5ts2_log_newline 2006.134.08:15:27.18/k5log//k5ts3_log_newline 2006.134.08:15:27.87/k5log//k5ts4_log_newline 2006.134.08:15:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:15:27.90:4f8m12a=2 2006.134.08:15:27.90$4f8m12a/echo=on 2006.134.08:15:27.90$4f8m12a/pcalon 2006.134.08:15:27.90$pcalon/"no phase cal control is implemented here 2006.134.08:15:27.90$4f8m12a/"tpicd=stop 2006.134.08:15:27.90$4f8m12a/vc4f8 2006.134.08:15:27.90$vc4f8/valo=1,532.99 2006.134.08:15:27.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:15:27.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:15:27.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:27.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:27.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:27.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:15:27.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:27.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:27.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:15:27.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:15:27.98$vc4f8/va=1,8 2006.134.08:15:27.99#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:15:27.99#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:15:27.99#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:27.99#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:27.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:27.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:28.01#ibcon#[25=AT01-08\r\n] 2006.134.08:15:28.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:28.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:28.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:15:28.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:28.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:28.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:28.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:28.18#ibcon#[25=USB\r\n] 2006.134.08:15:28.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:28.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:28.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:15:28.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:15:28.22$vc4f8/valo=2,572.99 2006.134.08:15:28.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:15:28.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:15:28.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:28.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:28.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:28.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:15:28.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:28.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:28.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:15:28.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:15:28.27$vc4f8/va=2,7 2006.134.08:15:28.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.08:15:28.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.08:15:28.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:28.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:28.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:28.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:28.35#ibcon#[25=AT02-07\r\n] 2006.134.08:15:28.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:28.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:28.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.08:15:28.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:28.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:28.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:28.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:28.52#ibcon#[25=USB\r\n] 2006.134.08:15:28.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:28.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:28.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:15:28.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:15:28.55$vc4f8/valo=3,672.99 2006.134.08:15:28.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:15:28.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:15:28.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:28.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:28.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:28.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:15:28.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:28.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:28.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:15:28.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:15:28.62$vc4f8/va=3,6 2006.134.08:15:28.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:15:28.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:15:28.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:28.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:28.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:28.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:28.68#ibcon#[25=AT03-06\r\n] 2006.134.08:15:28.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:28.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:28.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:15:28.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:28.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:28.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:28.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:28.85#ibcon#[25=USB\r\n] 2006.134.08:15:28.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:28.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:28.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:15:28.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:15:28.88$vc4f8/valo=4,832.99 2006.134.08:15:28.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:15:28.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:15:28.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:28.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:28.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:28.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:15:28.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:28.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:28.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:15:28.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:15:28.94$vc4f8/va=4,7 2006.134.08:15:28.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:15:28.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:15:28.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:28.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:28.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:28.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:29.01#ibcon#[25=AT04-07\r\n] 2006.134.08:15:29.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:29.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:29.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:15:29.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:29.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:29.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:29.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:29.18#ibcon#[25=USB\r\n] 2006.134.08:15:29.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:29.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:29.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:15:29.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:15:29.21$vc4f8/valo=5,652.99 2006.134.08:15:29.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:15:29.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:15:29.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:29.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:29.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:29.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:29.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:15:29.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:29.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:29.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:15:29.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:15:29.27$vc4f8/va=5,6 2006.134.08:15:29.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:15:29.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:15:29.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:29.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:29.32#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:29.32#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:29.34#ibcon#[25=AT05-06\r\n] 2006.134.08:15:29.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:29.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:29.37#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:15:29.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:29.37#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:29.49#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:29.49#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:29.51#ibcon#[25=USB\r\n] 2006.134.08:15:29.54#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:29.54#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:29.54#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:15:29.54#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:15:29.54$vc4f8/valo=6,772.99 2006.134.08:15:29.55#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:15:29.55#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:15:29.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:29.55#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:29.55#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:29.55#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:29.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:15:29.60#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:29.60#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:29.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:15:29.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:15:29.60$vc4f8/va=6,5 2006.134.08:15:29.61#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:15:29.61#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:15:29.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:29.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:29.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:29.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:29.67#ibcon#[25=AT06-05\r\n] 2006.134.08:15:29.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:29.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:29.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:15:29.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:29.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:15:29.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:15:29.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:15:29.84#ibcon#[25=USB\r\n] 2006.134.08:15:29.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:15:29.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:15:29.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:15:29.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:15:29.87$vc4f8/valo=7,832.99 2006.134.08:15:29.88#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:15:29.88#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:15:29.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:29.88#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:15:29.88#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:15:29.88#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:15:29.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:15:29.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:15:29.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:15:29.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:15:29.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:15:29.93$vc4f8/va=7,5 2006.134.08:15:29.94#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:15:29.94#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:15:29.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:29.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:15:29.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:15:29.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:15:30.00#ibcon#[25=AT07-05\r\n] 2006.134.08:15:30.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:15:30.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:15:30.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:15:30.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:30.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:15:30.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:15:30.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:15:30.17#ibcon#[25=USB\r\n] 2006.134.08:15:30.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:15:30.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:15:30.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:15:30.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:15:30.20$vc4f8/valo=8,852.99 2006.134.08:15:30.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:15:30.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:15:30.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:30.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:15:30.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:15:30.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:15:30.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:15:30.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:15:30.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:15:30.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:15:30.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:15:30.26$vc4f8/va=8,6 2006.134.08:15:30.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:15:30.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:15:30.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:30.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:15:30.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:15:30.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:15:30.33#ibcon#[25=AT08-06\r\n] 2006.134.08:15:30.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:15:30.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:15:30.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:15:30.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:30.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:15:30.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:15:30.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:15:30.50#ibcon#[25=USB\r\n] 2006.134.08:15:30.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:15:30.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:15:30.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:15:30.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:15:30.53$vc4f8/vblo=1,632.99 2006.134.08:15:30.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:15:30.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:15:30.54#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:30.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:15:30.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:15:30.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:15:30.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:15:30.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:15:30.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:15:30.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:15:30.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:15:30.59$vc4f8/vb=1,4 2006.134.08:15:30.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:15:30.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:15:30.60#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:30.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:15:30.60#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:15:30.60#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:15:30.61#ibcon#[27=AT01-04\r\n] 2006.134.08:15:30.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:15:30.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:15:30.64#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:15:30.64#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:30.64#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:15:30.76#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:15:30.76#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:15:30.78#ibcon#[27=USB\r\n] 2006.134.08:15:30.81#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:15:30.81#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:15:30.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:15:30.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:15:30.81$vc4f8/vblo=2,640.99 2006.134.08:15:30.82#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:15:30.82#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:15:30.82#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:30.82#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:30.82#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:30.82#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:30.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:15:30.87#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:30.87#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:15:30.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:15:30.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:15:30.87$vc4f8/vb=2,4 2006.134.08:15:30.88#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:15:30.88#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:15:30.88#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:30.88#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:30.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:30.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:30.94#ibcon#[27=AT02-04\r\n] 2006.134.08:15:30.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:30.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:15:30.97#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:15:30.97#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:30.97#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:31.09#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:31.09#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:31.11#ibcon#[27=USB\r\n] 2006.134.08:15:31.14#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:31.14#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:15:31.14#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:15:31.14#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:15:31.14$vc4f8/vblo=3,656.99 2006.134.08:15:31.15#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:15:31.15#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:15:31.15#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:31.15#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:31.15#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:31.15#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:31.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:15:31.21#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:31.21#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:15:31.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:15:31.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:15:31.21$vc4f8/vb=3,4 2006.134.08:15:31.21#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.08:15:31.21#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.08:15:31.21#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:31.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:31.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:31.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:31.27#ibcon#[27=AT03-04\r\n] 2006.134.08:15:31.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:31.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:15:31.30#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.08:15:31.30#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:31.30#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:31.42#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:31.42#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:31.44#ibcon#[27=USB\r\n] 2006.134.08:15:31.47#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:31.47#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:15:31.47#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:15:31.47#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:15:31.47$vc4f8/vblo=4,712.99 2006.134.08:15:31.48#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:15:31.48#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:15:31.48#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:31.48#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:31.48#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:31.48#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:31.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:15:31.53#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:31.53#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:15:31.53#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:15:31.53#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:15:31.53$vc4f8/vb=4,4 2006.134.08:15:31.54#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:15:31.54#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:15:31.54#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:31.54#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:31.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:31.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:31.60#ibcon#[27=AT04-04\r\n] 2006.134.08:15:31.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:31.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:15:31.63#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:15:31.63#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:31.63#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:31.75#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:31.75#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:31.77#ibcon#[27=USB\r\n] 2006.134.08:15:31.80#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:31.80#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:15:31.80#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:15:31.80#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:15:31.80$vc4f8/vblo=5,744.99 2006.134.08:15:31.81#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:15:31.81#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:15:31.81#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:31.81#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:31.81#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:31.81#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:31.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:15:31.86#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:31.86#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:15:31.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:15:31.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:15:31.86$vc4f8/vb=5,4 2006.134.08:15:31.87#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:15:31.87#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:15:31.87#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:31.87#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:31.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:31.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:31.93#ibcon#[27=AT05-04\r\n] 2006.134.08:15:31.96#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:31.96#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:15:31.96#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:15:31.96#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:31.96#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:32.08#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:32.08#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:32.10#ibcon#[27=USB\r\n] 2006.134.08:15:32.13#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:32.13#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:15:32.13#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:15:32.13#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:15:32.13$vc4f8/vblo=6,752.99 2006.134.08:15:32.14#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:15:32.14#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:15:32.14#ibcon#ireg 17 cls_cnt 0 2006.134.08:15:32.14#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:32.14#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:32.14#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:32.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:15:32.20#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:32.20#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:15:32.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:15:32.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:15:32.20$vc4f8/vb=6,4 2006.134.08:15:32.20#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:15:32.20#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:15:32.20#ibcon#ireg 11 cls_cnt 2 2006.134.08:15:32.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:32.24#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:32.24#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:32.26#ibcon#[27=AT06-04\r\n] 2006.134.08:15:32.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:32.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:15:32.29#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:15:32.29#ibcon#ireg 7 cls_cnt 0 2006.134.08:15:32.29#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:32.41#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:32.41#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:32.43#ibcon#[27=USB\r\n] 2006.134.08:15:32.46#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:32.46#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:15:32.46#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:15:32.46#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:15:32.46$vc4f8/vabw=wide 2006.134.08:15:32.46#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:15:32.46#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:15:32.47#ibcon#ireg 8 cls_cnt 0 2006.134.08:15:32.47#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:32.47#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:32.47#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:32.48#ibcon#[25=BW32\r\n] 2006.134.08:15:32.51#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:32.51#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:15:32.51#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:15:32.51#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:15:32.51$vc4f8/vbbw=wide 2006.134.08:15:32.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:15:32.52#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:15:32.52#ibcon#ireg 8 cls_cnt 0 2006.134.08:15:32.52#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:15:32.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:15:32.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:15:32.59#ibcon#[27=BW32\r\n] 2006.134.08:15:32.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:15:32.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:15:32.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:15:32.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:15:32.62$4f8m12a/ifd4f 2006.134.08:15:32.63$ifd4f/lo= 2006.134.08:15:32.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:15:32.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:15:32.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:15:32.63$ifd4f/patch= 2006.134.08:15:32.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:15:32.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:15:32.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:15:32.63$4f8m12a/"form=m,16.000,1:2 2006.134.08:15:32.63$4f8m12a/"tpicd 2006.134.08:15:32.63$4f8m12a/echo=off 2006.134.08:15:32.63$4f8m12a/xlog=off 2006.134.08:15:32.63:!2006.134.08:16:00 2006.134.08:15:38.13#trakl#Source acquired 2006.134.08:15:39.14#flagr#flagr/antenna,acquired 2006.134.08:16:00.02:preob 2006.134.08:16:01.14/onsource/TRACKING 2006.134.08:16:01.14:!2006.134.08:16:10 2006.134.08:16:10.02:data_valid=on 2006.134.08:16:10.02:midob 2006.134.08:16:11.14/onsource/TRACKING 2006.134.08:16:11.14/wx/18.56,1007.0,88 2006.134.08:16:11.19/cable/+6.5434E-03 2006.134.08:16:12.28/va/01,08,usb,yes,33,35 2006.134.08:16:12.28/va/02,07,usb,yes,33,35 2006.134.08:16:12.28/va/03,06,usb,yes,35,35 2006.134.08:16:12.28/va/04,07,usb,yes,34,37 2006.134.08:16:12.28/va/05,06,usb,yes,37,39 2006.134.08:16:12.28/va/06,05,usb,yes,37,37 2006.134.08:16:12.28/va/07,05,usb,yes,37,37 2006.134.08:16:12.28/va/08,06,usb,yes,35,34 2006.134.08:16:12.51/valo/01,532.99,yes,locked 2006.134.08:16:12.51/valo/02,572.99,yes,locked 2006.134.08:16:12.51/valo/03,672.99,yes,locked 2006.134.08:16:12.51/valo/04,832.99,yes,locked 2006.134.08:16:12.51/valo/05,652.99,yes,locked 2006.134.08:16:12.51/valo/06,772.99,yes,locked 2006.134.08:16:12.51/valo/07,832.99,yes,locked 2006.134.08:16:12.51/valo/08,852.99,yes,locked 2006.134.08:16:13.60/vb/01,04,usb,yes,31,30 2006.134.08:16:13.60/vb/02,04,usb,yes,33,34 2006.134.08:16:13.60/vb/03,04,usb,yes,29,33 2006.134.08:16:13.60/vb/04,04,usb,yes,30,30 2006.134.08:16:13.60/vb/05,04,usb,yes,28,33 2006.134.08:16:13.60/vb/06,04,usb,yes,30,32 2006.134.08:16:13.60/vb/07,04,usb,yes,32,31 2006.134.08:16:13.60/vb/08,04,usb,yes,29,33 2006.134.08:16:13.83/vblo/01,632.99,yes,locked 2006.134.08:16:13.83/vblo/02,640.99,yes,locked 2006.134.08:16:13.83/vblo/03,656.99,yes,locked 2006.134.08:16:13.83/vblo/04,712.99,yes,locked 2006.134.08:16:13.83/vblo/05,744.99,yes,locked 2006.134.08:16:13.83/vblo/06,752.99,yes,locked 2006.134.08:16:13.83/vblo/07,734.99,yes,locked 2006.134.08:16:13.83/vblo/08,744.99,yes,locked 2006.134.08:16:13.98/vabw/8 2006.134.08:16:14.13/vbbw/8 2006.134.08:16:14.30/xfe/off,on,15.7 2006.134.08:16:14.67/ifatt/23,28,28,28 2006.134.08:16:15.07/fmout-gps/S +1.79E-07 2006.134.08:16:15.12:!2006.134.08:17:10 2006.134.08:17:10.01:data_valid=off 2006.134.08:17:10.02:postob 2006.134.08:17:10.21/cable/+6.5446E-03 2006.134.08:17:10.22/wx/18.54,1007.1,87 2006.134.08:17:11.07/fmout-gps/S +1.79E-07 2006.134.08:17:11.08:scan_name=134-0818,k06134,60 2006.134.08:17:11.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.134.08:17:12.14#flagr#flagr/antenna,new-source 2006.134.08:17:12.15:checkk5 2006.134.08:17:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:17:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:17:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:17:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:17:14.00/chk_obsdata//k5ts1/T1340816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:17:14.37/chk_obsdata//k5ts2/T1340816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:17:14.74/chk_obsdata//k5ts3/T1340816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:17:15.10/chk_obsdata//k5ts4/T1340816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:17:15.80/k5log//k5ts1_log_newline 2006.134.08:17:16.50/k5log//k5ts2_log_newline 2006.134.08:17:17.19/k5log//k5ts3_log_newline 2006.134.08:17:17.88/k5log//k5ts4_log_newline 2006.134.08:17:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:17:17.90:4f8m12a=2 2006.134.08:17:17.90$4f8m12a/echo=on 2006.134.08:17:17.90$4f8m12a/pcalon 2006.134.08:17:17.90$pcalon/"no phase cal control is implemented here 2006.134.08:17:17.90$4f8m12a/"tpicd=stop 2006.134.08:17:17.90$4f8m12a/vc4f8 2006.134.08:17:17.90$vc4f8/valo=1,532.99 2006.134.08:17:17.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.08:17:17.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.08:17:17.91#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:17.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:17.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:17.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:17:17.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:17.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:17.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:17:17.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:17:17.99$vc4f8/va=1,8 2006.134.08:17:17.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.08:17:17.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.08:17:17.99#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:17.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:17.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:17.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:18.03#ibcon#[25=AT01-08\r\n] 2006.134.08:17:18.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:18.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:18.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.08:17:18.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:18.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:18.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:18.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:18.19#ibcon#[25=USB\r\n] 2006.134.08:17:18.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:18.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:18.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:17:18.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:17:18.23$vc4f8/valo=2,572.99 2006.134.08:17:18.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:17:18.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:17:18.23#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:18.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:18.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:18.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:17:18.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:18.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:18.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:17:18.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:17:18.29$vc4f8/va=2,7 2006.134.08:17:18.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:17:18.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:17:18.29#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:18.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:18.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:18.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:18.36#ibcon#[25=AT02-07\r\n] 2006.134.08:17:18.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:18.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:18.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:17:18.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:18.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:18.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:18.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:18.53#ibcon#[25=USB\r\n] 2006.134.08:17:18.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:18.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:18.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:17:18.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:17:18.58$vc4f8/valo=3,672.99 2006.134.08:17:18.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:17:18.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:17:18.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:18.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:18.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:18.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:17:18.63#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:18.63#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:18.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:17:18.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:17:18.63$vc4f8/va=3,6 2006.134.08:17:18.63#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:17:18.63#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:17:18.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:18.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:18.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:18.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:18.72#ibcon#[25=AT03-06\r\n] 2006.134.08:17:18.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:18.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:18.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:17:18.75#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:18.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:18.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:18.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:18.89#ibcon#[25=USB\r\n] 2006.134.08:17:18.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:18.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:18.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:17:18.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:17:18.92$vc4f8/valo=4,832.99 2006.134.08:17:18.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:17:18.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:17:18.92#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:18.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:18.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:18.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:17:18.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:18.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:18.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:17:18.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:17:18.98$vc4f8/va=4,7 2006.134.08:17:18.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.08:17:18.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.08:17:18.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:18.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:19.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:19.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:19.06#ibcon#[25=AT04-07\r\n] 2006.134.08:17:19.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:19.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:19.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.08:17:19.09#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:19.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:19.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:19.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:19.23#ibcon#[25=USB\r\n] 2006.134.08:17:19.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:19.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:19.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:17:19.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:17:19.26$vc4f8/valo=5,652.99 2006.134.08:17:19.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.08:17:19.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.08:17:19.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:19.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:19.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:19.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:17:19.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:19.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:19.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:17:19.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:17:19.32$vc4f8/va=5,6 2006.134.08:17:19.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.08:17:19.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.08:17:19.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:19.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:19.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:19.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:19.40#ibcon#[25=AT05-06\r\n] 2006.134.08:17:19.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:19.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:19.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.08:17:19.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:19.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:19.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:19.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:19.57#ibcon#[25=USB\r\n] 2006.134.08:17:19.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:19.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:19.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:17:19.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:17:19.60$vc4f8/valo=6,772.99 2006.134.08:17:19.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.08:17:19.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.08:17:19.60#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:19.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:19.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:19.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:17:19.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:19.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:19.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:17:19.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:17:19.66$vc4f8/va=6,5 2006.134.08:17:19.66#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.134.08:17:19.66#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.134.08:17:19.66#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:19.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:19.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:19.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:19.74#ibcon#[25=AT06-05\r\n] 2006.134.08:17:19.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:19.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:19.77#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.134.08:17:19.77#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:19.77#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:17:19.89#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:17:19.89#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:17:19.91#ibcon#[25=USB\r\n] 2006.134.08:17:19.94#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:17:19.94#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.134.08:17:19.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:17:19.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:17:19.94$vc4f8/valo=7,832.99 2006.134.08:17:19.94#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.134.08:17:19.94#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.134.08:17:19.94#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:19.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:17:19.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:17:19.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:17:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:17:20.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:17:20.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.134.08:17:20.00#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:17:20.00#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:17:20.00$vc4f8/va=7,5 2006.134.08:17:20.00#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.134.08:17:20.00#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.134.08:17:20.00#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:20.00#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:17:20.06#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:17:20.06#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:17:20.08#ibcon#[25=AT07-05\r\n] 2006.134.08:17:20.11#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:17:20.11#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.134.08:17:20.11#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.134.08:17:20.11#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:20.11#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:17:20.23#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:17:20.23#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:17:20.25#ibcon#[25=USB\r\n] 2006.134.08:17:20.28#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:17:20.28#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.134.08:17:20.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:17:20.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:17:20.28$vc4f8/valo=8,852.99 2006.134.08:17:20.28#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.134.08:17:20.28#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.134.08:17:20.28#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:20.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:17:20.28#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:17:20.28#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:17:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:17:20.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:17:20.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.134.08:17:20.34#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:17:20.34#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:17:20.34$vc4f8/va=8,6 2006.134.08:17:20.34#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.134.08:17:20.34#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.134.08:17:20.34#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:20.34#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:17:20.40#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:17:20.40#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:17:20.42#ibcon#[25=AT08-06\r\n] 2006.134.08:17:20.45#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:17:20.45#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.134.08:17:20.45#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.134.08:17:20.45#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:20.45#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:17:20.57#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:17:20.57#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:17:20.59#ibcon#[25=USB\r\n] 2006.134.08:17:20.62#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:17:20.62#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.134.08:17:20.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:17:20.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:17:20.62$vc4f8/vblo=1,632.99 2006.134.08:17:20.62#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.134.08:17:20.62#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.134.08:17:20.62#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:20.62#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:17:20.62#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:17:20.62#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:17:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:17:20.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:17:20.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.134.08:17:20.68#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:17:20.68#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:17:20.68$vc4f8/vb=1,4 2006.134.08:17:20.68#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.134.08:17:20.68#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.134.08:17:20.68#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:20.68#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:17:20.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:17:20.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:17:20.70#ibcon#[27=AT01-04\r\n] 2006.134.08:17:20.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:17:20.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.134.08:17:20.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.134.08:17:20.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:20.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:17:20.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:17:20.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:17:20.87#ibcon#[27=USB\r\n] 2006.134.08:17:20.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:17:20.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.134.08:17:20.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:17:20.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:17:20.90$vc4f8/vblo=2,640.99 2006.134.08:17:20.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.134.08:17:20.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.134.08:17:20.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:20.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:20.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:20.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:17:20.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:20.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.134.08:17:20.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:17:20.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:17:20.96$vc4f8/vb=2,4 2006.134.08:17:20.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.134.08:17:20.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.134.08:17:20.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:20.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:21.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:21.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:21.04#ibcon#[27=AT02-04\r\n] 2006.134.08:17:21.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:21.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.134.08:17:21.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.134.08:17:21.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:21.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:21.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:21.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:21.21#ibcon#[27=USB\r\n] 2006.134.08:17:21.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:21.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.134.08:17:21.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:17:21.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:17:21.24$vc4f8/vblo=3,656.99 2006.134.08:17:21.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.134.08:17:21.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.134.08:17:21.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:21.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:21.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:21.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:17:21.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:21.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.134.08:17:21.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:17:21.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:17:21.30$vc4f8/vb=3,4 2006.134.08:17:21.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.134.08:17:21.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.134.08:17:21.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:21.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:21.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:21.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:21.38#ibcon#[27=AT03-04\r\n] 2006.134.08:17:21.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:21.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.134.08:17:21.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.134.08:17:21.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:21.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:21.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:21.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:21.55#ibcon#[27=USB\r\n] 2006.134.08:17:21.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:21.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.134.08:17:21.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:17:21.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:17:21.58$vc4f8/vblo=4,712.99 2006.134.08:17:21.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:17:21.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:17:21.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:21.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:21.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:21.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:17:21.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:21.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:17:21.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:17:21.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:17:21.64$vc4f8/vb=4,4 2006.134.08:17:21.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.134.08:17:21.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.134.08:17:21.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:21.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:21.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:21.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:21.72#ibcon#[27=AT04-04\r\n] 2006.134.08:17:21.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:21.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.134.08:17:21.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.134.08:17:21.75#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:21.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:21.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:21.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:21.89#ibcon#[27=USB\r\n] 2006.134.08:17:21.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:21.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.134.08:17:21.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:17:21.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:17:21.92$vc4f8/vblo=5,744.99 2006.134.08:17:21.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:17:21.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:17:21.92#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:21.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:21.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:21.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:17:21.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:21.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:17:21.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:17:21.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:17:21.98$vc4f8/vb=5,4 2006.134.08:17:21.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.134.08:17:21.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.134.08:17:21.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:21.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:22.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:22.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:22.06#ibcon#[27=AT05-04\r\n] 2006.134.08:17:22.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:22.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.134.08:17:22.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.134.08:17:22.09#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:22.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:22.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:22.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:22.23#ibcon#[27=USB\r\n] 2006.134.08:17:22.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:22.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.134.08:17:22.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:17:22.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:17:22.26$vc4f8/vblo=6,752.99 2006.134.08:17:22.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.134.08:17:22.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.134.08:17:22.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:17:22.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:22.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:22.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:17:22.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:22.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.134.08:17:22.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:17:22.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:17:22.32$vc4f8/vb=6,4 2006.134.08:17:22.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.134.08:17:22.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.134.08:17:22.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:17:22.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:22.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:22.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:22.40#ibcon#[27=AT06-04\r\n] 2006.134.08:17:22.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:22.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.134.08:17:22.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.134.08:17:22.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:17:22.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:22.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:22.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:22.57#ibcon#[27=USB\r\n] 2006.134.08:17:22.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:22.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.134.08:17:22.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:17:22.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:17:22.60$vc4f8/vabw=wide 2006.134.08:17:22.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.134.08:17:22.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.134.08:17:22.60#ibcon#ireg 8 cls_cnt 0 2006.134.08:17:22.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:22.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:22.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:22.62#ibcon#[25=BW32\r\n] 2006.134.08:17:22.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:22.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.134.08:17:22.66#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:17:22.66#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:17:22.66$vc4f8/vbbw=wide 2006.134.08:17:22.66#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:17:22.66#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:17:22.66#ibcon#ireg 8 cls_cnt 0 2006.134.08:17:22.66#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:17:22.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:17:22.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:17:22.73#ibcon#[27=BW32\r\n] 2006.134.08:17:22.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:17:22.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:17:22.76#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:17:22.76#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:17:22.76$4f8m12a/ifd4f 2006.134.08:17:22.76$ifd4f/lo= 2006.134.08:17:22.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:17:22.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:17:22.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:17:22.77$ifd4f/patch= 2006.134.08:17:22.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:17:22.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:17:22.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:17:22.77$4f8m12a/"form=m,16.000,1:2 2006.134.08:17:22.77$4f8m12a/"tpicd 2006.134.08:17:22.77$4f8m12a/echo=off 2006.134.08:17:22.77$4f8m12a/xlog=off 2006.134.08:17:22.77:!2006.134.08:18:00 2006.134.08:17:39.14#trakl#Source acquired 2006.134.08:17:41.14#flagr#flagr/antenna,acquired 2006.134.08:18:00.01:preob 2006.134.08:18:01.14/onsource/TRACKING 2006.134.08:18:01.14:!2006.134.08:18:10 2006.134.08:18:10.00:data_valid=on 2006.134.08:18:10.00:midob 2006.134.08:18:10.14/onsource/TRACKING 2006.134.08:18:10.14/wx/18.51,1007.1,88 2006.134.08:18:10.28/cable/+6.5453E-03 2006.134.08:18:11.37/va/01,08,usb,yes,29,31 2006.134.08:18:11.37/va/02,07,usb,yes,29,30 2006.134.08:18:11.37/va/03,06,usb,yes,31,31 2006.134.08:18:11.37/va/04,07,usb,yes,30,32 2006.134.08:18:11.37/va/05,06,usb,yes,32,34 2006.134.08:18:11.37/va/06,05,usb,yes,32,32 2006.134.08:18:11.37/va/07,05,usb,yes,32,32 2006.134.08:18:11.37/va/08,06,usb,yes,30,29 2006.134.08:18:11.60/valo/01,532.99,yes,locked 2006.134.08:18:11.60/valo/02,572.99,yes,locked 2006.134.08:18:11.60/valo/03,672.99,yes,locked 2006.134.08:18:11.60/valo/04,832.99,yes,locked 2006.134.08:18:11.60/valo/05,652.99,yes,locked 2006.134.08:18:11.60/valo/06,772.99,yes,locked 2006.134.08:18:11.60/valo/07,832.99,yes,locked 2006.134.08:18:11.60/valo/08,852.99,yes,locked 2006.134.08:18:12.69/vb/01,04,usb,yes,28,27 2006.134.08:18:12.69/vb/02,04,usb,yes,30,32 2006.134.08:18:12.69/vb/03,04,usb,yes,27,30 2006.134.08:18:12.69/vb/04,04,usb,yes,28,28 2006.134.08:18:12.69/vb/05,04,usb,yes,26,30 2006.134.08:18:12.69/vb/06,04,usb,yes,27,30 2006.134.08:18:12.69/vb/07,04,usb,yes,29,29 2006.134.08:18:12.69/vb/08,04,usb,yes,27,30 2006.134.08:18:12.92/vblo/01,632.99,yes,locked 2006.134.08:18:12.92/vblo/02,640.99,yes,locked 2006.134.08:18:12.92/vblo/03,656.99,yes,locked 2006.134.08:18:12.92/vblo/04,712.99,yes,locked 2006.134.08:18:12.92/vblo/05,744.99,yes,locked 2006.134.08:18:12.92/vblo/06,752.99,yes,locked 2006.134.08:18:12.92/vblo/07,734.99,yes,locked 2006.134.08:18:12.92/vblo/08,744.99,yes,locked 2006.134.08:18:13.07/vabw/8 2006.134.08:18:13.22/vbbw/8 2006.134.08:18:13.31/xfe/off,on,14.7 2006.134.08:18:13.69/ifatt/23,28,28,28 2006.134.08:18:14.07/fmout-gps/S +1.79E-07 2006.134.08:18:14.12:!2006.134.08:19:10 2006.134.08:19:10.00:data_valid=off 2006.134.08:19:10.01:postob 2006.134.08:19:10.16/cable/+6.5458E-03 2006.134.08:19:10.17/wx/18.49,1007.1,88 2006.134.08:19:11.07/fmout-gps/S +1.80E-07 2006.134.08:19:11.08:scan_name=134-0821,k06134,60 2006.134.08:19:11.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.134.08:19:12.13#flagr#flagr/antenna,new-source 2006.134.08:19:12.14:checkk5 2006.134.08:19:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:19:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:19:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:19:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:19:13.99/chk_obsdata//k5ts1/T1340818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:19:14.36/chk_obsdata//k5ts2/T1340818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:19:14.73/chk_obsdata//k5ts3/T1340818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:19:15.10/chk_obsdata//k5ts4/T1340818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:19:15.78/k5log//k5ts1_log_newline 2006.134.08:19:16.47/k5log//k5ts2_log_newline 2006.134.08:19:17.16/k5log//k5ts3_log_newline 2006.134.08:19:17.84/k5log//k5ts4_log_newline 2006.134.08:19:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:19:17.87:4f8m12a=3 2006.134.08:19:17.87$4f8m12a/echo=on 2006.134.08:19:17.87$4f8m12a/pcalon 2006.134.08:19:17.87$pcalon/"no phase cal control is implemented here 2006.134.08:19:17.87$4f8m12a/"tpicd=stop 2006.134.08:19:17.87$4f8m12a/vc4f8 2006.134.08:19:17.87$vc4f8/valo=1,532.99 2006.134.08:19:17.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.08:19:17.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.08:19:17.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:17.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:17.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:17.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:17.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:19:17.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:17.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:17.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:19:17.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:19:17.95$vc4f8/va=1,8 2006.134.08:19:17.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:19:17.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:19:17.95#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:17.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:17.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:17.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:17.97#ibcon#[25=AT01-08\r\n] 2006.134.08:19:18.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:18.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:18.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:19:18.00#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:18.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:18.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:18.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:18.14#ibcon#[25=USB\r\n] 2006.134.08:19:18.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:18.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:18.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:19:18.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:19:18.17$vc4f8/valo=2,572.99 2006.134.08:19:18.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.08:19:18.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.08:19:18.17#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:18.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:18.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:18.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:19:18.24#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:18.24#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:18.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:19:18.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:19:18.24$vc4f8/va=2,7 2006.134.08:19:18.24#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.08:19:18.24#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.08:19:18.24#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:18.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:18.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:18.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:18.31#ibcon#[25=AT02-07\r\n] 2006.134.08:19:18.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:18.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:18.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.08:19:18.34#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:18.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:18.47#abcon#<5=/04 3.5 6.1 18.49 881007.1\r\n> 2006.134.08:19:18.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:18.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:18.48#ibcon#[25=USB\r\n] 2006.134.08:19:18.48#abcon#{5=INTERFACE CLEAR} 2006.134.08:19:18.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:18.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:18.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:19:18.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:19:18.51$vc4f8/valo=3,672.99 2006.134.08:19:18.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.134.08:19:18.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.134.08:19:18.51#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:18.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:19:18.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:19:18.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:19:18.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:19:18.56#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:19:18.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:19:18.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.134.08:19:18.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:19:18.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:19:18.58$vc4f8/va=3,6 2006.134.08:19:18.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.08:19:18.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.08:19:18.58#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:18.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:18.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:18.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:18.65#ibcon#[25=AT03-06\r\n] 2006.134.08:19:18.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:18.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:18.68#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.08:19:18.68#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:18.68#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:18.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:18.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:18.82#ibcon#[25=USB\r\n] 2006.134.08:19:18.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:18.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:18.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:19:18.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:19:18.85$vc4f8/valo=4,832.99 2006.134.08:19:18.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.08:19:18.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.08:19:18.85#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:18.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:18.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:18.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:19:18.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:18.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:18.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:19:18.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:19:18.91$vc4f8/va=4,7 2006.134.08:19:18.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.08:19:18.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.08:19:18.91#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:18.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:18.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:18.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:18.99#ibcon#[25=AT04-07\r\n] 2006.134.08:19:19.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:19.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:19.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.08:19:19.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:19.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:19.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:19.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:19.16#ibcon#[25=USB\r\n] 2006.134.08:19:19.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:19.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:19.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:19:19.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:19:19.19$vc4f8/valo=5,652.99 2006.134.08:19:19.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:19:19.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:19:19.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:19.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:19.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:19.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:19.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:19:19.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:19.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:19.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:19:19.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:19:19.25$vc4f8/va=5,6 2006.134.08:19:19.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.08:19:19.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.08:19:19.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:19.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:19.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:19.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:19.33#ibcon#[25=AT05-06\r\n] 2006.134.08:19:19.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:19.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:19.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.08:19:19.37#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:19.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:19.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:19.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:19.50#ibcon#[25=USB\r\n] 2006.134.08:19:19.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:19.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:19.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:19:19.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:19:19.53$vc4f8/valo=6,772.99 2006.134.08:19:19.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:19:19.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:19:19.53#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:19.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:19.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:19.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:19:19.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:19.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:19.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:19:19.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:19:19.59$vc4f8/va=6,5 2006.134.08:19:19.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.134.08:19:19.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.134.08:19:19.59#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:19.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:19.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:19.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:19.67#ibcon#[25=AT06-05\r\n] 2006.134.08:19:19.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:19.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:19.70#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.134.08:19:19.70#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:19.70#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:19:19.82#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:19:19.82#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:19:19.84#ibcon#[25=USB\r\n] 2006.134.08:19:19.87#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:19:19.87#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.134.08:19:19.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:19:19.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:19:19.87$vc4f8/valo=7,832.99 2006.134.08:19:19.87#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.134.08:19:19.87#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.134.08:19:19.87#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:19.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:19:19.87#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:19:19.87#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:19:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:19:19.93#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:19:19.93#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.134.08:19:19.93#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:19:19.93#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:19:19.93$vc4f8/va=7,5 2006.134.08:19:19.93#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.134.08:19:19.93#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.134.08:19:19.93#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:19.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:19:19.99#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:19:19.99#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:19:20.01#ibcon#[25=AT07-05\r\n] 2006.134.08:19:20.04#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:19:20.04#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.134.08:19:20.04#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.134.08:19:20.04#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:20.04#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:19:20.16#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:19:20.16#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:19:20.18#ibcon#[25=USB\r\n] 2006.134.08:19:20.21#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:19:20.21#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.134.08:19:20.21#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:19:20.21#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:19:20.21$vc4f8/valo=8,852.99 2006.134.08:19:20.21#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.134.08:19:20.21#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.134.08:19:20.21#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:20.21#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:19:20.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:19:20.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:19:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:19:20.27#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:19:20.27#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.134.08:19:20.27#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:19:20.27#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:19:20.27$vc4f8/va=8,6 2006.134.08:19:20.27#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.134.08:19:20.27#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.134.08:19:20.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:20.27#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:19:20.33#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:19:20.33#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:19:20.35#ibcon#[25=AT08-06\r\n] 2006.134.08:19:20.38#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:19:20.38#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.134.08:19:20.38#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.134.08:19:20.38#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:20.38#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:19:20.50#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:19:20.50#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:19:20.52#ibcon#[25=USB\r\n] 2006.134.08:19:20.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:19:20.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.134.08:19:20.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:19:20.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:19:20.55$vc4f8/vblo=1,632.99 2006.134.08:19:20.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.134.08:19:20.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.134.08:19:20.55#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:20.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:20.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:20.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:19:20.61#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:20.61#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.134.08:19:20.61#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:19:20.61#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:19:20.61$vc4f8/vb=1,4 2006.134.08:19:20.61#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:19:20.61#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:19:20.61#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:20.61#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:20.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:20.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:20.63#ibcon#[27=AT01-04\r\n] 2006.134.08:19:20.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:20.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:19:20.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:19:20.66#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:20.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:20.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:20.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:20.80#ibcon#[27=USB\r\n] 2006.134.08:19:20.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:20.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:19:20.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:19:20.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:19:20.83$vc4f8/vblo=2,640.99 2006.134.08:19:20.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.134.08:19:20.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.134.08:19:20.83#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:20.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:20.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:20.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:19:20.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:20.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.134.08:19:20.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:19:20.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:19:20.89$vc4f8/vb=2,4 2006.134.08:19:20.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.134.08:19:20.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.134.08:19:20.89#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:20.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:20.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:20.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:20.97#ibcon#[27=AT02-04\r\n] 2006.134.08:19:21.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:21.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.134.08:19:21.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.134.08:19:21.00#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:21.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:21.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:21.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:21.14#ibcon#[27=USB\r\n] 2006.134.08:19:21.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:21.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.134.08:19:21.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:19:21.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:19:21.17$vc4f8/vblo=3,656.99 2006.134.08:19:21.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.134.08:19:21.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.134.08:19:21.17#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:21.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:19:21.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:19:21.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:19:21.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:19:21.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:19:21.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.134.08:19:21.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:19:21.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:19:21.23$vc4f8/vb=3,4 2006.134.08:19:21.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.134.08:19:21.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.134.08:19:21.23#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:21.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:19:21.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:19:21.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:19:21.31#ibcon#[27=AT03-04\r\n] 2006.134.08:19:21.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:19:21.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.134.08:19:21.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.134.08:19:21.34#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:21.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:19:21.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:19:21.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:19:21.48#ibcon#[27=USB\r\n] 2006.134.08:19:21.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:19:21.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.134.08:19:21.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:19:21.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:19:21.51$vc4f8/vblo=4,712.99 2006.134.08:19:21.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.08:19:21.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.08:19:21.51#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:21.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:19:21.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:19:21.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:19:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:19:21.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:19:21.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:19:21.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:19:21.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:19:21.57$vc4f8/vb=4,4 2006.134.08:19:21.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.134.08:19:21.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.134.08:19:21.57#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:21.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:21.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:21.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:21.65#ibcon#[27=AT04-04\r\n] 2006.134.08:19:21.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:21.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.134.08:19:21.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.134.08:19:21.69#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:21.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:21.80#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:21.80#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:21.82#ibcon#[27=USB\r\n] 2006.134.08:19:21.85#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:21.85#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.134.08:19:21.85#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:19:21.85#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:19:21.85$vc4f8/vblo=5,744.99 2006.134.08:19:21.85#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.134.08:19:21.85#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.134.08:19:21.85#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:21.85#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:21.85#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:21.85#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:19:21.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:21.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.134.08:19:21.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:19:21.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:19:21.91$vc4f8/vb=5,4 2006.134.08:19:21.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.134.08:19:21.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.134.08:19:21.91#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:21.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:21.97#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:21.97#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:21.99#ibcon#[27=AT05-04\r\n] 2006.134.08:19:22.02#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:22.02#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.134.08:19:22.02#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.134.08:19:22.02#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:22.02#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:22.14#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:22.14#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:22.16#ibcon#[27=USB\r\n] 2006.134.08:19:22.19#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:22.19#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.134.08:19:22.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:19:22.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:19:22.19$vc4f8/vblo=6,752.99 2006.134.08:19:22.19#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.134.08:19:22.19#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.134.08:19:22.19#ibcon#ireg 17 cls_cnt 0 2006.134.08:19:22.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:22.19#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:22.19#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:22.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:19:22.25#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:22.25#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.134.08:19:22.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:19:22.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:19:22.25$vc4f8/vb=6,4 2006.134.08:19:22.25#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.134.08:19:22.25#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.134.08:19:22.25#ibcon#ireg 11 cls_cnt 2 2006.134.08:19:22.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:22.31#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:22.31#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:22.33#ibcon#[27=AT06-04\r\n] 2006.134.08:19:22.36#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:22.36#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.134.08:19:22.36#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.134.08:19:22.36#ibcon#ireg 7 cls_cnt 0 2006.134.08:19:22.36#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:22.48#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:22.48#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:22.50#ibcon#[27=USB\r\n] 2006.134.08:19:22.53#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:22.53#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.134.08:19:22.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:19:22.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:19:22.53$vc4f8/vabw=wide 2006.134.08:19:22.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.134.08:19:22.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.134.08:19:22.53#ibcon#ireg 8 cls_cnt 0 2006.134.08:19:22.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:22.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:22.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:22.55#ibcon#[25=BW32\r\n] 2006.134.08:19:22.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:22.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.134.08:19:22.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:19:22.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:19:22.58$vc4f8/vbbw=wide 2006.134.08:19:22.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:19:22.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:19:22.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:19:22.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:19:22.65#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:19:22.65#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:19:22.67#ibcon#[27=BW32\r\n] 2006.134.08:19:22.70#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:19:22.70#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:19:22.70#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:19:22.70#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:19:22.70$4f8m12a/ifd4f 2006.134.08:19:22.70$ifd4f/lo= 2006.134.08:19:22.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:19:22.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:19:22.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:19:22.70$ifd4f/patch= 2006.134.08:19:22.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:19:22.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:19:22.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:19:22.71$4f8m12a/"form=m,16.000,1:2 2006.134.08:19:22.71$4f8m12a/"tpicd 2006.134.08:19:22.71$4f8m12a/echo=off 2006.134.08:19:22.71$4f8m12a/xlog=off 2006.134.08:19:22.71:!2006.134.08:21:00 2006.134.08:19:57.14#trakl#Source acquired 2006.134.08:19:58.14#flagr#flagr/antenna,acquired 2006.134.08:21:00.01:preob 2006.134.08:21:01.14/onsource/TRACKING 2006.134.08:21:01.14:!2006.134.08:21:10 2006.134.08:21:10.00:data_valid=on 2006.134.08:21:10.00:midob 2006.134.08:21:10.14/onsource/TRACKING 2006.134.08:21:10.14/wx/18.45,1007.1,88 2006.134.08:21:10.22/cable/+6.5440E-03 2006.134.08:21:11.31/va/01,08,usb,yes,29,31 2006.134.08:21:11.31/va/02,07,usb,yes,29,31 2006.134.08:21:11.31/va/03,06,usb,yes,31,31 2006.134.08:21:11.31/va/04,07,usb,yes,30,32 2006.134.08:21:11.31/va/05,06,usb,yes,32,34 2006.134.08:21:11.31/va/06,05,usb,yes,32,32 2006.134.08:21:11.31/va/07,05,usb,yes,32,32 2006.134.08:21:11.31/va/08,06,usb,yes,30,29 2006.134.08:21:11.54/valo/01,532.99,yes,locked 2006.134.08:21:11.54/valo/02,572.99,yes,locked 2006.134.08:21:11.54/valo/03,672.99,yes,locked 2006.134.08:21:11.54/valo/04,832.99,yes,locked 2006.134.08:21:11.54/valo/05,652.99,yes,locked 2006.134.08:21:11.54/valo/06,772.99,yes,locked 2006.134.08:21:11.54/valo/07,832.99,yes,locked 2006.134.08:21:11.54/valo/08,852.99,yes,locked 2006.134.08:21:12.63/vb/01,04,usb,yes,29,28 2006.134.08:21:12.63/vb/02,04,usb,yes,31,32 2006.134.08:21:12.63/vb/03,04,usb,yes,27,31 2006.134.08:21:12.63/vb/04,04,usb,yes,28,28 2006.134.08:21:12.63/vb/05,04,usb,yes,27,30 2006.134.08:21:12.63/vb/06,04,usb,yes,28,30 2006.134.08:21:12.63/vb/07,04,usb,yes,29,29 2006.134.08:21:12.63/vb/08,04,usb,yes,27,30 2006.134.08:21:12.87/vblo/01,632.99,yes,locked 2006.134.08:21:12.87/vblo/02,640.99,yes,locked 2006.134.08:21:12.87/vblo/03,656.99,yes,locked 2006.134.08:21:12.87/vblo/04,712.99,yes,locked 2006.134.08:21:12.87/vblo/05,744.99,yes,locked 2006.134.08:21:12.87/vblo/06,752.99,yes,locked 2006.134.08:21:12.87/vblo/07,734.99,yes,locked 2006.134.08:21:12.87/vblo/08,744.99,yes,locked 2006.134.08:21:13.02/vabw/8 2006.134.08:21:13.17/vbbw/8 2006.134.08:21:13.26/xfe/off,on,15.2 2006.134.08:21:13.64/ifatt/23,28,28,28 2006.134.08:21:14.07/fmout-gps/S +1.79E-07 2006.134.08:21:14.15:!2006.134.08:22:10 2006.134.08:22:10.01:data_valid=off 2006.134.08:22:10.02:postob 2006.134.08:22:10.13/cable/+6.5468E-03 2006.134.08:22:10.14/wx/18.43,1007.1,87 2006.134.08:22:11.07/fmout-gps/S +1.79E-07 2006.134.08:22:11.08:scan_name=134-0824,k06134,60 2006.134.08:22:11.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.134.08:22:12.14#flagr#flagr/antenna,new-source 2006.134.08:22:12.15:checkk5 2006.134.08:22:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:22:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:22:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:22:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:22:14.00/chk_obsdata//k5ts1/T1340821??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:22:14.36/chk_obsdata//k5ts2/T1340821??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:22:14.73/chk_obsdata//k5ts3/T1340821??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:22:15.10/chk_obsdata//k5ts4/T1340821??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:22:15.78/k5log//k5ts1_log_newline 2006.134.08:22:16.48/k5log//k5ts2_log_newline 2006.134.08:22:17.17/k5log//k5ts3_log_newline 2006.134.08:22:17.85/k5log//k5ts4_log_newline 2006.134.08:22:17.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:22:17.88:4f8m12a=3 2006.134.08:22:17.88$4f8m12a/echo=on 2006.134.08:22:17.88$4f8m12a/pcalon 2006.134.08:22:17.88$pcalon/"no phase cal control is implemented here 2006.134.08:22:17.88$4f8m12a/"tpicd=stop 2006.134.08:22:17.88$4f8m12a/vc4f8 2006.134.08:22:17.88$vc4f8/valo=1,532.99 2006.134.08:22:17.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:22:17.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:22:17.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:17.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:17.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:17.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:22:17.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:17.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:17.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:22:17.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:22:17.97$vc4f8/va=1,8 2006.134.08:22:17.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.08:22:17.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.08:22:17.97#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:17.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:17.97#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:17.97#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:18.00#ibcon#[25=AT01-08\r\n] 2006.134.08:22:18.03#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:18.03#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:18.03#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.08:22:18.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:18.03#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:18.15#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:18.15#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:18.17#ibcon#[25=USB\r\n] 2006.134.08:22:18.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:18.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:18.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:22:18.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:22:18.22$vc4f8/valo=2,572.99 2006.134.08:22:18.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.08:22:18.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.08:22:18.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:18.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:18.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:18.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:22:18.27#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:18.27#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:18.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:22:18.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:22:18.27$vc4f8/va=2,7 2006.134.08:22:18.27#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.08:22:18.27#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.08:22:18.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:18.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:18.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:18.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:18.36#ibcon#[25=AT02-07\r\n] 2006.134.08:22:18.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:18.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:18.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.08:22:18.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:18.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:18.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:18.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:18.53#ibcon#[25=USB\r\n] 2006.134.08:22:18.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:18.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:18.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:22:18.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:22:18.56$vc4f8/valo=3,672.99 2006.134.08:22:18.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.08:22:18.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.08:22:18.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:18.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:18.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:18.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:22:18.63#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:18.63#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:18.63#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:22:18.63#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:22:18.63$vc4f8/va=3,6 2006.134.08:22:18.63#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.134.08:22:18.63#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.134.08:22:18.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:18.63#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:22:18.68#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:22:18.68#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:22:18.70#ibcon#[25=AT03-06\r\n] 2006.134.08:22:18.73#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:22:18.73#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.134.08:22:18.73#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.134.08:22:18.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:18.73#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:22:18.85#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:22:18.85#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:22:18.87#ibcon#[25=USB\r\n] 2006.134.08:22:18.90#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:22:18.90#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.134.08:22:18.90#ibcon#about to clear, iclass 24 cls_cnt 0 2006.134.08:22:18.90#ibcon#cleared, iclass 24 cls_cnt 0 2006.134.08:22:18.90$vc4f8/valo=4,832.99 2006.134.08:22:18.90#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.134.08:22:18.90#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.134.08:22:18.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:18.90#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:22:18.90#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:22:18.90#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:22:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:22:18.96#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:22:18.96#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.134.08:22:18.96#ibcon#about to clear, iclass 26 cls_cnt 0 2006.134.08:22:18.96#ibcon#cleared, iclass 26 cls_cnt 0 2006.134.08:22:18.96$vc4f8/va=4,7 2006.134.08:22:18.96#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.134.08:22:18.96#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.134.08:22:18.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:18.96#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:22:19.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:22:19.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:22:19.04#ibcon#[25=AT04-07\r\n] 2006.134.08:22:19.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:22:19.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.134.08:22:19.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.134.08:22:19.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:19.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:22:19.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:22:19.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:22:19.21#ibcon#[25=USB\r\n] 2006.134.08:22:19.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:22:19.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.134.08:22:19.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.134.08:22:19.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.134.08:22:19.24$vc4f8/valo=5,652.99 2006.134.08:22:19.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:22:19.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:22:19.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:19.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:19.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:19.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:22:19.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:19.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:19.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:22:19.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:22:19.30$vc4f8/va=5,6 2006.134.08:22:19.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.08:22:19.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.08:22:19.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:19.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:19.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:19.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:19.38#ibcon#[25=AT05-06\r\n] 2006.134.08:22:19.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:19.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:19.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.08:22:19.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:19.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:19.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:19.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:19.55#ibcon#[25=USB\r\n] 2006.134.08:22:19.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:19.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:19.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:22:19.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:22:19.58$vc4f8/valo=6,772.99 2006.134.08:22:19.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.08:22:19.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.08:22:19.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:19.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:19.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:19.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:22:19.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:19.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:19.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:22:19.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:22:19.64$vc4f8/va=6,5 2006.134.08:22:19.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.08:22:19.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.08:22:19.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:19.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:19.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:19.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:19.72#ibcon#[25=AT06-05\r\n] 2006.134.08:22:19.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:19.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:19.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.08:22:19.75#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:19.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:19.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:19.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:19.89#ibcon#[25=USB\r\n] 2006.134.08:22:19.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:19.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:19.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:22:19.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:22:19.92$vc4f8/valo=7,832.99 2006.134.08:22:19.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.08:22:19.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.08:22:19.92#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:19.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:19.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:19.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:22:19.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:19.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:19.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:22:19.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:22:19.98$vc4f8/va=7,5 2006.134.08:22:19.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.134.08:22:19.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.134.08:22:19.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:19.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:20.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:20.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:20.06#ibcon#[25=AT07-05\r\n] 2006.134.08:22:20.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:20.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:20.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.134.08:22:20.09#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:20.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:22:20.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:22:20.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:22:20.23#ibcon#[25=USB\r\n] 2006.134.08:22:20.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:22:20.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.134.08:22:20.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:22:20.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:22:20.26$vc4f8/valo=8,852.99 2006.134.08:22:20.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.134.08:22:20.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.134.08:22:20.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:20.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:22:20.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:22:20.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:22:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:22:20.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:22:20.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.134.08:22:20.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.134.08:22:20.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.134.08:22:20.32$vc4f8/va=8,6 2006.134.08:22:20.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.134.08:22:20.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.134.08:22:20.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:20.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:22:20.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:22:20.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:22:20.40#ibcon#[25=AT08-06\r\n] 2006.134.08:22:20.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:22:20.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.134.08:22:20.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.134.08:22:20.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:20.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:22:20.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:22:20.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:22:20.57#ibcon#[25=USB\r\n] 2006.134.08:22:20.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:22:20.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.134.08:22:20.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.134.08:22:20.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.134.08:22:20.60$vc4f8/vblo=1,632.99 2006.134.08:22:20.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.134.08:22:20.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.134.08:22:20.60#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:20.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:22:20.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:22:20.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:22:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:22:20.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:22:20.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.134.08:22:20.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.134.08:22:20.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.134.08:22:20.66$vc4f8/vb=1,4 2006.134.08:22:20.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.134.08:22:20.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.134.08:22:20.66#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:20.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:22:20.66#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:22:20.66#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:22:20.68#ibcon#[27=AT01-04\r\n] 2006.134.08:22:20.71#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:22:20.71#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.134.08:22:20.71#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.134.08:22:20.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:20.71#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:22:20.83#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:22:20.83#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:22:20.85#ibcon#[27=USB\r\n] 2006.134.08:22:20.88#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:22:20.88#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.134.08:22:20.88#ibcon#about to clear, iclass 12 cls_cnt 0 2006.134.08:22:20.88#ibcon#cleared, iclass 12 cls_cnt 0 2006.134.08:22:20.88$vc4f8/vblo=2,640.99 2006.134.08:22:20.88#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.134.08:22:20.88#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.134.08:22:20.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:20.88#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:20.88#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:20.88#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:22:20.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:20.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.134.08:22:20.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.134.08:22:20.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.134.08:22:20.94$vc4f8/vb=2,4 2006.134.08:22:20.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.134.08:22:20.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.134.08:22:20.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:20.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:21.00#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:21.00#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:21.02#ibcon#[27=AT02-04\r\n] 2006.134.08:22:21.05#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:21.05#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.134.08:22:21.05#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.134.08:22:21.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:21.05#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:21.17#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:21.17#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:21.19#ibcon#[27=USB\r\n] 2006.134.08:22:21.22#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:21.22#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.134.08:22:21.22#ibcon#about to clear, iclass 16 cls_cnt 0 2006.134.08:22:21.22#ibcon#cleared, iclass 16 cls_cnt 0 2006.134.08:22:21.22$vc4f8/vblo=3,656.99 2006.134.08:22:21.22#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.134.08:22:21.22#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.134.08:22:21.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:21.22#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:21.22#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:21.22#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:22:21.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:21.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.134.08:22:21.28#ibcon#about to clear, iclass 18 cls_cnt 0 2006.134.08:22:21.28#ibcon#cleared, iclass 18 cls_cnt 0 2006.134.08:22:21.28$vc4f8/vb=3,4 2006.134.08:22:21.28#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.134.08:22:21.28#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.134.08:22:21.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:21.28#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:21.34#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:21.34#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:21.36#ibcon#[27=AT03-04\r\n] 2006.134.08:22:21.39#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:21.39#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.134.08:22:21.39#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.134.08:22:21.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:21.39#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:21.51#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:21.51#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:21.53#ibcon#[27=USB\r\n] 2006.134.08:22:21.56#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:21.56#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.134.08:22:21.56#ibcon#about to clear, iclass 20 cls_cnt 0 2006.134.08:22:21.56#ibcon#cleared, iclass 20 cls_cnt 0 2006.134.08:22:21.56$vc4f8/vblo=4,712.99 2006.134.08:22:21.56#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.134.08:22:21.56#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.134.08:22:21.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:21.56#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:21.56#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:21.56#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:22:21.62#abcon#<5=/05 3.6 6.1 18.42 871007.2\r\n> 2006.134.08:22:21.62#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:21.62#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.134.08:22:21.62#ibcon#about to clear, iclass 22 cls_cnt 0 2006.134.08:22:21.62#ibcon#cleared, iclass 22 cls_cnt 0 2006.134.08:22:21.62$vc4f8/vb=4,4 2006.134.08:22:21.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.134.08:22:21.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.134.08:22:21.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:21.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:22:21.64#abcon#{5=INTERFACE CLEAR} 2006.134.08:22:21.68#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:22:21.68#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:22:21.70#ibcon#[27=AT04-04\r\n] 2006.134.08:22:21.70#abcon#[5=S1D000X0/0*\r\n] 2006.134.08:22:21.74#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:22:21.74#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.134.08:22:21.74#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.134.08:22:21.74#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:21.74#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:22:21.85#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:22:21.85#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:22:21.87#ibcon#[27=USB\r\n] 2006.134.08:22:21.90#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:22:21.90#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.134.08:22:21.90#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:22:21.90#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:22:21.90$vc4f8/vblo=5,744.99 2006.134.08:22:21.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.134.08:22:21.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.134.08:22:21.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:21.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:21.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:21.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:22:21.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:21.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.134.08:22:21.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.134.08:22:21.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.134.08:22:21.96$vc4f8/vb=5,4 2006.134.08:22:21.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.134.08:22:21.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.134.08:22:21.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:21.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:22.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:22.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:22.04#ibcon#[27=AT05-04\r\n] 2006.134.08:22:22.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:22.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.134.08:22:22.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.134.08:22:22.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:22.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:22.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:22.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:22.21#ibcon#[27=USB\r\n] 2006.134.08:22:22.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:22.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.134.08:22:22.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.134.08:22:22.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.134.08:22:22.24$vc4f8/vblo=6,752.99 2006.134.08:22:22.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.134.08:22:22.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.134.08:22:22.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:22:22.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:22.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:22.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:22:22.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:22.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.134.08:22:22.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.134.08:22:22.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.134.08:22:22.30$vc4f8/vb=6,4 2006.134.08:22:22.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.134.08:22:22.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.134.08:22:22.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:22:22.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:22.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:22.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:22.38#ibcon#[27=AT06-04\r\n] 2006.134.08:22:22.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:22.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.134.08:22:22.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.134.08:22:22.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:22:22.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:22.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:22.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:22.55#ibcon#[27=USB\r\n] 2006.134.08:22:22.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:22.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.134.08:22:22.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.134.08:22:22.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.134.08:22:22.58$vc4f8/vabw=wide 2006.134.08:22:22.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.134.08:22:22.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.134.08:22:22.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:22:22.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:22.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:22.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:22.60#ibcon#[25=BW32\r\n] 2006.134.08:22:22.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:22.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.134.08:22:22.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.134.08:22:22.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.134.08:22:22.63$vc4f8/vbbw=wide 2006.134.08:22:22.63#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.134.08:22:22.63#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.134.08:22:22.63#ibcon#ireg 8 cls_cnt 0 2006.134.08:22:22.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:22:22.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:22:22.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:22:22.72#ibcon#[27=BW32\r\n] 2006.134.08:22:22.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:22:22.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.134.08:22:22.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.134.08:22:22.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.134.08:22:22.75$4f8m12a/ifd4f 2006.134.08:22:22.75$ifd4f/lo= 2006.134.08:22:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:22:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:22:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:22:22.75$ifd4f/patch= 2006.134.08:22:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:22:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:22:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:22:22.75$4f8m12a/"form=m,16.000,1:2 2006.134.08:22:22.75$4f8m12a/"tpicd 2006.134.08:22:22.75$4f8m12a/echo=off 2006.134.08:22:22.76$4f8m12a/xlog=off 2006.134.08:22:22.76:!2006.134.08:24:30 2006.134.08:23:05.13#trakl#Source acquired 2006.134.08:23:07.13#flagr#flagr/antenna,acquired 2006.134.08:24:30.01:preob 2006.134.08:24:31.13/onsource/TRACKING 2006.134.08:24:31.13:!2006.134.08:24:40 2006.134.08:24:40.00:data_valid=on 2006.134.08:24:40.00:midob 2006.134.08:24:40.13/onsource/TRACKING 2006.134.08:24:40.13/wx/18.37,1007.2,87 2006.134.08:24:40.25/cable/+6.5461E-03 2006.134.08:24:41.34/va/01,08,usb,yes,29,30 2006.134.08:24:41.34/va/02,07,usb,yes,29,30 2006.134.08:24:41.34/va/03,06,usb,yes,30,30 2006.134.08:24:41.34/va/04,07,usb,yes,29,32 2006.134.08:24:41.34/va/05,06,usb,yes,32,34 2006.134.08:24:41.34/va/06,05,usb,yes,32,32 2006.134.08:24:41.34/va/07,05,usb,yes,32,32 2006.134.08:24:41.34/va/08,06,usb,yes,30,29 2006.134.08:24:41.57/valo/01,532.99,yes,locked 2006.134.08:24:41.57/valo/02,572.99,yes,locked 2006.134.08:24:41.57/valo/03,672.99,yes,locked 2006.134.08:24:41.57/valo/04,832.99,yes,locked 2006.134.08:24:41.57/valo/05,652.99,yes,locked 2006.134.08:24:41.57/valo/06,772.99,yes,locked 2006.134.08:24:41.57/valo/07,832.99,yes,locked 2006.134.08:24:41.57/valo/08,852.99,yes,locked 2006.134.08:24:42.66/vb/01,04,usb,yes,28,27 2006.134.08:24:42.66/vb/02,04,usb,yes,30,32 2006.134.08:24:42.66/vb/03,04,usb,yes,27,30 2006.134.08:24:42.66/vb/04,04,usb,yes,28,28 2006.134.08:24:42.66/vb/05,04,usb,yes,26,30 2006.134.08:24:42.66/vb/06,04,usb,yes,27,30 2006.134.08:24:42.66/vb/07,04,usb,yes,29,29 2006.134.08:24:42.66/vb/08,04,usb,yes,27,30 2006.134.08:24:42.89/vblo/01,632.99,yes,locked 2006.134.08:24:42.89/vblo/02,640.99,yes,locked 2006.134.08:24:42.89/vblo/03,656.99,yes,locked 2006.134.08:24:42.89/vblo/04,712.99,yes,locked 2006.134.08:24:42.89/vblo/05,744.99,yes,locked 2006.134.08:24:42.89/vblo/06,752.99,yes,locked 2006.134.08:24:42.89/vblo/07,734.99,yes,locked 2006.134.08:24:42.89/vblo/08,744.99,yes,locked 2006.134.08:24:43.04/vabw/8 2006.134.08:24:43.19/vbbw/8 2006.134.08:24:43.28/xfe/off,on,14.7 2006.134.08:24:43.65/ifatt/23,28,28,28 2006.134.08:24:44.07/fmout-gps/S +1.82E-07 2006.134.08:24:44.11:!2006.134.08:25:40 2006.134.08:25:40.01:data_valid=off 2006.134.08:25:40.02:postob 2006.134.08:25:40.16/cable/+6.5449E-03 2006.134.08:25:40.17/wx/18.34,1007.2,87 2006.134.08:25:41.07/fmout-gps/S +1.82E-07 2006.134.08:25:41.08:scan_name=134-0826,k06134,60 2006.134.08:25:41.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.134.08:25:42.14#flagr#flagr/antenna,new-source 2006.134.08:25:42.15:checkk5 2006.134.08:25:42.52/chk_autoobs//k5ts1/ autoobs is running! 2006.134.08:25:42.90/chk_autoobs//k5ts2/ autoobs is running! 2006.134.08:25:43.27/chk_autoobs//k5ts3/ autoobs is running! 2006.134.08:25:43.65/chk_autoobs//k5ts4/ autoobs is running! 2006.134.08:25:44.03/chk_obsdata//k5ts1/T1340824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:25:44.39/chk_obsdata//k5ts2/T1340824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:25:44.75/chk_obsdata//k5ts3/T1340824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:25:45.12/chk_obsdata//k5ts4/T1340824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.134.08:25:45.80/k5log//k5ts1_log_newline 2006.134.08:25:46.49/k5log//k5ts2_log_newline 2006.134.08:25:47.17/k5log//k5ts3_log_newline 2006.134.08:25:47.86/k5log//k5ts4_log_newline 2006.134.08:25:47.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:25:47.88:4f8m12a=3 2006.134.08:25:47.88$4f8m12a/echo=on 2006.134.08:25:47.88$4f8m12a/pcalon 2006.134.08:25:47.88$pcalon/"no phase cal control is implemented here 2006.134.08:25:47.88$4f8m12a/"tpicd=stop 2006.134.08:25:47.88$4f8m12a/vc4f8 2006.134.08:25:47.88$vc4f8/valo=1,532.99 2006.134.08:25:47.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:25:47.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:25:47.89#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:47.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:47.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:47.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:47.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.134.08:25:47.97#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:47.97#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:47.97#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:25:47.97#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:25:47.97$vc4f8/va=1,8 2006.134.08:25:47.97#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:25:47.97#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:25:47.97#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:47.97#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:47.97#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:47.97#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:48.01#ibcon#[25=AT01-08\r\n] 2006.134.08:25:48.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:48.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:48.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:25:48.03#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:48.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:48.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:48.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:48.17#ibcon#[25=USB\r\n] 2006.134.08:25:48.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:48.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:48.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:25:48.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:25:48.22$vc4f8/valo=2,572.99 2006.134.08:25:48.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:25:48.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:25:48.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:48.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:48.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:48.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:48.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.134.08:25:48.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:48.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:48.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:25:48.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:25:48.27$vc4f8/va=2,7 2006.134.08:25:48.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:25:48.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:25:48.27#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:48.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:48.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:48.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:48.36#ibcon#[25=AT02-07\r\n] 2006.134.08:25:48.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:48.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:48.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:25:48.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:48.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:48.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:48.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:48.53#ibcon#[25=USB\r\n] 2006.134.08:25:48.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:48.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:48.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:25:48.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:25:48.56$vc4f8/valo=3,672.99 2006.134.08:25:48.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:25:48.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:25:48.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:48.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:48.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:48.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:48.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.134.08:25:48.63#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:48.63#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:48.63#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:25:48.63#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:25:48.63$vc4f8/va=3,6 2006.134.08:25:48.63#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:25:48.63#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:25:48.63#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:48.63#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:48.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:48.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:48.70#ibcon#[25=AT03-06\r\n] 2006.134.08:25:48.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:48.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:48.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:25:48.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:48.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:48.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:48.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:48.87#ibcon#[25=USB\r\n] 2006.134.08:25:48.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:48.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:48.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:25:48.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:25:48.90$vc4f8/valo=4,832.99 2006.134.08:25:48.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:25:48.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:25:48.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:48.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:48.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:48.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.134.08:25:48.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:48.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:48.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:25:48.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:25:48.96$vc4f8/va=4,7 2006.134.08:25:48.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:25:48.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:25:48.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:48.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:49.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:49.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:49.04#ibcon#[25=AT04-07\r\n] 2006.134.08:25:49.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:49.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:49.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:25:49.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:49.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:49.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:49.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:49.21#ibcon#[25=USB\r\n] 2006.134.08:25:49.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:49.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:49.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:25:49.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:25:49.24$vc4f8/valo=5,652.99 2006.134.08:25:49.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:25:49.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:25:49.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:49.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:49.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:49.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.134.08:25:49.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:49.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:49.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:25:49.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:25:49.30$vc4f8/va=5,6 2006.134.08:25:49.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:25:49.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:25:49.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:49.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:49.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:49.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:49.38#ibcon#[25=AT05-06\r\n] 2006.134.08:25:49.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:49.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:49.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:25:49.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:49.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:49.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:49.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:49.55#ibcon#[25=USB\r\n] 2006.134.08:25:49.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:49.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:49.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:25:49.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:25:49.58$vc4f8/valo=6,772.99 2006.134.08:25:49.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:25:49.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:25:49.58#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:49.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:49.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:49.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.134.08:25:49.64#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:49.64#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:49.64#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:25:49.64#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:25:49.64$vc4f8/va=6,5 2006.134.08:25:49.64#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.134.08:25:49.64#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.134.08:25:49.64#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:49.64#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:49.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:49.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:49.72#ibcon#[25=AT06-05\r\n] 2006.134.08:25:49.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:49.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:49.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.134.08:25:49.75#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:49.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:25:49.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:25:49.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:25:49.89#ibcon#[25=USB\r\n] 2006.134.08:25:49.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:25:49.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.134.08:25:49.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:25:49.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:25:49.92$vc4f8/valo=7,832.99 2006.134.08:25:49.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.134.08:25:49.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.134.08:25:49.92#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:49.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:25:49.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:25:49.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:25:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.134.08:25:49.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:25:49.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.134.08:25:49.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.134.08:25:49.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.134.08:25:49.98$vc4f8/va=7,5 2006.134.08:25:49.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.134.08:25:49.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.134.08:25:49.98#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:49.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:25:50.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:25:50.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:25:50.06#ibcon#[25=AT07-05\r\n] 2006.134.08:25:50.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:25:50.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.134.08:25:50.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.134.08:25:50.09#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:50.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:25:50.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:25:50.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:25:50.23#ibcon#[25=USB\r\n] 2006.134.08:25:50.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:25:50.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.134.08:25:50.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.134.08:25:50.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.134.08:25:50.26$vc4f8/valo=8,852.99 2006.134.08:25:50.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.134.08:25:50.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.134.08:25:50.26#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:50.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:25:50.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:25:50.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:25:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.134.08:25:50.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:25:50.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.134.08:25:50.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.134.08:25:50.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.134.08:25:50.32$vc4f8/va=8,6 2006.134.08:25:50.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.134.08:25:50.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.134.08:25:50.32#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:50.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:25:50.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:25:50.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:25:50.40#ibcon#[25=AT08-06\r\n] 2006.134.08:25:50.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:25:50.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.134.08:25:50.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.134.08:25:50.43#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:50.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:25:50.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:25:50.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:25:50.57#ibcon#[25=USB\r\n] 2006.134.08:25:50.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:25:50.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.134.08:25:50.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.134.08:25:50.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.134.08:25:50.60$vc4f8/vblo=1,632.99 2006.134.08:25:50.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.134.08:25:50.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.134.08:25:50.60#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:50.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:25:50.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:25:50.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:25:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.134.08:25:50.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:25:50.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.134.08:25:50.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.134.08:25:50.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.134.08:25:50.66$vc4f8/vb=1,4 2006.134.08:25:50.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.134.08:25:50.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.134.08:25:50.66#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:50.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:25:50.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:25:50.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:25:50.68#ibcon#[27=AT01-04\r\n] 2006.134.08:25:50.71#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:25:50.71#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.134.08:25:50.71#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.134.08:25:50.71#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:50.71#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:25:50.83#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:25:50.83#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:25:50.85#ibcon#[27=USB\r\n] 2006.134.08:25:50.88#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:25:50.88#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.134.08:25:50.88#ibcon#about to clear, iclass 13 cls_cnt 0 2006.134.08:25:50.88#ibcon#cleared, iclass 13 cls_cnt 0 2006.134.08:25:50.88$vc4f8/vblo=2,640.99 2006.134.08:25:50.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.134.08:25:50.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.134.08:25:50.88#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:50.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:50.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:50.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.134.08:25:50.94#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:50.94#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.134.08:25:50.94#ibcon#about to clear, iclass 15 cls_cnt 0 2006.134.08:25:50.94#ibcon#cleared, iclass 15 cls_cnt 0 2006.134.08:25:50.94$vc4f8/vb=2,4 2006.134.08:25:50.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.134.08:25:50.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.134.08:25:50.94#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:50.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:51.00#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:51.00#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:51.02#ibcon#[27=AT02-04\r\n] 2006.134.08:25:51.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:51.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.134.08:25:51.05#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.134.08:25:51.05#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:51.05#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:51.17#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:51.17#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:51.19#ibcon#[27=USB\r\n] 2006.134.08:25:51.22#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:51.22#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.134.08:25:51.22#ibcon#about to clear, iclass 17 cls_cnt 0 2006.134.08:25:51.22#ibcon#cleared, iclass 17 cls_cnt 0 2006.134.08:25:51.22$vc4f8/vblo=3,656.99 2006.134.08:25:51.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.134.08:25:51.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.134.08:25:51.22#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:51.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:51.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:51.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.134.08:25:51.28#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:51.28#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.134.08:25:51.28#ibcon#about to clear, iclass 19 cls_cnt 0 2006.134.08:25:51.28#ibcon#cleared, iclass 19 cls_cnt 0 2006.134.08:25:51.28$vc4f8/vb=3,4 2006.134.08:25:51.28#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.134.08:25:51.28#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.134.08:25:51.28#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:51.28#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:51.34#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:51.34#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:51.36#ibcon#[27=AT03-04\r\n] 2006.134.08:25:51.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:51.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.134.08:25:51.39#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.134.08:25:51.39#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:51.39#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:51.51#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:51.51#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:51.53#ibcon#[27=USB\r\n] 2006.134.08:25:51.56#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:51.56#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.134.08:25:51.56#ibcon#about to clear, iclass 21 cls_cnt 0 2006.134.08:25:51.56#ibcon#cleared, iclass 21 cls_cnt 0 2006.134.08:25:51.56$vc4f8/vblo=4,712.99 2006.134.08:25:51.56#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.134.08:25:51.56#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.134.08:25:51.56#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:51.56#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:51.56#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:51.56#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.134.08:25:51.62#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:51.62#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.134.08:25:51.62#ibcon#about to clear, iclass 23 cls_cnt 0 2006.134.08:25:51.62#ibcon#cleared, iclass 23 cls_cnt 0 2006.134.08:25:51.62$vc4f8/vb=4,4 2006.134.08:25:51.62#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.134.08:25:51.62#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.134.08:25:51.62#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:51.62#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:51.68#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:51.68#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:51.70#ibcon#[27=AT04-04\r\n] 2006.134.08:25:51.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:51.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.134.08:25:51.73#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.134.08:25:51.73#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:51.73#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:51.85#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:51.85#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:51.87#ibcon#[27=USB\r\n] 2006.134.08:25:51.90#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:51.90#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.134.08:25:51.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.134.08:25:51.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.134.08:25:51.90$vc4f8/vblo=5,744.99 2006.134.08:25:51.90#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.134.08:25:51.90#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.134.08:25:51.90#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:51.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:51.90#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:51.90#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.134.08:25:51.96#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:51.96#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.134.08:25:51.96#ibcon#about to clear, iclass 27 cls_cnt 0 2006.134.08:25:51.96#ibcon#cleared, iclass 27 cls_cnt 0 2006.134.08:25:51.96$vc4f8/vb=5,4 2006.134.08:25:51.96#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.134.08:25:51.96#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.134.08:25:51.96#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:51.96#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:52.02#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:52.02#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:52.04#ibcon#[27=AT05-04\r\n] 2006.134.08:25:52.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:52.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.134.08:25:52.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.134.08:25:52.07#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:52.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:52.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:52.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:52.21#ibcon#[27=USB\r\n] 2006.134.08:25:52.24#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:52.24#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.134.08:25:52.24#ibcon#about to clear, iclass 29 cls_cnt 0 2006.134.08:25:52.24#ibcon#cleared, iclass 29 cls_cnt 0 2006.134.08:25:52.24$vc4f8/vblo=6,752.99 2006.134.08:25:52.24#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.134.08:25:52.24#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.134.08:25:52.24#ibcon#ireg 17 cls_cnt 0 2006.134.08:25:52.24#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:52.24#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:52.24#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.134.08:25:52.30#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:52.30#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.134.08:25:52.30#ibcon#about to clear, iclass 31 cls_cnt 0 2006.134.08:25:52.30#ibcon#cleared, iclass 31 cls_cnt 0 2006.134.08:25:52.30$vc4f8/vb=6,4 2006.134.08:25:52.30#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.134.08:25:52.30#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.134.08:25:52.30#ibcon#ireg 11 cls_cnt 2 2006.134.08:25:52.30#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:52.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:52.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:52.38#ibcon#[27=AT06-04\r\n] 2006.134.08:25:52.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:52.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.134.08:25:52.41#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.134.08:25:52.41#ibcon#ireg 7 cls_cnt 0 2006.134.08:25:52.41#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:52.53#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:52.53#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:52.55#ibcon#[27=USB\r\n] 2006.134.08:25:52.58#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:52.58#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.134.08:25:52.58#ibcon#about to clear, iclass 33 cls_cnt 0 2006.134.08:25:52.58#ibcon#cleared, iclass 33 cls_cnt 0 2006.134.08:25:52.58$vc4f8/vabw=wide 2006.134.08:25:52.58#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.134.08:25:52.58#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.134.08:25:52.58#ibcon#ireg 8 cls_cnt 0 2006.134.08:25:52.58#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:52.58#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:52.58#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:52.60#ibcon#[25=BW32\r\n] 2006.134.08:25:52.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:52.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.134.08:25:52.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.134.08:25:52.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.134.08:25:52.63$vc4f8/vbbw=wide 2006.134.08:25:52.63#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.134.08:25:52.63#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.134.08:25:52.63#ibcon#ireg 8 cls_cnt 0 2006.134.08:25:52.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:25:52.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:25:52.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:25:52.72#ibcon#[27=BW32\r\n] 2006.134.08:25:52.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:25:52.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.134.08:25:52.75#ibcon#about to clear, iclass 37 cls_cnt 0 2006.134.08:25:52.75#ibcon#cleared, iclass 37 cls_cnt 0 2006.134.08:25:52.75$4f8m12a/ifd4f 2006.134.08:25:52.75$ifd4f/lo= 2006.134.08:25:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.134.08:25:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.134.08:25:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.134.08:25:52.75$ifd4f/patch= 2006.134.08:25:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.134.08:25:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.134.08:25:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.134.08:25:52.75$4f8m12a/"form=m,16.000,1:2 2006.134.08:25:52.75$4f8m12a/"tpicd 2006.134.08:25:52.75$4f8m12a/echo=off 2006.134.08:25:52.75$4f8m12a/xlog=off 2006.134.08:25:52.75:!2006.134.08:26:20 2006.134.08:26:06.14#trakl#Source acquired 2006.134.08:26:07.14#flagr#flagr/antenna,acquired 2006.134.08:26:20.00:preob 2006.134.08:26:20.14/onsource/TRACKING 2006.134.08:26:20.14:!2006.134.08:26:30 2006.134.08:26:30.00:data_valid=on 2006.134.08:26:30.00:midob 2006.134.08:26:31.14/onsource/TRACKING 2006.134.08:26:31.14/wx/18.33,1007.2,87 2006.134.08:26:31.36/cable/+6.5457E-03 2006.134.08:26:32.45/va/01,08,usb,yes,34,36 2006.134.08:26:32.45/va/02,07,usb,yes,34,36 2006.134.08:26:32.45/va/03,06,usb,yes,36,36 2006.134.08:26:32.45/va/04,07,usb,yes,35,37 2006.134.08:26:32.45/va/05,06,usb,yes,38,40 2006.134.08:26:32.45/va/06,05,usb,yes,38,38 2006.134.08:26:32.45/va/07,05,usb,yes,38,38 2006.134.08:26:32.45/va/08,06,usb,yes,36,35 2006.134.08:26:32.68/valo/01,532.99,yes,locked 2006.134.08:26:32.68/valo/02,572.99,yes,locked 2006.134.08:26:32.68/valo/03,672.99,yes,locked 2006.134.08:26:32.68/valo/04,832.99,yes,locked 2006.134.08:26:32.68/valo/05,652.99,yes,locked 2006.134.08:26:32.68/valo/06,772.99,yes,locked 2006.134.08:26:32.68/valo/07,832.99,yes,locked 2006.134.08:26:32.68/valo/08,852.99,yes,locked 2006.134.08:26:33.77/vb/01,04,usb,yes,31,32 2006.134.08:26:33.77/vb/02,04,usb,yes,33,36 2006.134.08:26:33.77/vb/03,04,usb,yes,30,34 2006.134.08:26:33.77/vb/04,04,usb,yes,31,31 2006.134.08:26:33.77/vb/05,04,usb,yes,29,33 2006.134.08:26:33.77/vb/06,04,usb,yes,31,33 2006.134.08:26:33.77/vb/07,04,usb,yes,32,32 2006.134.08:26:33.77/vb/08,04,usb,yes,30,33 2006.134.08:26:34.00/vblo/01,632.99,yes,locked 2006.134.08:26:34.00/vblo/02,640.99,yes,locked 2006.134.08:26:34.00/vblo/03,656.99,yes,locked 2006.134.08:26:34.00/vblo/04,712.99,yes,locked 2006.134.08:26:34.00/vblo/05,744.99,yes,locked 2006.134.08:26:34.00/vblo/06,752.99,yes,locked 2006.134.08:26:34.00/vblo/07,734.99,yes,locked 2006.134.08:26:34.00/vblo/08,744.99,yes,locked 2006.134.08:26:34.15/vabw/8 2006.134.08:26:34.30/vbbw/8 2006.134.08:26:34.39/xfe/off,on,15.0 2006.134.08:26:34.76/ifatt/23,28,28,28 2006.134.08:26:35.07/fmout-gps/S +1.82E-07 2006.134.08:26:35.11:!2006.134.08:27:30 2006.134.08:27:30.01:data_valid=off 2006.134.08:27:30.02:postob 2006.134.08:27:30.16/cable/+6.5460E-03 2006.134.08:27:30.17/wx/18.30,1007.2,86 2006.134.08:27:31.07/fmout-gps/S +1.82E-07 2006.134.08:27:31.08:checkk5last 2006.134.08:27:31.08&checkk5last/chk_obsdata=1 2006.134.08:27:31.08&checkk5last/chk_obsdata=2 2006.134.08:27:31.08&checkk5last/chk_obsdata=3 2006.134.08:27:31.09&checkk5last/chk_obsdata=4 2006.134.08:27:31.09&checkk5last/k5log=1 2006.134.08:27:31.09&checkk5last/k5log=2 2006.134.08:27:31.10&checkk5last/k5log=3 2006.134.08:27:31.10&checkk5last/k5log=4 2006.134.08:27:31.10&checkk5last/obsinfo 2006.134.08:27:31.48/chk_obsdata//k5ts1/T1340826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:27:31.84/chk_obsdata//k5ts2/T1340826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:27:32.22/chk_obsdata//k5ts3/T1340826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:27:32.58/chk_obsdata//k5ts4/T1340826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.134.08:27:33.27/k5log//k5ts1_log_newline 2006.134.08:27:33.95/k5log//k5ts2_log_newline 2006.134.08:27:34.64/k5log//k5ts3_log_newline 2006.134.08:27:35.33/k5log//k5ts4_log_newline 2006.134.08:27:35.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.134.08:27:35.35:sched_end 2006.134.08:27:35.35&sched_end/stopcheck 2006.134.08:27:35.35&stopcheck/sy=killall check_fsrun.pl 2006.134.08:27:35.35&stopcheck/" sy=killall chmem.sh 2006.134.08:27:35.44:source=idle 2006.134.08:27:36.14#flagr#flagr/antenna,new-source 2006.134.08:27:36.15:stow 2006.134.08:27:36.15&stow/source=idle 2006.134.08:27:36.15&stow/"this is stow command. 2006.134.08:27:36.16&stow/antenna=m3 2006.134.08:27:40.01:!+10m 2006.134.08:37:40.03:standby 2006.134.08:37:40.03&standby/"this is standby command. 2006.134.08:37:40.04&standby/antenna=m0 2006.134.08:37:41.01:sy=cp /usr2/log/k06134ts.log /usr2/log_backup/ 2006.134.08:37:41.05:*end of schedule 2006.134.20:43:04.46?ERROR st -97 Trouble decoding pressure data 2006.134.20:43:04.46#wxget#14 0.5 1.5 13.861001017.5