2006.132.07:36:33.19;Log Opened: Mark IV Field System Version 9.7.7 2006.132.07:36:33.19;location,TSUKUB32,-140.09,36.10,61.0 2006.132.07:36:33.19;horizon1,0.,5.,360. 2006.132.07:36:33.19;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.132.07:36:33.19;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.132.07:36:33.19;drivev11,330,270,no 2006.132.07:36:33.19;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.132.07:36:33.19;drivev13,15.000,268,10.000,10.000,10.000 2006.132.07:36:33.19;drivev21,330,270,no 2006.132.07:36:33.19;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.132.07:36:33.19;drivev23,15.000,268,10.000,10.000,10.000 2006.132.07:36:33.19;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.132.07:36:33.19;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.132.07:36:33.19;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.132.07:36:33.19;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.132.07:36:33.19;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.132.07:36:33.19;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.132.07:36:33.19;time,-0.364,101.533,rate 2006.132.07:36:33.19;flagr,200 2006.132.07:36:33.19:" K06133 2006 TSUKUB32 T Ts 2006.132.07:36:33.19:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.132.07:36:33.19:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.132.07:36:33.19:" 108 TSUKUB32 14 17400 2006.132.07:36:33.19:" drudg version 050216 compiled under FS 9.7.07 2006.132.07:36:33.19:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.132.07:36:33.19:exper_initi 2006.132.07:36:33.19&exper_initi/proc_library 2006.132.07:36:33.19&exper_initi/sched_initi 2006.132.07:36:33.19:!2006.133.07:19:50 2006.132.07:36:33.19&proc_library/" k06133 tsukub32 ts 2006.132.07:36:33.19&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.132.07:36:33.19&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.132.07:36:33.19&sched_initi/startcheck 2006.132.07:36:33.19&startcheck/sy=check_fsrun.pl & 2006.132.07:36:33.19&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.132.07:36:54.47;cable 2006.132.07:36:54.68/cable/+6.5447E-03 2006.132.07:37:43.55;cablelong 2006.132.07:37:43.73/cablelong/+7.0993E-03 2006.132.07:37:45.91;cablediff 2006.132.07:37:45.91/cablediff/554.6e-6,+ 2006.132.07:38:28.79;cable 2006.132.07:38:29.00/cable/+6.5455E-03 2006.132.07:38:35.16;wx 2006.132.07:38:35.16/wx/17.57,1019.5,38 2006.132.07:38:48.01;"Sky is fine. 2006.132.07:38:56.04;xfe 2006.132.07:38:56.21/xfe/off,on,14.5 2006.132.07:39:03.04;clockoff 2006.132.07:39:03.04&clockoff/"gps-fmout=1p 2006.132.07:39:03.04&clockoff/fmout-gps=1p 2006.132.07:39:04.07/fmout-gps/S +1.94E-07 2006.133.07:19:50.00:unstow 2006.133.07:19:50.00&unstow/antenna=e 2006.133.07:19:50.00&unstow/!+10s 2006.133.07:19:50.00&unstow/antenna=m2 2006.133.07:20:02.01:scan_name=133-0730,k06133,60 2006.133.07:20:02.01:source=3c371,180650.68,694928.1,2000.0,ccw 2006.133.07:20:03.14#antcn#PM 1 00019 2005 228 00 22 31 00 2006.133.07:20:03.14#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.133.07:20:03.14#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.133.07:20:03.14#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.133.07:20:03.14#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.133.07:20:03.14#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.133.07:20:04.14:ready_k5 2006.133.07:20:04.14&ready_k5/obsinfo=st 2006.133.07:20:04.14&ready_k5/autoobs=1 2006.133.07:20:04.14&ready_k5/autoobs=2 2006.133.07:20:04.14&ready_k5/autoobs=3 2006.133.07:20:04.14&ready_k5/autoobs=4 2006.133.07:20:04.14&ready_k5/obsinfo 2006.133.07:20:04.14#flagr#flagr/antenna,new-source 2006.133.07:20:04.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.133.07:20:07.33/autoobs//k5ts1/ autoobs started! 2006.133.07:20:10.43/autoobs//k5ts2/ autoobs started! 2006.133.07:20:13.57/autoobs//k5ts3/ autoobs started! 2006.133.07:20:16.67/autoobs//k5ts4/ autoobs started! 2006.133.07:20:16.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:20:16.70:4f8m12a=1 2006.133.07:20:16.70&4f8m12a/xlog=on 2006.133.07:20:16.70&4f8m12a/echo=on 2006.133.07:20:16.70&4f8m12a/pcalon 2006.133.07:20:16.70&4f8m12a/"tpicd=stop 2006.133.07:20:16.70&4f8m12a/vc4f8 2006.133.07:20:16.70&4f8m12a/ifd4f 2006.133.07:20:16.70&4f8m12a/"form=m,16.000,1:2 2006.133.07:20:16.70&4f8m12a/"tpicd 2006.133.07:20:16.70&4f8m12a/echo=off 2006.133.07:20:16.70&4f8m12a/xlog=off 2006.133.07:20:16.70$4f8m12a/echo=on 2006.133.07:20:16.70$4f8m12a/pcalon 2006.133.07:20:16.70&pcalon/"no phase cal control is implemented here 2006.133.07:20:16.70$pcalon/"no phase cal control is implemented here 2006.133.07:20:16.70$4f8m12a/"tpicd=stop 2006.133.07:20:16.70$4f8m12a/vc4f8 2006.133.07:20:16.70&vc4f8/valo=1,532.99 2006.133.07:20:16.70&vc4f8/va=1,8 2006.133.07:20:16.70&vc4f8/valo=2,572.99 2006.133.07:20:16.70&vc4f8/va=2,7 2006.133.07:20:16.70&vc4f8/valo=3,672.99 2006.133.07:20:16.70&vc4f8/va=3,6 2006.133.07:20:16.70&vc4f8/valo=4,832.99 2006.133.07:20:16.70&vc4f8/va=4,7 2006.133.07:20:16.70&vc4f8/valo=5,652.99 2006.133.07:20:16.70&vc4f8/va=5,6 2006.133.07:20:16.70&vc4f8/valo=6,772.99 2006.133.07:20:16.70&vc4f8/va=6,5 2006.133.07:20:16.70&vc4f8/valo=7,832.99 2006.133.07:20:16.70&vc4f8/va=7,5 2006.133.07:20:16.70&vc4f8/valo=8,852.99 2006.133.07:20:16.70&vc4f8/va=8,6 2006.133.07:20:16.70&vc4f8/vblo=1,632.99 2006.133.07:20:16.70&vc4f8/vb=1,4 2006.133.07:20:16.70&vc4f8/vblo=2,640.99 2006.133.07:20:16.70&vc4f8/vb=2,4 2006.133.07:20:16.70&vc4f8/vblo=3,656.99 2006.133.07:20:16.70&vc4f8/vb=3,4 2006.133.07:20:16.70&vc4f8/vblo=4,712.99 2006.133.07:20:16.70&vc4f8/vb=4,4 2006.133.07:20:16.70&vc4f8/vblo=5,744.99 2006.133.07:20:16.70&vc4f8/vb=5,4 2006.133.07:20:16.70&vc4f8/vblo=6,752.99 2006.133.07:20:16.70&vc4f8/vb=6,4 2006.133.07:20:16.70&vc4f8/vabw=wide 2006.133.07:20:16.70&vc4f8/vbbw=wide 2006.133.07:20:16.70$vc4f8/valo=1,532.99 2006.133.07:20:16.70#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:20:16.70#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:20:16.70#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:16.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:16.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:16.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:16.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:20:16.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:16.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:16.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:20:16.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:20:16.80$vc4f8/va=1,8 2006.133.07:20:16.80#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:20:16.80#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:20:16.80#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:16.80#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:16.80#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:16.80#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:16.83#ibcon#[25=AT01-08\r\n] 2006.133.07:20:16.86#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:16.86#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:16.86#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:20:16.86#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:16.86#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:16.98#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:16.98#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:17.00#ibcon#[25=USB\r\n] 2006.133.07:20:17.05#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:17.05#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:17.05#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:20:17.05#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:20:17.05$vc4f8/valo=2,572.99 2006.133.07:20:17.05#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:20:17.05#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:20:17.05#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:17.05#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:17.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:17.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:17.06#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:20:17.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:17.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:17.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:20:17.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:20:17.10$vc4f8/va=2,7 2006.133.07:20:17.10#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:20:17.10#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:20:17.10#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:17.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:17.17#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:17.17#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:17.19#ibcon#[25=AT02-07\r\n] 2006.133.07:20:17.22#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:17.22#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:17.22#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:20:17.22#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:17.22#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:17.34#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:17.34#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:17.36#ibcon#[25=USB\r\n] 2006.133.07:20:17.41#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:17.41#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:17.41#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:20:17.41#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:20:17.41$vc4f8/valo=3,672.99 2006.133.07:20:17.41#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:20:17.41#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:20:17.41#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:17.41#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:17.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:17.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:17.42#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:20:17.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:17.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:17.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:20:17.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:20:17.46$vc4f8/va=3,6 2006.133.07:20:17.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:20:17.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:20:17.46#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:17.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:17.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:17.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:17.55#ibcon#[25=AT03-06\r\n] 2006.133.07:20:17.58#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:17.58#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:17.58#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:20:17.58#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:17.58#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:17.70#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:17.70#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:17.72#ibcon#[25=USB\r\n] 2006.133.07:20:17.75#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:17.75#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:17.75#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:20:17.75#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:20:17.75$vc4f8/valo=4,832.99 2006.133.07:20:17.75#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:20:17.75#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:20:17.75#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:17.75#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:17.75#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:17.75#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:17.77#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:20:17.81#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:17.81#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:17.81#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:20:17.81#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:20:17.81$vc4f8/va=4,7 2006.133.07:20:17.81#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:20:17.81#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:20:17.81#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:17.81#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:17.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:17.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:17.89#ibcon#[25=AT04-07\r\n] 2006.133.07:20:17.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:17.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:17.92#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:20:17.92#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:17.92#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:18.04#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:18.04#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:18.06#ibcon#[25=USB\r\n] 2006.133.07:20:18.09#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:18.09#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:18.09#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:20:18.09#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:20:18.09$vc4f8/valo=5,652.99 2006.133.07:20:18.09#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:20:18.09#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:20:18.09#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:18.09#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:18.09#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:18.09#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:18.11#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:20:18.15#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:18.15#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:18.15#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:20:18.15#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:20:18.15$vc4f8/va=5,6 2006.133.07:20:18.15#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:20:18.15#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:20:18.15#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:18.15#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:18.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:18.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:18.23#ibcon#[25=AT05-06\r\n] 2006.133.07:20:18.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:18.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:18.26#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:20:18.26#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:18.26#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:18.38#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:18.38#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:18.40#ibcon#[25=USB\r\n] 2006.133.07:20:18.43#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:18.43#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:18.43#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:20:18.43#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:20:18.43$vc4f8/valo=6,772.99 2006.133.07:20:18.43#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:20:18.43#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:20:18.43#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:18.43#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:18.43#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:18.43#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:18.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:20:18.49#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:18.49#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:18.49#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:20:18.49#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:20:18.49$vc4f8/va=6,5 2006.133.07:20:18.49#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.07:20:18.49#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.07:20:18.49#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:18.49#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:18.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:18.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:18.57#ibcon#[25=AT06-05\r\n] 2006.133.07:20:18.60#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:18.60#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:18.60#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.07:20:18.60#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:18.60#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:20:18.72#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:20:18.72#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:20:18.74#ibcon#[25=USB\r\n] 2006.133.07:20:18.77#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:20:18.77#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:20:18.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:20:18.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:20:18.77$vc4f8/valo=7,832.99 2006.133.07:20:18.77#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.07:20:18.77#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.07:20:18.77#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:18.77#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:20:18.77#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:20:18.77#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:20:18.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:20:18.83#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:20:18.83#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:20:18.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:20:18.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:20:18.83$vc4f8/va=7,5 2006.133.07:20:18.83#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.07:20:18.83#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.07:20:18.83#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:18.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:20:18.89#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:20:18.89#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:20:18.91#ibcon#[25=AT07-05\r\n] 2006.133.07:20:18.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:20:18.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:20:18.94#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.07:20:18.94#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:18.94#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:20:19.06#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:20:19.06#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:20:19.08#ibcon#[25=USB\r\n] 2006.133.07:20:19.11#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:20:19.11#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:20:19.11#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:20:19.11#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:20:19.11$vc4f8/valo=8,852.99 2006.133.07:20:19.11#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:20:19.11#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:20:19.11#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:19.11#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:20:19.11#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:20:19.11#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:20:19.13#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:20:19.17#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:20:19.17#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:20:19.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:20:19.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:20:19.17$vc4f8/va=8,6 2006.133.07:20:19.17#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:20:19.17#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:20:19.17#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:19.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:20:19.23#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:20:19.23#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:20:19.25#ibcon#[25=AT08-06\r\n] 2006.133.07:20:19.28#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:20:19.28#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:20:19.28#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:20:19.28#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:19.28#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:20:19.40#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:20:19.40#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:20:19.42#ibcon#[25=USB\r\n] 2006.133.07:20:19.45#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:20:19.45#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:20:19.45#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:20:19.45#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:20:19.45$vc4f8/vblo=1,632.99 2006.133.07:20:19.45#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:20:19.45#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:20:19.45#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:19.45#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:20:19.45#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:20:19.45#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:20:19.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:20:19.53#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:20:19.53#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:20:19.53#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:20:19.53#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:20:19.53$vc4f8/vb=1,4 2006.133.07:20:19.53#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.07:20:19.53#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.07:20:19.53#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:19.53#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:20:19.53#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:20:19.53#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:20:19.55#ibcon#[27=AT01-04\r\n] 2006.133.07:20:19.59#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:20:19.59#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:20:19.59#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.07:20:19.59#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:19.59#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:20:19.71#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:20:19.71#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:20:19.73#ibcon#[27=USB\r\n] 2006.133.07:20:19.76#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:20:19.76#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:20:19.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:20:19.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:20:19.76$vc4f8/vblo=2,640.99 2006.133.07:20:19.76#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:20:19.76#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:20:19.76#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:19.76#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:19.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:19.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:19.78#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:20:19.82#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:19.82#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:20:19.82#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:20:19.82#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:20:19.82$vc4f8/vb=2,4 2006.133.07:20:19.82#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:20:19.82#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:20:19.82#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:19.82#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:19.88#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:19.88#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:19.90#ibcon#[27=AT02-04\r\n] 2006.133.07:20:19.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:19.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:20:19.93#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:20:19.93#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:19.93#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:20.05#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:20.05#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:20.07#ibcon#[27=USB\r\n] 2006.133.07:20:20.10#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:20.10#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:20:20.10#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:20:20.10#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:20:20.10$vc4f8/vblo=3,656.99 2006.133.07:20:20.10#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:20:20.10#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:20:20.10#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:20.10#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:20.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:20.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:20.12#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:20:20.16#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:20.16#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:20:20.16#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:20:20.16#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:20:20.16$vc4f8/vb=3,4 2006.133.07:20:20.16#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:20:20.16#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:20:20.16#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:20.16#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:20.22#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:20.22#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:20.24#ibcon#[27=AT03-04\r\n] 2006.133.07:20:20.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:20.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:20:20.27#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:20:20.27#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:20.27#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:20.39#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:20.39#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:20.41#ibcon#[27=USB\r\n] 2006.133.07:20:20.44#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:20.44#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:20:20.44#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:20:20.44#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:20:20.44$vc4f8/vblo=4,712.99 2006.133.07:20:20.44#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:20:20.44#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:20:20.44#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:20.44#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:20.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:20.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:20.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:20:20.50#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:20.50#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:20:20.50#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:20:20.50#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:20:20.50$vc4f8/vb=4,4 2006.133.07:20:20.50#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:20:20.50#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:20:20.50#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:20.50#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:20.56#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:20.56#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:20.58#ibcon#[27=AT04-04\r\n] 2006.133.07:20:20.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:20.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:20:20.61#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:20:20.61#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:20.61#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:20.73#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:20.73#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:20.75#ibcon#[27=USB\r\n] 2006.133.07:20:20.78#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:20.78#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:20:20.78#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:20:20.78#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:20:20.78$vc4f8/vblo=5,744.99 2006.133.07:20:20.78#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:20:20.78#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:20:20.78#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:20.78#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:20.78#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:20.78#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:20.80#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:20:20.84#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:20.84#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:20:20.84#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:20:20.84#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:20:20.84$vc4f8/vb=5,4 2006.133.07:20:20.84#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:20:20.84#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:20:20.84#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:20.84#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:20.90#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:20.90#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:20.92#ibcon#[27=AT05-04\r\n] 2006.133.07:20:20.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:20.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:20:20.95#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:20:20.95#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:20.95#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:21.07#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:21.07#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:21.09#ibcon#[27=USB\r\n] 2006.133.07:20:21.12#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:21.12#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:20:21.12#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:20:21.12#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:20:21.12$vc4f8/vblo=6,752.99 2006.133.07:20:21.12#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:20:21.12#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:20:21.12#ibcon#ireg 17 cls_cnt 0 2006.133.07:20:21.12#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:21.12#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:21.12#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:21.14#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:20:21.18#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:21.18#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:20:21.18#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:20:21.18#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:20:21.18$vc4f8/vb=6,4 2006.133.07:20:21.18#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:20:21.18#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:20:21.18#ibcon#ireg 11 cls_cnt 2 2006.133.07:20:21.18#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:21.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:21.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:21.26#ibcon#[27=AT06-04\r\n] 2006.133.07:20:21.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:21.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:20:21.29#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:20:21.29#ibcon#ireg 7 cls_cnt 0 2006.133.07:20:21.29#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:21.41#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:21.41#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:21.43#ibcon#[27=USB\r\n] 2006.133.07:20:21.46#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:21.46#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:20:21.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:20:21.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:20:21.46$vc4f8/vabw=wide 2006.133.07:20:21.46#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:20:21.46#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:20:21.46#ibcon#ireg 8 cls_cnt 0 2006.133.07:20:21.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:21.46#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:21.46#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:21.48#ibcon#[25=BW32\r\n] 2006.133.07:20:21.51#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:21.51#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:20:21.51#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:20:21.51#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:20:21.51$vc4f8/vbbw=wide 2006.133.07:20:21.51#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:20:21.51#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:20:21.51#ibcon#ireg 8 cls_cnt 0 2006.133.07:20:21.51#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:20:21.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:20:21.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:20:21.60#ibcon#[27=BW32\r\n] 2006.133.07:20:21.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:20:21.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:20:21.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:20:21.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:20:21.63$4f8m12a/ifd4f 2006.133.07:20:21.63&ifd4f/lo= 2006.133.07:20:21.63&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:20:21.63&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:20:21.63&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:20:21.63&ifd4f/patch= 2006.133.07:20:21.63&ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:20:21.63&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:20:21.63&ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:20:21.63$ifd4f/lo= 2006.133.07:20:21.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:20:21.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:20:21.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:20:21.63$ifd4f/patch= 2006.133.07:20:21.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:20:21.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:20:21.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:20:21.63$4f8m12a/"form=m,16.000,1:2 2006.133.07:20:21.63$4f8m12a/"tpicd 2006.133.07:20:21.63$4f8m12a/echo=off 2006.133.07:20:21.63$4f8m12a/xlog=off 2006.133.07:20:21.63:!2006.133.07:29:50 2006.133.07:20:41.14#trakl#Source acquired 2006.133.07:20:41.14#flagr#flagr/antenna,acquired 2006.133.07:29:50.00:preob 2006.133.07:29:50.00&preob/onsource 2006.133.07:29:51.14/onsource/TRACKING 2006.133.07:29:51.14:!2006.133.07:30:00 2006.133.07:30:00.00:data_valid=on 2006.133.07:30:00.00:midob 2006.133.07:30:00.00&midob/onsource 2006.133.07:30:00.00&midob/wx 2006.133.07:30:00.00&midob/cable 2006.133.07:30:00.00&midob/va 2006.133.07:30:00.00&midob/valo 2006.133.07:30:00.00&midob/vb 2006.133.07:30:00.00&midob/vblo 2006.133.07:30:00.00&midob/vabw 2006.133.07:30:00.00&midob/vbbw 2006.133.07:30:00.00&midob/"form 2006.133.07:30:00.00&midob/xfe 2006.133.07:30:00.00&midob/ifatt 2006.133.07:30:00.00&midob/clockoff 2006.133.07:30:00.00&midob/sy=logmail 2006.133.07:30:00.00&midob/"sy=run setcl adapt & 2006.133.07:30:00.14/onsource/TRACKING 2006.133.07:30:00.14/wx/11.34,1010.4,100 2006.133.07:30:00.34/cable/+6.5566E-03 2006.133.07:30:01.43/va/01,08,usb,yes,43,46 2006.133.07:30:01.43/va/02,07,usb,yes,44,46 2006.133.07:30:01.43/va/03,06,usb,yes,46,47 2006.133.07:30:01.43/va/04,07,usb,yes,45,48 2006.133.07:30:01.43/va/05,06,usb,yes,52,55 2006.133.07:30:01.43/va/06,05,usb,yes,53,52 2006.133.07:30:01.43/va/07,05,usb,yes,53,52 2006.133.07:30:01.43/va/08,06,usb,yes,49,48 2006.133.07:30:01.66/valo/01,532.99,yes,locked 2006.133.07:30:01.66/valo/02,572.99,yes,locked 2006.133.07:30:01.66/valo/03,672.99,yes,locked 2006.133.07:30:01.66/valo/04,832.99,yes,locked 2006.133.07:30:01.66/valo/05,652.99,yes,locked 2006.133.07:30:01.66/valo/06,772.99,yes,locked 2006.133.07:30:01.66/valo/07,832.99,yes,locked 2006.133.07:30:01.66/valo/08,852.99,yes,locked 2006.133.07:30:02.75/vb/01,04,usb,yes,36,96 2006.133.07:30:02.75/vb/02,04,usb,yes,30,95 2006.133.07:30:02.75/vb/03,04,usb,yes,28,52 2006.133.07:30:02.75/vb/04,04,usb,yes,29,29 2006.133.07:30:02.75/vb/05,04,usb,yes,28,32 2006.133.07:30:02.75/vb/06,04,usb,yes,29,31 2006.133.07:30:02.75/vb/07,04,usb,yes,30,30 2006.133.07:30:02.75/vb/08,04,usb,yes,28,31 2006.133.07:30:02.98/vblo/01,632.99,yes,locked 2006.133.07:30:02.98/vblo/02,640.99,yes,locked 2006.133.07:30:02.98/vblo/03,656.99,yes,locked 2006.133.07:30:02.98/vblo/04,712.99,yes,locked 2006.133.07:30:02.98/vblo/05,744.99,yes,locked 2006.133.07:30:02.98/vblo/06,752.99,yes,locked 2006.133.07:30:02.98/vblo/07,734.99,yes,locked 2006.133.07:30:02.98/vblo/08,744.99,yes,locked 2006.133.07:30:03.13/vabw/8 2006.133.07:30:03.28/vbbw/8 2006.133.07:30:03.37/xfe/off,on,15.2 2006.133.07:30:03.75/ifatt/23,28,28,28 2006.133.07:30:04.08/fmout-gps/S +1.88E-07 2006.133.07:30:04.16:!2006.133.07:31:00 2006.133.07:31:00.00:data_valid=off 2006.133.07:31:00.00:postob 2006.133.07:31:00.01&postob/cable 2006.133.07:31:00.01&postob/wx 2006.133.07:31:00.01&postob/clockoff 2006.133.07:31:00.20/cable/+6.5571E-03 2006.133.07:31:00.20/wx/11.34,1010.4,100 2006.133.07:31:01.08/fmout-gps/S +1.89E-07 2006.133.07:31:01.08:scan_name=133-0733,k06133,60 2006.133.07:31:01.09:source=cta26,033930.94,-014635.8,2000.0,ccw 2006.133.07:31:01.13#flagr#flagr/antenna,new-source 2006.133.07:31:02.13:checkk5 2006.133.07:31:02.13&checkk5/chk_autoobs=1 2006.133.07:31:02.14&checkk5/chk_autoobs=2 2006.133.07:31:02.14&checkk5/chk_autoobs=3 2006.133.07:31:02.14&checkk5/chk_autoobs=4 2006.133.07:31:02.15&checkk5/chk_obsdata=1 2006.133.07:31:02.15&checkk5/chk_obsdata=2 2006.133.07:31:02.15&checkk5/chk_obsdata=3 2006.133.07:31:02.15&checkk5/chk_obsdata=4 2006.133.07:31:02.15&checkk5/k5log=1 2006.133.07:31:02.15&checkk5/k5log=2 2006.133.07:31:02.15&checkk5/k5log=3 2006.133.07:31:02.15&checkk5/k5log=4 2006.133.07:31:02.15&checkk5/obsinfo 2006.133.07:31:02.55/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:31:02.94/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:31:03.33/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:31:03.71/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:31:04.08/chk_obsdata//k5ts1/T1330730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:31:04.45/chk_obsdata//k5ts2/T1330730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:31:04.81/chk_obsdata//k5ts3/T1330730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:31:05.18/chk_obsdata//k5ts4/T1330730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:31:05.88/k5log//k5ts1_log_newline 2006.133.07:31:06.56/k5log//k5ts2_log_newline 2006.133.07:31:07.25/k5log//k5ts3_log_newline 2006.133.07:31:07.94/k5log//k5ts4_log_newline 2006.133.07:31:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:31:07.96:4f8m12a=1 2006.133.07:31:07.96$4f8m12a/echo=on 2006.133.07:31:07.96$4f8m12a/pcalon 2006.133.07:31:07.96$pcalon/"no phase cal control is implemented here 2006.133.07:31:07.96$4f8m12a/"tpicd=stop 2006.133.07:31:07.96$4f8m12a/vc4f8 2006.133.07:31:07.96$vc4f8/valo=1,532.99 2006.133.07:31:07.96#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:31:07.96#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:31:07.96#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:07.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:07.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:07.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:31:08.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:08.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:08.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:31:08.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:31:08.05$vc4f8/va=1,8 2006.133.07:31:08.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:31:08.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:31:08.05#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:08.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:08.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:08.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:08.07#ibcon#[25=AT01-08\r\n] 2006.133.07:31:08.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:08.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:08.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:31:08.10#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:08.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:08.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:08.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:08.24#ibcon#[25=USB\r\n] 2006.133.07:31:08.29#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:08.29#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:08.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:31:08.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:31:08.29$vc4f8/valo=2,572.99 2006.133.07:31:08.29#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:31:08.29#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:31:08.29#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:08.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:08.29#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:08.29#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:08.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:31:08.34#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:08.34#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:08.34#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:31:08.34#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:31:08.34$vc4f8/va=2,7 2006.133.07:31:08.34#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.07:31:08.34#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.07:31:08.34#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:08.34#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:08.41#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:08.41#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:08.43#ibcon#[25=AT02-07\r\n] 2006.133.07:31:08.46#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:08.46#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:08.46#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.07:31:08.46#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:08.46#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:08.58#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:08.58#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:08.60#ibcon#[25=USB\r\n] 2006.133.07:31:08.65#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:08.65#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:08.65#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:31:08.65#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:31:08.65$vc4f8/valo=3,672.99 2006.133.07:31:08.65#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:31:08.65#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:31:08.65#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:08.65#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:08.65#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:08.65#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:08.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:31:08.70#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:08.70#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:08.70#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:31:08.70#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:31:08.70$vc4f8/va=3,6 2006.133.07:31:08.70#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:31:08.70#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:31:08.70#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:08.70#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:08.77#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:08.77#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:08.79#ibcon#[25=AT03-06\r\n] 2006.133.07:31:08.82#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:08.82#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:08.82#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:31:08.82#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:08.82#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:08.94#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:08.94#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:08.96#ibcon#[25=USB\r\n] 2006.133.07:31:08.99#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:08.99#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:08.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:31:08.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:31:08.99$vc4f8/valo=4,832.99 2006.133.07:31:08.99#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.07:31:08.99#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.07:31:08.99#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:08.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:08.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:08.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:09.01#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:31:09.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:09.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:09.05#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:31:09.05#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:31:09.05$vc4f8/va=4,7 2006.133.07:31:09.05#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.07:31:09.05#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.07:31:09.05#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:09.05#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:09.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:09.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:09.13#ibcon#[25=AT04-07\r\n] 2006.133.07:31:09.16#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:09.16#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:09.16#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.07:31:09.16#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:09.16#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:09.28#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:09.28#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:09.30#ibcon#[25=USB\r\n] 2006.133.07:31:09.33#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:09.33#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:09.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:31:09.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:31:09.33$vc4f8/valo=5,652.99 2006.133.07:31:09.33#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:31:09.33#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:31:09.33#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:09.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:09.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:09.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:09.35#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:31:09.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:09.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:09.39#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:31:09.39#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:31:09.39$vc4f8/va=5,6 2006.133.07:31:09.39#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.07:31:09.39#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.07:31:09.39#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:09.39#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:09.45#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:09.45#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:09.47#ibcon#[25=AT05-06\r\n] 2006.133.07:31:09.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:09.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:09.50#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.07:31:09.50#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:09.50#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:09.62#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:09.62#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:09.64#ibcon#[25=USB\r\n] 2006.133.07:31:09.67#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:09.67#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:09.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:31:09.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:31:09.67$vc4f8/valo=6,772.99 2006.133.07:31:09.67#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.07:31:09.67#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.07:31:09.67#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:09.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:09.67#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:09.67#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:09.69#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:31:09.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:09.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:09.73#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:31:09.73#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:31:09.73$vc4f8/va=6,5 2006.133.07:31:09.73#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.07:31:09.73#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.07:31:09.73#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:09.73#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:09.79#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:09.79#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:09.81#ibcon#[25=AT06-05\r\n] 2006.133.07:31:09.84#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:09.84#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:09.84#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.07:31:09.84#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:09.84#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:31:09.96#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:31:09.96#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:31:09.98#ibcon#[25=USB\r\n] 2006.133.07:31:10.01#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:31:10.01#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:31:10.01#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:31:10.01#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:31:10.01$vc4f8/valo=7,832.99 2006.133.07:31:10.01#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.07:31:10.01#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.07:31:10.01#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:10.01#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:31:10.01#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:31:10.01#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:31:10.03#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:31:10.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:31:10.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:31:10.07#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:31:10.07#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:31:10.07$vc4f8/va=7,5 2006.133.07:31:10.07#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.07:31:10.07#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.07:31:10.07#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:10.07#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:31:10.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:31:10.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:31:10.15#ibcon#[25=AT07-05\r\n] 2006.133.07:31:10.18#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:31:10.18#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:31:10.18#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.07:31:10.18#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:10.18#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:31:10.30#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:31:10.30#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:31:10.32#ibcon#[25=USB\r\n] 2006.133.07:31:10.37#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:31:10.37#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:31:10.37#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:31:10.37#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:31:10.37$vc4f8/valo=8,852.99 2006.133.07:31:10.37#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.07:31:10.37#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.07:31:10.37#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:10.37#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:31:10.37#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:31:10.37#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:31:10.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:31:10.42#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:31:10.42#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:31:10.42#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:31:10.42#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:31:10.42$vc4f8/va=8,6 2006.133.07:31:10.42#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.07:31:10.42#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.07:31:10.42#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:10.42#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:31:10.49#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:31:10.49#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:31:10.51#ibcon#[25=AT08-06\r\n] 2006.133.07:31:10.54#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:31:10.54#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:31:10.54#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.07:31:10.54#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:10.54#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:31:10.66#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:31:10.66#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:31:10.68#ibcon#[25=USB\r\n] 2006.133.07:31:10.71#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:31:10.71#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:31:10.71#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:31:10.71#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:31:10.71$vc4f8/vblo=1,632.99 2006.133.07:31:10.71#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.07:31:10.71#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.07:31:10.71#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:10.71#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:31:10.71#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:31:10.71#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:31:10.73#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:31:10.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:31:10.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:31:10.77#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:31:10.77#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:31:10.77$vc4f8/vb=1,4 2006.133.07:31:10.77#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.07:31:10.77#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.07:31:10.77#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:10.77#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:31:10.77#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:31:10.77#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:31:10.79#ibcon#[27=AT01-04\r\n] 2006.133.07:31:10.82#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:31:10.82#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:31:10.82#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.07:31:10.82#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:10.82#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:31:10.94#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:31:10.94#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:31:10.96#ibcon#[27=USB\r\n] 2006.133.07:31:10.99#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:31:10.99#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:31:10.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:31:10.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:31:10.99$vc4f8/vblo=2,640.99 2006.133.07:31:10.99#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:31:10.99#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:31:10.99#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:10.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:10.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:10.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:11.01#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:31:11.05#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:11.05#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:31:11.05#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:31:11.05#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:31:11.05$vc4f8/vb=2,4 2006.133.07:31:11.05#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:31:11.05#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:31:11.05#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:11.05#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:11.11#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:11.11#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:11.13#ibcon#[27=AT02-04\r\n] 2006.133.07:31:11.16#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:11.16#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:31:11.16#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:31:11.16#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:11.16#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:11.28#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:11.28#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:11.30#ibcon#[27=USB\r\n] 2006.133.07:31:11.33#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:11.33#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:31:11.33#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:31:11.33#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:31:11.33$vc4f8/vblo=3,656.99 2006.133.07:31:11.33#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:31:11.33#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:31:11.33#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:11.33#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:11.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:11.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:11.35#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:31:11.39#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:11.39#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:31:11.39#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:31:11.39#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:31:11.39$vc4f8/vb=3,4 2006.133.07:31:11.39#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.07:31:11.39#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.07:31:11.39#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:11.39#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:11.45#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:11.45#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:11.47#ibcon#[27=AT03-04\r\n] 2006.133.07:31:11.50#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:11.50#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:31:11.50#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.07:31:11.50#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:11.50#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:11.62#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:11.62#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:11.64#ibcon#[27=USB\r\n] 2006.133.07:31:11.67#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:11.67#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:31:11.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:31:11.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:31:11.67$vc4f8/vblo=4,712.99 2006.133.07:31:11.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:31:11.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:31:11.67#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:11.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:11.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:11.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:11.69#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:31:11.73#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:11.73#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:31:11.73#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:31:11.73#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:31:11.73$vc4f8/vb=4,4 2006.133.07:31:11.73#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:31:11.73#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:31:11.73#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:11.73#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:11.79#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:11.79#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:11.81#ibcon#[27=AT04-04\r\n] 2006.133.07:31:11.84#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:11.84#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:31:11.84#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:31:11.84#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:11.84#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:11.96#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:11.96#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:11.98#ibcon#[27=USB\r\n] 2006.133.07:31:12.01#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:12.01#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:31:12.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:31:12.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:31:12.01$vc4f8/vblo=5,744.99 2006.133.07:31:12.01#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.07:31:12.01#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.07:31:12.01#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:12.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:12.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:12.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:12.03#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:31:12.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:12.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:31:12.07#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:31:12.07#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:31:12.07$vc4f8/vb=5,4 2006.133.07:31:12.07#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.07:31:12.07#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.07:31:12.07#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:12.07#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:12.13#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:12.13#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:12.15#ibcon#[27=AT05-04\r\n] 2006.133.07:31:12.18#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:12.18#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:31:12.18#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.07:31:12.18#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:12.18#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:12.30#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:12.30#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:12.32#ibcon#[27=USB\r\n] 2006.133.07:31:12.35#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:12.35#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:31:12.35#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:31:12.35#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:31:12.35$vc4f8/vblo=6,752.99 2006.133.07:31:12.35#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:31:12.35#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:31:12.35#ibcon#ireg 17 cls_cnt 0 2006.133.07:31:12.35#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:12.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:12.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:12.37#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:31:12.41#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:12.41#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:31:12.41#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:31:12.41#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:31:12.41$vc4f8/vb=6,4 2006.133.07:31:12.41#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.07:31:12.41#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.07:31:12.41#ibcon#ireg 11 cls_cnt 2 2006.133.07:31:12.41#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:12.47#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:12.47#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:12.49#ibcon#[27=AT06-04\r\n] 2006.133.07:31:12.52#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:12.52#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:31:12.52#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.07:31:12.52#ibcon#ireg 7 cls_cnt 0 2006.133.07:31:12.52#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:12.64#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:12.64#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:12.66#ibcon#[27=USB\r\n] 2006.133.07:31:12.69#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:12.69#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:31:12.69#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:31:12.69#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:31:12.69$vc4f8/vabw=wide 2006.133.07:31:12.69#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.07:31:12.69#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.07:31:12.69#ibcon#ireg 8 cls_cnt 0 2006.133.07:31:12.69#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:12.69#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:12.69#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:12.71#ibcon#[25=BW32\r\n] 2006.133.07:31:12.74#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:12.74#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:31:12.74#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:31:12.74#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:31:12.74$vc4f8/vbbw=wide 2006.133.07:31:12.74#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:31:12.74#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:31:12.74#ibcon#ireg 8 cls_cnt 0 2006.133.07:31:12.74#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:31:12.81#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:31:12.81#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:31:12.83#ibcon#[27=BW32\r\n] 2006.133.07:31:12.86#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:31:12.86#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:31:12.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:31:12.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:31:12.86$4f8m12a/ifd4f 2006.133.07:31:12.86$ifd4f/lo= 2006.133.07:31:12.86$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:31:12.86$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:31:12.86$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:31:12.86$ifd4f/patch= 2006.133.07:31:12.86$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:31:12.86$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:31:12.86$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:31:12.86$4f8m12a/"form=m,16.000,1:2 2006.133.07:31:12.86$4f8m12a/"tpicd 2006.133.07:31:12.86$4f8m12a/echo=off 2006.133.07:31:12.86$4f8m12a/xlog=off 2006.133.07:31:12.86:!2006.133.07:33:20 2006.133.07:31:50.13#trakl#Source acquired 2006.133.07:31:52.13#flagr#flagr/antenna,acquired 2006.133.07:33:20.00:preob 2006.133.07:33:20.14/onsource/TRACKING 2006.133.07:33:20.14:!2006.133.07:33:30 2006.133.07:33:30.00:data_valid=on 2006.133.07:33:30.00:midob 2006.133.07:33:31.14/onsource/TRACKING 2006.133.07:33:31.14/wx/11.32,1010.3,100 2006.133.07:33:31.36/cable/+6.5566E-03 2006.133.07:33:32.45/va/01,08,usb,yes,44,46 2006.133.07:33:32.45/va/02,07,usb,yes,44,46 2006.133.07:33:32.45/va/03,06,usb,yes,47,47 2006.133.07:33:32.45/va/04,07,usb,yes,45,48 2006.133.07:33:32.45/va/05,06,usb,yes,52,55 2006.133.07:33:32.45/va/06,05,usb,yes,53,53 2006.133.07:33:32.45/va/07,05,usb,yes,53,53 2006.133.07:33:32.45/va/08,06,usb,yes,49,49 2006.133.07:33:32.68/valo/01,532.99,yes,locked 2006.133.07:33:32.68/valo/02,572.99,yes,locked 2006.133.07:33:32.68/valo/03,672.99,yes,locked 2006.133.07:33:32.68/valo/04,832.99,yes,locked 2006.133.07:33:32.68/valo/05,652.99,yes,locked 2006.133.07:33:32.68/valo/06,772.99,yes,locked 2006.133.07:33:32.68/valo/07,832.99,yes,locked 2006.133.07:33:32.68/valo/08,852.99,yes,locked 2006.133.07:33:33.77/vb/01,04,usb,yes,30,28 2006.133.07:33:33.77/vb/02,04,usb,yes,32,33 2006.133.07:33:33.77/vb/03,04,usb,yes,28,32 2006.133.07:33:33.77/vb/04,04,usb,yes,29,29 2006.133.07:33:33.77/vb/05,04,usb,yes,28,31 2006.133.07:33:33.77/vb/06,04,usb,yes,29,31 2006.133.07:33:33.77/vb/07,04,usb,yes,31,30 2006.133.07:33:33.77/vb/08,04,usb,yes,28,31 2006.133.07:33:34.00/vblo/01,632.99,yes,locked 2006.133.07:33:34.00/vblo/02,640.99,yes,locked 2006.133.07:33:34.00/vblo/03,656.99,yes,locked 2006.133.07:33:34.00/vblo/04,712.99,yes,locked 2006.133.07:33:34.00/vblo/05,744.99,yes,locked 2006.133.07:33:34.00/vblo/06,752.99,yes,locked 2006.133.07:33:34.00/vblo/07,734.99,yes,locked 2006.133.07:33:34.00/vblo/08,744.99,yes,locked 2006.133.07:33:34.15/vabw/8 2006.133.07:33:34.30/vbbw/8 2006.133.07:33:34.39/xfe/off,on,15.2 2006.133.07:33:34.78/ifatt/23,28,28,28 2006.133.07:33:35.08/fmout-gps/S +1.88E-07 2006.133.07:33:35.12:!2006.133.07:34:30 2006.133.07:34:30.00:data_valid=off 2006.133.07:34:30.00:postob 2006.133.07:34:30.10/cable/+6.5595E-03 2006.133.07:34:30.10/wx/11.32,1010.2,100 2006.133.07:34:31.08/fmout-gps/S +1.87E-07 2006.133.07:34:31.08:scan_name=133-0735,k06133,60 2006.133.07:34:31.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.133.07:34:31.16#flagr#flagr/antenna,new-source 2006.133.07:34:32.13:checkk5 2006.133.07:34:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:34:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:34:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:34:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:34:33.99/chk_obsdata//k5ts1/T1330733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:34:34.36/chk_obsdata//k5ts2/T1330733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:34:34.73/chk_obsdata//k5ts3/T1330733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:34:35.10/chk_obsdata//k5ts4/T1330733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:34:35.78/k5log//k5ts1_log_newline 2006.133.07:34:36.46/k5log//k5ts2_log_newline 2006.133.07:34:37.15/k5log//k5ts3_log_newline 2006.133.07:34:37.84/k5log//k5ts4_log_newline 2006.133.07:34:37.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:34:37.86:4f8m12a=1 2006.133.07:34:37.86$4f8m12a/echo=on 2006.133.07:34:37.86$4f8m12a/pcalon 2006.133.07:34:37.86$pcalon/"no phase cal control is implemented here 2006.133.07:34:37.86$4f8m12a/"tpicd=stop 2006.133.07:34:37.86$4f8m12a/vc4f8 2006.133.07:34:37.86$vc4f8/valo=1,532.99 2006.133.07:34:37.87#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:34:37.87#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:34:37.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:37.87#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:37.87#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:37.87#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:34:37.96#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:37.96#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:37.96#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:34:37.96#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:34:37.96$vc4f8/va=1,8 2006.133.07:34:37.96#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:34:37.96#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:34:37.96#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:37.96#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:37.96#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:37.96#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:37.99#ibcon#[25=AT01-08\r\n] 2006.133.07:34:38.02#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:38.02#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:38.02#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:34:38.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:38.02#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:38.14#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:38.14#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:38.16#ibcon#[25=USB\r\n] 2006.133.07:34:38.19#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:38.19#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:38.19#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:34:38.19#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:34:38.19$vc4f8/valo=2,572.99 2006.133.07:34:38.19#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:34:38.19#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:34:38.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:38.19#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:38.19#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:38.19#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:34:38.26#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:38.26#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:38.26#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:34:38.26#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:34:38.26$vc4f8/va=2,7 2006.133.07:34:38.26#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:34:38.26#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:34:38.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:38.26#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:38.31#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:38.31#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:38.33#ibcon#[25=AT02-07\r\n] 2006.133.07:34:38.36#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:38.36#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:38.36#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:34:38.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:38.36#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:38.48#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:38.48#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:38.50#ibcon#[25=USB\r\n] 2006.133.07:34:38.55#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:38.55#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:38.55#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:34:38.55#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:34:38.55$vc4f8/valo=3,672.99 2006.133.07:34:38.55#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:34:38.55#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:34:38.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:38.55#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:38.55#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:38.55#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:34:38.60#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:38.60#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:38.60#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:34:38.60#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:34:38.60$vc4f8/va=3,6 2006.133.07:34:38.60#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:34:38.60#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:34:38.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:38.60#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:38.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:38.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:38.69#ibcon#[25=AT03-06\r\n] 2006.133.07:34:38.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:38.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:38.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:34:38.72#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:38.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:38.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:38.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:38.86#ibcon#[25=USB\r\n] 2006.133.07:34:38.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:38.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:38.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:34:38.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:34:38.89$vc4f8/valo=4,832.99 2006.133.07:34:38.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:34:38.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:34:38.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:38.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:38.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:38.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:34:38.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:38.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:38.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:34:38.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:34:38.95$vc4f8/va=4,7 2006.133.07:34:38.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:34:38.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:34:38.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:38.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:39.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:39.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:39.03#ibcon#[25=AT04-07\r\n] 2006.133.07:34:39.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:39.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:39.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:34:39.06#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:39.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:39.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:39.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:39.20#ibcon#[25=USB\r\n] 2006.133.07:34:39.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:39.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:39.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:34:39.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:34:39.23$vc4f8/valo=5,652.99 2006.133.07:34:39.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:34:39.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:34:39.23#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:39.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:39.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:39.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:34:39.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:39.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:39.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:34:39.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:34:39.29$vc4f8/va=5,6 2006.133.07:34:39.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:34:39.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:34:39.29#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:39.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:39.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:39.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:39.37#ibcon#[25=AT05-06\r\n] 2006.133.07:34:39.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:39.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:39.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:34:39.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:39.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:39.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:39.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:39.54#ibcon#[25=USB\r\n] 2006.133.07:34:39.59#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:39.59#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:39.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:34:39.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:34:39.59$vc4f8/valo=6,772.99 2006.133.07:34:39.59#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:34:39.59#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:34:39.59#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:39.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:39.59#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:39.59#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:34:39.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:39.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:39.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:34:39.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:34:39.64$vc4f8/va=6,5 2006.133.07:34:39.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:34:39.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:34:39.64#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:39.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:39.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:39.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:39.73#ibcon#[25=AT06-05\r\n] 2006.133.07:34:39.76#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:39.76#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:39.76#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:34:39.76#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:39.76#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:39.88#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:39.88#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:39.90#ibcon#[25=USB\r\n] 2006.133.07:34:39.93#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:39.93#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:39.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:34:39.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:34:39.93$vc4f8/valo=7,832.99 2006.133.07:34:39.93#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:34:39.93#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:34:39.93#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:39.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:39.93#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:39.93#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:34:39.99#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:39.99#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:39.99#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:34:39.99#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:34:39.99$vc4f8/va=7,5 2006.133.07:34:39.99#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.07:34:39.99#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.07:34:39.99#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:39.99#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:40.05#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:40.05#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:40.07#ibcon#[25=AT07-05\r\n] 2006.133.07:34:40.10#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:40.10#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:40.10#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.07:34:40.10#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:40.10#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:34:40.22#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:34:40.22#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:34:40.24#ibcon#[25=USB\r\n] 2006.133.07:34:40.27#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:34:40.27#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:34:40.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:34:40.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:34:40.27$vc4f8/valo=8,852.99 2006.133.07:34:40.27#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:34:40.27#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:34:40.27#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:40.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:34:40.27#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:34:40.27#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:34:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:34:40.31#abcon#<5=/16 1.2 2.9 11.331001010.2\r\n> 2006.133.07:34:40.33#abcon#{5=INTERFACE CLEAR} 2006.133.07:34:40.33#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:34:40.33#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:34:40.33#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:34:40.33#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:34:40.33$vc4f8/va=8,6 2006.133.07:34:40.33#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.07:34:40.33#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.07:34:40.33#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:40.33#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:34:40.39#abcon#[5=S1D000X0/0*\r\n] 2006.133.07:34:40.39#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:34:40.39#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:34:40.41#ibcon#[25=AT08-06\r\n] 2006.133.07:34:40.44#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:34:40.44#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:34:40.44#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.07:34:40.44#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:40.44#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:34:40.56#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:34:40.56#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:34:40.58#ibcon#[25=USB\r\n] 2006.133.07:34:40.61#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:34:40.61#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:34:40.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:34:40.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:34:40.61$vc4f8/vblo=1,632.99 2006.133.07:34:40.61#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:34:40.61#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:34:40.61#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:40.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:40.61#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:40.61#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:34:40.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:40.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:34:40.67#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:34:40.67#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:34:40.67$vc4f8/vb=1,4 2006.133.07:34:40.67#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:34:40.67#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:34:40.67#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:40.67#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:40.67#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:40.67#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:40.69#ibcon#[27=AT01-04\r\n] 2006.133.07:34:40.72#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:40.72#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:34:40.72#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:34:40.72#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:40.72#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:40.84#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:40.84#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:40.86#ibcon#[27=USB\r\n] 2006.133.07:34:40.89#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:40.89#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:34:40.89#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:34:40.89#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:34:40.89$vc4f8/vblo=2,640.99 2006.133.07:34:40.89#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:34:40.89#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:34:40.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:40.89#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:40.89#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:40.89#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:34:40.95#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:40.95#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:34:40.95#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:34:40.95#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:34:40.95$vc4f8/vb=2,4 2006.133.07:34:40.95#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:34:40.95#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:34:40.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:40.95#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:41.01#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:41.01#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:41.03#ibcon#[27=AT02-04\r\n] 2006.133.07:34:41.06#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:41.06#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:34:41.06#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:34:41.06#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:41.06#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:41.18#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:41.18#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:41.20#ibcon#[27=USB\r\n] 2006.133.07:34:41.23#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:41.23#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:34:41.23#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:34:41.23#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:34:41.23$vc4f8/vblo=3,656.99 2006.133.07:34:41.23#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:34:41.23#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:34:41.23#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:41.23#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:41.23#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:41.23#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:41.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:34:41.29#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:41.29#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:34:41.29#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:34:41.29#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:34:41.29$vc4f8/vb=3,4 2006.133.07:34:41.29#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:34:41.29#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:34:41.29#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:41.29#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:41.35#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:41.35#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:41.37#ibcon#[27=AT03-04\r\n] 2006.133.07:34:41.40#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:41.40#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:34:41.40#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:34:41.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:41.40#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:41.52#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:41.52#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:41.54#ibcon#[27=USB\r\n] 2006.133.07:34:41.57#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:41.57#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:34:41.57#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:34:41.57#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:34:41.57$vc4f8/vblo=4,712.99 2006.133.07:34:41.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:34:41.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:34:41.57#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:41.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:41.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:41.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:41.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:34:41.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:41.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:34:41.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:34:41.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:34:41.63$vc4f8/vb=4,4 2006.133.07:34:41.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:34:41.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:34:41.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:41.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:41.69#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:41.69#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:41.71#ibcon#[27=AT04-04\r\n] 2006.133.07:34:41.74#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:41.74#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:34:41.74#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:34:41.74#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:41.74#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:41.86#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:41.86#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:41.88#ibcon#[27=USB\r\n] 2006.133.07:34:41.91#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:41.91#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:34:41.91#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:34:41.91#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:34:41.91$vc4f8/vblo=5,744.99 2006.133.07:34:41.91#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:34:41.91#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:34:41.91#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:41.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:41.91#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:41.91#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:41.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:34:41.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:41.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:34:41.97#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:34:41.97#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:34:41.97$vc4f8/vb=5,4 2006.133.07:34:41.97#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:34:41.97#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:34:41.97#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:41.97#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:42.03#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:42.03#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:42.05#ibcon#[27=AT05-04\r\n] 2006.133.07:34:42.08#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:42.08#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:34:42.08#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:42.08#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:42.20#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:42.20#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:42.22#ibcon#[27=USB\r\n] 2006.133.07:34:42.25#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:42.25#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:34:42.25#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:34:42.25#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:34:42.25$vc4f8/vblo=6,752.99 2006.133.07:34:42.25#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:34:42.25#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:34:42.25#ibcon#ireg 17 cls_cnt 0 2006.133.07:34:42.25#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:42.25#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:42.25#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:42.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:34:42.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:42.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:34:42.31#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:34:42.31#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:34:42.31$vc4f8/vb=6,4 2006.133.07:34:42.31#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:34:42.31#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:34:42.31#ibcon#ireg 11 cls_cnt 2 2006.133.07:34:42.31#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:42.37#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:42.37#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:42.39#ibcon#[27=AT06-04\r\n] 2006.133.07:34:42.42#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:42.42#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:34:42.42#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:34:42.42#ibcon#ireg 7 cls_cnt 0 2006.133.07:34:42.42#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:42.54#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:42.54#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:42.56#ibcon#[27=USB\r\n] 2006.133.07:34:42.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:42.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:34:42.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:34:42.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:34:42.61$vc4f8/vabw=wide 2006.133.07:34:42.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:34:42.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:34:42.61#ibcon#ireg 8 cls_cnt 0 2006.133.07:34:42.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:42.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:42.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:42.62#ibcon#[25=BW32\r\n] 2006.133.07:34:42.65#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:42.65#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:34:42.65#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:34:42.65#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:34:42.65$vc4f8/vbbw=wide 2006.133.07:34:42.65#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:34:42.65#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:34:42.65#ibcon#ireg 8 cls_cnt 0 2006.133.07:34:42.65#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:34:42.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:34:42.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:34:42.75#ibcon#[27=BW32\r\n] 2006.133.07:34:42.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:34:42.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:34:42.78#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:34:42.78#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:34:42.78$4f8m12a/ifd4f 2006.133.07:34:42.78$ifd4f/lo= 2006.133.07:34:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:34:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:34:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:34:42.78$ifd4f/patch= 2006.133.07:34:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:34:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:34:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:34:42.78$4f8m12a/"form=m,16.000,1:2 2006.133.07:34:42.78$4f8m12a/"tpicd 2006.133.07:34:42.78$4f8m12a/echo=off 2006.133.07:34:42.78$4f8m12a/xlog=off 2006.133.07:34:42.78:!2006.133.07:35:10 2006.133.07:34:53.14#trakl#Source acquired 2006.133.07:34:55.14#flagr#flagr/antenna,acquired 2006.133.07:35:10.00:preob 2006.133.07:35:11.14/onsource/TRACKING 2006.133.07:35:11.14:!2006.133.07:35:20 2006.133.07:35:20.00:data_valid=on 2006.133.07:35:20.00:midob 2006.133.07:35:20.14/onsource/TRACKING 2006.133.07:35:20.14/wx/11.33,1010.2,100 2006.133.07:35:20.24/cable/+6.5565E-03 2006.133.07:35:21.33/va/01,08,usb,yes,41,43 2006.133.07:35:21.33/va/02,07,usb,yes,41,43 2006.133.07:35:21.33/va/03,06,usb,yes,43,44 2006.133.07:35:21.33/va/04,07,usb,yes,42,45 2006.133.07:35:21.33/va/05,06,usb,yes,48,51 2006.133.07:35:21.33/va/06,05,usb,yes,49,49 2006.133.07:35:21.33/va/07,05,usb,yes,49,49 2006.133.07:35:21.33/va/08,06,usb,yes,46,45 2006.133.07:35:21.56/valo/01,532.99,yes,locked 2006.133.07:35:21.56/valo/02,572.99,yes,locked 2006.133.07:35:21.56/valo/03,672.99,yes,locked 2006.133.07:35:21.56/valo/04,832.99,yes,locked 2006.133.07:35:21.56/valo/05,652.99,yes,locked 2006.133.07:35:21.56/valo/06,772.99,yes,locked 2006.133.07:35:21.56/valo/07,832.99,yes,locked 2006.133.07:35:21.56/valo/08,852.99,yes,locked 2006.133.07:35:22.65/vb/01,04,usb,yes,30,28 2006.133.07:35:22.65/vb/02,04,usb,yes,31,33 2006.133.07:35:22.65/vb/03,04,usb,yes,28,31 2006.133.07:35:22.65/vb/04,04,usb,yes,29,29 2006.133.07:35:22.65/vb/05,04,usb,yes,27,31 2006.133.07:35:22.65/vb/06,04,usb,yes,28,31 2006.133.07:35:22.65/vb/07,04,usb,yes,30,30 2006.133.07:35:22.65/vb/08,04,usb,yes,28,31 2006.133.07:35:22.88/vblo/01,632.99,yes,locked 2006.133.07:35:22.88/vblo/02,640.99,yes,locked 2006.133.07:35:22.88/vblo/03,656.99,yes,locked 2006.133.07:35:22.88/vblo/04,712.99,yes,locked 2006.133.07:35:22.88/vblo/05,744.99,yes,locked 2006.133.07:35:22.88/vblo/06,752.99,yes,locked 2006.133.07:35:22.88/vblo/07,734.99,yes,locked 2006.133.07:35:22.88/vblo/08,744.99,yes,locked 2006.133.07:35:23.03/vabw/8 2006.133.07:35:23.18/vbbw/8 2006.133.07:35:23.27/xfe/off,on,16.5 2006.133.07:35:23.65/ifatt/23,28,28,28 2006.133.07:35:24.08/fmout-gps/S +1.87E-07 2006.133.07:35:24.12:!2006.133.07:36:20 2006.133.07:36:20.00:data_valid=off 2006.133.07:36:20.00:postob 2006.133.07:36:20.12/cable/+6.5561E-03 2006.133.07:36:20.12/wx/11.34,1010.2,100 2006.133.07:36:21.08/fmout-gps/S +1.86E-07 2006.133.07:36:21.08:scan_name=133-0737,k06133,60 2006.133.07:36:21.08:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.133.07:36:21.14#flagr#flagr/antenna,new-source 2006.133.07:36:22.14:checkk5 2006.133.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:36:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:36:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:36:24.00/chk_obsdata//k5ts1/T1330735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:36:24.37/chk_obsdata//k5ts2/T1330735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:36:24.73/chk_obsdata//k5ts3/T1330735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:36:25.10/chk_obsdata//k5ts4/T1330735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:36:25.78/k5log//k5ts1_log_newline 2006.133.07:36:26.46/k5log//k5ts2_log_newline 2006.133.07:36:27.15/k5log//k5ts3_log_newline 2006.133.07:36:27.84/k5log//k5ts4_log_newline 2006.133.07:36:27.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:36:27.86:4f8m12a=1 2006.133.07:36:27.86$4f8m12a/echo=on 2006.133.07:36:27.86$4f8m12a/pcalon 2006.133.07:36:27.86$pcalon/"no phase cal control is implemented here 2006.133.07:36:27.86$4f8m12a/"tpicd=stop 2006.133.07:36:27.86$4f8m12a/vc4f8 2006.133.07:36:27.86$vc4f8/valo=1,532.99 2006.133.07:36:27.86#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.07:36:27.86#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.07:36:27.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:27.86#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:27.86#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:27.86#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:27.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:36:27.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:27.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:27.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:36:27.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:36:27.93$vc4f8/va=1,8 2006.133.07:36:27.93#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.07:36:27.93#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.07:36:27.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:27.93#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:27.93#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:27.93#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:27.95#ibcon#[25=AT01-08\r\n] 2006.133.07:36:27.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:27.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:27.99#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.07:36:27.99#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:27.99#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:28.10#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:28.10#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:28.12#ibcon#[25=USB\r\n] 2006.133.07:36:28.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:28.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:28.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:36:28.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:36:28.17$vc4f8/valo=2,572.99 2006.133.07:36:28.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:36:28.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:36:28.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:28.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:28.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:28.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:28.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:36:28.22#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:28.22#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:28.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:36:28.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:36:28.22$vc4f8/va=2,7 2006.133.07:36:28.22#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.07:36:28.22#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.07:36:28.22#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:28.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:28.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:28.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:28.31#ibcon#[25=AT02-07\r\n] 2006.133.07:36:28.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:28.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:28.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.07:36:28.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:28.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:28.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:28.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:28.48#ibcon#[25=USB\r\n] 2006.133.07:36:28.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:28.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:28.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:36:28.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:36:28.51$vc4f8/valo=3,672.99 2006.133.07:36:28.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:36:28.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:36:28.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:28.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:28.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:28.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:36:28.58#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:28.58#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:28.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:36:28.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:36:28.58$vc4f8/va=3,6 2006.133.07:36:28.58#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:36:28.58#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:36:28.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:28.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:28.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:28.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:28.65#ibcon#[25=AT03-06\r\n] 2006.133.07:36:28.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:28.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:28.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:36:28.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:28.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:28.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:28.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:28.82#ibcon#[25=USB\r\n] 2006.133.07:36:28.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:28.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:28.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:36:28.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:36:28.85$vc4f8/valo=4,832.99 2006.133.07:36:28.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:36:28.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:36:28.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:28.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:28.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:28.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:28.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:36:28.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:28.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:28.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:36:28.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:36:28.91$vc4f8/va=4,7 2006.133.07:36:28.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:36:28.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:36:28.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:28.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:28.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:28.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:28.99#ibcon#[25=AT04-07\r\n] 2006.133.07:36:29.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:29.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:29.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:36:29.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:29.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:29.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:29.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:29.16#ibcon#[25=USB\r\n] 2006.133.07:36:29.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:29.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:29.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:36:29.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:36:29.19$vc4f8/valo=5,652.99 2006.133.07:36:29.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:36:29.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:36:29.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:29.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:29.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:29.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:29.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:36:29.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:29.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:29.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:36:29.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:36:29.25$vc4f8/va=5,6 2006.133.07:36:29.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:36:29.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:36:29.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:29.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:29.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:29.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:29.33#ibcon#[25=AT05-06\r\n] 2006.133.07:36:29.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:29.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:29.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:36:29.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:29.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:29.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:29.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:29.50#ibcon#[25=USB\r\n] 2006.133.07:36:29.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:29.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:29.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:36:29.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:36:29.53$vc4f8/valo=6,772.99 2006.133.07:36:29.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:36:29.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:36:29.53#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:29.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:29.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:29.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:29.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:36:29.59#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:29.59#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:29.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:36:29.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:36:29.59$vc4f8/va=6,5 2006.133.07:36:29.59#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:36:29.59#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:36:29.59#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:29.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:29.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:29.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:29.67#ibcon#[25=AT06-05\r\n] 2006.133.07:36:29.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:29.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:29.70#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:36:29.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:29.70#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:36:29.82#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:36:29.82#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:36:29.84#ibcon#[25=USB\r\n] 2006.133.07:36:29.87#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:36:29.87#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:36:29.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:36:29.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:36:29.87$vc4f8/valo=7,832.99 2006.133.07:36:29.87#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:36:29.87#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:36:29.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:29.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:36:29.87#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:36:29.87#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:36:29.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:36:29.93#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:36:29.93#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:36:29.93#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:36:29.93#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:36:29.93$vc4f8/va=7,5 2006.133.07:36:29.93#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:36:29.93#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:36:29.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:29.93#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:36:29.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:36:29.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:36:30.01#ibcon#[25=AT07-05\r\n] 2006.133.07:36:30.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:36:30.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:36:30.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:36:30.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:30.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:36:30.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:36:30.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:36:30.18#ibcon#[25=USB\r\n] 2006.133.07:36:30.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:36:30.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:36:30.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:36:30.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:36:30.21$vc4f8/valo=8,852.99 2006.133.07:36:30.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:36:30.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:36:30.21#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:30.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:36:30.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:36:30.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:36:30.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:36:30.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:36:30.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:36:30.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:36:30.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:36:30.27$vc4f8/va=8,6 2006.133.07:36:30.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:36:30.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:36:30.27#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:30.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:36:30.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:36:30.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:36:30.35#ibcon#[25=AT08-06\r\n] 2006.133.07:36:30.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:36:30.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:36:30.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:36:30.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:30.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:36:30.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:36:30.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:36:30.52#ibcon#[25=USB\r\n] 2006.133.07:36:30.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:36:30.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:36:30.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:36:30.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:36:30.55$vc4f8/vblo=1,632.99 2006.133.07:36:30.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:36:30.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:36:30.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:30.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:36:30.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:36:30.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:36:30.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:36:30.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:36:30.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:36:30.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:36:30.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:36:30.61$vc4f8/vb=1,4 2006.133.07:36:30.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.07:36:30.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.07:36:30.61#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:30.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:36:30.61#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:36:30.61#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:36:30.63#ibcon#[27=AT01-04\r\n] 2006.133.07:36:30.66#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:36:30.66#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:36:30.66#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.07:36:30.66#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:30.66#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:36:30.78#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:36:30.78#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:36:30.80#ibcon#[27=USB\r\n] 2006.133.07:36:30.83#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:36:30.83#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:36:30.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:36:30.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:36:30.83$vc4f8/vblo=2,640.99 2006.133.07:36:30.83#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.07:36:30.83#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.07:36:30.83#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:30.83#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:30.83#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:30.83#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:30.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:36:30.89#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:30.89#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:36:30.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:36:30.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:36:30.89$vc4f8/vb=2,4 2006.133.07:36:30.89#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.07:36:30.89#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.07:36:30.89#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:30.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:30.95#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:30.95#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:30.97#ibcon#[27=AT02-04\r\n] 2006.133.07:36:31.00#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:31.00#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:36:31.00#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.07:36:31.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:31.00#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:31.12#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:31.12#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:31.14#ibcon#[27=USB\r\n] 2006.133.07:36:31.17#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:31.17#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:36:31.17#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:36:31.17#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:36:31.17$vc4f8/vblo=3,656.99 2006.133.07:36:31.17#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:36:31.17#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:36:31.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:31.17#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:31.17#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:31.17#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:31.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:36:31.23#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:31.23#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:36:31.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:36:31.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:36:31.23$vc4f8/vb=3,4 2006.133.07:36:31.23#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.07:36:31.23#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.07:36:31.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:31.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:31.29#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:31.29#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:31.31#ibcon#[27=AT03-04\r\n] 2006.133.07:36:31.34#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:31.34#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:36:31.34#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.07:36:31.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:31.34#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:31.46#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:31.46#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:31.48#ibcon#[27=USB\r\n] 2006.133.07:36:31.51#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:31.51#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:36:31.51#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:36:31.51#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:36:31.51$vc4f8/vblo=4,712.99 2006.133.07:36:31.51#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:36:31.51#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:36:31.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:31.51#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:31.51#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:31.51#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:31.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:36:31.57#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:31.57#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:36:31.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:36:31.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:36:31.57$vc4f8/vb=4,4 2006.133.07:36:31.57#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:36:31.57#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:36:31.57#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:31.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:31.63#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:31.63#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:31.65#ibcon#[27=AT04-04\r\n] 2006.133.07:36:31.68#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:31.68#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:36:31.68#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:36:31.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:31.68#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:31.80#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:31.80#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:31.82#ibcon#[27=USB\r\n] 2006.133.07:36:31.85#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:31.85#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:36:31.85#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:36:31.85#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:36:31.85$vc4f8/vblo=5,744.99 2006.133.07:36:31.85#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:36:31.85#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:36:31.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:31.85#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:31.85#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:31.85#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:31.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:36:31.91#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:31.91#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:36:31.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:36:31.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:36:31.91$vc4f8/vb=5,4 2006.133.07:36:31.91#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:36:31.91#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:36:31.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:31.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:31.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:31.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:31.99#ibcon#[27=AT05-04\r\n] 2006.133.07:36:32.02#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:32.02#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:36:32.02#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:36:32.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:32.02#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:32.14#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:32.14#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:32.16#ibcon#[27=USB\r\n] 2006.133.07:36:32.19#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:32.19#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:36:32.19#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:36:32.19#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:36:32.19$vc4f8/vblo=6,752.99 2006.133.07:36:32.19#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:36:32.19#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:36:32.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:36:32.19#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:32.19#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:32.19#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:32.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:36:32.25#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:32.25#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:36:32.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:36:32.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:36:32.25$vc4f8/vb=6,4 2006.133.07:36:32.25#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:36:32.25#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:36:32.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:36:32.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:32.31#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:32.31#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:32.33#ibcon#[27=AT06-04\r\n] 2006.133.07:36:32.36#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:32.36#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:36:32.36#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:36:32.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:36:32.36#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:32.48#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:32.48#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:32.50#ibcon#[27=USB\r\n] 2006.133.07:36:32.53#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:32.53#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:36:32.53#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:36:32.53#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:36:32.53$vc4f8/vabw=wide 2006.133.07:36:32.53#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:36:32.53#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:36:32.53#ibcon#ireg 8 cls_cnt 0 2006.133.07:36:32.53#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:32.53#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:32.53#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:32.55#ibcon#[25=BW32\r\n] 2006.133.07:36:32.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:32.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:36:32.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:36:32.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:36:32.58$vc4f8/vbbw=wide 2006.133.07:36:32.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:36:32.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:36:32.58#ibcon#ireg 8 cls_cnt 0 2006.133.07:36:32.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:36:32.65#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:36:32.65#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:36:32.67#ibcon#[27=BW32\r\n] 2006.133.07:36:32.70#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:36:32.70#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:36:32.70#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:36:32.70#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:36:32.70$4f8m12a/ifd4f 2006.133.07:36:32.70$ifd4f/lo= 2006.133.07:36:32.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:36:32.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:36:32.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:36:32.70$ifd4f/patch= 2006.133.07:36:32.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:36:32.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:36:32.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:36:32.70$4f8m12a/"form=m,16.000,1:2 2006.133.07:36:32.70$4f8m12a/"tpicd 2006.133.07:36:32.70$4f8m12a/echo=off 2006.133.07:36:32.70$4f8m12a/xlog=off 2006.133.07:36:32.70:!2006.133.07:37:00 2006.133.07:36:43.14#trakl#Source acquired 2006.133.07:36:45.14#flagr#flagr/antenna,acquired 2006.133.07:37:00.00:preob 2006.133.07:37:01.14/onsource/TRACKING 2006.133.07:37:01.14:!2006.133.07:37:10 2006.133.07:37:10.00:data_valid=on 2006.133.07:37:10.00:midob 2006.133.07:37:10.14/onsource/TRACKING 2006.133.07:37:10.14/wx/11.35,1010.2,100 2006.133.07:37:10.29/cable/+6.5573E-03 2006.133.07:37:11.38/va/01,08,usb,yes,45,47 2006.133.07:37:11.38/va/02,07,usb,yes,45,47 2006.133.07:37:11.38/va/03,06,usb,yes,48,48 2006.133.07:37:11.38/va/04,07,usb,yes,46,49 2006.133.07:37:11.38/va/05,06,usb,yes,53,57 2006.133.07:37:11.38/va/06,05,usb,yes,55,54 2006.133.07:37:11.38/va/07,05,usb,yes,54,54 2006.133.07:37:11.38/va/08,06,usb,yes,51,50 2006.133.07:37:11.61/valo/01,532.99,yes,locked 2006.133.07:37:11.61/valo/02,572.99,yes,locked 2006.133.07:37:11.61/valo/03,672.99,yes,locked 2006.133.07:37:11.61/valo/04,832.99,yes,locked 2006.133.07:37:11.61/valo/05,652.99,yes,locked 2006.133.07:37:11.61/valo/06,772.99,yes,locked 2006.133.07:37:11.61/valo/07,832.99,yes,locked 2006.133.07:37:11.61/valo/08,852.99,yes,locked 2006.133.07:37:12.70/vb/01,04,usb,yes,30,29 2006.133.07:37:12.70/vb/02,04,usb,yes,32,33 2006.133.07:37:12.70/vb/03,04,usb,yes,28,32 2006.133.07:37:12.70/vb/04,04,usb,yes,29,29 2006.133.07:37:12.70/vb/05,04,usb,yes,27,31 2006.133.07:37:12.70/vb/06,04,usb,yes,29,31 2006.133.07:37:12.70/vb/07,04,usb,yes,31,30 2006.133.07:37:12.70/vb/08,04,usb,yes,28,31 2006.133.07:37:12.93/vblo/01,632.99,yes,locked 2006.133.07:37:12.93/vblo/02,640.99,yes,locked 2006.133.07:37:12.93/vblo/03,656.99,yes,locked 2006.133.07:37:12.93/vblo/04,712.99,yes,locked 2006.133.07:37:12.93/vblo/05,744.99,yes,locked 2006.133.07:37:12.93/vblo/06,752.99,yes,locked 2006.133.07:37:12.93/vblo/07,734.99,yes,locked 2006.133.07:37:12.93/vblo/08,744.99,yes,locked 2006.133.07:37:13.08/vabw/8 2006.133.07:37:13.23/vbbw/8 2006.133.07:37:13.32/xfe/off,on,15.0 2006.133.07:37:13.69/ifatt/23,28,28,28 2006.133.07:37:14.08/fmout-gps/S +1.86E-07 2006.133.07:37:14.12:!2006.133.07:38:10 2006.133.07:38:10.00:data_valid=off 2006.133.07:38:10.00:postob 2006.133.07:38:10.21/cable/+6.5589E-03 2006.133.07:38:10.21/wx/11.37,1010.1,100 2006.133.07:38:11.08/fmout-gps/S +1.87E-07 2006.133.07:38:11.08:scan_name=133-0739,k06133,60 2006.133.07:38:11.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.133.07:38:11.16#flagr#flagr/antenna,new-source 2006.133.07:38:12.14:checkk5 2006.133.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:38:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:38:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:38:13.99/chk_obsdata//k5ts1/T1330737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:38:14.36/chk_obsdata//k5ts2/T1330737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:38:14.72/chk_obsdata//k5ts3/T1330737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:38:15.09/chk_obsdata//k5ts4/T1330737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:38:15.78/k5log//k5ts1_log_newline 2006.133.07:38:16.46/k5log//k5ts2_log_newline 2006.133.07:38:17.15/k5log//k5ts3_log_newline 2006.133.07:38:17.84/k5log//k5ts4_log_newline 2006.133.07:38:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:38:17.86:4f8m12a=1 2006.133.07:38:17.86$4f8m12a/echo=on 2006.133.07:38:17.86$4f8m12a/pcalon 2006.133.07:38:17.86$pcalon/"no phase cal control is implemented here 2006.133.07:38:17.86$4f8m12a/"tpicd=stop 2006.133.07:38:17.86$4f8m12a/vc4f8 2006.133.07:38:17.86$vc4f8/valo=1,532.99 2006.133.07:38:17.86#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:38:17.86#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:38:17.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:17.86#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:17.86#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:17.86#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:17.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:38:17.93#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:17.93#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:17.93#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:38:17.93#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:38:17.93$vc4f8/va=1,8 2006.133.07:38:17.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.07:38:17.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.07:38:17.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:17.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:17.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:17.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:17.95#ibcon#[25=AT01-08\r\n] 2006.133.07:38:17.98#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:17.98#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:17.98#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.07:38:17.98#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:17.98#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:18.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:18.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:18.12#ibcon#[25=USB\r\n] 2006.133.07:38:18.16#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:18.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:18.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:38:18.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:38:18.17$vc4f8/valo=2,572.99 2006.133.07:38:18.17#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:38:18.17#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:38:18.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:18.17#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:18.17#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:18.17#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:18.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:38:18.22#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:18.22#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:18.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:38:18.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:38:18.22$vc4f8/va=2,7 2006.133.07:38:18.22#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.07:38:18.22#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.07:38:18.22#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:18.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:18.29#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:18.29#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:18.31#ibcon#[25=AT02-07\r\n] 2006.133.07:38:18.34#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:18.34#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:18.34#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.07:38:18.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:18.34#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:18.46#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:18.46#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:18.48#ibcon#[25=USB\r\n] 2006.133.07:38:18.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:18.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:18.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:38:18.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:38:18.52$vc4f8/valo=3,672.99 2006.133.07:38:18.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:38:18.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:38:18.52#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:18.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:18.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:18.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:18.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:38:18.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:18.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:18.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:38:18.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:38:18.58$vc4f8/va=3,6 2006.133.07:38:18.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.07:38:18.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.07:38:18.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:18.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:18.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:18.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:18.66#ibcon#[25=AT03-06\r\n] 2006.133.07:38:18.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:18.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:18.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.07:38:18.69#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:18.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:18.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:18.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:18.83#ibcon#[25=USB\r\n] 2006.133.07:38:18.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:18.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:18.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:38:18.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:38:18.86$vc4f8/valo=4,832.99 2006.133.07:38:18.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.07:38:18.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.07:38:18.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:18.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:18.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:18.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:18.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:38:18.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:18.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:18.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:38:18.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:38:18.92$vc4f8/va=4,7 2006.133.07:38:18.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.07:38:18.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.07:38:18.92#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:18.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:18.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:18.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:19.00#ibcon#[25=AT04-07\r\n] 2006.133.07:38:19.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:19.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:19.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.07:38:19.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:19.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:19.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:19.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:19.17#ibcon#[25=USB\r\n] 2006.133.07:38:19.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:19.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:19.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:38:19.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:38:19.20$vc4f8/valo=5,652.99 2006.133.07:38:19.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.07:38:19.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.07:38:19.20#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:19.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:19.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:19.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:19.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:38:19.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:19.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:19.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:38:19.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:38:19.26$vc4f8/va=5,6 2006.133.07:38:19.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.07:38:19.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.07:38:19.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:19.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:19.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:19.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:19.34#ibcon#[25=AT05-06\r\n] 2006.133.07:38:19.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:19.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:19.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.07:38:19.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:19.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:19.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:19.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:19.51#ibcon#[25=USB\r\n] 2006.133.07:38:19.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:19.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:19.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:38:19.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:38:19.54$vc4f8/valo=6,772.99 2006.133.07:38:19.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:38:19.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:38:19.54#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:19.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:19.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:19.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:19.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:38:19.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:19.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:19.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:38:19.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:38:19.60$vc4f8/va=6,5 2006.133.07:38:19.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.07:38:19.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.07:38:19.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:19.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:19.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:19.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:19.68#ibcon#[25=AT06-05\r\n] 2006.133.07:38:19.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:19.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:19.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.07:38:19.71#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:19.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:38:19.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:38:19.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:38:19.85#ibcon#[25=USB\r\n] 2006.133.07:38:19.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:38:19.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:38:19.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:38:19.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:38:19.88$vc4f8/valo=7,832.99 2006.133.07:38:19.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.07:38:19.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.07:38:19.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:19.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:38:19.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:38:19.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:38:19.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:38:19.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:38:19.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:38:19.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:38:19.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:38:19.94$vc4f8/va=7,5 2006.133.07:38:19.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.07:38:19.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.07:38:19.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:19.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:38:20.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:38:20.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:38:20.02#ibcon#[25=AT07-05\r\n] 2006.133.07:38:20.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:38:20.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:38:20.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.07:38:20.05#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:20.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:38:20.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:38:20.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:38:20.19#ibcon#[25=USB\r\n] 2006.133.07:38:20.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:38:20.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:38:20.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:38:20.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:38:20.22$vc4f8/valo=8,852.99 2006.133.07:38:20.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.07:38:20.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.07:38:20.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:20.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:38:20.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:38:20.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:38:20.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:38:20.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:38:20.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:38:20.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:38:20.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:38:20.28$vc4f8/va=8,6 2006.133.07:38:20.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.07:38:20.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.07:38:20.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:20.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:38:20.35#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:38:20.35#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:38:20.37#ibcon#[25=AT08-06\r\n] 2006.133.07:38:20.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:38:20.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:38:20.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.07:38:20.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:20.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:38:20.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:38:20.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:38:20.54#ibcon#[25=USB\r\n] 2006.133.07:38:20.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:38:20.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:38:20.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:38:20.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:38:20.57$vc4f8/vblo=1,632.99 2006.133.07:38:20.57#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.07:38:20.57#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.07:38:20.57#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:20.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:38:20.57#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:38:20.57#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:38:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:38:20.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:38:20.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:38:20.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:38:20.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:38:20.63$vc4f8/vb=1,4 2006.133.07:38:20.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.07:38:20.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.07:38:20.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:20.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:38:20.63#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:38:20.63#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:38:20.65#ibcon#[27=AT01-04\r\n] 2006.133.07:38:20.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:38:20.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:38:20.68#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.07:38:20.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:20.68#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:38:20.80#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:38:20.80#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:38:20.82#ibcon#[27=USB\r\n] 2006.133.07:38:20.85#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:38:20.85#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:38:20.85#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:38:20.85#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:38:20.85$vc4f8/vblo=2,640.99 2006.133.07:38:20.85#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:38:20.85#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:38:20.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:20.85#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:20.85#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:20.85#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:20.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:38:20.91#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:20.91#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:38:20.91#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:38:20.91#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:38:20.91$vc4f8/vb=2,4 2006.133.07:38:20.91#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.07:38:20.91#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.07:38:20.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:20.91#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:20.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:20.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:20.99#ibcon#[27=AT02-04\r\n] 2006.133.07:38:21.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:21.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:38:21.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.07:38:21.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:21.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:21.14#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:21.14#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:21.16#ibcon#[27=USB\r\n] 2006.133.07:38:21.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:21.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:38:21.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:38:21.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:38:21.19$vc4f8/vblo=3,656.99 2006.133.07:38:21.19#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:38:21.19#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:38:21.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:21.19#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:21.19#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:21.19#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:38:21.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:21.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:38:21.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:38:21.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:38:21.25$vc4f8/vb=3,4 2006.133.07:38:21.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.07:38:21.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.07:38:21.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:21.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:21.31#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:21.31#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:21.33#ibcon#[27=AT03-04\r\n] 2006.133.07:38:21.36#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:21.36#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:38:21.36#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.07:38:21.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:21.36#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:21.48#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:21.48#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:21.50#ibcon#[27=USB\r\n] 2006.133.07:38:21.53#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:21.53#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:38:21.53#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:38:21.53#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:38:21.53$vc4f8/vblo=4,712.99 2006.133.07:38:21.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:38:21.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:38:21.53#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:21.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:21.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:21.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:21.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:38:21.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:21.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:38:21.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:38:21.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:38:21.59$vc4f8/vb=4,4 2006.133.07:38:21.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.07:38:21.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.07:38:21.59#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:21.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:21.65#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:21.65#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:21.67#ibcon#[27=AT04-04\r\n] 2006.133.07:38:21.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:21.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:38:21.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.07:38:21.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:21.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:21.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:21.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:21.84#ibcon#[27=USB\r\n] 2006.133.07:38:21.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:21.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:38:21.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:38:21.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:38:21.87$vc4f8/vblo=5,744.99 2006.133.07:38:21.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.07:38:21.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.07:38:21.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:21.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:21.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:21.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:21.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:38:21.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:21.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:38:21.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:38:21.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:38:21.95$vc4f8/vb=5,4 2006.133.07:38:21.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.07:38:21.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.07:38:21.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:21.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:21.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:21.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:22.01#ibcon#[27=AT05-04\r\n] 2006.133.07:38:22.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:22.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:38:22.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.07:38:22.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:22.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:22.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:22.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:22.18#ibcon#[27=USB\r\n] 2006.133.07:38:22.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:22.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:38:22.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:38:22.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:38:22.21$vc4f8/vblo=6,752.99 2006.133.07:38:22.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.07:38:22.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.07:38:22.21#ibcon#ireg 17 cls_cnt 0 2006.133.07:38:22.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:22.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:22.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:22.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:38:22.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:22.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:38:22.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:38:22.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:38:22.27$vc4f8/vb=6,4 2006.133.07:38:22.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.07:38:22.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.07:38:22.27#ibcon#ireg 11 cls_cnt 2 2006.133.07:38:22.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:22.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:22.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:22.35#ibcon#[27=AT06-04\r\n] 2006.133.07:38:22.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:22.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:38:22.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.07:38:22.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:38:22.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:22.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:22.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:22.52#ibcon#[27=USB\r\n] 2006.133.07:38:22.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:22.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:38:22.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:38:22.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:38:22.55$vc4f8/vabw=wide 2006.133.07:38:22.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:38:22.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:38:22.55#ibcon#ireg 8 cls_cnt 0 2006.133.07:38:22.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:22.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:22.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:22.57#ibcon#[25=BW32\r\n] 2006.133.07:38:22.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:22.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:38:22.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:38:22.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:38:22.60$vc4f8/vbbw=wide 2006.133.07:38:22.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:38:22.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:38:22.60#ibcon#ireg 8 cls_cnt 0 2006.133.07:38:22.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:38:22.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:38:22.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:38:22.69#ibcon#[27=BW32\r\n] 2006.133.07:38:22.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:38:22.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:38:22.72#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:38:22.72#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:38:22.72$4f8m12a/ifd4f 2006.133.07:38:22.72$ifd4f/lo= 2006.133.07:38:22.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:38:22.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:38:22.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:38:22.72$ifd4f/patch= 2006.133.07:38:22.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:38:22.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:38:22.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:38:22.72$4f8m12a/"form=m,16.000,1:2 2006.133.07:38:22.72$4f8m12a/"tpicd 2006.133.07:38:22.72$4f8m12a/echo=off 2006.133.07:38:22.72$4f8m12a/xlog=off 2006.133.07:38:22.72:!2006.133.07:38:50 2006.133.07:38:26.14#trakl#Source acquired 2006.133.07:38:26.14#flagr#flagr/antenna,acquired 2006.133.07:38:50.00:preob 2006.133.07:38:51.14/onsource/TRACKING 2006.133.07:38:51.14:!2006.133.07:39:00 2006.133.07:39:00.00:data_valid=on 2006.133.07:39:00.00:midob 2006.133.07:39:00.14/onsource/TRACKING 2006.133.07:39:00.14/wx/11.37,1010.0,100 2006.133.07:39:00.34/cable/+6.5573E-03 2006.133.07:39:01.43/va/01,08,usb,yes,46,49 2006.133.07:39:01.43/va/02,07,usb,yes,47,49 2006.133.07:39:01.43/va/03,06,usb,yes,49,50 2006.133.07:39:01.43/va/04,07,usb,yes,48,51 2006.133.07:39:01.43/va/05,06,usb,yes,55,59 2006.133.07:39:01.43/va/06,05,usb,yes,57,56 2006.133.07:39:01.43/va/07,05,usb,yes,57,56 2006.133.07:39:01.43/va/08,06,usb,yes,53,52 2006.133.07:39:01.66/valo/01,532.99,yes,locked 2006.133.07:39:01.66/valo/02,572.99,yes,locked 2006.133.07:39:01.66/valo/03,672.99,yes,locked 2006.133.07:39:01.66/valo/04,832.99,yes,locked 2006.133.07:39:01.66/valo/05,652.99,yes,locked 2006.133.07:39:01.66/valo/06,772.99,yes,locked 2006.133.07:39:01.66/valo/07,832.99,yes,locked 2006.133.07:39:01.66/valo/08,852.99,yes,locked 2006.133.07:39:02.75/vb/01,04,usb,yes,30,29 2006.133.07:39:02.75/vb/02,04,usb,yes,32,33 2006.133.07:39:02.75/vb/03,04,usb,yes,28,32 2006.133.07:39:02.75/vb/04,04,usb,yes,29,29 2006.133.07:39:02.75/vb/05,04,usb,yes,28,32 2006.133.07:39:02.75/vb/06,04,usb,yes,29,32 2006.133.07:39:02.75/vb/07,04,usb,yes,31,31 2006.133.07:39:02.75/vb/08,04,usb,yes,28,32 2006.133.07:39:02.98/vblo/01,632.99,yes,locked 2006.133.07:39:02.98/vblo/02,640.99,yes,locked 2006.133.07:39:02.98/vblo/03,656.99,yes,locked 2006.133.07:39:02.98/vblo/04,712.99,yes,locked 2006.133.07:39:02.98/vblo/05,744.99,yes,locked 2006.133.07:39:02.98/vblo/06,752.99,yes,locked 2006.133.07:39:02.98/vblo/07,734.99,yes,locked 2006.133.07:39:02.98/vblo/08,744.99,yes,locked 2006.133.07:39:03.13/vabw/8 2006.133.07:39:03.28/vbbw/8 2006.133.07:39:03.37/xfe/off,on,15.2 2006.133.07:39:03.75/ifatt/23,28,28,28 2006.133.07:39:04.08/fmout-gps/S +1.86E-07 2006.133.07:39:04.12:!2006.133.07:40:00 2006.133.07:40:00.01:data_valid=off 2006.133.07:40:00.01:postob 2006.133.07:40:00.25/cable/+6.5592E-03 2006.133.07:40:00.25/wx/11.38,1010.0,100 2006.133.07:40:01.08/fmout-gps/S +1.86E-07 2006.133.07:40:01.08:scan_name=133-0741,k06133,60 2006.133.07:40:01.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.133.07:40:01.13#flagr#flagr/antenna,new-source 2006.133.07:40:02.13:checkk5 2006.133.07:40:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:40:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:40:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:40:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:40:03.99/chk_obsdata//k5ts1/T1330739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:40:04.37/chk_obsdata//k5ts2/T1330739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:40:04.73/chk_obsdata//k5ts3/T1330739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:40:05.10/chk_obsdata//k5ts4/T1330739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:40:05.78/k5log//k5ts1_log_newline 2006.133.07:40:06.47/k5log//k5ts2_log_newline 2006.133.07:40:07.15/k5log//k5ts3_log_newline 2006.133.07:40:07.84/k5log//k5ts4_log_newline 2006.133.07:40:07.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:40:07.86:4f8m12a=1 2006.133.07:40:07.86$4f8m12a/echo=on 2006.133.07:40:07.86$4f8m12a/pcalon 2006.133.07:40:07.86$pcalon/"no phase cal control is implemented here 2006.133.07:40:07.86$4f8m12a/"tpicd=stop 2006.133.07:40:07.86$4f8m12a/vc4f8 2006.133.07:40:07.86$vc4f8/valo=1,532.99 2006.133.07:40:07.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:40:07.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:40:07.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:07.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:07.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:07.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:07.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:40:07.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:07.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:07.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:40:07.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:40:07.93$vc4f8/va=1,8 2006.133.07:40:07.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:40:07.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:40:07.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:07.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:07.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:07.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:07.95#ibcon#[25=AT01-08\r\n] 2006.133.07:40:07.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:07.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:07.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:40:07.98#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:07.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:08.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:08.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:08.12#ibcon#[25=USB\r\n] 2006.133.07:40:08.16#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:08.16#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:08.16#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:40:08.16#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:40:08.16$vc4f8/valo=2,572.99 2006.133.07:40:08.16#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:40:08.16#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:40:08.16#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:08.16#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:08.16#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:08.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:08.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:40:08.22#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:08.22#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:08.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:40:08.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:40:08.22$vc4f8/va=2,7 2006.133.07:40:08.22#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:40:08.22#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:40:08.22#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:08.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:08.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:08.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:08.30#ibcon#[25=AT02-07\r\n] 2006.133.07:40:08.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:08.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:08.33#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:40:08.33#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:08.33#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:08.45#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:08.45#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:08.47#ibcon#[25=USB\r\n] 2006.133.07:40:08.50#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:08.50#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:08.50#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:40:08.50#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:40:08.50$vc4f8/valo=3,672.99 2006.133.07:40:08.50#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:40:08.50#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:40:08.50#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:08.50#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:08.50#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:08.50#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:08.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:40:08.57#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:08.57#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:08.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:40:08.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:40:08.57$vc4f8/va=3,6 2006.133.07:40:08.57#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.07:40:08.57#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.07:40:08.57#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:08.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:40:08.59#abcon#<5=/01 1.0 2.9 11.381001010.0\r\n> 2006.133.07:40:08.61#abcon#{5=INTERFACE CLEAR} 2006.133.07:40:08.62#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:40:08.62#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:40:08.64#ibcon#[25=AT03-06\r\n] 2006.133.07:40:08.67#abcon#[5=S1D000X0/0*\r\n] 2006.133.07:40:08.67#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:40:08.67#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:40:08.67#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.07:40:08.67#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:08.67#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:40:08.79#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:40:08.79#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:40:08.81#ibcon#[25=USB\r\n] 2006.133.07:40:08.84#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:40:08.84#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:40:08.84#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:40:08.84#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:40:08.84$vc4f8/valo=4,832.99 2006.133.07:40:08.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.07:40:08.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.07:40:08.84#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:08.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:08.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:08.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:08.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:40:08.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:08.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:08.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:40:08.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:40:08.90$vc4f8/va=4,7 2006.133.07:40:08.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.07:40:08.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.07:40:08.90#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:08.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:08.96#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:08.96#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:08.98#ibcon#[25=AT04-07\r\n] 2006.133.07:40:09.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:09.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:09.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.07:40:09.01#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:09.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:09.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:09.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:09.15#ibcon#[25=USB\r\n] 2006.133.07:40:09.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:09.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:09.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:40:09.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:40:09.18$vc4f8/valo=5,652.99 2006.133.07:40:09.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:40:09.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:40:09.18#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:09.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:09.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:09.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:09.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:40:09.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:09.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:09.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:40:09.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:40:09.24$vc4f8/va=5,6 2006.133.07:40:09.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:40:09.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:40:09.24#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:09.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:09.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:09.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:09.32#ibcon#[25=AT05-06\r\n] 2006.133.07:40:09.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:09.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:09.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:40:09.35#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:09.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:09.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:09.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:09.49#ibcon#[25=USB\r\n] 2006.133.07:40:09.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:09.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:09.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:40:09.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:40:09.52$vc4f8/valo=6,772.99 2006.133.07:40:09.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:40:09.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:40:09.52#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:09.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:09.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:09.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:09.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:40:09.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:09.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:09.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:40:09.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:40:09.58$vc4f8/va=6,5 2006.133.07:40:09.58#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.07:40:09.58#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.07:40:09.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:09.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:09.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:09.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:09.66#ibcon#[25=AT06-05\r\n] 2006.133.07:40:09.69#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:09.69#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:09.69#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.07:40:09.69#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:09.69#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:40:09.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:40:09.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:40:09.83#ibcon#[25=USB\r\n] 2006.133.07:40:09.86#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:40:09.86#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:40:09.86#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:40:09.86#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:40:09.86$vc4f8/valo=7,832.99 2006.133.07:40:09.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:40:09.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:40:09.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:09.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:40:09.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:40:09.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:40:09.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:40:09.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:40:09.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:40:09.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:40:09.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:40:09.92$vc4f8/va=7,5 2006.133.07:40:09.92#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:40:09.92#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:40:09.92#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:09.92#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:40:09.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:40:09.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:40:10.00#ibcon#[25=AT07-05\r\n] 2006.133.07:40:10.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:40:10.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:40:10.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:40:10.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:10.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:40:10.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:40:10.15#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:40:10.17#ibcon#[25=USB\r\n] 2006.133.07:40:10.20#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:40:10.20#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:40:10.20#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:40:10.20#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:40:10.20$vc4f8/valo=8,852.99 2006.133.07:40:10.20#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:40:10.20#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:40:10.20#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:10.20#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:40:10.20#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:40:10.20#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:40:10.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:40:10.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:40:10.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:40:10.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:40:10.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:40:10.26$vc4f8/va=8,6 2006.133.07:40:10.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:40:10.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:40:10.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:10.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:40:10.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:40:10.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:40:10.34#ibcon#[25=AT08-06\r\n] 2006.133.07:40:10.37#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:40:10.37#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:40:10.37#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:40:10.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:10.37#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:40:10.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:40:10.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:40:10.51#ibcon#[25=USB\r\n] 2006.133.07:40:10.54#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:40:10.54#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:40:10.54#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:40:10.54#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:40:10.54$vc4f8/vblo=1,632.99 2006.133.07:40:10.54#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:40:10.54#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:40:10.54#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:10.54#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:10.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:10.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:10.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:40:10.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:10.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:40:10.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:40:10.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:40:10.60$vc4f8/vb=1,4 2006.133.07:40:10.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:40:10.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:40:10.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:10.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:10.60#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:10.60#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:10.62#ibcon#[27=AT01-04\r\n] 2006.133.07:40:10.65#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:10.65#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:40:10.65#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:40:10.65#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:10.65#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:10.77#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:10.77#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:10.79#ibcon#[27=USB\r\n] 2006.133.07:40:10.82#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:10.82#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:40:10.82#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:40:10.82#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:40:10.82$vc4f8/vblo=2,640.99 2006.133.07:40:10.82#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:40:10.82#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:40:10.82#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:10.82#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:10.82#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:10.82#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:10.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:40:10.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:10.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:40:10.88#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:40:10.88#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:40:10.88$vc4f8/vb=2,4 2006.133.07:40:10.88#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:40:10.88#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:40:10.88#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:10.88#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:10.94#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:10.94#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:10.96#ibcon#[27=AT02-04\r\n] 2006.133.07:40:11.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:11.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:40:11.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:40:11.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:11.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:11.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:11.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:11.14#ibcon#[27=USB\r\n] 2006.133.07:40:11.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:11.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:40:11.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:40:11.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:40:11.17$vc4f8/vblo=3,656.99 2006.133.07:40:11.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:40:11.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:40:11.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:11.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:11.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:11.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:11.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:40:11.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:11.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:40:11.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:40:11.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:40:11.23$vc4f8/vb=3,4 2006.133.07:40:11.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:40:11.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:40:11.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:11.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:40:11.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:40:11.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:40:11.31#ibcon#[27=AT03-04\r\n] 2006.133.07:40:11.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:40:11.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:40:11.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:40:11.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:11.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:40:11.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:40:11.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:40:11.48#ibcon#[27=USB\r\n] 2006.133.07:40:11.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:40:11.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:40:11.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:40:11.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:40:11.51$vc4f8/vblo=4,712.99 2006.133.07:40:11.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:40:11.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:40:11.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:11.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:40:11.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:40:11.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:40:11.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:40:11.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:40:11.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:40:11.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:40:11.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:40:11.57$vc4f8/vb=4,4 2006.133.07:40:11.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.07:40:11.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.07:40:11.57#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:11.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:40:11.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:40:11.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:40:11.65#ibcon#[27=AT04-04\r\n] 2006.133.07:40:11.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:40:11.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:40:11.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.07:40:11.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:11.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:40:11.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:40:11.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:40:11.82#ibcon#[27=USB\r\n] 2006.133.07:40:11.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:40:11.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:40:11.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:40:11.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:40:11.85$vc4f8/vblo=5,744.99 2006.133.07:40:11.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.07:40:11.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.07:40:11.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:11.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:11.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:11.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:11.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:40:11.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:11.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:40:11.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:40:11.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:40:11.91$vc4f8/vb=5,4 2006.133.07:40:11.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.07:40:11.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.07:40:11.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:11.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:11.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:11.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:11.99#ibcon#[27=AT05-04\r\n] 2006.133.07:40:12.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:12.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:40:12.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.07:40:12.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:12.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:12.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:12.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:12.16#ibcon#[27=USB\r\n] 2006.133.07:40:12.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:12.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:40:12.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:40:12.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:40:12.19$vc4f8/vblo=6,752.99 2006.133.07:40:12.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:40:12.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:40:12.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:40:12.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:12.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:12.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:12.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:40:12.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:12.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:40:12.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:40:12.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:40:12.25$vc4f8/vb=6,4 2006.133.07:40:12.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:40:12.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:40:12.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:40:12.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:12.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:12.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:12.33#ibcon#[27=AT06-04\r\n] 2006.133.07:40:12.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:12.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:40:12.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:40:12.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:40:12.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:12.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:12.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:12.50#ibcon#[27=USB\r\n] 2006.133.07:40:12.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:12.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:40:12.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:40:12.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:40:12.53$vc4f8/vabw=wide 2006.133.07:40:12.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:40:12.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:40:12.53#ibcon#ireg 8 cls_cnt 0 2006.133.07:40:12.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:12.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:12.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:12.55#ibcon#[25=BW32\r\n] 2006.133.07:40:12.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:12.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:40:12.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:40:12.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:40:12.58$vc4f8/vbbw=wide 2006.133.07:40:12.58#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:40:12.58#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:40:12.58#ibcon#ireg 8 cls_cnt 0 2006.133.07:40:12.58#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:40:12.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:40:12.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:40:12.67#ibcon#[27=BW32\r\n] 2006.133.07:40:12.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:40:12.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:40:12.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:40:12.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:40:12.70$4f8m12a/ifd4f 2006.133.07:40:12.70$ifd4f/lo= 2006.133.07:40:12.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:40:12.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:40:12.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:40:12.70$ifd4f/patch= 2006.133.07:40:12.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:40:12.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:40:12.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:40:12.70$4f8m12a/"form=m,16.000,1:2 2006.133.07:40:12.70$4f8m12a/"tpicd 2006.133.07:40:12.70$4f8m12a/echo=off 2006.133.07:40:12.70$4f8m12a/xlog=off 2006.133.07:40:12.70:!2006.133.07:40:50 2006.133.07:40:31.13#trakl#Source acquired 2006.133.07:40:31.13#flagr#flagr/antenna,acquired 2006.133.07:40:50.00:preob 2006.133.07:40:50.13/onsource/TRACKING 2006.133.07:40:50.13:!2006.133.07:41:00 2006.133.07:41:00.00:data_valid=on 2006.133.07:41:00.00:midob 2006.133.07:41:01.13/onsource/TRACKING 2006.133.07:41:01.13/wx/11.38,1009.9,100 2006.133.07:41:01.30/cable/+6.5581E-03 2006.133.07:41:02.39/va/01,08,usb,yes,48,51 2006.133.07:41:02.39/va/02,07,usb,yes,49,51 2006.133.07:41:02.39/va/03,06,usb,yes,52,52 2006.133.07:41:02.39/va/04,07,usb,yes,50,54 2006.133.07:41:02.39/va/05,06,usb,yes,58,62 2006.133.07:41:02.39/va/06,05,usb,yes,59,59 2006.133.07:41:02.39/va/07,05,usb,yes,59,59 2006.133.07:41:02.39/va/08,06,usb,yes,55,54 2006.133.07:41:02.62/valo/01,532.99,yes,locked 2006.133.07:41:02.62/valo/02,572.99,yes,locked 2006.133.07:41:02.62/valo/03,672.99,yes,locked 2006.133.07:41:02.62/valo/04,832.99,yes,locked 2006.133.07:41:02.62/valo/05,652.99,yes,locked 2006.133.07:41:02.62/valo/06,772.99,yes,locked 2006.133.07:41:02.62/valo/07,832.99,yes,locked 2006.133.07:41:02.62/valo/08,852.99,yes,locked 2006.133.07:41:03.71/vb/01,04,usb,yes,31,30 2006.133.07:41:03.71/vb/02,04,usb,yes,33,35 2006.133.07:41:03.71/vb/03,04,usb,yes,30,33 2006.133.07:41:03.71/vb/04,04,usb,yes,31,31 2006.133.07:41:03.71/vb/05,04,usb,yes,29,33 2006.133.07:41:03.71/vb/06,04,usb,yes,30,33 2006.133.07:41:03.71/vb/07,04,usb,yes,32,32 2006.133.07:41:03.71/vb/08,04,usb,yes,30,33 2006.133.07:41:03.95/vblo/01,632.99,yes,locked 2006.133.07:41:03.95/vblo/02,640.99,yes,locked 2006.133.07:41:03.95/vblo/03,656.99,yes,locked 2006.133.07:41:03.95/vblo/04,712.99,yes,locked 2006.133.07:41:03.95/vblo/05,744.99,yes,locked 2006.133.07:41:03.95/vblo/06,752.99,yes,locked 2006.133.07:41:03.95/vblo/07,734.99,yes,locked 2006.133.07:41:03.95/vblo/08,744.99,yes,locked 2006.133.07:41:04.10/vabw/8 2006.133.07:41:04.25/vbbw/8 2006.133.07:41:04.34/xfe/off,on,15.2 2006.133.07:41:04.72/ifatt/23,28,28,28 2006.133.07:41:05.08/fmout-gps/S +1.87E-07 2006.133.07:41:05.12:!2006.133.07:42:00 2006.133.07:42:00.00:data_valid=off 2006.133.07:42:00.00:postob 2006.133.07:42:00.06/cable/+6.5567E-03 2006.133.07:42:00.06/wx/11.40,1009.9,100 2006.133.07:42:01.08/fmout-gps/S +1.87E-07 2006.133.07:42:01.08:scan_name=133-0743,k06133,110 2006.133.07:42:01.08:source=0508+138,051138.32,135719.2,2000.0,ccw 2006.133.07:42:01.14#flagr#flagr/antenna,new-source 2006.133.07:42:02.14:checkk5 2006.133.07:42:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:42:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:42:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:42:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:42:03.99/chk_obsdata//k5ts1/T1330741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:42:04.36/chk_obsdata//k5ts2/T1330741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:42:04.73/chk_obsdata//k5ts3/T1330741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:42:05.10/chk_obsdata//k5ts4/T1330741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:42:05.79/k5log//k5ts1_log_newline 2006.133.07:42:06.48/k5log//k5ts2_log_newline 2006.133.07:42:07.17/k5log//k5ts3_log_newline 2006.133.07:42:07.84/k5log//k5ts4_log_newline 2006.133.07:42:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:42:07.87:4f8m12a=1 2006.133.07:42:07.87$4f8m12a/echo=on 2006.133.07:42:07.87$4f8m12a/pcalon 2006.133.07:42:07.87$pcalon/"no phase cal control is implemented here 2006.133.07:42:07.87$4f8m12a/"tpicd=stop 2006.133.07:42:07.87$4f8m12a/vc4f8 2006.133.07:42:07.87$vc4f8/valo=1,532.99 2006.133.07:42:07.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:42:07.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:42:07.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:07.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:42:07.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:42:07.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:42:07.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:42:07.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:42:07.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:42:07.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:42:07.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:42:07.94$vc4f8/va=1,8 2006.133.07:42:07.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.07:42:07.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.07:42:07.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:07.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:42:07.94#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:42:07.94#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:42:07.96#ibcon#[25=AT01-08\r\n] 2006.133.07:42:07.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:42:07.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:42:07.99#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.07:42:07.99#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:07.99#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:42:08.11#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:42:08.11#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:42:08.13#ibcon#[25=USB\r\n] 2006.133.07:42:08.17#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:42:08.17#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:42:08.17#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:42:08.17#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:42:08.17$vc4f8/valo=2,572.99 2006.133.07:42:08.17#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.07:42:08.17#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.07:42:08.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:08.17#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:08.17#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:08.17#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:08.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:42:08.23#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:08.23#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:08.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:42:08.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:42:08.23$vc4f8/va=2,7 2006.133.07:42:08.23#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.07:42:08.23#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.07:42:08.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:08.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:08.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:08.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:08.31#ibcon#[25=AT02-07\r\n] 2006.133.07:42:08.34#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:08.34#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:08.34#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.07:42:08.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:08.34#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:08.46#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:08.46#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:08.48#ibcon#[25=USB\r\n] 2006.133.07:42:08.52#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:08.52#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:08.52#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:42:08.52#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:42:08.52$vc4f8/valo=3,672.99 2006.133.07:42:08.52#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.07:42:08.52#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.07:42:08.52#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:08.52#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:08.52#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:08.52#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:08.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:42:08.58#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:08.58#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:08.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:42:08.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:42:08.58$vc4f8/va=3,6 2006.133.07:42:08.58#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.07:42:08.58#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.07:42:08.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:08.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:08.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:08.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:08.66#ibcon#[25=AT03-06\r\n] 2006.133.07:42:08.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:08.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:08.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.07:42:08.69#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:08.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:08.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:08.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:08.83#ibcon#[25=USB\r\n] 2006.133.07:42:08.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:08.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:08.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:42:08.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:42:08.86$vc4f8/valo=4,832.99 2006.133.07:42:08.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.07:42:08.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.07:42:08.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:08.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:08.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:08.86#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:42:08.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:08.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:08.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:42:08.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:42:08.92$vc4f8/va=4,7 2006.133.07:42:08.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.07:42:08.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.07:42:08.92#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:08.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:08.98#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:08.98#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:09.00#ibcon#[25=AT04-07\r\n] 2006.133.07:42:09.03#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:09.03#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:09.03#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.07:42:09.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:09.03#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:09.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:09.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:09.17#ibcon#[25=USB\r\n] 2006.133.07:42:09.20#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:09.20#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:09.20#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:42:09.20#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:42:09.20$vc4f8/valo=5,652.99 2006.133.07:42:09.20#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.07:42:09.20#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.07:42:09.20#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:09.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:09.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:09.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:09.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:42:09.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:09.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:09.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:42:09.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:42:09.26$vc4f8/va=5,6 2006.133.07:42:09.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.07:42:09.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.07:42:09.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:09.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:09.32#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:09.32#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:09.34#ibcon#[25=AT05-06\r\n] 2006.133.07:42:09.37#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:09.37#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:09.37#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.07:42:09.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:09.37#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:09.49#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:09.49#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:09.51#ibcon#[25=USB\r\n] 2006.133.07:42:09.54#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:09.54#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:09.54#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:42:09.54#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:42:09.54$vc4f8/valo=6,772.99 2006.133.07:42:09.54#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:42:09.54#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:42:09.54#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:09.54#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:09.54#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:09.54#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:42:09.60#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:09.60#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:09.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:42:09.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:42:09.60$vc4f8/va=6,5 2006.133.07:42:09.60#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:42:09.60#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:42:09.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:09.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:09.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:09.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:09.68#ibcon#[25=AT06-05\r\n] 2006.133.07:42:09.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:09.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:09.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:42:09.71#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:09.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:09.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:09.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:09.85#ibcon#[25=USB\r\n] 2006.133.07:42:09.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:09.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:09.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:42:09.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:42:09.88$vc4f8/valo=7,832.99 2006.133.07:42:09.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:42:09.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:42:09.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:09.88#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:09.88#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:09.88#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:09.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:42:09.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:09.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:09.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:42:09.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:42:09.94$vc4f8/va=7,5 2006.133.07:42:09.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.07:42:09.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.07:42:09.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:09.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:10.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:10.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:10.02#ibcon#[25=AT07-05\r\n] 2006.133.07:42:10.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:10.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:10.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.07:42:10.05#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:10.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:42:10.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:42:10.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:42:10.19#ibcon#[25=USB\r\n] 2006.133.07:42:10.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:42:10.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:42:10.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:42:10.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:42:10.22$vc4f8/valo=8,852.99 2006.133.07:42:10.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:42:10.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:42:10.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:10.22#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:42:10.22#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:42:10.22#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:42:10.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:42:10.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:42:10.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:42:10.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:42:10.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:42:10.28$vc4f8/va=8,6 2006.133.07:42:10.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:42:10.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:42:10.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:10.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:42:10.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:42:10.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:42:10.36#ibcon#[25=AT08-06\r\n] 2006.133.07:42:10.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:42:10.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:42:10.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:42:10.39#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:10.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:42:10.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:42:10.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:42:10.53#ibcon#[25=USB\r\n] 2006.133.07:42:10.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:42:10.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:42:10.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:42:10.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:42:10.56$vc4f8/vblo=1,632.99 2006.133.07:42:10.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.07:42:10.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.07:42:10.56#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:10.56#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:42:10.56#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:42:10.56#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:42:10.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:42:10.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:42:10.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:42:10.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:42:10.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:42:10.62$vc4f8/vb=1,4 2006.133.07:42:10.62#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:42:10.62#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:42:10.62#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:10.62#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:42:10.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:42:10.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:42:10.63#abcon#<5=/02 0.8 2.7 11.401001009.9\r\n> 2006.133.07:42:10.64#ibcon#[27=AT01-04\r\n] 2006.133.07:42:10.65#abcon#{5=INTERFACE CLEAR} 2006.133.07:42:10.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:42:10.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:42:10.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:42:10.67#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:10.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:42:10.71#abcon#[5=S1D000X0/0*\r\n] 2006.133.07:42:10.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:42:10.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:42:10.81#ibcon#[27=USB\r\n] 2006.133.07:42:10.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:42:10.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:42:10.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:42:10.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:42:10.84$vc4f8/vblo=2,640.99 2006.133.07:42:10.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.07:42:10.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.07:42:10.84#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:10.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:10.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:10.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:10.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:42:10.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:10.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:42:10.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:42:10.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:42:10.90$vc4f8/vb=2,4 2006.133.07:42:10.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.07:42:10.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.07:42:10.90#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:10.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:10.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:10.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:10.98#ibcon#[27=AT02-04\r\n] 2006.133.07:42:11.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:11.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:42:11.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.07:42:11.01#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:11.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:11.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:11.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:11.15#ibcon#[27=USB\r\n] 2006.133.07:42:11.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:11.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:42:11.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:42:11.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:42:11.18$vc4f8/vblo=3,656.99 2006.133.07:42:11.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.07:42:11.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.07:42:11.18#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:11.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:11.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:11.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:11.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:42:11.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:11.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:42:11.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:42:11.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:42:11.24$vc4f8/vb=3,4 2006.133.07:42:11.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.07:42:11.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.07:42:11.24#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:11.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:11.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:11.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:11.32#ibcon#[27=AT03-04\r\n] 2006.133.07:42:11.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:11.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.07:42:11.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.07:42:11.35#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:11.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:11.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:11.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:11.49#ibcon#[27=USB\r\n] 2006.133.07:42:11.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:11.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.07:42:11.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:42:11.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:42:11.52$vc4f8/vblo=4,712.99 2006.133.07:42:11.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.07:42:11.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.07:42:11.52#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:11.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:11.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:11.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:11.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:42:11.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:11.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:42:11.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:42:11.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:42:11.58$vc4f8/vb=4,4 2006.133.07:42:11.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.07:42:11.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.07:42:11.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:11.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:11.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:11.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:11.66#ibcon#[27=AT04-04\r\n] 2006.133.07:42:11.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:11.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:42:11.69#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.07:42:11.69#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:11.69#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:11.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:11.81#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:11.83#ibcon#[27=USB\r\n] 2006.133.07:42:11.86#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:11.86#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:42:11.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:42:11.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:42:11.86$vc4f8/vblo=5,744.99 2006.133.07:42:11.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.07:42:11.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.07:42:11.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:11.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:11.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:11.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:42:11.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:11.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:42:11.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:42:11.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:42:11.94$vc4f8/vb=5,4 2006.133.07:42:11.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.07:42:11.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.07:42:11.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:11.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:11.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:11.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:12.00#ibcon#[27=AT05-04\r\n] 2006.133.07:42:12.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:12.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:42:12.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.07:42:12.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:12.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:12.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:12.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:12.17#ibcon#[27=USB\r\n] 2006.133.07:42:12.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:12.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:42:12.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:42:12.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:42:12.20$vc4f8/vblo=6,752.99 2006.133.07:42:12.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:42:12.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:42:12.20#ibcon#ireg 17 cls_cnt 0 2006.133.07:42:12.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:12.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:12.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:12.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:42:12.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:12.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:42:12.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:42:12.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:42:12.26$vc4f8/vb=6,4 2006.133.07:42:12.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:42:12.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:42:12.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:42:12.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:12.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:12.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:12.34#ibcon#[27=AT06-04\r\n] 2006.133.07:42:12.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:12.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:42:12.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:42:12.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:42:12.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:12.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:12.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:12.51#ibcon#[27=USB\r\n] 2006.133.07:42:12.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:12.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:42:12.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:42:12.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:42:12.54$vc4f8/vabw=wide 2006.133.07:42:12.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:42:12.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:42:12.54#ibcon#ireg 8 cls_cnt 0 2006.133.07:42:12.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:12.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:12.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:12.56#ibcon#[25=BW32\r\n] 2006.133.07:42:12.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:12.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:42:12.59#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:42:12.59#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:42:12.59$vc4f8/vbbw=wide 2006.133.07:42:12.59#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:42:12.59#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:42:12.59#ibcon#ireg 8 cls_cnt 0 2006.133.07:42:12.59#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:42:12.66#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:42:12.66#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:42:12.68#ibcon#[27=BW32\r\n] 2006.133.07:42:12.71#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:42:12.71#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:42:12.71#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:42:12.71#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:42:12.71$4f8m12a/ifd4f 2006.133.07:42:12.71$ifd4f/lo= 2006.133.07:42:12.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:42:12.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:42:12.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:42:12.71$ifd4f/patch= 2006.133.07:42:12.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:42:12.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:42:12.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:42:12.71$4f8m12a/"form=m,16.000,1:2 2006.133.07:42:12.71$4f8m12a/"tpicd 2006.133.07:42:12.71$4f8m12a/echo=off 2006.133.07:42:12.71$4f8m12a/xlog=off 2006.133.07:42:12.71:!2006.133.07:42:50 2006.133.07:42:30.14#trakl#Source acquired 2006.133.07:42:31.14#flagr#flagr/antenna,acquired 2006.133.07:42:50.00:preob 2006.133.07:42:50.14/onsource/TRACKING 2006.133.07:42:50.14:!2006.133.07:43:00 2006.133.07:43:00.00:data_valid=on 2006.133.07:43:00.00:midob 2006.133.07:43:01.14/onsource/TRACKING 2006.133.07:43:01.14/wx/11.39,1009.8,100 2006.133.07:43:01.30/cable/+6.5585E-03 2006.133.07:43:02.39/va/01,08,usb,yes,43,46 2006.133.07:43:02.39/va/02,07,usb,yes,44,46 2006.133.07:43:02.39/va/03,06,usb,yes,46,47 2006.133.07:43:02.39/va/04,07,usb,yes,45,48 2006.133.07:43:02.39/va/05,06,usb,yes,52,55 2006.133.07:43:02.39/va/06,05,usb,yes,53,52 2006.133.07:43:02.39/va/07,05,usb,yes,52,52 2006.133.07:43:02.39/va/08,06,usb,yes,49,48 2006.133.07:43:02.62/valo/01,532.99,yes,locked 2006.133.07:43:02.62/valo/02,572.99,yes,locked 2006.133.07:43:02.62/valo/03,672.99,yes,locked 2006.133.07:43:02.62/valo/04,832.99,yes,locked 2006.133.07:43:02.62/valo/05,652.99,yes,locked 2006.133.07:43:02.62/valo/06,772.99,yes,locked 2006.133.07:43:02.62/valo/07,832.99,yes,locked 2006.133.07:43:02.62/valo/08,852.99,yes,locked 2006.133.07:43:03.71/vb/01,04,usb,yes,30,29 2006.133.07:43:03.71/vb/02,04,usb,yes,32,33 2006.133.07:43:03.71/vb/03,04,usb,yes,28,32 2006.133.07:43:03.71/vb/04,04,usb,yes,29,29 2006.133.07:43:03.71/vb/05,04,usb,yes,28,31 2006.133.07:43:03.71/vb/06,04,usb,yes,29,31 2006.133.07:43:03.71/vb/07,04,usb,yes,31,30 2006.133.07:43:03.71/vb/08,04,usb,yes,28,31 2006.133.07:43:03.95/vblo/01,632.99,yes,locked 2006.133.07:43:03.95/vblo/02,640.99,yes,locked 2006.133.07:43:03.95/vblo/03,656.99,yes,locked 2006.133.07:43:03.95/vblo/04,712.99,yes,locked 2006.133.07:43:03.95/vblo/05,744.99,yes,locked 2006.133.07:43:03.95/vblo/06,752.99,yes,locked 2006.133.07:43:03.95/vblo/07,734.99,yes,locked 2006.133.07:43:03.95/vblo/08,744.99,yes,locked 2006.133.07:43:04.10/vabw/8 2006.133.07:43:04.25/vbbw/8 2006.133.07:43:04.34/xfe/off,on,15.2 2006.133.07:43:04.72/ifatt/23,28,28,28 2006.133.07:43:05.08/fmout-gps/S +1.86E-07 2006.133.07:43:05.12:!2006.133.07:44:50 2006.133.07:44:50.02:data_valid=off 2006.133.07:44:50.02:postob 2006.133.07:44:50.10/cable/+6.5604E-03 2006.133.07:44:50.10/wx/11.38,1009.8,100 2006.133.07:44:51.07/fmout-gps/S +1.86E-07 2006.133.07:44:51.08:scan_name=133-0746,k06133,60 2006.133.07:44:51.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.133.07:44:52.15#flagr#flagr/antenna,new-source 2006.133.07:44:52.15:checkk5 2006.133.07:44:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:44:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:44:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:44:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:44:54.01/chk_obsdata//k5ts1/T1330743??a.dat file size is correct (nominal:880MB, actual:872MB). 2006.133.07:44:54.38/chk_obsdata//k5ts2/T1330743??b.dat file size is correct (nominal:880MB, actual:872MB). 2006.133.07:44:54.75/chk_obsdata//k5ts3/T1330743??c.dat file size is correct (nominal:880MB, actual:872MB). 2006.133.07:44:55.12/chk_obsdata//k5ts4/T1330743??d.dat file size is correct (nominal:880MB, actual:872MB). 2006.133.07:44:55.81/k5log//k5ts1_log_newline 2006.133.07:44:56.49/k5log//k5ts2_log_newline 2006.133.07:44:57.18/k5log//k5ts3_log_newline 2006.133.07:44:57.87/k5log//k5ts4_log_newline 2006.133.07:44:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:44:57.89:4f8m12a=1 2006.133.07:44:57.89$4f8m12a/echo=on 2006.133.07:44:57.89$4f8m12a/pcalon 2006.133.07:44:57.89$pcalon/"no phase cal control is implemented here 2006.133.07:44:57.89$4f8m12a/"tpicd=stop 2006.133.07:44:57.89$4f8m12a/vc4f8 2006.133.07:44:57.89$vc4f8/valo=1,532.99 2006.133.07:44:57.90#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:44:57.90#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:44:57.90#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:57.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:44:57.90#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:44:57.90#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:44:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:44:57.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:44:57.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:44:57.98#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:44:57.98#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:44:57.99$vc4f8/va=1,8 2006.133.07:44:57.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:44:57.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:44:57.99#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:57.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:44:57.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:44:57.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:44:58.02#ibcon#[25=AT01-08\r\n] 2006.133.07:44:58.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:44:58.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:44:58.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:44:58.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:58.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:44:58.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:44:58.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:44:58.18#ibcon#[25=USB\r\n] 2006.133.07:44:58.22#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:44:58.22#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:44:58.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:44:58.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:44:58.22$vc4f8/valo=2,572.99 2006.133.07:44:58.22#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:44:58.22#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:44:58.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:58.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:44:58.22#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:44:58.22#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:44:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:44:58.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:44:58.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:44:58.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:44:58.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:44:58.28$vc4f8/va=2,7 2006.133.07:44:58.28#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:44:58.28#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:44:58.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:58.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:44:58.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:44:58.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:44:58.35#ibcon#[25=AT02-07\r\n] 2006.133.07:44:58.39#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:44:58.39#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:44:58.39#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:44:58.39#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:58.39#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:44:58.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:44:58.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:44:58.52#ibcon#[25=USB\r\n] 2006.133.07:44:58.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:44:58.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:44:58.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:44:58.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:44:58.56$vc4f8/valo=3,672.99 2006.133.07:44:58.56#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:44:58.56#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:44:58.56#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:58.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:44:58.56#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:44:58.56#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:44:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:44:58.62#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:44:58.62#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:44:58.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:44:58.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:44:58.63$vc4f8/va=3,6 2006.133.07:44:58.63#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:44:58.63#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:44:58.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:58.63#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:44:58.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:44:58.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:44:58.68#ibcon#[25=AT03-06\r\n] 2006.133.07:44:58.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:44:58.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:44:58.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:44:58.71#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:58.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:44:58.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:44:58.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:44:58.85#ibcon#[25=USB\r\n] 2006.133.07:44:58.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:44:58.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:44:58.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:44:58.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:44:58.89$vc4f8/valo=4,832.99 2006.133.07:44:58.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:44:58.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:44:58.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:58.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:44:58.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:44:58.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:44:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:44:58.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:44:58.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:44:58.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:44:58.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:44:58.95$vc4f8/va=4,7 2006.133.07:44:58.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:44:58.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:44:58.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:58.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:44:58.99#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:44:58.99#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:44:59.01#ibcon#[25=AT04-07\r\n] 2006.133.07:44:59.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:44:59.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:44:59.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:44:59.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:59.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:44:59.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:44:59.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:44:59.18#ibcon#[25=USB\r\n] 2006.133.07:44:59.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:44:59.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:44:59.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:44:59.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:44:59.22$vc4f8/valo=5,652.99 2006.133.07:44:59.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:44:59.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:44:59.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:59.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:44:59.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:44:59.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:44:59.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:44:59.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:44:59.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:44:59.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:44:59.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:44:59.28$vc4f8/va=5,6 2006.133.07:44:59.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:44:59.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:44:59.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:59.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:44:59.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:44:59.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:44:59.34#ibcon#[25=AT05-06\r\n] 2006.133.07:44:59.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:44:59.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:44:59.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:44:59.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:59.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:44:59.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:44:59.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:44:59.51#ibcon#[25=USB\r\n] 2006.133.07:44:59.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:44:59.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:44:59.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:44:59.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:44:59.55$vc4f8/valo=6,772.99 2006.133.07:44:59.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:44:59.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:44:59.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:59.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:44:59.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:44:59.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:44:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:44:59.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:44:59.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:44:59.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:44:59.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:44:59.61$vc4f8/va=6,5 2006.133.07:44:59.61#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.07:44:59.61#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.07:44:59.61#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:59.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:44:59.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:44:59.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:44:59.67#ibcon#[25=AT06-05\r\n] 2006.133.07:44:59.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:44:59.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:44:59.70#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.07:44:59.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:44:59.70#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:44:59.82#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:44:59.82#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:44:59.84#ibcon#[25=USB\r\n] 2006.133.07:44:59.87#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:44:59.87#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:44:59.87#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:44:59.87#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:44:59.88$vc4f8/valo=7,832.99 2006.133.07:44:59.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.07:44:59.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.07:44:59.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:44:59.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:44:59.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:44:59.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:44:59.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:44:59.93#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:44:59.93#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:44:59.93#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:44:59.93#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:44:59.94$vc4f8/va=7,5 2006.133.07:44:59.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.07:44:59.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.07:44:59.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:44:59.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:44:59.98#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:44:59.98#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:45:00.00#ibcon#[25=AT07-05\r\n] 2006.133.07:45:00.03#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:45:00.03#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:45:00.03#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.07:45:00.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:00.03#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:45:00.15#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:45:00.15#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:45:00.17#ibcon#[25=USB\r\n] 2006.133.07:45:00.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:45:00.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:45:00.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:45:00.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:45:00.22$vc4f8/valo=8,852.99 2006.133.07:45:00.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:45:00.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:45:00.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:00.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:45:00.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:45:00.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:45:00.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:45:00.27#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:45:00.27#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:45:00.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:45:00.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:45:00.28$vc4f8/va=8,6 2006.133.07:45:00.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.07:45:00.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.07:45:00.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:00.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:45:00.33#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:45:00.33#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:45:00.35#ibcon#[25=AT08-06\r\n] 2006.133.07:45:00.38#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:45:00.38#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:45:00.38#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.07:45:00.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:00.38#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:45:00.50#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:45:00.50#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:45:00.52#ibcon#[25=USB\r\n] 2006.133.07:45:00.55#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:45:00.55#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:45:00.55#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:45:00.55#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:45:00.56$vc4f8/vblo=1,632.99 2006.133.07:45:00.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:45:00.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:45:00.56#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:00.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:45:00.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:45:00.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:45:00.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:45:00.61#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:45:00.61#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:45:00.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:45:00.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:45:00.62$vc4f8/vb=1,4 2006.133.07:45:00.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:45:00.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:45:00.62#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:00.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:45:00.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:45:00.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:45:00.63#ibcon#[27=AT01-04\r\n] 2006.133.07:45:00.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:45:00.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:45:00.66#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:45:00.66#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:00.66#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:45:00.78#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:45:00.78#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:45:00.80#ibcon#[27=USB\r\n] 2006.133.07:45:00.83#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:45:00.83#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:45:00.83#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:45:00.83#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:45:00.84$vc4f8/vblo=2,640.99 2006.133.07:45:00.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:45:00.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:45:00.84#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:00.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:45:00.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:45:00.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:45:00.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:45:00.89#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:45:00.89#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:45:00.89#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:45:00.89#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:45:00.90$vc4f8/vb=2,4 2006.133.07:45:00.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:45:00.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:45:00.90#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:00.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:45:00.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:45:00.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:45:00.96#ibcon#[27=AT02-04\r\n] 2006.133.07:45:00.99#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:45:00.99#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:45:00.99#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:45:00.99#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:00.99#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:45:01.11#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:45:01.11#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:45:01.13#ibcon#[27=USB\r\n] 2006.133.07:45:01.16#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:45:01.16#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:45:01.16#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:45:01.16#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:45:01.16$vc4f8/vblo=3,656.99 2006.133.07:45:01.17#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:45:01.17#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:45:01.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:01.17#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:45:01.17#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:45:01.17#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:45:01.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:45:01.22#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:45:01.22#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:45:01.22#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:45:01.22#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:45:01.23$vc4f8/vb=3,4 2006.133.07:45:01.23#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:45:01.23#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:45:01.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:01.23#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:45:01.27#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:45:01.27#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:45:01.29#ibcon#[27=AT03-04\r\n] 2006.133.07:45:01.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:45:01.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:45:01.32#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:45:01.32#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:01.32#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:45:01.44#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:45:01.44#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:45:01.46#ibcon#[27=USB\r\n] 2006.133.07:45:01.49#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:45:01.49#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:45:01.49#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:45:01.49#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:45:01.50$vc4f8/vblo=4,712.99 2006.133.07:45:01.50#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:45:01.50#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:45:01.50#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:01.50#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:45:01.50#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:45:01.50#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:45:01.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:45:01.55#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:45:01.55#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:45:01.55#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:45:01.55#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:45:01.56$vc4f8/vb=4,4 2006.133.07:45:01.56#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:45:01.56#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:45:01.56#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:01.56#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:45:01.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:45:01.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:45:01.62#ibcon#[27=AT04-04\r\n] 2006.133.07:45:01.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:45:01.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:45:01.65#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:45:01.65#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:01.65#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:45:01.77#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:45:01.77#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:45:01.79#ibcon#[27=USB\r\n] 2006.133.07:45:01.82#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:45:01.82#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:45:01.82#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:45:01.82#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:45:01.83$vc4f8/vblo=5,744.99 2006.133.07:45:01.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:45:01.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:45:01.83#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:01.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:45:01.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:45:01.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:45:01.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:45:01.88#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:45:01.88#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:45:01.88#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:45:01.88#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:45:01.89$vc4f8/vb=5,4 2006.133.07:45:01.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:45:01.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:45:01.89#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:01.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:45:01.93#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:45:01.93#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:45:01.95#ibcon#[27=AT05-04\r\n] 2006.133.07:45:02.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:45:02.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:45:02.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:45:02.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:02.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:45:02.11#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:45:02.11#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:45:02.13#ibcon#[27=USB\r\n] 2006.133.07:45:02.16#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:45:02.16#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:45:02.16#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:45:02.16#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:45:02.16$vc4f8/vblo=6,752.99 2006.133.07:45:02.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:45:02.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:45:02.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:45:02.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:45:02.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:45:02.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:45:02.18#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:45:02.22#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:45:02.22#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:45:02.22#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:45:02.22#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:45:02.23$vc4f8/vb=6,4 2006.133.07:45:02.23#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:45:02.23#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:45:02.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:45:02.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:45:02.27#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:45:02.27#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:45:02.29#ibcon#[27=AT06-04\r\n] 2006.133.07:45:02.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:45:02.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:45:02.32#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:45:02.32#ibcon#ireg 7 cls_cnt 0 2006.133.07:45:02.32#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:45:02.44#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:45:02.44#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:45:02.46#ibcon#[27=USB\r\n] 2006.133.07:45:02.49#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:45:02.49#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:45:02.49#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:45:02.49#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:45:02.50$vc4f8/vabw=wide 2006.133.07:45:02.50#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:45:02.50#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:45:02.50#ibcon#ireg 8 cls_cnt 0 2006.133.07:45:02.50#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:45:02.50#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:45:02.50#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:45:02.51#ibcon#[25=BW32\r\n] 2006.133.07:45:02.54#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:45:02.54#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:45:02.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:45:02.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:45:02.55$vc4f8/vbbw=wide 2006.133.07:45:02.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:45:02.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:45:02.55#ibcon#ireg 8 cls_cnt 0 2006.133.07:45:02.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:45:02.60#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:45:02.60#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:45:02.62#ibcon#[27=BW32\r\n] 2006.133.07:45:02.65#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:45:02.65#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:45:02.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:45:02.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:45:02.66$4f8m12a/ifd4f 2006.133.07:45:02.66$ifd4f/lo= 2006.133.07:45:02.66$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:45:02.66$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:45:02.66$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:45:02.66$ifd4f/patch= 2006.133.07:45:02.66$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:45:02.66$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:45:02.66$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:45:02.66$4f8m12a/"form=m,16.000,1:2 2006.133.07:45:02.66$4f8m12a/"tpicd 2006.133.07:45:02.66$4f8m12a/echo=off 2006.133.07:45:02.66$4f8m12a/xlog=off 2006.133.07:45:02.66:!2006.133.07:46:00 2006.133.07:45:37.14#trakl#Source acquired 2006.133.07:45:39.15#flagr#flagr/antenna,acquired 2006.133.07:46:00.02:preob 2006.133.07:46:01.15/onsource/TRACKING 2006.133.07:46:01.15:!2006.133.07:46:10 2006.133.07:46:10.02:data_valid=on 2006.133.07:46:10.02:midob 2006.133.07:46:11.15/onsource/TRACKING 2006.133.07:46:11.15/wx/11.39,1009.8,100 2006.133.07:46:11.27/cable/+6.5607E-03 2006.133.07:46:12.36/va/01,08,usb,yes,45,48 2006.133.07:46:12.36/va/02,07,usb,yes,46,47 2006.133.07:46:12.36/va/03,06,usb,yes,48,48 2006.133.07:46:12.36/va/04,07,usb,yes,47,50 2006.133.07:46:12.36/va/05,06,usb,yes,54,57 2006.133.07:46:12.36/va/06,05,usb,yes,55,54 2006.133.07:46:12.36/va/07,05,usb,yes,55,54 2006.133.07:46:12.36/va/08,06,usb,yes,51,50 2006.133.07:46:12.59/valo/01,532.99,yes,locked 2006.133.07:46:12.59/valo/02,572.99,yes,locked 2006.133.07:46:12.59/valo/03,672.99,yes,locked 2006.133.07:46:12.59/valo/04,832.99,yes,locked 2006.133.07:46:12.59/valo/05,652.99,yes,locked 2006.133.07:46:12.59/valo/06,772.99,yes,locked 2006.133.07:46:12.59/valo/07,832.99,yes,locked 2006.133.07:46:12.59/valo/08,852.99,yes,locked 2006.133.07:46:13.68/vb/01,04,usb,yes,30,29 2006.133.07:46:13.68/vb/02,04,usb,yes,32,34 2006.133.07:46:13.68/vb/03,04,usb,yes,28,32 2006.133.07:46:13.68/vb/04,04,usb,yes,29,30 2006.133.07:46:13.68/vb/05,04,usb,yes,28,32 2006.133.07:46:13.68/vb/06,04,usb,yes,29,32 2006.133.07:46:13.68/vb/07,04,usb,yes,31,31 2006.133.07:46:13.68/vb/08,04,usb,yes,29,32 2006.133.07:46:13.92/vblo/01,632.99,yes,locked 2006.133.07:46:13.92/vblo/02,640.99,yes,locked 2006.133.07:46:13.92/vblo/03,656.99,yes,locked 2006.133.07:46:13.92/vblo/04,712.99,yes,locked 2006.133.07:46:13.92/vblo/05,744.99,yes,locked 2006.133.07:46:13.92/vblo/06,752.99,yes,locked 2006.133.07:46:13.92/vblo/07,734.99,yes,locked 2006.133.07:46:13.92/vblo/08,744.99,yes,locked 2006.133.07:46:14.07/vabw/8 2006.133.07:46:14.22/vbbw/8 2006.133.07:46:14.34/xfe/off,on,15.2 2006.133.07:46:14.73/ifatt/23,28,28,28 2006.133.07:46:15.08/fmout-gps/S +1.86E-07 2006.133.07:46:15.13:!2006.133.07:47:10 2006.133.07:47:10.01:data_valid=off 2006.133.07:47:10.02:postob 2006.133.07:47:10.11/cable/+6.5588E-03 2006.133.07:47:10.12/wx/11.40,1009.8,100 2006.133.07:47:11.08/fmout-gps/S +1.87E-07 2006.133.07:47:11.09:scan_name=133-0748,k06133,60 2006.133.07:47:11.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.133.07:47:12.14#flagr#flagr/antenna,new-source 2006.133.07:47:12.15:checkk5 2006.133.07:47:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:47:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:47:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:47:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:47:14.02/chk_obsdata//k5ts1/T1330746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:47:14.38/chk_obsdata//k5ts2/T1330746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:47:14.74/chk_obsdata//k5ts3/T1330746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:47:15.11/chk_obsdata//k5ts4/T1330746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:47:15.81/k5log//k5ts1_log_newline 2006.133.07:47:16.51/k5log//k5ts2_log_newline 2006.133.07:47:17.20/k5log//k5ts3_log_newline 2006.133.07:47:17.90/k5log//k5ts4_log_newline 2006.133.07:47:17.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:47:17.92:4f8m12a=1 2006.133.07:47:17.92$4f8m12a/echo=on 2006.133.07:47:17.92$4f8m12a/pcalon 2006.133.07:47:17.92$pcalon/"no phase cal control is implemented here 2006.133.07:47:17.92$4f8m12a/"tpicd=stop 2006.133.07:47:17.92$4f8m12a/vc4f8 2006.133.07:47:17.92$vc4f8/valo=1,532.99 2006.133.07:47:17.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.07:47:17.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.07:47:17.93#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:17.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:17.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:17.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:17.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:47:18.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:18.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:18.01#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:47:18.01#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:47:18.01$vc4f8/va=1,8 2006.133.07:47:18.01#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.07:47:18.01#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.07:47:18.01#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:18.01#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:18.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:18.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:18.05#ibcon#[25=AT01-08\r\n] 2006.133.07:47:18.07#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:18.07#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:18.07#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.07:47:18.07#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:18.07#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:18.19#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:18.19#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:18.23#ibcon#[25=USB\r\n] 2006.133.07:47:18.25#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:18.25#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:18.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:47:18.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:47:18.25$vc4f8/valo=2,572.99 2006.133.07:47:18.25#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.07:47:18.25#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.07:47:18.25#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:18.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:18.25#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:18.25#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:18.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:47:18.31#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:18.31#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:18.31#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:47:18.31#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:47:18.31$vc4f8/va=2,7 2006.133.07:47:18.31#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.07:47:18.31#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.07:47:18.31#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:18.31#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:18.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:18.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:18.40#ibcon#[25=AT02-07\r\n] 2006.133.07:47:18.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:18.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:18.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.07:47:18.43#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:18.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:18.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:18.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:18.57#ibcon#[25=USB\r\n] 2006.133.07:47:18.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:18.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:18.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:47:18.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:47:18.60$vc4f8/valo=3,672.99 2006.133.07:47:18.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.07:47:18.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.07:47:18.60#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:18.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:18.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:18.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:18.64#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:47:18.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:18.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:18.67#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:47:18.67#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:47:18.67$vc4f8/va=3,6 2006.133.07:47:18.67#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.07:47:18.67#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.07:47:18.67#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:18.67#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:18.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:18.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:18.74#ibcon#[25=AT03-06\r\n] 2006.133.07:47:18.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:18.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:18.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.07:47:18.77#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:18.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:18.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:18.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:18.91#ibcon#[25=USB\r\n] 2006.133.07:47:18.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:18.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:18.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:47:18.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:47:18.94$vc4f8/valo=4,832.99 2006.133.07:47:18.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:47:18.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:47:18.94#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:18.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:18.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:18.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:18.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:47:19.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:19.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:19.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:47:19.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:47:19.00$vc4f8/va=4,7 2006.133.07:47:19.00#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.07:47:19.00#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.07:47:19.00#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:19.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:19.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:19.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:19.08#ibcon#[25=AT04-07\r\n] 2006.133.07:47:19.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:19.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:19.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.07:47:19.11#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:19.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:19.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:19.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:19.25#ibcon#[25=USB\r\n] 2006.133.07:47:19.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:19.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:19.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:47:19.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:47:19.28$vc4f8/valo=5,652.99 2006.133.07:47:19.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:47:19.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:47:19.28#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:19.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:19.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:19.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:19.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:47:19.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:19.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:19.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:47:19.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:47:19.34$vc4f8/va=5,6 2006.133.07:47:19.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.07:47:19.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.07:47:19.34#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:19.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:19.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:19.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:19.42#ibcon#[25=AT05-06\r\n] 2006.133.07:47:19.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:19.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:19.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.07:47:19.45#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:19.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:19.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:19.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:19.59#ibcon#[25=USB\r\n] 2006.133.07:47:19.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:19.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:19.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:47:19.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:47:19.62$vc4f8/valo=6,772.99 2006.133.07:47:19.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:47:19.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:47:19.62#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:19.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:19.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:19.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:19.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:47:19.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:19.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:19.69#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:47:19.69#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:47:19.69$vc4f8/va=6,5 2006.133.07:47:19.69#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.07:47:19.69#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.07:47:19.69#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:19.69#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:19.74#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:19.74#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:19.76#ibcon#[25=AT06-05\r\n] 2006.133.07:47:19.79#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:19.79#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:19.79#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.07:47:19.79#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:19.79#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:47:19.91#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:47:19.91#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:47:19.93#ibcon#[25=USB\r\n] 2006.133.07:47:19.96#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:47:19.96#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:47:19.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:47:19.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:47:19.96$vc4f8/valo=7,832.99 2006.133.07:47:19.96#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.07:47:19.96#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.07:47:19.96#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:19.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:47:19.96#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:47:19.96#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:47:19.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:47:20.02#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:47:20.02#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:47:20.02#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:47:20.02#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:47:20.02$vc4f8/va=7,5 2006.133.07:47:20.02#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.07:47:20.02#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.07:47:20.02#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:20.02#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:47:20.08#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:47:20.08#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:47:20.10#ibcon#[25=AT07-05\r\n] 2006.133.07:47:20.13#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:47:20.13#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:47:20.13#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.07:47:20.13#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:20.13#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:47:20.25#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:47:20.25#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:47:20.27#ibcon#[25=USB\r\n] 2006.133.07:47:20.30#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:47:20.30#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:47:20.30#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:47:20.30#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:47:20.30$vc4f8/valo=8,852.99 2006.133.07:47:20.30#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.07:47:20.30#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.07:47:20.30#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:20.30#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:47:20.30#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:47:20.30#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:47:20.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:47:20.36#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:47:20.36#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:47:20.36#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:47:20.36#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:47:20.36$vc4f8/va=8,6 2006.133.07:47:20.36#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.07:47:20.36#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.07:47:20.36#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:20.36#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:47:20.42#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:47:20.42#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:47:20.44#ibcon#[25=AT08-06\r\n] 2006.133.07:47:20.47#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:47:20.47#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:47:20.47#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.07:47:20.47#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:20.47#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:47:20.59#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:47:20.59#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:47:20.61#ibcon#[25=USB\r\n] 2006.133.07:47:20.64#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:47:20.64#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:47:20.64#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:47:20.64#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:47:20.64$vc4f8/vblo=1,632.99 2006.133.07:47:20.64#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:47:20.64#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:47:20.64#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:20.64#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:47:20.64#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:47:20.64#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:47:20.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:47:20.70#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:47:20.70#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:47:20.70#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:47:20.70#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:47:20.70$vc4f8/vb=1,4 2006.133.07:47:20.70#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.07:47:20.70#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.07:47:20.70#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:20.70#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:47:20.70#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:47:20.70#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:47:20.72#ibcon#[27=AT01-04\r\n] 2006.133.07:47:20.75#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:47:20.75#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:47:20.75#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.07:47:20.75#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:20.75#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:47:20.87#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:47:20.87#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:47:20.89#ibcon#[27=USB\r\n] 2006.133.07:47:20.92#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:47:20.92#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:47:20.92#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:47:20.92#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:47:20.92$vc4f8/vblo=2,640.99 2006.133.07:47:20.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.07:47:20.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.07:47:20.92#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:20.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:20.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:20.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:20.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:47:20.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:20.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:47:20.98#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:47:20.98#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:47:20.98$vc4f8/vb=2,4 2006.133.07:47:20.98#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.07:47:20.98#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.07:47:20.98#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:20.98#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:21.04#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:21.04#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:21.06#ibcon#[27=AT02-04\r\n] 2006.133.07:47:21.09#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:21.09#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:47:21.09#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.07:47:21.09#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:21.09#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:21.21#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:21.21#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:21.23#ibcon#[27=USB\r\n] 2006.133.07:47:21.26#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:21.26#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:47:21.26#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:47:21.26#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:47:21.26$vc4f8/vblo=3,656.99 2006.133.07:47:21.26#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.07:47:21.26#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.07:47:21.26#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:21.26#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:21.26#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:21.26#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:21.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:47:21.32#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:21.32#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:47:21.32#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:47:21.32#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:47:21.32$vc4f8/vb=3,4 2006.133.07:47:21.32#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.07:47:21.32#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.07:47:21.32#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:21.32#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:21.38#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:21.38#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:21.40#ibcon#[27=AT03-04\r\n] 2006.133.07:47:21.43#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:21.43#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:47:21.43#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.07:47:21.43#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:21.43#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:21.55#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:21.55#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:21.57#ibcon#[27=USB\r\n] 2006.133.07:47:21.60#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:21.60#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:47:21.60#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:47:21.60#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:47:21.60$vc4f8/vblo=4,712.99 2006.133.07:47:21.60#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.07:47:21.60#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.07:47:21.60#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:21.60#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:21.60#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:21.60#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:21.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:47:21.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:21.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:47:21.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:47:21.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:47:21.66$vc4f8/vb=4,4 2006.133.07:47:21.66#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.07:47:21.66#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.07:47:21.66#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:21.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:21.72#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:21.72#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:21.74#ibcon#[27=AT04-04\r\n] 2006.133.07:47:21.77#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:21.77#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:47:21.77#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.07:47:21.77#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:21.77#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:21.89#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:21.89#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:21.91#ibcon#[27=USB\r\n] 2006.133.07:47:21.94#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:21.94#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:47:21.94#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:47:21.94#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:47:21.94$vc4f8/vblo=5,744.99 2006.133.07:47:21.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:47:21.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:47:21.94#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:21.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:21.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:21.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:21.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:47:22.00#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:22.00#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:47:22.00#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:47:22.00#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:47:22.00$vc4f8/vb=5,4 2006.133.07:47:22.00#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.07:47:22.00#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.07:47:22.00#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:22.00#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:22.06#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:22.06#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:22.08#ibcon#[27=AT05-04\r\n] 2006.133.07:47:22.11#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:22.11#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:47:22.11#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.07:47:22.11#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:22.11#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:22.23#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:22.23#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:22.25#ibcon#[27=USB\r\n] 2006.133.07:47:22.28#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:22.28#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:47:22.28#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:47:22.28#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:47:22.28$vc4f8/vblo=6,752.99 2006.133.07:47:22.28#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:47:22.28#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:47:22.28#ibcon#ireg 17 cls_cnt 0 2006.133.07:47:22.28#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:22.28#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:22.28#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:22.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:47:22.34#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:22.34#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:47:22.34#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:47:22.34#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:47:22.34$vc4f8/vb=6,4 2006.133.07:47:22.34#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.07:47:22.34#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.07:47:22.34#ibcon#ireg 11 cls_cnt 2 2006.133.07:47:22.34#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:22.40#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:22.40#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:22.42#ibcon#[27=AT06-04\r\n] 2006.133.07:47:22.45#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:22.45#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:47:22.45#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.07:47:22.45#ibcon#ireg 7 cls_cnt 0 2006.133.07:47:22.45#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:22.57#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:22.57#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:22.59#ibcon#[27=USB\r\n] 2006.133.07:47:22.62#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:22.62#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:47:22.62#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:47:22.62#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:47:22.62$vc4f8/vabw=wide 2006.133.07:47:22.62#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:47:22.62#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:47:22.62#ibcon#ireg 8 cls_cnt 0 2006.133.07:47:22.62#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:22.62#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:22.62#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:22.64#ibcon#[25=BW32\r\n] 2006.133.07:47:22.68#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:22.68#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:47:22.68#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:47:22.68#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:47:22.68$vc4f8/vbbw=wide 2006.133.07:47:22.68#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.07:47:22.68#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.07:47:22.68#ibcon#ireg 8 cls_cnt 0 2006.133.07:47:22.68#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:47:22.73#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:47:22.73#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:47:22.75#ibcon#[27=BW32\r\n] 2006.133.07:47:22.78#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:47:22.78#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:47:22.78#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:47:22.78#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:47:22.78$4f8m12a/ifd4f 2006.133.07:47:22.78$ifd4f/lo= 2006.133.07:47:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:47:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:47:22.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:47:22.79$ifd4f/patch= 2006.133.07:47:22.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:47:22.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:47:22.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:47:22.79$4f8m12a/"form=m,16.000,1:2 2006.133.07:47:22.79$4f8m12a/"tpicd 2006.133.07:47:22.79$4f8m12a/echo=off 2006.133.07:47:22.79$4f8m12a/xlog=off 2006.133.07:47:22.79:!2006.133.07:47:50 2006.133.07:47:32.13#trakl#Source acquired 2006.133.07:47:32.13#flagr#flagr/antenna,acquired 2006.133.07:47:50.01:preob 2006.133.07:47:51.13/onsource/TRACKING 2006.133.07:47:51.13:!2006.133.07:48:00 2006.133.07:48:00.00:data_valid=on 2006.133.07:48:00.00:midob 2006.133.07:48:00.13/onsource/TRACKING 2006.133.07:48:00.13/wx/11.40,1009.8,100 2006.133.07:48:00.24/cable/+6.5578E-03 2006.133.07:48:01.33/va/01,08,usb,yes,45,47 2006.133.07:48:01.33/va/02,07,usb,yes,45,47 2006.133.07:48:01.33/va/03,06,usb,yes,48,48 2006.133.07:48:01.33/va/04,07,usb,yes,46,50 2006.133.07:48:01.33/va/05,06,usb,yes,54,57 2006.133.07:48:01.33/va/06,05,usb,yes,55,55 2006.133.07:48:01.33/va/07,05,usb,yes,55,55 2006.133.07:48:01.33/va/08,06,usb,yes,51,50 2006.133.07:48:01.56/valo/01,532.99,yes,locked 2006.133.07:48:01.56/valo/02,572.99,yes,locked 2006.133.07:48:01.56/valo/03,672.99,yes,locked 2006.133.07:48:01.56/valo/04,832.99,yes,locked 2006.133.07:48:01.56/valo/05,652.99,yes,locked 2006.133.07:48:01.56/valo/06,772.99,yes,locked 2006.133.07:48:01.56/valo/07,832.99,yes,locked 2006.133.07:48:01.56/valo/08,852.99,yes,locked 2006.133.07:48:02.65/vb/01,04,usb,yes,30,29 2006.133.07:48:02.65/vb/02,04,usb,yes,32,34 2006.133.07:48:02.65/vb/03,04,usb,yes,28,32 2006.133.07:48:02.65/vb/04,04,usb,yes,29,29 2006.133.07:48:02.65/vb/05,04,usb,yes,28,32 2006.133.07:48:02.65/vb/06,04,usb,yes,29,32 2006.133.07:48:02.65/vb/07,04,usb,yes,31,31 2006.133.07:48:02.65/vb/08,04,usb,yes,28,32 2006.133.07:48:02.88/vblo/01,632.99,yes,locked 2006.133.07:48:02.88/vblo/02,640.99,yes,locked 2006.133.07:48:02.88/vblo/03,656.99,yes,locked 2006.133.07:48:02.88/vblo/04,712.99,yes,locked 2006.133.07:48:02.88/vblo/05,744.99,yes,locked 2006.133.07:48:02.88/vblo/06,752.99,yes,locked 2006.133.07:48:02.88/vblo/07,734.99,yes,locked 2006.133.07:48:02.88/vblo/08,744.99,yes,locked 2006.133.07:48:03.03/vabw/8 2006.133.07:48:03.18/vbbw/8 2006.133.07:48:03.27/xfe/off,on,15.2 2006.133.07:48:03.67/ifatt/23,28,28,28 2006.133.07:48:04.07/fmout-gps/S +1.88E-07 2006.133.07:48:04.12:!2006.133.07:49:00 2006.133.07:49:00.01:data_valid=off 2006.133.07:49:00.02:postob 2006.133.07:49:00.12/cable/+6.5577E-03 2006.133.07:49:00.13/wx/11.40,1009.9,100 2006.133.07:49:01.08/fmout-gps/S +1.88E-07 2006.133.07:49:01.09:scan_name=133-0749,k06133,60 2006.133.07:49:01.09:source=0955+476,095819.67,472507.8,2000.0,cw 2006.133.07:49:01.13#flagr#flagr/antenna,new-source 2006.133.07:49:02.13:checkk5 2006.133.07:49:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:49:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:49:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:49:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:49:03.99/chk_obsdata//k5ts1/T1330748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:49:04.36/chk_obsdata//k5ts2/T1330748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:49:04.73/chk_obsdata//k5ts3/T1330748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:49:05.10/chk_obsdata//k5ts4/T1330748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:49:05.79/k5log//k5ts1_log_newline 2006.133.07:49:06.48/k5log//k5ts2_log_newline 2006.133.07:49:07.16/k5log//k5ts3_log_newline 2006.133.07:49:07.85/k5log//k5ts4_log_newline 2006.133.07:49:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:49:07.87:4f8m12a=1 2006.133.07:49:07.87$4f8m12a/echo=on 2006.133.07:49:07.87$4f8m12a/pcalon 2006.133.07:49:07.87$pcalon/"no phase cal control is implemented here 2006.133.07:49:07.87$4f8m12a/"tpicd=stop 2006.133.07:49:07.87$4f8m12a/vc4f8 2006.133.07:49:07.87$vc4f8/valo=1,532.99 2006.133.07:49:07.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:49:07.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:49:07.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:07.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:07.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:07.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:49:07.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:07.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:07.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:49:07.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:49:07.96$vc4f8/va=1,8 2006.133.07:49:07.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:49:07.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:49:07.96#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:07.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:07.96#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:07.96#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:07.99#ibcon#[25=AT01-08\r\n] 2006.133.07:49:08.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:08.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:08.02#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:49:08.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:08.02#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:08.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:08.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:08.16#ibcon#[25=USB\r\n] 2006.133.07:49:08.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:08.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:08.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:49:08.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:49:08.19$vc4f8/valo=2,572.99 2006.133.07:49:08.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:49:08.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:49:08.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:08.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:08.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:08.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:49:08.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:08.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:08.26#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:49:08.26#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:49:08.26$vc4f8/va=2,7 2006.133.07:49:08.26#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:49:08.26#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:49:08.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:08.26#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:08.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:08.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:08.33#ibcon#[25=AT02-07\r\n] 2006.133.07:49:08.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:08.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:08.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:49:08.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:08.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:08.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:08.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:08.50#ibcon#[25=USB\r\n] 2006.133.07:49:08.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:08.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:08.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:49:08.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:49:08.53$vc4f8/valo=3,672.99 2006.133.07:49:08.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:49:08.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:49:08.53#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:08.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:08.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:08.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:49:08.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:08.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:08.60#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:49:08.60#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:49:08.60$vc4f8/va=3,6 2006.133.07:49:08.60#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:49:08.60#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:49:08.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:08.60#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:08.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:08.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:08.67#ibcon#[25=AT03-06\r\n] 2006.133.07:49:08.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:08.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:08.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:49:08.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:08.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:08.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:08.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:08.84#ibcon#[25=USB\r\n] 2006.133.07:49:08.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:08.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:08.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:49:08.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:49:08.87$vc4f8/valo=4,832.99 2006.133.07:49:08.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:49:08.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:49:08.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:08.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:08.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:08.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:08.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:49:08.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:08.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:08.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:49:08.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:49:08.93$vc4f8/va=4,7 2006.133.07:49:08.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:49:08.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:49:08.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:08.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:08.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:08.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:09.01#ibcon#[25=AT04-07\r\n] 2006.133.07:49:09.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:09.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:09.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:49:09.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:09.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:09.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:09.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:09.18#ibcon#[25=USB\r\n] 2006.133.07:49:09.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:09.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:09.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:49:09.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:49:09.21$vc4f8/valo=5,652.99 2006.133.07:49:09.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:49:09.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:49:09.21#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:09.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:09.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:09.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:09.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:49:09.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:09.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:09.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:49:09.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:49:09.27$vc4f8/va=5,6 2006.133.07:49:09.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:49:09.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:49:09.27#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:09.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:09.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:09.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:09.35#ibcon#[25=AT05-06\r\n] 2006.133.07:49:09.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:09.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:09.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:49:09.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:09.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:09.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:09.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:09.52#ibcon#[25=USB\r\n] 2006.133.07:49:09.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:09.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:09.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:49:09.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:49:09.55$vc4f8/valo=6,772.99 2006.133.07:49:09.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:49:09.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:49:09.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:09.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:09.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:09.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:09.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:49:09.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:09.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:09.61#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:49:09.61#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:49:09.61$vc4f8/va=6,5 2006.133.07:49:09.61#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.07:49:09.61#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.07:49:09.61#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:09.61#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:09.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:09.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:09.69#ibcon#[25=AT06-05\r\n] 2006.133.07:49:09.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:09.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:09.72#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.07:49:09.72#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:09.72#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:49:09.84#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:49:09.84#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:49:09.86#ibcon#[25=USB\r\n] 2006.133.07:49:09.89#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:49:09.89#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:49:09.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:49:09.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:49:09.89$vc4f8/valo=7,832.99 2006.133.07:49:09.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.07:49:09.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.07:49:09.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:09.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:49:09.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:49:09.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:49:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:49:09.95#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:49:09.95#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:49:09.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:49:09.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:49:09.95$vc4f8/va=7,5 2006.133.07:49:09.95#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.07:49:09.95#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.07:49:09.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:09.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:49:10.01#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:49:10.01#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:49:10.03#ibcon#[25=AT07-05\r\n] 2006.133.07:49:10.06#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:49:10.06#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:49:10.06#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.07:49:10.06#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:10.06#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:49:10.18#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:49:10.18#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:49:10.20#ibcon#[25=USB\r\n] 2006.133.07:49:10.23#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:49:10.23#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:49:10.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:49:10.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:49:10.23$vc4f8/valo=8,852.99 2006.133.07:49:10.23#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:49:10.23#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:49:10.23#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:10.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:49:10.23#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:49:10.23#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:49:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:49:10.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:49:10.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:49:10.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:49:10.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:49:10.30$vc4f8/va=8,6 2006.133.07:49:10.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:49:10.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:49:10.30#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:10.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:49:10.35#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:49:10.35#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:49:10.37#ibcon#[25=AT08-06\r\n] 2006.133.07:49:10.40#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:49:10.40#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:49:10.40#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:49:10.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:10.40#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:49:10.52#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:49:10.52#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:49:10.54#ibcon#[25=USB\r\n] 2006.133.07:49:10.57#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:49:10.57#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:49:10.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:49:10.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:49:10.57$vc4f8/vblo=1,632.99 2006.133.07:49:10.57#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:49:10.57#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:49:10.57#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:10.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:49:10.57#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:49:10.57#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:49:10.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:49:10.63#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:49:10.63#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:49:10.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:49:10.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:49:10.63$vc4f8/vb=1,4 2006.133.07:49:10.63#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.07:49:10.63#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.07:49:10.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:10.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:49:10.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:49:10.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:49:10.65#ibcon#[27=AT01-04\r\n] 2006.133.07:49:10.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:49:10.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:49:10.68#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.07:49:10.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:10.68#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:49:10.80#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:49:10.80#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:49:10.82#ibcon#[27=USB\r\n] 2006.133.07:49:10.85#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:49:10.85#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:49:10.85#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:49:10.85#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:49:10.85$vc4f8/vblo=2,640.99 2006.133.07:49:10.85#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:49:10.85#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:49:10.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:10.85#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:10.85#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:10.85#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:10.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:49:10.91#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:10.91#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:49:10.91#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:49:10.91#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:49:10.91$vc4f8/vb=2,4 2006.133.07:49:10.91#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:49:10.91#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:49:10.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:10.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:10.97#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:10.97#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:10.99#ibcon#[27=AT02-04\r\n] 2006.133.07:49:11.03#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:11.03#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:49:11.03#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:49:11.03#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:11.03#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:11.14#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:11.14#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:11.16#ibcon#[27=USB\r\n] 2006.133.07:49:11.19#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:11.19#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:49:11.19#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:49:11.19#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:49:11.19$vc4f8/vblo=3,656.99 2006.133.07:49:11.19#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:49:11.19#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:49:11.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:11.19#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:11.19#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:11.19#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:49:11.25#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:11.25#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:49:11.25#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:49:11.25#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:49:11.25$vc4f8/vb=3,4 2006.133.07:49:11.25#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:49:11.25#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:49:11.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:11.25#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:11.31#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:11.31#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:11.33#ibcon#[27=AT03-04\r\n] 2006.133.07:49:11.36#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:11.36#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:49:11.36#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:49:11.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:11.36#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:11.48#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:11.48#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:11.50#ibcon#[27=USB\r\n] 2006.133.07:49:11.53#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:11.53#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:49:11.53#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:49:11.53#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:49:11.53$vc4f8/vblo=4,712.99 2006.133.07:49:11.53#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:49:11.53#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:49:11.53#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:11.53#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:11.53#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:11.53#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:11.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:49:11.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:11.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:49:11.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:49:11.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:49:11.59$vc4f8/vb=4,4 2006.133.07:49:11.59#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:49:11.59#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:49:11.59#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:11.59#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:11.65#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:11.65#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:11.67#ibcon#[27=AT04-04\r\n] 2006.133.07:49:11.70#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:11.70#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:49:11.70#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:49:11.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:11.70#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:11.82#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:11.82#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:11.84#ibcon#[27=USB\r\n] 2006.133.07:49:11.87#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:11.87#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:49:11.87#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:49:11.87#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:49:11.87$vc4f8/vblo=5,744.99 2006.133.07:49:11.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:49:11.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:49:11.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:11.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:11.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:11.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:11.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:49:11.93#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:11.93#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:49:11.93#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:49:11.93#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:49:11.93$vc4f8/vb=5,4 2006.133.07:49:11.93#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:49:11.93#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:49:11.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:11.93#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:11.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:11.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:12.01#ibcon#[27=AT05-04\r\n] 2006.133.07:49:12.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:12.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:49:12.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:49:12.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:12.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:12.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:12.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:12.18#ibcon#[27=USB\r\n] 2006.133.07:49:12.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:12.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:49:12.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:49:12.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:49:12.21$vc4f8/vblo=6,752.99 2006.133.07:49:12.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:49:12.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:49:12.21#ibcon#ireg 17 cls_cnt 0 2006.133.07:49:12.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:12.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:12.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:12.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:49:12.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:12.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:49:12.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:49:12.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:49:12.27$vc4f8/vb=6,4 2006.133.07:49:12.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:49:12.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:49:12.27#ibcon#ireg 11 cls_cnt 2 2006.133.07:49:12.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:12.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:12.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:12.35#ibcon#[27=AT06-04\r\n] 2006.133.07:49:12.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:12.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:49:12.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:49:12.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:49:12.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:12.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:12.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:12.52#ibcon#[27=USB\r\n] 2006.133.07:49:12.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:12.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:49:12.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:49:12.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:49:12.55$vc4f8/vabw=wide 2006.133.07:49:12.55#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:49:12.55#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:49:12.55#ibcon#ireg 8 cls_cnt 0 2006.133.07:49:12.55#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:12.55#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:12.55#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:12.57#ibcon#[25=BW32\r\n] 2006.133.07:49:12.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:12.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:49:12.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:49:12.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:49:12.60$vc4f8/vbbw=wide 2006.133.07:49:12.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:49:12.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:49:12.60#ibcon#ireg 8 cls_cnt 0 2006.133.07:49:12.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:49:12.67#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:49:12.67#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:49:12.69#ibcon#[27=BW32\r\n] 2006.133.07:49:12.72#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:49:12.72#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:49:12.72#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:49:12.72#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:49:12.72$4f8m12a/ifd4f 2006.133.07:49:12.72$ifd4f/lo= 2006.133.07:49:12.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:49:12.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:49:12.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:49:12.72$ifd4f/patch= 2006.133.07:49:12.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:49:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:49:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:49:12.73$4f8m12a/"form=m,16.000,1:2 2006.133.07:49:12.73$4f8m12a/"tpicd 2006.133.07:49:12.73$4f8m12a/echo=off 2006.133.07:49:12.73$4f8m12a/xlog=off 2006.133.07:49:12.73:!2006.133.07:49:40 2006.133.07:49:25.13#trakl#Source acquired 2006.133.07:49:25.13#flagr#flagr/antenna,acquired 2006.133.07:49:40.01:preob 2006.133.07:49:41.14/onsource/TRACKING 2006.133.07:49:41.14:!2006.133.07:49:50 2006.133.07:49:50.00:data_valid=on 2006.133.07:49:50.00:midob 2006.133.07:49:50.14/onsource/TRACKING 2006.133.07:49:50.14/wx/11.40,1009.9,100 2006.133.07:49:50.28/cable/+6.5562E-03 2006.133.07:49:51.37/va/01,08,usb,yes,47,49 2006.133.07:49:51.37/va/02,07,usb,yes,47,49 2006.133.07:49:51.37/va/03,06,usb,yes,50,50 2006.133.07:49:51.37/va/04,07,usb,yes,48,52 2006.133.07:49:51.37/va/05,06,usb,yes,56,60 2006.133.07:49:51.37/va/06,05,usb,yes,58,57 2006.133.07:49:51.37/va/07,05,usb,yes,57,57 2006.133.07:49:51.37/va/08,06,usb,yes,54,53 2006.133.07:49:51.60/valo/01,532.99,yes,locked 2006.133.07:49:51.60/valo/02,572.99,yes,locked 2006.133.07:49:51.60/valo/03,672.99,yes,locked 2006.133.07:49:51.60/valo/04,832.99,yes,locked 2006.133.07:49:51.60/valo/05,652.99,yes,locked 2006.133.07:49:51.60/valo/06,772.99,yes,locked 2006.133.07:49:51.60/valo/07,832.99,yes,locked 2006.133.07:49:51.60/valo/08,852.99,yes,locked 2006.133.07:49:52.69/vb/01,04,usb,yes,30,29 2006.133.07:49:52.69/vb/02,04,usb,yes,32,34 2006.133.07:49:52.69/vb/03,04,usb,yes,28,32 2006.133.07:49:52.69/vb/04,04,usb,yes,29,30 2006.133.07:49:52.69/vb/05,04,usb,yes,28,32 2006.133.07:49:52.69/vb/06,04,usb,yes,29,32 2006.133.07:49:52.69/vb/07,04,usb,yes,31,31 2006.133.07:49:52.69/vb/08,04,usb,yes,28,32 2006.133.07:49:52.92/vblo/01,632.99,yes,locked 2006.133.07:49:52.92/vblo/02,640.99,yes,locked 2006.133.07:49:52.92/vblo/03,656.99,yes,locked 2006.133.07:49:52.92/vblo/04,712.99,yes,locked 2006.133.07:49:52.92/vblo/05,744.99,yes,locked 2006.133.07:49:52.92/vblo/06,752.99,yes,locked 2006.133.07:49:52.92/vblo/07,734.99,yes,locked 2006.133.07:49:52.92/vblo/08,744.99,yes,locked 2006.133.07:49:53.07/vabw/8 2006.133.07:49:53.22/vbbw/8 2006.133.07:49:53.31/xfe/off,on,15.2 2006.133.07:49:53.69/ifatt/23,28,28,28 2006.133.07:49:54.08/fmout-gps/S +1.88E-07 2006.133.07:49:54.12:!2006.133.07:50:50 2006.133.07:50:50.01:data_valid=off 2006.133.07:50:50.02:postob 2006.133.07:50:50.12/cable/+6.5570E-03 2006.133.07:50:50.13/wx/11.39,1009.9,100 2006.133.07:50:51.07/fmout-gps/S +1.88E-07 2006.133.07:50:51.08:scan_name=133-0751,k06133,60 2006.133.07:50:51.08:source=1044+719,104827.62,714335.9,2000.0,cw 2006.133.07:50:51.14#flagr#flagr/antenna,new-source 2006.133.07:50:52.14:checkk5 2006.133.07:50:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:50:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:50:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:50:53.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:50:54.00/chk_obsdata//k5ts1/T1330749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:50:54.37/chk_obsdata//k5ts2/T1330749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:50:54.73/chk_obsdata//k5ts3/T1330749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:50:55.10/chk_obsdata//k5ts4/T1330749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:50:55.79/k5log//k5ts1_log_newline 2006.133.07:50:56.48/k5log//k5ts2_log_newline 2006.133.07:50:57.16/k5log//k5ts3_log_newline 2006.133.07:50:57.85/k5log//k5ts4_log_newline 2006.133.07:50:57.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:50:57.87:4f8m12a=1 2006.133.07:50:57.87$4f8m12a/echo=on 2006.133.07:50:57.87$4f8m12a/pcalon 2006.133.07:50:57.87$pcalon/"no phase cal control is implemented here 2006.133.07:50:57.87$4f8m12a/"tpicd=stop 2006.133.07:50:57.87$4f8m12a/vc4f8 2006.133.07:50:57.87$vc4f8/valo=1,532.99 2006.133.07:50:57.88#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:50:57.88#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:50:57.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:57.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:50:57.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:50:57.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:50:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:50:57.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:50:57.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:50:57.96#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:50:57.96#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:50:57.96$vc4f8/va=1,8 2006.133.07:50:57.96#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:50:57.96#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:50:57.96#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:57.96#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:50:57.96#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:50:57.96#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:50:58.00#ibcon#[25=AT01-08\r\n] 2006.133.07:50:58.02#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:50:58.02#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:50:58.02#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:50:58.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:58.02#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:50:58.14#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:50:58.14#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:50:58.16#ibcon#[25=USB\r\n] 2006.133.07:50:58.19#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:50:58.19#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:50:58.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:50:58.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:50:58.19$vc4f8/valo=2,572.99 2006.133.07:50:58.19#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:50:58.19#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:50:58.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:58.19#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:50:58.19#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:50:58.19#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:50:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:50:58.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:50:58.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:50:58.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:50:58.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:50:58.26$vc4f8/va=2,7 2006.133.07:50:58.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.07:50:58.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.07:50:58.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:58.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:50:58.31#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:50:58.31#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:50:58.33#ibcon#[25=AT02-07\r\n] 2006.133.07:50:58.36#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:50:58.36#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:50:58.36#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.07:50:58.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:58.36#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:50:58.48#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:50:58.48#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:50:58.50#ibcon#[25=USB\r\n] 2006.133.07:50:58.55#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:50:58.55#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:50:58.55#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:50:58.55#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:50:58.55$vc4f8/valo=3,672.99 2006.133.07:50:58.55#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:50:58.55#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:50:58.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:58.55#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:50:58.55#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:50:58.55#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:50:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:50:58.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:50:58.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:50:58.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:50:58.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:50:58.60$vc4f8/va=3,6 2006.133.07:50:58.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:50:58.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:50:58.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:58.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:50:58.67#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:50:58.67#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:50:58.69#ibcon#[25=AT03-06\r\n] 2006.133.07:50:58.72#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:50:58.72#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:50:58.72#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:50:58.72#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:58.72#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:50:58.84#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:50:58.84#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:50:58.86#ibcon#[25=USB\r\n] 2006.133.07:50:58.89#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:50:58.89#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:50:58.89#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:50:58.89#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:50:58.89$vc4f8/valo=4,832.99 2006.133.07:50:58.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.07:50:58.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.07:50:58.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:58.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:50:58.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:50:58.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:50:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:50:58.95#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:50:58.95#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:50:58.95#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:50:58.95#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:50:58.95$vc4f8/va=4,7 2006.133.07:50:58.95#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.07:50:58.95#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.07:50:58.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:58.95#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:50:59.01#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:50:59.01#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:50:59.03#ibcon#[25=AT04-07\r\n] 2006.133.07:50:59.06#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:50:59.06#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:50:59.06#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.07:50:59.06#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:59.06#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:50:59.18#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:50:59.18#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:50:59.20#ibcon#[25=USB\r\n] 2006.133.07:50:59.23#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:50:59.23#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:50:59.23#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:50:59.23#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:50:59.23$vc4f8/valo=5,652.99 2006.133.07:50:59.23#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:50:59.23#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:50:59.23#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:59.23#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:50:59.23#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:50:59.23#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:50:59.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:50:59.29#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:50:59.29#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:50:59.29#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:50:59.29#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:50:59.29$vc4f8/va=5,6 2006.133.07:50:59.29#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.07:50:59.29#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.07:50:59.29#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:59.29#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:50:59.35#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:50:59.35#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:50:59.37#ibcon#[25=AT05-06\r\n] 2006.133.07:50:59.40#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:50:59.40#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:50:59.40#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.07:50:59.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:59.40#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:50:59.52#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:50:59.52#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:50:59.54#ibcon#[25=USB\r\n] 2006.133.07:50:59.57#abcon#<5=/02 0.9 2.5 11.391001009.9\r\n> 2006.133.07:50:59.57#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:50:59.57#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:50:59.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:50:59.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:50:59.57$vc4f8/valo=6,772.99 2006.133.07:50:59.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:50:59.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:50:59.57#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:59.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:50:59.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:50:59.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:50:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:50:59.59#abcon#{5=INTERFACE CLEAR} 2006.133.07:50:59.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:50:59.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:50:59.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:50:59.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:50:59.63$vc4f8/va=6,5 2006.133.07:50:59.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:50:59.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:50:59.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:59.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:50:59.65#abcon#[5=S1D000X0/0*\r\n] 2006.133.07:50:59.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:50:59.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:50:59.71#ibcon#[25=AT06-05\r\n] 2006.133.07:50:59.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:50:59.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:50:59.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:50:59.74#ibcon#ireg 7 cls_cnt 0 2006.133.07:50:59.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:50:59.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:50:59.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:50:59.88#ibcon#[25=USB\r\n] 2006.133.07:50:59.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:50:59.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:50:59.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:50:59.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:50:59.91$vc4f8/valo=7,832.99 2006.133.07:50:59.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.07:50:59.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.07:50:59.91#ibcon#ireg 17 cls_cnt 0 2006.133.07:50:59.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:50:59.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:50:59.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:50:59.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:50:59.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:50:59.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.07:50:59.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:50:59.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:50:59.97$vc4f8/va=7,5 2006.133.07:50:59.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.07:50:59.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.07:50:59.97#ibcon#ireg 11 cls_cnt 2 2006.133.07:50:59.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:51:00.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:51:00.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:51:00.05#ibcon#[25=AT07-05\r\n] 2006.133.07:51:00.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:51:00.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.07:51:00.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.07:51:00.08#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:00.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:51:00.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:51:00.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:51:00.22#ibcon#[25=USB\r\n] 2006.133.07:51:00.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:51:00.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.07:51:00.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:51:00.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:51:00.27$vc4f8/valo=8,852.99 2006.133.07:51:00.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.07:51:00.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.07:51:00.27#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:00.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:51:00.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:51:00.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:51:00.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:51:00.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:51:00.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.07:51:00.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:51:00.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:51:00.32$vc4f8/va=8,6 2006.133.07:51:00.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.07:51:00.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.07:51:00.32#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:00.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:51:00.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:51:00.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:51:00.41#ibcon#[25=AT08-06\r\n] 2006.133.07:51:00.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:51:00.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.07:51:00.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.07:51:00.44#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:00.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:51:00.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:51:00.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:51:00.58#ibcon#[25=USB\r\n] 2006.133.07:51:00.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:51:00.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.07:51:00.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:51:00.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:51:00.61$vc4f8/vblo=1,632.99 2006.133.07:51:00.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.07:51:00.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.07:51:00.61#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:00.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:51:00.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:51:00.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:51:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:51:00.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:51:00.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.07:51:00.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:51:00.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:51:00.67$vc4f8/vb=1,4 2006.133.07:51:00.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.07:51:00.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.07:51:00.67#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:00.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:51:00.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:51:00.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:51:00.69#ibcon#[27=AT01-04\r\n] 2006.133.07:51:00.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:51:00.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.07:51:00.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.07:51:00.72#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:00.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:51:00.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:51:00.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:51:00.86#ibcon#[27=USB\r\n] 2006.133.07:51:00.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:51:00.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.07:51:00.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:51:00.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:51:00.89$vc4f8/vblo=2,640.99 2006.133.07:51:00.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.07:51:00.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.07:51:00.89#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:00.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:51:00.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:51:00.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:51:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:51:00.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:51:00.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.07:51:00.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:51:00.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:51:00.95$vc4f8/vb=2,4 2006.133.07:51:00.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.07:51:00.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.07:51:00.95#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:00.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:51:01.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:51:01.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:51:01.03#ibcon#[27=AT02-04\r\n] 2006.133.07:51:01.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:51:01.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.07:51:01.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.07:51:01.06#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:01.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:51:01.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:51:01.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:51:01.20#ibcon#[27=USB\r\n] 2006.133.07:51:01.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:51:01.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.07:51:01.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:51:01.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:51:01.23$vc4f8/vblo=3,656.99 2006.133.07:51:01.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.07:51:01.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.07:51:01.23#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:01.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:51:01.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:51:01.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:51:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:51:01.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:51:01.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.07:51:01.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:51:01.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:51:01.29$vc4f8/vb=3,4 2006.133.07:51:01.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:51:01.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:51:01.29#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:01.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:51:01.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:51:01.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:51:01.37#ibcon#[27=AT03-04\r\n] 2006.133.07:51:01.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:51:01.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:51:01.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:51:01.40#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:01.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:51:01.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:51:01.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:51:01.54#ibcon#[27=USB\r\n] 2006.133.07:51:01.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:51:01.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:51:01.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:51:01.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:51:01.57$vc4f8/vblo=4,712.99 2006.133.07:51:01.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.07:51:01.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.07:51:01.57#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:01.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:51:01.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:51:01.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:51:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:51:01.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:51:01.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.07:51:01.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:51:01.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:51:01.63$vc4f8/vb=4,4 2006.133.07:51:01.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.07:51:01.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.07:51:01.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:01.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:51:01.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:51:01.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:51:01.71#ibcon#[27=AT04-04\r\n] 2006.133.07:51:01.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:51:01.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.07:51:01.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.07:51:01.74#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:01.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:51:01.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:51:01.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:51:01.88#ibcon#[27=USB\r\n] 2006.133.07:51:01.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:51:01.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.07:51:01.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:51:01.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:51:01.91$vc4f8/vblo=5,744.99 2006.133.07:51:01.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:51:01.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:51:01.91#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:01.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:51:01.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:51:01.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:51:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:51:01.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:51:01.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:51:01.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:51:01.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:51:01.97$vc4f8/vb=5,4 2006.133.07:51:01.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.07:51:01.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.07:51:01.97#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:01.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:51:02.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:51:02.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:51:02.05#ibcon#[27=AT05-04\r\n] 2006.133.07:51:02.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:51:02.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.07:51:02.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.07:51:02.08#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:02.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:51:02.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:51:02.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:51:02.22#ibcon#[27=USB\r\n] 2006.133.07:51:02.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:51:02.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.07:51:02.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:51:02.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:51:02.25$vc4f8/vblo=6,752.99 2006.133.07:51:02.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.07:51:02.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.07:51:02.25#ibcon#ireg 17 cls_cnt 0 2006.133.07:51:02.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:51:02.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:51:02.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:51:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:51:02.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:51:02.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.07:51:02.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:51:02.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:51:02.31$vc4f8/vb=6,4 2006.133.07:51:02.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.07:51:02.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.07:51:02.31#ibcon#ireg 11 cls_cnt 2 2006.133.07:51:02.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:51:02.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:51:02.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:51:02.39#ibcon#[27=AT06-04\r\n] 2006.133.07:51:02.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:51:02.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.07:51:02.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.07:51:02.42#ibcon#ireg 7 cls_cnt 0 2006.133.07:51:02.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:51:02.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:51:02.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:51:02.56#ibcon#[27=USB\r\n] 2006.133.07:51:02.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:51:02.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.07:51:02.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:51:02.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:51:02.59$vc4f8/vabw=wide 2006.133.07:51:02.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.07:51:02.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.07:51:02.59#ibcon#ireg 8 cls_cnt 0 2006.133.07:51:02.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:51:02.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:51:02.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:51:02.61#ibcon#[25=BW32\r\n] 2006.133.07:51:02.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:51:02.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.07:51:02.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:51:02.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:51:02.64$vc4f8/vbbw=wide 2006.133.07:51:02.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:51:02.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:51:02.64#ibcon#ireg 8 cls_cnt 0 2006.133.07:51:02.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:51:02.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:51:02.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:51:02.73#ibcon#[27=BW32\r\n] 2006.133.07:51:02.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:51:02.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:51:02.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:51:02.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:51:02.76$4f8m12a/ifd4f 2006.133.07:51:02.76$ifd4f/lo= 2006.133.07:51:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:51:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:51:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:51:02.76$ifd4f/patch= 2006.133.07:51:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:51:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:51:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:51:02.76$4f8m12a/"form=m,16.000,1:2 2006.133.07:51:02.77$4f8m12a/"tpicd 2006.133.07:51:02.77$4f8m12a/echo=off 2006.133.07:51:02.77$4f8m12a/xlog=off 2006.133.07:51:02.77:!2006.133.07:51:30 2006.133.07:51:12.14#trakl#Source acquired 2006.133.07:51:12.14#flagr#flagr/antenna,acquired 2006.133.07:51:30.01:preob 2006.133.07:51:31.14/onsource/TRACKING 2006.133.07:51:31.14:!2006.133.07:51:40 2006.133.07:51:40.00:data_valid=on 2006.133.07:51:40.00:midob 2006.133.07:51:40.14/onsource/TRACKING 2006.133.07:51:40.14/wx/11.38,1009.9,100 2006.133.07:51:40.32/cable/+6.5590E-03 2006.133.07:51:41.41/va/01,08,usb,yes,49,52 2006.133.07:51:41.41/va/02,07,usb,yes,50,52 2006.133.07:51:41.41/va/03,06,usb,yes,53,53 2006.133.07:51:41.41/va/04,07,usb,yes,51,55 2006.133.07:51:41.41/va/05,06,usb,yes,59,62 2006.133.07:51:41.41/va/06,05,usb,yes,60,60 2006.133.07:51:41.41/va/07,05,usb,yes,60,60 2006.133.07:51:41.41/va/08,06,usb,yes,56,55 2006.133.07:51:41.64/valo/01,532.99,yes,locked 2006.133.07:51:41.64/valo/02,572.99,yes,locked 2006.133.07:51:41.64/valo/03,672.99,yes,locked 2006.133.07:51:41.64/valo/04,832.99,yes,locked 2006.133.07:51:41.64/valo/05,652.99,yes,locked 2006.133.07:51:41.64/valo/06,772.99,yes,locked 2006.133.07:51:41.64/valo/07,832.99,yes,locked 2006.133.07:51:41.64/valo/08,852.99,yes,locked 2006.133.07:51:42.73/vb/01,04,usb,yes,31,29 2006.133.07:51:42.73/vb/02,04,usb,yes,32,34 2006.133.07:51:42.73/vb/03,04,usb,yes,29,32 2006.133.07:51:42.73/vb/04,04,usb,yes,30,30 2006.133.07:51:42.73/vb/05,04,usb,yes,28,32 2006.133.07:51:42.73/vb/06,04,usb,yes,29,32 2006.133.07:51:42.73/vb/07,04,usb,yes,31,31 2006.133.07:51:42.73/vb/08,04,usb,yes,29,32 2006.133.07:51:42.96/vblo/01,632.99,yes,locked 2006.133.07:51:42.96/vblo/02,640.99,yes,locked 2006.133.07:51:42.96/vblo/03,656.99,yes,locked 2006.133.07:51:42.96/vblo/04,712.99,yes,locked 2006.133.07:51:42.96/vblo/05,744.99,yes,locked 2006.133.07:51:42.96/vblo/06,752.99,yes,locked 2006.133.07:51:42.96/vblo/07,734.99,yes,locked 2006.133.07:51:42.96/vblo/08,744.99,yes,locked 2006.133.07:51:43.11/vabw/8 2006.133.07:51:43.26/vbbw/8 2006.133.07:51:43.35/xfe/off,on,14.7 2006.133.07:51:43.73/ifatt/23,28,28,28 2006.133.07:51:44.07/fmout-gps/S +1.90E-07 2006.133.07:51:44.11:!2006.133.07:52:40 2006.133.07:52:40.00:data_valid=off 2006.133.07:52:40.01:postob 2006.133.07:52:40.09/cable/+6.5573E-03 2006.133.07:52:40.10/wx/11.36,1009.9,100 2006.133.07:52:41.07/fmout-gps/S +1.89E-07 2006.133.07:52:41.08:scan_name=133-0753,k06133,60 2006.133.07:52:41.08:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.133.07:52:41.15#flagr#flagr/antenna,new-source 2006.133.07:52:42.13:checkk5 2006.133.07:52:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:52:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:52:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:52:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:52:43.99/chk_obsdata//k5ts1/T1330751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:52:44.36/chk_obsdata//k5ts2/T1330751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:52:44.72/chk_obsdata//k5ts3/T1330751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:52:45.09/chk_obsdata//k5ts4/T1330751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:52:45.78/k5log//k5ts1_log_newline 2006.133.07:52:46.46/k5log//k5ts2_log_newline 2006.133.07:52:47.14/k5log//k5ts3_log_newline 2006.133.07:52:47.83/k5log//k5ts4_log_newline 2006.133.07:52:47.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:52:47.85:4f8m12a=1 2006.133.07:52:47.85$4f8m12a/echo=on 2006.133.07:52:47.85$4f8m12a/pcalon 2006.133.07:52:47.85$pcalon/"no phase cal control is implemented here 2006.133.07:52:47.85$4f8m12a/"tpicd=stop 2006.133.07:52:47.85$4f8m12a/vc4f8 2006.133.07:52:47.85$vc4f8/valo=1,532.99 2006.133.07:52:47.86#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:52:47.86#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:52:47.86#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:47.86#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:47.86#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:47.86#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:47.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:52:47.94#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:47.94#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:47.94#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:52:47.94#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:52:47.94$vc4f8/va=1,8 2006.133.07:52:47.94#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:52:47.94#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:52:47.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:47.94#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:47.94#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:47.94#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:47.97#ibcon#[25=AT01-08\r\n] 2006.133.07:52:48.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:48.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:48.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:52:48.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:48.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:48.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:48.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:48.14#ibcon#[25=USB\r\n] 2006.133.07:52:48.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:48.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:48.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:52:48.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:52:48.17$vc4f8/valo=2,572.99 2006.133.07:52:48.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:52:48.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:52:48.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:48.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:48.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:48.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:52:48.24#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:48.24#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:48.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:52:48.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:52:48.24$vc4f8/va=2,7 2006.133.07:52:48.24#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:52:48.24#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:52:48.24#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:48.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:48.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:48.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:48.31#ibcon#[25=AT02-07\r\n] 2006.133.07:52:48.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:48.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:48.34#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:52:48.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:48.34#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:48.46#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:48.46#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:48.48#ibcon#[25=USB\r\n] 2006.133.07:52:48.51#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:48.51#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:48.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:52:48.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:52:48.51$vc4f8/valo=3,672.99 2006.133.07:52:48.51#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.07:52:48.51#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.07:52:48.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:48.51#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:52:48.51#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:52:48.51#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:52:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:52:48.58#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:52:48.58#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.07:52:48.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:52:48.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:52:48.58$vc4f8/va=3,6 2006.133.07:52:48.58#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.07:52:48.58#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.07:52:48.58#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:48.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:52:48.63#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:52:48.63#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:52:48.65#ibcon#[25=AT03-06\r\n] 2006.133.07:52:48.68#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:52:48.68#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.07:52:48.68#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.07:52:48.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:48.68#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:52:48.80#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:52:48.80#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:52:48.82#ibcon#[25=USB\r\n] 2006.133.07:52:48.85#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:52:48.85#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.07:52:48.85#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:52:48.85#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:52:48.85$vc4f8/valo=4,832.99 2006.133.07:52:48.85#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.07:52:48.85#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.07:52:48.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:48.85#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:52:48.85#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:52:48.85#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:52:48.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:52:48.91#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:52:48.91#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.07:52:48.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:52:48.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:52:48.91$vc4f8/va=4,7 2006.133.07:52:48.91#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.07:52:48.91#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.07:52:48.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:48.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:52:48.97#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:52:48.97#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:52:48.99#ibcon#[25=AT04-07\r\n] 2006.133.07:52:49.02#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:52:49.02#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.07:52:49.02#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.07:52:49.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:49.02#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:52:49.14#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:52:49.14#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:52:49.16#ibcon#[25=USB\r\n] 2006.133.07:52:49.19#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:52:49.19#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.07:52:49.19#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:52:49.19#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:52:49.19$vc4f8/valo=5,652.99 2006.133.07:52:49.19#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:52:49.19#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:52:49.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:49.19#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:49.19#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:49.19#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:49.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:52:49.25#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:49.25#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:49.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:52:49.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:52:49.25$vc4f8/va=5,6 2006.133.07:52:49.25#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:52:49.25#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:52:49.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:49.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:49.31#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:49.31#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:49.33#ibcon#[25=AT05-06\r\n] 2006.133.07:52:49.36#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:49.36#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:49.36#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:52:49.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:49.36#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:49.48#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:49.48#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:49.50#ibcon#[25=USB\r\n] 2006.133.07:52:49.53#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:49.53#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:49.53#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:52:49.53#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:52:49.53$vc4f8/valo=6,772.99 2006.133.07:52:49.53#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:52:49.53#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:52:49.53#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:49.53#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:49.53#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:49.53#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:49.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:52:49.59#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:49.59#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:49.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:52:49.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:52:49.59$vc4f8/va=6,5 2006.133.07:52:49.59#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:52:49.59#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:52:49.59#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:49.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:49.65#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:49.65#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:49.67#ibcon#[25=AT06-05\r\n] 2006.133.07:52:49.70#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:49.70#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:49.70#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:52:49.70#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:49.70#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:49.82#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:49.82#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:49.84#ibcon#[25=USB\r\n] 2006.133.07:52:49.87#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:49.87#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:49.87#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:52:49.87#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:52:49.87$vc4f8/valo=7,832.99 2006.133.07:52:49.87#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:52:49.87#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:52:49.87#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:49.87#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:49.87#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:49.87#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:49.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:52:49.93#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:49.93#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:49.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:52:49.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:52:49.93$vc4f8/va=7,5 2006.133.07:52:49.93#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.07:52:49.93#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.07:52:49.93#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:49.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:49.99#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:49.99#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:50.01#ibcon#[25=AT07-05\r\n] 2006.133.07:52:50.04#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:50.04#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:50.04#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.07:52:50.04#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:50.04#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:52:50.16#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:52:50.16#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:52:50.18#ibcon#[25=USB\r\n] 2006.133.07:52:50.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:52:50.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.07:52:50.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:52:50.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:52:50.21$vc4f8/valo=8,852.99 2006.133.07:52:50.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.07:52:50.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.07:52:50.21#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:50.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:52:50.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:52:50.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:52:50.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:52:50.27#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:52:50.27#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.07:52:50.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:52:50.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:52:50.27$vc4f8/va=8,6 2006.133.07:52:50.27#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.07:52:50.27#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.07:52:50.27#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:50.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:52:50.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:52:50.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:52:50.35#ibcon#[25=AT08-06\r\n] 2006.133.07:52:50.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:52:50.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.07:52:50.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.07:52:50.38#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:50.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:52:50.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:52:50.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:52:50.52#ibcon#[25=USB\r\n] 2006.133.07:52:50.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:52:50.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.07:52:50.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:52:50.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:52:50.55$vc4f8/vblo=1,632.99 2006.133.07:52:50.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.07:52:50.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.07:52:50.55#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:50.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:52:50.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:52:50.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:52:50.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:52:50.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:52:50.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.07:52:50.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:52:50.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:52:50.61$vc4f8/vb=1,4 2006.133.07:52:50.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.07:52:50.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.07:52:50.61#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:50.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:52:50.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:52:50.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:52:50.63#ibcon#[27=AT01-04\r\n] 2006.133.07:52:50.66#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:52:50.66#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.07:52:50.66#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.07:52:50.66#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:50.66#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:52:50.78#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:52:50.78#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:52:50.80#ibcon#[27=USB\r\n] 2006.133.07:52:50.83#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:52:50.83#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.07:52:50.83#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:52:50.83#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:52:50.83$vc4f8/vblo=2,640.99 2006.133.07:52:50.83#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.07:52:50.83#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.07:52:50.83#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:50.83#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:50.83#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:50.83#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:50.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:52:50.89#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:50.89#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.07:52:50.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:52:50.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:52:50.89$vc4f8/vb=2,4 2006.133.07:52:50.89#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.07:52:50.89#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.07:52:50.89#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:50.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:50.95#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:50.95#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:50.97#ibcon#[27=AT02-04\r\n] 2006.133.07:52:51.00#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:51.00#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.07:52:51.00#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.07:52:51.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:51.00#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:51.12#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:51.12#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:51.14#ibcon#[27=USB\r\n] 2006.133.07:52:51.17#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:51.17#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.07:52:51.17#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:52:51.17#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:52:51.17$vc4f8/vblo=3,656.99 2006.133.07:52:51.17#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.07:52:51.17#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.07:52:51.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:51.17#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:51.17#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:51.17#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:51.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:52:51.23#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:51.23#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.07:52:51.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:52:51.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:52:51.23$vc4f8/vb=3,4 2006.133.07:52:51.23#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.07:52:51.23#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.07:52:51.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:51.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:51.29#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:51.29#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:51.31#ibcon#[27=AT03-04\r\n] 2006.133.07:52:51.34#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:51.34#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.07:52:51.34#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.07:52:51.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:51.34#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:51.46#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:51.46#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:51.48#ibcon#[27=USB\r\n] 2006.133.07:52:51.51#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:51.51#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.07:52:51.51#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:52:51.51#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:52:51.51$vc4f8/vblo=4,712.99 2006.133.07:52:51.51#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:52:51.51#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:52:51.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:51.51#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:52:51.51#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:52:51.51#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:52:51.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:52:51.55#abcon#<5=/02 0.8 2.4 11.361001009.8\r\n> 2006.133.07:52:51.57#abcon#{5=INTERFACE CLEAR} 2006.133.07:52:51.57#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:52:51.57#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:52:51.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:52:51.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:52:51.57$vc4f8/vb=4,4 2006.133.07:52:51.57#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.07:52:51.57#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.07:52:51.57#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:51.57#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:52:51.63#abcon#[5=S1D000X0/0*\r\n] 2006.133.07:52:51.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:52:51.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:52:51.65#ibcon#[27=AT04-04\r\n] 2006.133.07:52:51.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:52:51.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.07:52:51.68#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.07:52:51.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:51.68#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:52:51.80#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:52:51.80#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:52:51.82#ibcon#[27=USB\r\n] 2006.133.07:52:51.85#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:52:51.85#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.07:52:51.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:52:51.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:52:51.85$vc4f8/vblo=5,744.99 2006.133.07:52:51.85#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.07:52:51.85#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.07:52:51.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:51.85#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:51.85#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:51.85#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:51.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:52:51.91#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:51.91#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.07:52:51.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:52:51.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:52:51.91$vc4f8/vb=5,4 2006.133.07:52:51.91#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.07:52:51.91#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.07:52:51.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:51.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:51.97#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:51.97#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:51.99#ibcon#[27=AT05-04\r\n] 2006.133.07:52:52.02#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:52.02#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.07:52:52.02#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.07:52:52.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:52.02#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:52.14#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:52.14#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:52.16#ibcon#[27=USB\r\n] 2006.133.07:52:52.19#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:52.19#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.07:52:52.19#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:52:52.19#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:52:52.19$vc4f8/vblo=6,752.99 2006.133.07:52:52.19#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.07:52:52.19#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.07:52:52.19#ibcon#ireg 17 cls_cnt 0 2006.133.07:52:52.19#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:52.19#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:52.19#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:52.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:52:52.25#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:52.25#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.07:52:52.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:52:52.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:52:52.25$vc4f8/vb=6,4 2006.133.07:52:52.25#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.07:52:52.25#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.07:52:52.25#ibcon#ireg 11 cls_cnt 2 2006.133.07:52:52.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:52.31#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:52.31#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:52.33#ibcon#[27=AT06-04\r\n] 2006.133.07:52:52.36#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:52.36#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.07:52:52.36#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.07:52:52.36#ibcon#ireg 7 cls_cnt 0 2006.133.07:52:52.36#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:52.48#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:52.48#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:52.50#ibcon#[27=USB\r\n] 2006.133.07:52:52.53#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:52.53#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.07:52:52.53#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:52:52.53#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:52:52.53$vc4f8/vabw=wide 2006.133.07:52:52.53#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:52:52.53#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:52:52.53#ibcon#ireg 8 cls_cnt 0 2006.133.07:52:52.53#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:52.53#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:52.53#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:52.56#ibcon#[25=BW32\r\n] 2006.133.07:52:52.59#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:52.59#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:52:52.59#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:52:52.59#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:52:52.59$vc4f8/vbbw=wide 2006.133.07:52:52.59#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:52:52.59#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:52:52.59#ibcon#ireg 8 cls_cnt 0 2006.133.07:52:52.59#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:52:52.65#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:52:52.65#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:52:52.67#ibcon#[27=BW32\r\n] 2006.133.07:52:52.70#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:52:52.70#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:52:52.70#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:52:52.70#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:52:52.70$4f8m12a/ifd4f 2006.133.07:52:52.70$ifd4f/lo= 2006.133.07:52:52.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:52:52.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:52:52.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:52:52.70$ifd4f/patch= 2006.133.07:52:52.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:52:52.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:52:52.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:52:52.70$4f8m12a/"form=m,16.000,1:2 2006.133.07:52:52.70$4f8m12a/"tpicd 2006.133.07:52:52.70$4f8m12a/echo=off 2006.133.07:52:52.70$4f8m12a/xlog=off 2006.133.07:52:52.71:!2006.133.07:53:20 2006.133.07:53:02.14#trakl#Source acquired 2006.133.07:53:02.14#flagr#flagr/antenna,acquired 2006.133.07:53:20.01:preob 2006.133.07:53:21.14/onsource/TRACKING 2006.133.07:53:21.14:!2006.133.07:53:30 2006.133.07:53:30.00:data_valid=on 2006.133.07:53:30.00:midob 2006.133.07:53:30.14/onsource/TRACKING 2006.133.07:53:30.14/wx/11.36,1009.9,100 2006.133.07:53:30.24/cable/+6.5575E-03 2006.133.07:53:31.33/va/01,08,usb,yes,50,53 2006.133.07:53:31.33/va/02,07,usb,yes,51,53 2006.133.07:53:31.33/va/03,06,usb,yes,54,54 2006.133.07:53:31.33/va/04,07,usb,yes,52,56 2006.133.07:53:31.33/va/05,06,usb,yes,60,63 2006.133.07:53:31.33/va/06,05,usb,yes,61,60 2006.133.07:53:31.33/va/07,05,usb,yes,61,60 2006.133.07:53:31.33/va/08,06,usb,yes,57,56 2006.133.07:53:31.56/valo/01,532.99,yes,locked 2006.133.07:53:31.56/valo/02,572.99,yes,locked 2006.133.07:53:31.56/valo/03,672.99,yes,locked 2006.133.07:53:31.56/valo/04,832.99,yes,locked 2006.133.07:53:31.56/valo/05,652.99,yes,locked 2006.133.07:53:31.56/valo/06,772.99,yes,locked 2006.133.07:53:31.56/valo/07,832.99,yes,locked 2006.133.07:53:31.56/valo/08,852.99,yes,locked 2006.133.07:53:32.65/vb/01,04,usb,yes,31,29 2006.133.07:53:32.65/vb/02,04,usb,yes,33,34 2006.133.07:53:32.65/vb/03,04,usb,yes,29,33 2006.133.07:53:32.65/vb/04,04,usb,yes,31,30 2006.133.07:53:32.65/vb/05,04,usb,yes,28,33 2006.133.07:53:32.65/vb/06,04,usb,yes,29,32 2006.133.07:53:32.65/vb/07,04,usb,yes,32,32 2006.133.07:53:32.65/vb/08,04,usb,yes,29,32 2006.133.07:53:32.88/vblo/01,632.99,yes,locked 2006.133.07:53:32.88/vblo/02,640.99,yes,locked 2006.133.07:53:32.88/vblo/03,656.99,yes,locked 2006.133.07:53:32.88/vblo/04,712.99,yes,locked 2006.133.07:53:32.88/vblo/05,744.99,yes,locked 2006.133.07:53:32.88/vblo/06,752.99,yes,locked 2006.133.07:53:32.88/vblo/07,734.99,yes,locked 2006.133.07:53:32.88/vblo/08,744.99,yes,locked 2006.133.07:53:33.03/vabw/8 2006.133.07:53:33.18/vbbw/8 2006.133.07:53:33.27/xfe/off,on,15.5 2006.133.07:53:33.64/ifatt/23,28,28,28 2006.133.07:53:34.08/fmout-gps/S +1.89E-07 2006.133.07:53:34.12:!2006.133.07:54:30 2006.133.07:54:30.01:data_valid=off 2006.133.07:54:30.02:postob 2006.133.07:54:30.12/cable/+6.5569E-03 2006.133.07:54:30.13/wx/11.36,1009.9,100 2006.133.07:54:31.07/fmout-gps/S +1.89E-07 2006.133.07:54:31.08:scan_name=133-0755,k06133,60 2006.133.07:54:31.08:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.133.07:54:31.14#flagr#flagr/antenna,new-source 2006.133.07:54:32.14:checkk5 2006.133.07:54:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:54:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:54:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:54:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:54:34.00/chk_obsdata//k5ts1/T1330753??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:54:34.36/chk_obsdata//k5ts2/T1330753??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:54:34.74/chk_obsdata//k5ts3/T1330753??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:54:35.11/chk_obsdata//k5ts4/T1330753??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.07:54:35.80/k5log//k5ts1_log_newline 2006.133.07:54:36.48/k5log//k5ts2_log_newline 2006.133.07:54:37.16/k5log//k5ts3_log_newline 2006.133.07:54:37.85/k5log//k5ts4_log_newline 2006.133.07:54:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:54:37.88:4f8m12a=2 2006.133.07:54:37.88$4f8m12a/echo=on 2006.133.07:54:37.88$4f8m12a/pcalon 2006.133.07:54:37.88$pcalon/"no phase cal control is implemented here 2006.133.07:54:37.88$4f8m12a/"tpicd=stop 2006.133.07:54:37.88$4f8m12a/vc4f8 2006.133.07:54:37.88$vc4f8/valo=1,532.99 2006.133.07:54:37.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:54:37.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:54:37.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:37.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:37.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:37.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:37.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:54:37.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:37.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:37.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:54:37.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:54:37.94$vc4f8/va=1,8 2006.133.07:54:37.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.07:54:37.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.07:54:37.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:37.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:37.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:37.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:37.96#ibcon#[25=AT01-08\r\n] 2006.133.07:54:38.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:38.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:38.00#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.07:54:38.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:38.00#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:38.11#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:38.11#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:38.13#ibcon#[25=USB\r\n] 2006.133.07:54:38.18#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:38.18#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:38.18#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:54:38.18#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:54:38.18$vc4f8/valo=2,572.99 2006.133.07:54:38.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.07:54:38.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.07:54:38.18#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:38.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:38.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:38.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:54:38.23#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:38.23#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:38.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:54:38.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:54:38.23$vc4f8/va=2,7 2006.133.07:54:38.23#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.07:54:38.23#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.07:54:38.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:38.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:38.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:38.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:38.32#ibcon#[25=AT02-07\r\n] 2006.133.07:54:38.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:38.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:38.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.07:54:38.35#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:38.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:38.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:38.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:38.49#ibcon#[25=USB\r\n] 2006.133.07:54:38.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:38.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:38.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:54:38.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:54:38.54$vc4f8/valo=3,672.99 2006.133.07:54:38.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.07:54:38.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.07:54:38.54#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:38.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:38.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:38.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:38.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:54:38.59#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:38.59#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:38.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:54:38.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:54:38.59$vc4f8/va=3,6 2006.133.07:54:38.59#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.07:54:38.59#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.07:54:38.59#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:38.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:38.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:38.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:38.68#ibcon#[25=AT03-06\r\n] 2006.133.07:54:38.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:38.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:38.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.07:54:38.71#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:38.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:38.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:38.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:38.85#ibcon#[25=USB\r\n] 2006.133.07:54:38.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:38.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:38.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:54:38.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:54:38.88$vc4f8/valo=4,832.99 2006.133.07:54:38.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:54:38.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:54:38.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:38.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:38.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:38.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:54:38.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:38.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:38.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:54:38.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:54:38.94$vc4f8/va=4,7 2006.133.07:54:38.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.07:54:38.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.07:54:38.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:38.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:39.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:39.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:39.02#ibcon#[25=AT04-07\r\n] 2006.133.07:54:39.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:39.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:39.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.07:54:39.05#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:39.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:39.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:39.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:39.19#ibcon#[25=USB\r\n] 2006.133.07:54:39.22#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:39.22#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:39.22#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:54:39.22#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:54:39.22$vc4f8/valo=5,652.99 2006.133.07:54:39.22#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.07:54:39.22#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.07:54:39.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:39.22#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:39.22#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:39.22#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:54:39.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:39.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:39.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:54:39.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:54:39.28$vc4f8/va=5,6 2006.133.07:54:39.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.07:54:39.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.07:54:39.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:39.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:39.34#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:39.34#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:39.36#ibcon#[25=AT05-06\r\n] 2006.133.07:54:39.39#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:39.39#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:39.39#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.07:54:39.39#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:39.39#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:39.51#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:39.51#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:39.53#ibcon#[25=USB\r\n] 2006.133.07:54:39.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:39.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:39.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:54:39.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:54:39.58$vc4f8/valo=6,772.99 2006.133.07:54:39.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.07:54:39.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.07:54:39.58#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:39.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:39.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:39.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:54:39.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:39.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:39.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:54:39.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:54:39.63$vc4f8/va=6,5 2006.133.07:54:39.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.07:54:39.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.07:54:39.63#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:39.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:39.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:39.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:39.72#ibcon#[25=AT06-05\r\n] 2006.133.07:54:39.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:39.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:39.75#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.07:54:39.75#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:39.75#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:54:39.87#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:54:39.87#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:54:39.89#ibcon#[25=USB\r\n] 2006.133.07:54:39.92#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:54:39.92#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.07:54:39.92#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:54:39.92#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:54:39.92$vc4f8/valo=7,832.99 2006.133.07:54:39.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.07:54:39.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.07:54:39.92#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:39.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:54:39.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:54:39.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:54:39.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:54:39.98#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:54:39.98#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.07:54:39.98#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.07:54:39.98#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.07:54:39.98$vc4f8/va=7,5 2006.133.07:54:39.98#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.07:54:39.98#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.07:54:39.98#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:39.98#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:54:40.04#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:54:40.04#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:54:40.06#ibcon#[25=AT07-05\r\n] 2006.133.07:54:40.09#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:54:40.09#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.07:54:40.09#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.07:54:40.09#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:40.09#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:54:40.21#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:54:40.21#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:54:40.23#ibcon#[25=USB\r\n] 2006.133.07:54:40.26#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:54:40.26#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.07:54:40.26#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.07:54:40.26#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.07:54:40.26$vc4f8/valo=8,852.99 2006.133.07:54:40.26#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.07:54:40.26#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.07:54:40.26#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:40.26#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:54:40.26#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:54:40.26#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:54:40.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:54:40.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:54:40.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.07:54:40.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.07:54:40.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.07:54:40.33$vc4f8/va=8,6 2006.133.07:54:40.33#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.07:54:40.33#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.07:54:40.33#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:40.33#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:54:40.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:54:40.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:54:40.40#ibcon#[25=AT08-06\r\n] 2006.133.07:54:40.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:54:40.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.07:54:40.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.07:54:40.43#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:40.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:54:40.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:54:40.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:54:40.57#ibcon#[25=USB\r\n] 2006.133.07:54:40.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:54:40.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.07:54:40.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.07:54:40.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.07:54:40.60$vc4f8/vblo=1,632.99 2006.133.07:54:40.60#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.07:54:40.60#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.07:54:40.60#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:40.60#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:54:40.60#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:54:40.60#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:54:40.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:54:40.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:54:40.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.07:54:40.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.07:54:40.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.07:54:40.66$vc4f8/vb=1,4 2006.133.07:54:40.66#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.07:54:40.66#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.07:54:40.66#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:40.66#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:54:40.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:54:40.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:54:40.68#ibcon#[27=AT01-04\r\n] 2006.133.07:54:40.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:54:40.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.07:54:40.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.07:54:40.71#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:40.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:54:40.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:54:40.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:54:40.85#ibcon#[27=USB\r\n] 2006.133.07:54:40.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:54:40.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.07:54:40.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.07:54:40.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.07:54:40.88$vc4f8/vblo=2,640.99 2006.133.07:54:40.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.07:54:40.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.07:54:40.88#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:40.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:40.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:40.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:54:40.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:40.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.07:54:40.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.07:54:40.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.07:54:40.94$vc4f8/vb=2,4 2006.133.07:54:40.94#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.07:54:40.94#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.07:54:40.94#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:40.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:41.00#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:41.00#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:41.02#ibcon#[27=AT02-04\r\n] 2006.133.07:54:41.05#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:41.05#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.07:54:41.05#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.07:54:41.05#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:41.05#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:41.17#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:41.17#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:41.19#ibcon#[27=USB\r\n] 2006.133.07:54:41.22#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:41.22#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.07:54:41.22#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.07:54:41.22#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.07:54:41.22$vc4f8/vblo=3,656.99 2006.133.07:54:41.22#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.07:54:41.22#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.07:54:41.22#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:41.22#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:41.22#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:41.22#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:54:41.28#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:41.28#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.07:54:41.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.07:54:41.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.07:54:41.28$vc4f8/vb=3,4 2006.133.07:54:41.28#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.07:54:41.28#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.07:54:41.28#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:41.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:41.34#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:41.34#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:41.36#ibcon#[27=AT03-04\r\n] 2006.133.07:54:41.39#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:41.39#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.07:54:41.39#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.07:54:41.39#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:41.39#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:41.51#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:41.51#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:41.53#ibcon#[27=USB\r\n] 2006.133.07:54:41.56#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:41.56#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.07:54:41.56#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.07:54:41.56#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.07:54:41.56$vc4f8/vblo=4,712.99 2006.133.07:54:41.56#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.07:54:41.56#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.07:54:41.56#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:41.56#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:41.56#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:41.56#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:41.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:54:41.62#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:41.62#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.07:54:41.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.07:54:41.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.07:54:41.62$vc4f8/vb=4,4 2006.133.07:54:41.62#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.07:54:41.62#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.07:54:41.62#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:41.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:41.68#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:41.68#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:41.70#ibcon#[27=AT04-04\r\n] 2006.133.07:54:41.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:41.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.07:54:41.73#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.07:54:41.73#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:41.73#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:41.85#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:41.85#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:41.87#ibcon#[27=USB\r\n] 2006.133.07:54:41.90#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:41.90#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.07:54:41.90#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.07:54:41.90#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.07:54:41.90$vc4f8/vblo=5,744.99 2006.133.07:54:41.90#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.07:54:41.90#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.07:54:41.90#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:41.90#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:41.90#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:41.90#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:41.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:54:41.96#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:41.96#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.07:54:41.96#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.07:54:41.96#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.07:54:41.96$vc4f8/vb=5,4 2006.133.07:54:41.96#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.07:54:41.96#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.07:54:41.96#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:41.96#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:42.02#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:42.02#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:42.04#ibcon#[27=AT05-04\r\n] 2006.133.07:54:42.07#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:42.07#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.07:54:42.07#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.07:54:42.07#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:42.07#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:42.19#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:42.19#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:42.21#ibcon#[27=USB\r\n] 2006.133.07:54:42.24#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:42.24#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.07:54:42.24#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.07:54:42.24#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.07:54:42.24$vc4f8/vblo=6,752.99 2006.133.07:54:42.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.07:54:42.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.07:54:42.24#ibcon#ireg 17 cls_cnt 0 2006.133.07:54:42.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:42.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:42.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:42.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:54:42.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:42.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.07:54:42.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.07:54:42.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.07:54:42.30$vc4f8/vb=6,4 2006.133.07:54:42.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.07:54:42.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.07:54:42.30#ibcon#ireg 11 cls_cnt 2 2006.133.07:54:42.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:42.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:42.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:42.38#ibcon#[27=AT06-04\r\n] 2006.133.07:54:42.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:42.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.07:54:42.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.07:54:42.41#ibcon#ireg 7 cls_cnt 0 2006.133.07:54:42.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:42.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:42.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:42.55#ibcon#[27=USB\r\n] 2006.133.07:54:42.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:42.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.07:54:42.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.07:54:42.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.07:54:42.58$vc4f8/vabw=wide 2006.133.07:54:42.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.07:54:42.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.07:54:42.58#ibcon#ireg 8 cls_cnt 0 2006.133.07:54:42.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:42.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:42.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:42.60#ibcon#[25=BW32\r\n] 2006.133.07:54:42.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:42.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.07:54:42.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.07:54:42.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.07:54:42.63$vc4f8/vbbw=wide 2006.133.07:54:42.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.07:54:42.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.07:54:42.63#ibcon#ireg 8 cls_cnt 0 2006.133.07:54:42.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:54:42.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:54:42.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:54:42.72#ibcon#[27=BW32\r\n] 2006.133.07:54:42.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:54:42.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.07:54:42.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.07:54:42.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.07:54:42.75$4f8m12a/ifd4f 2006.133.07:54:42.75$ifd4f/lo= 2006.133.07:54:42.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:54:42.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:54:42.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:54:42.75$ifd4f/patch= 2006.133.07:54:42.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:54:42.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:54:42.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:54:42.75$4f8m12a/"form=m,16.000,1:2 2006.133.07:54:42.75$4f8m12a/"tpicd 2006.133.07:54:42.75$4f8m12a/echo=off 2006.133.07:54:42.75$4f8m12a/xlog=off 2006.133.07:54:42.75:!2006.133.07:55:30 2006.133.07:55:09.14#trakl#Source acquired 2006.133.07:55:10.14#flagr#flagr/antenna,acquired 2006.133.07:55:30.00:preob 2006.133.07:55:30.14/onsource/TRACKING 2006.133.07:55:30.14:!2006.133.07:55:40 2006.133.07:55:40.00:data_valid=on 2006.133.07:55:40.00:midob 2006.133.07:55:40.14/onsource/TRACKING 2006.133.07:55:40.14/wx/11.36,1009.9,100 2006.133.07:55:40.28/cable/+6.5588E-03 2006.133.07:55:41.37/va/01,08,usb,yes,51,54 2006.133.07:55:41.37/va/02,07,usb,yes,52,54 2006.133.07:55:41.37/va/03,06,usb,yes,55,55 2006.133.07:55:41.37/va/04,07,usb,yes,53,57 2006.133.07:55:41.37/va/05,06,usb,yes,61,64 2006.133.07:55:41.37/va/06,05,usb,yes,62,62 2006.133.07:55:41.37/va/07,05,usb,yes,62,62 2006.133.07:55:41.37/va/08,06,usb,yes,58,57 2006.133.07:55:41.60/valo/01,532.99,yes,locked 2006.133.07:55:41.60/valo/02,572.99,yes,locked 2006.133.07:55:41.60/valo/03,672.99,yes,locked 2006.133.07:55:41.60/valo/04,832.99,yes,locked 2006.133.07:55:41.60/valo/05,652.99,yes,locked 2006.133.07:55:41.60/valo/06,772.99,yes,locked 2006.133.07:55:41.60/valo/07,832.99,yes,locked 2006.133.07:55:41.60/valo/08,852.99,yes,locked 2006.133.07:55:42.69/vb/01,04,usb,yes,31,30 2006.133.07:55:42.69/vb/02,04,usb,yes,33,35 2006.133.07:55:42.69/vb/03,04,usb,yes,29,33 2006.133.07:55:42.69/vb/04,04,usb,yes,30,31 2006.133.07:55:42.69/vb/05,04,usb,yes,29,33 2006.133.07:55:42.69/vb/06,04,usb,yes,30,33 2006.133.07:55:42.69/vb/07,04,usb,yes,32,32 2006.133.07:55:42.69/vb/08,04,usb,yes,29,33 2006.133.07:55:42.92/vblo/01,632.99,yes,locked 2006.133.07:55:42.92/vblo/02,640.99,yes,locked 2006.133.07:55:42.92/vblo/03,656.99,yes,locked 2006.133.07:55:42.92/vblo/04,712.99,yes,locked 2006.133.07:55:42.92/vblo/05,744.99,yes,locked 2006.133.07:55:42.92/vblo/06,752.99,yes,locked 2006.133.07:55:42.92/vblo/07,734.99,yes,locked 2006.133.07:55:42.92/vblo/08,744.99,yes,locked 2006.133.07:55:43.07/vabw/8 2006.133.07:55:43.22/vbbw/8 2006.133.07:55:43.31/xfe/off,on,16.2 2006.133.07:55:43.69/ifatt/23,28,28,28 2006.133.07:55:44.07/fmout-gps/S +1.89E-07 2006.133.07:55:44.11:!2006.133.07:56:40 2006.133.07:56:40.01:data_valid=off 2006.133.07:56:40.02:postob 2006.133.07:56:40.13/cable/+6.5588E-03 2006.133.07:56:40.14/wx/11.35,1009.9,100 2006.133.07:56:41.07/fmout-gps/S +1.90E-07 2006.133.07:56:41.08:scan_name=133-0759,k06133,60 2006.133.07:56:41.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.133.07:56:41.13#flagr#flagr/antenna,new-source 2006.133.07:56:42.13:checkk5 2006.133.07:56:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.07:56:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.07:56:43.24/chk_autoobs//k5ts3/ autoobs is running! 2006.133.07:56:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.07:56:43.98/chk_obsdata//k5ts1/T1330755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:56:44.34/chk_obsdata//k5ts2/T1330755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:56:44.70/chk_obsdata//k5ts3/T1330755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:56:45.07/chk_obsdata//k5ts4/T1330755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.07:56:45.75/k5log//k5ts1_log_newline 2006.133.07:56:46.44/k5log//k5ts2_log_newline 2006.133.07:56:47.13/k5log//k5ts3_log_newline 2006.133.07:56:47.81/k5log//k5ts4_log_newline 2006.133.07:56:47.83/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.07:56:47.83:4f8m12a=2 2006.133.07:56:47.83$4f8m12a/echo=on 2006.133.07:56:47.83$4f8m12a/pcalon 2006.133.07:56:47.83$pcalon/"no phase cal control is implemented here 2006.133.07:56:47.83$4f8m12a/"tpicd=stop 2006.133.07:56:47.83$4f8m12a/vc4f8 2006.133.07:56:47.83$vc4f8/valo=1,532.99 2006.133.07:56:47.83#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:56:47.83#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:56:47.83#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:47.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:47.83#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:47.83#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:47.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.07:56:47.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:47.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:47.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:56:47.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:56:47.92$vc4f8/va=1,8 2006.133.07:56:47.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:56:47.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:56:47.92#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:47.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:47.92#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:47.92#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:47.95#ibcon#[25=AT01-08\r\n] 2006.133.07:56:47.98#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:47.98#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:47.98#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:56:47.98#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:47.98#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:48.10#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:48.10#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:48.12#ibcon#[25=USB\r\n] 2006.133.07:56:48.15#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:48.15#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:48.15#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:56:48.15#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:56:48.15$vc4f8/valo=2,572.99 2006.133.07:56:48.15#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:56:48.15#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:56:48.15#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:48.15#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:48.15#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:48.15#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:48.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.07:56:48.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:48.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:48.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:56:48.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:56:48.22$vc4f8/va=2,7 2006.133.07:56:48.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.07:56:48.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.07:56:48.22#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:48.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:48.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:48.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:48.29#ibcon#[25=AT02-07\r\n] 2006.133.07:56:48.32#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:48.32#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:48.32#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.07:56:48.32#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:48.32#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:48.44#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:48.44#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:48.46#ibcon#[25=USB\r\n] 2006.133.07:56:48.49#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:48.49#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:48.49#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:56:48.49#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:56:48.49$vc4f8/valo=3,672.99 2006.133.07:56:48.49#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:56:48.49#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:56:48.49#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:48.49#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:48.49#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:48.49#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:48.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.07:56:48.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:48.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:48.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:56:48.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:56:48.56$vc4f8/va=3,6 2006.133.07:56:48.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:56:48.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:56:48.56#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:48.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:48.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:48.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:48.63#ibcon#[25=AT03-06\r\n] 2006.133.07:56:48.66#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:48.66#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:48.66#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:56:48.66#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:48.66#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:48.78#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:48.78#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:48.80#ibcon#[25=USB\r\n] 2006.133.07:56:48.83#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:48.83#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:48.83#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:56:48.83#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:56:48.83$vc4f8/valo=4,832.99 2006.133.07:56:48.83#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:56:48.83#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:56:48.83#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:48.83#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:48.83#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:48.83#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:48.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.07:56:48.89#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:48.89#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:48.89#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:56:48.89#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:56:48.89$vc4f8/va=4,7 2006.133.07:56:48.89#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:56:48.89#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:56:48.89#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:48.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:48.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:48.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:48.97#ibcon#[25=AT04-07\r\n] 2006.133.07:56:49.00#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:49.00#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:49.00#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:56:49.00#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:49.00#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:49.12#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:49.12#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:49.14#ibcon#[25=USB\r\n] 2006.133.07:56:49.17#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:49.17#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:49.17#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:56:49.17#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:56:49.17$vc4f8/valo=5,652.99 2006.133.07:56:49.17#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:56:49.17#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:56:49.17#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:49.17#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:49.17#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:49.17#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:49.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.07:56:49.23#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:49.23#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:49.23#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:56:49.23#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:56:49.23$vc4f8/va=5,6 2006.133.07:56:49.23#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:56:49.23#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:56:49.23#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:49.23#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:49.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:49.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:49.31#ibcon#[25=AT05-06\r\n] 2006.133.07:56:49.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:49.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:49.34#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:56:49.34#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:49.34#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:49.46#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:49.46#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:49.48#ibcon#[25=USB\r\n] 2006.133.07:56:49.51#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:49.51#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:49.51#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:56:49.51#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:56:49.51$vc4f8/valo=6,772.99 2006.133.07:56:49.51#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:56:49.51#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:56:49.51#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:49.51#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:49.51#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:49.51#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:49.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.07:56:49.57#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:49.57#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:49.57#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:56:49.57#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:56:49.57$vc4f8/va=6,5 2006.133.07:56:49.57#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.07:56:49.57#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.07:56:49.57#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:49.57#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:49.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:49.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:49.65#ibcon#[25=AT06-05\r\n] 2006.133.07:56:49.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:49.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:49.68#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.07:56:49.68#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:49.68#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:56:49.80#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:56:49.80#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:56:49.82#ibcon#[25=USB\r\n] 2006.133.07:56:49.85#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:56:49.85#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.07:56:49.85#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:56:49.85#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:56:49.85$vc4f8/valo=7,832.99 2006.133.07:56:49.85#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.07:56:49.85#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.07:56:49.85#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:49.85#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:56:49.85#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:56:49.85#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:56:49.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.07:56:49.91#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:56:49.91#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.07:56:49.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.07:56:49.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.07:56:49.91$vc4f8/va=7,5 2006.133.07:56:49.91#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.07:56:49.91#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.07:56:49.91#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:49.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:56:49.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:56:49.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:56:49.99#ibcon#[25=AT07-05\r\n] 2006.133.07:56:50.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:56:50.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.07:56:50.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.07:56:50.02#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:50.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:56:50.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:56:50.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:56:50.16#ibcon#[25=USB\r\n] 2006.133.07:56:50.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:56:50.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.07:56:50.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.07:56:50.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.07:56:50.20$vc4f8/valo=8,852.99 2006.133.07:56:50.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.07:56:50.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.07:56:50.20#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:50.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:56:50.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:56:50.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:56:50.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.07:56:50.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:56:50.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.07:56:50.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.07:56:50.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.07:56:50.26$vc4f8/va=8,6 2006.133.07:56:50.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.07:56:50.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.07:56:50.26#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:50.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:56:50.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:56:50.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:56:50.34#ibcon#[25=AT08-06\r\n] 2006.133.07:56:50.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:56:50.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.07:56:50.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.07:56:50.37#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:50.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:56:50.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:56:50.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:56:50.51#ibcon#[25=USB\r\n] 2006.133.07:56:50.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:56:50.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.07:56:50.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.07:56:50.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.07:56:50.54$vc4f8/vblo=1,632.99 2006.133.07:56:50.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.07:56:50.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.07:56:50.54#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:50.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:56:50.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:56:50.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:56:50.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.07:56:50.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:56:50.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.07:56:50.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.07:56:50.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.07:56:50.60$vc4f8/vb=1,4 2006.133.07:56:50.60#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.07:56:50.60#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.07:56:50.60#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:50.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:56:50.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:56:50.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:56:50.62#ibcon#[27=AT01-04\r\n] 2006.133.07:56:50.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:56:50.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.07:56:50.65#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.07:56:50.65#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:50.65#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:56:50.77#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:56:50.77#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:56:50.79#ibcon#[27=USB\r\n] 2006.133.07:56:50.82#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:56:50.82#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.07:56:50.82#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.07:56:50.82#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.07:56:50.82$vc4f8/vblo=2,640.99 2006.133.07:56:50.82#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.07:56:50.82#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.07:56:50.82#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:50.82#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:50.82#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:50.82#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:50.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.07:56:50.88#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:50.88#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.07:56:50.88#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.07:56:50.88#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.07:56:50.88$vc4f8/vb=2,4 2006.133.07:56:50.88#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.07:56:50.88#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.07:56:50.88#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:50.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:50.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:50.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:50.96#ibcon#[27=AT02-04\r\n] 2006.133.07:56:50.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:50.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.07:56:50.99#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.07:56:50.99#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:50.99#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:51.11#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:51.11#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:51.13#ibcon#[27=USB\r\n] 2006.133.07:56:51.16#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:51.16#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.07:56:51.16#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.07:56:51.16#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.07:56:51.16$vc4f8/vblo=3,656.99 2006.133.07:56:51.16#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.07:56:51.16#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.07:56:51.16#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:51.16#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:51.16#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:51.16#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:51.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.07:56:51.22#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:51.22#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.07:56:51.22#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.07:56:51.22#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.07:56:51.22$vc4f8/vb=3,4 2006.133.07:56:51.22#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.07:56:51.22#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.07:56:51.22#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:51.22#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:51.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:51.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:51.30#ibcon#[27=AT03-04\r\n] 2006.133.07:56:51.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:51.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.07:56:51.33#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.07:56:51.33#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:51.33#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:51.45#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:51.45#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:51.47#ibcon#[27=USB\r\n] 2006.133.07:56:51.50#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:51.50#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.07:56:51.50#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.07:56:51.50#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.07:56:51.50$vc4f8/vblo=4,712.99 2006.133.07:56:51.50#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.07:56:51.50#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.07:56:51.50#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:51.50#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:51.50#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:51.50#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:51.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.07:56:51.56#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:51.56#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.07:56:51.56#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.07:56:51.56#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.07:56:51.56$vc4f8/vb=4,4 2006.133.07:56:51.56#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.07:56:51.56#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.07:56:51.56#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:51.56#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:51.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:51.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:51.64#ibcon#[27=AT04-04\r\n] 2006.133.07:56:51.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:51.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.07:56:51.67#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.07:56:51.67#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:51.67#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:51.79#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:51.79#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:51.81#ibcon#[27=USB\r\n] 2006.133.07:56:51.84#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:51.84#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.07:56:51.84#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.07:56:51.84#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.07:56:51.84$vc4f8/vblo=5,744.99 2006.133.07:56:51.84#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.07:56:51.84#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.07:56:51.84#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:51.84#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:51.84#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:51.84#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:51.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.07:56:51.90#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:51.90#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.07:56:51.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.07:56:51.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.07:56:51.90$vc4f8/vb=5,4 2006.133.07:56:51.90#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.07:56:51.90#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.07:56:51.90#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:51.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:51.96#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:51.96#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:51.98#ibcon#[27=AT05-04\r\n] 2006.133.07:56:52.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:52.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.07:56:52.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.07:56:52.01#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:52.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:52.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:52.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:52.15#ibcon#[27=USB\r\n] 2006.133.07:56:52.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:52.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.07:56:52.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.07:56:52.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.07:56:52.18$vc4f8/vblo=6,752.99 2006.133.07:56:52.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.07:56:52.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.07:56:52.18#ibcon#ireg 17 cls_cnt 0 2006.133.07:56:52.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:52.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:52.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:52.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.07:56:52.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:52.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.07:56:52.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.07:56:52.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.07:56:52.24$vc4f8/vb=6,4 2006.133.07:56:52.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.07:56:52.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.07:56:52.24#ibcon#ireg 11 cls_cnt 2 2006.133.07:56:52.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:52.30#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:52.30#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:52.32#ibcon#[27=AT06-04\r\n] 2006.133.07:56:52.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:52.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.07:56:52.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.07:56:52.35#ibcon#ireg 7 cls_cnt 0 2006.133.07:56:52.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:52.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:52.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:52.49#ibcon#[27=USB\r\n] 2006.133.07:56:52.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:52.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.07:56:52.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.07:56:52.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.07:56:52.54$vc4f8/vabw=wide 2006.133.07:56:52.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.07:56:52.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.07:56:52.54#ibcon#ireg 8 cls_cnt 0 2006.133.07:56:52.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:52.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:52.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:52.55#ibcon#[25=BW32\r\n] 2006.133.07:56:52.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:52.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.07:56:52.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.07:56:52.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.07:56:52.58$vc4f8/vbbw=wide 2006.133.07:56:52.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.07:56:52.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.07:56:52.58#ibcon#ireg 8 cls_cnt 0 2006.133.07:56:52.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:56:52.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:56:52.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:56:52.68#ibcon#[27=BW32\r\n] 2006.133.07:56:52.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:56:52.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.07:56:52.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.07:56:52.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.07:56:52.71$4f8m12a/ifd4f 2006.133.07:56:52.71$ifd4f/lo= 2006.133.07:56:52.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.07:56:52.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.07:56:52.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.07:56:52.71$ifd4f/patch= 2006.133.07:56:52.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.07:56:52.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.07:56:52.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.07:56:52.71$4f8m12a/"form=m,16.000,1:2 2006.133.07:56:52.71$4f8m12a/"tpicd 2006.133.07:56:52.71$4f8m12a/echo=off 2006.133.07:56:52.71$4f8m12a/xlog=off 2006.133.07:56:52.71:!2006.133.07:59:00 2006.133.07:57:30.13#trakl#Source acquired 2006.133.07:57:32.13#flagr#flagr/antenna,acquired 2006.133.07:59:00.00:preob 2006.133.07:59:00.14/onsource/TRACKING 2006.133.07:59:00.14:!2006.133.07:59:10 2006.133.07:59:10.00:data_valid=on 2006.133.07:59:10.00:midob 2006.133.07:59:11.14/onsource/TRACKING 2006.133.07:59:11.14/wx/11.33,1009.9,100 2006.133.07:59:11.25/cable/+6.5562E-03 2006.133.07:59:12.34/va/01,08,usb,yes,48,50 2006.133.07:59:12.34/va/02,07,usb,yes,48,50 2006.133.07:59:12.34/va/03,06,usb,yes,51,51 2006.133.07:59:12.34/va/04,07,usb,yes,49,53 2006.133.07:59:12.34/va/05,06,usb,yes,57,60 2006.133.07:59:12.34/va/06,05,usb,yes,58,57 2006.133.07:59:12.34/va/07,05,usb,yes,58,57 2006.133.07:59:12.34/va/08,06,usb,yes,54,53 2006.133.07:59:12.57/valo/01,532.99,yes,locked 2006.133.07:59:12.57/valo/02,572.99,yes,locked 2006.133.07:59:12.57/valo/03,672.99,yes,locked 2006.133.07:59:12.57/valo/04,832.99,yes,locked 2006.133.07:59:12.57/valo/05,652.99,yes,locked 2006.133.07:59:12.57/valo/06,772.99,yes,locked 2006.133.07:59:12.57/valo/07,832.99,yes,locked 2006.133.07:59:12.57/valo/08,852.99,yes,locked 2006.133.07:59:13.66/vb/01,04,usb,yes,31,41 2006.133.07:59:13.66/vb/02,04,usb,yes,32,43 2006.133.07:59:13.66/vb/03,04,usb,yes,29,33 2006.133.07:59:13.66/vb/04,04,usb,yes,30,30 2006.133.07:59:13.66/vb/05,04,usb,yes,29,33 2006.133.07:59:13.66/vb/06,04,usb,yes,30,33 2006.133.07:59:13.66/vb/07,04,usb,yes,32,32 2006.133.07:59:13.66/vb/08,04,usb,yes,29,33 2006.133.07:59:13.90/vblo/01,632.99,yes,locked 2006.133.07:59:13.90/vblo/02,640.99,yes,locked 2006.133.07:59:13.90/vblo/03,656.99,yes,locked 2006.133.07:59:13.90/vblo/04,712.99,yes,locked 2006.133.07:59:13.90/vblo/05,744.99,yes,locked 2006.133.07:59:13.90/vblo/06,752.99,yes,locked 2006.133.07:59:13.90/vblo/07,734.99,yes,locked 2006.133.07:59:13.90/vblo/08,744.99,yes,locked 2006.133.07:59:14.05/vabw/8 2006.133.07:59:14.20/vbbw/8 2006.133.07:59:14.29/xfe/off,on,15.2 2006.133.07:59:14.67/ifatt/23,28,28,28 2006.133.07:59:15.08/fmout-gps/S +1.90E-07 2006.133.07:59:15.12:!2006.133.08:00:10 2006.133.08:00:10.01:data_valid=off 2006.133.08:00:10.02:postob 2006.133.08:00:10.12/cable/+6.5559E-03 2006.133.08:00:10.12/wx/11.32,1009.9,100 2006.133.08:00:11.08/fmout-gps/S +1.90E-07 2006.133.08:00:11.08:scan_name=133-0801,k06133,60 2006.133.08:00:11.09:source=1300+580,130252.47,574837.6,2000.0,cw 2006.133.08:00:11.16#flagr#flagr/antenna,new-source 2006.133.08:00:12.13:checkk5 2006.133.08:00:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:00:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:00:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:00:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:00:13.98/chk_obsdata//k5ts1/T1330759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:00:14.35/chk_obsdata//k5ts2/T1330759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:00:14.72/chk_obsdata//k5ts3/T1330759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:00:15.08/chk_obsdata//k5ts4/T1330759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:00:15.77/k5log//k5ts1_log_newline 2006.133.08:00:16.45/k5log//k5ts2_log_newline 2006.133.08:00:17.14/k5log//k5ts3_log_newline 2006.133.08:00:17.82/k5log//k5ts4_log_newline 2006.133.08:00:17.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:00:17.84:4f8m12a=2 2006.133.08:00:17.84$4f8m12a/echo=on 2006.133.08:00:17.84$4f8m12a/pcalon 2006.133.08:00:17.84$pcalon/"no phase cal control is implemented here 2006.133.08:00:17.84$4f8m12a/"tpicd=stop 2006.133.08:00:17.84$4f8m12a/vc4f8 2006.133.08:00:17.84$vc4f8/valo=1,532.99 2006.133.08:00:17.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:00:17.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:00:17.84#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:17.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:17.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:17.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:17.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:00:17.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:17.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:17.91#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:00:17.91#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:00:17.91$vc4f8/va=1,8 2006.133.08:00:17.91#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:00:17.91#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:00:17.91#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:17.91#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:17.91#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:17.91#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:17.93#ibcon#[25=AT01-08\r\n] 2006.133.08:00:17.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:17.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:17.96#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:00:17.96#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:17.96#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:18.08#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:18.08#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:18.10#ibcon#[25=USB\r\n] 2006.133.08:00:18.13#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:18.13#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:18.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:00:18.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:00:18.13$vc4f8/valo=2,572.99 2006.133.08:00:18.13#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:00:18.13#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:00:18.13#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:18.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:18.13#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:18.13#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:18.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:00:18.20#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:18.20#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:18.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:00:18.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:00:18.20$vc4f8/va=2,7 2006.133.08:00:18.20#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.08:00:18.20#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.08:00:18.20#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:18.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:18.25#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:18.25#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:18.27#ibcon#[25=AT02-07\r\n] 2006.133.08:00:18.30#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:18.30#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:18.30#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.08:00:18.30#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:18.30#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:18.42#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:18.42#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:18.44#ibcon#[25=USB\r\n] 2006.133.08:00:18.47#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:18.47#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:18.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:00:18.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:00:18.47$vc4f8/valo=3,672.99 2006.133.08:00:18.47#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.08:00:18.47#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.08:00:18.47#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:18.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:18.47#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:18.47#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:18.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:00:18.54#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:18.54#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:18.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:00:18.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:00:18.54$vc4f8/va=3,6 2006.133.08:00:18.54#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.08:00:18.54#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.08:00:18.54#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:18.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:18.59#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:18.59#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:18.61#ibcon#[25=AT03-06\r\n] 2006.133.08:00:18.64#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:18.64#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:18.64#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.08:00:18.64#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:18.64#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:18.76#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:18.76#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:18.78#ibcon#[25=USB\r\n] 2006.133.08:00:18.81#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:18.81#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:18.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:00:18.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:00:18.81$vc4f8/valo=4,832.99 2006.133.08:00:18.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.08:00:18.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.08:00:18.81#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:18.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:18.81#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:18.81#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:18.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:00:18.87#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:18.87#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:18.87#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:00:18.87#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:00:18.87$vc4f8/va=4,7 2006.133.08:00:18.87#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.08:00:18.87#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.08:00:18.87#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:18.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:18.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:18.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:18.95#ibcon#[25=AT04-07\r\n] 2006.133.08:00:18.98#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:18.98#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:18.98#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.08:00:18.98#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:18.98#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:19.05#abcon#<5=/16 0.8 2.3 11.321001009.9\r\n> 2006.133.08:00:19.07#abcon#{5=INTERFACE CLEAR} 2006.133.08:00:19.10#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:19.10#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:19.12#ibcon#[25=USB\r\n] 2006.133.08:00:19.13#abcon#[5=S1D000X0/0*\r\n] 2006.133.08:00:19.15#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:19.15#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:19.15#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:00:19.15#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:00:19.15$vc4f8/valo=5,652.99 2006.133.08:00:19.15#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.08:00:19.15#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.08:00:19.15#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:19.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:19.15#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:19.15#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:19.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:00:19.21#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:19.21#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:19.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:00:19.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:00:19.21$vc4f8/va=5,6 2006.133.08:00:19.21#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.08:00:19.21#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.08:00:19.21#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:19.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:19.27#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:19.27#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:19.29#ibcon#[25=AT05-06\r\n] 2006.133.08:00:19.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:19.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:19.32#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.08:00:19.32#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:19.32#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:19.44#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:19.44#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:19.46#ibcon#[25=USB\r\n] 2006.133.08:00:19.49#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:19.49#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:19.49#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:00:19.49#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:00:19.49$vc4f8/valo=6,772.99 2006.133.08:00:19.49#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:00:19.49#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:00:19.49#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:19.49#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:19.49#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:19.49#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:19.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:00:19.55#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:19.55#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:19.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:00:19.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:00:19.55$vc4f8/va=6,5 2006.133.08:00:19.55#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.08:00:19.55#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.08:00:19.55#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:19.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:19.61#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:19.61#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:19.63#ibcon#[25=AT06-05\r\n] 2006.133.08:00:19.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:19.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:19.66#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.08:00:19.66#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:19.66#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:00:19.78#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:00:19.78#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:00:19.80#ibcon#[25=USB\r\n] 2006.133.08:00:19.83#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:00:19.83#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:00:19.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:00:19.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:00:19.83$vc4f8/valo=7,832.99 2006.133.08:00:19.83#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.08:00:19.83#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.08:00:19.83#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:19.83#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:00:19.83#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:00:19.83#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:00:19.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:00:19.89#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:00:19.89#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:00:19.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:00:19.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:00:19.89$vc4f8/va=7,5 2006.133.08:00:19.89#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.08:00:19.89#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.08:00:19.89#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:19.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:00:19.95#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:00:19.95#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:00:19.97#ibcon#[25=AT07-05\r\n] 2006.133.08:00:20.00#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:00:20.00#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:00:20.00#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.08:00:20.00#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:20.00#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:00:20.12#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:00:20.12#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:00:20.14#ibcon#[25=USB\r\n] 2006.133.08:00:20.17#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:00:20.17#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:00:20.17#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:00:20.17#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:00:20.17$vc4f8/valo=8,852.99 2006.133.08:00:20.17#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:00:20.17#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:00:20.17#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:20.17#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:00:20.17#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:00:20.17#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:00:20.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:00:20.23#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:00:20.23#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:00:20.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:00:20.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:00:20.23$vc4f8/va=8,6 2006.133.08:00:20.23#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.08:00:20.23#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.08:00:20.23#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:20.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:00:20.29#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:00:20.29#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:00:20.31#ibcon#[25=AT08-06\r\n] 2006.133.08:00:20.34#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:00:20.34#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:00:20.34#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.08:00:20.34#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:20.34#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:00:20.46#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:00:20.46#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:00:20.48#ibcon#[25=USB\r\n] 2006.133.08:00:20.51#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:00:20.51#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:00:20.51#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:00:20.51#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:00:20.51$vc4f8/vblo=1,632.99 2006.133.08:00:20.51#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:00:20.51#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:00:20.51#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:20.51#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:20.51#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:20.51#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:20.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:00:20.57#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:20.57#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:00:20.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:00:20.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:00:20.57$vc4f8/vb=1,4 2006.133.08:00:20.57#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:00:20.57#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:00:20.57#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:20.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:20.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:20.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:20.59#ibcon#[27=AT01-04\r\n] 2006.133.08:00:20.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:20.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:00:20.62#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:00:20.62#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:20.62#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:20.74#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:20.74#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:20.76#ibcon#[27=USB\r\n] 2006.133.08:00:20.79#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:20.79#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:00:20.79#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:00:20.79#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:00:20.79$vc4f8/vblo=2,640.99 2006.133.08:00:20.79#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:00:20.79#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:00:20.79#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:20.79#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:20.79#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:20.79#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:20.81#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:00:20.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:20.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:00:20.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:00:20.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:00:20.85$vc4f8/vb=2,4 2006.133.08:00:20.85#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.08:00:20.85#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.08:00:20.85#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:20.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:20.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:20.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:20.93#ibcon#[27=AT02-04\r\n] 2006.133.08:00:20.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:20.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:00:20.96#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.08:00:20.96#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:20.96#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:21.08#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:21.08#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:21.10#ibcon#[27=USB\r\n] 2006.133.08:00:21.13#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:21.13#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:00:21.13#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:00:21.13#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:00:21.13$vc4f8/vblo=3,656.99 2006.133.08:00:21.13#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.08:00:21.13#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.08:00:21.13#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:21.13#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:21.13#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:21.13#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:21.15#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:00:21.19#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:21.19#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:00:21.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:00:21.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:00:21.19$vc4f8/vb=3,4 2006.133.08:00:21.19#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.08:00:21.19#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.08:00:21.19#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:21.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:21.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:21.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:21.27#ibcon#[27=AT03-04\r\n] 2006.133.08:00:21.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:21.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:00:21.30#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.08:00:21.30#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:21.30#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:21.42#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:21.42#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:21.44#ibcon#[27=USB\r\n] 2006.133.08:00:21.47#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:21.47#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:00:21.47#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:00:21.47#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:00:21.47$vc4f8/vblo=4,712.99 2006.133.08:00:21.47#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.08:00:21.47#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.08:00:21.47#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:21.47#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:21.47#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:21.47#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:21.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:00:21.53#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:21.53#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:00:21.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:00:21.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:00:21.53$vc4f8/vb=4,4 2006.133.08:00:21.53#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.08:00:21.53#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.08:00:21.53#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:21.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:21.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:21.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:21.61#ibcon#[27=AT04-04\r\n] 2006.133.08:00:21.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:21.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:00:21.64#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.08:00:21.64#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:21.64#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:21.76#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:21.76#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:21.78#ibcon#[27=USB\r\n] 2006.133.08:00:21.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:21.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:00:21.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:00:21.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:00:21.83$vc4f8/vblo=5,744.99 2006.133.08:00:21.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.08:00:21.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.08:00:21.83#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:21.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:00:21.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:00:21.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:00:21.84#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:00:21.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:00:21.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:00:21.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:00:21.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:00:21.88$vc4f8/vb=5,4 2006.133.08:00:21.88#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.08:00:21.88#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.08:00:21.88#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:21.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:00:21.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:00:21.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:00:21.97#ibcon#[27=AT05-04\r\n] 2006.133.08:00:22.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:00:22.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:00:22.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.08:00:22.00#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:22.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:00:22.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:00:22.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:00:22.14#ibcon#[27=USB\r\n] 2006.133.08:00:22.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:00:22.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:00:22.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:00:22.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:00:22.17$vc4f8/vblo=6,752.99 2006.133.08:00:22.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.08:00:22.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.08:00:22.17#ibcon#ireg 17 cls_cnt 0 2006.133.08:00:22.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:22.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:22.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:22.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:00:22.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:22.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:00:22.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:00:22.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:00:22.23$vc4f8/vb=6,4 2006.133.08:00:22.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.08:00:22.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.08:00:22.23#ibcon#ireg 11 cls_cnt 2 2006.133.08:00:22.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:22.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:22.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:22.31#ibcon#[27=AT06-04\r\n] 2006.133.08:00:22.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:22.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:00:22.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.08:00:22.34#ibcon#ireg 7 cls_cnt 0 2006.133.08:00:22.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:22.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:22.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:22.48#ibcon#[27=USB\r\n] 2006.133.08:00:22.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:22.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:00:22.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:00:22.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:00:22.51$vc4f8/vabw=wide 2006.133.08:00:22.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:00:22.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:00:22.51#ibcon#ireg 8 cls_cnt 0 2006.133.08:00:22.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:22.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:22.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:22.53#ibcon#[25=BW32\r\n] 2006.133.08:00:22.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:22.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:00:22.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:00:22.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:00:22.56$vc4f8/vbbw=wide 2006.133.08:00:22.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:00:22.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:00:22.56#ibcon#ireg 8 cls_cnt 0 2006.133.08:00:22.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:00:22.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:00:22.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:00:22.65#ibcon#[27=BW32\r\n] 2006.133.08:00:22.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:00:22.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:00:22.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:00:22.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:00:22.68$4f8m12a/ifd4f 2006.133.08:00:22.68$ifd4f/lo= 2006.133.08:00:22.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:00:22.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:00:22.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:00:22.68$ifd4f/patch= 2006.133.08:00:22.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:00:22.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:00:22.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:00:22.68$4f8m12a/"form=m,16.000,1:2 2006.133.08:00:22.68$4f8m12a/"tpicd 2006.133.08:00:22.68$4f8m12a/echo=off 2006.133.08:00:22.68$4f8m12a/xlog=off 2006.133.08:00:22.68:!2006.133.08:00:50 2006.133.08:00:31.14#trakl#Source acquired 2006.133.08:00:32.14#flagr#flagr/antenna,acquired 2006.133.08:00:50.00:preob 2006.133.08:00:51.14/onsource/TRACKING 2006.133.08:00:51.14:!2006.133.08:01:00 2006.133.08:01:00.00:data_valid=on 2006.133.08:01:00.00:midob 2006.133.08:01:00.14/onsource/TRACKING 2006.133.08:01:00.14/wx/11.31,1009.9,100 2006.133.08:01:00.21/cable/+6.5593E-03 2006.133.08:01:01.30/va/01,08,usb,yes,45,48 2006.133.08:01:01.30/va/02,07,usb,yes,46,48 2006.133.08:01:01.30/va/03,06,usb,yes,49,49 2006.133.08:01:01.30/va/04,07,usb,yes,47,50 2006.133.08:01:01.30/va/05,06,usb,yes,55,58 2006.133.08:01:01.30/va/06,05,usb,yes,56,55 2006.133.08:01:01.30/va/07,05,usb,yes,56,56 2006.133.08:01:01.30/va/08,06,usb,yes,52,51 2006.133.08:01:01.53/valo/01,532.99,yes,locked 2006.133.08:01:01.53/valo/02,572.99,yes,locked 2006.133.08:01:01.53/valo/03,672.99,yes,locked 2006.133.08:01:01.53/valo/04,832.99,yes,locked 2006.133.08:01:01.53/valo/05,652.99,yes,locked 2006.133.08:01:01.53/valo/06,772.99,yes,locked 2006.133.08:01:01.53/valo/07,832.99,yes,locked 2006.133.08:01:01.53/valo/08,852.99,yes,locked 2006.133.08:01:02.62/vb/01,04,usb,yes,30,29 2006.133.08:01:02.62/vb/02,04,usb,yes,32,34 2006.133.08:01:02.62/vb/03,04,usb,yes,28,32 2006.133.08:01:02.62/vb/04,04,usb,yes,29,30 2006.133.08:01:02.62/vb/05,04,usb,yes,28,32 2006.133.08:01:02.62/vb/06,04,usb,yes,29,32 2006.133.08:01:02.62/vb/07,04,usb,yes,31,31 2006.133.08:01:02.62/vb/08,04,usb,yes,29,32 2006.133.08:01:02.85/vblo/01,632.99,yes,locked 2006.133.08:01:02.85/vblo/02,640.99,yes,locked 2006.133.08:01:02.85/vblo/03,656.99,yes,locked 2006.133.08:01:02.85/vblo/04,712.99,yes,locked 2006.133.08:01:02.85/vblo/05,744.99,yes,locked 2006.133.08:01:02.85/vblo/06,752.99,yes,locked 2006.133.08:01:02.85/vblo/07,734.99,yes,locked 2006.133.08:01:02.85/vblo/08,744.99,yes,locked 2006.133.08:01:03.00/vabw/8 2006.133.08:01:03.15/vbbw/8 2006.133.08:01:03.24/xfe/off,on,15.2 2006.133.08:01:03.61/ifatt/23,28,28,28 2006.133.08:01:04.08/fmout-gps/S +1.91E-07 2006.133.08:01:04.12:!2006.133.08:02:00 2006.133.08:02:00.01:data_valid=off 2006.133.08:02:00.01:postob 2006.133.08:02:00.24/cable/+6.5567E-03 2006.133.08:02:00.24/wx/11.30,1009.9,100 2006.133.08:02:01.08/fmout-gps/S +1.91E-07 2006.133.08:02:01.08:scan_name=133-0802,k06133,60 2006.133.08:02:01.09:source=1044+719,104827.62,714335.9,2000.0,cw 2006.133.08:02:01.14#flagr#flagr/antenna,new-source 2006.133.08:02:02.14:checkk5 2006.133.08:02:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:02:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:02:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:02:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:02:04.00/chk_obsdata//k5ts1/T1330801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:02:04.37/chk_obsdata//k5ts2/T1330801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:02:04.74/chk_obsdata//k5ts3/T1330801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:02:05.11/chk_obsdata//k5ts4/T1330801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:02:05.80/k5log//k5ts1_log_newline 2006.133.08:02:06.48/k5log//k5ts2_log_newline 2006.133.08:02:07.17/k5log//k5ts3_log_newline 2006.133.08:02:07.85/k5log//k5ts4_log_newline 2006.133.08:02:07.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:02:07.87:4f8m12a=2 2006.133.08:02:07.87$4f8m12a/echo=on 2006.133.08:02:07.87$4f8m12a/pcalon 2006.133.08:02:07.87$pcalon/"no phase cal control is implemented here 2006.133.08:02:07.87$4f8m12a/"tpicd=stop 2006.133.08:02:07.87$4f8m12a/vc4f8 2006.133.08:02:07.87$vc4f8/valo=1,532.99 2006.133.08:02:07.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.08:02:07.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.08:02:07.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:07.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:02:07.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:02:07.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:02:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:02:07.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:02:07.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:02:07.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:02:07.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:02:07.96$vc4f8/va=1,8 2006.133.08:02:07.96#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.08:02:07.96#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.08:02:07.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:07.96#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:02:07.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:02:07.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:02:07.99#ibcon#[25=AT01-08\r\n] 2006.133.08:02:08.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:02:08.02#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:02:08.02#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.08:02:08.02#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:08.02#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:02:08.14#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:02:08.14#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:02:08.16#ibcon#[25=USB\r\n] 2006.133.08:02:08.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:02:08.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:02:08.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:02:08.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:02:08.19$vc4f8/valo=2,572.99 2006.133.08:02:08.19#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.08:02:08.19#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.08:02:08.19#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:08.19#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:02:08.19#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:02:08.19#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:02:08.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:02:08.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:02:08.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:02:08.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:02:08.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:02:08.26$vc4f8/va=2,7 2006.133.08:02:08.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.08:02:08.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.08:02:08.26#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:08.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:02:08.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:02:08.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:02:08.33#ibcon#[25=AT02-07\r\n] 2006.133.08:02:08.36#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:02:08.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:02:08.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.08:02:08.36#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:08.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:02:08.48#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:02:08.48#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:02:08.50#ibcon#[25=USB\r\n] 2006.133.08:02:08.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:02:08.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:02:08.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:02:08.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:02:08.55$vc4f8/valo=3,672.99 2006.133.08:02:08.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:02:08.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:02:08.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:08.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:08.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:08.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:08.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:02:08.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:08.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:08.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:02:08.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:02:08.60$vc4f8/va=3,6 2006.133.08:02:08.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.08:02:08.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.08:02:08.60#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:08.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:08.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:08.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:08.69#ibcon#[25=AT03-06\r\n] 2006.133.08:02:08.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:08.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:08.72#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.08:02:08.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:08.72#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:08.84#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:08.84#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:08.86#ibcon#[25=USB\r\n] 2006.133.08:02:08.89#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:08.89#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:08.89#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:02:08.89#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:02:08.89$vc4f8/valo=4,832.99 2006.133.08:02:08.89#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.08:02:08.89#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.08:02:08.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:08.89#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:08.89#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:08.89#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:02:08.95#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:08.95#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:08.95#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:02:08.95#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:02:08.95$vc4f8/va=4,7 2006.133.08:02:08.95#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.08:02:08.95#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.08:02:08.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:08.95#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:09.01#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:09.01#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:09.03#ibcon#[25=AT04-07\r\n] 2006.133.08:02:09.06#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:09.06#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:09.06#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.08:02:09.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:09.06#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:09.18#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:09.18#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:09.20#ibcon#[25=USB\r\n] 2006.133.08:02:09.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:09.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:09.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:02:09.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:02:09.23$vc4f8/valo=5,652.99 2006.133.08:02:09.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:02:09.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:02:09.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:09.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:09.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:09.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:02:09.29#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:09.29#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:09.29#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:02:09.29#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:02:09.29$vc4f8/va=5,6 2006.133.08:02:09.29#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.08:02:09.29#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.08:02:09.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:09.29#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:09.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:09.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:09.37#ibcon#[25=AT05-06\r\n] 2006.133.08:02:09.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:09.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:09.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.08:02:09.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:09.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:09.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:09.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:09.54#ibcon#[25=USB\r\n] 2006.133.08:02:09.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:09.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:09.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:02:09.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:02:09.59$vc4f8/valo=6,772.99 2006.133.08:02:09.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:02:09.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:02:09.59#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:09.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:09.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:09.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:02:09.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:09.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:09.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:02:09.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:02:09.64$vc4f8/va=6,5 2006.133.08:02:09.64#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:02:09.64#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:02:09.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:09.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:09.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:09.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:09.73#ibcon#[25=AT06-05\r\n] 2006.133.08:02:09.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:09.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:09.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:02:09.76#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:09.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:09.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:09.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:09.90#ibcon#[25=USB\r\n] 2006.133.08:02:09.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:09.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:09.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:02:09.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:02:09.93$vc4f8/valo=7,832.99 2006.133.08:02:09.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:02:09.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:02:09.93#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:09.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:09.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:09.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:02:09.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:09.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:09.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:02:09.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:02:09.99$vc4f8/va=7,5 2006.133.08:02:09.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.08:02:09.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.08:02:09.99#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:09.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:10.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:10.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:10.07#ibcon#[25=AT07-05\r\n] 2006.133.08:02:10.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:10.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:10.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.08:02:10.10#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:10.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:02:10.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:02:10.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:02:10.24#ibcon#[25=USB\r\n] 2006.133.08:02:10.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:02:10.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:02:10.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:02:10.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:02:10.27$vc4f8/valo=8,852.99 2006.133.08:02:10.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.08:02:10.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.08:02:10.27#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:10.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:02:10.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:02:10.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:02:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:02:10.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:02:10.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:02:10.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:02:10.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:02:10.33$vc4f8/va=8,6 2006.133.08:02:10.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.08:02:10.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.08:02:10.33#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:10.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:02:10.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:02:10.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:02:10.41#ibcon#[25=AT08-06\r\n] 2006.133.08:02:10.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:02:10.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:02:10.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.08:02:10.44#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:10.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:02:10.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:02:10.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:02:10.58#ibcon#[25=USB\r\n] 2006.133.08:02:10.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:02:10.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:02:10.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:02:10.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:02:10.61$vc4f8/vblo=1,632.99 2006.133.08:02:10.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.08:02:10.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.08:02:10.61#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:10.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:02:10.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:02:10.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:02:10.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:02:10.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:02:10.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:02:10.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:02:10.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:02:10.67$vc4f8/vb=1,4 2006.133.08:02:10.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.08:02:10.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.08:02:10.67#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:10.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:02:10.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:02:10.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:02:10.69#ibcon#[27=AT01-04\r\n] 2006.133.08:02:10.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:02:10.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:02:10.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.08:02:10.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:10.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:02:10.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:02:10.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:02:10.86#ibcon#[27=USB\r\n] 2006.133.08:02:10.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:02:10.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:02:10.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:02:10.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:02:10.89$vc4f8/vblo=2,640.99 2006.133.08:02:10.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:02:10.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:02:10.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:10.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:02:10.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:02:10.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:02:10.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:02:10.92#abcon#<5=/16 0.7 1.8 11.301001009.9\r\n> 2006.133.08:02:10.94#abcon#{5=INTERFACE CLEAR} 2006.133.08:02:10.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:02:10.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:02:10.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:02:10.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:02:10.95$vc4f8/vb=2,4 2006.133.08:02:10.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:02:10.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:02:10.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:10.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:02:11.00#abcon#[5=S1D000X0/0*\r\n] 2006.133.08:02:11.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:02:11.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:02:11.03#ibcon#[27=AT02-04\r\n] 2006.133.08:02:11.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:02:11.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:02:11.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:02:11.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:11.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:02:11.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:02:11.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:02:11.20#ibcon#[27=USB\r\n] 2006.133.08:02:11.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:02:11.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:02:11.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:02:11.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:02:11.25$vc4f8/vblo=3,656.99 2006.133.08:02:11.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:02:11.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:02:11.25#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:11.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:11.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:11.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:02:11.30#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:11.30#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:02:11.30#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:02:11.30#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:02:11.30$vc4f8/vb=3,4 2006.133.08:02:11.30#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.08:02:11.30#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.08:02:11.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:11.30#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:11.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:11.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:11.39#ibcon#[27=AT03-04\r\n] 2006.133.08:02:11.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:11.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:02:11.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.08:02:11.42#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:11.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:11.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:11.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:11.56#ibcon#[27=USB\r\n] 2006.133.08:02:11.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:11.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:02:11.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:02:11.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:02:11.59$vc4f8/vblo=4,712.99 2006.133.08:02:11.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.08:02:11.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.08:02:11.59#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:11.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:11.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:11.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:02:11.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:11.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:02:11.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:02:11.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:02:11.65$vc4f8/vb=4,4 2006.133.08:02:11.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.08:02:11.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.08:02:11.65#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:11.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:11.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:11.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:11.73#ibcon#[27=AT04-04\r\n] 2006.133.08:02:11.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:11.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:02:11.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.08:02:11.76#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:11.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:11.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:11.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:11.90#ibcon#[27=USB\r\n] 2006.133.08:02:11.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:11.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:02:11.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:02:11.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:02:11.93$vc4f8/vblo=5,744.99 2006.133.08:02:11.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:02:11.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:02:11.93#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:11.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:11.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:11.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:02:11.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:11.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:02:11.99#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:02:11.99#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:02:11.99$vc4f8/vb=5,4 2006.133.08:02:11.99#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.08:02:11.99#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.08:02:11.99#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:11.99#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:12.05#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:12.05#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:12.07#ibcon#[27=AT05-04\r\n] 2006.133.08:02:12.10#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:12.10#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:02:12.10#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.08:02:12.10#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:12.10#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:12.22#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:12.22#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:12.24#ibcon#[27=USB\r\n] 2006.133.08:02:12.27#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:12.27#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:02:12.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:02:12.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:02:12.27$vc4f8/vblo=6,752.99 2006.133.08:02:12.27#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:02:12.27#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:02:12.27#ibcon#ireg 17 cls_cnt 0 2006.133.08:02:12.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:12.27#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:12.27#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:02:12.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:12.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:02:12.33#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:02:12.33#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:02:12.33$vc4f8/vb=6,4 2006.133.08:02:12.33#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:02:12.33#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:02:12.33#ibcon#ireg 11 cls_cnt 2 2006.133.08:02:12.33#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:12.39#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:12.39#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:12.41#ibcon#[27=AT06-04\r\n] 2006.133.08:02:12.44#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:12.44#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:02:12.44#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:02:12.44#ibcon#ireg 7 cls_cnt 0 2006.133.08:02:12.44#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:12.56#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:12.56#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:12.58#ibcon#[27=USB\r\n] 2006.133.08:02:12.61#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:12.61#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:02:12.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:02:12.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:02:12.61$vc4f8/vabw=wide 2006.133.08:02:12.61#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:02:12.61#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:02:12.61#ibcon#ireg 8 cls_cnt 0 2006.133.08:02:12.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:12.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:12.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:12.63#ibcon#[25=BW32\r\n] 2006.133.08:02:12.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:12.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:02:12.66#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:02:12.66#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:02:12.66$vc4f8/vbbw=wide 2006.133.08:02:12.66#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.08:02:12.66#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.08:02:12.66#ibcon#ireg 8 cls_cnt 0 2006.133.08:02:12.66#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:02:12.73#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:02:12.73#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:02:12.75#ibcon#[27=BW32\r\n] 2006.133.08:02:12.78#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:02:12.78#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:02:12.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:02:12.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:02:12.78$4f8m12a/ifd4f 2006.133.08:02:12.78$ifd4f/lo= 2006.133.08:02:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:02:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:02:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:02:12.78$ifd4f/patch= 2006.133.08:02:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:02:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:02:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:02:12.78$4f8m12a/"form=m,16.000,1:2 2006.133.08:02:12.78$4f8m12a/"tpicd 2006.133.08:02:12.78$4f8m12a/echo=off 2006.133.08:02:12.78$4f8m12a/xlog=off 2006.133.08:02:12.78:!2006.133.08:02:40 2006.133.08:02:20.14#trakl#Source acquired 2006.133.08:02:22.14#flagr#flagr/antenna,acquired 2006.133.08:02:40.00:preob 2006.133.08:02:41.14/onsource/TRACKING 2006.133.08:02:41.14:!2006.133.08:02:50 2006.133.08:02:50.00:data_valid=on 2006.133.08:02:50.00:midob 2006.133.08:02:50.14/onsource/TRACKING 2006.133.08:02:50.14/wx/11.30,1009.9,100 2006.133.08:02:50.28/cable/+6.5580E-03 2006.133.08:02:51.37/va/01,08,usb,yes,47,49 2006.133.08:02:51.37/va/02,07,usb,yes,47,49 2006.133.08:02:51.37/va/03,06,usb,yes,50,50 2006.133.08:02:51.37/va/04,07,usb,yes,48,52 2006.133.08:02:51.37/va/05,06,usb,yes,56,59 2006.133.08:02:51.37/va/06,05,usb,yes,57,57 2006.133.08:02:51.37/va/07,05,usb,yes,57,57 2006.133.08:02:51.37/va/08,06,usb,yes,53,52 2006.133.08:02:51.60/valo/01,532.99,yes,locked 2006.133.08:02:51.60/valo/02,572.99,yes,locked 2006.133.08:02:51.60/valo/03,672.99,yes,locked 2006.133.08:02:51.60/valo/04,832.99,yes,locked 2006.133.08:02:51.60/valo/05,652.99,yes,locked 2006.133.08:02:51.60/valo/06,772.99,yes,locked 2006.133.08:02:51.60/valo/07,832.99,yes,locked 2006.133.08:02:51.60/valo/08,852.99,yes,locked 2006.133.08:02:52.69/vb/01,04,usb,yes,30,29 2006.133.08:02:52.69/vb/02,04,usb,yes,32,34 2006.133.08:02:52.69/vb/03,04,usb,yes,28,32 2006.133.08:02:52.69/vb/04,04,usb,yes,29,30 2006.133.08:02:52.69/vb/05,04,usb,yes,28,32 2006.133.08:02:52.69/vb/06,04,usb,yes,29,32 2006.133.08:02:52.69/vb/07,04,usb,yes,31,31 2006.133.08:02:52.69/vb/08,04,usb,yes,29,32 2006.133.08:02:52.92/vblo/01,632.99,yes,locked 2006.133.08:02:52.92/vblo/02,640.99,yes,locked 2006.133.08:02:52.92/vblo/03,656.99,yes,locked 2006.133.08:02:52.92/vblo/04,712.99,yes,locked 2006.133.08:02:52.92/vblo/05,744.99,yes,locked 2006.133.08:02:52.92/vblo/06,752.99,yes,locked 2006.133.08:02:52.92/vblo/07,734.99,yes,locked 2006.133.08:02:52.92/vblo/08,744.99,yes,locked 2006.133.08:02:53.07/vabw/8 2006.133.08:02:53.22/vbbw/8 2006.133.08:02:53.31/xfe/off,on,15.2 2006.133.08:02:53.69/ifatt/23,28,28,28 2006.133.08:02:54.08/fmout-gps/S +1.90E-07 2006.133.08:02:54.12:!2006.133.08:03:50 2006.133.08:03:50.01:data_valid=off 2006.133.08:03:50.01:postob 2006.133.08:03:50.09/cable/+6.5571E-03 2006.133.08:03:50.10/wx/11.29,1009.8,100 2006.133.08:03:51.08/fmout-gps/S +1.90E-07 2006.133.08:03:51.08:scan_name=133-0804,k06133,60 2006.133.08:03:51.09:source=0749+540,075301.38,535300.0,2000.0,ccw 2006.133.08:03:51.14#flagr#flagr/antenna,new-source 2006.133.08:03:52.14:checkk5 2006.133.08:03:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:03:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:03:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:03:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:03:54.01/chk_obsdata//k5ts1/T1330802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:03:54.37/chk_obsdata//k5ts2/T1330802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:03:54.74/chk_obsdata//k5ts3/T1330802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:03:55.10/chk_obsdata//k5ts4/T1330802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:03:55.79/k5log//k5ts1_log_newline 2006.133.08:03:56.47/k5log//k5ts2_log_newline 2006.133.08:03:57.16/k5log//k5ts3_log_newline 2006.133.08:03:57.85/k5log//k5ts4_log_newline 2006.133.08:03:57.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:03:57.87:4f8m12a=2 2006.133.08:03:57.88$4f8m12a/echo=on 2006.133.08:03:57.88$4f8m12a/pcalon 2006.133.08:03:57.88$pcalon/"no phase cal control is implemented here 2006.133.08:03:57.88$4f8m12a/"tpicd=stop 2006.133.08:03:57.88$4f8m12a/vc4f8 2006.133.08:03:57.88$vc4f8/valo=1,532.99 2006.133.08:03:57.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:03:57.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:03:57.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:57.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:03:57.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:03:57.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:03:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:03:57.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:03:57.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:03:57.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:03:57.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:03:57.97$vc4f8/va=1,8 2006.133.08:03:57.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:03:57.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:03:57.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:57.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:03:57.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:03:57.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:03:58.00#ibcon#[25=AT01-08\r\n] 2006.133.08:03:58.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:03:58.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:03:58.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:03:58.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:58.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:03:58.15#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:03:58.15#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:03:58.17#ibcon#[25=USB\r\n] 2006.133.08:03:58.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:03:58.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:03:58.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:03:58.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:03:58.22$vc4f8/valo=2,572.99 2006.133.08:03:58.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:03:58.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:03:58.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:58.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:03:58.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:03:58.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:03:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:03:58.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:03:58.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:03:58.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:03:58.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:03:58.27$vc4f8/va=2,7 2006.133.08:03:58.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:03:58.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:03:58.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:58.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:03:58.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:03:58.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:03:58.36#ibcon#[25=AT02-07\r\n] 2006.133.08:03:58.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:03:58.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:03:58.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:03:58.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:58.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:03:58.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:03:58.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:03:58.53#ibcon#[25=USB\r\n] 2006.133.08:03:58.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:03:58.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:03:58.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:03:58.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:03:58.56$vc4f8/valo=3,672.99 2006.133.08:03:58.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:03:58.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:03:58.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:58.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:03:58.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:03:58.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:03:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:03:58.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:03:58.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:03:58.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:03:58.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:03:58.63$vc4f8/va=3,6 2006.133.08:03:58.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:03:58.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:03:58.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:58.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:03:58.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:03:58.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:03:58.70#ibcon#[25=AT03-06\r\n] 2006.133.08:03:58.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:03:58.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:03:58.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:03:58.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:58.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:03:58.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:03:58.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:03:58.87#ibcon#[25=USB\r\n] 2006.133.08:03:58.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:03:58.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:03:58.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:03:58.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:03:58.90$vc4f8/valo=4,832.99 2006.133.08:03:58.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:03:58.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:03:58.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:58.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:03:58.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:03:58.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:03:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:03:58.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:03:58.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:03:58.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:03:58.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:03:58.96$vc4f8/va=4,7 2006.133.08:03:58.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:03:58.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:03:58.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:58.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:03:59.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:03:59.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:03:59.04#ibcon#[25=AT04-07\r\n] 2006.133.08:03:59.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:03:59.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:03:59.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:03:59.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:59.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:03:59.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:03:59.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:03:59.21#ibcon#[25=USB\r\n] 2006.133.08:03:59.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:03:59.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:03:59.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:03:59.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:03:59.24$vc4f8/valo=5,652.99 2006.133.08:03:59.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:03:59.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:03:59.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:59.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:03:59.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:03:59.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:03:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:03:59.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:03:59.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:03:59.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:03:59.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:03:59.30$vc4f8/va=5,6 2006.133.08:03:59.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.08:03:59.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.08:03:59.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:59.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:03:59.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:03:59.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:03:59.38#ibcon#[25=AT05-06\r\n] 2006.133.08:03:59.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:03:59.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:03:59.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.08:03:59.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:59.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:03:59.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:03:59.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:03:59.55#ibcon#[25=USB\r\n] 2006.133.08:03:59.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:03:59.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:03:59.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:03:59.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:03:59.58$vc4f8/valo=6,772.99 2006.133.08:03:59.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:03:59.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:03:59.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:59.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:03:59.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:03:59.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:03:59.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:03:59.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:03:59.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:03:59.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:03:59.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:03:59.64$vc4f8/va=6,5 2006.133.08:03:59.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:03:59.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:03:59.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:59.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:03:59.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:03:59.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:03:59.72#ibcon#[25=AT06-05\r\n] 2006.133.08:03:59.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:03:59.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:03:59.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:03:59.75#ibcon#ireg 7 cls_cnt 0 2006.133.08:03:59.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:03:59.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:03:59.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:03:59.89#ibcon#[25=USB\r\n] 2006.133.08:03:59.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:03:59.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:03:59.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:03:59.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:03:59.92$vc4f8/valo=7,832.99 2006.133.08:03:59.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:03:59.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:03:59.92#ibcon#ireg 17 cls_cnt 0 2006.133.08:03:59.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:03:59.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:03:59.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:03:59.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:03:59.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:03:59.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:03:59.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:03:59.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:03:59.98$vc4f8/va=7,5 2006.133.08:03:59.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:03:59.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:03:59.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:03:59.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:04:00.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:04:00.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:04:00.06#ibcon#[25=AT07-05\r\n] 2006.133.08:04:00.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:04:00.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:04:00.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:04:00.09#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:00.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:04:00.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:04:00.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:04:00.23#ibcon#[25=USB\r\n] 2006.133.08:04:00.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:04:00.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:04:00.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:04:00.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:04:00.26$vc4f8/valo=8,852.99 2006.133.08:04:00.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:04:00.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:04:00.26#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:00.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:04:00.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:04:00.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:04:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:04:00.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:04:00.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:04:00.33#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:04:00.33#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:04:00.33$vc4f8/va=8,6 2006.133.08:04:00.33#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:04:00.33#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:04:00.33#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:00.33#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:04:00.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:04:00.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:04:00.40#ibcon#[25=AT08-06\r\n] 2006.133.08:04:00.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:04:00.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:04:00.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:04:00.43#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:00.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:04:00.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:04:00.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:04:00.57#ibcon#[25=USB\r\n] 2006.133.08:04:00.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:04:00.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:04:00.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:04:00.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:04:00.60$vc4f8/vblo=1,632.99 2006.133.08:04:00.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:04:00.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:04:00.60#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:00.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:04:00.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:04:00.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:04:00.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:04:00.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:04:00.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:04:00.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:04:00.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:04:00.66$vc4f8/vb=1,4 2006.133.08:04:00.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:04:00.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:04:00.66#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:00.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:04:00.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:04:00.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:04:00.68#ibcon#[27=AT01-04\r\n] 2006.133.08:04:00.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:04:00.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:04:00.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:04:00.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:00.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:04:00.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:04:00.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:04:00.85#ibcon#[27=USB\r\n] 2006.133.08:04:00.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:04:00.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:04:00.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:04:00.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:04:00.88$vc4f8/vblo=2,640.99 2006.133.08:04:00.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:04:00.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:04:00.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:00.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:04:00.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:04:00.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:04:00.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:04:00.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:04:00.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:04:00.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:04:00.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:04:00.94$vc4f8/vb=2,4 2006.133.08:04:00.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:04:00.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:04:00.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:00.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:04:01.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:04:01.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:04:01.02#ibcon#[27=AT02-04\r\n] 2006.133.08:04:01.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:04:01.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:04:01.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:04:01.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:01.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:04:01.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:04:01.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:04:01.19#ibcon#[27=USB\r\n] 2006.133.08:04:01.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:04:01.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:04:01.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:04:01.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:04:01.22$vc4f8/vblo=3,656.99 2006.133.08:04:01.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:04:01.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:04:01.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:01.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:04:01.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:04:01.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:04:01.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:04:01.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:04:01.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:04:01.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:04:01.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:04:01.28$vc4f8/vb=3,4 2006.133.08:04:01.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:04:01.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:04:01.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:01.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:04:01.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:04:01.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:04:01.36#ibcon#[27=AT03-04\r\n] 2006.133.08:04:01.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:04:01.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:04:01.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:04:01.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:01.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:04:01.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:04:01.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:04:01.53#ibcon#[27=USB\r\n] 2006.133.08:04:01.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:04:01.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:04:01.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:04:01.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:04:01.56$vc4f8/vblo=4,712.99 2006.133.08:04:01.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:04:01.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:04:01.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:01.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:04:01.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:04:01.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:04:01.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:04:01.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:04:01.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:04:01.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:04:01.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:04:01.62$vc4f8/vb=4,4 2006.133.08:04:01.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:04:01.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:04:01.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:01.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:04:01.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:04:01.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:04:01.70#ibcon#[27=AT04-04\r\n] 2006.133.08:04:01.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:04:01.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:04:01.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:04:01.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:01.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:04:01.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:04:01.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:04:01.87#ibcon#[27=USB\r\n] 2006.133.08:04:01.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:04:01.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:04:01.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:04:01.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:04:01.90$vc4f8/vblo=5,744.99 2006.133.08:04:01.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:04:01.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:04:01.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:01.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:04:01.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:04:01.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:04:01.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:04:01.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:04:01.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:04:01.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:04:01.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:04:01.96$vc4f8/vb=5,4 2006.133.08:04:01.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:04:01.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:04:01.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:01.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:04:02.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:04:02.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:04:02.04#ibcon#[27=AT05-04\r\n] 2006.133.08:04:02.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:04:02.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:04:02.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:04:02.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:02.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:04:02.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:04:02.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:04:02.21#ibcon#[27=USB\r\n] 2006.133.08:04:02.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:04:02.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:04:02.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:04:02.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:04:02.24$vc4f8/vblo=6,752.99 2006.133.08:04:02.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:04:02.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:04:02.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:04:02.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:04:02.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:04:02.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:04:02.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:04:02.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:04:02.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:04:02.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:04:02.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:04:02.30$vc4f8/vb=6,4 2006.133.08:04:02.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.08:04:02.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.08:04:02.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:04:02.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:04:02.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:04:02.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:04:02.38#ibcon#[27=AT06-04\r\n] 2006.133.08:04:02.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:04:02.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:04:02.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.08:04:02.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:04:02.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:04:02.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:04:02.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:04:02.55#ibcon#[27=USB\r\n] 2006.133.08:04:02.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:04:02.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:04:02.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:04:02.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:04:02.58$vc4f8/vabw=wide 2006.133.08:04:02.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:04:02.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:04:02.58#ibcon#ireg 8 cls_cnt 0 2006.133.08:04:02.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:04:02.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:04:02.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:04:02.60#ibcon#[25=BW32\r\n] 2006.133.08:04:02.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:04:02.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:04:02.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:04:02.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:04:02.63$vc4f8/vbbw=wide 2006.133.08:04:02.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.08:04:02.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.08:04:02.63#ibcon#ireg 8 cls_cnt 0 2006.133.08:04:02.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:04:02.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:04:02.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:04:02.72#ibcon#[27=BW32\r\n] 2006.133.08:04:02.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:04:02.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:04:02.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:04:02.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:04:02.75$4f8m12a/ifd4f 2006.133.08:04:02.75$ifd4f/lo= 2006.133.08:04:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:04:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:04:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:04:02.75$ifd4f/patch= 2006.133.08:04:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:04:02.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:04:02.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:04:02.75$4f8m12a/"form=m,16.000,1:2 2006.133.08:04:02.75$4f8m12a/"tpicd 2006.133.08:04:02.75$4f8m12a/echo=off 2006.133.08:04:02.75$4f8m12a/xlog=off 2006.133.08:04:02.75:!2006.133.08:04:30 2006.133.08:04:13.13#trakl#Source acquired 2006.133.08:04:15.13#flagr#flagr/antenna,acquired 2006.133.08:04:30.00:preob 2006.133.08:04:31.13/onsource/TRACKING 2006.133.08:04:31.13:!2006.133.08:04:40 2006.133.08:04:40.00:data_valid=on 2006.133.08:04:40.00:midob 2006.133.08:04:40.13/onsource/TRACKING 2006.133.08:04:40.13/wx/11.28,1009.8,100 2006.133.08:04:40.25/cable/+6.5597E-03 2006.133.08:04:41.34/va/01,08,usb,yes,49,52 2006.133.08:04:41.34/va/02,07,usb,yes,50,51 2006.133.08:04:41.34/va/03,06,usb,yes,52,52 2006.133.08:04:41.34/va/04,07,usb,yes,50,54 2006.133.08:04:41.34/va/05,06,usb,yes,58,62 2006.133.08:04:41.34/va/06,05,usb,yes,60,59 2006.133.08:04:41.34/va/07,05,usb,yes,59,59 2006.133.08:04:41.34/va/08,06,usb,yes,55,54 2006.133.08:04:41.57/valo/01,532.99,yes,locked 2006.133.08:04:41.57/valo/02,572.99,yes,locked 2006.133.08:04:41.57/valo/03,672.99,yes,locked 2006.133.08:04:41.57/valo/04,832.99,yes,locked 2006.133.08:04:41.57/valo/05,652.99,yes,locked 2006.133.08:04:41.57/valo/06,772.99,yes,locked 2006.133.08:04:41.57/valo/07,832.99,yes,locked 2006.133.08:04:41.57/valo/08,852.99,yes,locked 2006.133.08:04:42.66/vb/01,04,usb,yes,31,29 2006.133.08:04:42.66/vb/02,04,usb,yes,33,34 2006.133.08:04:42.66/vb/03,04,usb,yes,29,33 2006.133.08:04:42.66/vb/04,04,usb,yes,30,30 2006.133.08:04:42.66/vb/05,04,usb,yes,28,32 2006.133.08:04:42.66/vb/06,04,usb,yes,29,32 2006.133.08:04:42.66/vb/07,04,usb,yes,31,31 2006.133.08:04:42.66/vb/08,04,usb,yes,29,32 2006.133.08:04:42.89/vblo/01,632.99,yes,locked 2006.133.08:04:42.89/vblo/02,640.99,yes,locked 2006.133.08:04:42.89/vblo/03,656.99,yes,locked 2006.133.08:04:42.89/vblo/04,712.99,yes,locked 2006.133.08:04:42.89/vblo/05,744.99,yes,locked 2006.133.08:04:42.89/vblo/06,752.99,yes,locked 2006.133.08:04:42.89/vblo/07,734.99,yes,locked 2006.133.08:04:42.89/vblo/08,744.99,yes,locked 2006.133.08:04:43.04/vabw/8 2006.133.08:04:43.19/vbbw/8 2006.133.08:04:43.28/xfe/off,on,14.5 2006.133.08:04:43.65/ifatt/23,28,28,28 2006.133.08:04:44.08/fmout-gps/S +1.89E-07 2006.133.08:04:44.12:!2006.133.08:05:40 2006.133.08:05:40.01:data_valid=off 2006.133.08:05:40.01:postob 2006.133.08:05:40.08/cable/+6.5587E-03 2006.133.08:05:40.09/wx/11.27,1009.8,100 2006.133.08:05:41.08/fmout-gps/S +1.90E-07 2006.133.08:05:41.08:scan_name=133-0806,k06133,60 2006.133.08:05:41.09:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.133.08:05:41.13#flagr#flagr/antenna,new-source 2006.133.08:05:42.13:checkk5 2006.133.08:05:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:05:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:05:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:05:43.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:05:44.00/chk_obsdata//k5ts1/T1330804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:05:44.36/chk_obsdata//k5ts2/T1330804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:05:44.73/chk_obsdata//k5ts3/T1330804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:05:45.10/chk_obsdata//k5ts4/T1330804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:05:45.80/k5log//k5ts1_log_newline 2006.133.08:05:46.48/k5log//k5ts2_log_newline 2006.133.08:05:47.17/k5log//k5ts3_log_newline 2006.133.08:05:47.86/k5log//k5ts4_log_newline 2006.133.08:05:47.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:05:47.88:4f8m12a=2 2006.133.08:05:47.88$4f8m12a/echo=on 2006.133.08:05:47.88$4f8m12a/pcalon 2006.133.08:05:47.88$pcalon/"no phase cal control is implemented here 2006.133.08:05:47.88$4f8m12a/"tpicd=stop 2006.133.08:05:47.88$4f8m12a/vc4f8 2006.133.08:05:47.88$vc4f8/valo=1,532.99 2006.133.08:05:47.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.08:05:47.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.08:05:47.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:47.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:47.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:47.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:47.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:05:47.97#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:47.97#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:47.97#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:05:47.97#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:05:47.97$vc4f8/va=1,8 2006.133.08:05:47.97#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.08:05:47.97#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.08:05:47.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:47.97#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:47.97#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:47.97#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:47.99#ibcon#[25=AT01-08\r\n] 2006.133.08:05:48.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:48.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:48.02#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.08:05:48.02#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:48.02#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:48.14#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:48.14#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:48.16#ibcon#[25=USB\r\n] 2006.133.08:05:48.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:48.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:48.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:05:48.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:05:48.20$vc4f8/valo=2,572.99 2006.133.08:05:48.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:05:48.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:05:48.20#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:48.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:48.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:48.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:48.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:05:48.25#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:48.25#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:48.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:05:48.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:05:48.25$vc4f8/va=2,7 2006.133.08:05:48.25#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:05:48.25#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:05:48.25#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:48.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:48.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:48.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:48.34#ibcon#[25=AT02-07\r\n] 2006.133.08:05:48.37#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:48.37#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:48.37#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:05:48.37#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:48.37#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:48.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:48.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:48.51#ibcon#[25=USB\r\n] 2006.133.08:05:48.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:48.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:48.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:05:48.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:05:48.56$vc4f8/valo=3,672.99 2006.133.08:05:48.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:05:48.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:05:48.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:48.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:48.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:48.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:48.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:05:48.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:48.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:48.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:05:48.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:05:48.61$vc4f8/va=3,6 2006.133.08:05:48.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:05:48.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:05:48.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:48.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:48.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:48.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:48.70#ibcon#[25=AT03-06\r\n] 2006.133.08:05:48.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:48.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:48.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:05:48.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:48.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:48.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:48.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:48.87#ibcon#[25=USB\r\n] 2006.133.08:05:48.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:48.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:48.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:05:48.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:05:48.90$vc4f8/valo=4,832.99 2006.133.08:05:48.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:05:48.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:05:48.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:48.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:48.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:48.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:48.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:05:48.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:48.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:48.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:05:48.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:05:48.96$vc4f8/va=4,7 2006.133.08:05:48.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.08:05:48.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.08:05:48.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:48.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:49.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:49.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:49.04#ibcon#[25=AT04-07\r\n] 2006.133.08:05:49.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:49.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:49.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.08:05:49.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:49.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:49.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:49.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:49.21#ibcon#[25=USB\r\n] 2006.133.08:05:49.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:49.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:49.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:05:49.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:05:49.24$vc4f8/valo=5,652.99 2006.133.08:05:49.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:05:49.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:05:49.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:49.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:49.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:49.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:49.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:05:49.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:49.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:49.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:05:49.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:05:49.30$vc4f8/va=5,6 2006.133.08:05:49.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.08:05:49.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.08:05:49.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:49.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:49.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:49.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:49.38#ibcon#[25=AT05-06\r\n] 2006.133.08:05:49.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:49.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:49.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.08:05:49.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:49.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:49.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:49.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:49.55#ibcon#[25=USB\r\n] 2006.133.08:05:49.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:49.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:49.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:05:49.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:05:49.58$vc4f8/valo=6,772.99 2006.133.08:05:49.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.08:05:49.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.08:05:49.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:49.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:49.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:49.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:49.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:05:49.64#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:49.64#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:49.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:05:49.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:05:49.64$vc4f8/va=6,5 2006.133.08:05:49.64#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.08:05:49.64#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.08:05:49.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:49.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:49.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:49.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:49.72#ibcon#[25=AT06-05\r\n] 2006.133.08:05:49.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:49.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:49.75#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.08:05:49.75#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:49.75#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:05:49.87#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:05:49.87#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:05:49.89#ibcon#[25=USB\r\n] 2006.133.08:05:49.92#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:05:49.92#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:05:49.92#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:05:49.92#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:05:49.92$vc4f8/valo=7,832.99 2006.133.08:05:49.92#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.08:05:49.92#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.08:05:49.92#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:49.92#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:05:49.92#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:05:49.92#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:05:49.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:05:49.98#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:05:49.98#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:05:49.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:05:49.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:05:49.98$vc4f8/va=7,5 2006.133.08:05:49.98#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.08:05:49.98#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.08:05:49.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:49.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:05:50.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:05:50.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:05:50.06#ibcon#[25=AT07-05\r\n] 2006.133.08:05:50.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:05:50.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:05:50.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.08:05:50.09#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:50.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:05:50.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:05:50.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:05:50.23#ibcon#[25=USB\r\n] 2006.133.08:05:50.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:05:50.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:05:50.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:05:50.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:05:50.26$vc4f8/valo=8,852.99 2006.133.08:05:50.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.08:05:50.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.08:05:50.26#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:50.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:05:50.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:05:50.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:05:50.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:05:50.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:05:50.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:05:50.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:05:50.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:05:50.32$vc4f8/va=8,6 2006.133.08:05:50.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.08:05:50.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.08:05:50.32#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:50.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:05:50.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:05:50.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:05:50.40#ibcon#[25=AT08-06\r\n] 2006.133.08:05:50.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:05:50.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:05:50.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.08:05:50.43#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:50.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:05:50.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:05:50.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:05:50.57#ibcon#[25=USB\r\n] 2006.133.08:05:50.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:05:50.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:05:50.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:05:50.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:05:50.60$vc4f8/vblo=1,632.99 2006.133.08:05:50.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.08:05:50.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.08:05:50.60#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:50.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:05:50.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:05:50.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:05:50.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:05:50.66#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:05:50.66#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:05:50.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:05:50.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:05:50.66$vc4f8/vb=1,4 2006.133.08:05:50.66#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.08:05:50.66#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.08:05:50.66#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:50.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:05:50.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:05:50.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:05:50.68#ibcon#[27=AT01-04\r\n] 2006.133.08:05:50.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:05:50.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:05:50.71#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.08:05:50.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:50.71#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:05:50.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:05:50.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:05:50.85#ibcon#[27=USB\r\n] 2006.133.08:05:50.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:05:50.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:05:50.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:05:50.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:05:50.88$vc4f8/vblo=2,640.99 2006.133.08:05:50.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.08:05:50.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.08:05:50.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:50.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:50.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:50.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:50.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:05:50.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:50.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:05:50.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:05:50.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:05:50.94$vc4f8/vb=2,4 2006.133.08:05:50.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.08:05:50.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.08:05:50.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:50.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:51.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:51.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:51.02#ibcon#[27=AT02-04\r\n] 2006.133.08:05:51.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:51.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:05:51.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.08:05:51.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:51.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:51.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:51.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:51.19#ibcon#[27=USB\r\n] 2006.133.08:05:51.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:51.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:05:51.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:05:51.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:05:51.22$vc4f8/vblo=3,656.99 2006.133.08:05:51.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:05:51.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:05:51.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:51.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:51.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:51.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:51.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:05:51.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:51.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:05:51.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:05:51.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:05:51.28$vc4f8/vb=3,4 2006.133.08:05:51.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:05:51.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:05:51.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:51.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:51.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:51.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:51.36#ibcon#[27=AT03-04\r\n] 2006.133.08:05:51.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:51.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:05:51.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:05:51.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:51.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:51.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:51.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:51.53#ibcon#[27=USB\r\n] 2006.133.08:05:51.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:51.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:05:51.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:05:51.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:05:51.56$vc4f8/vblo=4,712.99 2006.133.08:05:51.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:05:51.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:05:51.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:51.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:51.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:51.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:51.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:05:51.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:51.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:05:51.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:05:51.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:05:51.62$vc4f8/vb=4,4 2006.133.08:05:51.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:05:51.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:05:51.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:51.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:51.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:51.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:51.70#ibcon#[27=AT04-04\r\n] 2006.133.08:05:51.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:51.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:05:51.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:05:51.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:51.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:51.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:51.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:51.87#ibcon#[27=USB\r\n] 2006.133.08:05:51.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:51.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:05:51.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:05:51.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:05:51.90$vc4f8/vblo=5,744.99 2006.133.08:05:51.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:05:51.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:05:51.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:51.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:51.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:51.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:51.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:05:51.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:51.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:05:51.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:05:51.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:05:51.96$vc4f8/vb=5,4 2006.133.08:05:51.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.08:05:51.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.08:05:51.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:51.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:52.02#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:52.02#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:52.04#ibcon#[27=AT05-04\r\n] 2006.133.08:05:52.07#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:52.07#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:05:52.07#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.08:05:52.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:52.07#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:52.19#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:52.19#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:52.21#ibcon#[27=USB\r\n] 2006.133.08:05:52.24#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:52.24#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:05:52.24#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:05:52.24#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:05:52.24$vc4f8/vblo=6,752.99 2006.133.08:05:52.24#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:05:52.24#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:05:52.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:05:52.24#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:52.24#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:52.24#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:52.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:05:52.30#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:52.30#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:05:52.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:05:52.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:05:52.30$vc4f8/vb=6,4 2006.133.08:05:52.30#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.08:05:52.30#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.08:05:52.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:05:52.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:52.36#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:52.36#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:52.38#ibcon#[27=AT06-04\r\n] 2006.133.08:05:52.41#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:52.41#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:05:52.41#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.08:05:52.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:05:52.41#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:52.53#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:52.53#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:52.55#ibcon#[27=USB\r\n] 2006.133.08:05:52.58#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:52.58#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:05:52.58#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:05:52.58#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:05:52.58$vc4f8/vabw=wide 2006.133.08:05:52.58#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.08:05:52.58#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.08:05:52.58#ibcon#ireg 8 cls_cnt 0 2006.133.08:05:52.58#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:52.58#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:52.58#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:52.60#ibcon#[25=BW32\r\n] 2006.133.08:05:52.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:52.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:05:52.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:05:52.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:05:52.63$vc4f8/vbbw=wide 2006.133.08:05:52.63#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:05:52.63#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:05:52.63#ibcon#ireg 8 cls_cnt 0 2006.133.08:05:52.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:05:52.70#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:05:52.70#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:05:52.72#ibcon#[27=BW32\r\n] 2006.133.08:05:52.75#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:05:52.75#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:05:52.75#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:05:52.75#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:05:52.75$4f8m12a/ifd4f 2006.133.08:05:52.75$ifd4f/lo= 2006.133.08:05:52.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:05:52.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:05:52.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:05:52.75$ifd4f/patch= 2006.133.08:05:52.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:05:52.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:05:52.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:05:52.75$4f8m12a/"form=m,16.000,1:2 2006.133.08:05:52.75$4f8m12a/"tpicd 2006.133.08:05:52.75$4f8m12a/echo=off 2006.133.08:05:52.75$4f8m12a/xlog=off 2006.133.08:05:52.75:!2006.133.08:06:20 2006.133.08:06:04.13#trakl#Source acquired 2006.133.08:06:05.13#flagr#flagr/antenna,acquired 2006.133.08:06:20.00:preob 2006.133.08:06:21.14/onsource/TRACKING 2006.133.08:06:21.14:!2006.133.08:06:30 2006.133.08:06:30.00:data_valid=on 2006.133.08:06:30.00:midob 2006.133.08:06:30.14/onsource/TRACKING 2006.133.08:06:30.14/wx/11.27,1009.8,100 2006.133.08:06:30.33/cable/+6.5583E-03 2006.133.08:06:31.42/va/01,08,usb,yes,51,53 2006.133.08:06:31.42/va/02,07,usb,yes,51,53 2006.133.08:06:31.42/va/03,06,usb,yes,54,54 2006.133.08:06:31.42/va/04,07,usb,yes,52,56 2006.133.08:06:31.42/va/05,06,usb,yes,61,64 2006.133.08:06:31.42/va/06,05,usb,yes,62,62 2006.133.08:06:31.42/va/07,05,usb,yes,62,61 2006.133.08:06:31.42/va/08,06,usb,yes,58,57 2006.133.08:06:31.65/valo/01,532.99,yes,locked 2006.133.08:06:31.65/valo/02,572.99,yes,locked 2006.133.08:06:31.65/valo/03,672.99,yes,locked 2006.133.08:06:31.65/valo/04,832.99,yes,locked 2006.133.08:06:31.65/valo/05,652.99,yes,locked 2006.133.08:06:31.65/valo/06,772.99,yes,locked 2006.133.08:06:31.65/valo/07,832.99,yes,locked 2006.133.08:06:31.65/valo/08,852.99,yes,locked 2006.133.08:06:32.74/vb/01,04,usb,yes,31,29 2006.133.08:06:32.74/vb/02,04,usb,yes,33,34 2006.133.08:06:32.74/vb/03,04,usb,yes,29,33 2006.133.08:06:32.74/vb/04,04,usb,yes,30,30 2006.133.08:06:32.74/vb/05,04,usb,yes,28,33 2006.133.08:06:32.74/vb/06,04,usb,yes,30,32 2006.133.08:06:32.74/vb/07,04,usb,yes,32,31 2006.133.08:06:32.74/vb/08,04,usb,yes,29,32 2006.133.08:06:32.98/vblo/01,632.99,yes,locked 2006.133.08:06:32.98/vblo/02,640.99,yes,locked 2006.133.08:06:32.98/vblo/03,656.99,yes,locked 2006.133.08:06:32.98/vblo/04,712.99,yes,locked 2006.133.08:06:32.98/vblo/05,744.99,yes,locked 2006.133.08:06:32.98/vblo/06,752.99,yes,locked 2006.133.08:06:32.98/vblo/07,734.99,yes,locked 2006.133.08:06:32.98/vblo/08,744.99,yes,locked 2006.133.08:06:33.13/vabw/8 2006.133.08:06:33.28/vbbw/8 2006.133.08:06:33.37/xfe/off,on,15.2 2006.133.08:06:33.76/ifatt/23,28,28,28 2006.133.08:06:34.08/fmout-gps/S +1.90E-07 2006.133.08:06:34.12:!2006.133.08:07:30 2006.133.08:07:30.01:data_valid=off 2006.133.08:07:30.01:postob 2006.133.08:07:30.21/cable/+6.5588E-03 2006.133.08:07:30.21/wx/11.27,1009.9,100 2006.133.08:07:31.08/fmout-gps/S +1.90E-07 2006.133.08:07:31.08:scan_name=133-0808,k06133,60 2006.133.08:07:31.09:source=0552+398,055530.81,394849.2,2000.0,ccw 2006.133.08:07:31.14#flagr#flagr/antenna,new-source 2006.133.08:07:32.14:checkk5 2006.133.08:07:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:07:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:07:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:07:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:07:34.00/chk_obsdata//k5ts1/T1330806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:07:34.37/chk_obsdata//k5ts2/T1330806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:07:34.74/chk_obsdata//k5ts3/T1330806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:07:35.12/chk_obsdata//k5ts4/T1330806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:07:35.81/k5log//k5ts1_log_newline 2006.133.08:07:36.49/k5log//k5ts2_log_newline 2006.133.08:07:37.18/k5log//k5ts3_log_newline 2006.133.08:07:37.87/k5log//k5ts4_log_newline 2006.133.08:07:37.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:07:37.89:4f8m12a=2 2006.133.08:07:37.89$4f8m12a/echo=on 2006.133.08:07:37.89$4f8m12a/pcalon 2006.133.08:07:37.89$pcalon/"no phase cal control is implemented here 2006.133.08:07:37.89$4f8m12a/"tpicd=stop 2006.133.08:07:37.89$4f8m12a/vc4f8 2006.133.08:07:37.89$vc4f8/valo=1,532.99 2006.133.08:07:37.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:07:37.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:07:37.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:37.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:37.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:37.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:07:37.98#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:37.98#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:37.98#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:07:37.98#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:07:37.98$vc4f8/va=1,8 2006.133.08:07:37.98#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.08:07:37.98#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.08:07:37.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:37.98#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:37.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:37.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:38.00#ibcon#[25=AT01-08\r\n] 2006.133.08:07:38.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:38.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:38.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.08:07:38.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:38.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:38.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:38.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:38.17#ibcon#[25=USB\r\n] 2006.133.08:07:38.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:38.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:38.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:07:38.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:07:38.20$vc4f8/valo=2,572.99 2006.133.08:07:38.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.08:07:38.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.08:07:38.20#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:38.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:38.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:38.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:07:38.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:38.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:38.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:07:38.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:07:38.27$vc4f8/va=2,7 2006.133.08:07:38.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.08:07:38.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.08:07:38.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:38.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:38.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:38.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:38.34#ibcon#[25=AT02-07\r\n] 2006.133.08:07:38.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:38.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:38.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.08:07:38.37#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:38.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:38.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:38.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:38.51#ibcon#[25=USB\r\n] 2006.133.08:07:38.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:38.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:38.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:07:38.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:07:38.54$vc4f8/valo=3,672.99 2006.133.08:07:38.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:07:38.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:07:38.54#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:38.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:38.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:38.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:07:38.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:38.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:38.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:07:38.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:07:38.61$vc4f8/va=3,6 2006.133.08:07:38.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.08:07:38.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.08:07:38.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:38.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:38.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:38.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:38.68#ibcon#[25=AT03-06\r\n] 2006.133.08:07:38.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:38.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:38.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.08:07:38.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:38.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:38.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:38.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:38.85#ibcon#[25=USB\r\n] 2006.133.08:07:38.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:38.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:38.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:07:38.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:07:38.88$vc4f8/valo=4,832.99 2006.133.08:07:38.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:07:38.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:07:38.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:38.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:38.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:38.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:38.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:07:38.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:38.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:38.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:07:38.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:07:38.94$vc4f8/va=4,7 2006.133.08:07:38.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:07:38.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:07:38.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:38.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:39.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:39.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:39.02#ibcon#[25=AT04-07\r\n] 2006.133.08:07:39.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:39.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:39.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:07:39.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:39.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:39.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:39.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:39.19#ibcon#[25=USB\r\n] 2006.133.08:07:39.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:39.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:39.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:07:39.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:07:39.22$vc4f8/valo=5,652.99 2006.133.08:07:39.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:07:39.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:07:39.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:39.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:39.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:39.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:39.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:07:39.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:39.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:39.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:07:39.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:07:39.28$vc4f8/va=5,6 2006.133.08:07:39.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.08:07:39.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.08:07:39.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:39.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:39.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:39.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:39.36#ibcon#[25=AT05-06\r\n] 2006.133.08:07:39.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:39.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:39.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.08:07:39.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:39.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:39.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:39.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:39.53#ibcon#[25=USB\r\n] 2006.133.08:07:39.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:39.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:39.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:07:39.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:07:39.56$vc4f8/valo=6,772.99 2006.133.08:07:39.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.08:07:39.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.08:07:39.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:39.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:39.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:39.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:39.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:07:39.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:39.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:39.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:07:39.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:07:39.62$vc4f8/va=6,5 2006.133.08:07:39.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.08:07:39.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.08:07:39.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:39.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:39.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:39.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:39.70#ibcon#[25=AT06-05\r\n] 2006.133.08:07:39.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:39.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:39.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.08:07:39.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:39.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:07:39.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:07:39.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:07:39.87#ibcon#[25=USB\r\n] 2006.133.08:07:39.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:07:39.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:07:39.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:07:39.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:07:39.90$vc4f8/valo=7,832.99 2006.133.08:07:39.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.08:07:39.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.08:07:39.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:39.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:07:39.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:07:39.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:07:39.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:07:39.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:07:39.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:07:39.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:07:39.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:07:39.96$vc4f8/va=7,5 2006.133.08:07:39.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.08:07:39.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.08:07:39.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:39.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:07:40.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:07:40.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:07:40.04#ibcon#[25=AT07-05\r\n] 2006.133.08:07:40.07#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:07:40.07#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:07:40.07#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.08:07:40.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:40.07#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:07:40.19#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:07:40.19#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:07:40.21#ibcon#[25=USB\r\n] 2006.133.08:07:40.24#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:07:40.24#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:07:40.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:07:40.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:07:40.24$vc4f8/valo=8,852.99 2006.133.08:07:40.24#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.08:07:40.24#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.08:07:40.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:40.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:07:40.24#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:07:40.24#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:07:40.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:07:40.30#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:07:40.30#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:07:40.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:07:40.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:07:40.30$vc4f8/va=8,6 2006.133.08:07:40.30#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.08:07:40.30#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.08:07:40.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:40.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:07:40.36#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:07:40.36#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:07:40.38#ibcon#[25=AT08-06\r\n] 2006.133.08:07:40.41#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:07:40.41#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:07:40.41#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.08:07:40.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:40.41#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:07:40.53#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:07:40.53#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:07:40.55#ibcon#[25=USB\r\n] 2006.133.08:07:40.58#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:07:40.58#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:07:40.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:07:40.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:07:40.58$vc4f8/vblo=1,632.99 2006.133.08:07:40.58#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.08:07:40.58#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.08:07:40.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:40.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:07:40.58#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:07:40.58#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:07:40.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:07:40.64#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:07:40.64#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:07:40.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:07:40.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:07:40.64$vc4f8/vb=1,4 2006.133.08:07:40.64#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.08:07:40.64#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.08:07:40.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:40.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:07:40.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:07:40.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:07:40.66#ibcon#[27=AT01-04\r\n] 2006.133.08:07:40.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:07:40.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:07:40.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.08:07:40.69#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:40.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:07:40.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:07:40.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:07:40.83#ibcon#[27=USB\r\n] 2006.133.08:07:40.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:07:40.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:07:40.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:07:40.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:07:40.86$vc4f8/vblo=2,640.99 2006.133.08:07:40.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:07:40.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:07:40.86#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:40.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:40.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:40.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:40.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:07:40.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:40.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:07:40.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:07:40.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:07:40.92$vc4f8/vb=2,4 2006.133.08:07:40.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.08:07:40.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.08:07:40.92#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:40.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:40.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:40.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:41.00#ibcon#[27=AT02-04\r\n] 2006.133.08:07:41.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:41.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:07:41.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.08:07:41.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:41.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:41.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:41.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:41.17#ibcon#[27=USB\r\n] 2006.133.08:07:41.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:41.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:07:41.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:07:41.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:07:41.20$vc4f8/vblo=3,656.99 2006.133.08:07:41.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.08:07:41.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.08:07:41.20#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:41.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:41.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:41.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:07:41.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:41.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:07:41.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:07:41.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:07:41.26$vc4f8/vb=3,4 2006.133.08:07:41.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.08:07:41.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.08:07:41.26#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:41.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:41.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:41.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:41.34#ibcon#[27=AT03-04\r\n] 2006.133.08:07:41.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:41.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:07:41.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.08:07:41.37#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:41.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:41.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:41.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:41.51#ibcon#[27=USB\r\n] 2006.133.08:07:41.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:41.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:07:41.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:07:41.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:07:41.54$vc4f8/vblo=4,712.99 2006.133.08:07:41.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:07:41.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:07:41.54#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:41.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:41.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:41.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:07:41.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:41.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:07:41.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:07:41.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:07:41.60$vc4f8/vb=4,4 2006.133.08:07:41.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.08:07:41.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.08:07:41.60#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:41.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:41.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:41.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:41.68#ibcon#[27=AT04-04\r\n] 2006.133.08:07:41.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:41.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:07:41.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.08:07:41.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:41.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:41.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:41.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:41.85#ibcon#[27=USB\r\n] 2006.133.08:07:41.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:41.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:07:41.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:07:41.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:07:41.88$vc4f8/vblo=5,744.99 2006.133.08:07:41.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:07:41.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:07:41.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:41.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:41.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:41.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:07:41.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:41.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:07:41.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:07:41.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:07:41.94$vc4f8/vb=5,4 2006.133.08:07:41.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:07:41.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:07:41.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:41.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:42.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:42.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:42.02#ibcon#[27=AT05-04\r\n] 2006.133.08:07:42.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:42.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:07:42.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:07:42.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:42.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:42.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:42.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:42.19#ibcon#[27=USB\r\n] 2006.133.08:07:42.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:42.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:07:42.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:07:42.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:07:42.22$vc4f8/vblo=6,752.99 2006.133.08:07:42.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:07:42.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:07:42.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:07:42.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:42.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:42.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:42.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:07:42.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:42.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:07:42.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:07:42.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:07:42.28$vc4f8/vb=6,4 2006.133.08:07:42.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.08:07:42.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.08:07:42.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:07:42.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:42.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:42.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:42.36#ibcon#[27=AT06-04\r\n] 2006.133.08:07:42.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:42.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:07:42.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.08:07:42.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:07:42.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:42.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:42.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:42.53#ibcon#[27=USB\r\n] 2006.133.08:07:42.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:42.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:07:42.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:07:42.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:07:42.56$vc4f8/vabw=wide 2006.133.08:07:42.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.08:07:42.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.08:07:42.56#ibcon#ireg 8 cls_cnt 0 2006.133.08:07:42.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:42.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:42.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:42.58#ibcon#[25=BW32\r\n] 2006.133.08:07:42.61#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:42.61#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:07:42.61#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:07:42.61#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:07:42.61$vc4f8/vbbw=wide 2006.133.08:07:42.61#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:07:42.61#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:07:42.61#ibcon#ireg 8 cls_cnt 0 2006.133.08:07:42.61#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:07:42.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:07:42.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:07:42.70#ibcon#[27=BW32\r\n] 2006.133.08:07:42.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:07:42.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:07:42.73#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:07:42.73#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:07:42.73$4f8m12a/ifd4f 2006.133.08:07:42.73$ifd4f/lo= 2006.133.08:07:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:07:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:07:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:07:42.73$ifd4f/patch= 2006.133.08:07:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:07:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:07:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:07:42.73$4f8m12a/"form=m,16.000,1:2 2006.133.08:07:42.73$4f8m12a/"tpicd 2006.133.08:07:42.73$4f8m12a/echo=off 2006.133.08:07:42.73$4f8m12a/xlog=off 2006.133.08:07:42.73:!2006.133.08:08:10 2006.133.08:07:47.14#trakl#Source acquired 2006.133.08:07:49.14#flagr#flagr/antenna,acquired 2006.133.08:08:10.00:preob 2006.133.08:08:11.14/onsource/TRACKING 2006.133.08:08:11.14:!2006.133.08:08:20 2006.133.08:08:20.00:data_valid=on 2006.133.08:08:20.00:midob 2006.133.08:08:20.14/onsource/TRACKING 2006.133.08:08:20.14/wx/11.27,1009.9,100 2006.133.08:08:20.29/cable/+6.5600E-03 2006.133.08:08:21.38/va/01,08,usb,yes,50,53 2006.133.08:08:21.38/va/02,07,usb,yes,51,52 2006.133.08:08:21.38/va/03,06,usb,yes,53,54 2006.133.08:08:21.38/va/04,07,usb,yes,51,55 2006.133.08:08:21.38/va/05,06,usb,yes,60,63 2006.133.08:08:21.38/va/06,05,usb,yes,61,60 2006.133.08:08:21.38/va/07,05,usb,yes,61,60 2006.133.08:08:21.38/va/08,06,usb,yes,57,56 2006.133.08:08:21.61/valo/01,532.99,yes,locked 2006.133.08:08:21.61/valo/02,572.99,yes,locked 2006.133.08:08:21.61/valo/03,672.99,yes,locked 2006.133.08:08:21.61/valo/04,832.99,yes,locked 2006.133.08:08:21.61/valo/05,652.99,yes,locked 2006.133.08:08:21.61/valo/06,772.99,yes,locked 2006.133.08:08:21.61/valo/07,832.99,yes,locked 2006.133.08:08:21.61/valo/08,852.99,yes,locked 2006.133.08:08:22.70/vb/01,04,usb,yes,31,29 2006.133.08:08:22.70/vb/02,04,usb,yes,33,34 2006.133.08:08:22.70/vb/03,04,usb,yes,29,33 2006.133.08:08:22.70/vb/04,04,usb,yes,30,30 2006.133.08:08:22.70/vb/05,04,usb,yes,28,32 2006.133.08:08:22.70/vb/06,04,usb,yes,29,32 2006.133.08:08:22.70/vb/07,04,usb,yes,32,31 2006.133.08:08:22.70/vb/08,04,usb,yes,29,32 2006.133.08:08:22.94/vblo/01,632.99,yes,locked 2006.133.08:08:22.94/vblo/02,640.99,yes,locked 2006.133.08:08:22.94/vblo/03,656.99,yes,locked 2006.133.08:08:22.94/vblo/04,712.99,yes,locked 2006.133.08:08:22.94/vblo/05,744.99,yes,locked 2006.133.08:08:22.94/vblo/06,752.99,yes,locked 2006.133.08:08:22.94/vblo/07,734.99,yes,locked 2006.133.08:08:22.94/vblo/08,744.99,yes,locked 2006.133.08:08:23.09/vabw/8 2006.133.08:08:23.24/vbbw/8 2006.133.08:08:23.33/xfe/off,on,16.0 2006.133.08:08:23.71/ifatt/23,28,28,28 2006.133.08:08:24.08/fmout-gps/S +1.90E-07 2006.133.08:08:24.12:!2006.133.08:09:20 2006.133.08:09:20.01:data_valid=off 2006.133.08:09:20.01:postob 2006.133.08:09:20.13/cable/+6.5575E-03 2006.133.08:09:20.13/wx/11.26,1009.9,100 2006.133.08:09:21.08/fmout-gps/S +1.89E-07 2006.133.08:09:21.08:scan_name=133-0810,k06133,60 2006.133.08:09:21.09:source=0528+134,053056.42,133155.1,2000.0,ccw 2006.133.08:09:21.14#flagr#flagr/antenna,new-source 2006.133.08:09:22.14:checkk5 2006.133.08:09:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:09:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:09:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:09:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:09:24.00/chk_obsdata//k5ts1/T1330808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:09:24.37/chk_obsdata//k5ts2/T1330808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:09:24.74/chk_obsdata//k5ts3/T1330808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:09:25.12/chk_obsdata//k5ts4/T1330808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:09:25.80/k5log//k5ts1_log_newline 2006.133.08:09:26.48/k5log//k5ts2_log_newline 2006.133.08:09:27.17/k5log//k5ts3_log_newline 2006.133.08:09:27.86/k5log//k5ts4_log_newline 2006.133.08:09:27.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:09:27.88:4f8m12a=2 2006.133.08:09:27.88$4f8m12a/echo=on 2006.133.08:09:27.88$4f8m12a/pcalon 2006.133.08:09:27.88$pcalon/"no phase cal control is implemented here 2006.133.08:09:27.88$4f8m12a/"tpicd=stop 2006.133.08:09:27.88$4f8m12a/vc4f8 2006.133.08:09:27.88$vc4f8/valo=1,532.99 2006.133.08:09:27.89#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:09:27.89#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:09:27.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:27.89#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:27.89#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:27.89#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:09:27.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:27.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:27.98#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:09:27.98#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:09:27.98$vc4f8/va=1,8 2006.133.08:09:27.98#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:09:27.98#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:09:27.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:27.98#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:27.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:27.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:28.01#ibcon#[25=AT01-08\r\n] 2006.133.08:09:28.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:28.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:28.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:09:28.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:28.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:28.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:28.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:28.19#ibcon#[25=USB\r\n] 2006.133.08:09:28.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:28.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:28.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:09:28.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:09:28.24$vc4f8/valo=2,572.99 2006.133.08:09:28.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:09:28.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:09:28.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:28.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:28.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:28.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:09:28.29#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:28.29#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:28.29#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:09:28.29#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:09:28.29$vc4f8/va=2,7 2006.133.08:09:28.29#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.08:09:28.29#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.08:09:28.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:28.29#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:28.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:28.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:28.38#ibcon#[25=AT02-07\r\n] 2006.133.08:09:28.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:28.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:28.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.08:09:28.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:28.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:28.49#abcon#<5=/01 0.7 1.7 11.261001009.9\r\n> 2006.133.08:09:28.51#abcon#{5=INTERFACE CLEAR} 2006.133.08:09:28.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:28.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:28.55#ibcon#[25=USB\r\n] 2006.133.08:09:28.58#abcon#[5=S1D000X0/0*\r\n] 2006.133.08:09:28.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:28.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:28.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:09:28.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:09:28.58$vc4f8/valo=3,672.99 2006.133.08:09:28.58#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.08:09:28.58#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.08:09:28.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:28.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:28.58#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:28.58#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:09:28.64#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:28.64#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:28.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:09:28.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:09:28.64$vc4f8/va=3,6 2006.133.08:09:28.64#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.08:09:28.64#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.08:09:28.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:28.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:28.70#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:28.70#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:28.72#ibcon#[25=AT03-06\r\n] 2006.133.08:09:28.75#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:28.75#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:28.75#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.08:09:28.75#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:28.75#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:28.87#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:28.87#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:28.89#ibcon#[25=USB\r\n] 2006.133.08:09:28.92#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:28.92#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:28.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:09:28.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:09:28.92$vc4f8/valo=4,832.99 2006.133.08:09:28.92#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.08:09:28.92#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.08:09:28.92#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:28.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:28.92#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:28.92#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:09:28.98#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:28.98#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:28.98#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:09:28.98#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:09:28.98$vc4f8/va=4,7 2006.133.08:09:28.98#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.08:09:28.98#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.08:09:28.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:28.98#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:29.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:29.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:29.06#ibcon#[25=AT04-07\r\n] 2006.133.08:09:29.09#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:29.09#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:29.09#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.08:09:29.09#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:29.09#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:29.21#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:29.21#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:29.23#ibcon#[25=USB\r\n] 2006.133.08:09:29.26#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:29.26#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:29.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:09:29.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:09:29.26$vc4f8/valo=5,652.99 2006.133.08:09:29.26#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.08:09:29.26#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.08:09:29.26#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:29.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:29.26#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:29.26#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:09:29.32#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:29.32#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:29.32#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:09:29.32#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:09:29.32$vc4f8/va=5,6 2006.133.08:09:29.32#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.08:09:29.32#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.08:09:29.32#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:29.32#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:29.38#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:29.38#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:29.40#ibcon#[25=AT05-06\r\n] 2006.133.08:09:29.43#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:29.43#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:29.43#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.08:09:29.43#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:29.43#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:29.55#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:29.55#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:29.57#ibcon#[25=USB\r\n] 2006.133.08:09:29.62#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:29.62#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:29.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:09:29.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:09:29.62$vc4f8/valo=6,772.99 2006.133.08:09:29.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:09:29.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:09:29.62#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:29.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:29.62#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:29.62#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:29.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:09:29.67#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:29.67#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:29.67#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:09:29.67#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:09:29.67$vc4f8/va=6,5 2006.133.08:09:29.67#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.08:09:29.67#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.08:09:29.67#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:29.67#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:29.74#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:29.74#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:29.76#ibcon#[25=AT06-05\r\n] 2006.133.08:09:29.79#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:29.79#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:29.79#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.08:09:29.79#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:29.79#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:09:29.91#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:09:29.91#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:09:29.93#ibcon#[25=USB\r\n] 2006.133.08:09:29.96#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:09:29.96#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:09:29.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:09:29.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:09:29.96$vc4f8/valo=7,832.99 2006.133.08:09:29.96#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.08:09:29.96#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.08:09:29.96#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:29.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:09:29.96#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:09:29.96#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:09:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:09:30.02#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:09:30.02#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:09:30.02#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:09:30.02#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:09:30.02$vc4f8/va=7,5 2006.133.08:09:30.02#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.08:09:30.02#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.08:09:30.02#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:30.02#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:09:30.08#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:09:30.08#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:09:30.10#ibcon#[25=AT07-05\r\n] 2006.133.08:09:30.13#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:09:30.13#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:09:30.13#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.08:09:30.13#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:30.13#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:09:30.25#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:09:30.25#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:09:30.27#ibcon#[25=USB\r\n] 2006.133.08:09:30.30#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:09:30.30#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:09:30.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:09:30.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:09:30.30$vc4f8/valo=8,852.99 2006.133.08:09:30.30#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:09:30.30#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:09:30.30#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:30.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:09:30.30#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:09:30.30#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:09:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:09:30.36#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:09:30.36#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:09:30.36#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:09:30.36#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:09:30.36$vc4f8/va=8,6 2006.133.08:09:30.36#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.08:09:30.36#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.08:09:30.36#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:30.36#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:09:30.42#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:09:30.42#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:09:30.44#ibcon#[25=AT08-06\r\n] 2006.133.08:09:30.47#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:09:30.47#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:09:30.47#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.08:09:30.47#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:30.47#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:09:30.59#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:09:30.59#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:09:30.61#ibcon#[25=USB\r\n] 2006.133.08:09:30.64#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:09:30.64#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:09:30.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:09:30.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:09:30.64$vc4f8/vblo=1,632.99 2006.133.08:09:30.64#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:09:30.64#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:09:30.64#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:30.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:30.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:30.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:09:30.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:30.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:09:30.70#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:09:30.70#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:09:30.70$vc4f8/vb=1,4 2006.133.08:09:30.70#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:09:30.70#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:09:30.70#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:30.70#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:30.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:30.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:30.72#ibcon#[27=AT01-04\r\n] 2006.133.08:09:30.75#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:30.75#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:09:30.75#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:09:30.75#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:30.75#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:30.87#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:30.87#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:30.89#ibcon#[27=USB\r\n] 2006.133.08:09:30.92#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:30.92#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:09:30.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:09:30.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:09:30.92$vc4f8/vblo=2,640.99 2006.133.08:09:30.92#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:09:30.92#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:09:30.92#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:30.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:30.92#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:30.92#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:09:30.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:30.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:09:30.98#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:09:30.98#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:09:30.98$vc4f8/vb=2,4 2006.133.08:09:30.98#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.08:09:30.98#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.08:09:30.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:30.98#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:31.04#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:31.04#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:31.06#ibcon#[27=AT02-04\r\n] 2006.133.08:09:31.09#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:31.09#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:09:31.09#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.08:09:31.09#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:31.09#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:31.21#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:31.21#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:31.23#ibcon#[27=USB\r\n] 2006.133.08:09:31.28#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:31.28#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:09:31.28#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:09:31.28#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:09:31.28$vc4f8/vblo=3,656.99 2006.133.08:09:31.28#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.08:09:31.28#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.08:09:31.28#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:31.28#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:09:31.28#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:09:31.28#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:09:31.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:09:31.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:09:31.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:09:31.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:09:31.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:09:31.33$vc4f8/vb=3,4 2006.133.08:09:31.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.08:09:31.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.08:09:31.33#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:31.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:09:31.40#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:09:31.40#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:09:31.42#ibcon#[27=AT03-04\r\n] 2006.133.08:09:31.45#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:09:31.45#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:09:31.45#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.08:09:31.45#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:31.45#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:09:31.57#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:09:31.57#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:09:31.59#ibcon#[27=USB\r\n] 2006.133.08:09:31.62#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:09:31.62#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:09:31.62#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:09:31.62#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:09:31.62$vc4f8/vblo=4,712.99 2006.133.08:09:31.62#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.08:09:31.62#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.08:09:31.62#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:31.62#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:31.62#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:31.62#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:31.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:09:31.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:31.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:09:31.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:09:31.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:09:31.68$vc4f8/vb=4,4 2006.133.08:09:31.68#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.08:09:31.68#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.08:09:31.68#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:31.68#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:31.74#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:31.74#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:31.76#ibcon#[27=AT04-04\r\n] 2006.133.08:09:31.79#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:31.79#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:09:31.79#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.08:09:31.79#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:31.79#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:31.91#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:31.91#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:31.93#ibcon#[27=USB\r\n] 2006.133.08:09:31.96#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:31.96#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:09:31.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:09:31.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:09:31.96$vc4f8/vblo=5,744.99 2006.133.08:09:31.96#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.08:09:31.96#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.08:09:31.96#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:31.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:31.96#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:31.96#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:31.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:09:32.02#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:32.02#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:09:32.02#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:09:32.02#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:09:32.02$vc4f8/vb=5,4 2006.133.08:09:32.02#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.08:09:32.02#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.08:09:32.02#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:32.02#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:32.08#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:32.08#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:32.10#ibcon#[27=AT05-04\r\n] 2006.133.08:09:32.13#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:32.13#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:09:32.13#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.08:09:32.13#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:32.13#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:32.25#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:32.25#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:32.27#ibcon#[27=USB\r\n] 2006.133.08:09:32.30#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:32.30#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:09:32.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:09:32.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:09:32.30$vc4f8/vblo=6,752.99 2006.133.08:09:32.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.08:09:32.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.08:09:32.30#ibcon#ireg 17 cls_cnt 0 2006.133.08:09:32.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:32.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:32.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:32.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:09:32.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:32.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:09:32.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:09:32.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:09:32.36$vc4f8/vb=6,4 2006.133.08:09:32.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.08:09:32.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.08:09:32.36#ibcon#ireg 11 cls_cnt 2 2006.133.08:09:32.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:32.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:32.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:32.44#ibcon#[27=AT06-04\r\n] 2006.133.08:09:32.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:32.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:09:32.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.08:09:32.47#ibcon#ireg 7 cls_cnt 0 2006.133.08:09:32.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:32.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:32.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:32.61#ibcon#[27=USB\r\n] 2006.133.08:09:32.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:32.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:09:32.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:09:32.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:09:32.64$vc4f8/vabw=wide 2006.133.08:09:32.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:09:32.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:09:32.64#ibcon#ireg 8 cls_cnt 0 2006.133.08:09:32.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:32.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:32.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:32.66#ibcon#[25=BW32\r\n] 2006.133.08:09:32.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:32.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:09:32.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:09:32.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:09:32.69$vc4f8/vbbw=wide 2006.133.08:09:32.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:09:32.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:09:32.69#ibcon#ireg 8 cls_cnt 0 2006.133.08:09:32.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:09:32.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:09:32.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:09:32.78#ibcon#[27=BW32\r\n] 2006.133.08:09:32.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:09:32.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:09:32.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:09:32.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:09:32.81$4f8m12a/ifd4f 2006.133.08:09:32.81$ifd4f/lo= 2006.133.08:09:32.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:09:32.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:09:32.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:09:32.81$ifd4f/patch= 2006.133.08:09:32.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:09:32.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:09:32.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:09:32.81$4f8m12a/"form=m,16.000,1:2 2006.133.08:09:32.81$4f8m12a/"tpicd 2006.133.08:09:32.81$4f8m12a/echo=off 2006.133.08:09:32.81$4f8m12a/xlog=off 2006.133.08:09:32.81:!2006.133.08:10:00 2006.133.08:09:43.14#trakl#Source acquired 2006.133.08:09:45.14#flagr#flagr/antenna,acquired 2006.133.08:10:00.00:preob 2006.133.08:10:01.14/onsource/TRACKING 2006.133.08:10:01.14:!2006.133.08:10:10 2006.133.08:10:10.00:data_valid=on 2006.133.08:10:10.00:midob 2006.133.08:10:10.14/onsource/TRACKING 2006.133.08:10:10.14/wx/11.26,1009.8,100 2006.133.08:10:10.33/cable/+6.5578E-03 2006.133.08:10:11.42/va/01,08,usb,yes,48,51 2006.133.08:10:11.42/va/02,07,usb,yes,49,51 2006.133.08:10:11.42/va/03,06,usb,yes,52,52 2006.133.08:10:11.42/va/04,07,usb,yes,50,54 2006.133.08:10:11.42/va/05,06,usb,yes,57,61 2006.133.08:10:11.42/va/06,05,usb,yes,59,58 2006.133.08:10:11.42/va/07,05,usb,yes,58,58 2006.133.08:10:11.42/va/08,06,usb,yes,55,54 2006.133.08:10:11.65/valo/01,532.99,yes,locked 2006.133.08:10:11.65/valo/02,572.99,yes,locked 2006.133.08:10:11.65/valo/03,672.99,yes,locked 2006.133.08:10:11.65/valo/04,832.99,yes,locked 2006.133.08:10:11.65/valo/05,652.99,yes,locked 2006.133.08:10:11.65/valo/06,772.99,yes,locked 2006.133.08:10:11.65/valo/07,832.99,yes,locked 2006.133.08:10:11.65/valo/08,852.99,yes,locked 2006.133.08:10:12.74/vb/01,04,usb,yes,31,29 2006.133.08:10:12.74/vb/02,04,usb,yes,32,34 2006.133.08:10:12.74/vb/03,04,usb,yes,29,32 2006.133.08:10:12.74/vb/04,04,usb,yes,30,30 2006.133.08:10:12.74/vb/05,04,usb,yes,28,32 2006.133.08:10:12.74/vb/06,04,usb,yes,29,32 2006.133.08:10:12.74/vb/07,04,usb,yes,31,31 2006.133.08:10:12.74/vb/08,04,usb,yes,29,32 2006.133.08:10:12.97/vblo/01,632.99,yes,locked 2006.133.08:10:12.97/vblo/02,640.99,yes,locked 2006.133.08:10:12.97/vblo/03,656.99,yes,locked 2006.133.08:10:12.97/vblo/04,712.99,yes,locked 2006.133.08:10:12.97/vblo/05,744.99,yes,locked 2006.133.08:10:12.97/vblo/06,752.99,yes,locked 2006.133.08:10:12.97/vblo/07,734.99,yes,locked 2006.133.08:10:12.97/vblo/08,744.99,yes,locked 2006.133.08:10:13.12/vabw/8 2006.133.08:10:13.27/vbbw/8 2006.133.08:10:13.38/xfe/off,on,15.2 2006.133.08:10:13.75/ifatt/23,28,28,28 2006.133.08:10:14.08/fmout-gps/S +1.90E-07 2006.133.08:10:14.12:!2006.133.08:11:10 2006.133.08:11:10.00:data_valid=off 2006.133.08:11:10.00:postob 2006.133.08:11:10.09/cable/+6.5604E-03 2006.133.08:11:10.09/wx/11.26,1009.8,100 2006.133.08:11:11.08/fmout-gps/S +1.88E-07 2006.133.08:11:11.08:scan_name=133-0812,k06133,60 2006.133.08:11:11.09:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.133.08:11:11.14#flagr#flagr/antenna,new-source 2006.133.08:11:12.14:checkk5 2006.133.08:11:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:11:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:11:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:11:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:11:14.00/chk_obsdata//k5ts1/T1330810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:11:14.37/chk_obsdata//k5ts2/T1330810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:11:14.74/chk_obsdata//k5ts3/T1330810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:11:15.11/chk_obsdata//k5ts4/T1330810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:11:15.79/k5log//k5ts1_log_newline 2006.133.08:11:16.47/k5log//k5ts2_log_newline 2006.133.08:11:17.16/k5log//k5ts3_log_newline 2006.133.08:11:17.85/k5log//k5ts4_log_newline 2006.133.08:11:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:11:17.87:4f8m12a=2 2006.133.08:11:17.87$4f8m12a/echo=on 2006.133.08:11:17.87$4f8m12a/pcalon 2006.133.08:11:17.87$pcalon/"no phase cal control is implemented here 2006.133.08:11:17.88$4f8m12a/"tpicd=stop 2006.133.08:11:17.88$4f8m12a/vc4f8 2006.133.08:11:17.88$vc4f8/valo=1,532.99 2006.133.08:11:17.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:11:17.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:11:17.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:17.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:17.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:17.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:11:17.97#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:17.97#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:17.97#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:11:17.97#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:11:17.97$vc4f8/va=1,8 2006.133.08:11:17.97#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:11:17.97#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:11:17.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:17.97#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:17.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:17.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:18.00#ibcon#[25=AT01-08\r\n] 2006.133.08:11:18.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:18.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:18.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:11:18.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:18.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:18.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:18.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:18.17#ibcon#[25=USB\r\n] 2006.133.08:11:18.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:18.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:18.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:11:18.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:11:18.22$vc4f8/valo=2,572.99 2006.133.08:11:18.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:11:18.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:11:18.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:18.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:18.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:18.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:11:18.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:18.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:18.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:11:18.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:11:18.27$vc4f8/va=2,7 2006.133.08:11:18.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:11:18.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:11:18.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:18.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:18.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:18.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:18.36#ibcon#[25=AT02-07\r\n] 2006.133.08:11:18.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:18.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:18.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:11:18.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:18.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:18.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:18.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:18.53#ibcon#[25=USB\r\n] 2006.133.08:11:18.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:18.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:18.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:11:18.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:11:18.56$vc4f8/valo=3,672.99 2006.133.08:11:18.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:11:18.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:11:18.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:18.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:18.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:18.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:11:18.63#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:18.63#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:18.63#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:11:18.63#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:11:18.63$vc4f8/va=3,6 2006.133.08:11:18.63#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:11:18.63#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:11:18.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:18.63#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:18.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:18.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:18.70#ibcon#[25=AT03-06\r\n] 2006.133.08:11:18.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:18.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:18.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:11:18.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:18.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:18.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:18.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:18.87#ibcon#[25=USB\r\n] 2006.133.08:11:18.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:18.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:18.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:11:18.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:11:18.90$vc4f8/valo=4,832.99 2006.133.08:11:18.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:11:18.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:11:18.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:18.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:18.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:18.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:11:18.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:18.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:18.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:11:18.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:11:18.96$vc4f8/va=4,7 2006.133.08:11:18.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:11:18.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:11:18.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:18.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:19.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:19.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:19.04#ibcon#[25=AT04-07\r\n] 2006.133.08:11:19.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:19.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:19.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:11:19.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:19.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:19.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:19.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:19.21#ibcon#[25=USB\r\n] 2006.133.08:11:19.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:19.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:19.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:11:19.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:11:19.24$vc4f8/valo=5,652.99 2006.133.08:11:19.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:11:19.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:11:19.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:19.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:19.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:19.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:11:19.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:19.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:19.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:11:19.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:11:19.30$vc4f8/va=5,6 2006.133.08:11:19.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:11:19.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:11:19.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:19.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:19.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:19.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:19.38#ibcon#[25=AT05-06\r\n] 2006.133.08:11:19.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:19.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:19.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:11:19.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:19.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:19.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:19.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:19.55#ibcon#[25=USB\r\n] 2006.133.08:11:19.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:19.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:19.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:11:19.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:11:19.58$vc4f8/valo=6,772.99 2006.133.08:11:19.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:11:19.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:11:19.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:19.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:19.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:19.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:11:19.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:19.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:19.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:11:19.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:11:19.64$vc4f8/va=6,5 2006.133.08:11:19.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:11:19.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:11:19.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:19.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:19.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:19.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:19.72#ibcon#[25=AT06-05\r\n] 2006.133.08:11:19.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:19.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:19.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:11:19.75#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:19.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:19.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:19.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:19.89#ibcon#[25=USB\r\n] 2006.133.08:11:19.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:19.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:19.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:11:19.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:11:19.92$vc4f8/valo=7,832.99 2006.133.08:11:19.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:11:19.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:11:19.92#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:19.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:19.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:19.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:11:19.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:19.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:19.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:11:19.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:11:19.98$vc4f8/va=7,5 2006.133.08:11:19.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:11:19.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:11:19.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:19.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:20.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:20.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:20.06#ibcon#[25=AT07-05\r\n] 2006.133.08:11:20.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:20.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:20.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:11:20.09#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:20.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:11:20.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:11:20.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:11:20.23#ibcon#[25=USB\r\n] 2006.133.08:11:20.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:11:20.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:11:20.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:11:20.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:11:20.26$vc4f8/valo=8,852.99 2006.133.08:11:20.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:11:20.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:11:20.26#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:20.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:11:20.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:11:20.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:11:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:11:20.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:11:20.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:11:20.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:11:20.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:11:20.32$vc4f8/va=8,6 2006.133.08:11:20.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:11:20.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:11:20.32#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:20.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:11:20.37#abcon#<5=/02 0.6 1.7 11.261001009.8\r\n> 2006.133.08:11:20.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:11:20.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:11:20.39#abcon#{5=INTERFACE CLEAR} 2006.133.08:11:20.40#ibcon#[25=AT08-06\r\n] 2006.133.08:11:20.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:11:20.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:11:20.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:11:20.43#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:20.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:11:20.45#abcon#[5=S1D000X0/0*\r\n] 2006.133.08:11:20.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:11:20.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:11:20.57#ibcon#[25=USB\r\n] 2006.133.08:11:20.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:11:20.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:11:20.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:11:20.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:11:20.60$vc4f8/vblo=1,632.99 2006.133.08:11:20.60#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:11:20.60#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:11:20.60#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:20.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:20.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:20.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:11:20.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:20.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:11:20.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:11:20.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:11:20.66$vc4f8/vb=1,4 2006.133.08:11:20.66#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:11:20.66#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:11:20.66#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:20.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:20.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:20.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:20.68#ibcon#[27=AT01-04\r\n] 2006.133.08:11:20.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:20.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:11:20.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:11:20.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:20.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:20.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:20.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:20.85#ibcon#[27=USB\r\n] 2006.133.08:11:20.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:20.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:11:20.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:11:20.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:11:20.88$vc4f8/vblo=2,640.99 2006.133.08:11:20.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:11:20.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:11:20.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:20.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:20.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:20.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:20.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:11:20.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:20.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:11:20.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:11:20.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:11:20.95$vc4f8/vb=2,4 2006.133.08:11:20.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:11:20.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:11:20.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:20.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:21.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:21.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:21.02#ibcon#[27=AT02-04\r\n] 2006.133.08:11:21.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:21.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:11:21.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:11:21.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:21.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:21.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:21.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:21.19#ibcon#[27=USB\r\n] 2006.133.08:11:21.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:21.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:11:21.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:11:21.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:11:21.22$vc4f8/vblo=3,656.99 2006.133.08:11:21.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:11:21.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:11:21.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:21.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:21.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:21.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:11:21.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:21.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:11:21.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:11:21.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:11:21.28$vc4f8/vb=3,4 2006.133.08:11:21.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:11:21.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:11:21.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:21.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:21.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:21.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:21.36#ibcon#[27=AT03-04\r\n] 2006.133.08:11:21.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:21.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:11:21.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:11:21.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:21.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:21.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:21.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:21.53#ibcon#[27=USB\r\n] 2006.133.08:11:21.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:21.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:11:21.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:11:21.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:11:21.56$vc4f8/vblo=4,712.99 2006.133.08:11:21.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:11:21.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:11:21.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:21.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:21.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:21.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:11:21.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:21.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:11:21.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:11:21.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:11:21.62$vc4f8/vb=4,4 2006.133.08:11:21.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:11:21.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:11:21.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:21.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:21.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:21.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:21.70#ibcon#[27=AT04-04\r\n] 2006.133.08:11:21.73#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:21.73#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:11:21.73#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:11:21.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:21.73#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:21.85#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:21.85#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:21.87#ibcon#[27=USB\r\n] 2006.133.08:11:21.90#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:21.90#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:11:21.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:11:21.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:11:21.90$vc4f8/vblo=5,744.99 2006.133.08:11:21.90#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:11:21.90#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:11:21.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:21.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:21.90#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:21.90#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:21.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:11:21.96#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:21.96#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:11:21.96#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:11:21.96#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:11:21.96$vc4f8/vb=5,4 2006.133.08:11:21.96#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:11:21.96#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:11:21.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:21.96#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:22.02#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:22.02#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:22.04#ibcon#[27=AT05-04\r\n] 2006.133.08:11:22.07#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:22.07#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:11:22.07#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:11:22.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:22.07#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:22.19#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:22.19#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:22.21#ibcon#[27=USB\r\n] 2006.133.08:11:22.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:22.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:11:22.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:11:22.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:11:22.24$vc4f8/vblo=6,752.99 2006.133.08:11:22.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:11:22.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:11:22.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:11:22.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:22.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:22.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:11:22.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:22.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:11:22.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:11:22.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:11:22.30$vc4f8/vb=6,4 2006.133.08:11:22.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:11:22.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:11:22.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:11:22.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:22.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:22.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:22.38#ibcon#[27=AT06-04\r\n] 2006.133.08:11:22.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:22.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:11:22.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:11:22.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:11:22.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:22.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:22.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:22.55#ibcon#[27=USB\r\n] 2006.133.08:11:22.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:22.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:11:22.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:11:22.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:11:22.58$vc4f8/vabw=wide 2006.133.08:11:22.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:11:22.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:11:22.58#ibcon#ireg 8 cls_cnt 0 2006.133.08:11:22.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:22.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:22.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:22.60#ibcon#[25=BW32\r\n] 2006.133.08:11:22.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:22.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:11:22.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:11:22.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:11:22.63$vc4f8/vbbw=wide 2006.133.08:11:22.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:11:22.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:11:22.63#ibcon#ireg 8 cls_cnt 0 2006.133.08:11:22.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:11:22.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:11:22.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:11:22.72#ibcon#[27=BW32\r\n] 2006.133.08:11:22.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:11:22.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:11:22.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:11:22.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:11:22.75$4f8m12a/ifd4f 2006.133.08:11:22.75$ifd4f/lo= 2006.133.08:11:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:11:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:11:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:11:22.75$ifd4f/patch= 2006.133.08:11:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:11:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:11:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:11:22.75$4f8m12a/"form=m,16.000,1:2 2006.133.08:11:22.75$4f8m12a/"tpicd 2006.133.08:11:22.75$4f8m12a/echo=off 2006.133.08:11:22.75$4f8m12a/xlog=off 2006.133.08:11:22.75:!2006.133.08:12:10 2006.133.08:11:47.14#trakl#Source acquired 2006.133.08:11:47.14#flagr#flagr/antenna,acquired 2006.133.08:12:10.00:preob 2006.133.08:12:10.14/onsource/TRACKING 2006.133.08:12:10.14:!2006.133.08:12:20 2006.133.08:12:20.00:data_valid=on 2006.133.08:12:20.00:midob 2006.133.08:12:20.14/onsource/TRACKING 2006.133.08:12:20.14/wx/11.27,1009.8,100 2006.133.08:12:20.29/cable/+6.5592E-03 2006.133.08:12:21.38/va/01,08,usb,yes,48,50 2006.133.08:12:21.38/va/02,07,usb,yes,48,50 2006.133.08:12:21.38/va/03,06,usb,yes,51,51 2006.133.08:12:21.38/va/04,07,usb,yes,49,53 2006.133.08:12:21.38/va/05,06,usb,yes,57,60 2006.133.08:12:21.38/va/06,05,usb,yes,58,58 2006.133.08:12:21.38/va/07,05,usb,yes,58,58 2006.133.08:12:21.38/va/08,06,usb,yes,54,53 2006.133.08:12:21.61/valo/01,532.99,yes,locked 2006.133.08:12:21.61/valo/02,572.99,yes,locked 2006.133.08:12:21.61/valo/03,672.99,yes,locked 2006.133.08:12:21.61/valo/04,832.99,yes,locked 2006.133.08:12:21.61/valo/05,652.99,yes,locked 2006.133.08:12:21.61/valo/06,772.99,yes,locked 2006.133.08:12:21.61/valo/07,832.99,yes,locked 2006.133.08:12:21.61/valo/08,852.99,yes,locked 2006.133.08:12:22.70/vb/01,04,usb,yes,30,29 2006.133.08:12:22.70/vb/02,04,usb,yes,32,34 2006.133.08:12:22.70/vb/03,04,usb,yes,29,32 2006.133.08:12:22.70/vb/04,04,usb,yes,30,30 2006.133.08:12:22.70/vb/05,04,usb,yes,28,32 2006.133.08:12:22.70/vb/06,04,usb,yes,29,32 2006.133.08:12:22.70/vb/07,04,usb,yes,31,31 2006.133.08:12:22.70/vb/08,04,usb,yes,29,32 2006.133.08:12:22.94/vblo/01,632.99,yes,locked 2006.133.08:12:22.94/vblo/02,640.99,yes,locked 2006.133.08:12:22.94/vblo/03,656.99,yes,locked 2006.133.08:12:22.94/vblo/04,712.99,yes,locked 2006.133.08:12:22.94/vblo/05,744.99,yes,locked 2006.133.08:12:22.94/vblo/06,752.99,yes,locked 2006.133.08:12:22.94/vblo/07,734.99,yes,locked 2006.133.08:12:22.94/vblo/08,744.99,yes,locked 2006.133.08:12:23.09/vabw/8 2006.133.08:12:23.24/vbbw/8 2006.133.08:12:23.33/xfe/off,on,15.2 2006.133.08:12:23.71/ifatt/23,28,28,28 2006.133.08:12:24.08/fmout-gps/S +1.87E-07 2006.133.08:12:24.12:!2006.133.08:13:20 2006.133.08:13:20.00:data_valid=off 2006.133.08:13:20.00:postob 2006.133.08:13:20.20/cable/+6.5589E-03 2006.133.08:13:20.20/wx/11.27,1009.7,100 2006.133.08:13:21.08/fmout-gps/S +1.88E-07 2006.133.08:13:21.08:scan_name=133-0814,k06133,60 2006.133.08:13:21.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.133.08:13:21.13#flagr#flagr/antenna,new-source 2006.133.08:13:22.13:checkk5 2006.133.08:13:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:13:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:13:23.24/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:13:23.61/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:13:23.97/chk_obsdata//k5ts1/T1330812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:13:24.34/chk_obsdata//k5ts2/T1330812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:13:24.70/chk_obsdata//k5ts3/T1330812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:13:25.07/chk_obsdata//k5ts4/T1330812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:13:25.76/k5log//k5ts1_log_newline 2006.133.08:13:26.44/k5log//k5ts2_log_newline 2006.133.08:13:27.14/k5log//k5ts3_log_newline 2006.133.08:13:27.82/k5log//k5ts4_log_newline 2006.133.08:13:27.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:13:27.84:4f8m12a=2 2006.133.08:13:27.84$4f8m12a/echo=on 2006.133.08:13:27.84$4f8m12a/pcalon 2006.133.08:13:27.84$pcalon/"no phase cal control is implemented here 2006.133.08:13:27.84$4f8m12a/"tpicd=stop 2006.133.08:13:27.85$4f8m12a/vc4f8 2006.133.08:13:27.85$vc4f8/valo=1,532.99 2006.133.08:13:27.85#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.08:13:27.85#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.08:13:27.85#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:27.85#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:27.85#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:27.85#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:27.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:13:27.94#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:27.94#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:27.94#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:13:27.94#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:13:27.94$vc4f8/va=1,8 2006.133.08:13:27.94#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.08:13:27.94#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.08:13:27.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:27.94#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:27.94#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:27.94#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:27.97#ibcon#[25=AT01-08\r\n] 2006.133.08:13:28.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:28.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:28.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.08:13:28.00#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:28.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:28.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:28.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:28.14#ibcon#[25=USB\r\n] 2006.133.08:13:28.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:28.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:28.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:13:28.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:13:28.19$vc4f8/valo=2,572.99 2006.133.08:13:28.19#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.08:13:28.19#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.08:13:28.19#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:28.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:28.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:28.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:13:28.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:28.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:28.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:13:28.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:13:28.24$vc4f8/va=2,7 2006.133.08:13:28.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.08:13:28.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.08:13:28.24#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:28.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:28.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:28.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:28.32#ibcon#[25=AT02-07\r\n] 2006.133.08:13:28.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:28.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:28.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.08:13:28.35#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:28.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:28.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:28.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:28.49#ibcon#[25=USB\r\n] 2006.133.08:13:28.53#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:28.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:28.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:13:28.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:13:28.54$vc4f8/valo=3,672.99 2006.133.08:13:28.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.08:13:28.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.08:13:28.54#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:28.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:28.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:28.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:28.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:13:28.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:28.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:28.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:13:28.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:13:28.59$vc4f8/va=3,6 2006.133.08:13:28.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.08:13:28.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.08:13:28.59#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:28.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:28.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:28.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:28.68#ibcon#[25=AT03-06\r\n] 2006.133.08:13:28.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:28.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:28.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.08:13:28.71#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:28.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:28.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:28.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:28.85#ibcon#[25=USB\r\n] 2006.133.08:13:28.88#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:28.88#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:28.88#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:13:28.88#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:13:28.88$vc4f8/valo=4,832.99 2006.133.08:13:28.88#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:13:28.88#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:13:28.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:28.88#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:28.88#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:28.88#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:28.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:13:28.94#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:28.94#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:28.94#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:13:28.94#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:13:28.94$vc4f8/va=4,7 2006.133.08:13:28.94#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:13:28.94#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:13:28.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:28.94#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:29.00#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:29.00#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:29.02#ibcon#[25=AT04-07\r\n] 2006.133.08:13:29.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:29.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:29.05#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:13:29.05#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:29.05#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:29.17#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:29.17#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:29.19#ibcon#[25=USB\r\n] 2006.133.08:13:29.22#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:29.22#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:29.22#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:13:29.22#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:13:29.22$vc4f8/valo=5,652.99 2006.133.08:13:29.22#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:13:29.22#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:13:29.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:29.22#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:29.22#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:29.22#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:29.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:13:29.28#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:29.28#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:29.28#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:13:29.28#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:13:29.28$vc4f8/va=5,6 2006.133.08:13:29.28#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:13:29.28#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:13:29.28#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:29.28#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:29.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:29.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:29.36#ibcon#[25=AT05-06\r\n] 2006.133.08:13:29.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:29.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:29.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:13:29.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:29.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:29.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:29.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:29.53#ibcon#[25=USB\r\n] 2006.133.08:13:29.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:29.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:29.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:13:29.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:13:29.56$vc4f8/valo=6,772.99 2006.133.08:13:29.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:13:29.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:13:29.56#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:29.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:29.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:29.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:13:29.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:29.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:29.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:13:29.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:13:29.64$vc4f8/va=6,5 2006.133.08:13:29.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.08:13:29.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.08:13:29.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:29.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:29.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:29.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:29.70#ibcon#[25=AT06-05\r\n] 2006.133.08:13:29.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:29.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:29.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.08:13:29.73#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:29.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:13:29.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:13:29.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:13:29.87#ibcon#[25=USB\r\n] 2006.133.08:13:29.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:13:29.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:13:29.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:13:29.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:13:29.90$vc4f8/valo=7,832.99 2006.133.08:13:29.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:13:29.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:13:29.90#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:29.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:13:29.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:13:29.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:13:29.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:13:29.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:13:29.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:13:29.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:13:29.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:13:29.96$vc4f8/va=7,5 2006.133.08:13:29.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.08:13:29.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.08:13:29.96#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:29.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:13:30.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:13:30.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:13:30.04#ibcon#[25=AT07-05\r\n] 2006.133.08:13:30.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:13:30.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:13:30.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.08:13:30.07#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:30.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:13:30.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:13:30.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:13:30.21#ibcon#[25=USB\r\n] 2006.133.08:13:30.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:13:30.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:13:30.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:13:30.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:13:30.24$vc4f8/valo=8,852.99 2006.133.08:13:30.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.08:13:30.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.08:13:30.24#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:30.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:13:30.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:13:30.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:13:30.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:13:30.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:13:30.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:13:30.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:13:30.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:13:30.30$vc4f8/va=8,6 2006.133.08:13:30.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.08:13:30.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.08:13:30.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:30.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:13:30.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:13:30.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:13:30.38#ibcon#[25=AT08-06\r\n] 2006.133.08:13:30.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:13:30.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:13:30.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.08:13:30.41#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:30.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:13:30.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:13:30.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:13:30.55#ibcon#[25=USB\r\n] 2006.133.08:13:30.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:13:30.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:13:30.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:13:30.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:13:30.58$vc4f8/vblo=1,632.99 2006.133.08:13:30.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.08:13:30.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.08:13:30.58#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:30.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:13:30.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:13:30.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:13:30.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:13:30.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:13:30.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:13:30.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:13:30.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:13:30.64$vc4f8/vb=1,4 2006.133.08:13:30.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.08:13:30.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.08:13:30.64#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:30.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:13:30.64#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:13:30.64#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:13:30.66#ibcon#[27=AT01-04\r\n] 2006.133.08:13:30.69#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:13:30.69#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:13:30.69#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.08:13:30.69#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:30.69#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:13:30.81#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:13:30.81#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:13:30.83#ibcon#[27=USB\r\n] 2006.133.08:13:30.86#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:13:30.86#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:13:30.86#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:13:30.86#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:13:30.86$vc4f8/vblo=2,640.99 2006.133.08:13:30.86#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.08:13:30.86#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.08:13:30.86#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:30.86#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:30.86#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:30.86#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:30.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:13:30.92#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:30.92#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:13:30.92#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:13:30.92#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:13:30.92$vc4f8/vb=2,4 2006.133.08:13:30.92#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.08:13:30.92#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.08:13:30.92#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:30.92#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:30.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:30.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:31.00#ibcon#[27=AT02-04\r\n] 2006.133.08:13:31.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:31.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:13:31.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.08:13:31.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:31.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:31.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:31.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:31.17#ibcon#[27=USB\r\n] 2006.133.08:13:31.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:31.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:13:31.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:13:31.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:13:31.21$vc4f8/vblo=3,656.99 2006.133.08:13:31.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.08:13:31.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.08:13:31.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:31.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:31.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:31.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:31.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:13:31.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:31.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:13:31.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:13:31.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:13:31.26$vc4f8/vb=3,4 2006.133.08:13:31.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.08:13:31.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.08:13:31.26#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:31.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:31.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:31.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:31.35#ibcon#[27=AT03-04\r\n] 2006.133.08:13:31.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:31.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:13:31.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.08:13:31.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:31.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:31.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:31.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:31.52#ibcon#[27=USB\r\n] 2006.133.08:13:31.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:31.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:13:31.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:13:31.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:13:31.55$vc4f8/vblo=4,712.99 2006.133.08:13:31.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.08:13:31.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.08:13:31.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:31.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:31.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:31.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:31.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:13:31.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:31.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:13:31.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:13:31.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:13:31.61$vc4f8/vb=4,4 2006.133.08:13:31.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.08:13:31.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.08:13:31.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:31.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:31.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:31.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:31.69#ibcon#[27=AT04-04\r\n] 2006.133.08:13:31.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:31.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:13:31.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.08:13:31.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:31.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:31.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:31.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:31.86#ibcon#[27=USB\r\n] 2006.133.08:13:31.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:31.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:13:31.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:13:31.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:13:31.89$vc4f8/vblo=5,744.99 2006.133.08:13:31.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:13:31.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:13:31.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:31.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:31.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:31.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:31.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:13:31.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:31.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:13:31.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:13:31.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:13:31.95$vc4f8/vb=5,4 2006.133.08:13:31.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:13:31.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:13:31.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:31.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:32.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:32.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:32.03#ibcon#[27=AT05-04\r\n] 2006.133.08:13:32.06#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:32.06#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:13:32.06#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:13:32.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:32.06#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:32.18#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:32.18#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:32.20#ibcon#[27=USB\r\n] 2006.133.08:13:32.23#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:32.23#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:13:32.23#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:13:32.23#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:13:32.23$vc4f8/vblo=6,752.99 2006.133.08:13:32.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:13:32.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:13:32.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:13:32.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:32.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:32.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:32.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:13:32.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:32.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:13:32.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:13:32.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:13:32.29$vc4f8/vb=6,4 2006.133.08:13:32.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:13:32.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:13:32.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:13:32.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:32.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:32.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:32.37#ibcon#[27=AT06-04\r\n] 2006.133.08:13:32.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:32.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:13:32.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:13:32.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:13:32.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:32.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:32.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:32.54#ibcon#[27=USB\r\n] 2006.133.08:13:32.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:32.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:13:32.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:13:32.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:13:32.57$vc4f8/vabw=wide 2006.133.08:13:32.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:13:32.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:13:32.57#ibcon#ireg 8 cls_cnt 0 2006.133.08:13:32.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:32.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:32.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:32.59#ibcon#[25=BW32\r\n] 2006.133.08:13:32.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:32.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:13:32.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:13:32.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:13:32.62$vc4f8/vbbw=wide 2006.133.08:13:32.62#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:13:32.62#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:13:32.62#ibcon#ireg 8 cls_cnt 0 2006.133.08:13:32.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:13:32.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:13:32.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:13:32.71#ibcon#[27=BW32\r\n] 2006.133.08:13:32.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:13:32.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:13:32.74#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:13:32.74#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:13:32.74$4f8m12a/ifd4f 2006.133.08:13:32.74$ifd4f/lo= 2006.133.08:13:32.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:13:32.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:13:32.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:13:32.74$ifd4f/patch= 2006.133.08:13:32.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:13:32.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:13:32.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:13:32.74$4f8m12a/"form=m,16.000,1:2 2006.133.08:13:32.74$4f8m12a/"tpicd 2006.133.08:13:32.74$4f8m12a/echo=off 2006.133.08:13:32.74$4f8m12a/xlog=off 2006.133.08:13:32.74:!2006.133.08:14:00 2006.133.08:13:44.13#trakl#Source acquired 2006.133.08:13:45.13#flagr#flagr/antenna,acquired 2006.133.08:14:00.00:preob 2006.133.08:14:01.13/onsource/TRACKING 2006.133.08:14:01.13:!2006.133.08:14:10 2006.133.08:14:10.00:data_valid=on 2006.133.08:14:10.00:midob 2006.133.08:14:10.13/onsource/TRACKING 2006.133.08:14:10.13/wx/11.27,1009.7,100 2006.133.08:14:10.24/cable/+6.5562E-03 2006.133.08:14:11.33/va/01,08,usb,yes,48,51 2006.133.08:14:11.33/va/02,07,usb,yes,49,51 2006.133.08:14:11.33/va/03,06,usb,yes,51,52 2006.133.08:14:11.33/va/04,07,usb,yes,50,53 2006.133.08:14:11.33/va/05,06,usb,yes,57,61 2006.133.08:14:11.33/va/06,05,usb,yes,59,58 2006.133.08:14:11.33/va/07,05,usb,yes,59,58 2006.133.08:14:11.33/va/08,06,usb,yes,55,54 2006.133.08:14:11.56/valo/01,532.99,yes,locked 2006.133.08:14:11.56/valo/02,572.99,yes,locked 2006.133.08:14:11.56/valo/03,672.99,yes,locked 2006.133.08:14:11.56/valo/04,832.99,yes,locked 2006.133.08:14:11.56/valo/05,652.99,yes,locked 2006.133.08:14:11.56/valo/06,772.99,yes,locked 2006.133.08:14:11.56/valo/07,832.99,yes,locked 2006.133.08:14:11.56/valo/08,852.99,yes,locked 2006.133.08:14:12.65/vb/01,04,usb,yes,30,29 2006.133.08:14:12.65/vb/02,04,usb,yes,32,34 2006.133.08:14:12.65/vb/03,04,usb,yes,29,32 2006.133.08:14:12.65/vb/04,04,usb,yes,30,30 2006.133.08:14:12.65/vb/05,04,usb,yes,28,32 2006.133.08:14:12.65/vb/06,04,usb,yes,29,32 2006.133.08:14:12.65/vb/07,04,usb,yes,31,31 2006.133.08:14:12.65/vb/08,04,usb,yes,29,32 2006.133.08:14:12.88/vblo/01,632.99,yes,locked 2006.133.08:14:12.88/vblo/02,640.99,yes,locked 2006.133.08:14:12.88/vblo/03,656.99,yes,locked 2006.133.08:14:12.88/vblo/04,712.99,yes,locked 2006.133.08:14:12.88/vblo/05,744.99,yes,locked 2006.133.08:14:12.88/vblo/06,752.99,yes,locked 2006.133.08:14:12.88/vblo/07,734.99,yes,locked 2006.133.08:14:12.88/vblo/08,744.99,yes,locked 2006.133.08:14:13.03/vabw/8 2006.133.08:14:13.18/vbbw/8 2006.133.08:14:13.27/xfe/off,on,15.2 2006.133.08:14:13.67/ifatt/23,28,28,28 2006.133.08:14:14.08/fmout-gps/S +1.89E-07 2006.133.08:14:14.12:!2006.133.08:15:10 2006.133.08:15:10.01:data_valid=off 2006.133.08:15:10.01:postob 2006.133.08:15:10.14/cable/+6.5563E-03 2006.133.08:15:10.14/wx/11.26,1009.7,100 2006.133.08:15:11.08/fmout-gps/S +1.89E-07 2006.133.08:15:11.08:scan_name=133-0816,k06133,60 2006.133.08:15:11.08:source=1300+580,130252.47,574837.6,2000.0,cw 2006.133.08:15:11.14#flagr#flagr/antenna,new-source 2006.133.08:15:12.14:checkk5 2006.133.08:15:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:15:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:15:13.24/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:15:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:15:13.98/chk_obsdata//k5ts1/T1330814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:15:14.35/chk_obsdata//k5ts2/T1330814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:15:14.72/chk_obsdata//k5ts3/T1330814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:15:15.08/chk_obsdata//k5ts4/T1330814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:15:15.78/k5log//k5ts1_log_newline 2006.133.08:15:16.48/k5log//k5ts2_log_newline 2006.133.08:15:17.20/k5log//k5ts3_log_newline 2006.133.08:15:17.89/k5log//k5ts4_log_newline 2006.133.08:15:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:15:17.91:4f8m12a=2 2006.133.08:15:17.91$4f8m12a/echo=on 2006.133.08:15:17.91$4f8m12a/pcalon 2006.133.08:15:17.91$pcalon/"no phase cal control is implemented here 2006.133.08:15:17.91$4f8m12a/"tpicd=stop 2006.133.08:15:17.91$4f8m12a/vc4f8 2006.133.08:15:17.91$vc4f8/valo=1,532.99 2006.133.08:15:17.91#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.08:15:17.91#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.08:15:17.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:17.91#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:17.91#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:17.91#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:17.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:15:17.98#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:17.98#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:17.98#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:15:17.98#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:15:17.98$vc4f8/va=1,8 2006.133.08:15:17.98#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.08:15:17.98#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.08:15:17.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:17.98#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:17.98#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:17.98#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:18.00#ibcon#[25=AT01-08\r\n] 2006.133.08:15:18.03#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:18.03#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:18.03#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.08:15:18.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:18.03#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:18.15#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:18.15#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:18.17#ibcon#[25=USB\r\n] 2006.133.08:15:18.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:18.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:18.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:15:18.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:15:18.22$vc4f8/valo=2,572.99 2006.133.08:15:18.22#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.08:15:18.22#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.08:15:18.22#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:18.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:18.22#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:18.22#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:15:18.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:18.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:18.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:15:18.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:15:18.27$vc4f8/va=2,7 2006.133.08:15:18.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.08:15:18.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.08:15:18.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:18.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:18.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:18.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:18.35#ibcon#[25=AT02-07\r\n] 2006.133.08:15:18.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:18.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:18.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.08:15:18.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:18.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:18.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:18.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:18.52#ibcon#[25=USB\r\n] 2006.133.08:15:18.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:18.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:18.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:15:18.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:15:18.55$vc4f8/valo=3,672.99 2006.133.08:15:18.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:15:18.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:15:18.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:18.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:18.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:18.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:15:18.62#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:18.62#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:18.62#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:15:18.62#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:15:18.62$vc4f8/va=3,6 2006.133.08:15:18.62#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.08:15:18.62#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.08:15:18.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:18.62#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:18.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:18.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:18.69#ibcon#[25=AT03-06\r\n] 2006.133.08:15:18.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:18.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:18.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.08:15:18.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:18.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:18.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:18.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:18.86#ibcon#[25=USB\r\n] 2006.133.08:15:18.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:18.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:18.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:15:18.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:15:18.89$vc4f8/valo=4,832.99 2006.133.08:15:18.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.08:15:18.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.08:15:18.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:18.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:18.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:18.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:18.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:15:18.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:18.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:18.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:15:18.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:15:18.95$vc4f8/va=4,7 2006.133.08:15:18.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.08:15:18.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.08:15:18.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:18.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:19.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:19.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:19.03#ibcon#[25=AT04-07\r\n] 2006.133.08:15:19.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:19.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:19.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.08:15:19.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:19.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:19.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:19.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:19.20#ibcon#[25=USB\r\n] 2006.133.08:15:19.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:19.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:19.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:15:19.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:15:19.23$vc4f8/valo=5,652.99 2006.133.08:15:19.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:15:19.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:15:19.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:19.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:19.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:19.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:19.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:15:19.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:19.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:19.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:15:19.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:15:19.29$vc4f8/va=5,6 2006.133.08:15:19.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.08:15:19.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.08:15:19.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:19.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:19.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:19.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:19.37#ibcon#[25=AT05-06\r\n] 2006.133.08:15:19.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:19.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:19.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.08:15:19.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:19.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:19.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:19.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:19.54#ibcon#[25=USB\r\n] 2006.133.08:15:19.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:19.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:19.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:15:19.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:15:19.57$vc4f8/valo=6,772.99 2006.133.08:15:19.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:15:19.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:15:19.57#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:19.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:19.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:19.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:19.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:15:19.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:19.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:19.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:15:19.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:15:19.63$vc4f8/va=6,5 2006.133.08:15:19.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.133.08:15:19.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.133.08:15:19.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:19.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:19.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:19.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:19.71#ibcon#[25=AT06-05\r\n] 2006.133.08:15:19.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:19.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:19.74#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.133.08:15:19.74#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:19.74#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:15:19.86#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:15:19.86#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:15:19.88#ibcon#[25=USB\r\n] 2006.133.08:15:19.91#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:15:19.91#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.133.08:15:19.91#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:15:19.91#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:15:19.91$vc4f8/valo=7,832.99 2006.133.08:15:19.91#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.133.08:15:19.91#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.133.08:15:19.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:19.91#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:15:19.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:15:19.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:15:19.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:15:19.97#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:15:19.97#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.133.08:15:19.97#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:15:19.97#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:15:19.97$vc4f8/va=7,5 2006.133.08:15:19.97#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.133.08:15:19.97#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.133.08:15:19.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:19.97#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:15:20.03#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:15:20.03#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:15:20.05#ibcon#[25=AT07-05\r\n] 2006.133.08:15:20.08#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:15:20.08#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.133.08:15:20.08#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.133.08:15:20.08#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:20.08#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:15:20.20#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:15:20.20#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:15:20.22#ibcon#[25=USB\r\n] 2006.133.08:15:20.25#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:15:20.25#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.133.08:15:20.25#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:15:20.25#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:15:20.25$vc4f8/valo=8,852.99 2006.133.08:15:20.25#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.133.08:15:20.25#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.133.08:15:20.25#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:20.25#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:15:20.25#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:15:20.25#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:15:20.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:15:20.31#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:15:20.31#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.133.08:15:20.31#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:15:20.31#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:15:20.31$vc4f8/va=8,6 2006.133.08:15:20.31#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.133.08:15:20.31#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.133.08:15:20.31#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:20.31#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:15:20.37#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:15:20.37#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:15:20.39#ibcon#[25=AT08-06\r\n] 2006.133.08:15:20.42#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:15:20.42#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.133.08:15:20.42#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.133.08:15:20.42#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:20.42#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:15:20.54#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:15:20.54#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:15:20.56#ibcon#[25=USB\r\n] 2006.133.08:15:20.59#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:15:20.59#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.133.08:15:20.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:15:20.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:15:20.59$vc4f8/vblo=1,632.99 2006.133.08:15:20.59#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.08:15:20.59#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.08:15:20.59#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:20.59#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:15:20.59#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:15:20.59#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:15:20.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:15:20.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:15:20.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:15:20.65#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:15:20.65#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:15:20.65$vc4f8/vb=1,4 2006.133.08:15:20.65#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.133.08:15:20.65#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.133.08:15:20.65#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:20.65#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:15:20.65#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:15:20.65#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:15:20.67#ibcon#[27=AT01-04\r\n] 2006.133.08:15:20.70#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:15:20.70#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.133.08:15:20.70#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.133.08:15:20.70#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:20.70#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:15:20.82#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:15:20.82#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:15:20.84#ibcon#[27=USB\r\n] 2006.133.08:15:20.87#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:15:20.87#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.133.08:15:20.87#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:15:20.87#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:15:20.87$vc4f8/vblo=2,640.99 2006.133.08:15:20.87#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.133.08:15:20.87#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.133.08:15:20.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:20.87#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:20.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:20.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:20.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:15:20.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:20.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.133.08:15:20.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:15:20.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:15:20.93$vc4f8/vb=2,4 2006.133.08:15:20.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.133.08:15:20.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.133.08:15:20.93#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:20.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:20.99#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:20.99#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:21.01#ibcon#[27=AT02-04\r\n] 2006.133.08:15:21.04#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:21.04#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.133.08:15:21.04#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.133.08:15:21.04#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:21.04#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:21.16#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:21.16#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:21.18#ibcon#[27=USB\r\n] 2006.133.08:15:21.21#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:21.21#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.133.08:15:21.21#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:15:21.21#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:15:21.21$vc4f8/vblo=3,656.99 2006.133.08:15:21.21#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.133.08:15:21.21#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.133.08:15:21.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:21.21#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:21.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:21.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:21.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:15:21.27#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:21.27#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.133.08:15:21.27#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:15:21.27#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:15:21.27$vc4f8/vb=3,4 2006.133.08:15:21.27#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.133.08:15:21.27#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.133.08:15:21.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:21.27#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:21.33#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:21.33#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:21.35#ibcon#[27=AT03-04\r\n] 2006.133.08:15:21.38#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:21.38#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.133.08:15:21.38#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.133.08:15:21.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:21.38#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:21.50#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:21.50#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:21.52#ibcon#[27=USB\r\n] 2006.133.08:15:21.55#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:21.55#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.133.08:15:21.55#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:15:21.55#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:15:21.55$vc4f8/vblo=4,712.99 2006.133.08:15:21.55#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:15:21.55#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:15:21.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:21.55#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:21.55#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:21.55#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:21.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:15:21.61#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:21.61#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:15:21.61#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:15:21.61#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:15:21.61$vc4f8/vb=4,4 2006.133.08:15:21.61#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.133.08:15:21.61#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.133.08:15:21.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:21.61#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:21.67#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:21.67#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:21.69#ibcon#[27=AT04-04\r\n] 2006.133.08:15:21.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:21.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.133.08:15:21.72#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.133.08:15:21.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:21.72#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:21.84#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:21.84#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:21.86#ibcon#[27=USB\r\n] 2006.133.08:15:21.89#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:21.89#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.133.08:15:21.89#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:15:21.89#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:15:21.89$vc4f8/vblo=5,744.99 2006.133.08:15:21.89#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.133.08:15:21.89#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.133.08:15:21.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:21.89#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:21.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:21.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:21.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:15:21.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:21.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.133.08:15:21.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:15:21.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:15:21.95$vc4f8/vb=5,4 2006.133.08:15:21.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.133.08:15:21.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.133.08:15:21.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:21.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:22.01#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:22.01#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:22.03#ibcon#[27=AT05-04\r\n] 2006.133.08:15:22.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:22.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.133.08:15:22.06#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.133.08:15:22.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:22.06#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:22.18#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:22.18#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:22.20#ibcon#[27=USB\r\n] 2006.133.08:15:22.23#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:22.23#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.133.08:15:22.23#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:15:22.23#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:15:22.23$vc4f8/vblo=6,752.99 2006.133.08:15:22.23#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:15:22.23#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:15:22.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:15:22.23#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:22.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:22.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:22.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:15:22.29#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:22.29#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:15:22.29#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:15:22.29#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:15:22.29$vc4f8/vb=6,4 2006.133.08:15:22.29#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.133.08:15:22.29#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.133.08:15:22.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:15:22.29#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:22.35#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:22.35#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:22.37#ibcon#[27=AT06-04\r\n] 2006.133.08:15:22.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:22.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.133.08:15:22.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.133.08:15:22.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:15:22.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:22.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:22.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:22.54#ibcon#[27=USB\r\n] 2006.133.08:15:22.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:22.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.133.08:15:22.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:15:22.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:15:22.57$vc4f8/vabw=wide 2006.133.08:15:22.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.133.08:15:22.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.133.08:15:22.57#ibcon#ireg 8 cls_cnt 0 2006.133.08:15:22.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:22.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:22.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:22.59#ibcon#[25=BW32\r\n] 2006.133.08:15:22.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:22.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.133.08:15:22.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:15:22.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:15:22.62$vc4f8/vbbw=wide 2006.133.08:15:22.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:15:22.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:15:22.62#ibcon#ireg 8 cls_cnt 0 2006.133.08:15:22.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:15:22.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:15:22.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:15:22.71#ibcon#[27=BW32\r\n] 2006.133.08:15:22.74#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:15:22.74#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:15:22.74#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:15:22.74#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:15:22.74$4f8m12a/ifd4f 2006.133.08:15:22.74$ifd4f/lo= 2006.133.08:15:22.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:15:22.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:15:22.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:15:22.74$ifd4f/patch= 2006.133.08:15:22.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:15:22.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:15:22.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:15:22.74$4f8m12a/"form=m,16.000,1:2 2006.133.08:15:22.74$4f8m12a/"tpicd 2006.133.08:15:22.74$4f8m12a/echo=off 2006.133.08:15:22.74$4f8m12a/xlog=off 2006.133.08:15:22.74:!2006.133.08:15:50 2006.133.08:15:31.14#trakl#Source acquired 2006.133.08:15:32.14#flagr#flagr/antenna,acquired 2006.133.08:15:50.00:preob 2006.133.08:15:51.14/onsource/TRACKING 2006.133.08:15:51.14:!2006.133.08:16:00 2006.133.08:16:00.00:data_valid=on 2006.133.08:16:00.00:midob 2006.133.08:16:00.14/onsource/TRACKING 2006.133.08:16:00.14/wx/11.26,1009.7,100 2006.133.08:16:00.26/cable/+6.5567E-03 2006.133.08:16:01.35/va/01,08,usb,yes,48,50 2006.133.08:16:01.35/va/02,07,usb,yes,48,50 2006.133.08:16:01.35/va/03,06,usb,yes,51,51 2006.133.08:16:01.35/va/04,07,usb,yes,49,53 2006.133.08:16:01.35/va/05,06,usb,yes,57,61 2006.133.08:16:01.35/va/06,05,usb,yes,59,58 2006.133.08:16:01.35/va/07,05,usb,yes,58,58 2006.133.08:16:01.35/va/08,06,usb,yes,54,53 2006.133.08:16:01.58/valo/01,532.99,yes,locked 2006.133.08:16:01.58/valo/02,572.99,yes,locked 2006.133.08:16:01.58/valo/03,672.99,yes,locked 2006.133.08:16:01.58/valo/04,832.99,yes,locked 2006.133.08:16:01.58/valo/05,652.99,yes,locked 2006.133.08:16:01.58/valo/06,772.99,yes,locked 2006.133.08:16:01.58/valo/07,832.99,yes,locked 2006.133.08:16:01.58/valo/08,852.99,yes,locked 2006.133.08:16:02.67/vb/01,04,usb,yes,31,29 2006.133.08:16:02.67/vb/02,04,usb,yes,32,34 2006.133.08:16:02.67/vb/03,04,usb,yes,29,33 2006.133.08:16:02.67/vb/04,04,usb,yes,30,30 2006.133.08:16:02.67/vb/05,04,usb,yes,28,32 2006.133.08:16:02.67/vb/06,04,usb,yes,29,32 2006.133.08:16:02.67/vb/07,04,usb,yes,31,31 2006.133.08:16:02.67/vb/08,04,usb,yes,29,32 2006.133.08:16:02.90/vblo/01,632.99,yes,locked 2006.133.08:16:02.90/vblo/02,640.99,yes,locked 2006.133.08:16:02.90/vblo/03,656.99,yes,locked 2006.133.08:16:02.90/vblo/04,712.99,yes,locked 2006.133.08:16:02.90/vblo/05,744.99,yes,locked 2006.133.08:16:02.90/vblo/06,752.99,yes,locked 2006.133.08:16:02.90/vblo/07,734.99,yes,locked 2006.133.08:16:02.90/vblo/08,744.99,yes,locked 2006.133.08:16:03.05/vabw/8 2006.133.08:16:03.20/vbbw/8 2006.133.08:16:03.29/xfe/off,on,16.0 2006.133.08:16:03.67/ifatt/23,28,28,28 2006.133.08:16:04.08/fmout-gps/S +1.90E-07 2006.133.08:16:04.12:!2006.133.08:17:00 2006.133.08:17:00.00:data_valid=off 2006.133.08:17:00.00:postob 2006.133.08:17:00.08/cable/+6.5561E-03 2006.133.08:17:00.08/wx/11.27,1009.8,100 2006.133.08:17:01.08/fmout-gps/S +1.89E-07 2006.133.08:17:01.08:scan_name=133-0817,k06133,60 2006.133.08:17:01.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.133.08:17:01.14#flagr#flagr/antenna,new-source 2006.133.08:17:02.14:checkk5 2006.133.08:17:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:17:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:17:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:17:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:17:03.98/chk_obsdata//k5ts1/T1330816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:17:04.35/chk_obsdata//k5ts2/T1330816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:17:04.72/chk_obsdata//k5ts3/T1330816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:17:05.08/chk_obsdata//k5ts4/T1330816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:17:05.78/k5log//k5ts1_log_newline 2006.133.08:17:06.48/k5log//k5ts2_log_newline 2006.133.08:17:07.19/k5log//k5ts3_log_newline 2006.133.08:17:07.88/k5log//k5ts4_log_newline 2006.133.08:17:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:17:07.90:4f8m12a=2 2006.133.08:17:07.90$4f8m12a/echo=on 2006.133.08:17:07.90$4f8m12a/pcalon 2006.133.08:17:07.90$pcalon/"no phase cal control is implemented here 2006.133.08:17:07.90$4f8m12a/"tpicd=stop 2006.133.08:17:07.90$4f8m12a/vc4f8 2006.133.08:17:07.90$vc4f8/valo=1,532.99 2006.133.08:17:07.91#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:17:07.91#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:17:07.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:07.91#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:07.91#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:07.91#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:17:08.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:08.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:08.00#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:17:08.00#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:17:08.00$vc4f8/va=1,8 2006.133.08:17:08.00#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.08:17:08.00#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.08:17:08.00#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:08.00#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:08.00#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:08.00#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:08.03#ibcon#[25=AT01-08\r\n] 2006.133.08:17:08.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:08.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:08.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.08:17:08.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:08.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:08.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:08.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:08.20#ibcon#[25=USB\r\n] 2006.133.08:17:08.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:08.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:08.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:17:08.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:17:08.23$vc4f8/valo=2,572.99 2006.133.08:17:08.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:17:08.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:17:08.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:08.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:08.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:08.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:17:08.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:08.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:08.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:17:08.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:17:08.30$vc4f8/va=2,7 2006.133.08:17:08.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:17:08.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:17:08.30#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:08.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:08.34#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:08.34#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:08.36#ibcon#[25=AT02-07\r\n] 2006.133.08:17:08.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:08.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:08.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:17:08.39#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:08.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:08.51#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:08.51#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:08.53#ibcon#[25=USB\r\n] 2006.133.08:17:08.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:08.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:08.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:17:08.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:17:08.57$vc4f8/valo=3,672.99 2006.133.08:17:08.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:17:08.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:17:08.57#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:08.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:08.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:08.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:17:08.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:08.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:08.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:17:08.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:17:08.63$vc4f8/va=3,6 2006.133.08:17:08.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.08:17:08.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.08:17:08.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:08.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:08.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:08.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:08.71#ibcon#[25=AT03-06\r\n] 2006.133.08:17:08.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:08.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:08.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.08:17:08.74#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:08.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:08.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:08.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:08.88#ibcon#[25=USB\r\n] 2006.133.08:17:08.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:08.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:08.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:17:08.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:17:08.91$vc4f8/valo=4,832.99 2006.133.08:17:08.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.08:17:08.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.08:17:08.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:08.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:08.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:08.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:17:08.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:08.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:08.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:17:08.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:17:08.97$vc4f8/va=4,7 2006.133.08:17:08.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.08:17:08.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.08:17:08.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:08.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:09.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:09.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:09.05#ibcon#[25=AT04-07\r\n] 2006.133.08:17:09.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:09.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:09.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.08:17:09.08#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:09.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:09.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:09.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:09.22#ibcon#[25=USB\r\n] 2006.133.08:17:09.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:09.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:09.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:17:09.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:17:09.25$vc4f8/valo=5,652.99 2006.133.08:17:09.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.08:17:09.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.08:17:09.25#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:09.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:09.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:09.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:17:09.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:09.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:09.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:17:09.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:17:09.31$vc4f8/va=5,6 2006.133.08:17:09.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.08:17:09.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.08:17:09.31#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:09.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:09.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:09.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:09.39#ibcon#[25=AT05-06\r\n] 2006.133.08:17:09.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:09.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:09.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.08:17:09.42#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:09.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:09.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:09.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:09.56#ibcon#[25=USB\r\n] 2006.133.08:17:09.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:09.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:09.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:17:09.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:17:09.59$vc4f8/valo=6,772.99 2006.133.08:17:09.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.08:17:09.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.08:17:09.59#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:09.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:09.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:09.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:17:09.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:09.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:09.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:17:09.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:17:09.65$vc4f8/va=6,5 2006.133.08:17:09.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.133.08:17:09.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.133.08:17:09.65#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:09.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:09.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:09.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:09.73#ibcon#[25=AT06-05\r\n] 2006.133.08:17:09.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:09.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:09.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.133.08:17:09.76#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:09.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:17:09.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:17:09.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:17:09.90#ibcon#[25=USB\r\n] 2006.133.08:17:09.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:17:09.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.133.08:17:09.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:17:09.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:17:09.93$vc4f8/valo=7,832.99 2006.133.08:17:09.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.133.08:17:09.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.133.08:17:09.93#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:09.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:17:09.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:17:09.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:17:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:17:09.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:17:09.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.133.08:17:09.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:17:09.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:17:09.99$vc4f8/va=7,5 2006.133.08:17:09.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.133.08:17:09.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.133.08:17:09.99#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:09.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:17:10.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:17:10.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:17:10.07#ibcon#[25=AT07-05\r\n] 2006.133.08:17:10.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:17:10.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.133.08:17:10.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.133.08:17:10.10#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:10.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:17:10.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:17:10.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:17:10.24#ibcon#[25=USB\r\n] 2006.133.08:17:10.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:17:10.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.133.08:17:10.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:17:10.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:17:10.27$vc4f8/valo=8,852.99 2006.133.08:17:10.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.133.08:17:10.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.133.08:17:10.27#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:10.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:17:10.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:17:10.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:17:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:17:10.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:17:10.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.133.08:17:10.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:17:10.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:17:10.33$vc4f8/va=8,6 2006.133.08:17:10.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.133.08:17:10.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.133.08:17:10.33#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:10.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:17:10.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:17:10.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:17:10.41#ibcon#[25=AT08-06\r\n] 2006.133.08:17:10.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:17:10.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.133.08:17:10.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.133.08:17:10.44#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:10.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:17:10.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:17:10.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:17:10.58#ibcon#[25=USB\r\n] 2006.133.08:17:10.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:17:10.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.133.08:17:10.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:17:10.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:17:10.61$vc4f8/vblo=1,632.99 2006.133.08:17:10.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.133.08:17:10.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.133.08:17:10.61#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:10.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:17:10.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:17:10.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:17:10.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:17:10.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:17:10.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.133.08:17:10.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:17:10.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:17:10.67$vc4f8/vb=1,4 2006.133.08:17:10.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.133.08:17:10.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.133.08:17:10.67#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:10.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:17:10.67#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:17:10.67#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:17:10.69#ibcon#[27=AT01-04\r\n] 2006.133.08:17:10.72#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:17:10.72#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.133.08:17:10.72#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.133.08:17:10.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:10.72#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:17:10.84#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:17:10.84#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:17:10.86#ibcon#[27=USB\r\n] 2006.133.08:17:10.89#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:17:10.89#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.133.08:17:10.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:17:10.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:17:10.89$vc4f8/vblo=2,640.99 2006.133.08:17:10.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:17:10.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:17:10.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:10.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:10.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:10.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:10.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:17:10.95#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:10.95#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:17:10.95#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:17:10.95#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:17:10.95$vc4f8/vb=2,4 2006.133.08:17:10.95#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.133.08:17:10.95#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.133.08:17:10.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:10.95#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:11.01#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:11.01#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:11.03#ibcon#[27=AT02-04\r\n] 2006.133.08:17:11.06#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:11.06#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.133.08:17:11.06#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.133.08:17:11.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:11.06#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:11.18#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:11.18#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:11.20#ibcon#[27=USB\r\n] 2006.133.08:17:11.23#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:11.23#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.133.08:17:11.23#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:17:11.23#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:17:11.23$vc4f8/vblo=3,656.99 2006.133.08:17:11.23#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.133.08:17:11.23#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.133.08:17:11.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:11.23#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:11.23#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:11.23#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:11.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:17:11.29#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:11.29#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.133.08:17:11.29#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:17:11.29#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:17:11.29$vc4f8/vb=3,4 2006.133.08:17:11.29#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.133.08:17:11.29#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.133.08:17:11.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:11.29#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:11.35#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:11.35#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:11.37#ibcon#[27=AT03-04\r\n] 2006.133.08:17:11.40#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:11.40#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.133.08:17:11.40#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.133.08:17:11.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:11.40#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:11.52#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:11.52#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:11.54#ibcon#[27=USB\r\n] 2006.133.08:17:11.57#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:11.57#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.133.08:17:11.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:17:11.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:17:11.57$vc4f8/vblo=4,712.99 2006.133.08:17:11.57#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.133.08:17:11.57#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.133.08:17:11.57#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:11.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:11.57#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:11.57#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:11.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:17:11.63#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:11.63#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.133.08:17:11.63#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:17:11.63#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:17:11.63$vc4f8/vb=4,4 2006.133.08:17:11.63#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.133.08:17:11.63#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.133.08:17:11.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:11.63#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:11.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:11.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:11.71#ibcon#[27=AT04-04\r\n] 2006.133.08:17:11.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:11.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.133.08:17:11.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.133.08:17:11.74#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:11.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:11.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:11.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:11.88#ibcon#[27=USB\r\n] 2006.133.08:17:11.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:11.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.133.08:17:11.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:17:11.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:17:11.91$vc4f8/vblo=5,744.99 2006.133.08:17:11.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.133.08:17:11.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.133.08:17:11.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:11.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:11.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:11.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:11.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:17:11.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:11.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.133.08:17:11.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:17:11.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:17:11.97$vc4f8/vb=5,4 2006.133.08:17:11.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.133.08:17:11.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.133.08:17:11.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:11.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:12.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:12.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:12.05#ibcon#[27=AT05-04\r\n] 2006.133.08:17:12.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:12.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.133.08:17:12.08#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.133.08:17:12.08#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:12.08#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:12.20#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:12.20#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:12.22#ibcon#[27=USB\r\n] 2006.133.08:17:12.25#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:12.25#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.133.08:17:12.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:17:12.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:17:12.25$vc4f8/vblo=6,752.99 2006.133.08:17:12.25#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.133.08:17:12.25#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.133.08:17:12.25#ibcon#ireg 17 cls_cnt 0 2006.133.08:17:12.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:12.25#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:12.25#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:12.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:17:12.31#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:12.31#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.133.08:17:12.31#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:17:12.31#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:17:12.31$vc4f8/vb=6,4 2006.133.08:17:12.31#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.133.08:17:12.31#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.133.08:17:12.31#ibcon#ireg 11 cls_cnt 2 2006.133.08:17:12.31#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:12.37#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:12.37#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:12.39#ibcon#[27=AT06-04\r\n] 2006.133.08:17:12.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:12.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.133.08:17:12.42#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.133.08:17:12.42#ibcon#ireg 7 cls_cnt 0 2006.133.08:17:12.42#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:12.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:12.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:12.56#ibcon#[27=USB\r\n] 2006.133.08:17:12.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:12.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.133.08:17:12.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:17:12.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:17:12.59$vc4f8/vabw=wide 2006.133.08:17:12.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.133.08:17:12.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.133.08:17:12.59#ibcon#ireg 8 cls_cnt 0 2006.133.08:17:12.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:12.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:12.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:12.61#ibcon#[25=BW32\r\n] 2006.133.08:17:12.64#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:12.64#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.133.08:17:12.64#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:17:12.64#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:17:12.64$vc4f8/vbbw=wide 2006.133.08:17:12.64#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:17:12.64#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:17:12.64#ibcon#ireg 8 cls_cnt 0 2006.133.08:17:12.64#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:17:12.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:17:12.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:17:12.73#ibcon#[27=BW32\r\n] 2006.133.08:17:12.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:17:12.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:17:12.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:17:12.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:17:12.76$4f8m12a/ifd4f 2006.133.08:17:12.76$ifd4f/lo= 2006.133.08:17:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:17:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:17:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:17:12.76$ifd4f/patch= 2006.133.08:17:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:17:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:17:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:17:12.76$4f8m12a/"form=m,16.000,1:2 2006.133.08:17:12.76$4f8m12a/"tpicd 2006.133.08:17:12.76$4f8m12a/echo=off 2006.133.08:17:12.76$4f8m12a/xlog=off 2006.133.08:17:12.76:!2006.133.08:17:40 2006.133.08:17:23.14#trakl#Source acquired 2006.133.08:17:25.14#flagr#flagr/antenna,acquired 2006.133.08:17:40.00:preob 2006.133.08:17:41.14/onsource/TRACKING 2006.133.08:17:41.14:!2006.133.08:17:50 2006.133.08:17:50.00:data_valid=on 2006.133.08:17:50.00:midob 2006.133.08:17:50.14/onsource/TRACKING 2006.133.08:17:50.14/wx/11.29,1009.7,100 2006.133.08:17:50.25/cable/+6.5555E-03 2006.133.08:17:51.34/va/01,08,usb,yes,48,51 2006.133.08:17:51.34/va/02,07,usb,yes,49,51 2006.133.08:17:51.34/va/03,06,usb,yes,52,52 2006.133.08:17:51.34/va/04,07,usb,yes,50,53 2006.133.08:17:51.34/va/05,06,usb,yes,58,61 2006.133.08:17:51.34/va/06,05,usb,yes,59,58 2006.133.08:17:51.34/va/07,05,usb,yes,59,58 2006.133.08:17:51.34/va/08,06,usb,yes,55,54 2006.133.08:17:51.57/valo/01,532.99,yes,locked 2006.133.08:17:51.57/valo/02,572.99,yes,locked 2006.133.08:17:51.57/valo/03,672.99,yes,locked 2006.133.08:17:51.57/valo/04,832.99,yes,locked 2006.133.08:17:51.57/valo/05,652.99,yes,locked 2006.133.08:17:51.57/valo/06,772.99,yes,locked 2006.133.08:17:51.57/valo/07,832.99,yes,locked 2006.133.08:17:51.57/valo/08,852.99,yes,locked 2006.133.08:17:52.66/vb/01,04,usb,yes,31,30 2006.133.08:17:52.66/vb/02,04,usb,yes,33,35 2006.133.08:17:52.66/vb/03,04,usb,yes,30,34 2006.133.08:17:52.66/vb/04,04,usb,yes,31,31 2006.133.08:17:52.66/vb/05,04,usb,yes,29,33 2006.133.08:17:52.66/vb/06,04,usb,yes,30,33 2006.133.08:17:52.66/vb/07,04,usb,yes,32,32 2006.133.08:17:52.66/vb/08,04,usb,yes,30,33 2006.133.08:17:52.89/vblo/01,632.99,yes,locked 2006.133.08:17:52.89/vblo/02,640.99,yes,locked 2006.133.08:17:52.89/vblo/03,656.99,yes,locked 2006.133.08:17:52.89/vblo/04,712.99,yes,locked 2006.133.08:17:52.89/vblo/05,744.99,yes,locked 2006.133.08:17:52.89/vblo/06,752.99,yes,locked 2006.133.08:17:52.89/vblo/07,734.99,yes,locked 2006.133.08:17:52.89/vblo/08,744.99,yes,locked 2006.133.08:17:53.04/vabw/8 2006.133.08:17:53.19/vbbw/8 2006.133.08:17:53.28/xfe/off,on,14.7 2006.133.08:17:53.66/ifatt/23,28,28,28 2006.133.08:17:54.08/fmout-gps/S +1.89E-07 2006.133.08:17:54.12:!2006.133.08:18:50 2006.133.08:18:50.01:data_valid=off 2006.133.08:18:50.01:postob 2006.133.08:18:50.17/cable/+6.5558E-03 2006.133.08:18:50.17/wx/11.30,1009.7,100 2006.133.08:18:51.08/fmout-gps/S +1.89E-07 2006.133.08:18:51.08:scan_name=133-0820,k06133,60 2006.133.08:18:51.08:source=0133+476,013658.59,475129.1,2000.0,ccw 2006.133.08:18:51.14#flagr#flagr/antenna,new-source 2006.133.08:18:52.14:checkk5 2006.133.08:18:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:18:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:18:56.26/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:18:56.63/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:18:57.00/chk_obsdata//k5ts1/T1330817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:18:57.37/chk_obsdata//k5ts2/T1330817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:18:57.74/chk_obsdata//k5ts3/T1330817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:18:58.11/chk_obsdata//k5ts4/T1330817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:18:58.80/k5log//k5ts1_log_newline 2006.133.08:18:59.48/k5log//k5ts2_log_newline 2006.133.08:19:00.17/k5log//k5ts3_log_newline 2006.133.08:19:00.85/k5log//k5ts4_log_newline 2006.133.08:19:00.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:19:00.87:4f8m12a=3 2006.133.08:19:00.87$4f8m12a/echo=on 2006.133.08:19:00.87$4f8m12a/pcalon 2006.133.08:19:00.87$pcalon/"no phase cal control is implemented here 2006.133.08:19:00.88$4f8m12a/"tpicd=stop 2006.133.08:19:00.88$4f8m12a/vc4f8 2006.133.08:19:00.88$vc4f8/valo=1,532.99 2006.133.08:19:00.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:19:00.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:19:00.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:00.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:00.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:00.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:00.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:19:00.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:00.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:00.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:19:00.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:19:00.97$vc4f8/va=1,8 2006.133.08:19:00.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.08:19:00.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.08:19:00.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:00.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:00.97#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:00.97#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:01.00#ibcon#[25=AT01-08\r\n] 2006.133.08:19:01.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:01.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:01.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.08:19:01.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:01.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:01.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:01.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:01.17#ibcon#[25=USB\r\n] 2006.133.08:19:01.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:01.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:01.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:19:01.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:19:01.21$vc4f8/valo=2,572.99 2006.133.08:19:01.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:19:01.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:19:01.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:01.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:01.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:01.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:01.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:19:01.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:01.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:01.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:19:01.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:19:01.27$vc4f8/va=2,7 2006.133.08:19:01.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:19:01.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:19:01.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:01.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:01.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:01.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:01.35#ibcon#[25=AT02-07\r\n] 2006.133.08:19:01.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:01.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:01.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:19:01.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:01.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:01.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:01.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:01.52#ibcon#[25=USB\r\n] 2006.133.08:19:01.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:01.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:01.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:19:01.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:19:01.55$vc4f8/valo=3,672.99 2006.133.08:19:01.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:19:01.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:19:01.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:01.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:01.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:01.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:01.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:19:01.62#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:01.62#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:01.62#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:19:01.62#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:19:01.62$vc4f8/va=3,6 2006.133.08:19:01.62#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:19:01.62#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:19:01.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:01.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:01.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:01.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:01.69#ibcon#[25=AT03-06\r\n] 2006.133.08:19:01.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:01.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:01.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:19:01.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:01.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:01.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:01.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:01.86#ibcon#[25=USB\r\n] 2006.133.08:19:01.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:01.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:01.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:19:01.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:19:01.89$vc4f8/valo=4,832.99 2006.133.08:19:01.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:19:01.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:19:01.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:01.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:01.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:01.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:01.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:19:01.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:01.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:01.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:19:01.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:19:01.95$vc4f8/va=4,7 2006.133.08:19:01.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:19:01.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:19:01.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:01.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:02.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:02.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:02.03#ibcon#[25=AT04-07\r\n] 2006.133.08:19:02.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:02.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:02.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:19:02.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:02.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:02.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:02.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:02.20#ibcon#[25=USB\r\n] 2006.133.08:19:02.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:02.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:02.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:19:02.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:19:02.23$vc4f8/valo=5,652.99 2006.133.08:19:02.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:19:02.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:19:02.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:02.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:02.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:02.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:02.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:19:02.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:02.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:02.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:19:02.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:19:02.29$vc4f8/va=5,6 2006.133.08:19:02.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:19:02.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:19:02.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:02.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:02.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:02.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:02.37#ibcon#[25=AT05-06\r\n] 2006.133.08:19:02.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:02.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:02.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:19:02.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:02.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:02.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:02.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:02.54#ibcon#[25=USB\r\n] 2006.133.08:19:02.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:02.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:02.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:19:02.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:19:02.57$vc4f8/valo=6,772.99 2006.133.08:19:02.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:19:02.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:19:02.57#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:02.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:02.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:02.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:02.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:19:02.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:02.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:02.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:19:02.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:19:02.63$vc4f8/va=6,5 2006.133.08:19:02.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:19:02.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:19:02.63#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:02.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:02.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:02.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:02.71#ibcon#[25=AT06-05\r\n] 2006.133.08:19:02.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:02.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:02.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:19:02.74#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:02.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:19:02.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:19:02.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:19:02.88#ibcon#[25=USB\r\n] 2006.133.08:19:02.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:19:02.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:19:02.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:19:02.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:19:02.91$vc4f8/valo=7,832.99 2006.133.08:19:02.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:19:02.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:19:02.91#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:02.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:19:02.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:19:02.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:19:02.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:19:02.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:19:02.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:19:02.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:19:02.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:19:02.97$vc4f8/va=7,5 2006.133.08:19:02.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:19:02.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:19:02.97#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:02.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:19:03.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:19:03.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:19:03.05#ibcon#[25=AT07-05\r\n] 2006.133.08:19:03.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:19:03.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:19:03.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:19:03.08#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:03.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:19:03.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:19:03.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:19:03.22#ibcon#[25=USB\r\n] 2006.133.08:19:03.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:19:03.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:19:03.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:19:03.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:19:03.25$vc4f8/valo=8,852.99 2006.133.08:19:03.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:19:03.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:19:03.25#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:03.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:19:03.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:19:03.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:19:03.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:19:03.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:19:03.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:19:03.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:19:03.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:19:03.32$vc4f8/va=8,6 2006.133.08:19:03.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:19:03.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:19:03.32#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:03.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:19:03.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:19:03.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:19:03.39#ibcon#[25=AT08-06\r\n] 2006.133.08:19:03.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:19:03.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:19:03.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:19:03.42#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:03.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:19:03.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:19:03.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:19:03.56#ibcon#[25=USB\r\n] 2006.133.08:19:03.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:19:03.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:19:03.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:19:03.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:19:03.59$vc4f8/vblo=1,632.99 2006.133.08:19:03.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:19:03.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:19:03.59#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:03.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:19:03.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:19:03.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:19:03.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:19:03.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:19:03.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:19:03.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:19:03.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:19:03.65$vc4f8/vb=1,4 2006.133.08:19:03.65#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:19:03.65#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:19:03.65#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:03.65#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:19:03.65#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:19:03.65#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:19:03.67#ibcon#[27=AT01-04\r\n] 2006.133.08:19:03.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:19:03.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:19:03.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:19:03.70#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:03.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:19:03.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:19:03.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:19:03.84#ibcon#[27=USB\r\n] 2006.133.08:19:03.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:19:03.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:19:03.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:19:03.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:19:03.87$vc4f8/vblo=2,640.99 2006.133.08:19:03.87#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:19:03.87#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:19:03.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:03.87#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:03.87#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:03.87#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:03.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:19:03.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:03.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:19:03.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:19:03.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:19:03.93$vc4f8/vb=2,4 2006.133.08:19:03.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.08:19:03.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.08:19:03.93#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:03.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:03.99#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:03.99#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:04.01#ibcon#[27=AT02-04\r\n] 2006.133.08:19:04.04#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:04.04#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:19:04.04#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.08:19:04.04#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:04.04#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:04.16#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:04.16#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:04.18#ibcon#[27=USB\r\n] 2006.133.08:19:04.21#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:04.21#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:19:04.21#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:19:04.21#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:19:04.21$vc4f8/vblo=3,656.99 2006.133.08:19:04.21#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:19:04.21#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:19:04.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:04.21#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:04.21#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:04.21#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:04.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:19:04.27#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:04.27#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:19:04.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:19:04.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:19:04.27$vc4f8/vb=3,4 2006.133.08:19:04.27#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:19:04.27#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:19:04.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:04.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:04.33#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:04.33#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:04.35#ibcon#[27=AT03-04\r\n] 2006.133.08:19:04.38#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:04.38#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:19:04.38#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:19:04.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:04.38#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:04.50#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:04.50#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:04.52#ibcon#[27=USB\r\n] 2006.133.08:19:04.55#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:04.55#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:19:04.55#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:19:04.55#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:19:04.55$vc4f8/vblo=4,712.99 2006.133.08:19:04.55#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:19:04.55#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:19:04.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:04.55#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:04.55#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:04.55#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:04.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:19:04.61#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:04.61#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:19:04.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:19:04.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:19:04.61$vc4f8/vb=4,4 2006.133.08:19:04.61#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:19:04.61#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:19:04.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:04.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:04.67#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:04.67#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:04.69#ibcon#[27=AT04-04\r\n] 2006.133.08:19:04.72#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:04.72#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:19:04.72#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:19:04.72#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:04.72#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:04.84#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:04.84#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:04.86#ibcon#[27=USB\r\n] 2006.133.08:19:04.89#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:04.89#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:19:04.89#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:19:04.89#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:19:04.89$vc4f8/vblo=5,744.99 2006.133.08:19:04.89#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:19:04.89#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:19:04.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:04.89#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:04.89#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:04.89#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:04.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:19:04.95#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:04.95#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:19:04.95#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:19:04.95#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:19:04.95$vc4f8/vb=5,4 2006.133.08:19:04.95#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:19:04.95#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:19:04.95#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:04.95#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:05.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:05.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:05.03#ibcon#[27=AT05-04\r\n] 2006.133.08:19:05.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:05.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:19:05.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:19:05.06#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:05.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:05.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:05.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:05.20#ibcon#[27=USB\r\n] 2006.133.08:19:05.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:05.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:19:05.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:19:05.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:19:05.23$vc4f8/vblo=6,752.99 2006.133.08:19:05.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:19:05.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:19:05.23#ibcon#ireg 17 cls_cnt 0 2006.133.08:19:05.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:05.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:05.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:05.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:19:05.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:05.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:19:05.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:19:05.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:19:05.29$vc4f8/vb=6,4 2006.133.08:19:05.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:19:05.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:19:05.29#ibcon#ireg 11 cls_cnt 2 2006.133.08:19:05.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:05.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:05.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:05.37#ibcon#[27=AT06-04\r\n] 2006.133.08:19:05.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:05.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:19:05.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:19:05.40#ibcon#ireg 7 cls_cnt 0 2006.133.08:19:05.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:05.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:05.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:05.54#ibcon#[27=USB\r\n] 2006.133.08:19:05.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:05.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:19:05.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:19:05.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:19:05.57$vc4f8/vabw=wide 2006.133.08:19:05.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:19:05.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:19:05.57#ibcon#ireg 8 cls_cnt 0 2006.133.08:19:05.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:05.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:05.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:05.60#ibcon#[25=BW32\r\n] 2006.133.08:19:05.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:05.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:19:05.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:19:05.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:19:05.63$vc4f8/vbbw=wide 2006.133.08:19:05.63#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.133.08:19:05.63#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.133.08:19:05.63#ibcon#ireg 8 cls_cnt 0 2006.133.08:19:05.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:19:05.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:19:05.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:19:05.71#ibcon#[27=BW32\r\n] 2006.133.08:19:05.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:19:05.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.133.08:19:05.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:19:05.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:19:05.74$4f8m12a/ifd4f 2006.133.08:19:05.74$ifd4f/lo= 2006.133.08:19:05.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:19:05.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:19:05.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:19:05.74$ifd4f/patch= 2006.133.08:19:05.74$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:19:05.74$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:19:05.74$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:19:05.74$4f8m12a/"form=m,16.000,1:2 2006.133.08:19:05.74$4f8m12a/"tpicd 2006.133.08:19:05.74$4f8m12a/echo=off 2006.133.08:19:05.74$4f8m12a/xlog=off 2006.133.08:19:05.74:!2006.133.08:20:40 2006.133.08:19:21.14#trakl#Source acquired 2006.133.08:19:21.14#flagr#flagr/antenna,acquired 2006.133.08:20:40.00:preob 2006.133.08:20:40.14/onsource/TRACKING 2006.133.08:20:40.14:!2006.133.08:20:50 2006.133.08:20:50.00:data_valid=on 2006.133.08:20:50.00:midob 2006.133.08:20:51.14/onsource/TRACKING 2006.133.08:20:51.14/wx/11.30,1009.7,100 2006.133.08:20:51.21/cable/+6.5555E-03 2006.133.08:20:52.30/va/01,08,usb,yes,47,49 2006.133.08:20:52.30/va/02,07,usb,yes,47,49 2006.133.08:20:52.30/va/03,06,usb,yes,50,50 2006.133.08:20:52.30/va/04,07,usb,yes,48,52 2006.133.08:20:52.30/va/05,06,usb,yes,56,60 2006.133.08:20:52.30/va/06,05,usb,yes,58,57 2006.133.08:20:52.30/va/07,05,usb,yes,57,57 2006.133.08:20:52.30/va/08,06,usb,yes,54,53 2006.133.08:20:52.53/valo/01,532.99,yes,locked 2006.133.08:20:52.53/valo/02,572.99,yes,locked 2006.133.08:20:52.53/valo/03,672.99,yes,locked 2006.133.08:20:52.53/valo/04,832.99,yes,locked 2006.133.08:20:52.53/valo/05,652.99,yes,locked 2006.133.08:20:52.53/valo/06,772.99,yes,locked 2006.133.08:20:52.53/valo/07,832.99,yes,locked 2006.133.08:20:52.53/valo/08,852.99,yes,locked 2006.133.08:20:53.62/vb/01,04,usb,yes,32,31 2006.133.08:20:53.62/vb/02,04,usb,yes,34,36 2006.133.08:20:53.62/vb/03,04,usb,yes,30,34 2006.133.08:20:53.62/vb/04,04,usb,yes,31,32 2006.133.08:20:53.62/vb/05,04,usb,yes,30,34 2006.133.08:20:53.62/vb/06,04,usb,yes,31,34 2006.133.08:20:53.62/vb/07,04,usb,yes,33,33 2006.133.08:20:53.62/vb/08,04,usb,yes,30,34 2006.133.08:20:53.85/vblo/01,632.99,yes,locked 2006.133.08:20:53.85/vblo/02,640.99,yes,locked 2006.133.08:20:53.85/vblo/03,656.99,yes,locked 2006.133.08:20:53.85/vblo/04,712.99,yes,locked 2006.133.08:20:53.85/vblo/05,744.99,yes,locked 2006.133.08:20:53.85/vblo/06,752.99,yes,locked 2006.133.08:20:53.85/vblo/07,734.99,yes,locked 2006.133.08:20:53.85/vblo/08,744.99,yes,locked 2006.133.08:20:54.00/vabw/8 2006.133.08:20:54.15/vbbw/8 2006.133.08:20:54.24/xfe/off,on,15.2 2006.133.08:20:54.63/ifatt/23,28,28,28 2006.133.08:20:55.08/fmout-gps/S +1.90E-07 2006.133.08:20:55.12:!2006.133.08:21:50 2006.133.08:21:50.02:data_valid=off 2006.133.08:21:50.02:postob 2006.133.08:21:50.13/cable/+6.5601E-03 2006.133.08:21:50.13/wx/11.30,1009.8,100 2006.133.08:21:51.08/fmout-gps/S +1.92E-07 2006.133.08:21:51.08:scan_name=133-0824,k06133,60 2006.133.08:21:51.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.133.08:21:51.15#flagr#flagr/antenna,new-source 2006.133.08:21:52.13:checkk5 2006.133.08:21:52.50/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:21:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:21:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:21:53.62/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:21:53.98/chk_obsdata//k5ts1/T1330820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:21:54.35/chk_obsdata//k5ts2/T1330820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:21:54.71/chk_obsdata//k5ts3/T1330820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:21:55.08/chk_obsdata//k5ts4/T1330820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:21:55.76/k5log//k5ts1_log_newline 2006.133.08:21:56.45/k5log//k5ts2_log_newline 2006.133.08:21:57.18/k5log//k5ts3_log_newline 2006.133.08:21:57.86/k5log//k5ts4_log_newline 2006.133.08:21:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:21:57.89:4f8m12a=3 2006.133.08:21:57.89$4f8m12a/echo=on 2006.133.08:21:57.89$4f8m12a/pcalon 2006.133.08:21:57.89$pcalon/"no phase cal control is implemented here 2006.133.08:21:57.89$4f8m12a/"tpicd=stop 2006.133.08:21:57.89$4f8m12a/vc4f8 2006.133.08:21:57.89$vc4f8/valo=1,532.99 2006.133.08:21:57.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:21:57.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:21:57.89#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:57.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:21:57.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:21:57.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:21:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:21:57.97#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:21:57.97#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:21:57.97#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:21:57.97#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:21:57.98$vc4f8/va=1,8 2006.133.08:21:57.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:21:57.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:21:57.98#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:57.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:21:57.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:21:57.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:21:58.00#ibcon#[25=AT01-08\r\n] 2006.133.08:21:58.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:21:58.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:21:58.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:21:58.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:58.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:21:58.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:21:58.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:21:58.17#ibcon#[25=USB\r\n] 2006.133.08:21:58.21#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:21:58.21#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:21:58.21#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:21:58.21#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:21:58.21$vc4f8/valo=2,572.99 2006.133.08:21:58.21#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:21:58.21#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:21:58.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:58.21#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:21:58.21#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:21:58.21#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:21:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:21:58.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:21:58.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:21:58.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:21:58.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:21:58.27$vc4f8/va=2,7 2006.133.08:21:58.27#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:21:58.27#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:21:58.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:58.27#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:21:58.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:21:58.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:21:58.34#ibcon#[25=AT02-07\r\n] 2006.133.08:21:58.38#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:21:58.38#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:21:58.38#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:21:58.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:58.38#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:21:58.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:21:58.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:21:58.51#ibcon#[25=USB\r\n] 2006.133.08:21:58.54#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:21:58.54#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:21:58.54#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:21:58.54#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:21:58.55$vc4f8/valo=3,672.99 2006.133.08:21:58.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:21:58.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:21:58.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:58.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:21:58.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:21:58.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:21:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:21:58.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:21:58.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:21:58.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:21:58.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:21:58.62$vc4f8/va=3,6 2006.133.08:21:58.62#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:21:58.62#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:21:58.62#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:58.62#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:21:58.66#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:21:58.66#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:21:58.67#ibcon#[25=AT03-06\r\n] 2006.133.08:21:58.70#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:21:58.70#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:21:58.70#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:21:58.70#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:58.70#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:21:58.82#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:21:58.82#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:21:58.84#ibcon#[25=USB\r\n] 2006.133.08:21:58.87#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:21:58.87#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:21:58.87#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:21:58.87#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:21:58.88$vc4f8/valo=4,832.99 2006.133.08:21:58.88#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:21:58.88#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:21:58.88#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:58.88#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:21:58.88#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:21:58.88#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:21:58.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:21:58.93#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:21:58.93#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:21:58.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:21:58.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:21:58.94$vc4f8/va=4,7 2006.133.08:21:58.94#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:21:58.94#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:21:58.94#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:58.94#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:21:58.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:21:58.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:21:59.00#ibcon#[25=AT04-07\r\n] 2006.133.08:21:59.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:21:59.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:21:59.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:21:59.03#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:59.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:21:59.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:21:59.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:21:59.17#ibcon#[25=USB\r\n] 2006.133.08:21:59.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:21:59.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:21:59.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:21:59.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:21:59.21$vc4f8/valo=5,652.99 2006.133.08:21:59.21#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:21:59.21#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:21:59.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:59.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:21:59.21#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:21:59.21#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:21:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:21:59.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:21:59.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:21:59.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:21:59.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:21:59.27$vc4f8/va=5,6 2006.133.08:21:59.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:21:59.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:21:59.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:59.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:21:59.31#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:21:59.31#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:21:59.33#ibcon#[25=AT05-06\r\n] 2006.133.08:21:59.36#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:21:59.36#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:21:59.36#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:21:59.36#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:59.36#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:21:59.48#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:21:59.48#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:21:59.50#ibcon#[25=USB\r\n] 2006.133.08:21:59.53#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:21:59.53#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:21:59.53#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:21:59.53#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:21:59.54$vc4f8/valo=6,772.99 2006.133.08:21:59.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:21:59.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:21:59.54#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:59.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:21:59.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:21:59.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:21:59.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:21:59.59#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:21:59.59#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:21:59.59#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:21:59.59#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:21:59.60$vc4f8/va=6,5 2006.133.08:21:59.60#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.133.08:21:59.60#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.133.08:21:59.60#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:59.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:21:59.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:21:59.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:21:59.66#ibcon#[25=AT06-05\r\n] 2006.133.08:21:59.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:21:59.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.133.08:21:59.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.133.08:21:59.69#ibcon#ireg 7 cls_cnt 0 2006.133.08:21:59.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:21:59.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:21:59.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:21:59.83#ibcon#[25=USB\r\n] 2006.133.08:21:59.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:21:59.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.133.08:21:59.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:21:59.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:21:59.87$vc4f8/valo=7,832.99 2006.133.08:21:59.87#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.133.08:21:59.87#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.133.08:21:59.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:21:59.87#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:21:59.87#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:21:59.87#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:21:59.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:21:59.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:21:59.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.133.08:21:59.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.133.08:21:59.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.133.08:21:59.93$vc4f8/va=7,5 2006.133.08:21:59.93#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.133.08:21:59.93#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.133.08:21:59.93#ibcon#ireg 11 cls_cnt 2 2006.133.08:21:59.93#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:21:59.97#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:21:59.97#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:21:59.99#ibcon#[25=AT07-05\r\n] 2006.133.08:22:00.02#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:22:00.02#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.133.08:22:00.02#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.133.08:22:00.02#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:00.02#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:22:00.14#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:22:00.14#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:22:00.16#ibcon#[25=USB\r\n] 2006.133.08:22:00.19#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:22:00.19#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.133.08:22:00.19#ibcon#about to clear, iclass 29 cls_cnt 0 2006.133.08:22:00.19#ibcon#cleared, iclass 29 cls_cnt 0 2006.133.08:22:00.20$vc4f8/valo=8,852.99 2006.133.08:22:00.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.133.08:22:00.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.133.08:22:00.20#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:00.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:22:00.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:22:00.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:22:00.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:22:00.25#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:22:00.25#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.133.08:22:00.25#ibcon#about to clear, iclass 31 cls_cnt 0 2006.133.08:22:00.25#ibcon#cleared, iclass 31 cls_cnt 0 2006.133.08:22:00.26$vc4f8/va=8,6 2006.133.08:22:00.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.133.08:22:00.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.133.08:22:00.26#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:00.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:22:00.30#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:22:00.30#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:22:00.32#ibcon#[25=AT08-06\r\n] 2006.133.08:22:00.35#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:22:00.35#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.133.08:22:00.35#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.133.08:22:00.35#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:00.35#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:22:00.47#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:22:00.47#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:22:00.49#ibcon#[25=USB\r\n] 2006.133.08:22:00.52#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:22:00.52#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.133.08:22:00.52#ibcon#about to clear, iclass 33 cls_cnt 0 2006.133.08:22:00.52#ibcon#cleared, iclass 33 cls_cnt 0 2006.133.08:22:00.53$vc4f8/vblo=1,632.99 2006.133.08:22:00.53#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.133.08:22:00.53#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.133.08:22:00.53#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:00.53#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:22:00.53#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:22:00.53#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:22:00.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:22:00.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:22:00.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.133.08:22:00.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.133.08:22:00.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.133.08:22:00.60$vc4f8/vb=1,4 2006.133.08:22:00.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.133.08:22:00.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.133.08:22:00.60#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:00.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:22:00.60#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:22:00.60#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:22:00.61#ibcon#[27=AT01-04\r\n] 2006.133.08:22:00.64#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:22:00.64#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.133.08:22:00.64#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.133.08:22:00.64#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:00.64#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:22:00.76#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:22:00.76#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:22:00.78#ibcon#[27=USB\r\n] 2006.133.08:22:00.81#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:22:00.81#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.133.08:22:00.81#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:22:00.81#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:22:00.82$vc4f8/vblo=2,640.99 2006.133.08:22:00.82#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.133.08:22:00.82#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.133.08:22:00.82#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:00.82#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:22:00.82#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:22:00.82#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:22:00.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:22:00.87#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:22:00.87#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.133.08:22:00.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.133.08:22:00.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.133.08:22:00.88$vc4f8/vb=2,4 2006.133.08:22:00.88#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:22:00.88#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:22:00.88#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:00.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:22:00.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:22:00.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:22:00.94#ibcon#[27=AT02-04\r\n] 2006.133.08:22:00.97#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:22:00.97#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:22:00.97#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:22:00.97#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:00.97#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:22:01.09#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:22:01.09#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:22:01.11#ibcon#[27=USB\r\n] 2006.133.08:22:01.14#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:22:01.14#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:22:01.14#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:22:01.14#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:22:01.15$vc4f8/vblo=3,656.99 2006.133.08:22:01.15#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.133.08:22:01.15#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.133.08:22:01.15#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:01.15#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:22:01.15#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:22:01.15#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:22:01.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:22:01.20#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:22:01.20#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.133.08:22:01.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.133.08:22:01.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.133.08:22:01.21$vc4f8/vb=3,4 2006.133.08:22:01.21#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.133.08:22:01.21#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.133.08:22:01.21#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:01.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:22:01.25#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:22:01.25#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:22:01.27#ibcon#[27=AT03-04\r\n] 2006.133.08:22:01.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:22:01.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.133.08:22:01.30#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.133.08:22:01.30#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:01.30#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:22:01.42#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:22:01.42#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:22:01.44#ibcon#[27=USB\r\n] 2006.133.08:22:01.47#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:22:01.47#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.133.08:22:01.47#ibcon#about to clear, iclass 7 cls_cnt 0 2006.133.08:22:01.47#ibcon#cleared, iclass 7 cls_cnt 0 2006.133.08:22:01.48$vc4f8/vblo=4,712.99 2006.133.08:22:01.48#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.133.08:22:01.48#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.133.08:22:01.48#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:01.48#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:22:01.48#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:22:01.48#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:22:01.49#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:22:01.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:22:01.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.133.08:22:01.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.133.08:22:01.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.133.08:22:01.54$vc4f8/vb=4,4 2006.133.08:22:01.54#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.133.08:22:01.54#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.133.08:22:01.54#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:01.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:22:01.58#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:22:01.58#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:22:01.60#ibcon#[27=AT04-04\r\n] 2006.133.08:22:01.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:22:01.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.133.08:22:01.63#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.133.08:22:01.63#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:01.63#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:22:01.75#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:22:01.75#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:22:01.77#ibcon#[27=USB\r\n] 2006.133.08:22:01.80#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:22:01.80#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.133.08:22:01.80#ibcon#about to clear, iclass 13 cls_cnt 0 2006.133.08:22:01.80#ibcon#cleared, iclass 13 cls_cnt 0 2006.133.08:22:01.81$vc4f8/vblo=5,744.99 2006.133.08:22:01.81#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.133.08:22:01.81#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.133.08:22:01.81#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:01.81#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:22:01.81#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:22:01.81#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:22:01.82#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:22:01.86#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:22:01.86#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.133.08:22:01.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.133.08:22:01.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.133.08:22:01.87$vc4f8/vb=5,4 2006.133.08:22:01.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.133.08:22:01.87#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.133.08:22:01.87#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:01.87#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:22:01.91#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:22:01.91#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:22:01.93#ibcon#[27=AT05-04\r\n] 2006.133.08:22:01.96#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:22:01.96#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.133.08:22:01.96#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.133.08:22:01.96#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:01.96#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:22:02.08#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:22:02.08#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:22:02.10#ibcon#[27=USB\r\n] 2006.133.08:22:02.13#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:22:02.13#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.133.08:22:02.13#ibcon#about to clear, iclass 17 cls_cnt 0 2006.133.08:22:02.13#ibcon#cleared, iclass 17 cls_cnt 0 2006.133.08:22:02.14$vc4f8/vblo=6,752.99 2006.133.08:22:02.14#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.133.08:22:02.14#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.133.08:22:02.14#ibcon#ireg 17 cls_cnt 0 2006.133.08:22:02.14#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:22:02.14#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:22:02.14#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:22:02.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:22:02.19#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:22:02.19#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.133.08:22:02.19#ibcon#about to clear, iclass 19 cls_cnt 0 2006.133.08:22:02.19#ibcon#cleared, iclass 19 cls_cnt 0 2006.133.08:22:02.20$vc4f8/vb=6,4 2006.133.08:22:02.20#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.133.08:22:02.20#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.133.08:22:02.20#ibcon#ireg 11 cls_cnt 2 2006.133.08:22:02.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:22:02.24#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:22:02.24#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:22:02.26#ibcon#[27=AT06-04\r\n] 2006.133.08:22:02.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:22:02.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.133.08:22:02.29#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.133.08:22:02.29#ibcon#ireg 7 cls_cnt 0 2006.133.08:22:02.29#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:22:02.41#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:22:02.41#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:22:02.43#ibcon#[27=USB\r\n] 2006.133.08:22:02.46#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:22:02.46#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.133.08:22:02.46#ibcon#about to clear, iclass 21 cls_cnt 0 2006.133.08:22:02.46#ibcon#cleared, iclass 21 cls_cnt 0 2006.133.08:22:02.47$vc4f8/vabw=wide 2006.133.08:22:02.47#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.133.08:22:02.47#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.133.08:22:02.47#ibcon#ireg 8 cls_cnt 0 2006.133.08:22:02.47#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:22:02.47#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:22:02.47#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:22:02.48#ibcon#[25=BW32\r\n] 2006.133.08:22:02.52#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:22:02.52#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.133.08:22:02.52#ibcon#about to clear, iclass 23 cls_cnt 0 2006.133.08:22:02.52#ibcon#cleared, iclass 23 cls_cnt 0 2006.133.08:22:02.52$vc4f8/vbbw=wide 2006.133.08:22:02.52#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.133.08:22:02.52#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.133.08:22:02.52#ibcon#ireg 8 cls_cnt 0 2006.133.08:22:02.52#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:22:02.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:22:02.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:22:02.59#ibcon#[27=BW32\r\n] 2006.133.08:22:02.62#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:22:02.62#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.133.08:22:02.62#ibcon#about to clear, iclass 25 cls_cnt 0 2006.133.08:22:02.62#ibcon#cleared, iclass 25 cls_cnt 0 2006.133.08:22:02.63$4f8m12a/ifd4f 2006.133.08:22:02.63$ifd4f/lo= 2006.133.08:22:02.63$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:22:02.63$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:22:02.63$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:22:02.63$ifd4f/patch= 2006.133.08:22:02.63$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:22:02.63$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:22:02.63$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:22:02.63$4f8m12a/"form=m,16.000,1:2 2006.133.08:22:02.63$4f8m12a/"tpicd 2006.133.08:22:02.63$4f8m12a/echo=off 2006.133.08:22:02.63$4f8m12a/xlog=off 2006.133.08:22:02.63:!2006.133.08:24:10 2006.133.08:22:23.13#trakl#Source acquired 2006.133.08:22:24.14#flagr#flagr/antenna,acquired 2006.133.08:24:10.01:preob 2006.133.08:24:11.14/onsource/TRACKING 2006.133.08:24:11.15:!2006.133.08:24:20 2006.133.08:24:20.01:data_valid=on 2006.133.08:24:20.02:midob 2006.133.08:24:21.14/onsource/TRACKING 2006.133.08:24:21.15/wx/11.30,1009.7,100 2006.133.08:24:21.32/cable/+6.5584E-03 2006.133.08:24:22.41/va/01,08,usb,yes,46,49 2006.133.08:24:22.41/va/02,07,usb,yes,47,49 2006.133.08:24:22.41/va/03,06,usb,yes,50,50 2006.133.08:24:22.41/va/04,07,usb,yes,48,51 2006.133.08:24:22.41/va/05,06,usb,yes,56,59 2006.133.08:24:22.41/va/06,05,usb,yes,57,57 2006.133.08:24:22.41/va/07,05,usb,yes,57,57 2006.133.08:24:22.41/va/08,06,usb,yes,53,52 2006.133.08:24:22.64/valo/01,532.99,yes,locked 2006.133.08:24:22.64/valo/02,572.99,yes,locked 2006.133.08:24:22.64/valo/03,672.99,yes,locked 2006.133.08:24:22.64/valo/04,832.99,yes,locked 2006.133.08:24:22.64/valo/05,652.99,yes,locked 2006.133.08:24:22.64/valo/06,772.99,yes,locked 2006.133.08:24:22.64/valo/07,832.99,yes,locked 2006.133.08:24:22.64/valo/08,852.99,yes,locked 2006.133.08:24:23.73/vb/01,04,usb,yes,33,31 2006.133.08:24:23.73/vb/02,04,usb,yes,35,36 2006.133.08:24:23.73/vb/03,04,usb,yes,31,35 2006.133.08:24:23.73/vb/04,04,usb,yes,32,32 2006.133.08:24:23.73/vb/05,04,usb,yes,30,35 2006.133.08:24:23.73/vb/06,04,usb,yes,32,35 2006.133.08:24:23.73/vb/07,04,usb,yes,34,34 2006.133.08:24:23.73/vb/08,04,usb,yes,31,35 2006.133.08:24:23.97/vblo/01,632.99,yes,locked 2006.133.08:24:23.97/vblo/02,640.99,yes,locked 2006.133.08:24:23.97/vblo/03,656.99,yes,locked 2006.133.08:24:23.97/vblo/04,712.99,yes,locked 2006.133.08:24:23.97/vblo/05,744.99,yes,locked 2006.133.08:24:23.97/vblo/06,752.99,yes,locked 2006.133.08:24:23.97/vblo/07,734.99,yes,locked 2006.133.08:24:23.97/vblo/08,744.99,yes,locked 2006.133.08:24:24.12/vabw/8 2006.133.08:24:24.27/vbbw/8 2006.133.08:24:24.36/xfe/off,on,14.7 2006.133.08:24:24.75/ifatt/23,28,28,28 2006.133.08:24:25.07/fmout-gps/S +1.92E-07 2006.133.08:24:25.12:!2006.133.08:25:20 2006.133.08:25:20.01:data_valid=off 2006.133.08:25:20.02:postob 2006.133.08:25:20.10/cable/+6.5564E-03 2006.133.08:25:20.10/wx/11.31,1009.7,100 2006.133.08:25:21.07/fmout-gps/S +1.93E-07 2006.133.08:25:21.08:scan_name=133-0826,k06133,60 2006.133.08:25:21.08:source=1357+769,135755.37,764321.1,2000.0,cw 2006.133.08:25:22.14#flagr#flagr/antenna,new-source 2006.133.08:25:22.15:checkk5 2006.133.08:25:22.53/chk_autoobs//k5ts1/ autoobs is running! 2006.133.08:25:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.133.08:25:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.133.08:25:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.133.08:25:24.00/chk_obsdata//k5ts1/T1330824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:25:24.37/chk_obsdata//k5ts2/T1330824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:25:24.73/chk_obsdata//k5ts3/T1330824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:25:25.11/chk_obsdata//k5ts4/T1330824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.133.08:25:25.79/k5log//k5ts1_log_newline 2006.133.08:25:26.48/k5log//k5ts2_log_newline 2006.133.08:25:27.16/k5log//k5ts3_log_newline 2006.133.08:25:27.84/k5log//k5ts4_log_newline 2006.133.08:25:27.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:25:27.87:4f8m12a=3 2006.133.08:25:27.87$4f8m12a/echo=on 2006.133.08:25:27.87$4f8m12a/pcalon 2006.133.08:25:27.87$pcalon/"no phase cal control is implemented here 2006.133.08:25:27.87$4f8m12a/"tpicd=stop 2006.133.08:25:27.87$4f8m12a/vc4f8 2006.133.08:25:27.87$vc4f8/valo=1,532.99 2006.133.08:25:27.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.133.08:25:27.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.133.08:25:27.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:27.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:25:27.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:25:27.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:25:27.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.133.08:25:27.92#abcon#{5=INTERFACE CLEAR} 2006.133.08:25:27.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:25:27.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.133.08:25:27.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.133.08:25:27.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.133.08:25:27.93$vc4f8/va=1,8 2006.133.08:25:27.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.133.08:25:27.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.133.08:25:27.93#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:27.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:25:27.93#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:25:27.93#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:25:27.95#ibcon#[25=AT01-08\r\n] 2006.133.08:25:27.99#abcon#[5=S1D000X0/0*\r\n] 2006.133.08:25:27.99#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:25:27.99#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.133.08:25:27.99#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.133.08:25:27.99#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:27.99#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:25:28.10#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:25:28.10#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:25:28.12#ibcon#[25=USB\r\n] 2006.133.08:25:28.17#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:25:28.17#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.133.08:25:28.17#ibcon#about to clear, iclass 3 cls_cnt 0 2006.133.08:25:28.17#ibcon#cleared, iclass 3 cls_cnt 0 2006.133.08:25:28.17$vc4f8/valo=2,572.99 2006.133.08:25:28.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:25:28.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:25:28.17#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:28.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:28.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:28.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:28.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.133.08:25:28.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:28.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:28.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:25:28.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:25:28.22$vc4f8/va=2,7 2006.133.08:25:28.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:25:28.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:25:28.22#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:28.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:28.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:28.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:28.31#ibcon#[25=AT02-07\r\n] 2006.133.08:25:28.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:28.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:28.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:25:28.34#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:28.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:28.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:28.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:28.48#ibcon#[25=USB\r\n] 2006.133.08:25:28.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:28.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:28.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:25:28.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:25:28.51$vc4f8/valo=3,672.99 2006.133.08:25:28.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:25:28.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:25:28.51#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:28.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:28.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:28.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:28.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.133.08:25:28.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:28.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:28.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:25:28.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:25:28.58$vc4f8/va=3,6 2006.133.08:25:28.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:25:28.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:25:28.58#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:28.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:28.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:28.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:28.65#ibcon#[25=AT03-06\r\n] 2006.133.08:25:28.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:28.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:28.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:25:28.68#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:28.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:28.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:28.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:28.82#ibcon#[25=USB\r\n] 2006.133.08:25:28.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:28.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:28.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:25:28.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:25:28.85$vc4f8/valo=4,832.99 2006.133.08:25:28.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:25:28.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:25:28.85#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:28.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:28.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:28.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:28.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.133.08:25:28.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:28.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:28.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:25:28.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:25:28.91$vc4f8/va=4,7 2006.133.08:25:28.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.08:25:28.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.08:25:28.91#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:28.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:28.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:28.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:28.99#ibcon#[25=AT04-07\r\n] 2006.133.08:25:29.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:29.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:29.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.08:25:29.02#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:29.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:29.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:29.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:29.16#ibcon#[25=USB\r\n] 2006.133.08:25:29.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:29.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:29.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:25:29.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:25:29.19$vc4f8/valo=5,652.99 2006.133.08:25:29.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:25:29.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:25:29.19#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:29.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:29.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:29.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:29.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.133.08:25:29.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:29.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:29.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:25:29.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:25:29.25$vc4f8/va=5,6 2006.133.08:25:29.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.08:25:29.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.08:25:29.25#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:29.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:29.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:29.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:29.33#ibcon#[25=AT05-06\r\n] 2006.133.08:25:29.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:29.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:29.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.08:25:29.36#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:29.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:29.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:29.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:29.50#ibcon#[25=USB\r\n] 2006.133.08:25:29.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:29.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:29.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:25:29.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:25:29.53$vc4f8/valo=6,772.99 2006.133.08:25:29.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.08:25:29.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.08:25:29.53#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:29.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:29.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:29.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:29.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.133.08:25:29.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:29.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:29.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:25:29.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:25:29.59$vc4f8/va=6,5 2006.133.08:25:29.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.133.08:25:29.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.133.08:25:29.59#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:29.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:29.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:29.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:29.67#ibcon#[25=AT06-05\r\n] 2006.133.08:25:29.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:29.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:29.70#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.133.08:25:29.70#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:29.70#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:25:29.82#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:25:29.82#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:25:29.84#ibcon#[25=USB\r\n] 2006.133.08:25:29.87#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:25:29.87#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.133.08:25:29.87#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:25:29.87#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:25:29.87$vc4f8/valo=7,832.99 2006.133.08:25:29.87#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.133.08:25:29.87#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.133.08:25:29.87#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:29.87#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:25:29.87#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:25:29.87#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:25:29.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.133.08:25:29.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:25:29.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.133.08:25:29.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.133.08:25:29.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.133.08:25:29.93$vc4f8/va=7,5 2006.133.08:25:29.93#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.133.08:25:29.93#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.133.08:25:29.93#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:29.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:25:29.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:25:29.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:25:30.01#ibcon#[25=AT07-05\r\n] 2006.133.08:25:30.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:25:30.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.133.08:25:30.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.133.08:25:30.04#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:30.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:25:30.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:25:30.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:25:30.18#ibcon#[25=USB\r\n] 2006.133.08:25:30.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:25:30.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.133.08:25:30.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.133.08:25:30.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.133.08:25:30.21$vc4f8/valo=8,852.99 2006.133.08:25:30.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.133.08:25:30.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.133.08:25:30.21#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:30.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:25:30.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:25:30.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:25:30.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.133.08:25:30.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:25:30.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.133.08:25:30.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.133.08:25:30.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.133.08:25:30.27$vc4f8/va=8,6 2006.133.08:25:30.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.133.08:25:30.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.133.08:25:30.27#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:30.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:25:30.33#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:25:30.33#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:25:30.35#ibcon#[25=AT08-06\r\n] 2006.133.08:25:30.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:25:30.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.133.08:25:30.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.133.08:25:30.38#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:30.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:25:30.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:25:30.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:25:30.52#ibcon#[25=USB\r\n] 2006.133.08:25:30.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:25:30.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.133.08:25:30.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.133.08:25:30.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.133.08:25:30.55$vc4f8/vblo=1,632.99 2006.133.08:25:30.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.133.08:25:30.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.133.08:25:30.55#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:30.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:25:30.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:25:30.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:25:30.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.133.08:25:30.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:25:30.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.133.08:25:30.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.133.08:25:30.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.133.08:25:30.61$vc4f8/vb=1,4 2006.133.08:25:30.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.133.08:25:30.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.133.08:25:30.61#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:30.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:25:30.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:25:30.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:25:30.63#ibcon#[27=AT01-04\r\n] 2006.133.08:25:30.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:25:30.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.133.08:25:30.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.133.08:25:30.66#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:30.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:25:30.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:25:30.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:25:30.80#ibcon#[27=USB\r\n] 2006.133.08:25:30.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:25:30.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.133.08:25:30.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.133.08:25:30.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.133.08:25:30.83$vc4f8/vblo=2,640.99 2006.133.08:25:30.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.133.08:25:30.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.133.08:25:30.83#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:30.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:25:30.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:25:30.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:25:30.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.133.08:25:30.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:25:30.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.133.08:25:30.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.133.08:25:30.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.133.08:25:30.89$vc4f8/vb=2,4 2006.133.08:25:30.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.133.08:25:30.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.133.08:25:30.89#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:30.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:25:30.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:25:30.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:25:30.97#ibcon#[27=AT02-04\r\n] 2006.133.08:25:31.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:25:31.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.133.08:25:31.00#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.133.08:25:31.00#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:31.00#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:25:31.12#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:25:31.12#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:25:31.14#ibcon#[27=USB\r\n] 2006.133.08:25:31.17#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:25:31.17#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.133.08:25:31.17#ibcon#about to clear, iclass 4 cls_cnt 0 2006.133.08:25:31.17#ibcon#cleared, iclass 4 cls_cnt 0 2006.133.08:25:31.17$vc4f8/vblo=3,656.99 2006.133.08:25:31.17#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.133.08:25:31.17#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.133.08:25:31.17#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:31.17#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:31.17#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:31.17#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:31.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.133.08:25:31.23#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:31.23#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.133.08:25:31.23#ibcon#about to clear, iclass 6 cls_cnt 0 2006.133.08:25:31.23#ibcon#cleared, iclass 6 cls_cnt 0 2006.133.08:25:31.23$vc4f8/vb=3,4 2006.133.08:25:31.23#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.133.08:25:31.23#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.133.08:25:31.23#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:31.23#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:31.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:31.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:31.31#ibcon#[27=AT03-04\r\n] 2006.133.08:25:31.34#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:31.34#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.133.08:25:31.34#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.133.08:25:31.34#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:31.34#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:31.46#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:31.46#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:31.48#ibcon#[27=USB\r\n] 2006.133.08:25:31.51#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:31.51#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.133.08:25:31.51#ibcon#about to clear, iclass 10 cls_cnt 0 2006.133.08:25:31.51#ibcon#cleared, iclass 10 cls_cnt 0 2006.133.08:25:31.51$vc4f8/vblo=4,712.99 2006.133.08:25:31.51#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.133.08:25:31.51#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.133.08:25:31.51#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:31.51#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:31.51#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:31.51#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:31.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.133.08:25:31.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:31.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.133.08:25:31.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.133.08:25:31.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.133.08:25:31.57$vc4f8/vb=4,4 2006.133.08:25:31.57#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.133.08:25:31.57#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.133.08:25:31.57#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:31.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:31.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:31.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:31.65#ibcon#[27=AT04-04\r\n] 2006.133.08:25:31.68#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:31.68#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.133.08:25:31.68#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.133.08:25:31.68#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:31.68#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:31.80#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:31.80#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:31.82#ibcon#[27=USB\r\n] 2006.133.08:25:31.85#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:31.85#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.133.08:25:31.85#ibcon#about to clear, iclass 14 cls_cnt 0 2006.133.08:25:31.85#ibcon#cleared, iclass 14 cls_cnt 0 2006.133.08:25:31.85$vc4f8/vblo=5,744.99 2006.133.08:25:31.85#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.133.08:25:31.85#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.133.08:25:31.85#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:31.85#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:31.85#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:31.85#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:31.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.133.08:25:31.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:31.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.133.08:25:31.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.133.08:25:31.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.133.08:25:31.91$vc4f8/vb=5,4 2006.133.08:25:31.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.133.08:25:31.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.133.08:25:31.91#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:31.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:31.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:31.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:31.99#ibcon#[27=AT05-04\r\n] 2006.133.08:25:32.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:32.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.133.08:25:32.02#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.133.08:25:32.02#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:32.02#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:32.14#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:32.14#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:32.16#ibcon#[27=USB\r\n] 2006.133.08:25:32.19#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:32.19#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.133.08:25:32.19#ibcon#about to clear, iclass 18 cls_cnt 0 2006.133.08:25:32.19#ibcon#cleared, iclass 18 cls_cnt 0 2006.133.08:25:32.19$vc4f8/vblo=6,752.99 2006.133.08:25:32.19#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.133.08:25:32.19#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.133.08:25:32.19#ibcon#ireg 17 cls_cnt 0 2006.133.08:25:32.19#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:32.19#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:32.19#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:32.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.133.08:25:32.25#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:32.25#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.133.08:25:32.25#ibcon#about to clear, iclass 20 cls_cnt 0 2006.133.08:25:32.25#ibcon#cleared, iclass 20 cls_cnt 0 2006.133.08:25:32.25$vc4f8/vb=6,4 2006.133.08:25:32.25#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.133.08:25:32.25#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.133.08:25:32.25#ibcon#ireg 11 cls_cnt 2 2006.133.08:25:32.25#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:32.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:32.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:32.33#ibcon#[27=AT06-04\r\n] 2006.133.08:25:32.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:32.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.133.08:25:32.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.133.08:25:32.36#ibcon#ireg 7 cls_cnt 0 2006.133.08:25:32.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:32.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:32.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:32.50#ibcon#[27=USB\r\n] 2006.133.08:25:32.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:32.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.133.08:25:32.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.133.08:25:32.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.133.08:25:32.53$vc4f8/vabw=wide 2006.133.08:25:32.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.133.08:25:32.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.133.08:25:32.53#ibcon#ireg 8 cls_cnt 0 2006.133.08:25:32.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:32.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:32.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:32.55#ibcon#[25=BW32\r\n] 2006.133.08:25:32.58#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:32.58#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.133.08:25:32.58#ibcon#about to clear, iclass 24 cls_cnt 0 2006.133.08:25:32.58#ibcon#cleared, iclass 24 cls_cnt 0 2006.133.08:25:32.58$vc4f8/vbbw=wide 2006.133.08:25:32.58#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.133.08:25:32.58#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.133.08:25:32.58#ibcon#ireg 8 cls_cnt 0 2006.133.08:25:32.58#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:25:32.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:25:32.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:25:32.67#ibcon#[27=BW32\r\n] 2006.133.08:25:32.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:25:32.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.133.08:25:32.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.133.08:25:32.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.133.08:25:32.70$4f8m12a/ifd4f 2006.133.08:25:32.70$ifd4f/lo= 2006.133.08:25:32.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.133.08:25:32.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.133.08:25:32.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.133.08:25:32.71$ifd4f/patch= 2006.133.08:25:32.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.133.08:25:32.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.133.08:25:32.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.133.08:25:32.71$4f8m12a/"form=m,16.000,1:2 2006.133.08:25:32.71$4f8m12a/"tpicd 2006.133.08:25:32.71$4f8m12a/echo=off 2006.133.08:25:32.71$4f8m12a/xlog=off 2006.133.08:25:32.71:!2006.133.08:26:00 2006.133.08:25:42.14#trakl#Source acquired 2006.133.08:25:42.14#flagr#flagr/antenna,acquired 2006.133.08:26:00.01:preob 2006.133.08:26:01.14/onsource/TRACKING 2006.133.08:26:01.14:!2006.133.08:26:10 2006.133.08:26:10.00:data_valid=on 2006.133.08:26:10.00:midob 2006.133.08:26:10.14/onsource/TRACKING 2006.133.08:26:10.14/wx/11.31,1009.7,100 2006.133.08:26:10.24/cable/+6.5579E-03 2006.133.08:26:11.33/va/01,08,usb,yes,42,44 2006.133.08:26:11.33/va/02,07,usb,yes,42,44 2006.133.08:26:11.33/va/03,06,usb,yes,44,45 2006.133.08:26:11.33/va/04,07,usb,yes,43,46 2006.133.08:26:11.33/va/05,06,usb,yes,50,53 2006.133.08:26:11.33/va/06,05,usb,yes,51,50 2006.133.08:26:11.33/va/07,05,usb,yes,51,50 2006.133.08:26:11.33/va/08,06,usb,yes,47,46 2006.133.08:26:11.56/valo/01,532.99,yes,locked 2006.133.08:26:11.56/valo/02,572.99,yes,locked 2006.133.08:26:11.56/valo/03,672.99,yes,locked 2006.133.08:26:11.56/valo/04,832.99,yes,locked 2006.133.08:26:11.56/valo/05,652.99,yes,locked 2006.133.08:26:11.56/valo/06,772.99,yes,locked 2006.133.08:26:11.56/valo/07,832.99,yes,locked 2006.133.08:26:11.56/valo/08,852.99,yes,locked 2006.133.08:26:12.65/vb/01,04,usb,yes,29,28 2006.133.08:26:12.65/vb/02,04,usb,yes,31,33 2006.133.08:26:12.65/vb/03,04,usb,yes,28,31 2006.133.08:26:12.65/vb/04,04,usb,yes,29,29 2006.133.08:26:12.65/vb/05,04,usb,yes,27,31 2006.133.08:26:12.65/vb/06,04,usb,yes,28,31 2006.133.08:26:12.65/vb/07,04,usb,yes,30,30 2006.133.08:26:12.65/vb/08,04,usb,yes,28,31 2006.133.08:26:12.88/vblo/01,632.99,yes,locked 2006.133.08:26:12.88/vblo/02,640.99,yes,locked 2006.133.08:26:12.88/vblo/03,656.99,yes,locked 2006.133.08:26:12.88/vblo/04,712.99,yes,locked 2006.133.08:26:12.88/vblo/05,744.99,yes,locked 2006.133.08:26:12.88/vblo/06,752.99,yes,locked 2006.133.08:26:12.88/vblo/07,734.99,yes,locked 2006.133.08:26:12.88/vblo/08,744.99,yes,locked 2006.133.08:26:13.03/vabw/8 2006.133.08:26:13.18/vbbw/8 2006.133.08:26:13.27/xfe/off,on,15.2 2006.133.08:26:13.65/ifatt/23,28,28,28 2006.133.08:26:14.07/fmout-gps/S +1.93E-07 2006.133.08:26:14.12:!2006.133.08:27:10 2006.133.08:27:10.00:data_valid=off 2006.133.08:27:10.01:postob 2006.133.08:27:10.17/cable/+6.5575E-03 2006.133.08:27:10.18/wx/11.31,1009.7,100 2006.133.08:27:11.08/fmout-gps/S +1.94E-07 2006.133.08:27:11.09:checkk5last 2006.133.08:27:11.09&checkk5last/chk_obsdata=1 2006.133.08:27:11.09&checkk5last/chk_obsdata=2 2006.133.08:27:11.10&checkk5last/chk_obsdata=3 2006.133.08:27:11.10&checkk5last/chk_obsdata=4 2006.133.08:27:11.10&checkk5last/k5log=1 2006.133.08:27:11.11&checkk5last/k5log=2 2006.133.08:27:11.11&checkk5last/k5log=3 2006.133.08:27:11.11&checkk5last/k5log=4 2006.133.08:27:11.12&checkk5last/obsinfo 2006.133.08:27:11.49/chk_obsdata//k5ts1/T1330826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:27:11.85/chk_obsdata//k5ts2/T1330826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:27:12.22/chk_obsdata//k5ts3/T1330826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:27:12.58/chk_obsdata//k5ts4/T1330826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.133.08:27:13.27/k5log//k5ts1_log_newline 2006.133.08:27:13.96/k5log//k5ts2_log_newline 2006.133.08:27:14.64/k5log//k5ts3_log_newline 2006.133.08:27:15.32/k5log//k5ts4_log_newline 2006.133.08:27:15.35/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.133.08:27:15.35:"sched_end 2006.133.08:27:15.35:source=idle 2006.133.08:27:16.14:stow 2006.133.08:27:16.14&stow/source=idle 2006.133.08:27:16.14&stow/"this is stow command. 2006.133.08:27:16.14&stow/antenna=m3 2006.133.08:27:16.14#flagr#flagr/antenna,new-source 2006.133.08:27:19.01:!+10m 2006.133.08:37:19.02:standby 2006.133.08:37:19.02&standby/"this is standby command. 2006.133.08:37:19.02&standby/antenna=m0 2006.133.08:37:20.01:sy=cp /usr2/log/k06133ts.log /usr2/log_backup/ 2006.133.08:37:20.05:log=k06134ts